repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
boztalay/OZ-3 | FPGA/OZ-3/GenReg.vhd | 2 | 1482 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:58:50 10/27/2009
-- Design Name:
-- Module Name: GenReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.90 - File written and syntax checked. No simulation necessary
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GenReg is
generic (size : integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end GenReg;
architecture Behavioral of GenReg is
begin
main: process (clock, reset) is
variable data_reg : STD_LOGIC_VECTOR((size - 1) downto 0);
begin
if rising_edge(clock) then
if reset = '1' then
data_reg := (others => '0');
elsif enable = '1' then
data_reg := data;
end if;
end if;
output <= data_reg;
end process;
end Behavioral;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_cordic_m1.vhd | 10 | 13050 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_mul23x56.vhd | 10 | 6888 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_inv_core.vhd | 10 | 6144 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - CORE ***
--*** ***
--*** FP_INV_CORE.VHD ***
--*** ***
--*** Function: 36 bit Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 12 ***
--***************************************************
ENTITY fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_inv_core;
ARCHITECTURE rtl OF fp_inv_core IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal divisordel : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal invdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal delinvdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal scaleden : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal twonode : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal nextguessff : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal quotientnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
component fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
invcore: fp_div_est
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>divisor(36 DOWNTO 18),invdivisor=>invdivisor);
delinone: fp_del
GENERIC MAP (width=>36,pipes=>5)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>divisor,cc=>divisordel);
--**********************************
--*** ITERATION 0 - SCALE INPUTS ***
--**********************************
-- in level 5, out level 8
mulscaleone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>36,
pipes=>3,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>divisordel,databb=>invdivisor,
result=>scaleden);
--********************
--*** ITERATION 1 ***
--********************
twonode <= '1' & zerovec(36 DOWNTO 1);
pita: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 37 LOOP
nextguessff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
nextguessff <= twonode - ('0' & scaleden); -- level 9
END IF;
END IF;
END PROCESS;
deloneone: fp_del
GENERIC MAP (width=>18,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invdivisor,
cc=>delinvdivisor);
-- in level 9, out level 12
muloneone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>36,
pipes=>3,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>nextguessff(36 DOWNTO 1),databb=>delinvdivisor,
result=>quotientnode);
quotient <= quotientnode(36 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/hcc_rsftpipe36.vhd | 10 | 4753 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE36.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_rsftpipe36;
ARCHITECTURE rtl OF hcc_rsftpipe36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND ((shift(2)) OR shift(1)));
levone(36) <= levzip(36);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(36) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(36) AND shift(4));
END GENERATE;
gbd: FOR k IN 33 TO 35 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(36) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(36) <= levone(36);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 36 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(36) AND shiftff(2));
END GENERATE;
gcc: FOR k IN 21 TO 35 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(36) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(36) <= levtwoff(36);
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_sum36x18.vhd | 10 | 18695 | -- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fp_sum36x18 IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END fp_sum36x18;
ARCHITECTURE SYN OF fp_sum36x18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
accumulator : STRING;
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
chainout_adder : STRING;
chainout_register : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_a1 : STRING;
input_aclr_b0 : STRING;
input_aclr_b1 : STRING;
input_register_a0 : STRING;
input_register_a1 : STRING;
input_register_b0 : STRING;
input_register_b1 : STRING;
input_source_a0 : STRING;
input_source_a1 : STRING;
input_source_b0 : STRING;
input_source_b1 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_aclr1 : STRING;
multiplier_register0 : STRING;
multiplier_register1 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_chainin : NATURAL;
width_result : NATURAL;
zero_chainout_output_aclr : STRING;
zero_chainout_output_register : STRING;
zero_loopback_aclr : STRING;
zero_loopback_output_aclr : STRING;
zero_loopback_output_register : STRING;
zero_loopback_pipeline_aclr : STRING;
zero_loopback_pipeline_register : STRING;
zero_loopback_register : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6 <= datab_1(35 DOWNTO 0);
sub_wire3 <= dataa_1(17 DOWNTO 0);
result <= sub_wire0(54 DOWNTO 0);
sub_wire1 <= dataa_0(17 DOWNTO 0);
sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0);
sub_wire4 <= datab_0(35 DOWNTO 0);
sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0);
ALTMULT_ADD_component : ALTMULT_ADD
GENERIC MAP (
accumulator => "NO",
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
chainout_adder => "NO",
chainout_register => "UNREGISTERED",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_a1 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_aclr_b1 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_a1 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_register_b1 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_a1 => "DATAA",
input_source_b0 => "DATAB",
input_source_b1 => "DATAB",
intended_device_family => "Stratix III",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_aclr1 => "ACLR3",
multiplier_register0 => "CLOCK0",
multiplier_register1 => "CLOCK0",
number_of_multipliers => 2,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 36,
width_chainin => 1,
width_result => 55,
zero_chainout_output_aclr => "ACLR3",
zero_chainout_output_register => "CLOCK0",
zero_loopback_aclr => "ACLR3",
zero_loopback_output_aclr => "ACLR3",
zero_loopback_output_register => "CLOCK0",
zero_loopback_pipeline_aclr => "ACLR3",
zero_loopback_pipeline_register => "CLOCK0",
zero_loopback_register => "CLOCK0"
)
PORT MAP (
dataa => sub_wire2,
datab => sub_wire5,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
-- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1"
-- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: NUM_MULT STRING "2"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: RNFORMAT STRING "55"
-- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_REG STRING "1"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "55"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
-- Retrieval info: PRIVATE: SIGNA STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "18"
-- Retrieval info: PRIVATE: WIDTHB STRING "36"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
-- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
-- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
-- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]"
-- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]"
-- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
-- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]"
-- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0
-- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0
-- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
-- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
-- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/dp_exp.vhd | 10 | 10773 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION EXPONENT(e) - TOP LEVEL ***
--*** ***
--*** DP_EXP.VHD ***
--*** ***
--*** Function: IEEE754 DP EXP() ***
--*** ***
--*** 12/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Stratix II ***
--*** Latency = 20 + 2*DoubleSpeed + ***
--*** Roundconvert*(1+DoubleSpeed) ***
--*** DoubleSpeed = 0, Roundconvert = 0 : 20 ***
--*** DoubleSpeed = 1, Roundconvert = 0 : 22 ***
--*** DoubleSpeed = 0, Roundconvert = 1 : 21 ***
--*** DoubleSpeed = 1, Roundconvert = 1 : 24 ***
--*** ***
--*** Stratix III ***
--*** Latency = 18 + ***
--*** Roundconvert*(1+DoubleSpeed) ***
--*** DoubleSpeed = 0, Roundconvert = 0 : 18 ***
--*** DoubleSpeed = 1, Roundconvert = 0 : 18 ***
--*** DoubleSpeed = 0, Roundconvert = 1 : 19 ***
--*** DoubleSpeed = 1, Roundconvert = 1 : 20 ***
--*** ***
--***************************************************
ENTITY dp_exp IS
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END dp_exp;
ARCHITECTURE rtl OF dp_exp IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
constant coredepth : positive := 19 + 2*doublespeed - device*(4 + 2*doublespeed);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal rangeerror : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
--*** SII Latency = 19 + 2*doublespeed ***
--*** SIII/IV Latency = 14 ***
component dp_exp_core
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aasgn : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (54 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
rangeerror : OUT STD_LOGIC
);
end component;
component dp_expnornd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
component dp_exprnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
component dp_exprndpipe
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--****************
--*** EXP CORE ***
--****************
expcore: dp_exp_core
GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aasgn=>signin,aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,
rangeerror=>rangeerror);
--************************
--*** ROUND AND OUTPUT ***
--************************
gra: IF (roundconvert = 0) GENERATE
norndout: dp_expnornd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentexp=>exponentnode,
mantissaexp=>mantissanode(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
rangeerror=>rangeerror,
exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,underflowout=>underflowout);
END GENERATE;
grb: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
rndout: dp_exprnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentexp=>exponentnode,
mantissaexp=>mantissanode(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
rangeerror=>rangeerror,
exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,underflowout=>underflowout);
END GENERATE;
grc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
rndoutpipe: dp_exprndpipe
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentexp=>exponentnode,
mantissaexp=>mantissanode(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
rangeerror=>rangeerror,
exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,underflowout=>underflowout);
END GENERATE;
signout <= '0';
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_sinpi_s5.vhd | 10 | 314232 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/hcc_castltox.vhd | 10 | 3526 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOX.VHD ***
--*** ***
--*** Function: Cast Long to Internal Single ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltox IS
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castltox;
ARCHITECTURE rtl OF hcc_castltox IS
signal fit : STD_LOGIC;
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
cc(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
cc(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
cc(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
cc(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
ccsat <= '0';
cczip <= '0';
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_arccos_s5.vhd | 10 | 566550 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccos_s5
-- VHDL created on Thu Feb 28 17:20:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid15_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal cstBiasM2_uid16_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid17_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid45_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid48_fpArccosXTest_q : std_logic_vector (12 downto 0);
signal pi_uid85_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal pi2_uid102_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid118_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid353_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (10 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_a : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_pr : UNSIGNED (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : signal is true;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid18_uid54_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid102_uid103_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid114_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid128_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid24_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid26_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid36_fpArccosXTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid36_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid36_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid37_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid43_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid43_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid43_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal oMy_uid54_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal oMy_uid54_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expL_uid58_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expL_uid58_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid86_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid103_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid103_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid125_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid125_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid129_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid399_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal piF_uid119_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal piF_uid119_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid122_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid122_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal concExc_uid398_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal R_uid411_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid42_uid42_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_b : std_logic_vector (5 downto 0);
signal l_uid56_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal l_uid56_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid60_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid60_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid68_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid68_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal normBit_uid105_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal normBit_uid105_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal sR_uid132_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (18 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (32 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid49_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid31_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid47_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid47_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (2 downto 0);
signal fpL_uid61_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid94_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid107_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid110_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal cStage_uid179_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid186_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid200_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid80_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid32_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid32_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal cStage_uid172_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid96_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid96_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal s1_uid301_uid304_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid307_uid310_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid445_uid448_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid451_uid454_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid35_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid116_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid116_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal inputIsMax_uid51_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid51_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal y_uid52_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal y_uid52_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid71_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid71_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal lrs_uid369_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (28 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid127_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal firstPath_uid53_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid53_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid98_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid98_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal cStage_uid193_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid207_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid117_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal yT1_uid443_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid443_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid209_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid76_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal join_uid255_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (25 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid65_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid9_fpArccosXTest(CONSTANT,8)
cstAllOWE_uid9_fpArccosXTest_q <= "11111111";
--cstBiasP1_uid17_fpArccosXTest(CONSTANT,16)
cstBiasP1_uid17_fpArccosXTest_q <= "10000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable(LOGICAL,1194)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q <= not ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor(LOGICAL,1222)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q <= not (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a or ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top(CONSTANT,1218)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q <= "011001";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp(LOGICAL,1219)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q <= "1" when ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a = ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b else "0";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg(REG,1220)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena(REG,1223)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd(LOGICAL,1224)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a and ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest(CONSTANT,161)
rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q <= "000";
--RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest(BITSELECT,160)@1
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in(36 downto 3);
--rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest(BITJOIN,162)@1
rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest(CONSTANT,158)
rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q <= "00";
--RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest(BITSELECT,157)@1
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in(36 downto 2);
--rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest(BITJOIN,159)@1
rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b;
--RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest(BITSELECT,154)@1
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in(36 downto 1);
--rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest(BITJOIN,156)@1
rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q <= GND_q & RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest(CONSTANT,150)
rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q <= "000000000000";
--rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest(CONSTANT,140)
rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest(CONSTANT,138)
rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q <= "00000000000000000000000000000000";
--X36dto32_uid138_fxpX_uid50_fpArccosXTest(BITSELECT,137)@0
X36dto32_uid138_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto32_uid138_fxpX_uid50_fpArccosXTest_b <= X36dto32_uid138_fxpX_uid50_fpArccosXTest_in(36 downto 32);
--rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest(BITJOIN,139)@0
rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q & X36dto32_uid138_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest(CONSTANT,135)
rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q <= "0000000000000000";
--X36dto16_uid135_fxpX_uid50_fpArccosXTest(BITSELECT,134)@0
X36dto16_uid135_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto16_uid135_fxpX_uid50_fpArccosXTest_b <= X36dto16_uid135_fxpX_uid50_fpArccosXTest_in(36 downto 16);
--rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest(BITJOIN,136)@0
rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X36dto16_uid135_fxpX_uid50_fpArccosXTest_b;
--fracX_uid7_fpArccosXTest(BITSELECT,6)@0
fracX_uid7_fpArccosXTest_in <= a(22 downto 0);
fracX_uid7_fpArccosXTest_b <= fracX_uid7_fpArccosXTest_in(22 downto 0);
--oFracX_uid42_uid42_fpArccosXTest(BITJOIN,41)@0
oFracX_uid42_uid42_fpArccosXTest_q <= VCC_q & fracX_uid7_fpArccosXTest_b;
--cst01pWShift_uid48_fpArccosXTest(CONSTANT,47)
cst01pWShift_uid48_fpArccosXTest_q <= "0000000000000";
--oFracXExt_uid49_fpArccosXTest(BITJOIN,48)@0
oFracXExt_uid49_fpArccosXTest_q <= oFracX_uid42_uid42_fpArccosXTest_q & cst01pWShift_uid48_fpArccosXTest_q;
--shiftOutVal_uid45_fpArccosXTest(CONSTANT,44)
shiftOutVal_uid45_fpArccosXTest_q <= "100100";
--expX_uid6_fpArccosXTest(BITSELECT,5)@0
expX_uid6_fpArccosXTest_in <= a(30 downto 0);
expX_uid6_fpArccosXTest_b <= expX_uid6_fpArccosXTest_in(30 downto 23);
--cstBias_uid13_fpArccosXTest(CONSTANT,12)
cstBias_uid13_fpArccosXTest_q <= "01111111";
--shiftValuePre_uid44_fpArccosXTest(SUB,43)@0
shiftValuePre_uid44_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
shiftValuePre_uid44_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArccosXTest_b);
shiftValuePre_uid44_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid44_fpArccosXTest_a) - UNSIGNED(shiftValuePre_uid44_fpArccosXTest_b));
shiftValuePre_uid44_fpArccosXTest_q <= shiftValuePre_uid44_fpArccosXTest_o(8 downto 0);
--fxpShifterBits_uid46_fpArccosXTest(BITSELECT,45)@0
fxpShifterBits_uid46_fpArccosXTest_in <= shiftValuePre_uid44_fpArccosXTest_q(5 downto 0);
fxpShifterBits_uid46_fpArccosXTest_b <= fxpShifterBits_uid46_fpArccosXTest_in(5 downto 0);
--cstBiasMwFMwShift_uid15_fpArccosXTest(CONSTANT,14)
cstBiasMwFMwShift_uid15_fpArccosXTest_q <= "001011100";
--shiftValue_uid43_fpArccosXTest(COMPARE,42)@0
shiftValue_uid43_fpArccosXTest_cin <= GND_q;
shiftValue_uid43_fpArccosXTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid15_fpArccosXTest_q(8)) & cstBiasMwFMwShift_uid15_fpArccosXTest_q) & '0';
shiftValue_uid43_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid6_fpArccosXTest_b) & shiftValue_uid43_fpArccosXTest_cin(0);
shiftValue_uid43_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid43_fpArccosXTest_a) - SIGNED(shiftValue_uid43_fpArccosXTest_b));
shiftValue_uid43_fpArccosXTest_n(0) <= not shiftValue_uid43_fpArccosXTest_o(11);
--shiftValue_uid47_fpArccosXTest(MUX,46)@0
shiftValue_uid47_fpArccosXTest_s <= shiftValue_uid43_fpArccosXTest_n;
shiftValue_uid47_fpArccosXTest: PROCESS (shiftValue_uid47_fpArccosXTest_s, en, fxpShifterBits_uid46_fpArccosXTest_b, shiftOutVal_uid45_fpArccosXTest_q)
BEGIN
CASE shiftValue_uid47_fpArccosXTest_s IS
WHEN "0" => shiftValue_uid47_fpArccosXTest_q <= fxpShifterBits_uid46_fpArccosXTest_b;
WHEN "1" => shiftValue_uid47_fpArccosXTest_q <= shiftOutVal_uid45_fpArccosXTest_q;
WHEN OTHERS => shiftValue_uid47_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest(BITSELECT,141)@0
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q;
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in(5 downto 4);
--rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest(MUX,142)@0
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b;
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s, en, oFracXExt_uid49_fpArccosXTest_q, rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= oFracXExt_uid49_fpArccosXTest_q;
WHEN "01" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest(BITSELECT,149)@0
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in(36 downto 12);
--rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest(BITJOIN,151)@0
rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5(REG,503)@0
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest(BITSELECT,146)@0
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in(36 downto 8);
--rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest(BITJOIN,148)@0
rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4(REG,502)@0
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest(CONSTANT,144)
rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q <= "0000";
--RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest(BITSELECT,143)@0
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in(36 downto 4);
--rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest(BITJOIN,145)@0
rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3(REG,501)@0
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2(REG,500)@0
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest(BITSELECT,152)@0
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1(REG,499)@0
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest(MUX,153)@1
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s, en, reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest(BITSELECT,163)@0
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1(REG,504)@0
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest(MUX,164)@1
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s, en, rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
WHEN "01" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid52_fpArccosXTest(BITSELECT,51)@1
y_uid52_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q(35 downto 0);
y_uid52_fpArccosXTest_b <= y_uid52_fpArccosXTest_in(35 downto 1);
--mAddr_uid98_fpArccosXTest(BITSELECT,97)@1
mAddr_uid98_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
mAddr_uid98_fpArccosXTest_b <= mAddr_uid98_fpArccosXTest_in(34 downto 27);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0(REG,578)@1
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= mAddr_uid98_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid442_arccosXO2TabGen_lutmem(DUALMEM,494)@2
memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid442_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid442_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid442_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid442_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid442_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid442_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid442_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid442_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid442_arccosXO2TabGen_lutmem_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1(REG,580)@4
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid99_fpArccosXTest(BITSELECT,98)@1
mPPolyEval_uid99_fpArccosXTest_in <= y_uid52_fpArccosXTest_b(26 downto 0);
mPPolyEval_uid99_fpArccosXTest_b <= mPPolyEval_uid99_fpArccosXTest_in(26 downto 12);
--yT1_uid443_arccosXO2PolyEval(BITSELECT,442)@1
yT1_uid443_arccosXO2PolyEval_in <= mPPolyEval_uid99_fpArccosXTest_b;
yT1_uid443_arccosXO2PolyEval_b <= yT1_uid443_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg(DELAY,1328)
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid443_arccosXO2PolyEval_b, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a(DELAY,1172)@1
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0(REG,579)@4
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid478_pT1_uid444_arccosXO2PolyEval(MULT,477)@5
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b);
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval(BITSELECT,478)@8
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q;
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid446_arccosXO2PolyEval(BITSELECT,445)@8
highBBits_uid446_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b;
highBBits_uid446_arccosXO2PolyEval_b <= highBBits_uid446_arccosXO2PolyEval_in(12 downto 1);
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a(DELAY,1086)@2
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1289)
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid441_arccosXO2TabGen_lutmem(DUALMEM,493)@6
memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid441_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC1_uid441_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid441_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid441_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid441_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid441_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid441_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid441_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid441_arccosXO2TabGen_lutmem_q <= memoryC1_uid441_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid447_arccosXO2PolyEval(ADD,446)@8
sumAHighB_uid447_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid441_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid441_arccosXO2TabGen_lutmem_q);
sumAHighB_uid447_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid446_arccosXO2PolyEval_b(11)) & highBBits_uid446_arccosXO2PolyEval_b);
sumAHighB_uid447_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid447_arccosXO2PolyEval_b));
sumAHighB_uid447_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid445_arccosXO2PolyEval(BITSELECT,444)@8
lowRangeB_uid445_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid445_arccosXO2PolyEval_b <= lowRangeB_uid445_arccosXO2PolyEval_in(0 downto 0);
--s1_uid445_uid448_arccosXO2PolyEval(BITJOIN,447)@8
s1_uid445_uid448_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_q & lowRangeB_uid445_arccosXO2PolyEval_b;
--reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1(REG,583)@8
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= s1_uid445_uid448_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor(LOGICAL,1339)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q <= not (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a or ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b);
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top(CONSTANT,1335)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q <= "0100";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp(LOGICAL,1336)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q <= "1" when ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a = ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b else "0";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg(REG,1337)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena(REG,1340)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd(LOGICAL,1341)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a and ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg(DELAY,1329)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => mPPolyEval_uid99_fpArccosXTest_b, xout => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt(COUNTER,1331)
-- every=1, low=0, high=4, step=1, init=1
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i = 3 THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i - 4;
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i,3));
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg(REG,1332)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux(MUX,1333)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux: PROCESS (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem(DUALMEM,1330)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq,
address_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa,
data_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia
);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0(REG,582)@8
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid481_pT2_uid450_arccosXO2PolyEval(MULT,480)@9
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b);
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval(BITSELECT,481)@12
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q;
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid452_arccosXO2PolyEval(BITSELECT,451)@12
highBBits_uid452_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b;
highBBits_uid452_arccosXO2PolyEval_b <= highBBits_uid452_arccosXO2PolyEval_in(24 downto 2);
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor(LOGICAL,1352)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a or ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,1296)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q <= "0101";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,1297)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg(REG,1298)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena(REG,1353)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd(LOGICAL,1354)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1342)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid98_fpArccosXTest_b, xout => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,1292)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,1293)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,1294)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem(DUALMEM,1343)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0(REG,584)@9
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid440_arccosXO2TabGen_lutmem(DUALMEM,492)@10
memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid440_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q;
memoryC0_uid440_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid440_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid440_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid440_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid440_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid440_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid440_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid440_arccosXO2TabGen_lutmem_q <= memoryC0_uid440_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid453_arccosXO2PolyEval(ADD,452)@12
sumAHighB_uid453_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid440_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid440_arccosXO2TabGen_lutmem_q);
sumAHighB_uid453_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid452_arccosXO2PolyEval_b(22)) & highBBits_uid452_arccosXO2PolyEval_b);
sumAHighB_uid453_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid453_arccosXO2PolyEval_b));
sumAHighB_uid453_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid451_arccosXO2PolyEval(BITSELECT,450)@12
lowRangeB_uid451_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid451_arccosXO2PolyEval_b <= lowRangeB_uid451_arccosXO2PolyEval_in(1 downto 0);
--s2_uid451_uid454_arccosXO2PolyEval(BITJOIN,453)@12
s2_uid451_uid454_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_q & lowRangeB_uid451_arccosXO2PolyEval_b;
--fxpArccosX_uid101_fpArccosXTest(BITSELECT,100)@12
fxpArccosX_uid101_fpArccosXTest_in <= s2_uid451_uid454_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid101_fpArccosXTest_b <= fxpArccosX_uid101_fpArccosXTest_in(30 downto 4);
--reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1(REG,586)@12
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= fxpArccosX_uid101_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid102_fpArccosXTest(CONSTANT,101)
pi2_uid102_fpArccosXTest_q <= "110010010000111111011010101";
--pad_pi2_uid102_uid103_fpArccosXTest(BITJOIN,102)@12
pad_pi2_uid102_uid103_fpArccosXTest_q <= pi2_uid102_fpArccosXTest_q & GND_q;
--reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0(REG,585)@12
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= pad_pi2_uid102_uid103_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid103_fpArccosXTest(SUB,103)@13
path2Diff_uid103_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q);
path2Diff_uid103_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q);
path2Diff_uid103_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid103_fpArccosXTest_a) - UNSIGNED(path2Diff_uid103_fpArccosXTest_b));
path2Diff_uid103_fpArccosXTest_q <= path2Diff_uid103_fpArccosXTest_o(28 downto 0);
--path2NegCaseFPFrac_uid106_fpArccosXTest(BITSELECT,105)@13
path2NegCaseFPFrac_uid106_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(26 downto 0);
path2NegCaseFPFrac_uid106_fpArccosXTest_b <= path2NegCaseFPFrac_uid106_fpArccosXTest_in(26 downto 4);
--path2NegCaseFPL_uid107_fpArccosXTest(BITJOIN,106)@13
path2NegCaseFPL_uid107_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & path2NegCaseFPFrac_uid106_fpArccosXTest_b;
--path2NegCaseFPFrac_uid109_fpArccosXTest(BITSELECT,108)@13
path2NegCaseFPFrac_uid109_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(25 downto 0);
path2NegCaseFPFrac_uid109_fpArccosXTest_b <= path2NegCaseFPFrac_uid109_fpArccosXTest_in(25 downto 3);
--path2NegCaseFPS_uid110_fpArccosXTest(BITJOIN,109)@13
path2NegCaseFPS_uid110_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & path2NegCaseFPFrac_uid109_fpArccosXTest_b;
--normBit_uid105_fpArccosXTest(BITSELECT,104)@13
normBit_uid105_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(27 downto 0);
normBit_uid105_fpArccosXTest_b <= normBit_uid105_fpArccosXTest_in(27 downto 27);
--path2NegCaseFP_uid112_fpArccosXTest(MUX,111)@13
path2NegCaseFP_uid112_fpArccosXTest_s <= normBit_uid105_fpArccosXTest_b;
path2NegCaseFP_uid112_fpArccosXTest: PROCESS (path2NegCaseFP_uid112_fpArccosXTest_s, en, path2NegCaseFPS_uid110_fpArccosXTest_q, path2NegCaseFPL_uid107_fpArccosXTest_q)
BEGIN
CASE path2NegCaseFP_uid112_fpArccosXTest_s IS
WHEN "0" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPS_uid110_fpArccosXTest_q;
WHEN "1" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPL_uid107_fpArccosXTest_q;
WHEN OTHERS => path2NegCaseFP_uid112_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid113_fpArccosXTest(BITSELECT,112)@12
path2PosCaseFPFraction_uid113_fpArccosXTest_in <= fxpArccosX_uid101_fpArccosXTest_b(25 downto 0);
path2PosCaseFPFraction_uid113_fpArccosXTest_b <= path2PosCaseFPFraction_uid113_fpArccosXTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a(DELAY,680)@12
ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid113_fpArccosXTest_b, xout => ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid114_fpArccosXTest(BITJOIN,113)@13
path2PosCaseFP_uid114_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q;
--singX_uid8_fpArccosXTest(BITSELECT,7)@0
singX_uid8_fpArccosXTest_in <= a;
singX_uid8_fpArccosXTest_b <= singX_uid8_fpArccosXTest_in(31 downto 31);
--ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b(DELAY,681)@0
ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid116_fpArccosXTest(MUX,115)@13
path2ResFP_uid116_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q;
path2ResFP_uid116_fpArccosXTest: PROCESS (path2ResFP_uid116_fpArccosXTest_s, en, path2PosCaseFP_uid114_fpArccosXTest_q, path2NegCaseFP_uid112_fpArccosXTest_q)
BEGIN
CASE path2ResFP_uid116_fpArccosXTest_s IS
WHEN "0" => path2ResFP_uid116_fpArccosXTest_q <= path2PosCaseFP_uid114_fpArccosXTest_q;
WHEN "1" => path2ResFP_uid116_fpArccosXTest_q <= path2NegCaseFP_uid112_fpArccosXTest_q;
WHEN OTHERS => path2ResFP_uid116_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid123_fpArccosXTest(BITSELECT,122)@13
Path2ResFP30dto23_uid123_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(30 downto 0);
Path2ResFP30dto23_uid123_fpArccosXTest_b <= Path2ResFP30dto23_uid123_fpArccosXTest_in(30 downto 23);
--reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3(REG,590)@13
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= Path2ResFP30dto23_uid123_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt(COUNTER,1214)
-- every=1, low=0, high=25, step=1, init=1
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i = 24 THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i - 25;
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i,5));
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg(REG,1215)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux(MUX,1216)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux: PROCESS (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem(DUALMEM,1213)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 <= areset;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia <= reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq,
address_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa,
data_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia
);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq(7 downto 0);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg(DELAY,1212)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q, xout => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest(BITSELECT,433)@39
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest(BITJOIN,435)@39
rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest(CONSTANT,285)
rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q <= "000000";
--RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest(BITSELECT,428)@39
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest(BITJOIN,430)@39
rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest(BITSELECT,425)@39
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest(BITJOIN,427)@39
rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest(BITSELECT,422)@39
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest(BITJOIN,424)@39
rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest(CONSTANT,275)
rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q <= "000000000000000000000000";
--cstAllZWF_uid10_fpArccosXTest(CONSTANT,9)
cstAllZWF_uid10_fpArccosXTest_q <= "00000000000000000000000";
--maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest(CONSTANT,209)
maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q <= "100011";
--reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1(REG,506)@1
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= y_uid52_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid18_uid54_fpArccosXTest(BITJOIN,53)@1
pad_o_uid18_uid54_fpArccosXTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0(REG,505)@1
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= pad_o_uid18_uid54_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid54_fpArccosXTest(SUB,54)@2
oMy_uid54_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q);
oMy_uid54_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q);
oMy_uid54_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid54_fpArccosXTest_a) - UNSIGNED(oMy_uid54_fpArccosXTest_b));
oMy_uid54_fpArccosXTest_q <= oMy_uid54_fpArccosXTest_o(36 downto 0);
--l_uid56_fpArccosXTest(BITSELECT,55)@2
l_uid56_fpArccosXTest_in <= oMy_uid54_fpArccosXTest_q(34 downto 0);
l_uid56_fpArccosXTest_b <= l_uid56_fpArccosXTest_in(34 downto 0);
--rVStage_uid168_fpLOut1_uid57_fpArccosXTest(BITSELECT,167)@2
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b;
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in(34 downto 3);
--reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1(REG,507)@2
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid169_fpLOut1_uid57_fpArccosXTest(LOGICAL,168)@3
vCount_uid169_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid169_fpLOut1_uid57_fpArccosXTest_a = vCount_uid169_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f(DELAY,792)@3
ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid169_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid171_fpLOut1_uid57_fpArccosXTest(BITSELECT,170)@2
vStage_uid171_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b(2 downto 0);
vStage_uid171_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_in(2 downto 0);
--cStage_uid172_fpLOut1_uid57_fpArccosXTest(BITJOIN,171)@2
cStage_uid172_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3(REG,509)@2
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid172_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2(REG,508)@2
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= l_uid56_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid173_fpLOut1_uid57_fpArccosXTest(MUX,172)@3
vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid169_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid173_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s, en, reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid175_fpLOut1_uid57_fpArccosXTest(BITSELECT,174)@3
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in(34 downto 19);
--reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1(REG,510)@3
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid176_fpLOut1_uid57_fpArccosXTest(LOGICAL,175)@4
vCount_uid176_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid176_fpLOut1_uid57_fpArccosXTest_a = vCount_uid176_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e(DELAY,791)@4
ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid176_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid178_fpLOut1_uid57_fpArccosXTest(BITSELECT,177)@3
vStage_uid178_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q(18 downto 0);
vStage_uid178_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_in(18 downto 0);
--cStage_uid179_fpLOut1_uid57_fpArccosXTest(BITJOIN,178)@3
cStage_uid179_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3(REG,512)@3
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid179_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2(REG,511)@3
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid180_fpLOut1_uid57_fpArccosXTest(MUX,179)@4
vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid176_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid180_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid182_fpLOut1_uid57_fpArccosXTest(BITSELECT,181)@4
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in(34 downto 27);
--vCount_uid183_fpLOut1_uid57_fpArccosXTest(LOGICAL,182)@4
vCount_uid183_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid183_fpLOut1_uid57_fpArccosXTest_a = vCount_uid183_fpLOut1_uid57_fpArccosXTest_b else "0";
--reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3(REG,516)@4
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid185_fpLOut1_uid57_fpArccosXTest(BITSELECT,184)@4
vStage_uid185_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q(26 downto 0);
vStage_uid185_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_in(26 downto 0);
--cStage_uid186_fpLOut1_uid57_fpArccosXTest(BITJOIN,185)@4
cStage_uid186_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_b & cstAllZWE_uid12_fpArccosXTest_q;
--vStagei_uid187_fpLOut1_uid57_fpArccosXTest(MUX,186)@4
vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid187_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q, cStage_uid186_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid186_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid189_fpLOut1_uid57_fpArccosXTest(BITSELECT,188)@4
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in(34 downto 31);
--reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1(REG,513)@4
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid190_fpLOut1_uid57_fpArccosXTest(LOGICAL,189)@5
vCount_uid190_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid190_fpLOut1_uid57_fpArccosXTest_a = vCount_uid190_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid192_fpLOut1_uid57_fpArccosXTest(BITSELECT,191)@4
vStage_uid192_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q(30 downto 0);
vStage_uid192_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_in(30 downto 0);
--cStage_uid193_fpLOut1_uid57_fpArccosXTest(BITJOIN,192)@4
cStage_uid193_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3(REG,515)@4
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid193_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2(REG,514)@4
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_fpLOut1_uid57_fpArccosXTest(MUX,193)@5
vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid190_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid194_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_fpLOut1_uid57_fpArccosXTest(BITSELECT,195)@5
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in(34 downto 33);
--vCount_uid197_fpLOut1_uid57_fpArccosXTest(LOGICAL,196)@5
vCount_uid197_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid197_fpLOut1_uid57_fpArccosXTest_a = vCount_uid197_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid199_fpLOut1_uid57_fpArccosXTest(BITSELECT,198)@5
vStage_uid199_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q(32 downto 0);
vStage_uid199_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_in(32 downto 0);
--cStage_uid200_fpLOut1_uid57_fpArccosXTest(BITJOIN,199)@5
cStage_uid200_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
--vStagei_uid201_fpLOut1_uid57_fpArccosXTest(MUX,200)@5
vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid197_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid201_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q, cStage_uid200_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid200_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid203_fpLOut1_uid57_fpArccosXTest(BITSELECT,202)@5
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in(34 downto 34);
--vCount_uid204_fpLOut1_uid57_fpArccosXTest(LOGICAL,203)@5
vCount_uid204_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_b <= GND_q;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid204_fpLOut1_uid57_fpArccosXTest_a = vCount_uid204_fpLOut1_uid57_fpArccosXTest_b else "0";
--vCount_uid209_fpLOut1_uid57_fpArccosXTest(BITJOIN,208)@5
vCount_uid209_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q & ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q & reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q & vCount_uid190_fpLOut1_uid57_fpArccosXTest_q & vCount_uid197_fpLOut1_uid57_fpArccosXTest_q & vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
--ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c(DELAY,795)@5
ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid209_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1(REG,517)@5
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= vCount_uid209_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid211_fpLOut1_uid57_fpArccosXTest(COMPARE,210)@6
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin <= GND_q;
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q) & '0';
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q) & vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin(0);
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a) - UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b));
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c(0) <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o(8);
--vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest(MUX,212)@6
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c;
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q;
WHEN "1" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid16_fpArccosXTest(CONSTANT,15)
cstBiasM2_uid16_fpArccosXTest_q <= "01111101";
--expL_uid58_fpArccosXTest(SUB,57)@7
expL_uid58_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid16_fpArccosXTest_q);
expL_uid58_fpArccosXTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q);
expL_uid58_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid58_fpArccosXTest_a) - UNSIGNED(expL_uid58_fpArccosXTest_b));
expL_uid58_fpArccosXTest_q <= expL_uid58_fpArccosXTest_o(8 downto 0);
--expLRange_uid60_fpArccosXTest(BITSELECT,59)@7
expLRange_uid60_fpArccosXTest_in <= expL_uid58_fpArccosXTest_q(7 downto 0);
expLRange_uid60_fpArccosXTest_b <= expLRange_uid60_fpArccosXTest_in(7 downto 0);
--vStage_uid206_fpLOut1_uid57_fpArccosXTest(BITSELECT,205)@5
vStage_uid206_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
vStage_uid206_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_in(33 downto 0);
--cStage_uid207_fpLOut1_uid57_fpArccosXTest(BITJOIN,206)@5
cStage_uid207_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_b & GND_q;
--vStagei_uid208_fpLOut1_uid57_fpArccosXTest(MUX,207)@5
vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid208_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q, cStage_uid207_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid207_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid59_fpArccosXTest(BITSELECT,58)@5
fpLOutFrac_uid59_fpArccosXTest_in <= vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
fpLOutFrac_uid59_fpArccosXTest_b <= fpLOutFrac_uid59_fpArccosXTest_in(33 downto 11);
--ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a(DELAY,1111)@5
ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid59_fpArccosXTest_b, xout => ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0(REG,518)@6
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid61_fpArccosXTest(BITJOIN,60)@7
fpL_uid61_fpArccosXTest_q <= GND_q & expLRange_uid60_fpArccosXTest_b & reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q;
--signX_uid218_sqrtFPL_uid63_fpArccosXTest(BITSELECT,217)@7
signX_uid218_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q;
signX_uid218_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_in(31 downto 31);
--expX_uid216_sqrtFPL_uid63_fpArccosXTest(BITSELECT,215)@7
expX_uid216_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(30 downto 0);
expX_uid216_sqrtFPL_uid63_fpArccosXTest_b <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest(LOGICAL,222)@7
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q <= "1" when expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a = expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b else "0";
--negZero_uid266_sqrtFPL_uid63_fpArccosXTest(LOGICAL,265)@7
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a and negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c(DELAY,851)@8
ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor(LOGICAL,1249)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q <= not (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a or ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b);
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top(CONSTANT,1245)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp(LOGICAL,1246)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q <= "1" when ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a = ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b else "0";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg(REG,1247)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena(REG,1250)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd(LOGICAL,1251)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a and ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b;
--cstBiasM1_uid14_fpArccosXTest(CONSTANT,13)
cstBiasM1_uid14_fpArccosXTest_q <= "01111110";
--reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0(REG,528)@7
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest(ADD,238)@8
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b));
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expROdd_uid240_sqrtFPL_uid63_fpArccosXTest(BITSELECT,239)@8
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q;
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest(ADD,235)@8
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b));
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expREven_uid237_sqrtFPL_uid63_fpArccosXTest(BITSELECT,236)@8
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q;
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expX0_uid241_sqrtFPL_uid63_fpArccosXTest(BITSELECT,240)@7
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b(0 downto 0);
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in(0 downto 0);
--expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest(LOGICAL,241)@7
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b;
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q <= not expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a;
--ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b(DELAY,819)@7
ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid243_sqrtFPL_uid63_fpArccosXTest(MUX,242)@8
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s <= ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q;
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "0" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "1" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b;
WHEN OTHERS => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b(DELAY,831)@7
ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid218_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest(LOGICAL,230)@8
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a;
--fracX_uid217_sqrtFPL_uid63_fpArccosXTest(BITSELECT,216)@7
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(22 downto 0);
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in(22 downto 0);
--reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1(REG,519)@7
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest(LOGICAL,226)@8
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a <= reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q <= "1" when fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a = fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b else "0";
--expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest(LOGICAL,224)@7
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a = expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b) THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid228_sqrtFPL_uid63_fpArccosXTest(LOGICAL,227)@8
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a and exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b;
--InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest(LOGICAL,231)@8
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a;
--InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest(LOGICAL,232)@7
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= not InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid234_sqrtFPL_uid63_fpArccosXTest(LOGICAL,233)@8
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a <= InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b <= InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c <= InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c;
--minReg_uid252_sqrtFPL_uid63_fpArccosXTest(LOGICAL,251)@8
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a and minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b;
--minInf_uid253_sqrtFPL_uid63_fpArccosXTest(LOGICAL,252)@8
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a and minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b;
--InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest(LOGICAL,228)@8
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q <= not InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a;
--exc_N_uid230_sqrtFPL_uid63_fpArccosXTest(LOGICAL,229)@8
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b <= InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a and exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b;
--excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest(LOGICAL,253)@8
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c;
--InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest(LOGICAL,249)@7
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q <= not InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a;
--ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b(DELAY,829)@7
ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest(LOGICAL,250)@8
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b <= ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q <= inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a and inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b;
--ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a(DELAY,837)@7
ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid255_sqrtFPL_uid63_fpArccosXTest(BITJOIN,254)@8
join_uid255_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q & inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q & ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q;
--fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest(BITJOIN,255)@8
fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q & join_uid255_sqrtFPL_uid63_fpArccosXTest_q;
--reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0(REG,520)@8
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid257_sqrtFPL_uid63_fpArccosXTest(LOOKUP,256)@9
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest: PROCESS (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q) IS
WHEN "0000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "01";
WHEN "0001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "0101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN OTHERS =>
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest(MUX,260)@9
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s <= fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q;
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest: PROCESS (expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg(DELAY,1239)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt(COUNTER,1241)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg(REG,1242)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux(MUX,1243)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem(DUALMEM,1240)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia
);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArccosXTest(CONSTANT,10)
cstNaNWF_uid11_fpArccosXTest_q <= "00000000000000000000001";
--fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest(BITSELECT,244)@7
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b <= fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in(22 downto 16);
--addrTable_uid246_sqrtFPL_uid63_fpArccosXTest(BITJOIN,245)@7
addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q <= expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q & fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b;
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0(REG,521)@7
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sqrtTableGenerator_lutmem(DUALMEM,497)@8
memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid458_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid458_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid458_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid458_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid458_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid458_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid458_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid458_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid458_sqrtTableGenerator_lutmem_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1(REG,523)@10
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg(DELAY,1238)
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a(DELAY,825)@7
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest(BITSELECT,246)@10
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in <= ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q(15 downto 0);
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in(15 downto 0);
--yT1_uid459_sqrtPolynomialEvaluator(BITSELECT,458)@10
yT1_uid459_sqrtPolynomialEvaluator_in <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
yT1_uid459_sqrtPolynomialEvaluator_b <= yT1_uid459_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0(REG,522)@10
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= yT1_uid459_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator(MULT,483)@11
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b);
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator(BITSELECT,484)@14
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid462_sqrtPolynomialEvaluator(BITSELECT,461)@14
highBBits_uid462_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b;
highBBits_uid462_sqrtPolynomialEvaluator_b <= highBBits_uid462_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1303)
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a(DELAY,1117)@7
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0(REG,524)@11
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sqrtTableGenerator_lutmem(DUALMEM,496)@12
memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid457_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid457_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid457_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid457_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid457_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid457_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid457_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid457_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid457_sqrtTableGenerator_lutmem_q <= memoryC1_uid457_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid463_sqrtPolynomialEvaluator(ADD,462)@14
sumAHighB_uid463_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid457_sqrtTableGenerator_lutmem_q);
sumAHighB_uid463_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid462_sqrtPolynomialEvaluator_b(11)) & highBBits_uid462_sqrtPolynomialEvaluator_b);
sumAHighB_uid463_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_b));
sumAHighB_uid463_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid461_sqrtPolynomialEvaluator(BITSELECT,460)@14
lowRangeB_uid461_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid461_sqrtPolynomialEvaluator_b <= lowRangeB_uid461_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid461_uid464_sqrtPolynomialEvaluator(BITJOIN,463)@14
s1_uid461_uid464_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_q & lowRangeB_uid461_sqrtPolynomialEvaluator_b;
--reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1(REG,526)@14
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= s1_uid461_uid464_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor(LOGICAL,1285)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b);
--roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest(CONSTANT,369)
roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q <= "010";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp(LOGICAL,1282)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a = ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg(REG,1283)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena(REG,1286)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,1287)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0(REG,525)@10
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,1277)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 1 THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i,2));
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg(REG,1278)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,1279)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,1276)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia <= reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator(MULT,486)@15
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b);
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator(BITSELECT,487)@18
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid468_sqrtPolynomialEvaluator(BITSELECT,467)@18
highBBits_uid468_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b;
highBBits_uid468_sqrtPolynomialEvaluator_b <= highBBits_uid468_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor(LOGICAL,1300)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena(REG,1301)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,1302)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,1291)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1290)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q, xout => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid456_sqrtTableGenerator_lutmem(DUALMEM,495)@16
memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid456_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC0_uid456_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid456_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid456_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid456_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid456_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid456_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid456_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid456_sqrtTableGenerator_lutmem_q <= memoryC0_uid456_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid469_sqrtPolynomialEvaluator(ADD,468)@18
sumAHighB_uid469_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid456_sqrtTableGenerator_lutmem_q);
sumAHighB_uid469_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sqrtPolynomialEvaluator_b(21)) & highBBits_uid468_sqrtPolynomialEvaluator_b);
sumAHighB_uid469_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_b));
sumAHighB_uid469_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid467_sqrtPolynomialEvaluator(BITSELECT,466)@18
lowRangeB_uid467_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid467_sqrtPolynomialEvaluator_b <= lowRangeB_uid467_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid467_uid470_sqrtPolynomialEvaluator(BITJOIN,469)@18
s2_uid467_uid470_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_q & lowRangeB_uid467_sqrtPolynomialEvaluator_b;
--fracR_uid249_sqrtFPL_uid63_fpArccosXTest(BITSELECT,248)@18
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in <= s2_uid467_uid470_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in(28 downto 6);
--ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b(DELAY,845)@9
ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest(MUX,264)@18
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s <= ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q;
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest: PROCESS (fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "10" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest(BITJOIN,266)@18
RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q <= ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q & fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q;
--SqrtFPL22dto0_uid64_fpArccosXTest(BITSELECT,63)@18
SqrtFPL22dto0_uid64_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(22 downto 0);
SqrtFPL22dto0_uid64_fpArccosXTest_b <= SqrtFPL22dto0_uid64_fpArccosXTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1(REG,552)@18
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL22dto0_uid64_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest(LOGICAL,327)@19
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b(DELAY,901)@19
ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q, xout => ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid66_fpArccosXTest(BITSELECT,65)@18
SqrtFPL30dto23_uid66_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(30 downto 0);
SqrtFPL30dto23_uid66_fpArccosXTest_b <= SqrtFPL30dto23_uid66_fpArccosXTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1(REG,530)@18
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL30dto23_uid66_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid326_arcsinL_uid78_fpArccosXTest(LOGICAL,325)@19
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a(DELAY,900)@19
ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid329_arcsinL_uid78_fpArccosXTest(LOGICAL,328)@31
exc_I_uid329_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_b <= ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_a and exc_I_uid329_arcsinL_uid78_fpArccosXTest_b;
--reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2(REG,565)@31
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest(BITSELECT,289)@20
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest(BITJOIN,291)@20
rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b;
--oSqrtFPLFrac_uid65_fpArccosXTest(BITJOIN,64)@18
oSqrtFPLFrac_uid65_fpArccosXTest_q <= VCC_q & SqrtFPL22dto0_uid64_fpArccosXTest_b;
--X23dto16_uid273_alignSqrt_uid69_fpArccosXTest(BITSELECT,272)@18
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b <= X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest(BITJOIN,274)@18
rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4(REG,534)@18
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid270_alignSqrt_uid69_fpArccosXTest(BITSELECT,269)@18
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b <= X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest(BITJOIN,271)@18
rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3(REG,533)@18
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2(REG,532)@18
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid67_fpArccosXTest(SUB,66)@19
srVal_uid67_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
srVal_uid67_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q);
srVal_uid67_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid67_fpArccosXTest_a) - UNSIGNED(srVal_uid67_fpArccosXTest_b));
srVal_uid67_fpArccosXTest_q <= srVal_uid67_fpArccosXTest_o(8 downto 0);
--srValRange_uid68_fpArccosXTest(BITSELECT,67)@19
srValRange_uid68_fpArccosXTest_in <= srVal_uid67_fpArccosXTest_q(4 downto 0);
srValRange_uid68_fpArccosXTest_b <= srValRange_uid68_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest(BITSELECT,276)@19
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in(4 downto 3);
--rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest(MUX,277)@19
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b;
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s, en, reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest(BITSELECT,284)@19
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest(BITJOIN,286)@19
rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5(REG,539)@19
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest(BITSELECT,281)@19
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest(BITJOIN,283)@19
rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4(REG,538)@19
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest(BITSELECT,278)@19
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest(BITJOIN,280)@19
rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3(REG,537)@19
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2(REG,536)@19
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest(BITSELECT,287)@19
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1(REG,535)@19
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest(MUX,288)@20
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s, en, reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest(BITSELECT,292)@19
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1(REG,540)@19
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest(MUX,293)@20
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s, en, rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q, rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid71_fpArccosXTest(BITSELECT,70)@20
sAddr_uid71_fpArccosXTest_in <= rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q;
sAddr_uid71_fpArccosXTest_b <= sAddr_uid71_fpArccosXTest_in(23 downto 16);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0(REG,541)@20
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid71_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid298_arcsinXO2XTabGen_lutmem(DUALMEM,491)@21
memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid298_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid298_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1(REG,543)@23
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg(DELAY,1185)
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a(DELAY,642)@20
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid72_fpArccosXTest(BITSELECT,71)@23
sPPolyEval_uid72_fpArccosXTest_in <= ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q(15 downto 0);
sPPolyEval_uid72_fpArccosXTest_b <= sPPolyEval_uid72_fpArccosXTest_in(15 downto 1);
--yT1_uid299_arcsinXO2XPolyEval(BITSELECT,298)@23
yT1_uid299_arcsinXO2XPolyEval_in <= sPPolyEval_uid72_fpArccosXTest_b;
yT1_uid299_arcsinXO2XPolyEval_b <= yT1_uid299_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0(REG,542)@23
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= yT1_uid299_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval(MULT,471)@24
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b);
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval(BITSELECT,472)@27
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid302_arcsinXO2XPolyEval(BITSELECT,301)@27
highBBits_uid302_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b;
highBBits_uid302_arcsinXO2XPolyEval_b <= highBBits_uid302_arcsinXO2XPolyEval_in(12 downto 1);
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a(DELAY,1083)@21
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1288)
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid297_arcsinXO2XTabGen_lutmem(DUALMEM,490)@25
memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab <= ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid297_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid297_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid303_arcsinXO2XPolyEval(ADD,302)@27
sumAHighB_uid303_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid297_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid303_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid302_arcsinXO2XPolyEval_b(11)) & highBBits_uid302_arcsinXO2XPolyEval_b);
sumAHighB_uid303_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_b));
sumAHighB_uid303_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid301_arcsinXO2XPolyEval(BITSELECT,300)@27
lowRangeB_uid301_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid301_arcsinXO2XPolyEval_b <= lowRangeB_uid301_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid301_uid304_arcsinXO2XPolyEval(BITJOIN,303)@27
s1_uid301_uid304_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_q & lowRangeB_uid301_arcsinXO2XPolyEval_b;
--reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1(REG,546)@27
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= s1_uid301_uid304_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1312)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg(REG,1310)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1313)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1314)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1304)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid72_fpArccosXTest_b, xout => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt(COUNTER,1306)
-- every=1, low=0, high=1, step=1, init=1
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i,1));
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg(REG,1307)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux(MUX,1308)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux: PROCESS (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1305)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0(REG,545)@27
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval(MULT,474)@28
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b);
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval(BITSELECT,475)@31
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid308_arcsinXO2XPolyEval(BITSELECT,307)@31
highBBits_uid308_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b;
highBBits_uid308_arcsinXO2XPolyEval_b <= highBBits_uid308_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1325)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1326)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1327)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1315)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid71_fpArccosXTest_b, xout => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1316)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0(REG,547)@28
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid296_arcsinXO2XTabGen_lutmem(DUALMEM,489)@29
memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid296_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid296_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid309_arcsinXO2XPolyEval(ADD,308)@31
sumAHighB_uid309_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid296_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid309_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid308_arcsinXO2XPolyEval_b(19)) & highBBits_uid308_arcsinXO2XPolyEval_b);
sumAHighB_uid309_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_b));
sumAHighB_uid309_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid307_arcsinXO2XPolyEval(BITSELECT,306)@31
lowRangeB_uid307_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid307_arcsinXO2XPolyEval_b <= lowRangeB_uid307_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid307_uid310_arcsinXO2XPolyEval(BITJOIN,309)@31
s2_uid307_uid310_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_q & lowRangeB_uid307_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid74_fpArccosXTest(BITSELECT,73)@31
fxpArcSinXO2XRes_uid74_fpArccosXTest_in <= s2_uid307_uid310_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid74_fpArccosXTest_b <= fxpArcSinXO2XRes_uid74_fpArccosXTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid75_fpArccosXTest(BITSELECT,74)@31
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in <= fxpArcSinXO2XRes_uid74_fpArccosXTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b <= fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in(24 downto 2);
--fpArcsinXO2XRes_uid76_fpArccosXTest(BITJOIN,75)@31
fpArcsinXO2XRes_uid76_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b;
--expY_uid313_arcsinL_uid78_fpArccosXTest(BITSELECT,312)@31
expY_uid313_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(30 downto 0);
expY_uid313_arcsinL_uid78_fpArccosXTest_b <= expY_uid313_arcsinL_uid78_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid340_arcsinL_uid78_fpArccosXTest(LOGICAL,339)@31
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b else "0";
--reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2(REG,549)@31
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest(LOGICAL,393)@32
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b <= reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b;
--fracY_uid318_arcsinL_uid78_fpArccosXTest(BITSELECT,317)@31
fracY_uid318_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(22 downto 0);
fracY_uid318_arcsinL_uid78_fpArccosXTest_b <= fracY_uid318_arcsinL_uid78_fpArccosXTest_in(22 downto 0);
--reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1(REG,550)@31
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest(LOGICAL,343)@32
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a <= reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b else "0";
--expXIsMax_uid342_arcsinL_uid78_fpArccosXTest(LOGICAL,341)@31
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b) THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid345_arcsinL_uid78_fpArccosXTest(LOGICAL,344)@32
exc_I_uid345_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_b <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_a and exc_I_uid345_arcsinL_uid78_fpArccosXTest_b;
--expXIsZero_uid324_arcsinL_uid78_fpArccosXTest(LOGICAL,323)@19
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a(DELAY,964)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest(LOGICAL,394)@32
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b;
--ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest(LOGICAL,395)@32
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a or ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest(LOGICAL,345)@32
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid347_arcsinL_uid78_fpArccosXTest(LOGICAL,346)@32
exc_N_uid347_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_a and exc_N_uid347_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest(LOGICAL,329)@19
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid331_arcsinL_uid78_fpArccosXTest(LOGICAL,330)@19
exc_N_uid331_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_a and exc_N_uid331_arcsinL_uid78_fpArccosXTest_b;
--ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a(DELAY,994)@19
ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid331_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid397_arcsinL_uid78_fpArccosXTest(LOGICAL,396)@32
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a <= ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c;
--InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest(LOGICAL,408)@32
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q;
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= not InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--signY_uid315_arcsinL_uid78_fpArccosXTest(BITSELECT,314)@31
signY_uid315_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q;
signY_uid315_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--signX_uid314_arcsinL_uid78_fpArccosXTest(BITSELECT,313)@18
signX_uid314_arcsinL_uid78_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q;
signX_uid314_arcsinL_uid78_fpArccosXTest_b <= signX_uid314_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1(REG,569)@18
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= signX_uid314_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a(DELAY,958)@19
ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid380_arcsinL_uid78_fpArccosXTest(LOGICAL,379)@31
signR_uid380_arcsinL_uid78_fpArccosXTest_a <= ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q;
signR_uid380_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_b;
signR_uid380_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= signR_uid380_arcsinL_uid78_fpArccosXTest_a xor signR_uid380_arcsinL_uid78_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a(DELAY,1006)@32
ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid380_arcsinL_uid78_fpArccosXTest_q, xout => ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid410_arcsinL_uid78_fpArccosXTest(LOGICAL,409)@33
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a <= ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b <= InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q <= signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a and signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b;
--ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c(DELAY,1010)@33
ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q, xout => ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest(BITJOIN,318)@31
add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q <= VCC_q & fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
--reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1(REG,556)@31
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1273)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top(CONSTANT,1257)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp(LOGICAL,1258)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg(REG,1259)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1274)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1275)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt(COUNTER,1253)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg(REG,1254)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux(MUX,1255)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1264)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(23 downto 0);
--prod_uid355_arcsinL_uid78_fpArccosXTest(MULT,354)@32
prod_uid355_arcsinL_uid78_fpArccosXTest_pr <= UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_a) * UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_b);
prod_uid355_arcsinL_uid78_fpArccosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= STD_LOGIC_VECTOR(prod_uid355_arcsinL_uid78_fpArccosXTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid355_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= prod_uid355_arcsinL_uid78_fpArccosXTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid356_arcsinL_uid78_fpArccosXTest(BITSELECT,355)@35
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q;
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in(47 downto 47);
--fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest(BITSELECT,357)@35
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(46 downto 0);
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in(46 downto 23);
--fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest(BITSELECT,358)@35
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(45 downto 0);
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in(45 downto 22);
--fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest(MUX,359)@35
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s, en, fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b, fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b;
WHEN "1" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest(BITSELECT,367)@35
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in <= fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q(1 downto 0);
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in(1 downto 0);
--Prod22_uid362_arcsinL_uid78_fpArccosXTest(BITSELECT,361)@35
Prod22_uid362_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
Prod22_uid362_arcsinL_uid78_fpArccosXTest_b <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_in(22 downto 22);
--extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest(MUX,362)@35
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest: PROCESS (extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s, en, GND_q, Prod22_uid362_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid361_arcsinL_uid78_fpArccosXTest(BITSELECT,360)@35
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(21 downto 0);
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b <= stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in(21 downto 0);
--stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest(BITJOIN,363)@35
stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q <= extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q & stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b;
--stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest(LOGICAL,365)@35
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a <= stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q <= "1" when stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a = stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b else "0";
--sticky_uid367_arcsinL_uid78_fpArccosXTest(LOGICAL,366)@35
sticky_uid367_arcsinL_uid78_fpArccosXTest_a <= stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q;
sticky_uid367_arcsinL_uid78_fpArccosXTest_q <= not sticky_uid367_arcsinL_uid78_fpArccosXTest_a;
--lrs_uid369_arcsinL_uid78_fpArccosXTest(BITJOIN,368)@35
lrs_uid369_arcsinL_uid78_fpArccosXTest_q <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b & sticky_uid367_arcsinL_uid78_fpArccosXTest_q;
--roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest(LOGICAL,370)@35
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a <= lrs_uid369_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q <= "1" when roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a = roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b else "0";
--roundBit_uid372_arcsinL_uid78_fpArccosXTest(LOGICAL,371)@35
roundBit_uid372_arcsinL_uid78_fpArccosXTest_a <= roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q;
roundBit_uid372_arcsinL_uid78_fpArccosXTest_q <= not roundBit_uid372_arcsinL_uid78_fpArccosXTest_a;
--roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest(BITJOIN,374)@35
roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q <= GND_q & normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b & cstAllZWF_uid10_fpArccosXTest_q & roundBit_uid372_arcsinL_uid78_fpArccosXTest_q;
--reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1(REG,560)@35
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid353_arcsinL_uid78_fpArccosXTest(CONSTANT,352)
biasInc_uid353_arcsinL_uid78_fpArccosXTest_q <= "0001111111";
--reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1(REG,558)@31
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1261)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1262)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1263)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1252)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(7 downto 0);
--expSum_uid352_arcsinL_uid78_fpArccosXTest(ADD,351)@32
expSum_uid352_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_a) + UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid352_arcsinL_uid78_fpArccosXTest_q <= expSum_uid352_arcsinL_uid78_fpArccosXTest_o(8 downto 0);
--ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a(DELAY,927)@33
ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid352_arcsinL_uid78_fpArccosXTest_q, xout => ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid354_arcsinL_uid78_fpArccosXTest(SUB,353)@34
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid353_arcsinL_uid78_fpArccosXTest_q(9)) & biasInc_uid353_arcsinL_uid78_fpArccosXTest_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o(10 downto 0);
--expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest(BITJOIN,372)@35
expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q & fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q;
--reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0(REG,559)@35
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest(ADD,375)@36
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q(34)) & reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a) + SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b));
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o(35 downto 0);
--expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest(BITSELECT,377)@36
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q;
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in(35 downto 24);
--expRPreExc_uid379_arcsinL_uid78_fpArccosXTest(BITSELECT,378)@36
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b(7 downto 0);
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in(7 downto 0);
--reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3(REG,568)@36
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d(DELAY,1004)@37
ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c(DELAY,999)@32
ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q, xout => ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1(REG,561)@36
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid383_arcsinL_uid78_fpArccosXTest(COMPARE,382)@37
expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expOvf_uid383_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & '0';
expOvf_uid383_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid9_fpArccosXTest_q) & expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin(0);
expOvf_uid383_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_b));
expOvf_uid383_arcsinL_uid78_fpArccosXTest_n(0) <= not expOvf_uid383_arcsinL_uid78_fpArccosXTest_o(14);
--InvExc_N_uid348_arcsinL_uid78_fpArccosXTest(LOGICAL,347)@32
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a;
--InvExc_I_uid349_arcsinL_uid78_fpArccosXTest(LOGICAL,348)@32
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a;
--InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest(LOGICAL,349)@31
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid351_arcsinL_uid78_fpArccosXTest(LOGICAL,350)@32
exc_R_uid351_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_c <= InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_a and exc_R_uid351_arcsinL_uid78_fpArccosXTest_b and exc_R_uid351_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b(DELAY,969)@32
ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid351_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid332_arcsinL_uid78_fpArccosXTest(LOGICAL,331)@19
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a;
--ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c(DELAY,910)@19
ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q, xout => ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid333_arcsinL_uid78_fpArccosXTest(LOGICAL,332)@31
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a;
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a(DELAY,907)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest(LOGICAL,333)@31
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q;
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a;
--exc_R_uid335_arcsinL_uid78_fpArccosXTest(LOGICAL,334)@31
exc_R_uid335_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_c <= ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_a and exc_R_uid335_arcsinL_uid78_fpArccosXTest_b and exc_R_uid335_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a(DELAY,968)@31
ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid335_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest(LOGICAL,391)@37
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c <= expOvf_uid383_arcsinL_uid78_fpArccosXTest_n;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a(DELAY,975)@31
ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid329_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest(LOGICAL,390)@32
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q <= excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a and excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b;
--ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c(DELAY,986)@32
ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2(REG,554)@31
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest(LOGICAL,389)@32
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q <= excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a and excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b;
--ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b(DELAY,985)@32
ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest(LOGICAL,388)@32
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q <= excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a and excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b;
--ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a(DELAY,984)@32
ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid393_arcsinL_uid78_fpArccosXTest(LOGICAL,392)@37
excRInf_uid393_arcsinL_uid78_fpArccosXTest_a <= ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_b <= ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_c <= ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_d <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_q <= excRInf_uid393_arcsinL_uid78_fpArccosXTest_a or excRInf_uid393_arcsinL_uid78_fpArccosXTest_b or excRInf_uid393_arcsinL_uid78_fpArccosXTest_c or excRInf_uid393_arcsinL_uid78_fpArccosXTest_d;
--expUdf_uid381_arcsinL_uid78_fpArccosXTest(COMPARE,380)@37
expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expUdf_uid381_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid381_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin(0);
expUdf_uid381_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_b));
expUdf_uid381_arcsinL_uid78_fpArccosXTest_n(0) <= not expUdf_uid381_arcsinL_uid78_fpArccosXTest_o(14);
--excZC3_uid387_arcsinL_uid78_fpArccosXTest(LOGICAL,386)@37
excZC3_uid387_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_c <= expUdf_uid381_arcsinL_uid78_fpArccosXTest_n;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_q <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_a and excZC3_uid387_arcsinL_uid78_fpArccosXTest_b and excZC3_uid387_arcsinL_uid78_fpArccosXTest_c;
--excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest(LOGICAL,385)@32
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b;
--ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c(DELAY,973)@32
ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest(LOGICAL,384)@32
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b(DELAY,972)@32
ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1(REG,548)@19
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a(DELAY,962)@20
ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest(LOGICAL,383)@32
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a <= ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a(DELAY,971)@32
ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid388_arcsinL_uid78_fpArccosXTest(LOGICAL,387)@37
excRZero_uid388_arcsinL_uid78_fpArccosXTest_a <= ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_b <= ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_c <= ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_d <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_q <= excRZero_uid388_arcsinL_uid78_fpArccosXTest_a or excRZero_uid388_arcsinL_uid78_fpArccosXTest_b or excRZero_uid388_arcsinL_uid78_fpArccosXTest_c or excRZero_uid388_arcsinL_uid78_fpArccosXTest_d;
--concExc_uid398_arcsinL_uid78_fpArccosXTest(BITJOIN,397)@37
concExc_uid398_arcsinL_uid78_fpArccosXTest_q <= ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q & excRInf_uid393_arcsinL_uid78_fpArccosXTest_q & excRZero_uid388_arcsinL_uid78_fpArccosXTest_q;
--reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0(REG,566)@37
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= concExc_uid398_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid399_arcsinL_uid78_fpArccosXTest(LOOKUP,398)@38
excREnc_uid399_arcsinL_uid78_fpArccosXTest: PROCESS (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q) IS
WHEN "000" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "01";
WHEN "001" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "010" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "10";
WHEN "011" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "100" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "11";
WHEN "101" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "110" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "111" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN OTHERS =>
excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid408_arcsinL_uid78_fpArccosXTest(MUX,407)@38
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest: PROCESS (expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest(BITSELECT,376)@36
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q(23 downto 0);
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in(23 downto 1);
--reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3(REG,567)@36
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d(DELAY,1002)@37
ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest(MUX,402)@38
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid411_arcsinL_uid78_fpArccosXTest(BITJOIN,410)@38
R_uid411_arcsinL_uid78_fpArccosXTest_q <= ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q & expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q & fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q;
--ArcsinL22dto0_uid79_fpArccosXTest(BITSELECT,78)@38
ArcsinL22dto0_uid79_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
ArcsinL22dto0_uid79_fpArccosXTest_b <= ArcsinL22dto0_uid79_fpArccosXTest_in(22 downto 0);
--oFracArcsinL_uid80_fpArccosXTest(BITJOIN,79)@38
oFracArcsinL_uid80_fpArccosXTest_q <= VCC_q & ArcsinL22dto0_uid79_fpArccosXTest_b;
--X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest(BITSELECT,416)@38
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b <= X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest(BITJOIN,418)@38
rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4(REG,573)@38
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest(BITSELECT,413)@38
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b <= X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest(BITJOIN,415)@38
rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3(REG,572)@38
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2(REG,571)@38
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= oFracArcsinL_uid80_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid81_fpArccosXTest(BITSELECT,80)@38
ArcsinL30dto23_uid81_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(30 downto 0);
ArcsinL30dto23_uid81_fpArccosXTest_b <= ArcsinL30dto23_uid81_fpArccosXTest_in(30 downto 23);
--srValArcsinL_uid82_fpArccosXTest(SUB,81)@38
srValArcsinL_uid82_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
srValArcsinL_uid82_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid81_fpArccosXTest_b);
srValArcsinL_uid82_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid82_fpArccosXTest_a) - UNSIGNED(srValArcsinL_uid82_fpArccosXTest_b));
srValArcsinL_uid82_fpArccosXTest_q <= srValArcsinL_uid82_fpArccosXTest_o(8 downto 0);
--srValArcsinLRange_uid83_fpArccosXTest(BITSELECT,82)@38
srValArcsinLRange_uid83_fpArccosXTest_in <= srValArcsinL_uid82_fpArccosXTest_q(4 downto 0);
srValArcsinLRange_uid83_fpArccosXTest_b <= srValArcsinLRange_uid83_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest(BITSELECT,420)@38
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1(REG,570)@38
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest(MUX,421)@39
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s, en, reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest(BITSELECT,431)@38
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1(REG,574)@38
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest(MUX,432)@39
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "01" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "10" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "11" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest(BITSELECT,436)@38
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1(REG,575)@38
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest(MUX,437)@39
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid85_uid86_fpArccosXTest(BITJOIN,85)@39
pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q <= rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1(REG,576)@39
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid85_fpArccosXTest(CONSTANT,84)
pi_uid85_fpArccosXTest_q <= "1100100100001111110110101010";
--path1NegCase_uid86_fpArccosXTest(SUB,86)@40
path1NegCase_uid86_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & pi_uid85_fpArccosXTest_q);
path1NegCase_uid86_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q);
path1NegCase_uid86_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid86_fpArccosXTest_a) - UNSIGNED(path1NegCase_uid86_fpArccosXTest_b));
path1NegCase_uid86_fpArccosXTest_q <= path1NegCase_uid86_fpArccosXTest_o(28 downto 0);
--path1NegCaseN_uid88_fpArccosXTest(BITSELECT,87)@40
path1NegCaseN_uid88_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(27 downto 0);
path1NegCaseN_uid88_fpArccosXTest_b <= path1NegCaseN_uid88_fpArccosXTest_in(27 downto 27);
--reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1(REG,577)@40
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= path1NegCaseN_uid88_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid92_fpArccosXTest(ADD,91)@41
path1NegCaseExp_uid92_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
path1NegCaseExp_uid92_fpArccosXTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q);
path1NegCaseExp_uid92_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_a) + UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_b));
path1NegCaseExp_uid92_fpArccosXTest_q <= path1NegCaseExp_uid92_fpArccosXTest_o(8 downto 0);
--path1NegCaseExpRange_uid93_fpArccosXTest(BITSELECT,92)@41
path1NegCaseExpRange_uid93_fpArccosXTest_in <= path1NegCaseExp_uid92_fpArccosXTest_q(7 downto 0);
path1NegCaseExpRange_uid93_fpArccosXTest_b <= path1NegCaseExpRange_uid93_fpArccosXTest_in(7 downto 0);
--path1NegCaseFracHigh_uid89_fpArccosXTest(BITSELECT,88)@40
path1NegCaseFracHigh_uid89_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(26 downto 0);
path1NegCaseFracHigh_uid89_fpArccosXTest_b <= path1NegCaseFracHigh_uid89_fpArccosXTest_in(26 downto 4);
--path1NegCaseFracLow_uid90_fpArccosXTest(BITSELECT,89)@40
path1NegCaseFracLow_uid90_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(25 downto 0);
path1NegCaseFracLow_uid90_fpArccosXTest_b <= path1NegCaseFracLow_uid90_fpArccosXTest_in(25 downto 3);
--path1NegCaseFrac_uid91_fpArccosXTest(MUX,90)@40
path1NegCaseFrac_uid91_fpArccosXTest_s <= path1NegCaseN_uid88_fpArccosXTest_b;
path1NegCaseFrac_uid91_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid91_fpArccosXTest_s IS
WHEN "0" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracLow_uid90_fpArccosXTest_b;
WHEN "1" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracHigh_uid89_fpArccosXTest_b;
WHEN OTHERS => path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid94_fpArccosXTest(BITJOIN,93)@41
path1NegCaseUR_uid94_fpArccosXTest_q <= GND_q & path1NegCaseExpRange_uid93_fpArccosXTest_b & path1NegCaseFrac_uid91_fpArccosXTest_q;
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg(DELAY,1198)
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid411_arcsinL_uid78_fpArccosXTest_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c(DELAY,664)@38
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor(LOGICAL,1195)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q <= not (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a or ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b);
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top(CONSTANT,1191)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q <= "0100111";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp(LOGICAL,1192)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q <= "1" when ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a = ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b else "0";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg(REG,1193)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena(REG,1196)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd(LOGICAL,1197)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a and ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt(COUNTER,1187)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i,6));
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg(REG,1188)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux(MUX,1189)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux: PROCESS (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem(DUALMEM,1186)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia <= singX_uid8_fpArccosXTest_b;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq,
address_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa,
data_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia
);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid96_fpArccosXTest(MUX,95)@41
path1ResFP_uid96_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q;
path1ResFP_uid96_fpArccosXTest: PROCESS (path1ResFP_uid96_fpArccosXTest_s, en, ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, path1NegCaseUR_uid94_fpArccosXTest_q)
BEGIN
CASE path1ResFP_uid96_fpArccosXTest_s IS
WHEN "0" => path1ResFP_uid96_fpArccosXTest_q <= ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q;
WHEN "1" => path1ResFP_uid96_fpArccosXTest_q <= path1NegCaseUR_uid94_fpArccosXTest_q;
WHEN OTHERS => path1ResFP_uid96_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid124_fpArccosXTest(BITSELECT,123)@41
Path1ResFP30dto23_uid124_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(30 downto 0);
Path1ResFP30dto23_uid124_fpArccosXTest_b <= Path1ResFP30dto23_uid124_fpArccosXTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2(REG,589)@41
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= Path1ResFP30dto23_uid124_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor(LOGICAL,1209)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q <= not (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a or ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b);
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top(CONSTANT,1205)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp(LOGICAL,1206)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q <= "1" when ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a = ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b else "0";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg(REG,1207)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena(REG,1210)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd(LOGICAL,1211)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a and ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c(DELAY,686)@0
ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid51_fpArccosXTest(BITSELECT,50)@1
inputIsMax_uid51_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q;
inputIsMax_uid51_fpArccosXTest_b <= inputIsMax_uid51_fpArccosXTest_in(36 downto 36);
--firstPath_uid53_fpArccosXTest(BITSELECT,52)@1
firstPath_uid53_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
firstPath_uid53_fpArccosXTest_b <= firstPath_uid53_fpArccosXTest_in(34 downto 34);
--pathSelBits_uid117_fpArccosXTest(BITJOIN,116)@1
pathSelBits_uid117_fpArccosXTest_q <= ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q & inputIsMax_uid51_fpArccosXTest_b & firstPath_uid53_fpArccosXTest_b;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg(DELAY,1199)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid117_fpArccosXTest_q, xout => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt(COUNTER,1201)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg(REG,1202)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux(MUX,1203)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem(DUALMEM,1200)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia
);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid118_fpArccosXTest(LOOKUP,117)@41
fracOutMuxSelEnc_uid118_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid125_fpArccosXTest(MUX,124)@42
expRCalc_uid125_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
expRCalc_uid125_fpArccosXTest: PROCESS (expRCalc_uid125_fpArccosXTest_s, en, reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, cstBiasP1_uid17_fpArccosXTest_q, cstAllZWE_uid12_fpArccosXTest_q)
BEGIN
CASE expRCalc_uid125_fpArccosXTest_s IS
WHEN "00" => expRCalc_uid125_fpArccosXTest_q <= reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q;
WHEN "01" => expRCalc_uid125_fpArccosXTest_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q;
WHEN "10" => expRCalc_uid125_fpArccosXTest_q <= cstBiasP1_uid17_fpArccosXTest_q;
WHEN "11" => expRCalc_uid125_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN OTHERS => expRCalc_uid125_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArccosXTest(CONSTANT,11)
cstAllZWE_uid12_fpArccosXTest_q <= "00000000";
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor(LOGICAL,1235)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q <= not (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a or ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b);
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena(REG,1236)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q = "1") THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd(LOGICAL,1237)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b <= en;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a and ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b;
--fracXIsZero_uid38_fpArccosXTest(LOGICAL,37)@0
fracXIsZero_uid38_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid38_fpArccosXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid38_fpArccosXTest_q <= "1" when fracXIsZero_uid38_fpArccosXTest_a = fracXIsZero_uid38_fpArccosXTest_b else "0";
--InvFracXIsZero_uid39_fpArccosXTest(LOGICAL,38)@0
InvFracXIsZero_uid39_fpArccosXTest_a <= fracXIsZero_uid38_fpArccosXTest_q;
InvFracXIsZero_uid39_fpArccosXTest_q <= not InvFracXIsZero_uid39_fpArccosXTest_a;
--expEQ0_uid37_fpArccosXTest(LOGICAL,36)@0
expEQ0_uid37_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expEQ0_uid37_fpArccosXTest_b <= cstBias_uid13_fpArccosXTest_q;
expEQ0_uid37_fpArccosXTest_q <= "1" when expEQ0_uid37_fpArccosXTest_a = expEQ0_uid37_fpArccosXTest_b else "0";
--expXZFracNotZero_uid40_fpArccosXTest(LOGICAL,39)@0
expXZFracNotZero_uid40_fpArccosXTest_a <= expEQ0_uid37_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_b <= InvFracXIsZero_uid39_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_q <= expXZFracNotZero_uid40_fpArccosXTest_a and expXZFracNotZero_uid40_fpArccosXTest_b;
--expGT0_uid36_fpArccosXTest(COMPARE,35)@0
expGT0_uid36_fpArccosXTest_cin <= GND_q;
expGT0_uid36_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArccosXTest_q) & '0';
expGT0_uid36_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArccosXTest_b) & expGT0_uid36_fpArccosXTest_cin(0);
expGT0_uid36_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid36_fpArccosXTest_a) - UNSIGNED(expGT0_uid36_fpArccosXTest_b));
expGT0_uid36_fpArccosXTest_c(0) <= expGT0_uid36_fpArccosXTest_o(10);
--inputOutOfRange_uid41_fpArccosXTest(LOGICAL,40)@0
inputOutOfRange_uid41_fpArccosXTest_a <= expGT0_uid36_fpArccosXTest_c;
inputOutOfRange_uid41_fpArccosXTest_b <= expXZFracNotZero_uid40_fpArccosXTest_q;
inputOutOfRange_uid41_fpArccosXTest_q <= inputOutOfRange_uid41_fpArccosXTest_a or inputOutOfRange_uid41_fpArccosXTest_b;
--InvExc_N_uid32_fpArccosXTest(LOGICAL,31)@0
InvExc_N_uid32_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
InvExc_N_uid32_fpArccosXTest_q <= not InvExc_N_uid32_fpArccosXTest_a;
--InvExc_I_uid33_fpArccosXTest(LOGICAL,32)@0
InvExc_I_uid33_fpArccosXTest_a <= exc_I_uid29_fpArccosXTest_q;
InvExc_I_uid33_fpArccosXTest_q <= not InvExc_I_uid33_fpArccosXTest_a;
--expXIsZero_uid24_fpArccosXTest(LOGICAL,23)@0
expXIsZero_uid24_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsZero_uid24_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid24_fpArccosXTest_q <= "1" when expXIsZero_uid24_fpArccosXTest_a = expXIsZero_uid24_fpArccosXTest_b else "0";
--InvExpXIsZero_uid34_fpArccosXTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpArccosXTest_a <= expXIsZero_uid24_fpArccosXTest_q;
InvExpXIsZero_uid34_fpArccosXTest_q <= not InvExpXIsZero_uid34_fpArccosXTest_a;
--exc_R_uid35_fpArccosXTest(LOGICAL,34)@0
exc_R_uid35_fpArccosXTest_a <= InvExpXIsZero_uid34_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_b <= InvExc_I_uid33_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_c <= InvExc_N_uid32_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_q <= exc_R_uid35_fpArccosXTest_a and exc_R_uid35_fpArccosXTest_b and exc_R_uid35_fpArccosXTest_c;
--xRegAndOutOfRange_uid126_fpArccosXTest(LOGICAL,125)@0
xRegAndOutOfRange_uid126_fpArccosXTest_a <= exc_R_uid35_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_b <= inputOutOfRange_uid41_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_q <= xRegAndOutOfRange_uid126_fpArccosXTest_a and xRegAndOutOfRange_uid126_fpArccosXTest_b;
--fracXIsZero_uid28_fpArccosXTest(LOGICAL,27)@0
fracXIsZero_uid28_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid28_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid28_fpArccosXTest_q <= "1" when fracXIsZero_uid28_fpArccosXTest_a = fracXIsZero_uid28_fpArccosXTest_b else "0";
--expXIsMax_uid26_fpArccosXTest(LOGICAL,25)@0
expXIsMax_uid26_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsMax_uid26_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid26_fpArccosXTest_q <= "1" when expXIsMax_uid26_fpArccosXTest_a = expXIsMax_uid26_fpArccosXTest_b else "0";
--exc_I_uid29_fpArccosXTest(LOGICAL,28)@0
exc_I_uid29_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_b <= fracXIsZero_uid28_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_q <= exc_I_uid29_fpArccosXTest_a and exc_I_uid29_fpArccosXTest_b;
--InvFracXIsZero_uid30_fpArccosXTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpArccosXTest_a <= fracXIsZero_uid28_fpArccosXTest_q;
InvFracXIsZero_uid30_fpArccosXTest_q <= not InvFracXIsZero_uid30_fpArccosXTest_a;
--exc_N_uid31_fpArccosXTest(LOGICAL,30)@0
exc_N_uid31_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_b <= InvFracXIsZero_uid30_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_q <= exc_N_uid31_fpArccosXTest_a and exc_N_uid31_fpArccosXTest_b;
--excRNaN_uid127_fpArccosXTest(LOGICAL,126)@0
excRNaN_uid127_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_b <= exc_I_uid29_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_c <= xRegAndOutOfRange_uid126_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_q <= excRNaN_uid127_fpArccosXTest_a or excRNaN_uid127_fpArccosXTest_b or excRNaN_uid127_fpArccosXTest_c;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg(DELAY,1225)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid127_fpArccosXTest_q, xout => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem(DUALMEM,1226)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia
);
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid128_fpArccosXTest(BITJOIN,127)@40
excSelBits_uid128_fpArccosXTest_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0(REG,498)@40
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= excSelBits_uid128_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid129_fpArccosXTest(LOOKUP,128)@41
outMuxSelEnc_uid129_fpArccosXTest: PROCESS (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid129_fpArccosXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid129_fpArccosXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid129_fpArccosXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid129_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1(REG,591)@41
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= outMuxSelEnc_uid129_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid131_fpArccosXTest(MUX,130)@42
expRPostExc_uid131_fpArccosXTest_s <= reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q;
expRPostExc_uid131_fpArccosXTest: PROCESS (expRPostExc_uid131_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRCalc_uid125_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid131_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid131_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid131_fpArccosXTest_q <= expRCalc_uid125_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid131_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid119_fpArccosXTest(BITSELECT,118)@42
piF_uid119_fpArccosXTest_in <= pi_uid85_fpArccosXTest_q(26 downto 0);
piF_uid119_fpArccosXTest_b <= piF_uid119_fpArccosXTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor(LOGICAL,1365)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a or ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena(REG,1366)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd(LOGICAL,1367)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid120_fpArccosXTest(BITSELECT,119)@13
Path2ResFP22dto0_uid120_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(22 downto 0);
Path2ResFP22dto0_uid120_fpArccosXTest_b <= Path2ResFP22dto0_uid120_fpArccosXTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg(DELAY,1355)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid120_fpArccosXTest_b, xout => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem(DUALMEM,1356)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3(REG,588)@41
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid121_fpArccosXTest(BITSELECT,120)@41
Path1ResFP22dto0_uid121_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(22 downto 0);
Path1ResFP22dto0_uid121_fpArccosXTest_b <= Path1ResFP22dto0_uid121_fpArccosXTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2(REG,587)@41
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= Path1ResFP22dto0_uid121_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid122_fpArccosXTest(MUX,121)@42
fracRCalc_uid122_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
fracRCalc_uid122_fpArccosXTest: PROCESS (fracRCalc_uid122_fpArccosXTest_s, en, reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q, reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q, piF_uid119_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q)
BEGIN
CASE fracRCalc_uid122_fpArccosXTest_s IS
WHEN "00" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q;
WHEN "01" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q;
WHEN "10" => fracRCalc_uid122_fpArccosXTest_q <= piF_uid119_fpArccosXTest_b;
WHEN "11" => fracRCalc_uid122_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN OTHERS => fracRCalc_uid122_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b(DELAY,706)@41
ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid129_fpArccosXTest_q, xout => ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid130_fpArccosXTest(MUX,129)@42
fracRPostExc_uid130_fpArccosXTest_s <= ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q;
fracRPostExc_uid130_fpArccosXTest: PROCESS (fracRPostExc_uid130_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracRCalc_uid122_fpArccosXTest_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid130_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid130_fpArccosXTest_q <= fracRCalc_uid122_fpArccosXTest_q;
WHEN "10" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid130_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid130_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid132_fpArccosXTest(BITJOIN,131)@42
sR_uid132_fpArccosXTest_q <= GND_q & expRPostExc_uid131_fpArccosXTest_q & fracRPostExc_uid130_fpArccosXTest_q;
--xOut(GPOUT,4)@42
q <= sR_uid132_fpArccosXTest_q;
end normal;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/dp_lnlut9.vhd | 10 | 142018 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNLUT9.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnlut9 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (12 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END dp_lnlut9;
ARCHITECTURE rtl OF dp_lnlut9 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" =>
inv <= conv_std_logic_vector(2048,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
WHEN "000000001" =>
inv <= conv_std_logic_vector(4089,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12608028,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166435551,28);
logexp <= conv_std_logic_vector(1013,11);
WHEN "000000010" =>
inv <= conv_std_logic_vector(4081,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14737805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3321276,28);
logexp <= conv_std_logic_vector(1014,11);
WHEN "000000011" =>
inv <= conv_std_logic_vector(4073,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7407998,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148040387,28);
logexp <= conv_std_logic_vector(1015,11);
WHEN "000000100" =>
inv <= conv_std_logic_vector(4065,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15852272,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51070306,28);
logexp <= conv_std_logic_vector(1015,11);
WHEN "000000101" =>
inv <= conv_std_logic_vector(4057,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3767982,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94668708,28);
logexp <= conv_std_logic_vector(1016,11);
WHEN "000000110" =>
inv <= conv_std_logic_vector(4049,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8006786,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237055061,28);
logexp <= conv_std_logic_vector(1016,11);
WHEN "000000111" =>
inv <= conv_std_logic_vector(4041,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12253974,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192188802,28);
logexp <= conv_std_logic_vector(1016,11);
WHEN "000001000" =>
inv <= conv_std_logic_vector(4033,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16509579,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20710393,28);
logexp <= conv_std_logic_vector(1016,11);
WHEN "000001001" =>
inv <= conv_std_logic_vector(4026,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1731473,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180827014,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001010" =>
inv <= conv_std_logic_vector(4018,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3867211,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(126637664,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001011" =>
inv <= conv_std_logic_vector(4010,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6007205,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228245542,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001100" =>
inv <= conv_std_logic_vector(4003,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7883206,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5368567,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001101" =>
inv <= conv_std_logic_vector(3995,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10031227,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104563152,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001110" =>
inv <= conv_std_logic_vector(3987,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12183554,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132223343,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001111" =>
inv <= conv_std_logic_vector(3980,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14070386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93820959,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000010000" =>
inv <= conv_std_logic_vector(3972,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16230833,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108537941,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000010001" =>
inv <= conv_std_logic_vector(3965,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(673790,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140554826,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010010" =>
inv <= conv_std_logic_vector(3957,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1758104,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(208459132,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010011" =>
inv <= conv_std_logic_vector(3950,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2708679,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147574307,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010100" =>
inv <= conv_std_logic_vector(3943,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3660940,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102190772,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010101" =>
inv <= conv_std_logic_vector(3935,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4751310,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(193668840,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010110" =>
inv <= conv_std_logic_vector(3928,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5707204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201576161,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010111" =>
inv <= conv_std_logic_vector(3920,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6801743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47496037,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011000" =>
inv <= conv_std_logic_vector(3913,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7761298,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63049717,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011001" =>
inv <= conv_std_logic_vector(3906,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8722571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103870568,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011010" =>
inv <= conv_std_logic_vector(3899,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9685568,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213866899,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011011" =>
inv <= conv_std_logic_vector(3891,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10788256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148111271,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011100" =>
inv <= conv_std_logic_vector(3884,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11754969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190364328,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011101" =>
inv <= conv_std_logic_vector(3877,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12723426,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191372810,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011110" =>
inv <= conv_std_logic_vector(3870,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13693633,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232417040,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011111" =>
inv <= conv_std_logic_vector(3863,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14665597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135531172,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000100000" =>
inv <= conv_std_logic_vector(3856,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15639324,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(440444,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000100001" =>
inv <= conv_std_logic_vector(3848,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16754321,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28021513,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000100010" =>
inv <= conv_std_logic_vector(3841,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(477315,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103375890,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000100011" =>
inv <= conv_std_logic_vector(3834,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(966969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207463933,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000100100" =>
inv <= conv_std_logic_vector(3827,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1457518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261454332,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000100101" =>
inv <= conv_std_logic_vector(3820,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1948966,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71112978,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000100110" =>
inv <= conv_std_logic_vector(3814,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2370924,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27626077,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000100111" =>
inv <= conv_std_logic_vector(3807,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2864048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7790664,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101000" =>
inv <= conv_std_logic_vector(3800,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3358079,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135806794,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101001" =>
inv <= conv_std_logic_vector(3793,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3853021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236303861,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101010" =>
inv <= conv_std_logic_vector(3786,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4348878,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138889654,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101011" =>
inv <= conv_std_logic_vector(3779,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845652,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215058204,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101100" =>
inv <= conv_std_logic_vector(3772,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5343348,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36049681,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101101" =>
inv <= conv_std_logic_vector(3766,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5770679,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(216749821,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101110" =>
inv <= conv_std_logic_vector(3759,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6270094,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202231188,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101111" =>
inv <= conv_std_logic_vector(3752,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6770440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(154557048,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110000" =>
inv <= conv_std_logic_vector(3745,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7271720,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201681452,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110001" =>
inv <= conv_std_logic_vector(3739,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7702135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212518450,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110010" =>
inv <= conv_std_logic_vector(3732,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8205160,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130192328,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110011" =>
inv <= conv_std_logic_vector(3725,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8709129,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153765892,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110100" =>
inv <= conv_std_logic_vector(3719,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9141857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115454106,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110101" =>
inv <= conv_std_logic_vector(3712,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9647589,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(223955336,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110110" =>
inv <= conv_std_logic_vector(3706,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10081834,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(106871151,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110111" =>
inv <= conv_std_logic_vector(3699,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10589342,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134545541,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111000" =>
inv <= conv_std_logic_vector(3693,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11025114,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118400992,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111001" =>
inv <= conv_std_logic_vector(3686,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11534410,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203065005,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111010" =>
inv <= conv_std_logic_vector(3680,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11971720,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229464861,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111011" =>
inv <= conv_std_logic_vector(3673,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12482818,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7696520,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111100" =>
inv <= conv_std_logic_vector(3667,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12921677,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49003431,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111101" =>
inv <= conv_std_logic_vector(3660,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13434587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267260840,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111110" =>
inv <= conv_std_logic_vector(3654,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13875007,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(58597277,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111111" =>
inv <= conv_std_logic_vector(3648,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14316150,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59000478,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000000" =>
inv <= conv_std_logic_vector(3641,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14831735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2814011,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000001" =>
inv <= conv_std_logic_vector(3635,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15274454,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104571506,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000010" =>
inv <= conv_std_logic_vector(3629,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15717905,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35857837,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000011" =>
inv <= conv_std_logic_vector(3623,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16162089,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177959810,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000100" =>
inv <= conv_std_logic_vector(3616,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16681235,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165401956,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000101" =>
inv <= conv_std_logic_vector(3610,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(174901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50275830,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001000110" =>
inv <= conv_std_logic_vector(3604,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(398163,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(88951577,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001000111" =>
inv <= conv_std_logic_vector(3598,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(621797,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127737931,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001000" =>
inv <= conv_std_logic_vector(3592,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(845804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231522955,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001001" =>
inv <= conv_std_logic_vector(3585,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1107620,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(57821111,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001010" =>
inv <= conv_std_logic_vector(3579,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1332440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156464157,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001011" =>
inv <= conv_std_logic_vector(3573,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1557638,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44535294,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001100" =>
inv <= conv_std_logic_vector(3567,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1783214,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62397887,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001101" =>
inv <= conv_std_logic_vector(3561,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2009170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15263403,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001110" =>
inv <= conv_std_logic_vector(3555,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2235506,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246944822,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001111" =>
inv <= conv_std_logic_vector(3549,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2462226,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29255593,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010000" =>
inv <= conv_std_logic_vector(3543,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2689328,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246376003,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010001" =>
inv <= conv_std_logic_vector(3537,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2916816,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173639564,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010010" =>
inv <= conv_std_logic_vector(3531,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3144690,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161899610,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010011" =>
inv <= conv_std_logic_vector(3525,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3372952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26928617,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010100" =>
inv <= conv_std_logic_vector(3519,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3601602,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123172243,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010101" =>
inv <= conv_std_logic_vector(3513,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3830643,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1584354,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010110" =>
inv <= conv_std_logic_vector(3507,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4060075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20252153,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010111" =>
inv <= conv_std_logic_vector(3502,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4251568,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137854980,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011000" =>
inv <= conv_std_logic_vector(3496,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4481721,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231322588,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011001" =>
inv <= conv_std_logic_vector(3490,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4712270,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147480442,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011010" =>
inv <= conv_std_logic_vector(3484,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4943215,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251536037,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011011" =>
inv <= conv_std_logic_vector(3478,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5174559,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105278949,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011100" =>
inv <= conv_std_logic_vector(3473,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5367650,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181375864,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011101" =>
inv <= conv_std_logic_vector(3467,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5599727,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133308340,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011110" =>
inv <= conv_std_logic_vector(3461,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5832206,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80096944,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011111" =>
inv <= conv_std_logic_vector(3455,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6065088,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127763081,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100000" =>
inv <= conv_std_logic_vector(3450,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6259466,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27642512,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100001" =>
inv <= conv_std_logic_vector(3444,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6493091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120806774,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100010" =>
inv <= conv_std_logic_vector(3438,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6727124,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44281139,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100011" =>
inv <= conv_std_logic_vector(3433,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6922463,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171170237,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100100" =>
inv <= conv_std_logic_vector(3427,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7157246,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(240302137,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100101" =>
inv <= conv_std_logic_vector(3422,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7353213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222094360,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100110" =>
inv <= conv_std_logic_vector(3416,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7588752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122671437,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100111" =>
inv <= conv_std_logic_vector(3411,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7785350,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(239607246,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101000" =>
inv <= conv_std_logic_vector(3405,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8021649,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206841234,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101001" =>
inv <= conv_std_logic_vector(3399,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8258365,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(107795018,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101010" =>
inv <= conv_std_logic_vector(3394,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8455947,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226201607,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101011" =>
inv <= conv_std_logic_vector(3388,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8693431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94327085,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101100" =>
inv <= conv_std_logic_vector(3383,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8891655,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206124156,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101101" =>
inv <= conv_std_logic_vector(3378,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9090173,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99984141,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101110" =>
inv <= conv_std_logic_vector(3372,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9328782,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195833281,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101111" =>
inv <= conv_std_logic_vector(3367,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9527948,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110283065,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110000" =>
inv <= conv_std_logic_vector(3361,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9767338,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(282511,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110001" =>
inv <= conv_std_logic_vector(3356,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9967156,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1157748,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110010" =>
inv <= conv_std_logic_vector(3351,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10167271,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250247631,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110011" =>
inv <= conv_std_logic_vector(3345,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10407805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150148144,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110100" =>
inv <= conv_std_logic_vector(3340,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10608580,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15841264,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110101" =>
inv <= conv_std_logic_vector(3335,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10809655,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92492368,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110110" =>
inv <= conv_std_logic_vector(3329,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11051343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267282110,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110111" =>
inv <= conv_std_logic_vector(3324,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11253084,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51811246,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111000" =>
inv <= conv_std_logic_vector(3319,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11455128,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21159361,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111001" =>
inv <= conv_std_logic_vector(3314,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11657476,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152694737,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111010" =>
inv <= conv_std_logic_vector(3308,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11900698,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34843865,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111011" =>
inv <= conv_std_logic_vector(3303,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12103719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266488285,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111100" =>
inv <= conv_std_logic_vector(3298,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12307049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112230017,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111101" =>
inv <= conv_std_logic_vector(3293,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12510687,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91030082,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111110" =>
inv <= conv_std_logic_vector(3288,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12714634,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186120630,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111111" =>
inv <= conv_std_logic_vector(3282,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12959781,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79635368,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000000" =>
inv <= conv_std_logic_vector(3277,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13164412,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194678646,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000001" =>
inv <= conv_std_logic_vector(3272,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13369356,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165362770,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000010" =>
inv <= conv_std_logic_vector(3267,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13574613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248228452,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000011" =>
inv <= conv_std_logic_vector(3262,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13780185,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164124274,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000100" =>
inv <= conv_std_logic_vector(3257,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13986072,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171955743,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000101" =>
inv <= conv_std_logic_vector(3252,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14192275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263386193,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000110" =>
inv <= conv_std_logic_vector(3247,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14398796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162844158,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000111" =>
inv <= conv_std_logic_vector(3242,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14605635,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132837122,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001000" =>
inv <= conv_std_logic_vector(3237,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14812793,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168652610,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001001" =>
inv <= conv_std_logic_vector(3232,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15020271,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266801170,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001010" =>
inv <= conv_std_logic_vector(3227,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15228071,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156588484,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001011" =>
inv <= conv_std_logic_vector(3222,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15436193,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105429361,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001100" =>
inv <= conv_std_logic_vector(3217,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15644638,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113549080,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001101" =>
inv <= conv_std_logic_vector(3212,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15853407,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182426590,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001110" =>
inv <= conv_std_logic_vector(3207,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16062502,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(46366848,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001111" =>
inv <= conv_std_logic_vector(3202,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16271922,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246250548,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010010000" =>
inv <= conv_std_logic_vector(3197,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16481670,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250493842,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010010001" =>
inv <= conv_std_logic_vector(3193,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16649705,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179677631,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010010010" =>
inv <= conv_std_logic_vector(3188,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(41414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182297714,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010010011" =>
inv <= conv_std_logic_vector(3183,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(146749,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160926493,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010010100" =>
inv <= conv_std_logic_vector(3178,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(252250,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30832263,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010010101" =>
inv <= conv_std_logic_vector(3173,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(357916,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(200433438,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010010110" =>
inv <= conv_std_logic_vector(3168,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(463750,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5068900,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010010111" =>
inv <= conv_std_logic_vector(3164,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(548536,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260761497,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011000" =>
inv <= conv_std_logic_vector(3159,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(654671,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140824337,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011001" =>
inv <= conv_std_logic_vector(3154,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(760974,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53287185,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011010" =>
inv <= conv_std_logic_vector(3149,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(867445,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141350373,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011011" =>
inv <= conv_std_logic_vector(3145,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(952744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102039527,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011100" =>
inv <= conv_std_logic_vector(3140,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1059520,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171297819,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011101" =>
inv <= conv_std_logic_vector(3135,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1166467,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15456691,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011110" =>
inv <= conv_std_logic_vector(3131,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1252147,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19951762,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011111" =>
inv <= conv_std_logic_vector(3126,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1359401,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41610452,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100000" =>
inv <= conv_std_logic_vector(3121,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1466826,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248224675,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100001" =>
inv <= conv_std_logic_vector(3117,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1552891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141314514,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100010" =>
inv <= conv_std_logic_vector(3112,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1660627,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194757369,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100011" =>
inv <= conv_std_logic_vector(3107,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1768537,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43450957,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100100" =>
inv <= conv_std_logic_vector(3103,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1854989,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219219906,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100101" =>
inv <= conv_std_logic_vector(3098,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1963212,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131015724,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100110" =>
inv <= conv_std_logic_vector(3094,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2049916,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123155162,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100111" =>
inv <= conv_std_logic_vector(3089,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2158454,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50751187,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101000" =>
inv <= conv_std_logic_vector(3085,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2245410,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252626322,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101001" =>
inv <= conv_std_logic_vector(3080,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2354265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153008713,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101010" =>
inv <= conv_std_logic_vector(3076,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2441476,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156128968,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101011" =>
inv <= conv_std_logic_vector(3071,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2550649,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(259057771,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101100" =>
inv <= conv_std_logic_vector(3067,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2638116,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195294519,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101101" =>
inv <= conv_std_logic_vector(3062,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2747610,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198048260,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101110" =>
inv <= conv_std_logic_vector(3058,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2835334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202805005,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101111" =>
inv <= conv_std_logic_vector(3053,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2945151,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75538772,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110000" =>
inv <= conv_std_logic_vector(3049,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3033134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19357354,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110001" =>
inv <= conv_std_logic_vector(3044,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3143275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5155285,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110010" =>
inv <= conv_std_logic_vector(3040,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3231518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30629091,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110011" =>
inv <= conv_std_logic_vector(3035,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3341985,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108686704,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110100" =>
inv <= conv_std_logic_vector(3031,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3430490,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93632684,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110101" =>
inv <= conv_std_logic_vector(3027,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3519112,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45511961,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110110" =>
inv <= conv_std_logic_vector(3022,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3630054,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(73684067,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110111" =>
inv <= conv_std_logic_vector(3018,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3718940,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53706357,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111000" =>
inv <= conv_std_logic_vector(3014,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3807944,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3094116,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111001" =>
inv <= conv_std_logic_vector(3009,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3919365,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(8048359,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111010" =>
inv <= conv_std_logic_vector(3005,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4008635,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62108895,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111011" =>
inv <= conv_std_logic_vector(3001,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4098024,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91490091,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111100" =>
inv <= conv_std_logic_vector(2996,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209928,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114206619,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111101" =>
inv <= conv_std_logic_vector(2992,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4299586,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64350406,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111110" =>
inv <= conv_std_logic_vector(2988,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4389363,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267789889,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111111" =>
inv <= conv_std_logic_vector(2984,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4479262,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5480265,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000000" =>
inv <= conv_std_logic_vector(2979,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4591804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43802136,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000001" =>
inv <= conv_std_logic_vector(2975,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4681973,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(258711462,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000010" =>
inv <= conv_std_logic_vector(2971,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4772265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(22193356,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000011" =>
inv <= conv_std_logic_vector(2967,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4862677,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227303994,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000100" =>
inv <= conv_std_logic_vector(2963,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4953212,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156841963,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000101" =>
inv <= conv_std_logic_vector(2958,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5066553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(8978848,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000110" =>
inv <= conv_std_logic_vector(2954,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5157363,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112226691,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000111" =>
inv <= conv_std_logic_vector(2950,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5248296,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228718953,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001000" =>
inv <= conv_std_logic_vector(2946,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5339353,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179656048,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001001" =>
inv <= conv_std_logic_vector(2942,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5430534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55039221,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001010" =>
inv <= conv_std_logic_vector(2938,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5521838,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213672522,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001011" =>
inv <= conv_std_logic_vector(2934,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5613267,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(209422987,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001100" =>
inv <= conv_std_logic_vector(2929,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5727729,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122280556,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001101" =>
inv <= conv_std_logic_vector(2925,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5819439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152340981,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001110" =>
inv <= conv_std_logic_vector(2921,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5911275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48556746,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001111" =>
inv <= conv_std_logic_vector(2917,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6003236,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171693667,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010000" =>
inv <= conv_std_logic_vector(2913,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6095324,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77591273,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010001" =>
inv <= conv_std_logic_vector(2909,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6187538,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127777649,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010010" =>
inv <= conv_std_logic_vector(2905,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6279879,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147294249,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010011" =>
inv <= conv_std_logic_vector(2901,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6372347,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230004385,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010100" =>
inv <= conv_std_logic_vector(2897,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6464943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201724446,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010101" =>
inv <= conv_std_logic_vector(2893,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6557667,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(157096962,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010110" =>
inv <= conv_std_logic_vector(2889,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6650519,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191157304,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010111" =>
inv <= conv_std_logic_vector(2885,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6743500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130900404,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011000" =>
inv <= conv_std_logic_vector(2881,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6836610,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72153870,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011001" =>
inv <= conv_std_logic_vector(2877,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6929849,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111144728,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011010" =>
inv <= conv_std_logic_vector(2873,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7023218,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76066192,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011011" =>
inv <= conv_std_logic_vector(2869,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7116717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63950809,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011100" =>
inv <= conv_std_logic_vector(2865,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7210346,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172237270,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011101" =>
inv <= conv_std_logic_vector(2862,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7280654,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139653305,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011110" =>
inv <= conv_std_logic_vector(2858,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7374513,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(23245886,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011111" =>
inv <= conv_std_logic_vector(2854,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7468503,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28873967,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100000" =>
inv <= conv_std_logic_vector(2850,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7562624,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255519588,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100001" =>
inv <= conv_std_logic_vector(2846,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7656878,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265710940,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100010" =>
inv <= conv_std_logic_vector(2842,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7751265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159266526,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100011" =>
inv <= conv_std_logic_vector(2838,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7845785,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36426622,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100100" =>
inv <= conv_std_logic_vector(2834,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7940437,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266291107,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100101" =>
inv <= conv_std_logic_vector(2831,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8011515,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93413946,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100110" =>
inv <= conv_std_logic_vector(2827,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8106402,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110277380,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100111" =>
inv <= conv_std_logic_vector(2823,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8201423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222008092,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101000" =>
inv <= conv_std_logic_vector(2819,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8296579,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(262447083,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101001" =>
inv <= conv_std_logic_vector(2815,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8391871,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(65871042,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101010" =>
inv <= conv_std_logic_vector(2812,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8463428,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160477028,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101011" =>
inv <= conv_std_logic_vector(2808,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8558957,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66030540,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101100" =>
inv <= conv_std_logic_vector(2804,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8654622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19294193,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101101" =>
inv <= conv_std_logic_vector(2800,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8750423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124636155,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101110" =>
inv <= conv_std_logic_vector(2797,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8822364,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98044902,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101111" =>
inv <= conv_std_logic_vector(2793,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8918405,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(185136678,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110000" =>
inv <= conv_std_logic_vector(2789,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9014584,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176764031,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110001" =>
inv <= conv_std_logic_vector(2786,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9086809,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(121288912,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110010" =>
inv <= conv_std_logic_vector(2782,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9183230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67117648,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110011" =>
inv <= conv_std_logic_vector(2778,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9279789,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210248932,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110100" =>
inv <= conv_std_logic_vector(2775,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9352300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192854718,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110101" =>
inv <= conv_std_logic_vector(2771,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9449104,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(269037,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110110" =>
inv <= conv_std_logic_vector(2767,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9546047,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32810921,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110111" =>
inv <= conv_std_logic_vector(2764,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9618846,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127667797,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111000" =>
inv <= conv_std_logic_vector(2760,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9716035,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77607514,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111001" =>
inv <= conv_std_logic_vector(2756,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9813365,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15613650,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111010" =>
inv <= conv_std_logic_vector(2753,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9886455,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35776871,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111011" =>
inv <= conv_std_logic_vector(2749,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9984032,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150556503,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111100" =>
inv <= conv_std_logic_vector(2745,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10081752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19947644,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111101" =>
inv <= conv_std_logic_vector(2742,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10155135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54345836,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111110" =>
inv <= conv_std_logic_vector(2738,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10253104,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97812156,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111111" =>
inv <= conv_std_logic_vector(2735,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10326675,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55696655,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000000" =>
inv <= conv_std_logic_vector(2731,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10424895,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79654305,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000001" =>
inv <= conv_std_logic_vector(2728,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10498654,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219479460,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000010" =>
inv <= conv_std_logic_vector(2724,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10597127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32989146,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000011" =>
inv <= conv_std_logic_vector(2721,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10671076,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78331980,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000100" =>
inv <= conv_std_logic_vector(2717,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10769802,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29997091,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000101" =>
inv <= conv_std_logic_vector(2714,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10843941,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243319683,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000110" =>
inv <= conv_std_logic_vector(2710,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10942922,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147572067,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000111" =>
inv <= conv_std_logic_vector(2707,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11017253,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256500550,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001000" =>
inv <= conv_std_logic_vector(2703,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11116490,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198934815,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001001" =>
inv <= conv_std_logic_vector(2700,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11191014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201586837,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001010" =>
inv <= conv_std_logic_vector(2696,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11290509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2117744,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001011" =>
inv <= conv_std_logic_vector(2693,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11365226,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167123833,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001100" =>
inv <= conv_std_logic_vector(2689,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11464979,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(185321336,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001101" =>
inv <= conv_std_logic_vector(2686,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11539891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246540176,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001110" =>
inv <= conv_std_logic_vector(2682,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11639905,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(39481193,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001111" =>
inv <= conv_std_logic_vector(2679,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11715013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1327916,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010000" =>
inv <= conv_std_logic_vector(2675,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11815287,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202673946,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010001" =>
inv <= conv_std_logic_vector(2672,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11890592,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71706890,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010010" =>
inv <= conv_std_logic_vector(2669,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11965981,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100723928,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010011" =>
inv <= conv_std_logic_vector(2665,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12066632,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29193386,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010100" =>
inv <= conv_std_logic_vector(2662,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12142219,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93571958,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010101" =>
inv <= conv_std_logic_vector(2658,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12243134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255701348,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010110" =>
inv <= conv_std_logic_vector(2655,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12318921,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98863551,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010111" =>
inv <= conv_std_logic_vector(2652,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12394793,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125312048,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011000" =>
inv <= conv_std_logic_vector(2648,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12496089,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237443793,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011001" =>
inv <= conv_std_logic_vector(2645,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12572162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178518688,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011010" =>
inv <= conv_std_logic_vector(2642,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12648321,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(208688605,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011011" =>
inv <= conv_std_logic_vector(2638,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12750001,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(239940349,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011100" =>
inv <= conv_std_logic_vector(2635,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12826363,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56746753,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011101" =>
inv <= conv_std_logic_vector(2632,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12902811,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138879938,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011110" =>
inv <= conv_std_logic_vector(2629,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12979347,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2730614,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011111" =>
inv <= conv_std_logic_vector(2625,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13081530,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81091197,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100000" =>
inv <= conv_std_logic_vector(2622,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13158270,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1684866,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100001" =>
inv <= conv_std_logic_vector(2619,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13235097,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151292526,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100010" =>
inv <= conv_std_logic_vector(2615,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13337671,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84646293,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100011" =>
inv <= conv_std_logic_vector(2612,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13414704,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173861808,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100100" =>
inv <= conv_std_logic_vector(2609,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13491826,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136139682,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100101" =>
inv <= conv_std_logic_vector(2606,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13569037,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26161775,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100110" =>
inv <= conv_std_logic_vector(2602,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13672122,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249732568,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100111" =>
inv <= conv_std_logic_vector(2599,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749541,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95394098,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101000" =>
inv <= conv_std_logic_vector(2596,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13827049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52442312,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101001" =>
inv <= conv_std_logic_vector(2593,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13904646,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176384205,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101010" =>
inv <= conv_std_logic_vector(2590,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13982333,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254484090,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101011" =>
inv <= conv_std_logic_vector(2586,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14086057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26027470,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101100" =>
inv <= conv_std_logic_vector(2583,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14163954,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214862414,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101101" =>
inv <= conv_std_logic_vector(2580,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14241943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(8054063,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101110" =>
inv <= conv_std_logic_vector(2577,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14320021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267454282,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101111" =>
inv <= conv_std_logic_vector(2574,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14398191,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244499796,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110000" =>
inv <= conv_std_logic_vector(2571,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14476452,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264567670,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110001" =>
inv <= conv_std_logic_vector(2567,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14580943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69299566,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110010" =>
inv <= conv_std_logic_vector(2564,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14659417,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233357662,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110011" =>
inv <= conv_std_logic_vector(2561,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14737984,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94818262,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110100" =>
inv <= conv_std_logic_vector(2558,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14816642,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248364916,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110101" =>
inv <= conv_std_logic_vector(2555,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14895393,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215142880,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110110" =>
inv <= conv_std_logic_vector(2552,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14974237,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53372798,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110111" =>
inv <= conv_std_logic_vector(2549,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15053173,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(89916221,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111000" =>
inv <= conv_std_logic_vector(2546,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15132202,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114970198,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111001" =>
inv <= conv_std_logic_vector(2543,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15211324,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187374614,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111010" =>
inv <= conv_std_logic_vector(2539,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15316966,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101744986,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111011" =>
inv <= conv_std_logic_vector(2536,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15396306,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246192396,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111100" =>
inv <= conv_std_logic_vector(2533,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15475741,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98762703,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111101" =>
inv <= conv_std_logic_vector(2530,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15555269,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256076770,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111110" =>
inv <= conv_std_logic_vector(2527,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15634892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241226312,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111111" =>
inv <= conv_std_logic_vector(2524,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15714610,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114387642,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000000" =>
inv <= conv_std_logic_vector(2521,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15794422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204387226,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000001" =>
inv <= conv_std_logic_vector(2518,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15874330,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34960895,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000010" =>
inv <= conv_std_logic_vector(2515,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15954332,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203803056,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000011" =>
inv <= conv_std_logic_vector(2512,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16034430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235084078,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000100" =>
inv <= conv_std_logic_vector(2509,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16114624,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190064071,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000101" =>
inv <= conv_std_logic_vector(2506,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16194914,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130223025,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000110" =>
inv <= conv_std_logic_vector(2503,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16275300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117261858,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000111" =>
inv <= conv_std_logic_vector(2500,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16355782,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213103482,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001000" =>
inv <= conv_std_logic_vector(2497,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16436361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211458404,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001001" =>
inv <= conv_std_logic_vector(2494,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16517037,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(174696720,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001010" =>
inv <= conv_std_logic_vector(2491,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16597810,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165413733,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001011" =>
inv <= conv_std_logic_vector(2488,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16678680,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246431038,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001100" =>
inv <= conv_std_logic_vector(2485,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16759648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212362162,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001101" =>
inv <= conv_std_logic_vector(2482,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(31749,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63242286,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101001110" =>
inv <= conv_std_logic_vector(2479,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(72331,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26152662,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101001111" =>
inv <= conv_std_logic_vector(2476,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(112962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26781090,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010000" =>
inv <= conv_std_logic_vector(2474,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(140076,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213075491,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010001" =>
inv <= conv_std_logic_vector(2471,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(180789,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(258223654,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010010" =>
inv <= conv_std_logic_vector(2468,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(221552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(158206290,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010011" =>
inv <= conv_std_logic_vector(2465,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(262364,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213755501,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010100" =>
inv <= conv_std_logic_vector(2462,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(303226,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188850466,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010101" =>
inv <= conv_std_logic_vector(2459,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(344138,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116024386,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010110" =>
inv <= conv_std_logic_vector(2456,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(385100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27929606,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010111" =>
inv <= conv_std_logic_vector(2453,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(426111,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225773656,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011000" =>
inv <= conv_std_logic_vector(2450,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(467173,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205578013,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011001" =>
inv <= conv_std_logic_vector(2448,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(494576,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87278952,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011010" =>
inv <= conv_std_logic_vector(2445,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(535722,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45542114,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011011" =>
inv <= conv_std_logic_vector(2442,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(576918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142506767,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011100" =>
inv <= conv_std_logic_vector(2439,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(618165,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143076061,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011101" =>
inv <= conv_std_logic_vector(2436,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(659463,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80711705,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011110" =>
inv <= conv_std_logic_vector(2433,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(700811,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257434563,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011111" =>
inv <= conv_std_logic_vector(2431,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(728406,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17672925,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100000" =>
inv <= conv_std_logic_vector(2428,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(769839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220454209,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100001" =>
inv <= conv_std_logic_vector(2425,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(811324,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215622313,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100010" =>
inv <= conv_std_logic_vector(2422,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(852861,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37221475,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100011" =>
inv <= conv_std_logic_vector(2419,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(894448,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256293434,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100100" =>
inv <= conv_std_logic_vector(2417,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(922202,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222525409,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100101" =>
inv <= conv_std_logic_vector(2414,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(963876,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196069656,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100110" =>
inv <= conv_std_logic_vector(2411,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1005602,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(121961634,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100111" =>
inv <= conv_std_logic_vector(2408,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1047380,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34841718,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101000" =>
inv <= conv_std_logic_vector(2405,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1089209,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237915287,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101001" =>
inv <= conv_std_logic_vector(2403,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1117125,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104353094,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101010" =>
inv <= conv_std_logic_vector(2400,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1159042,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63396520,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101011" =>
inv <= conv_std_logic_vector(2397,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1201011,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137556064,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101100" =>
inv <= conv_std_logic_vector(2395,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1229020,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59568237,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101101" =>
inv <= conv_std_logic_vector(2392,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1271077,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(46073956,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101110" =>
inv <= conv_std_logic_vector(2389,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1313186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241992154,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101111" =>
inv <= conv_std_logic_vector(2386,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1355349,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146057517,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110000" =>
inv <= conv_std_logic_vector(2384,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1383487,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116561426,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110001" =>
inv <= conv_std_logic_vector(2381,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1425738,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150565181,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110010" =>
inv <= conv_std_logic_vector(2378,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1468042,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256758677,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110011" =>
inv <= conv_std_logic_vector(2376,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1496275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146872826,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110100" =>
inv <= conv_std_logic_vector(2373,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1538669,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(6283669,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110101" =>
inv <= conv_std_logic_vector(2370,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1581116,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34459956,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110110" =>
inv <= conv_std_logic_vector(2367,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1623616,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267869958,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110111" =>
inv <= conv_std_logic_vector(2365,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1651980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227479388,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111000" =>
inv <= conv_std_logic_vector(2362,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1694571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168535478,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111001" =>
inv <= conv_std_logic_vector(2360,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1722995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146252604,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111010" =>
inv <= conv_std_logic_vector(2357,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1765676,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165723426,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111011" =>
inv <= conv_std_logic_vector(2354,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1808412,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13198653,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111100" =>
inv <= conv_std_logic_vector(2352,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1836932,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162422791,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111101" =>
inv <= conv_std_logic_vector(2349,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1879758,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253404775,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111110" =>
inv <= conv_std_logic_vector(2346,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1922640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3516811,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111111" =>
inv <= conv_std_logic_vector(2344,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1951257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232810820,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000000" =>
inv <= conv_std_logic_vector(2341,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1994230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124778707,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000001" =>
inv <= conv_std_logic_vector(2338,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2037258,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44895651,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000010" =>
inv <= conv_std_logic_vector(2336,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2065973,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264640088,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000011" =>
inv <= conv_std_logic_vector(2333,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2109093,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226677719,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000100" =>
inv <= conv_std_logic_vector(2331,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2137871,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62314345,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000101" =>
inv <= conv_std_logic_vector(2328,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2181083,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172467092,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000110" =>
inv <= conv_std_logic_vector(2326,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2209922,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231891008,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000111" =>
inv <= conv_std_logic_vector(2323,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2253228,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60167664,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001000" =>
inv <= conv_std_logic_vector(2320,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2296589,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146717848,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001001" =>
inv <= conv_std_logic_vector(2318,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2325528,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68833327,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001010" =>
inv <= conv_std_logic_vector(2315,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2368983,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45955088,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001011" =>
inv <= conv_std_logic_vector(2313,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2397984,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110242438,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001100" =>
inv <= conv_std_logic_vector(2310,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2441533,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86625006,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001101" =>
inv <= conv_std_logic_vector(2308,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2470597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97343330,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001110" =>
inv <= conv_std_logic_vector(2305,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2514240,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182382776,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001111" =>
inv <= conv_std_logic_vector(2303,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2543367,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212699904,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010000" =>
inv <= conv_std_logic_vector(2300,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2587105,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248069835,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010001" =>
inv <= conv_std_logic_vector(2297,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2630901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(38353874,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010010" =>
inv <= conv_std_logic_vector(2295,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2660129,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199724201,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010011" =>
inv <= conv_std_logic_vector(2292,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2704020,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118011763,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010100" =>
inv <= conv_std_logic_vector(2290,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2733312,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(223026379,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010101" =>
inv <= conv_std_logic_vector(2287,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2777299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112874067,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010110" =>
inv <= conv_std_logic_vector(2285,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2806655,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236438996,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010111" =>
inv <= conv_std_logic_vector(2282,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2850738,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210574529,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011000" =>
inv <= conv_std_logic_vector(2280,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2880159,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159652923,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011001" =>
inv <= conv_std_logic_vector(2278,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2909606,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60159477,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011010" =>
inv <= conv_std_logic_vector(2275,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2953824,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182033526,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011011" =>
inv <= conv_std_logic_vector(2273,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2983336,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14447396,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011100" =>
inv <= conv_std_logic_vector(2270,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3027651,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225760651,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011101" =>
inv <= conv_std_logic_vector(2268,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3057228,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66680404,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011110" =>
inv <= conv_std_logic_vector(2265,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3101641,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214275106,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011111" =>
inv <= conv_std_logic_vector(2263,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3131283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140806814,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100000" =>
inv <= conv_std_logic_vector(2260,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3175795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72289811,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100001" =>
inv <= conv_std_logic_vector(2258,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3205502,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162051533,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100010" =>
inv <= conv_std_logic_vector(2256,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3235236,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70518411,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100011" =>
inv <= conv_std_logic_vector(2253,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3279886,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56927398,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100100" =>
inv <= conv_std_logic_vector(2251,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3309685,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238158383,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100101" =>
inv <= conv_std_logic_vector(2248,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3354435,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21682069,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100110" =>
inv <= conv_std_logic_vector(2246,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3384301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17671725,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100111" =>
inv <= conv_std_logic_vector(2243,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3429149,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253874147,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101000" =>
inv <= conv_std_logic_vector(2241,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3459082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144015594,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101001" =>
inv <= conv_std_logic_vector(2239,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3489041,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228915285,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101010" =>
inv <= conv_std_logic_vector(2236,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3534031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11297232,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101011" =>
inv <= conv_std_logic_vector(2234,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3564057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102394521,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101100" =>
inv <= conv_std_logic_vector(2232,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3594110,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164843479,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101101" =>
inv <= conv_std_logic_vector(2229,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3639240,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266678657,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101110" =>
inv <= conv_std_logic_vector(2227,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3669361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179992124,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101111" =>
inv <= conv_std_logic_vector(2224,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3714593,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119109352,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110000" =>
inv <= conv_std_logic_vector(2222,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3744781,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233164434,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110001" =>
inv <= conv_std_logic_vector(2220,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3774997,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128320487,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110010" =>
inv <= conv_std_logic_vector(2217,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3820371,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260492078,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110011" =>
inv <= conv_std_logic_vector(2215,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3850655,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202899023,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110100" =>
inv <= conv_std_logic_vector(2213,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3880966,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241038144,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110101" =>
inv <= conv_std_logic_vector(2210,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3926485,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3486646,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110110" =>
inv <= conv_std_logic_vector(2208,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3956864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204914613,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110111" =>
inv <= conv_std_logic_vector(2206,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3987272,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11839650,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111000" =>
inv <= conv_std_logic_vector(2203,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4032934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186275213,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111001" =>
inv <= conv_std_logic_vector(2201,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4063411,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5198727,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111010" =>
inv <= conv_std_logic_vector(2199,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4093915,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13571695,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111011" =>
inv <= conv_std_logic_vector(2196,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4139723,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41866951,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111100" =>
inv <= conv_std_logic_vector(2194,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4170296,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180504741,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111101" =>
inv <= conv_std_logic_vector(2192,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4200898,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19253907,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111110" =>
inv <= conv_std_logic_vector(2190,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4231527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108649881,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111111" =>
inv <= conv_std_logic_vector(2187,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4277523,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(239373474,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000000" =>
inv <= conv_std_logic_vector(2185,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4308223,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75890782,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000001" =>
inv <= conv_std_logic_vector(2183,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4338950,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211176572,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000010" =>
inv <= conv_std_logic_vector(2180,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4385094,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232816832,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000011" =>
inv <= conv_std_logic_vector(2178,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4415892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236107455,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000100" =>
inv <= conv_std_logic_vector(2176,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4446719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49882053,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000101" =>
inv <= conv_std_logic_vector(2174,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4477573,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(224979561,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000110" =>
inv <= conv_std_logic_vector(2171,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4523909,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21351166,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000111" =>
inv <= conv_std_logic_vector(2169,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4554834,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221595418,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001000" =>
inv <= conv_std_logic_vector(2167,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4585789,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27048959,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001001" =>
inv <= conv_std_logic_vector(2165,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4616771,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257160862,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001010" =>
inv <= conv_std_logic_vector(2163,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4647783,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120806675,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001011" =>
inv <= conv_std_logic_vector(2160,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4694354,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132686548,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001100" =>
inv <= conv_std_logic_vector(2158,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4725437,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(216213494,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001101" =>
inv <= conv_std_logic_vector(2156,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4756549,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251657420,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001110" =>
inv <= conv_std_logic_vector(2154,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4787690,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253378504,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001111" =>
inv <= conv_std_logic_vector(2151,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4834456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190686783,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010000" =>
inv <= conv_std_logic_vector(2149,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4865670,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36971813,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010001" =>
inv <= conv_std_logic_vector(2147,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4896912,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168546215,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010010" =>
inv <= conv_std_logic_vector(2145,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4928184,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63080520,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010011" =>
inv <= conv_std_logic_vector(2143,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4959485,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3592320,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010100" =>
inv <= conv_std_logic_vector(2140,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5006490,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267447830,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010101" =>
inv <= conv_std_logic_vector(2138,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5037864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252750919,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010110" =>
inv <= conv_std_logic_vector(2136,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5069268,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66956194,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010111" =>
inv <= conv_std_logic_vector(2134,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5100700,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261701721,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011000" =>
inv <= conv_std_logic_vector(2132,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5132163,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(46489821,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011001" =>
inv <= conv_std_logic_vector(2130,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5163654,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241477251,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011010" =>
inv <= conv_std_logic_vector(2127,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5210947,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261928568,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011011" =>
inv <= conv_std_logic_vector(2125,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5242513,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205482523,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011100" =>
inv <= conv_std_logic_vector(2123,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5274109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(74671864,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011101" =>
inv <= conv_std_logic_vector(2121,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5305734,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152972013,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011110" =>
inv <= conv_std_logic_vector(2119,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5337389,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187030043,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011111" =>
inv <= conv_std_logic_vector(2117,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5369074,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191971210,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100000" =>
inv <= conv_std_logic_vector(2115,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5400789,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182963660,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100001" =>
inv <= conv_std_logic_vector(2112,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5448418,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(109475927,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100010" =>
inv <= conv_std_logic_vector(2110,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5480208,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132240138,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100011" =>
inv <= conv_std_logic_vector(2108,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5512028,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194484233,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100100" =>
inv <= conv_std_logic_vector(2106,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5543879,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43135919,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100101" =>
inv <= conv_std_logic_vector(2104,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5575759,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230473058,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100110" =>
inv <= conv_std_logic_vector(2102,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5607670,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235075650,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100111" =>
inv <= conv_std_logic_vector(2100,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5639612,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72438727,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101000" =>
inv <= conv_std_logic_vector(2098,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5671584,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26537070,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101001" =>
inv <= conv_std_logic_vector(2096,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5703586,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112954470,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101010" =>
inv <= conv_std_logic_vector(2093,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5751647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55116163,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101011" =>
inv <= conv_std_logic_vector(2091,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5783726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3932676,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101100" =>
inv <= conv_std_logic_vector(2089,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5815835,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139964094,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101101" =>
inv <= conv_std_logic_vector(2087,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5847975,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210560941,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101110" =>
inv <= conv_std_logic_vector(2085,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5880146,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231554600,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101111" =>
inv <= conv_std_logic_vector(2083,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5912348,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218822034,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110000" =>
inv <= conv_std_logic_vector(2081,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5944581,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188285963,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110001" =>
inv <= conv_std_logic_vector(2079,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5976845,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155915034,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110010" =>
inv <= conv_std_logic_vector(2077,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6009140,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137724004,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110011" =>
inv <= conv_std_logic_vector(2075,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6041466,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149773915,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110100" =>
inv <= conv_std_logic_vector(2073,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6073823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(208172277,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110101" =>
inv <= conv_std_logic_vector(2071,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6106212,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60637778,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110110" =>
inv <= conv_std_logic_vector(2069,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6138631,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260242308,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110111" =>
inv <= conv_std_logic_vector(2067,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6171083,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17927474,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111000" =>
inv <= conv_std_logic_vector(2065,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6203565,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155294811,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111001" =>
inv <= conv_std_logic_vector(2063,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6236079,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151815941,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111010" =>
inv <= conv_std_logic_vector(2061,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6268625,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(23880951,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111011" =>
inv <= conv_std_logic_vector(2059,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6301202,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56363124,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111100" =>
inv <= conv_std_logic_vector(2057,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6333810,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265748209,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111101" =>
inv <= conv_std_logic_vector(2055,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6366451,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131699156,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111110" =>
inv <= conv_std_logic_vector(2053,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6399123,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207669033,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111111" =>
inv <= conv_std_logic_vector(2051,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6431827,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241853027,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN others =>
inv <= conv_std_logic_vector(0,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_lsft32x5.vhd | 10 | 4319 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT32X5.VHD ***
--*** ***
--*** Function: Single Precision Left Shift ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft32x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END fp_lsft32x5;
ARCHITECTURE rtl OF fp_lsft32x5 IS
signal leftone, lefttwo, leftthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
leftone(1) <= inbus(1) AND NOT(shift(2)) AND NOT(shift(1));
leftone(2) <= (inbus(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(1) AND NOT(shift(2)) AND shift(1));
leftone(3) <= (inbus(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(2) AND NOT(shift(2)) AND shift(1)) OR
(inbus(1) AND shift(2) AND NOT(shift(1)));
gla: FOR k IN 4 TO 32 GENERATE
leftone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k-1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k-2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k-3) AND shift(2) AND shift(1));
END GENERATE;
glb: FOR k IN 1 TO 4 GENERATE
lefttwo(k) <= leftone(k) AND NOT(shift(4)) AND NOT(shift(3));
END GENERATE;
glc: FOR k IN 5 TO 8 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(leftone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gld: FOR k IN 9 TO 12 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(leftone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(leftone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gle: FOR k IN 13 TO 32 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(leftone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(leftone(k-8) AND shift(4) AND NOT(shift(3))) OR
(leftone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glf: FOR k IN 1 TO 16 GENERATE
leftthr(k) <= lefttwo(k) AND NOT(shift(5));
END GENERATE;
glg: FOR k IN 17 TO 32 GENERATE
leftthr(k) <= (lefttwo(k) AND NOT(shift(5))) OR
(lefttwo(k-16) AND shift(5));
END GENERATE;
outbus <= leftthr;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/hcc_cntsgn36.vhd | 10 | 6463 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTSGN36.VHD ***
--*** ***
--*** Function: Count leading bits in a signed ***
--*** 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntsgn36;
ARCHITECTURE rtl OF hcc_cntsgn36 IS
type positiontype IS ARRAY (9 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal possec, negsec, sec, sel : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal position : positiontype;
component hcc_sgnpstn
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
possec(1) <= frac(35) OR frac(34) OR frac(33) OR frac(32);
possec(2) <= frac(31) OR frac(30) OR frac(29) OR frac(28);
possec(3) <= frac(27) OR frac(26) OR frac(25) OR frac(24);
possec(4) <= frac(23) OR frac(22) OR frac(21) OR frac(20);
possec(5) <= frac(19) OR frac(18) OR frac(17) OR frac(16);
possec(6) <= frac(15) OR frac(14) OR frac(13) OR frac(12);
possec(7) <= frac(11) OR frac(10) OR frac(9) OR frac(8);
possec(8) <= frac(7) OR frac(6) OR frac(5) OR frac(4);
possec(9) <= frac(3) OR frac(2) OR frac(1);
-- find first leading '0' in inexact portion for 32 bit negative number
negsec(1) <= frac(35) AND frac(34) AND frac(33) AND frac(32);
negsec(2) <= frac(31) AND frac(30) AND frac(29) AND frac(28);
negsec(3) <= frac(27) AND frac(26) AND frac(25) AND frac(24);
negsec(4) <= frac(23) AND frac(22) AND frac(21) AND frac(20);
negsec(5) <= frac(19) AND frac(18) AND frac(17) AND frac(16);
negsec(6) <= frac(15) AND frac(14) AND frac(13) AND frac(12);
negsec(7) <= frac(11) AND frac(10) AND frac(9) AND frac(8);
negsec(8) <= frac(7) AND frac(6) AND frac(5) AND frac(4);
negsec(9) <= frac(3) AND frac(2) AND frac(1);
gaa: FOR k IN 1 TO 9 GENERATE
sec(k) <= (possec(k) AND NOT(frac(36))) OR (negsec(k) AND frac(36));
END GENERATE;
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(7) <= sec(7) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(8) <= sec(8) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(9) <= sec(9) AND NOT(sec(8)) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND
NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_sgnpstn
GENERIC MAP (offset=>0,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(35 DOWNTO 32),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_sgnpstn
GENERIC MAP (offset=>4,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(31 DOWNTO 28),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_sgnpstn
GENERIC MAP (offset=>8,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(27 DOWNTO 24),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_sgnpstn
GENERIC MAP (offset=>12,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(23 DOWNTO 20),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_sgnpstn
GENERIC MAP (offset=>16,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(19 DOWNTO 16),
position=>position(5)(6 DOWNTO 1));
psix: hcc_sgnpstn
GENERIC MAP (offset=>20,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(15 DOWNTO 12),
position=>position(6)(6 DOWNTO 1));
psev: hcc_sgnpstn
GENERIC MAP (offset=>24,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(11 DOWNTO 8),
position=>position(7)(6 DOWNTO 1));
pegt: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(7 DOWNTO 4),
position=>position(8)(6 DOWNTO 1));
pnin: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>6)
PORT MAP (signbit=>frac(36),inbus=>lastfrac,
position=>position(9)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & frac(36);
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6)) OR
(position(7)(k) AND sel(7)) OR
(position(8)(k) AND sel(8)) OR
(position(9)(k) AND sel(9));
END GENERATE;
END rtl;
| mit |
boztalay/OZ-3 | FPGA/OZ-3/output_pin_cntl.vhd | 2 | 1660 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 23:51:17 12/20/2009
-- Design Name:
-- Module Name: output_pin_cntl - Behavioral
-- Project Name: OZ-3
-- Target Devices:
-- Tool versions:
-- Description: The output pin register and controller for the OZ-3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.20 - File written, will test with rest of processor; not complex enough to warrant the time
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity output_pin_cntl is
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(3 downto 0);
pins : out STD_LOGIC_VECTOR (15 downto 0));
end output_pin_cntl;
architecture Behavioral of output_pin_cntl is
begin
opin: process (clock, reset) is
variable opin_reg : STD_LOGIC_VECTOR(15 downto 0) := x"0000";
begin
if falling_edge(clock) then
if enable = '1' then
opin_reg(conv_integer(unsigned(sel))) := data;
end if;
end if;
if reset = '1' then
opin_reg := (others => '0');
end if;
pins <= opin_reg;
end process;
end Behavioral;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fpc_library_package_cmd.vhd | 10 | 48869 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/hcc_neg2x.vhd | 10 | 2843 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NEG2X.VHD ***
--*** ***
--*** Function: Negation (for unary -ve) ***
--*** ***
--*** 13/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_neg2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_neg2x;
ARCHITECTURE rtl OF hcc_neg2x IS
signal aaff : STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC;
BEGIN
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64+13*xoutput+3*funcoutput LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
goa: IF (ieeeoutput = 1) GENERATE
cc(64) <= NOT(aaff(64));
cc(63 DOWNTO 1) <= aaff(63 DOWNTO 1);
ccsat <= '0';
cczip <= '0';
END GENERATE;
gob: IF (xoutput = 1) GENERATE
gxa: FOR k IN 14 TO 77 GENERATE
cc(k) <= NOT(aaff(k));
END GENERATE;
cc(13 DOWNTO 1) <= aaff(13 DOWNTO 1);
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
goc: IF (funcoutput = 1) GENERATE
cc(67) <= NOT(aaff(67));
cc(66 DOWNTO 1) <= aaff(66 DOWNTO 1);
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/hcc_neg2x.vhd | 10 | 2843 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NEG2X.VHD ***
--*** ***
--*** Function: Negation (for unary -ve) ***
--*** ***
--*** 13/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_neg2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_neg2x;
ARCHITECTURE rtl OF hcc_neg2x IS
signal aaff : STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC;
BEGIN
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64+13*xoutput+3*funcoutput LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
goa: IF (ieeeoutput = 1) GENERATE
cc(64) <= NOT(aaff(64));
cc(63 DOWNTO 1) <= aaff(63 DOWNTO 1);
ccsat <= '0';
cczip <= '0';
END GENERATE;
gob: IF (xoutput = 1) GENERATE
gxa: FOR k IN 14 TO 77 GENERATE
cc(k) <= NOT(aaff(k));
END GENERATE;
cc(13 DOWNTO 1) <= aaff(13 DOWNTO 1);
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
goc: IF (funcoutput = 1) GENERATE
cc(67) <= NOT(aaff(67));
cc(66 DOWNTO 1) <= aaff(66 DOWNTO 1);
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/hcc_mul54uss_8tst.vhd | 10 | 8877 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54USS_8TST.VHD ***
--*** ***
--*** Function: 6 pipeline stage unsigned 54 ***
--*** bit multiplier (synthesizable) ***
--*** ***
--*** FOR FITTING TESTING ONLY - NOT TESTED ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul54uss_8tst IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54uss_8tst;
ARCHITECTURE syn of hcc_mul54uss_8tst IS
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mulforout, mulfivout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal sumone, carone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecfor, vecfiv, vecsix : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal sumtwo, cartwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (38 DOWNTO 1);
signal vecsev, vecegt, vecnin : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumthr, carthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumthrff, carthrff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (34 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 34 GENERATE
zerovec(k) <= '0';
END GENERATE;
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => mulaa(54 DOWNTO 19),
datab => mulbb(54 DOWNTO 19),
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => mulaa(54 DOWNTO 37),
datab_0 => mulbb(18 DOWNTO 1),
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => mulaa(36 DOWNTO 19),
datab_0 => mulbb(18 DOWNTO 1),
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulbb(54 DOWNTO 37),
datab_0 => mulaa(18 DOWNTO 1),
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulbb(36 DOWNTO 19),
datab_0 => mulaa(18 DOWNTO 1),
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
vecone <= multwoout;
vectwo <= zerovec(18 DOWNTO 1) & multhrout(36 DOWNTO 19);
vecthr <= mulforout;
gca: FOR k IN 1 TO 36 GENERATE
sumone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carone(k) <= (vecone(k) AND vectwo(k)) OR
(vecone(k) AND vecthr(k)) OR
(vectwo(k) AND vecthr(k));
END GENERATE;
vecfor <= '0' & sumone;
vecfiv <= carone & '0';
vecsix <= zerovec(19 DOWNTO 1) & mulfivout(36 DOWNTO 19);
gcb: FOR k IN 1 TO 37 GENERATE
sumtwo(k) <= vecfor(k) XOR vecfiv(k) XOR vecsix(k);
cartwo(k) <= (vecfor(k) AND vecfiv(k)) OR
(vecfor(k) AND vecsix(k)) OR
(vecfiv(k) AND vecsix(k));
END GENERATE;
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 38 LOOP
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumtwoff <= '0' & sumtwo;
cartwoff <= cartwo & '0';
END IF;
END IF;
END PROCESS;
vecsev <= zerovec(34 DOWNTO 1) & sumtwoff;
vecegt <= zerovec(34 DOWNTO 1) & cartwoff;
vecnin <= muloneout;
gcc: FOR k IN 1 TO 72 GENERATE
sumthr(k) <= vecsev(k) XOR vecegt(k) XOR vecnin(k);
carthr(k) <= (vecsev(k) AND vecegt(k)) OR
(vecsev(k) AND vecnin(k)) OR
(vecegt(k) AND vecnin(k));
END GENERATE;
pmb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
sumthrff(k) <= '0';
carthrff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumthrff <= sumthr;
carthrff <= carthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
-- according to marcel, 2 pipes = 1 pipe in middle, on on output
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => 2,
lpm_type => "LPM_ADD_SUB",
lpm_width => 64
)
PORT MAP (
dataa => sumthrff(72 DOWNTO 9),
datab => carthrff(72 DOWNTO 9),
clken => enable,
aclr => reset,
clock => sysclk,
result => mulcc
);
END syn;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_invsqr_lut1.vhd | 10 | 35784 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_INVSQR_LUT1.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse Root ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_invsqr_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END fp_invsqr_lut1;
ARCHITECTURE rtl OF fp_invsqr_lut1 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1023,11);
WHEN "000000001" => data <= conv_std_logic_vector(1020,11);
WHEN "000000010" => data <= conv_std_logic_vector(1017,11);
WHEN "000000011" => data <= conv_std_logic_vector(1014,11);
WHEN "000000100" => data <= conv_std_logic_vector(1011,11);
WHEN "000000101" => data <= conv_std_logic_vector(1008,11);
WHEN "000000110" => data <= conv_std_logic_vector(1005,11);
WHEN "000000111" => data <= conv_std_logic_vector(1002,11);
WHEN "000001000" => data <= conv_std_logic_vector(999,11);
WHEN "000001001" => data <= conv_std_logic_vector(996,11);
WHEN "000001010" => data <= conv_std_logic_vector(993,11);
WHEN "000001011" => data <= conv_std_logic_vector(990,11);
WHEN "000001100" => data <= conv_std_logic_vector(988,11);
WHEN "000001101" => data <= conv_std_logic_vector(985,11);
WHEN "000001110" => data <= conv_std_logic_vector(982,11);
WHEN "000001111" => data <= conv_std_logic_vector(979,11);
WHEN "000010000" => data <= conv_std_logic_vector(976,11);
WHEN "000010001" => data <= conv_std_logic_vector(974,11);
WHEN "000010010" => data <= conv_std_logic_vector(971,11);
WHEN "000010011" => data <= conv_std_logic_vector(968,11);
WHEN "000010100" => data <= conv_std_logic_vector(965,11);
WHEN "000010101" => data <= conv_std_logic_vector(963,11);
WHEN "000010110" => data <= conv_std_logic_vector(960,11);
WHEN "000010111" => data <= conv_std_logic_vector(957,11);
WHEN "000011000" => data <= conv_std_logic_vector(955,11);
WHEN "000011001" => data <= conv_std_logic_vector(952,11);
WHEN "000011010" => data <= conv_std_logic_vector(949,11);
WHEN "000011011" => data <= conv_std_logic_vector(947,11);
WHEN "000011100" => data <= conv_std_logic_vector(944,11);
WHEN "000011101" => data <= conv_std_logic_vector(941,11);
WHEN "000011110" => data <= conv_std_logic_vector(939,11);
WHEN "000011111" => data <= conv_std_logic_vector(936,11);
WHEN "000100000" => data <= conv_std_logic_vector(934,11);
WHEN "000100001" => data <= conv_std_logic_vector(931,11);
WHEN "000100010" => data <= conv_std_logic_vector(929,11);
WHEN "000100011" => data <= conv_std_logic_vector(926,11);
WHEN "000100100" => data <= conv_std_logic_vector(924,11);
WHEN "000100101" => data <= conv_std_logic_vector(921,11);
WHEN "000100110" => data <= conv_std_logic_vector(918,11);
WHEN "000100111" => data <= conv_std_logic_vector(916,11);
WHEN "000101000" => data <= conv_std_logic_vector(913,11);
WHEN "000101001" => data <= conv_std_logic_vector(911,11);
WHEN "000101010" => data <= conv_std_logic_vector(909,11);
WHEN "000101011" => data <= conv_std_logic_vector(906,11);
WHEN "000101100" => data <= conv_std_logic_vector(904,11);
WHEN "000101101" => data <= conv_std_logic_vector(901,11);
WHEN "000101110" => data <= conv_std_logic_vector(899,11);
WHEN "000101111" => data <= conv_std_logic_vector(896,11);
WHEN "000110000" => data <= conv_std_logic_vector(894,11);
WHEN "000110001" => data <= conv_std_logic_vector(892,11);
WHEN "000110010" => data <= conv_std_logic_vector(889,11);
WHEN "000110011" => data <= conv_std_logic_vector(887,11);
WHEN "000110100" => data <= conv_std_logic_vector(885,11);
WHEN "000110101" => data <= conv_std_logic_vector(882,11);
WHEN "000110110" => data <= conv_std_logic_vector(880,11);
WHEN "000110111" => data <= conv_std_logic_vector(878,11);
WHEN "000111000" => data <= conv_std_logic_vector(875,11);
WHEN "000111001" => data <= conv_std_logic_vector(873,11);
WHEN "000111010" => data <= conv_std_logic_vector(871,11);
WHEN "000111011" => data <= conv_std_logic_vector(868,11);
WHEN "000111100" => data <= conv_std_logic_vector(866,11);
WHEN "000111101" => data <= conv_std_logic_vector(864,11);
WHEN "000111110" => data <= conv_std_logic_vector(862,11);
WHEN "000111111" => data <= conv_std_logic_vector(859,11);
WHEN "001000000" => data <= conv_std_logic_vector(857,11);
WHEN "001000001" => data <= conv_std_logic_vector(855,11);
WHEN "001000010" => data <= conv_std_logic_vector(853,11);
WHEN "001000011" => data <= conv_std_logic_vector(850,11);
WHEN "001000100" => data <= conv_std_logic_vector(848,11);
WHEN "001000101" => data <= conv_std_logic_vector(846,11);
WHEN "001000110" => data <= conv_std_logic_vector(844,11);
WHEN "001000111" => data <= conv_std_logic_vector(842,11);
WHEN "001001000" => data <= conv_std_logic_vector(840,11);
WHEN "001001001" => data <= conv_std_logic_vector(837,11);
WHEN "001001010" => data <= conv_std_logic_vector(835,11);
WHEN "001001011" => data <= conv_std_logic_vector(833,11);
WHEN "001001100" => data <= conv_std_logic_vector(831,11);
WHEN "001001101" => data <= conv_std_logic_vector(829,11);
WHEN "001001110" => data <= conv_std_logic_vector(827,11);
WHEN "001001111" => data <= conv_std_logic_vector(825,11);
WHEN "001010000" => data <= conv_std_logic_vector(823,11);
WHEN "001010001" => data <= conv_std_logic_vector(820,11);
WHEN "001010010" => data <= conv_std_logic_vector(818,11);
WHEN "001010011" => data <= conv_std_logic_vector(816,11);
WHEN "001010100" => data <= conv_std_logic_vector(814,11);
WHEN "001010101" => data <= conv_std_logic_vector(812,11);
WHEN "001010110" => data <= conv_std_logic_vector(810,11);
WHEN "001010111" => data <= conv_std_logic_vector(808,11);
WHEN "001011000" => data <= conv_std_logic_vector(806,11);
WHEN "001011001" => data <= conv_std_logic_vector(804,11);
WHEN "001011010" => data <= conv_std_logic_vector(802,11);
WHEN "001011011" => data <= conv_std_logic_vector(800,11);
WHEN "001011100" => data <= conv_std_logic_vector(798,11);
WHEN "001011101" => data <= conv_std_logic_vector(796,11);
WHEN "001011110" => data <= conv_std_logic_vector(794,11);
WHEN "001011111" => data <= conv_std_logic_vector(792,11);
WHEN "001100000" => data <= conv_std_logic_vector(790,11);
WHEN "001100001" => data <= conv_std_logic_vector(788,11);
WHEN "001100010" => data <= conv_std_logic_vector(786,11);
WHEN "001100011" => data <= conv_std_logic_vector(785,11);
WHEN "001100100" => data <= conv_std_logic_vector(783,11);
WHEN "001100101" => data <= conv_std_logic_vector(781,11);
WHEN "001100110" => data <= conv_std_logic_vector(779,11);
WHEN "001100111" => data <= conv_std_logic_vector(777,11);
WHEN "001101000" => data <= conv_std_logic_vector(775,11);
WHEN "001101001" => data <= conv_std_logic_vector(773,11);
WHEN "001101010" => data <= conv_std_logic_vector(771,11);
WHEN "001101011" => data <= conv_std_logic_vector(769,11);
WHEN "001101100" => data <= conv_std_logic_vector(768,11);
WHEN "001101101" => data <= conv_std_logic_vector(766,11);
WHEN "001101110" => data <= conv_std_logic_vector(764,11);
WHEN "001101111" => data <= conv_std_logic_vector(762,11);
WHEN "001110000" => data <= conv_std_logic_vector(760,11);
WHEN "001110001" => data <= conv_std_logic_vector(758,11);
WHEN "001110010" => data <= conv_std_logic_vector(757,11);
WHEN "001110011" => data <= conv_std_logic_vector(755,11);
WHEN "001110100" => data <= conv_std_logic_vector(753,11);
WHEN "001110101" => data <= conv_std_logic_vector(751,11);
WHEN "001110110" => data <= conv_std_logic_vector(749,11);
WHEN "001110111" => data <= conv_std_logic_vector(748,11);
WHEN "001111000" => data <= conv_std_logic_vector(746,11);
WHEN "001111001" => data <= conv_std_logic_vector(744,11);
WHEN "001111010" => data <= conv_std_logic_vector(742,11);
WHEN "001111011" => data <= conv_std_logic_vector(741,11);
WHEN "001111100" => data <= conv_std_logic_vector(739,11);
WHEN "001111101" => data <= conv_std_logic_vector(737,11);
WHEN "001111110" => data <= conv_std_logic_vector(735,11);
WHEN "001111111" => data <= conv_std_logic_vector(734,11);
WHEN "010000000" => data <= conv_std_logic_vector(732,11);
WHEN "010000001" => data <= conv_std_logic_vector(730,11);
WHEN "010000010" => data <= conv_std_logic_vector(728,11);
WHEN "010000011" => data <= conv_std_logic_vector(727,11);
WHEN "010000100" => data <= conv_std_logic_vector(725,11);
WHEN "010000101" => data <= conv_std_logic_vector(723,11);
WHEN "010000110" => data <= conv_std_logic_vector(722,11);
WHEN "010000111" => data <= conv_std_logic_vector(720,11);
WHEN "010001000" => data <= conv_std_logic_vector(718,11);
WHEN "010001001" => data <= conv_std_logic_vector(717,11);
WHEN "010001010" => data <= conv_std_logic_vector(715,11);
WHEN "010001011" => data <= conv_std_logic_vector(713,11);
WHEN "010001100" => data <= conv_std_logic_vector(712,11);
WHEN "010001101" => data <= conv_std_logic_vector(710,11);
WHEN "010001110" => data <= conv_std_logic_vector(709,11);
WHEN "010001111" => data <= conv_std_logic_vector(707,11);
WHEN "010010000" => data <= conv_std_logic_vector(705,11);
WHEN "010010001" => data <= conv_std_logic_vector(704,11);
WHEN "010010010" => data <= conv_std_logic_vector(702,11);
WHEN "010010011" => data <= conv_std_logic_vector(700,11);
WHEN "010010100" => data <= conv_std_logic_vector(699,11);
WHEN "010010101" => data <= conv_std_logic_vector(697,11);
WHEN "010010110" => data <= conv_std_logic_vector(696,11);
WHEN "010010111" => data <= conv_std_logic_vector(694,11);
WHEN "010011000" => data <= conv_std_logic_vector(693,11);
WHEN "010011001" => data <= conv_std_logic_vector(691,11);
WHEN "010011010" => data <= conv_std_logic_vector(689,11);
WHEN "010011011" => data <= conv_std_logic_vector(688,11);
WHEN "010011100" => data <= conv_std_logic_vector(686,11);
WHEN "010011101" => data <= conv_std_logic_vector(685,11);
WHEN "010011110" => data <= conv_std_logic_vector(683,11);
WHEN "010011111" => data <= conv_std_logic_vector(682,11);
WHEN "010100000" => data <= conv_std_logic_vector(680,11);
WHEN "010100001" => data <= conv_std_logic_vector(679,11);
WHEN "010100010" => data <= conv_std_logic_vector(677,11);
WHEN "010100011" => data <= conv_std_logic_vector(676,11);
WHEN "010100100" => data <= conv_std_logic_vector(674,11);
WHEN "010100101" => data <= conv_std_logic_vector(673,11);
WHEN "010100110" => data <= conv_std_logic_vector(671,11);
WHEN "010100111" => data <= conv_std_logic_vector(670,11);
WHEN "010101000" => data <= conv_std_logic_vector(668,11);
WHEN "010101001" => data <= conv_std_logic_vector(667,11);
WHEN "010101010" => data <= conv_std_logic_vector(665,11);
WHEN "010101011" => data <= conv_std_logic_vector(664,11);
WHEN "010101100" => data <= conv_std_logic_vector(662,11);
WHEN "010101101" => data <= conv_std_logic_vector(661,11);
WHEN "010101110" => data <= conv_std_logic_vector(660,11);
WHEN "010101111" => data <= conv_std_logic_vector(658,11);
WHEN "010110000" => data <= conv_std_logic_vector(657,11);
WHEN "010110001" => data <= conv_std_logic_vector(655,11);
WHEN "010110010" => data <= conv_std_logic_vector(654,11);
WHEN "010110011" => data <= conv_std_logic_vector(652,11);
WHEN "010110100" => data <= conv_std_logic_vector(651,11);
WHEN "010110101" => data <= conv_std_logic_vector(650,11);
WHEN "010110110" => data <= conv_std_logic_vector(648,11);
WHEN "010110111" => data <= conv_std_logic_vector(647,11);
WHEN "010111000" => data <= conv_std_logic_vector(645,11);
WHEN "010111001" => data <= conv_std_logic_vector(644,11);
WHEN "010111010" => data <= conv_std_logic_vector(643,11);
WHEN "010111011" => data <= conv_std_logic_vector(641,11);
WHEN "010111100" => data <= conv_std_logic_vector(640,11);
WHEN "010111101" => data <= conv_std_logic_vector(639,11);
WHEN "010111110" => data <= conv_std_logic_vector(637,11);
WHEN "010111111" => data <= conv_std_logic_vector(636,11);
WHEN "011000000" => data <= conv_std_logic_vector(634,11);
WHEN "011000001" => data <= conv_std_logic_vector(633,11);
WHEN "011000010" => data <= conv_std_logic_vector(632,11);
WHEN "011000011" => data <= conv_std_logic_vector(630,11);
WHEN "011000100" => data <= conv_std_logic_vector(629,11);
WHEN "011000101" => data <= conv_std_logic_vector(628,11);
WHEN "011000110" => data <= conv_std_logic_vector(626,11);
WHEN "011000111" => data <= conv_std_logic_vector(625,11);
WHEN "011001000" => data <= conv_std_logic_vector(624,11);
WHEN "011001001" => data <= conv_std_logic_vector(622,11);
WHEN "011001010" => data <= conv_std_logic_vector(621,11);
WHEN "011001011" => data <= conv_std_logic_vector(620,11);
WHEN "011001100" => data <= conv_std_logic_vector(619,11);
WHEN "011001101" => data <= conv_std_logic_vector(617,11);
WHEN "011001110" => data <= conv_std_logic_vector(616,11);
WHEN "011001111" => data <= conv_std_logic_vector(615,11);
WHEN "011010000" => data <= conv_std_logic_vector(613,11);
WHEN "011010001" => data <= conv_std_logic_vector(612,11);
WHEN "011010010" => data <= conv_std_logic_vector(611,11);
WHEN "011010011" => data <= conv_std_logic_vector(610,11);
WHEN "011010100" => data <= conv_std_logic_vector(608,11);
WHEN "011010101" => data <= conv_std_logic_vector(607,11);
WHEN "011010110" => data <= conv_std_logic_vector(606,11);
WHEN "011010111" => data <= conv_std_logic_vector(605,11);
WHEN "011011000" => data <= conv_std_logic_vector(603,11);
WHEN "011011001" => data <= conv_std_logic_vector(602,11);
WHEN "011011010" => data <= conv_std_logic_vector(601,11);
WHEN "011011011" => data <= conv_std_logic_vector(600,11);
WHEN "011011100" => data <= conv_std_logic_vector(598,11);
WHEN "011011101" => data <= conv_std_logic_vector(597,11);
WHEN "011011110" => data <= conv_std_logic_vector(596,11);
WHEN "011011111" => data <= conv_std_logic_vector(595,11);
WHEN "011100000" => data <= conv_std_logic_vector(594,11);
WHEN "011100001" => data <= conv_std_logic_vector(592,11);
WHEN "011100010" => data <= conv_std_logic_vector(591,11);
WHEN "011100011" => data <= conv_std_logic_vector(590,11);
WHEN "011100100" => data <= conv_std_logic_vector(589,11);
WHEN "011100101" => data <= conv_std_logic_vector(588,11);
WHEN "011100110" => data <= conv_std_logic_vector(586,11);
WHEN "011100111" => data <= conv_std_logic_vector(585,11);
WHEN "011101000" => data <= conv_std_logic_vector(584,11);
WHEN "011101001" => data <= conv_std_logic_vector(583,11);
WHEN "011101010" => data <= conv_std_logic_vector(582,11);
WHEN "011101011" => data <= conv_std_logic_vector(580,11);
WHEN "011101100" => data <= conv_std_logic_vector(579,11);
WHEN "011101101" => data <= conv_std_logic_vector(578,11);
WHEN "011101110" => data <= conv_std_logic_vector(577,11);
WHEN "011101111" => data <= conv_std_logic_vector(576,11);
WHEN "011110000" => data <= conv_std_logic_vector(575,11);
WHEN "011110001" => data <= conv_std_logic_vector(574,11);
WHEN "011110010" => data <= conv_std_logic_vector(572,11);
WHEN "011110011" => data <= conv_std_logic_vector(571,11);
WHEN "011110100" => data <= conv_std_logic_vector(570,11);
WHEN "011110101" => data <= conv_std_logic_vector(569,11);
WHEN "011110110" => data <= conv_std_logic_vector(568,11);
WHEN "011110111" => data <= conv_std_logic_vector(567,11);
WHEN "011111000" => data <= conv_std_logic_vector(566,11);
WHEN "011111001" => data <= conv_std_logic_vector(565,11);
WHEN "011111010" => data <= conv_std_logic_vector(563,11);
WHEN "011111011" => data <= conv_std_logic_vector(562,11);
WHEN "011111100" => data <= conv_std_logic_vector(561,11);
WHEN "011111101" => data <= conv_std_logic_vector(560,11);
WHEN "011111110" => data <= conv_std_logic_vector(559,11);
WHEN "011111111" => data <= conv_std_logic_vector(558,11);
WHEN "100000000" => data <= conv_std_logic_vector(557,11);
WHEN "100000001" => data <= conv_std_logic_vector(556,11);
WHEN "100000010" => data <= conv_std_logic_vector(555,11);
WHEN "100000011" => data <= conv_std_logic_vector(554,11);
WHEN "100000100" => data <= conv_std_logic_vector(553,11);
WHEN "100000101" => data <= conv_std_logic_vector(551,11);
WHEN "100000110" => data <= conv_std_logic_vector(550,11);
WHEN "100000111" => data <= conv_std_logic_vector(549,11);
WHEN "100001000" => data <= conv_std_logic_vector(548,11);
WHEN "100001001" => data <= conv_std_logic_vector(547,11);
WHEN "100001010" => data <= conv_std_logic_vector(546,11);
WHEN "100001011" => data <= conv_std_logic_vector(545,11);
WHEN "100001100" => data <= conv_std_logic_vector(544,11);
WHEN "100001101" => data <= conv_std_logic_vector(543,11);
WHEN "100001110" => data <= conv_std_logic_vector(542,11);
WHEN "100001111" => data <= conv_std_logic_vector(541,11);
WHEN "100010000" => data <= conv_std_logic_vector(540,11);
WHEN "100010001" => data <= conv_std_logic_vector(539,11);
WHEN "100010010" => data <= conv_std_logic_vector(538,11);
WHEN "100010011" => data <= conv_std_logic_vector(537,11);
WHEN "100010100" => data <= conv_std_logic_vector(536,11);
WHEN "100010101" => data <= conv_std_logic_vector(535,11);
WHEN "100010110" => data <= conv_std_logic_vector(534,11);
WHEN "100010111" => data <= conv_std_logic_vector(533,11);
WHEN "100011000" => data <= conv_std_logic_vector(532,11);
WHEN "100011001" => data <= conv_std_logic_vector(531,11);
WHEN "100011010" => data <= conv_std_logic_vector(530,11);
WHEN "100011011" => data <= conv_std_logic_vector(529,11);
WHEN "100011100" => data <= conv_std_logic_vector(528,11);
WHEN "100011101" => data <= conv_std_logic_vector(527,11);
WHEN "100011110" => data <= conv_std_logic_vector(526,11);
WHEN "100011111" => data <= conv_std_logic_vector(525,11);
WHEN "100100000" => data <= conv_std_logic_vector(524,11);
WHEN "100100001" => data <= conv_std_logic_vector(523,11);
WHEN "100100010" => data <= conv_std_logic_vector(522,11);
WHEN "100100011" => data <= conv_std_logic_vector(521,11);
WHEN "100100100" => data <= conv_std_logic_vector(520,11);
WHEN "100100101" => data <= conv_std_logic_vector(519,11);
WHEN "100100110" => data <= conv_std_logic_vector(518,11);
WHEN "100100111" => data <= conv_std_logic_vector(517,11);
WHEN "100101000" => data <= conv_std_logic_vector(516,11);
WHEN "100101001" => data <= conv_std_logic_vector(515,11);
WHEN "100101010" => data <= conv_std_logic_vector(514,11);
WHEN "100101011" => data <= conv_std_logic_vector(513,11);
WHEN "100101100" => data <= conv_std_logic_vector(512,11);
WHEN "100101101" => data <= conv_std_logic_vector(511,11);
WHEN "100101110" => data <= conv_std_logic_vector(510,11);
WHEN "100101111" => data <= conv_std_logic_vector(509,11);
WHEN "100110000" => data <= conv_std_logic_vector(508,11);
WHEN "100110001" => data <= conv_std_logic_vector(508,11);
WHEN "100110010" => data <= conv_std_logic_vector(507,11);
WHEN "100110011" => data <= conv_std_logic_vector(506,11);
WHEN "100110100" => data <= conv_std_logic_vector(505,11);
WHEN "100110101" => data <= conv_std_logic_vector(504,11);
WHEN "100110110" => data <= conv_std_logic_vector(503,11);
WHEN "100110111" => data <= conv_std_logic_vector(502,11);
WHEN "100111000" => data <= conv_std_logic_vector(501,11);
WHEN "100111001" => data <= conv_std_logic_vector(500,11);
WHEN "100111010" => data <= conv_std_logic_vector(499,11);
WHEN "100111011" => data <= conv_std_logic_vector(498,11);
WHEN "100111100" => data <= conv_std_logic_vector(497,11);
WHEN "100111101" => data <= conv_std_logic_vector(497,11);
WHEN "100111110" => data <= conv_std_logic_vector(496,11);
WHEN "100111111" => data <= conv_std_logic_vector(495,11);
WHEN "101000000" => data <= conv_std_logic_vector(494,11);
WHEN "101000001" => data <= conv_std_logic_vector(493,11);
WHEN "101000010" => data <= conv_std_logic_vector(492,11);
WHEN "101000011" => data <= conv_std_logic_vector(491,11);
WHEN "101000100" => data <= conv_std_logic_vector(490,11);
WHEN "101000101" => data <= conv_std_logic_vector(489,11);
WHEN "101000110" => data <= conv_std_logic_vector(489,11);
WHEN "101000111" => data <= conv_std_logic_vector(488,11);
WHEN "101001000" => data <= conv_std_logic_vector(487,11);
WHEN "101001001" => data <= conv_std_logic_vector(486,11);
WHEN "101001010" => data <= conv_std_logic_vector(485,11);
WHEN "101001011" => data <= conv_std_logic_vector(484,11);
WHEN "101001100" => data <= conv_std_logic_vector(483,11);
WHEN "101001101" => data <= conv_std_logic_vector(483,11);
WHEN "101001110" => data <= conv_std_logic_vector(482,11);
WHEN "101001111" => data <= conv_std_logic_vector(481,11);
WHEN "101010000" => data <= conv_std_logic_vector(480,11);
WHEN "101010001" => data <= conv_std_logic_vector(479,11);
WHEN "101010010" => data <= conv_std_logic_vector(478,11);
WHEN "101010011" => data <= conv_std_logic_vector(477,11);
WHEN "101010100" => data <= conv_std_logic_vector(477,11);
WHEN "101010101" => data <= conv_std_logic_vector(476,11);
WHEN "101010110" => data <= conv_std_logic_vector(475,11);
WHEN "101010111" => data <= conv_std_logic_vector(474,11);
WHEN "101011000" => data <= conv_std_logic_vector(473,11);
WHEN "101011001" => data <= conv_std_logic_vector(472,11);
WHEN "101011010" => data <= conv_std_logic_vector(472,11);
WHEN "101011011" => data <= conv_std_logic_vector(471,11);
WHEN "101011100" => data <= conv_std_logic_vector(470,11);
WHEN "101011101" => data <= conv_std_logic_vector(469,11);
WHEN "101011110" => data <= conv_std_logic_vector(468,11);
WHEN "101011111" => data <= conv_std_logic_vector(468,11);
WHEN "101100000" => data <= conv_std_logic_vector(467,11);
WHEN "101100001" => data <= conv_std_logic_vector(466,11);
WHEN "101100010" => data <= conv_std_logic_vector(465,11);
WHEN "101100011" => data <= conv_std_logic_vector(464,11);
WHEN "101100100" => data <= conv_std_logic_vector(464,11);
WHEN "101100101" => data <= conv_std_logic_vector(463,11);
WHEN "101100110" => data <= conv_std_logic_vector(462,11);
WHEN "101100111" => data <= conv_std_logic_vector(461,11);
WHEN "101101000" => data <= conv_std_logic_vector(460,11);
WHEN "101101001" => data <= conv_std_logic_vector(460,11);
WHEN "101101010" => data <= conv_std_logic_vector(459,11);
WHEN "101101011" => data <= conv_std_logic_vector(458,11);
WHEN "101101100" => data <= conv_std_logic_vector(457,11);
WHEN "101101101" => data <= conv_std_logic_vector(456,11);
WHEN "101101110" => data <= conv_std_logic_vector(456,11);
WHEN "101101111" => data <= conv_std_logic_vector(455,11);
WHEN "101110000" => data <= conv_std_logic_vector(454,11);
WHEN "101110001" => data <= conv_std_logic_vector(453,11);
WHEN "101110010" => data <= conv_std_logic_vector(453,11);
WHEN "101110011" => data <= conv_std_logic_vector(452,11);
WHEN "101110100" => data <= conv_std_logic_vector(451,11);
WHEN "101110101" => data <= conv_std_logic_vector(450,11);
WHEN "101110110" => data <= conv_std_logic_vector(449,11);
WHEN "101110111" => data <= conv_std_logic_vector(449,11);
WHEN "101111000" => data <= conv_std_logic_vector(448,11);
WHEN "101111001" => data <= conv_std_logic_vector(447,11);
WHEN "101111010" => data <= conv_std_logic_vector(446,11);
WHEN "101111011" => data <= conv_std_logic_vector(446,11);
WHEN "101111100" => data <= conv_std_logic_vector(445,11);
WHEN "101111101" => data <= conv_std_logic_vector(444,11);
WHEN "101111110" => data <= conv_std_logic_vector(443,11);
WHEN "101111111" => data <= conv_std_logic_vector(443,11);
WHEN "110000000" => data <= conv_std_logic_vector(442,11);
WHEN "110000001" => data <= conv_std_logic_vector(441,11);
WHEN "110000010" => data <= conv_std_logic_vector(440,11);
WHEN "110000011" => data <= conv_std_logic_vector(440,11);
WHEN "110000100" => data <= conv_std_logic_vector(439,11);
WHEN "110000101" => data <= conv_std_logic_vector(438,11);
WHEN "110000110" => data <= conv_std_logic_vector(438,11);
WHEN "110000111" => data <= conv_std_logic_vector(437,11);
WHEN "110001000" => data <= conv_std_logic_vector(436,11);
WHEN "110001001" => data <= conv_std_logic_vector(435,11);
WHEN "110001010" => data <= conv_std_logic_vector(435,11);
WHEN "110001011" => data <= conv_std_logic_vector(434,11);
WHEN "110001100" => data <= conv_std_logic_vector(433,11);
WHEN "110001101" => data <= conv_std_logic_vector(433,11);
WHEN "110001110" => data <= conv_std_logic_vector(432,11);
WHEN "110001111" => data <= conv_std_logic_vector(431,11);
WHEN "110010000" => data <= conv_std_logic_vector(430,11);
WHEN "110010001" => data <= conv_std_logic_vector(430,11);
WHEN "110010010" => data <= conv_std_logic_vector(429,11);
WHEN "110010011" => data <= conv_std_logic_vector(428,11);
WHEN "110010100" => data <= conv_std_logic_vector(428,11);
WHEN "110010101" => data <= conv_std_logic_vector(427,11);
WHEN "110010110" => data <= conv_std_logic_vector(426,11);
WHEN "110010111" => data <= conv_std_logic_vector(425,11);
WHEN "110011000" => data <= conv_std_logic_vector(425,11);
WHEN "110011001" => data <= conv_std_logic_vector(424,11);
WHEN "110011010" => data <= conv_std_logic_vector(423,11);
WHEN "110011011" => data <= conv_std_logic_vector(423,11);
WHEN "110011100" => data <= conv_std_logic_vector(422,11);
WHEN "110011101" => data <= conv_std_logic_vector(421,11);
WHEN "110011110" => data <= conv_std_logic_vector(421,11);
WHEN "110011111" => data <= conv_std_logic_vector(420,11);
WHEN "110100000" => data <= conv_std_logic_vector(419,11);
WHEN "110100001" => data <= conv_std_logic_vector(419,11);
WHEN "110100010" => data <= conv_std_logic_vector(418,11);
WHEN "110100011" => data <= conv_std_logic_vector(417,11);
WHEN "110100100" => data <= conv_std_logic_vector(417,11);
WHEN "110100101" => data <= conv_std_logic_vector(416,11);
WHEN "110100110" => data <= conv_std_logic_vector(415,11);
WHEN "110100111" => data <= conv_std_logic_vector(415,11);
WHEN "110101000" => data <= conv_std_logic_vector(414,11);
WHEN "110101001" => data <= conv_std_logic_vector(413,11);
WHEN "110101010" => data <= conv_std_logic_vector(413,11);
WHEN "110101011" => data <= conv_std_logic_vector(412,11);
WHEN "110101100" => data <= conv_std_logic_vector(411,11);
WHEN "110101101" => data <= conv_std_logic_vector(411,11);
WHEN "110101110" => data <= conv_std_logic_vector(410,11);
WHEN "110101111" => data <= conv_std_logic_vector(409,11);
WHEN "110110000" => data <= conv_std_logic_vector(409,11);
WHEN "110110001" => data <= conv_std_logic_vector(408,11);
WHEN "110110010" => data <= conv_std_logic_vector(407,11);
WHEN "110110011" => data <= conv_std_logic_vector(407,11);
WHEN "110110100" => data <= conv_std_logic_vector(406,11);
WHEN "110110101" => data <= conv_std_logic_vector(405,11);
WHEN "110110110" => data <= conv_std_logic_vector(405,11);
WHEN "110110111" => data <= conv_std_logic_vector(404,11);
WHEN "110111000" => data <= conv_std_logic_vector(404,11);
WHEN "110111001" => data <= conv_std_logic_vector(403,11);
WHEN "110111010" => data <= conv_std_logic_vector(402,11);
WHEN "110111011" => data <= conv_std_logic_vector(402,11);
WHEN "110111100" => data <= conv_std_logic_vector(401,11);
WHEN "110111101" => data <= conv_std_logic_vector(400,11);
WHEN "110111110" => data <= conv_std_logic_vector(400,11);
WHEN "110111111" => data <= conv_std_logic_vector(399,11);
WHEN "111000000" => data <= conv_std_logic_vector(399,11);
WHEN "111000001" => data <= conv_std_logic_vector(398,11);
WHEN "111000010" => data <= conv_std_logic_vector(397,11);
WHEN "111000011" => data <= conv_std_logic_vector(397,11);
WHEN "111000100" => data <= conv_std_logic_vector(396,11);
WHEN "111000101" => data <= conv_std_logic_vector(395,11);
WHEN "111000110" => data <= conv_std_logic_vector(395,11);
WHEN "111000111" => data <= conv_std_logic_vector(394,11);
WHEN "111001000" => data <= conv_std_logic_vector(394,11);
WHEN "111001001" => data <= conv_std_logic_vector(393,11);
WHEN "111001010" => data <= conv_std_logic_vector(392,11);
WHEN "111001011" => data <= conv_std_logic_vector(392,11);
WHEN "111001100" => data <= conv_std_logic_vector(391,11);
WHEN "111001101" => data <= conv_std_logic_vector(391,11);
WHEN "111001110" => data <= conv_std_logic_vector(390,11);
WHEN "111001111" => data <= conv_std_logic_vector(389,11);
WHEN "111010000" => data <= conv_std_logic_vector(389,11);
WHEN "111010001" => data <= conv_std_logic_vector(388,11);
WHEN "111010010" => data <= conv_std_logic_vector(388,11);
WHEN "111010011" => data <= conv_std_logic_vector(387,11);
WHEN "111010100" => data <= conv_std_logic_vector(386,11);
WHEN "111010101" => data <= conv_std_logic_vector(386,11);
WHEN "111010110" => data <= conv_std_logic_vector(385,11);
WHEN "111010111" => data <= conv_std_logic_vector(385,11);
WHEN "111011000" => data <= conv_std_logic_vector(384,11);
WHEN "111011001" => data <= conv_std_logic_vector(383,11);
WHEN "111011010" => data <= conv_std_logic_vector(383,11);
WHEN "111011011" => data <= conv_std_logic_vector(382,11);
WHEN "111011100" => data <= conv_std_logic_vector(382,11);
WHEN "111011101" => data <= conv_std_logic_vector(381,11);
WHEN "111011110" => data <= conv_std_logic_vector(381,11);
WHEN "111011111" => data <= conv_std_logic_vector(380,11);
WHEN "111100000" => data <= conv_std_logic_vector(379,11);
WHEN "111100001" => data <= conv_std_logic_vector(379,11);
WHEN "111100010" => data <= conv_std_logic_vector(378,11);
WHEN "111100011" => data <= conv_std_logic_vector(378,11);
WHEN "111100100" => data <= conv_std_logic_vector(377,11);
WHEN "111100101" => data <= conv_std_logic_vector(377,11);
WHEN "111100110" => data <= conv_std_logic_vector(376,11);
WHEN "111100111" => data <= conv_std_logic_vector(375,11);
WHEN "111101000" => data <= conv_std_logic_vector(375,11);
WHEN "111101001" => data <= conv_std_logic_vector(374,11);
WHEN "111101010" => data <= conv_std_logic_vector(374,11);
WHEN "111101011" => data <= conv_std_logic_vector(373,11);
WHEN "111101100" => data <= conv_std_logic_vector(373,11);
WHEN "111101101" => data <= conv_std_logic_vector(372,11);
WHEN "111101110" => data <= conv_std_logic_vector(372,11);
WHEN "111101111" => data <= conv_std_logic_vector(371,11);
WHEN "111110000" => data <= conv_std_logic_vector(370,11);
WHEN "111110001" => data <= conv_std_logic_vector(370,11);
WHEN "111110010" => data <= conv_std_logic_vector(369,11);
WHEN "111110011" => data <= conv_std_logic_vector(369,11);
WHEN "111110100" => data <= conv_std_logic_vector(368,11);
WHEN "111110101" => data <= conv_std_logic_vector(368,11);
WHEN "111110110" => data <= conv_std_logic_vector(367,11);
WHEN "111110111" => data <= conv_std_logic_vector(367,11);
WHEN "111111000" => data <= conv_std_logic_vector(366,11);
WHEN "111111001" => data <= conv_std_logic_vector(366,11);
WHEN "111111010" => data <= conv_std_logic_vector(365,11);
WHEN "111111011" => data <= conv_std_logic_vector(364,11);
WHEN "111111100" => data <= conv_std_logic_vector(364,11);
WHEN "111111101" => data <= conv_std_logic_vector(363,11);
WHEN "111111110" => data <= conv_std_logic_vector(363,11);
WHEN "111111111" => data <= conv_std_logic_vector(362,11);
WHEN others => data <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_sqrroot.vhd | 10 | 5288 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--********************************************************************
--*** ***
--*** FP_SQRROOT.VHD ***
--*** ***
--*** Fixed Point Square Root Core - Restoring ***
--*** ***
--*** 21/12/06 ML ***
--*** ***
--*** Copyright Altera 2006 ***
--*** ***
--*** ***
--********************************************************************
ENTITY fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_sqrroot;
ARCHITECTURE rtl OF fp_sqrroot IS
type nodetype IS ARRAY (width DOWNTO 1) OF STD_LOGIC_VECTOR (width+2 DOWNTO 1);
type qfftype IS ARRAY (width-1 DOWNTO 1) OF STD_LOGIC_VECTOR (width-1 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width DOWNTO 1);
signal onevec : STD_LOGIC_VECTOR (width+1 DOWNTO 1);
signal subnode, slevel, qlevel, radff : nodetype;
signal qff : qfftype;
BEGIN
gza: FOR k IN 1 TO width GENERATE
zerovec(k) <= '0';
END GENERATE;
onevec <= "01" & zerovec(width-1 DOWNTO 1);
-- 1 <= input range < 4, therefore 1 <= root < 2
-- input may be shifted left by 1, therefore first subtract "001" not "01"
slevel(1)(width+2 DOWNTO 1) <= '0' & rad;
qlevel(1)(width+2 DOWNTO 1) <= "001" & zerovec(width-1 DOWNTO 1);
subnode(1)(width+2 DOWNTO width) <= slevel(1)(width+2 DOWNTO width) - qlevel(1)(width+2 DOWNTO width);
subnode(1)(width-1 DOWNTO 1) <= slevel(1)(width-1 DOWNTO 1);
slevel(2)(width+2 DOWNTO 1) <= radff(1)(width+1 DOWNTO 1) & '0';
qlevel(2)(width+2 DOWNTO 1) <= "0101" & zerovec(width-2 DOWNTO 1);
subnode(2)(width+2 DOWNTO width-1) <= slevel(2)(width+2 DOWNTO width-1) - qlevel(2)(width+2 DOWNTO width-1);
subnode(2)(width-2 DOWNTO 1) <= slevel(2)(width-2 DOWNTO 1);
gla: FOR k IN 3 TO width GENERATE
glb: FOR j IN 1 TO k-2 GENERATE
qlevel(k)(width+1-j) <= qff(width-j)(k-1-j);
END GENERATE;
END GENERATE;
gsa: FOR k IN 3 TO width-1 GENERATE
slevel(k)(width+2 DOWNTO 1) <= radff(k-1)(width+1 DOWNTO 1) & '0';
qlevel(k)(width+2 DOWNTO width+1) <= "01";
qlevel(k)(width+2-k DOWNTO 1) <= "01" & zerovec(width-k DOWNTO 1);
subnode(k)(width+2 DOWNTO width+1-k) <= slevel(k)(width+2 DOWNTO width+1-k) -
qlevel(k)(width+2 DOWNTO width+1-k);
subnode(k)(width-k DOWNTO 1) <= slevel(k)(width-k DOWNTO 1);
END GENERATE;
slevel(width)(width+2 DOWNTO 1) <= radff(width-1)(width+1 DOWNTO 1) & '0';
qlevel(width)(width+2 DOWNTO width+1) <= "01";
qlevel(width)(2 DOWNTO 1) <= "01";
subnode(width)(width+2 DOWNTO 1) <= slevel(width)(width+2 DOWNTO 1) - qlevel(width)(width+2 DOWNTO 1);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
FOR j IN 1 TO width+2 LOOP
radff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO width-1 LOOP
FOR j IN 1 TO width-1 LOOP
qff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
radff(1)(width+2 DOWNTO 1) <= subnode(1)(width+2 DOWNTO 1);
FOR k IN 2 TO width LOOP
FOR j IN 1 TO width+2 LOOP
radff(k)(j) <= (slevel(k)(j) AND subnode(k)(width+2)) OR
(subnode(k)(j) AND NOT(subnode(k)(width+2)));
END LOOP;
END LOOP;
FOR k IN 1 TO width-1 LOOP
qff(width-k)(1) <= NOT(subnode(k+1)(width+2));
FOR j IN 2 TO width-1 LOOP
qff(k)(j) <= qff(k)(j-1);
END LOOP;
END LOOP;
END IF;
END IF;
END PROCESS;
fro: FOR k IN 1 TO width-1 GENERATE
root(k) <= qff(k)(k);
END GENERATE;
root(width) <= '1';
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/dp_divnornd.vhd | 10 | 5286 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION DIVIDER - OUTPUT STAGE ***
--*** ***
--*** DP_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY dp_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END dp_divnornd;
ARCHITECTURE rtl OF dp_divnornd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
nanff <= '0';
dividebyzeroff <= '0';
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
nanff <= nanin;
dividebyzeroff <= dividebyzeroin;
-- nan takes precedence (set max)
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (mantissadiv(k+1) AND setmanzero) OR setmanmax;
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponentff(k) <= (exponentdiv(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent >= 255
infinitygen(1) <= exponentdiv(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentdiv(k);
END GENERATE;
infinitygen(expwidth+1) <= infinitygen(expwidth) OR
(exponentdiv(expwidth+1) AND
NOT(exponentdiv(expwidth+2))); -- ;1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentdiv(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentdiv(k);
END GENERATE;
zerogen(expwidth+1) <= zerogen(expwidth) AND
NOT(exponentdiv(expwidth+2)); -- '0' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(dividebyzeroin);
-- setmantissa to "11..11" when nan
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth+1);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanin OR infinitygen(expwidth+1) OR dividebyzeroin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff(expwidth DOWNTO 1);
-----------------------------------------------
nanout <= nanff;
invalidout <= nanff;
dividebyzeroout <= dividebyzeroff;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/dotp_core_sv.vhd | 10 | 13923 | LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/FPSinCosXDPS5f375_safe_path.vhd | 10 | 427 | -- safe_path for FPSinCosXDPS5f375 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE FPSinCosXDPS5f375_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END FPSinCosXDPS5f375_safe_path;
PACKAGE body FPSinCosXDPS5f375_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END FPSinCosXDPS5f375_safe_path;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_range1.vhd | 10 | 12008 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Core. Output as a fraction of 2PI. ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range1 IS
GENERIC (device : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_range1;
ARCHITECTURE rtl of fp_range1 IS
type rangeexponentfftype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissadelff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissamultipliernode : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissamultiplierff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaexponentnode : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal leadnode, leadff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal rangeexponentff : rangeexponentfftype;
signal negrangeexponentff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal tableaddressff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal basefractionnode, basefractionff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal incmantissanode, incmantissaff : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal incexponentnode, incexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal basefractiondelnode, basefractiondelff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (79 DOWNTO 1);
signal multipliernormnode : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal multipliernormff : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal leftrotatenode, rightrotatenode : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal leftrotateff, rightrotateff : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal rotatenode : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal rotateff : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal selectrotateff : STD_LOGIC;
signal circlenode : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal circleff : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal negbasefractiondelnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negbasefractiondelff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negrotatenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcirclenode : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal negcircleff : STD_LOGIC_VECTOR (37 DOWNTO 1);
component fp_clz23
PORT (
mantissa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
component fp_lsft23
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_lsft78
PORT (
inbus : IN STD_LOGIC_VECTOR (78 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (78 DOWNTO 1)
);
end component;
component fp_rsft78
PORT (
inbus : IN STD_LOGIC_VECTOR (78 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (78 DOWNTO 1)
);
end component;
component fp_range_table1
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
end component;
component fp_mul23x56 IS
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= '0';
mantissadelff(k) <= '0';
mantissamultiplierff(k) <= '0';
END LOOP;
exponentff <= "00000000";
FOR k IN 1 TO 6 LOOP
rangeexponentff(k)(9 DOWNTO 1) <= "000000000";
END LOOP;
negrangeexponentff(9 DOWNTO 1) <= "000000000";
leadff <= "00000";
tableaddressff <= "00000000";
FOR k IN 1 TO 36 LOOP
basefractionff(k) <= '0';
END LOOP;
FOR k IN 1 TO 56 LOOP
incmantissaff(k) <= '0';
END LOOP;
incexponentff <= "00000000";
FOR k IN 1 TO 78 LOOP
multipliernormff(k) <= '0';
leftrotateff(k) <= '0';
rightrotateff(k) <= '0';
END LOOP;
selectrotateff <= '0';
FOR k IN 1 TO 37 LOOP
circleff(k) <= '0';
negcircleff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mantissaff <= mantissain; -- level 1
mantissadelff <= mantissaff; -- level 2
exponentff <= exponentin; -- level 1
leadff <= leadnode; -- level 2
mantissamultiplierff <= mantissamultipliernode; -- level 3
tableaddressff <= exponentff; -- level 2
basefractionff <= basefractionnode; -- level 3
incmantissaff <= incmantissanode; -- level 3
incexponentff <= incexponentnode; -- level 3
rangeexponentff(1)(9 DOWNTO 1) <= mantissaexponentnode; -- levels 3,4,5,6,7, and 8
rangeexponentff(2)(9 DOWNTO 1) <= rangeexponentff(1)(9 DOWNTO 1) - ('0' & incexponentff);
rangeexponentff(3)(9 DOWNTO 1) <= rangeexponentff(2)(9 DOWNTO 1);
rangeexponentff(4)(9 DOWNTO 1) <= rangeexponentff(3)(9 DOWNTO 1);
rangeexponentff(5)(9 DOWNTO 1) <= rangeexponentff(4)(9 DOWNTO 1);
rangeexponentff(6)(9 DOWNTO 1) <= rangeexponentff(5)(9 DOWNTO 1) - ("00000000" & NOT(multipliernode(79)));
negrangeexponentff <= "100000000" -
(rangeexponentff(5)(9 DOWNTO 1) -
("00000000" & NOT(multipliernode(79)))); -- level 8
multipliernormff <= multipliernormnode;
leftrotateff <= leftrotatenode;
rightrotateff <= rightrotatenode;
rotateff <= rotatenode;
selectrotateff <= negrangeexponentff(9);
basefractiondelff <= basefractiondelnode;
negbasefractiondelff <= negbasefractiondelnode;
circleff <= circlenode;
negcircleff <= negcirclenode;
END IF;
END IF;
END PROCESS;
cbfd: fp_del
GENERIC MAP (width=>36,pipes=>6)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>basefractionff,
cc=>basefractiondelnode);
--turn mantissa fractional part into floating point number
-- level 1 in
cclzin: fp_clz23
PORT MAP (mantissa=>mantissaff,leading=>leadnode);
-- need to do this shift so that both mult inputs normalized, so we can see
-- if 1 bit mult output normalization required
-- level 2 in
csftin: fp_lsft23
PORT MAP (inbus=>mantissadelff,shift=>leadff,
outbus=>mantissamultipliernode);
-- exponents (expin, baseexp, incexp) reversed
-- exponents show shift from 0.9999 posisition
-- ex: 0.111e3 = 0.000111, 0.111e5 = 0.00000111
-- if no shift, expin = 23
-- ex: mantissain = 123, after shift = 0.1111011 (0.96), same as 7
-- level 2 in
mantissaexponentnode <= "000010111" - ("0000" & leadff); -- 23 - shift
-- level 2 in
clut: fp_range_table1
PORT MAP (address=>tableaddressff,
basefraction=>basefractionnode,
incmantissa=>incmantissanode,
incexponent=>incexponentnode);
-- 23 x 56 = 79 bits
-- mantissamulin, incman both in range 0.5 to 0.9999, so result is range 0.25 to 0.999
-- if < 0.5, shift left and add 1 to exponent
-- levels 4,5,6,7
cmul: fp_mul23x56
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mantissamultiplierff,databb=>incmantissaff,
result=>multipliernode);
-- level 7 in
gma: FOR k IN 1 TO 78 GENERATE
multipliernormnode(k) <= (multipliernode(k+1) AND multipliernode(79)) OR
(multipliernode(k) AND NOT(multipliernode(79)));
END GENERATE;
lftsft: fp_lsft78
PORT MAP (inbus=>multipliernormff,shift=>rangeexponentff(6)(6 DOWNTO 1),
outbus=>leftrotatenode);
rgtsft: fp_rsft78
PORT MAP (inbus=>multipliernormff,shift=>negrangeexponentff(6 DOWNTO 1),
outbus=>rightrotatenode);
gra: FOR k IN 1 TO 78 GENERATE
rotatenode(k) <= (leftrotateff(k) AND NOT(selectrotateff)) OR
(rightrotateff(k) AND selectrotateff);
END GENERATE;
-- use 3-1 adder to round as well?
-- max will be 1.9999, but only interested in fractional part
circlenode <= ('0' & basefractiondelff) + ('0' & rotateff(78 DOWNTO 43));
negbasefractiondelnode <= 0 - (basefractiondelnode(36 DOWNTO 1));
gnra: FOR k IN 1 TO 36 GENERATE
negrotatenode(k) <= NOT(rotateff(k+42));
END GENERATE;
negcirclenode <= ('1' & negbasefractiondelff) + ('1' & negrotatenode) + 1;
-- fractional part of 2pi will be circle(36 DOWNTO 1)
circle <= circleff(36 DOWNTO 1);
negcircle <= negcircleff(36 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_exp_double_s5.vhd | 10 | 750433 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_double_s5
-- VHDL created on Thu Apr 11 10:14:45 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid8_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid11_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstZeroWEP1_uid12_fpExpETest_q : std_logic_vector (11 downto 0);
signal cstBiasPWE_uid13_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExpETest_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid15_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid16_fpExpETest_q : std_logic_vector (51 downto 0);
signal exc_R_uid30_fpExpETest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_q : std_logic_vector(0 downto 0);
signal zY_uid60_fpExpETest_q : std_logic_vector (54 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_a : std_logic_vector(15 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_b : std_logic_vector(15 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_o : std_logic_vector (15 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_q : std_logic_vector (14 downto 0);
signal oneFracRPostExc2_uid90_fpExpETest_q : std_logic_vector (51 downto 0);
signal p8_uid109_constMult_q : std_logic_vector(61 downto 0);
signal p6_uid111_constMult_q : std_logic_vector(49 downto 0);
signal p4_uid113_constMult_q : std_logic_vector(37 downto 0);
signal p2_uid115_constMult_q : std_logic_vector(25 downto 0);
signal lev1_a0_uid118_constMult_a : std_logic_vector(63 downto 0);
signal lev1_a0_uid118_constMult_b : std_logic_vector(63 downto 0);
signal lev1_a0_uid118_constMult_o : std_logic_vector (63 downto 0);
signal lev1_a0_uid118_constMult_q : std_logic_vector (62 downto 0);
signal lev1_a2_uid120_constMult_a : std_logic_vector(38 downto 0);
signal lev1_a2_uid120_constMult_b : std_logic_vector(38 downto 0);
signal lev1_a2_uid120_constMult_o : std_logic_vector (38 downto 0);
signal lev1_a2_uid120_constMult_q : std_logic_vector (38 downto 0);
signal lev2_a0_uid122_constMult_a : std_logic_vector(64 downto 0);
signal lev2_a0_uid122_constMult_b : std_logic_vector(64 downto 0);
signal lev2_a0_uid122_constMult_o : std_logic_vector (64 downto 0);
signal lev2_a0_uid122_constMult_q : std_logic_vector (63 downto 0);
signal lev3_a0_uid124_constMult_a : std_logic_vector(65 downto 0);
signal lev3_a0_uid124_constMult_b : std_logic_vector(65 downto 0);
signal lev3_a0_uid124_constMult_o : std_logic_vector (65 downto 0);
signal lev3_a0_uid124_constMult_q : std_logic_vector (64 downto 0);
signal z_uid129_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (31 downto 0);
signal z_uid133_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(68 downto 0);
signal z_uid141_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(7 downto 0);
signal z_uid145_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(15 downto 0);
signal z_uid149_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(23 downto 0);
signal z_uid155_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(1 downto 0);
signal z_uid159_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(3 downto 0);
signal z_uid163_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(0 downto 0);
signal p2_uid179_constMult_q : std_logic_vector(76 downto 0);
signal lev1_a0_uid182_constMult_a : std_logic_vector(78 downto 0);
signal lev1_a0_uid182_constMult_b : std_logic_vector(78 downto 0);
signal lev1_a0_uid182_constMult_o : std_logic_vector (78 downto 0);
signal lev1_a0_uid182_constMult_q : std_logic_vector (77 downto 0);
signal rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(65 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(23 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid234_exp10TabGen_q : std_logic_vector(39 downto 0);
signal memoryC0_uid235_exp10TabGen_q : std_logic_vector(17 downto 0);
signal memoryC1_uid237_exp10TabGen_q : std_logic_vector(39 downto 0);
signal memoryC1_uid238_exp10TabGen_q : std_logic_vector(10 downto 0);
signal memoryC2_uid240_exp10TabGen_q : std_logic_vector(39 downto 0);
signal memoryC2_uid241_exp10TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid243_exp10TabGen_q : std_logic_vector(34 downto 0);
signal memoryC4_uid245_exp10TabGen_q : std_logic_vector(24 downto 0);
signal memoryC5_uid247_exp10TabGen_q : std_logic_vector(15 downto 0);
signal rndBit_uid263_exp10PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid275_exp10PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_s1 : std_logic_vector (31 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_pr : SIGNED (32 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_q : std_logic_vector (31 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_a : std_logic_vector (24 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_s1 : std_logic_vector (51 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_pr : SIGNED (52 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_q : std_logic_vector (51 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid332_pT5_uid274_exp10PolyEval_pr: signal is "logic";
signal sm0_uid332_pT5_uid274_exp10PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s_type;
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s_type;
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s_type;
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q : std_logic_vector (11 downto 0);
signal reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q : std_logic_vector (13 downto 0);
signal reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q : std_logic_vector (1 downto 0);
signal reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q : std_logic_vector (73 downto 0);
signal reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q : std_logic_vector (74 downto 0);
signal reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q : std_logic_vector (54 downto 0);
signal reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q : std_logic_vector (24 downto 0);
signal reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q : std_logic_vector (36 downto 0);
signal reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q : std_logic_vector (60 downto 0);
signal reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q : std_logic_vector (15 downto 0);
signal reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q : std_logic_vector (2 downto 0);
signal ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a_q : std_logic_vector (54 downto 0);
signal ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a_q : std_logic_vector (0 downto 0);
signal ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q : std_logic_vector (51 downto 0);
signal ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q : std_logic_vector (10 downto 0);
signal ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (52 downto 0);
signal ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (44 downto 0);
signal ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (66 downto 0);
signal ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (64 downto 0);
signal ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (62 downto 0);
signal ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (57 downto 0);
signal ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (49 downto 0);
signal ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (41 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (63 downto 0);
signal ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (61 downto 0);
signal ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (59 downto 0);
signal ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a_q : std_logic_vector (6 downto 0);
signal ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a_q : std_logic_vector (0 downto 0);
signal ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a_q : std_logic_vector (1 downto 0);
signal ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg_q : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq : std_logic;
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top_q : std_logic_vector (2 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q : signal is true;
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg_q : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq : std_logic;
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq : std_logic;
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_reset0 : std_logic;
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q : signal is true;
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg_q : std_logic_vector (51 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg_q : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ia : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_iq : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_q : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q : signal is true;
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq : std_logic;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q : signal is true;
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg_q : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ia : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_iq : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_q : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid42_fpExpETest_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid42_fpExpETest_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid42_fpExpETest_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid42_fpExpETest_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid42_fpExpETest_n : std_logic_vector (0 downto 0);
signal expUdf_uid72_fpExpETest_a : std_logic_vector(18 downto 0);
signal expUdf_uid72_fpExpETest_b : std_logic_vector(18 downto 0);
signal expUdf_uid72_fpExpETest_o : std_logic_vector (18 downto 0);
signal expUdf_uid72_fpExpETest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid72_fpExpETest_n : std_logic_vector (0 downto 0);
signal expOvf_uid74_fpExpETest_a : std_logic_vector(18 downto 0);
signal expOvf_uid74_fpExpETest_b : std_logic_vector(18 downto 0);
signal expOvf_uid74_fpExpETest_o : std_logic_vector (18 downto 0);
signal expOvf_uid74_fpExpETest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid74_fpExpETest_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal oFracXZwE_uid48_fpExpETest_q : std_logic_vector (65 downto 0);
signal InvExpOvfInitial_uid78_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid78_fpExpETest_q : std_logic_vector(0 downto 0);
signal InvSignX_uid81_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid81_fpExpETest_q : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal expX_uid6_fpExpETest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExpETest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExpETest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExpETest_b : std_logic_vector (0 downto 0);
signal frac_uid22_fpExpETest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpExpETest_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid19_fpExpETest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpExpETest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpExpETest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpExpETest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpExpETest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpExpETest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid23_fpExpETest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpExpETest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpExpETest_q : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpExpETest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpExpETest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpExpETest_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_q : std_logic_vector (11 downto 0);
signal shiftVal_uid44_fpExpETest_s : std_logic_vector (0 downto 0);
signal shiftVal_uid44_fpExpETest_q : std_logic_vector (6 downto 0);
signal onesCmpFxpIn_uid49_fpExpETest_a : std_logic_vector(65 downto 0);
signal onesCmpFxpIn_uid49_fpExpETest_b : std_logic_vector(65 downto 0);
signal onesCmpFxpIn_uid49_fpExpETest_q : std_logic_vector(65 downto 0);
signal fxpInExt_uid50_fpExpETest_a : std_logic_vector(67 downto 0);
signal fxpInExt_uid50_fpExpETest_b : std_logic_vector(67 downto 0);
signal fxpInExt_uid50_fpExpETest_o : std_logic_vector (67 downto 0);
signal fxpInExt_uid50_fpExpETest_q : std_logic_vector (66 downto 0);
signal yExt_uid57_fpExpETest_a : std_logic_vector(75 downto 0);
signal yExt_uid57_fpExpETest_b : std_logic_vector(75 downto 0);
signal yExt_uid57_fpExpETest_o : std_logic_vector (75 downto 0);
signal yExt_uid57_fpExpETest_q : std_logic_vector (75 downto 0);
signal yRedPostMux_uid62_fpExpETest_s : std_logic_vector (0 downto 0);
signal yRedPostMux_uid62_fpExpETest_q : std_logic_vector (54 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_a : std_logic_vector(16 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_b : std_logic_vector(16 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_o : std_logic_vector (16 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_q : std_logic_vector (15 downto 0);
signal negInf_uid76_fpExpETest_a : std_logic_vector(0 downto 0);
signal negInf_uid76_fpExpETest_b : std_logic_vector(0 downto 0);
signal negInf_uid76_fpExpETest_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_q : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_a : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_b : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_c : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_q : std_logic_vector(0 downto 0);
signal posInf_uid86_fpExpETest_a : std_logic_vector(0 downto 0);
signal posInf_uid86_fpExpETest_b : std_logic_vector(0 downto 0);
signal posInf_uid86_fpExpETest_q : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_a : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_b : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_c : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_q : std_logic_vector(0 downto 0);
signal excREnc_uid89_fpExpETest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid93_fpExpETest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid93_fpExpETest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid97_fpExpETest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid97_fpExpETest_q : std_logic_vector (10 downto 0);
signal p7_uid110_constMult_q : std_logic_vector(55 downto 0);
signal p5_uid112_constMult_q : std_logic_vector(43 downto 0);
signal p3_uid114_constMult_q : std_logic_vector(31 downto 0);
signal p1_uid116_constMult_q : std_logic_vector(19 downto 0);
signal p0_uid117_constMult_q : std_logic_vector(13 downto 0);
signal lev1_a1_uid119_constMult_a : std_logic_vector(50 downto 0);
signal lev1_a1_uid119_constMult_b : std_logic_vector(50 downto 0);
signal lev1_a1_uid119_constMult_o : std_logic_vector (50 downto 0);
signal lev1_a1_uid119_constMult_q : std_logic_vector (50 downto 0);
signal lev1_a3_uid121_constMult_a : std_logic_vector(26 downto 0);
signal lev1_a3_uid121_constMult_b : std_logic_vector(26 downto 0);
signal lev1_a3_uid121_constMult_o : std_logic_vector (26 downto 0);
signal lev1_a3_uid121_constMult_q : std_logic_vector (26 downto 0);
signal lev2_a1_uid123_constMult_a : std_logic_vector(39 downto 0);
signal lev2_a1_uid123_constMult_b : std_logic_vector(39 downto 0);
signal lev2_a1_uid123_constMult_o : std_logic_vector (39 downto 0);
signal lev2_a1_uid123_constMult_q : std_logic_vector (39 downto 0);
signal lev4_a0_uid125_constMult_a : std_logic_vector(66 downto 0);
signal lev4_a0_uid125_constMult_b : std_logic_vector(66 downto 0);
signal lev4_a0_uid125_constMult_o : std_logic_vector (66 downto 0);
signal lev4_a0_uid125_constMult_q : std_logic_vector (65 downto 0);
signal rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal p1_uid180_constMult_q : std_logic_vector(74 downto 0);
signal p0_uid181_constMult_q : std_logic_vector(68 downto 0);
signal lev2_a0_uid183_constMult_a : std_logic_vector(79 downto 0);
signal lev2_a0_uid183_constMult_b : std_logic_vector(79 downto 0);
signal lev2_a0_uid183_constMult_o : std_logic_vector (79 downto 0);
signal lev2_a0_uid183_constMult_q : std_logic_vector (78 downto 0);
signal rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal ts3_uid265_exp10PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid265_exp10PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid265_exp10PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid265_exp10PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid271_exp10PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid271_exp10PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid271_exp10PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid271_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid277_exp10PolyEval_a : std_logic_vector(61 downto 0);
signal ts5_uid277_exp10PolyEval_b : std_logic_vector(61 downto 0);
signal ts5_uid277_exp10PolyEval_o : std_logic_vector (61 downto 0);
signal ts5_uid277_exp10PolyEval_q : std_logic_vector (61 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal os_uid236_exp10TabGen_q : std_logic_vector (57 downto 0);
signal os_uid239_exp10TabGen_q : std_logic_vector (50 downto 0);
signal os_uid242_exp10TabGen_q : std_logic_vector (42 downto 0);
signal cIncludingRoundingBit_uid264_exp10PolyEval_q : std_logic_vector (44 downto 0);
signal cIncludingRoundingBit_uid270_exp10PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid276_exp10PolyEval_q : std_logic_vector (60 downto 0);
signal prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_in : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b : std_logic_vector (16 downto 0);
signal prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_in : std_logic_vector (51 downto 0);
signal prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b : std_logic_vector (27 downto 0);
signal TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b : std_logic_vector (29 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid65_fpExpETest_in : std_logic_vector (47 downto 0);
signal yPPolyEval_uid65_fpExpETest_b : std_logic_vector (47 downto 0);
signal xTop27Bits_uid303_pT4_uid268_exp10PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid303_pT4_uid268_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_a : std_logic_vector(2 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_b : std_logic_vector(2 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal concExc_uid88_fpExpETest_q : std_logic_vector (2 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid261_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT3_uid261_exp10PolyEval_b : std_logic_vector (34 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid267_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT4_uid267_exp10PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_uid32_fpExpETest_q : std_logic_vector (52 downto 0);
signal InvExpXIsZero_uid29_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpExpETest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpExpETest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpExpETest_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid41_fpExpETest_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid41_fpExpETest_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid43_fpExpETest_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid43_fpExpETest_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (0 downto 0);
signal fxpInPreAlign_uid51_fpExpETest_in : std_logic_vector (65 downto 0);
signal fxpInPreAlign_uid51_fpExpETest_b : std_logic_vector (65 downto 0);
signal YExt75_uid59_fpExpETest_in : std_logic_vector (75 downto 0);
signal YExt75_uid59_fpExpETest_b : std_logic_vector (0 downto 0);
signal yRed_uid61_fpExpETest_in : std_logic_vector (60 downto 0);
signal yRed_uid61_fpExpETest_b : std_logic_vector (54 downto 0);
signal addr_uid64_fpExpETest_in : std_logic_vector (54 downto 0);
signal addr_uid64_fpExpETest_b : std_logic_vector (6 downto 0);
signal expR_uid75_fpExpETest_in : std_logic_vector (10 downto 0);
signal expR_uid75_fpExpETest_b : std_logic_vector (10 downto 0);
signal RExpE_uid98_fpExpETest_q : std_logic_vector (63 downto 0);
signal sR_uid126_constMult_in : std_logic_vector (61 downto 0);
signal sR_uid126_constMult_b : std_logic_vector (57 downto 0);
signal RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (60 downto 0);
signal RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (52 downto 0);
signal RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (44 downto 0);
signal sR_uid184_constMult_in : std_logic_vector (76 downto 0);
signal sR_uid184_constMult_b : std_logic_vector (74 downto 0);
signal RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (57 downto 0);
signal RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (49 downto 0);
signal RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (41 downto 0);
signal s3_uid266_exp10PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid266_exp10PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid272_exp10PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid272_exp10PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid278_exp10PolyEval_in : std_logic_vector (61 downto 0);
signal s5_uid278_exp10PolyEval_b : std_logic_vector (60 downto 0);
signal lowRangeB_uid251_exp10PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid251_exp10PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid252_exp10PolyEval_in : std_logic_vector (16 downto 0);
signal highBBits_uid252_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal lowRangeB_uid257_exp10PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_exp10PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_exp10PolyEval_in : std_logic_vector (27 downto 0);
signal highBBits_uid258_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal lowRangeB_uid298_pT3_uid262_exp10PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid298_pT3_uid262_exp10PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid299_pT3_uid262_exp10PolyEval_in : std_logic_vector (29 downto 0);
signal highBBits_uid299_pT3_uid262_exp10PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid313_pT4_uid268_exp10PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid313_pT4_uid268_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid314_pT4_uid268_exp10PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid314_pT4_uid268_exp10PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid334_pT5_uid274_exp10PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid334_pT5_uid274_exp10PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid335_pT5_uid274_exp10PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid335_pT5_uid274_exp10PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (66 downto 0);
signal RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (64 downto 0);
signal RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (62 downto 0);
signal RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (67 downto 0);
signal RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (63 downto 0);
signal RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (61 downto 0);
signal RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (59 downto 0);
signal RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (64 downto 0);
signal yT1_uid249_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT1_uid249_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal yT2_uid255_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT2_uid255_exp10PolyEval_b : std_logic_vector (24 downto 0);
signal xTop27Bits_uid318_pT5_uid274_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal xBottomBits_uid322_pT5_uid274_exp10PolyEval_in : std_logic_vector (20 downto 0);
signal xBottomBits_uid322_pT5_uid274_exp10PolyEval_b : std_logic_vector (20 downto 0);
signal xTop26Bits_uid323_pT5_uid274_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid331_pT5_uid274_exp10PolyEval_in : std_logic_vector (20 downto 0);
signal sSM0W_uid331_pT5_uid274_exp10PolyEval_b : std_logic_vector (2 downto 0);
signal xTop27Bits_uid286_pT3_uid262_exp10PolyEval_in : std_logic_vector (34 downto 0);
signal xTop27Bits_uid286_pT3_uid262_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid289_pT3_uid262_exp10PolyEval_in : std_logic_vector (34 downto 0);
signal xTop18Bits_uid289_pT3_uid262_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid291_pT3_uid262_exp10PolyEval_in : std_logic_vector (7 downto 0);
signal xBottomBits_uid291_pT3_uid262_exp10PolyEval_b : std_logic_vector (7 downto 0);
signal xBottomBits_uid307_pT4_uid268_exp10PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid307_pT4_uid268_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal oFracX_uid33_fpExpETest_q : std_logic_vector (53 downto 0);
signal exc_N_uid26_fpExpETest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpExpETest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpExpETest_q : std_logic_vector(0 downto 0);
signal msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (0 downto 0);
signal X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (33 downto 0);
signal X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (1 downto 0);
signal oFracXZwE_uid39_fpExpETest_q : std_logic_vector (68 downto 0);
signal yTop27Bits_uid304_pT4_uid268_exp10PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid306_pT4_uid268_exp10PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid306_pT4_uid268_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid319_pT5_uid274_exp10PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid319_pT5_uid274_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid321_pT5_uid274_exp10PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid321_pT5_uid274_exp10PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid330_pT5_uid274_exp10PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid330_pT5_uid274_exp10PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid67_fpExpETest_in : std_logic_vector (57 downto 0);
signal peOR_uid67_fpExpETest_b : std_logic_vector (52 downto 0);
signal peORExpInc_uid68_fpExpETest_in : std_logic_vector (58 downto 0);
signal peORExpInc_uid68_fpExpETest_b : std_logic_vector (0 downto 0);
signal sumAHighB_uid253_exp10PolyEval_a : std_logic_vector(25 downto 0);
signal sumAHighB_uid253_exp10PolyEval_b : std_logic_vector(25 downto 0);
signal sumAHighB_uid253_exp10PolyEval_o : std_logic_vector (25 downto 0);
signal sumAHighB_uid253_exp10PolyEval_q : std_logic_vector (25 downto 0);
signal sumAHighB_uid259_exp10PolyEval_a : std_logic_vector(35 downto 0);
signal sumAHighB_uid259_exp10PolyEval_b : std_logic_vector(35 downto 0);
signal sumAHighB_uid259_exp10PolyEval_o : std_logic_vector (35 downto 0);
signal sumAHighB_uid259_exp10PolyEval_q : std_logic_vector (35 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_q : std_logic_vector (25 downto 0);
signal onesCmpFxpInX_uid34_fpExpETest_a : std_logic_vector(53 downto 0);
signal onesCmpFxpInX_uid34_fpExpETest_b : std_logic_vector(53 downto 0);
signal onesCmpFxpInX_uid34_fpExpETest_q : std_logic_vector(53 downto 0);
signal InvExc_N_uid27_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpExpETest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal msbx_uid128_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (0 downto 0);
signal X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (36 downto 0);
signal X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (4 downto 0);
signal fracR_uid71_fpExpETest_in : std_logic_vector (51 downto 0);
signal fracR_uid71_fpExpETest_b : std_logic_vector (51 downto 0);
signal s1_uid251_uid254_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal s2_uid257_uid260_exp10PolyEval_q : std_logic_vector (36 downto 0);
signal add0_uid298_uid301_pT3_uid262_exp10PolyEval_q : std_logic_vector (55 downto 0);
signal add0_uid313_uid316_pT4_uid268_exp10PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid334_uid337_pT5_uid274_exp10PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal fxpInExtX_uid35_fpExpETest_a : std_logic_vector(55 downto 0);
signal fxpInExtX_uid35_fpExpETest_b : std_logic_vector(55 downto 0);
signal fxpInExtX_uid35_fpExpETest_o : std_logic_vector (55 downto 0);
signal fxpInExtX_uid35_fpExpETest_q : std_logic_vector (54 downto 0);
signal rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal yTop27Bits_uid287_pT3_uid262_exp10PolyEval_in : std_logic_vector (36 downto 0);
signal yTop27Bits_uid287_pT3_uid262_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid290_pT3_uid262_exp10PolyEval_in : std_logic_vector (9 downto 0);
signal yBottomBits_uid290_pT3_uid262_exp10PolyEval_b : std_logic_vector (9 downto 0);
signal yTop18Bits_uid292_pT3_uid262_exp10PolyEval_in : std_logic_vector (36 downto 0);
signal yTop18Bits_uid292_pT3_uid262_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal R_uid302_pT3_uid262_exp10PolyEval_in : std_logic_vector (54 downto 0);
signal R_uid302_pT3_uid262_exp10PolyEval_b : std_logic_vector (36 downto 0);
signal R_uid317_pT4_uid268_exp10PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid317_pT4_uid268_exp10PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid338_pT5_uid274_exp10PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid338_pT5_uid274_exp10PolyEval_b : std_logic_vector (54 downto 0);
signal ePreRnd_uid46_fpExpETest_in : std_logic_vector (68 downto 0);
signal ePreRnd_uid46_fpExpETest_b : std_logic_vector (13 downto 0);
signal pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_q : std_logic_vector (73 downto 0);
signal fxpInPreAlign_uid36_fpExpETest_in : std_logic_vector (53 downto 0);
signal fxpInPreAlign_uid36_fpExpETest_b : std_logic_vector (53 downto 0);
signal spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval_q : std_logic_vector (10 downto 0);
signal xv0_uid176_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid176_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid177_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid177_constMult_b : std_logic_vector (5 downto 0);
signal xv2_uid178_constMult_in : std_logic_vector (13 downto 0);
signal xv2_uid178_constMult_b : std_logic_vector (1 downto 0);
signal xv0_uid100_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid100_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid101_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid101_constMult_b : std_logic_vector (5 downto 0);
signal xv2_uid102_constMult_in : std_logic_vector (17 downto 0);
signal xv2_uid102_constMult_b : std_logic_vector (5 downto 0);
signal xv3_uid103_constMult_in : std_logic_vector (23 downto 0);
signal xv3_uid103_constMult_b : std_logic_vector (5 downto 0);
signal xv4_uid104_constMult_in : std_logic_vector (29 downto 0);
signal xv4_uid104_constMult_b : std_logic_vector (5 downto 0);
signal xv5_uid105_constMult_in : std_logic_vector (35 downto 0);
signal xv5_uid105_constMult_b : std_logic_vector (5 downto 0);
signal xv6_uid106_constMult_in : std_logic_vector (41 downto 0);
signal xv6_uid106_constMult_b : std_logic_vector (5 downto 0);
signal xv7_uid107_constMult_in : std_logic_vector (47 downto 0);
signal xv7_uid107_constMult_b : std_logic_vector (5 downto 0);
signal xv8_uid108_constMult_in : std_logic_vector (53 downto 0);
signal xv8_uid108_constMult_b : std_logic_vector (5 downto 0);
signal pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_q : std_logic_vector (17 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid15_fpExpETest(CONSTANT,14)
cstAllOWE_uid15_fpExpETest_q <= "11111111111";
--zY_uid60_fpExpETest(CONSTANT,59)
zY_uid60_fpExpETest_q <= "0000000000000000000000000000000000000000000000000000000";
--signX_uid7_fpExpETest(BITSELECT,6)@0
signX_uid7_fpExpETest_in <= a;
signX_uid7_fpExpETest_b <= signX_uid7_fpExpETest_in(63 downto 63);
--frac_uid22_fpExpETest(BITSELECT,21)@0
frac_uid22_fpExpETest_in <= a(51 downto 0);
frac_uid22_fpExpETest_b <= frac_uid22_fpExpETest_in(51 downto 0);
--oFracX_uid32_uid32_fpExpETest(BITJOIN,31)@0
oFracX_uid32_uid32_fpExpETest_q <= VCC_q & frac_uid22_fpExpETest_b;
--oFracX_uid33_fpExpETest(BITJOIN,32)@0
oFracX_uid33_fpExpETest_q <= GND_q & oFracX_uid32_uid32_fpExpETest_q;
--onesCmpFxpInX_uid34_fpExpETest(LOGICAL,33)@0
onesCmpFxpInX_uid34_fpExpETest_a <= oFracX_uid33_fpExpETest_q;
onesCmpFxpInX_uid34_fpExpETest_b <= STD_LOGIC_VECTOR((53 downto 1 => signX_uid7_fpExpETest_b(0)) & signX_uid7_fpExpETest_b);
onesCmpFxpInX_uid34_fpExpETest_q <= onesCmpFxpInX_uid34_fpExpETest_a xor onesCmpFxpInX_uid34_fpExpETest_b;
--fxpInExtX_uid35_fpExpETest(ADD,34)@0
fxpInExtX_uid35_fpExpETest_a <= STD_LOGIC_VECTOR((55 downto 54 => onesCmpFxpInX_uid34_fpExpETest_q(53)) & onesCmpFxpInX_uid34_fpExpETest_q);
fxpInExtX_uid35_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000000000000000000000000000" & signX_uid7_fpExpETest_b);
fxpInExtX_uid35_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExtX_uid35_fpExpETest_a) + SIGNED(fxpInExtX_uid35_fpExpETest_b));
fxpInExtX_uid35_fpExpETest_q <= fxpInExtX_uid35_fpExpETest_o(54 downto 0);
--fxpInPreAlign_uid36_fpExpETest(BITSELECT,35)@0
fxpInPreAlign_uid36_fpExpETest_in <= fxpInExtX_uid35_fpExpETest_q(53 downto 0);
fxpInPreAlign_uid36_fpExpETest_b <= fxpInPreAlign_uid36_fpExpETest_in(53 downto 0);
--xv0_uid100_constMult(BITSELECT,99)@0
xv0_uid100_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(5 downto 0);
xv0_uid100_constMult_b <= xv0_uid100_constMult_in(5 downto 0);
--reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0(REG,350)@0
reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q <= xv0_uid100_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a(DELAY,529)@1
ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q, xout => ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid117_constMult(LOOKUP,116)@5
p0_uid117_constMult: PROCESS (ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q) IS
WHEN "000000" => p0_uid117_constMult_q <= "00000000000000";
WHEN "000001" => p0_uid117_constMult_q <= "00000010111001";
WHEN "000010" => p0_uid117_constMult_q <= "00000101110001";
WHEN "000011" => p0_uid117_constMult_q <= "00001000101010";
WHEN "000100" => p0_uid117_constMult_q <= "00001011100011";
WHEN "000101" => p0_uid117_constMult_q <= "00001110011011";
WHEN "000110" => p0_uid117_constMult_q <= "00010001010100";
WHEN "000111" => p0_uid117_constMult_q <= "00010100001101";
WHEN "001000" => p0_uid117_constMult_q <= "00010111000101";
WHEN "001001" => p0_uid117_constMult_q <= "00011001111110";
WHEN "001010" => p0_uid117_constMult_q <= "00011100110111";
WHEN "001011" => p0_uid117_constMult_q <= "00011111101111";
WHEN "001100" => p0_uid117_constMult_q <= "00100010101000";
WHEN "001101" => p0_uid117_constMult_q <= "00100101100001";
WHEN "001110" => p0_uid117_constMult_q <= "00101000011001";
WHEN "001111" => p0_uid117_constMult_q <= "00101011010010";
WHEN "010000" => p0_uid117_constMult_q <= "00101110001011";
WHEN "010001" => p0_uid117_constMult_q <= "00110001000011";
WHEN "010010" => p0_uid117_constMult_q <= "00110011111100";
WHEN "010011" => p0_uid117_constMult_q <= "00110110110101";
WHEN "010100" => p0_uid117_constMult_q <= "00111001101101";
WHEN "010101" => p0_uid117_constMult_q <= "00111100100110";
WHEN "010110" => p0_uid117_constMult_q <= "00111111011111";
WHEN "010111" => p0_uid117_constMult_q <= "01000010010111";
WHEN "011000" => p0_uid117_constMult_q <= "01000101010000";
WHEN "011001" => p0_uid117_constMult_q <= "01001000001001";
WHEN "011010" => p0_uid117_constMult_q <= "01001011000001";
WHEN "011011" => p0_uid117_constMult_q <= "01001101111010";
WHEN "011100" => p0_uid117_constMult_q <= "01010000110011";
WHEN "011101" => p0_uid117_constMult_q <= "01010011101011";
WHEN "011110" => p0_uid117_constMult_q <= "01010110100100";
WHEN "011111" => p0_uid117_constMult_q <= "01011001011101";
WHEN "100000" => p0_uid117_constMult_q <= "01011100010101";
WHEN "100001" => p0_uid117_constMult_q <= "01011111001110";
WHEN "100010" => p0_uid117_constMult_q <= "01100010000111";
WHEN "100011" => p0_uid117_constMult_q <= "01100100111111";
WHEN "100100" => p0_uid117_constMult_q <= "01100111111000";
WHEN "100101" => p0_uid117_constMult_q <= "01101010110001";
WHEN "100110" => p0_uid117_constMult_q <= "01101101101001";
WHEN "100111" => p0_uid117_constMult_q <= "01110000100010";
WHEN "101000" => p0_uid117_constMult_q <= "01110011011011";
WHEN "101001" => p0_uid117_constMult_q <= "01110110010011";
WHEN "101010" => p0_uid117_constMult_q <= "01111001001100";
WHEN "101011" => p0_uid117_constMult_q <= "01111100000101";
WHEN "101100" => p0_uid117_constMult_q <= "01111110111101";
WHEN "101101" => p0_uid117_constMult_q <= "10000001110110";
WHEN "101110" => p0_uid117_constMult_q <= "10000100101111";
WHEN "101111" => p0_uid117_constMult_q <= "10000111100111";
WHEN "110000" => p0_uid117_constMult_q <= "10001010100000";
WHEN "110001" => p0_uid117_constMult_q <= "10001101011001";
WHEN "110010" => p0_uid117_constMult_q <= "10010000010001";
WHEN "110011" => p0_uid117_constMult_q <= "10010011001010";
WHEN "110100" => p0_uid117_constMult_q <= "10010110000011";
WHEN "110101" => p0_uid117_constMult_q <= "10011000111011";
WHEN "110110" => p0_uid117_constMult_q <= "10011011110100";
WHEN "110111" => p0_uid117_constMult_q <= "10011110101101";
WHEN "111000" => p0_uid117_constMult_q <= "10100001100101";
WHEN "111001" => p0_uid117_constMult_q <= "10100100011110";
WHEN "111010" => p0_uid117_constMult_q <= "10100111010111";
WHEN "111011" => p0_uid117_constMult_q <= "10101010001111";
WHEN "111100" => p0_uid117_constMult_q <= "10101101001000";
WHEN "111101" => p0_uid117_constMult_q <= "10110000000001";
WHEN "111110" => p0_uid117_constMult_q <= "10110010111001";
WHEN "111111" => p0_uid117_constMult_q <= "10110101110010";
WHEN OTHERS =>
p0_uid117_constMult_q <= "00000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid101_constMult(BITSELECT,100)@0
xv1_uid101_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(11 downto 0);
xv1_uid101_constMult_b <= xv1_uid101_constMult_in(11 downto 6);
--ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a(DELAY,803)@0
ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 3 )
PORT MAP ( xin => xv1_uid101_constMult_b, xout => ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0(REG,349)@3
reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q <= ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p1_uid116_constMult(LOOKUP,115)@4
p1_uid116_constMult: PROCESS (reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q) IS
WHEN "000000" => p1_uid116_constMult_q <= "00000000000000000000";
WHEN "000001" => p1_uid116_constMult_q <= "00000010111000101011";
WHEN "000010" => p1_uid116_constMult_q <= "00000101110001010101";
WHEN "000011" => p1_uid116_constMult_q <= "00001000101010000000";
WHEN "000100" => p1_uid116_constMult_q <= "00001011100010101010";
WHEN "000101" => p1_uid116_constMult_q <= "00001110011011010101";
WHEN "000110" => p1_uid116_constMult_q <= "00010001010011111111";
WHEN "000111" => p1_uid116_constMult_q <= "00010100001100101010";
WHEN "001000" => p1_uid116_constMult_q <= "00010111000101010100";
WHEN "001001" => p1_uid116_constMult_q <= "00011001111101111111";
WHEN "001010" => p1_uid116_constMult_q <= "00011100110110101010";
WHEN "001011" => p1_uid116_constMult_q <= "00011111101111010100";
WHEN "001100" => p1_uid116_constMult_q <= "00100010100111111111";
WHEN "001101" => p1_uid116_constMult_q <= "00100101100000101001";
WHEN "001110" => p1_uid116_constMult_q <= "00101000011001010100";
WHEN "001111" => p1_uid116_constMult_q <= "00101011010001111110";
WHEN "010000" => p1_uid116_constMult_q <= "00101110001010101001";
WHEN "010001" => p1_uid116_constMult_q <= "00110001000011010011";
WHEN "010010" => p1_uid116_constMult_q <= "00110011111011111110";
WHEN "010011" => p1_uid116_constMult_q <= "00110110110100101001";
WHEN "010100" => p1_uid116_constMult_q <= "00111001101101010011";
WHEN "010101" => p1_uid116_constMult_q <= "00111100100101111110";
WHEN "010110" => p1_uid116_constMult_q <= "00111111011110101000";
WHEN "010111" => p1_uid116_constMult_q <= "01000010010111010011";
WHEN "011000" => p1_uid116_constMult_q <= "01000101001111111101";
WHEN "011001" => p1_uid116_constMult_q <= "01001000001000101000";
WHEN "011010" => p1_uid116_constMult_q <= "01001011000001010011";
WHEN "011011" => p1_uid116_constMult_q <= "01001101111001111101";
WHEN "011100" => p1_uid116_constMult_q <= "01010000110010101000";
WHEN "011101" => p1_uid116_constMult_q <= "01010011101011010010";
WHEN "011110" => p1_uid116_constMult_q <= "01010110100011111101";
WHEN "011111" => p1_uid116_constMult_q <= "01011001011100100111";
WHEN "100000" => p1_uid116_constMult_q <= "01011100010101010010";
WHEN "100001" => p1_uid116_constMult_q <= "01011111001101111100";
WHEN "100010" => p1_uid116_constMult_q <= "01100010000110100111";
WHEN "100011" => p1_uid116_constMult_q <= "01100100111111010010";
WHEN "100100" => p1_uid116_constMult_q <= "01100111110111111100";
WHEN "100101" => p1_uid116_constMult_q <= "01101010110000100111";
WHEN "100110" => p1_uid116_constMult_q <= "01101101101001010001";
WHEN "100111" => p1_uid116_constMult_q <= "01110000100001111100";
WHEN "101000" => p1_uid116_constMult_q <= "01110011011010100110";
WHEN "101001" => p1_uid116_constMult_q <= "01110110010011010001";
WHEN "101010" => p1_uid116_constMult_q <= "01111001001011111011";
WHEN "101011" => p1_uid116_constMult_q <= "01111100000100100110";
WHEN "101100" => p1_uid116_constMult_q <= "01111110111101010001";
WHEN "101101" => p1_uid116_constMult_q <= "10000001110101111011";
WHEN "101110" => p1_uid116_constMult_q <= "10000100101110100110";
WHEN "101111" => p1_uid116_constMult_q <= "10000111100111010000";
WHEN "110000" => p1_uid116_constMult_q <= "10001010011111111011";
WHEN "110001" => p1_uid116_constMult_q <= "10001101011000100101";
WHEN "110010" => p1_uid116_constMult_q <= "10010000010001010000";
WHEN "110011" => p1_uid116_constMult_q <= "10010011001001111010";
WHEN "110100" => p1_uid116_constMult_q <= "10010110000010100101";
WHEN "110101" => p1_uid116_constMult_q <= "10011000111011010000";
WHEN "110110" => p1_uid116_constMult_q <= "10011011110011111010";
WHEN "110111" => p1_uid116_constMult_q <= "10011110101100100101";
WHEN "111000" => p1_uid116_constMult_q <= "10100001100101001111";
WHEN "111001" => p1_uid116_constMult_q <= "10100100011101111010";
WHEN "111010" => p1_uid116_constMult_q <= "10100111010110100100";
WHEN "111011" => p1_uid116_constMult_q <= "10101010001111001111";
WHEN "111100" => p1_uid116_constMult_q <= "10101101000111111001";
WHEN "111101" => p1_uid116_constMult_q <= "10110000000000100100";
WHEN "111110" => p1_uid116_constMult_q <= "10110010111001001111";
WHEN "111111" => p1_uid116_constMult_q <= "10110101110001111001";
WHEN OTHERS =>
p1_uid116_constMult_q <= "00000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv2_uid102_constMult(BITSELECT,101)@0
xv2_uid102_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(17 downto 0);
xv2_uid102_constMult_b <= xv2_uid102_constMult_in(17 downto 12);
--ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a(DELAY,802)@0
ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => xv2_uid102_constMult_b, xout => ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0(REG,348)@2
reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q <= ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p2_uid115_constMult(LOOKUP,114)@3
p2_uid115_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p2_uid115_constMult_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q) IS
WHEN "000000" => p2_uid115_constMult_q <= "00000000000000000000000000";
WHEN "000001" => p2_uid115_constMult_q <= "00000010111000101010100100";
WHEN "000010" => p2_uid115_constMult_q <= "00000101110001010101000111";
WHEN "000011" => p2_uid115_constMult_q <= "00001000101001111111101011";
WHEN "000100" => p2_uid115_constMult_q <= "00001011100010101010001111";
WHEN "000101" => p2_uid115_constMult_q <= "00001110011011010100110010";
WHEN "000110" => p2_uid115_constMult_q <= "00010001010011111111010110";
WHEN "000111" => p2_uid115_constMult_q <= "00010100001100101001111010";
WHEN "001000" => p2_uid115_constMult_q <= "00010111000101010100011110";
WHEN "001001" => p2_uid115_constMult_q <= "00011001111101111111000001";
WHEN "001010" => p2_uid115_constMult_q <= "00011100110110101001100101";
WHEN "001011" => p2_uid115_constMult_q <= "00011111101111010100001001";
WHEN "001100" => p2_uid115_constMult_q <= "00100010100111111110101100";
WHEN "001101" => p2_uid115_constMult_q <= "00100101100000101001010000";
WHEN "001110" => p2_uid115_constMult_q <= "00101000011001010011110100";
WHEN "001111" => p2_uid115_constMult_q <= "00101011010001111110010111";
WHEN "010000" => p2_uid115_constMult_q <= "00101110001010101000111011";
WHEN "010001" => p2_uid115_constMult_q <= "00110001000011010011011111";
WHEN "010010" => p2_uid115_constMult_q <= "00110011111011111110000011";
WHEN "010011" => p2_uid115_constMult_q <= "00110110110100101000100110";
WHEN "010100" => p2_uid115_constMult_q <= "00111001101101010011001010";
WHEN "010101" => p2_uid115_constMult_q <= "00111100100101111101101110";
WHEN "010110" => p2_uid115_constMult_q <= "00111111011110101000010001";
WHEN "010111" => p2_uid115_constMult_q <= "01000010010111010010110101";
WHEN "011000" => p2_uid115_constMult_q <= "01000101001111111101011001";
WHEN "011001" => p2_uid115_constMult_q <= "01001000001000100111111100";
WHEN "011010" => p2_uid115_constMult_q <= "01001011000001010010100000";
WHEN "011011" => p2_uid115_constMult_q <= "01001101111001111101000100";
WHEN "011100" => p2_uid115_constMult_q <= "01010000110010100111101000";
WHEN "011101" => p2_uid115_constMult_q <= "01010011101011010010001011";
WHEN "011110" => p2_uid115_constMult_q <= "01010110100011111100101111";
WHEN "011111" => p2_uid115_constMult_q <= "01011001011100100111010011";
WHEN "100000" => p2_uid115_constMult_q <= "01011100010101010001110110";
WHEN "100001" => p2_uid115_constMult_q <= "01011111001101111100011010";
WHEN "100010" => p2_uid115_constMult_q <= "01100010000110100110111110";
WHEN "100011" => p2_uid115_constMult_q <= "01100100111111010001100001";
WHEN "100100" => p2_uid115_constMult_q <= "01100111110111111100000101";
WHEN "100101" => p2_uid115_constMult_q <= "01101010110000100110101001";
WHEN "100110" => p2_uid115_constMult_q <= "01101101101001010001001101";
WHEN "100111" => p2_uid115_constMult_q <= "01110000100001111011110000";
WHEN "101000" => p2_uid115_constMult_q <= "01110011011010100110010100";
WHEN "101001" => p2_uid115_constMult_q <= "01110110010011010000111000";
WHEN "101010" => p2_uid115_constMult_q <= "01111001001011111011011011";
WHEN "101011" => p2_uid115_constMult_q <= "01111100000100100101111111";
WHEN "101100" => p2_uid115_constMult_q <= "01111110111101010000100011";
WHEN "101101" => p2_uid115_constMult_q <= "10000001110101111011000110";
WHEN "101110" => p2_uid115_constMult_q <= "10000100101110100101101010";
WHEN "101111" => p2_uid115_constMult_q <= "10000111100111010000001110";
WHEN "110000" => p2_uid115_constMult_q <= "10001010011111111010110001";
WHEN "110001" => p2_uid115_constMult_q <= "10001101011000100101010101";
WHEN "110010" => p2_uid115_constMult_q <= "10010000010001001111111001";
WHEN "110011" => p2_uid115_constMult_q <= "10010011001001111010011101";
WHEN "110100" => p2_uid115_constMult_q <= "10010110000010100101000000";
WHEN "110101" => p2_uid115_constMult_q <= "10011000111011001111100100";
WHEN "110110" => p2_uid115_constMult_q <= "10011011110011111010001000";
WHEN "110111" => p2_uid115_constMult_q <= "10011110101100100100101011";
WHEN "111000" => p2_uid115_constMult_q <= "10100001100101001111001111";
WHEN "111001" => p2_uid115_constMult_q <= "10100100011101111001110011";
WHEN "111010" => p2_uid115_constMult_q <= "10100111010110100100010110";
WHEN "111011" => p2_uid115_constMult_q <= "10101010001111001110111010";
WHEN "111100" => p2_uid115_constMult_q <= "10101101000111111001011110";
WHEN "111101" => p2_uid115_constMult_q <= "10110000000000100100000010";
WHEN "111110" => p2_uid115_constMult_q <= "10110010111001001110100101";
WHEN "111111" => p2_uid115_constMult_q <= "10110101110001111001001001";
WHEN OTHERS =>
p2_uid115_constMult_q <= "00000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a3_uid121_constMult(ADD,120)@4
lev1_a3_uid121_constMult_a <= STD_LOGIC_VECTOR("0" & p2_uid115_constMult_q);
lev1_a3_uid121_constMult_b <= STD_LOGIC_VECTOR("0000000" & p1_uid116_constMult_q);
lev1_a3_uid121_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a3_uid121_constMult_a) + UNSIGNED(lev1_a3_uid121_constMult_b));
lev1_a3_uid121_constMult_q <= lev1_a3_uid121_constMult_o(26 downto 0);
--xv3_uid103_constMult(BITSELECT,102)@0
xv3_uid103_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(23 downto 0);
xv3_uid103_constMult_b <= xv3_uid103_constMult_in(23 downto 18);
--reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0(REG,347)@0
reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q <= xv3_uid103_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a(DELAY,526)@1
ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q, xout => ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p3_uid114_constMult(LOOKUP,113)@3
p3_uid114_constMult: PROCESS (ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q) IS
WHEN "000000" => p3_uid114_constMult_q <= "00000000000000000000000000000000";
WHEN "000001" => p3_uid114_constMult_q <= "00000010111000101010100011101101";
WHEN "000010" => p3_uid114_constMult_q <= "00000101110001010101000111011001";
WHEN "000011" => p3_uid114_constMult_q <= "00001000101001111111101011000110";
WHEN "000100" => p3_uid114_constMult_q <= "00001011100010101010001110110011";
WHEN "000101" => p3_uid114_constMult_q <= "00001110011011010100110010011111";
WHEN "000110" => p3_uid114_constMult_q <= "00010001010011111111010110001100";
WHEN "000111" => p3_uid114_constMult_q <= "00010100001100101001111001111001";
WHEN "001000" => p3_uid114_constMult_q <= "00010111000101010100011101100101";
WHEN "001001" => p3_uid114_constMult_q <= "00011001111101111111000001010010";
WHEN "001010" => p3_uid114_constMult_q <= "00011100110110101001100100111110";
WHEN "001011" => p3_uid114_constMult_q <= "00011111101111010100001000101011";
WHEN "001100" => p3_uid114_constMult_q <= "00100010100111111110101100011000";
WHEN "001101" => p3_uid114_constMult_q <= "00100101100000101001010000000100";
WHEN "001110" => p3_uid114_constMult_q <= "00101000011001010011110011110001";
WHEN "001111" => p3_uid114_constMult_q <= "00101011010001111110010111011110";
WHEN "010000" => p3_uid114_constMult_q <= "00101110001010101000111011001010";
WHEN "010001" => p3_uid114_constMult_q <= "00110001000011010011011110110111";
WHEN "010010" => p3_uid114_constMult_q <= "00110011111011111110000010100100";
WHEN "010011" => p3_uid114_constMult_q <= "00110110110100101000100110010000";
WHEN "010100" => p3_uid114_constMult_q <= "00111001101101010011001001111101";
WHEN "010101" => p3_uid114_constMult_q <= "00111100100101111101101101101010";
WHEN "010110" => p3_uid114_constMult_q <= "00111111011110101000010001010110";
WHEN "010111" => p3_uid114_constMult_q <= "01000010010111010010110101000011";
WHEN "011000" => p3_uid114_constMult_q <= "01000101001111111101011000110000";
WHEN "011001" => p3_uid114_constMult_q <= "01001000001000100111111100011100";
WHEN "011010" => p3_uid114_constMult_q <= "01001011000001010010100000001001";
WHEN "011011" => p3_uid114_constMult_q <= "01001101111001111101000011110101";
WHEN "011100" => p3_uid114_constMult_q <= "01010000110010100111100111100010";
WHEN "011101" => p3_uid114_constMult_q <= "01010011101011010010001011001111";
WHEN "011110" => p3_uid114_constMult_q <= "01010110100011111100101110111011";
WHEN "011111" => p3_uid114_constMult_q <= "01011001011100100111010010101000";
WHEN "100000" => p3_uid114_constMult_q <= "01011100010101010001110110010101";
WHEN "100001" => p3_uid114_constMult_q <= "01011111001101111100011010000001";
WHEN "100010" => p3_uid114_constMult_q <= "01100010000110100110111101101110";
WHEN "100011" => p3_uid114_constMult_q <= "01100100111111010001100001011011";
WHEN "100100" => p3_uid114_constMult_q <= "01100111110111111100000101000111";
WHEN "100101" => p3_uid114_constMult_q <= "01101010110000100110101000110100";
WHEN "100110" => p3_uid114_constMult_q <= "01101101101001010001001100100001";
WHEN "100111" => p3_uid114_constMult_q <= "01110000100001111011110000001101";
WHEN "101000" => p3_uid114_constMult_q <= "01110011011010100110010011111010";
WHEN "101001" => p3_uid114_constMult_q <= "01110110010011010000110111100110";
WHEN "101010" => p3_uid114_constMult_q <= "01111001001011111011011011010011";
WHEN "101011" => p3_uid114_constMult_q <= "01111100000100100101111111000000";
WHEN "101100" => p3_uid114_constMult_q <= "01111110111101010000100010101100";
WHEN "101101" => p3_uid114_constMult_q <= "10000001110101111011000110011001";
WHEN "101110" => p3_uid114_constMult_q <= "10000100101110100101101010000110";
WHEN "101111" => p3_uid114_constMult_q <= "10000111100111010000001101110010";
WHEN "110000" => p3_uid114_constMult_q <= "10001010011111111010110001011111";
WHEN "110001" => p3_uid114_constMult_q <= "10001101011000100101010101001100";
WHEN "110010" => p3_uid114_constMult_q <= "10010000010001001111111000111000";
WHEN "110011" => p3_uid114_constMult_q <= "10010011001001111010011100100101";
WHEN "110100" => p3_uid114_constMult_q <= "10010110000010100101000000010010";
WHEN "110101" => p3_uid114_constMult_q <= "10011000111011001111100011111110";
WHEN "110110" => p3_uid114_constMult_q <= "10011011110011111010000111101011";
WHEN "110111" => p3_uid114_constMult_q <= "10011110101100100100101011011000";
WHEN "111000" => p3_uid114_constMult_q <= "10100001100101001111001111000100";
WHEN "111001" => p3_uid114_constMult_q <= "10100100011101111001110010110001";
WHEN "111010" => p3_uid114_constMult_q <= "10100111010110100100010110011101";
WHEN "111011" => p3_uid114_constMult_q <= "10101010001111001110111010001010";
WHEN "111100" => p3_uid114_constMult_q <= "10101101000111111001011101110111";
WHEN "111101" => p3_uid114_constMult_q <= "10110000000000100100000001100011";
WHEN "111110" => p3_uid114_constMult_q <= "10110010111001001110100101010000";
WHEN "111111" => p3_uid114_constMult_q <= "10110101110001111001001000111101";
WHEN OTHERS =>
p3_uid114_constMult_q <= "00000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv4_uid104_constMult(BITSELECT,103)@0
xv4_uid104_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(29 downto 0);
xv4_uid104_constMult_b <= xv4_uid104_constMult_in(29 downto 24);
--reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0(REG,346)@0
reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q <= xv4_uid104_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a(DELAY,525)@1
ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q, xout => ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p4_uid113_constMult(LOOKUP,112)@2
p4_uid113_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p4_uid113_constMult_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a_q) IS
WHEN "000000" => p4_uid113_constMult_q <= "00000000000000000000000000000000000000";
WHEN "000001" => p4_uid113_constMult_q <= "00000010111000101010100011101100101001";
WHEN "000010" => p4_uid113_constMult_q <= "00000101110001010101000111011001010011";
WHEN "000011" => p4_uid113_constMult_q <= "00001000101001111111101011000101111100";
WHEN "000100" => p4_uid113_constMult_q <= "00001011100010101010001110110010100101";
WHEN "000101" => p4_uid113_constMult_q <= "00001110011011010100110010011111001111";
WHEN "000110" => p4_uid113_constMult_q <= "00010001010011111111010110001011111000";
WHEN "000111" => p4_uid113_constMult_q <= "00010100001100101001111001111000100010";
WHEN "001000" => p4_uid113_constMult_q <= "00010111000101010100011101100101001011";
WHEN "001001" => p4_uid113_constMult_q <= "00011001111101111111000001010001110100";
WHEN "001010" => p4_uid113_constMult_q <= "00011100110110101001100100111110011110";
WHEN "001011" => p4_uid113_constMult_q <= "00011111101111010100001000101011000111";
WHEN "001100" => p4_uid113_constMult_q <= "00100010100111111110101100010111110000";
WHEN "001101" => p4_uid113_constMult_q <= "00100101100000101001010000000100011010";
WHEN "001110" => p4_uid113_constMult_q <= "00101000011001010011110011110001000011";
WHEN "001111" => p4_uid113_constMult_q <= "00101011010001111110010111011101101100";
WHEN "010000" => p4_uid113_constMult_q <= "00101110001010101000111011001010010110";
WHEN "010001" => p4_uid113_constMult_q <= "00110001000011010011011110110110111111";
WHEN "010010" => p4_uid113_constMult_q <= "00110011111011111110000010100011101000";
WHEN "010011" => p4_uid113_constMult_q <= "00110110110100101000100110010000010010";
WHEN "010100" => p4_uid113_constMult_q <= "00111001101101010011001001111100111011";
WHEN "010101" => p4_uid113_constMult_q <= "00111100100101111101101101101001100101";
WHEN "010110" => p4_uid113_constMult_q <= "00111111011110101000010001010110001110";
WHEN "010111" => p4_uid113_constMult_q <= "01000010010111010010110101000010110111";
WHEN "011000" => p4_uid113_constMult_q <= "01000101001111111101011000101111100001";
WHEN "011001" => p4_uid113_constMult_q <= "01001000001000100111111100011100001010";
WHEN "011010" => p4_uid113_constMult_q <= "01001011000001010010100000001000110011";
WHEN "011011" => p4_uid113_constMult_q <= "01001101111001111101000011110101011101";
WHEN "011100" => p4_uid113_constMult_q <= "01010000110010100111100111100010000110";
WHEN "011101" => p4_uid113_constMult_q <= "01010011101011010010001011001110101111";
WHEN "011110" => p4_uid113_constMult_q <= "01010110100011111100101110111011011001";
WHEN "011111" => p4_uid113_constMult_q <= "01011001011100100111010010101000000010";
WHEN "100000" => p4_uid113_constMult_q <= "01011100010101010001110110010100101100";
WHEN "100001" => p4_uid113_constMult_q <= "01011111001101111100011010000001010101";
WHEN "100010" => p4_uid113_constMult_q <= "01100010000110100110111101101101111110";
WHEN "100011" => p4_uid113_constMult_q <= "01100100111111010001100001011010101000";
WHEN "100100" => p4_uid113_constMult_q <= "01100111110111111100000101000111010001";
WHEN "100101" => p4_uid113_constMult_q <= "01101010110000100110101000110011111010";
WHEN "100110" => p4_uid113_constMult_q <= "01101101101001010001001100100000100100";
WHEN "100111" => p4_uid113_constMult_q <= "01110000100001111011110000001101001101";
WHEN "101000" => p4_uid113_constMult_q <= "01110011011010100110010011111001110110";
WHEN "101001" => p4_uid113_constMult_q <= "01110110010011010000110111100110100000";
WHEN "101010" => p4_uid113_constMult_q <= "01111001001011111011011011010011001001";
WHEN "101011" => p4_uid113_constMult_q <= "01111100000100100101111110111111110010";
WHEN "101100" => p4_uid113_constMult_q <= "01111110111101010000100010101100011100";
WHEN "101101" => p4_uid113_constMult_q <= "10000001110101111011000110011001000101";
WHEN "101110" => p4_uid113_constMult_q <= "10000100101110100101101010000101101111";
WHEN "101111" => p4_uid113_constMult_q <= "10000111100111010000001101110010011000";
WHEN "110000" => p4_uid113_constMult_q <= "10001010011111111010110001011111000001";
WHEN "110001" => p4_uid113_constMult_q <= "10001101011000100101010101001011101011";
WHEN "110010" => p4_uid113_constMult_q <= "10010000010001001111111000111000010100";
WHEN "110011" => p4_uid113_constMult_q <= "10010011001001111010011100100100111101";
WHEN "110100" => p4_uid113_constMult_q <= "10010110000010100101000000010001100111";
WHEN "110101" => p4_uid113_constMult_q <= "10011000111011001111100011111110010000";
WHEN "110110" => p4_uid113_constMult_q <= "10011011110011111010000111101010111001";
WHEN "110111" => p4_uid113_constMult_q <= "10011110101100100100101011010111100011";
WHEN "111000" => p4_uid113_constMult_q <= "10100001100101001111001111000100001100";
WHEN "111001" => p4_uid113_constMult_q <= "10100100011101111001110010110000110110";
WHEN "111010" => p4_uid113_constMult_q <= "10100111010110100100010110011101011111";
WHEN "111011" => p4_uid113_constMult_q <= "10101010001111001110111010001010001000";
WHEN "111100" => p4_uid113_constMult_q <= "10101101000111111001011101110110110010";
WHEN "111101" => p4_uid113_constMult_q <= "10110000000000100100000001100011011011";
WHEN "111110" => p4_uid113_constMult_q <= "10110010111001001110100101010000000100";
WHEN "111111" => p4_uid113_constMult_q <= "10110101110001111001001000111100101110";
WHEN OTHERS =>
p4_uid113_constMult_q <= "00000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a2_uid120_constMult(ADD,119)@3
lev1_a2_uid120_constMult_a <= STD_LOGIC_VECTOR("0" & p4_uid113_constMult_q);
lev1_a2_uid120_constMult_b <= STD_LOGIC_VECTOR("0000000" & p3_uid114_constMult_q);
lev1_a2_uid120_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev1_a2_uid120_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev1_a2_uid120_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a2_uid120_constMult_a) + UNSIGNED(lev1_a2_uid120_constMult_b));
END IF;
END IF;
END PROCESS;
lev1_a2_uid120_constMult_q <= lev1_a2_uid120_constMult_o(38 downto 0);
--lev2_a1_uid123_constMult(ADD,122)@4
lev2_a1_uid123_constMult_a <= STD_LOGIC_VECTOR("0" & lev1_a2_uid120_constMult_q);
lev2_a1_uid123_constMult_b <= STD_LOGIC_VECTOR("0000000000000" & lev1_a3_uid121_constMult_q);
lev2_a1_uid123_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev2_a1_uid123_constMult_a) + UNSIGNED(lev2_a1_uid123_constMult_b));
lev2_a1_uid123_constMult_q <= lev2_a1_uid123_constMult_o(39 downto 0);
--xv5_uid105_constMult(BITSELECT,104)@0
xv5_uid105_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(35 downto 0);
xv5_uid105_constMult_b <= xv5_uid105_constMult_in(35 downto 30);
--ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a(DELAY,799)@0
ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => xv5_uid105_constMult_b, xout => ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0(REG,345)@2
reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q <= ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p5_uid112_constMult(LOOKUP,111)@3
p5_uid112_constMult: PROCESS (reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q) IS
WHEN "000000" => p5_uid112_constMult_q <= "00000000000000000000000000000000000000000000";
WHEN "000001" => p5_uid112_constMult_q <= "00000010111000101010100011101100101001010111";
WHEN "000010" => p5_uid112_constMult_q <= "00000101110001010101000111011001010010101110";
WHEN "000011" => p5_uid112_constMult_q <= "00001000101001111111101011000101111100000101";
WHEN "000100" => p5_uid112_constMult_q <= "00001011100010101010001110110010100101011100";
WHEN "000101" => p5_uid112_constMult_q <= "00001110011011010100110010011111001110110011";
WHEN "000110" => p5_uid112_constMult_q <= "00010001010011111111010110001011111000001010";
WHEN "000111" => p5_uid112_constMult_q <= "00010100001100101001111001111000100001100001";
WHEN "001000" => p5_uid112_constMult_q <= "00010111000101010100011101100101001010111000";
WHEN "001001" => p5_uid112_constMult_q <= "00011001111101111111000001010001110100001111";
WHEN "001010" => p5_uid112_constMult_q <= "00011100110110101001100100111110011101100110";
WHEN "001011" => p5_uid112_constMult_q <= "00011111101111010100001000101011000110111101";
WHEN "001100" => p5_uid112_constMult_q <= "00100010100111111110101100010111110000010100";
WHEN "001101" => p5_uid112_constMult_q <= "00100101100000101001010000000100011001101011";
WHEN "001110" => p5_uid112_constMult_q <= "00101000011001010011110011110001000011000010";
WHEN "001111" => p5_uid112_constMult_q <= "00101011010001111110010111011101101100011001";
WHEN "010000" => p5_uid112_constMult_q <= "00101110001010101000111011001010010101110000";
WHEN "010001" => p5_uid112_constMult_q <= "00110001000011010011011110110110111111000111";
WHEN "010010" => p5_uid112_constMult_q <= "00110011111011111110000010100011101000011110";
WHEN "010011" => p5_uid112_constMult_q <= "00110110110100101000100110010000010001110101";
WHEN "010100" => p5_uid112_constMult_q <= "00111001101101010011001001111100111011001100";
WHEN "010101" => p5_uid112_constMult_q <= "00111100100101111101101101101001100100100011";
WHEN "010110" => p5_uid112_constMult_q <= "00111111011110101000010001010110001101111011";
WHEN "010111" => p5_uid112_constMult_q <= "01000010010111010010110101000010110111010010";
WHEN "011000" => p5_uid112_constMult_q <= "01000101001111111101011000101111100000101001";
WHEN "011001" => p5_uid112_constMult_q <= "01001000001000100111111100011100001010000000";
WHEN "011010" => p5_uid112_constMult_q <= "01001011000001010010100000001000110011010111";
WHEN "011011" => p5_uid112_constMult_q <= "01001101111001111101000011110101011100101110";
WHEN "011100" => p5_uid112_constMult_q <= "01010000110010100111100111100010000110000101";
WHEN "011101" => p5_uid112_constMult_q <= "01010011101011010010001011001110101111011100";
WHEN "011110" => p5_uid112_constMult_q <= "01010110100011111100101110111011011000110011";
WHEN "011111" => p5_uid112_constMult_q <= "01011001011100100111010010101000000010001010";
WHEN "100000" => p5_uid112_constMult_q <= "01011100010101010001110110010100101011100001";
WHEN "100001" => p5_uid112_constMult_q <= "01011111001101111100011010000001010100111000";
WHEN "100010" => p5_uid112_constMult_q <= "01100010000110100110111101101101111110001111";
WHEN "100011" => p5_uid112_constMult_q <= "01100100111111010001100001011010100111100110";
WHEN "100100" => p5_uid112_constMult_q <= "01100111110111111100000101000111010000111101";
WHEN "100101" => p5_uid112_constMult_q <= "01101010110000100110101000110011111010010100";
WHEN "100110" => p5_uid112_constMult_q <= "01101101101001010001001100100000100011101011";
WHEN "100111" => p5_uid112_constMult_q <= "01110000100001111011110000001101001101000010";
WHEN "101000" => p5_uid112_constMult_q <= "01110011011010100110010011111001110110011001";
WHEN "101001" => p5_uid112_constMult_q <= "01110110010011010000110111100110011111110000";
WHEN "101010" => p5_uid112_constMult_q <= "01111001001011111011011011010011001001000111";
WHEN "101011" => p5_uid112_constMult_q <= "01111100000100100101111110111111110010011110";
WHEN "101100" => p5_uid112_constMult_q <= "01111110111101010000100010101100011011110101";
WHEN "101101" => p5_uid112_constMult_q <= "10000001110101111011000110011001000101001100";
WHEN "101110" => p5_uid112_constMult_q <= "10000100101110100101101010000101101110100011";
WHEN "101111" => p5_uid112_constMult_q <= "10000111100111010000001101110010010111111010";
WHEN "110000" => p5_uid112_constMult_q <= "10001010011111111010110001011111000001010001";
WHEN "110001" => p5_uid112_constMult_q <= "10001101011000100101010101001011101010101000";
WHEN "110010" => p5_uid112_constMult_q <= "10010000010001001111111000111000010011111111";
WHEN "110011" => p5_uid112_constMult_q <= "10010011001001111010011100100100111101010110";
WHEN "110100" => p5_uid112_constMult_q <= "10010110000010100101000000010001100110101101";
WHEN "110101" => p5_uid112_constMult_q <= "10011000111011001111100011111110010000000100";
WHEN "110110" => p5_uid112_constMult_q <= "10011011110011111010000111101010111001011011";
WHEN "110111" => p5_uid112_constMult_q <= "10011110101100100100101011010111100010110010";
WHEN "111000" => p5_uid112_constMult_q <= "10100001100101001111001111000100001100001001";
WHEN "111001" => p5_uid112_constMult_q <= "10100100011101111001110010110000110101100000";
WHEN "111010" => p5_uid112_constMult_q <= "10100111010110100100010110011101011110110111";
WHEN "111011" => p5_uid112_constMult_q <= "10101010001111001110111010001010001000001110";
WHEN "111100" => p5_uid112_constMult_q <= "10101101000111111001011101110110110001100101";
WHEN "111101" => p5_uid112_constMult_q <= "10110000000000100100000001100011011010111100";
WHEN "111110" => p5_uid112_constMult_q <= "10110010111001001110100101010000000100010011";
WHEN "111111" => p5_uid112_constMult_q <= "10110101110001111001001000111100101101101010";
WHEN OTHERS =>
p5_uid112_constMult_q <= "00000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv6_uid106_constMult(BITSELECT,105)@0
xv6_uid106_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(41 downto 0);
xv6_uid106_constMult_b <= xv6_uid106_constMult_in(41 downto 36);
--reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0(REG,344)@0
reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q <= xv6_uid106_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a(DELAY,523)@1
ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q, xout => ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p6_uid111_constMult(LOOKUP,110)@2
p6_uid111_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p6_uid111_constMult_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a_q) IS
WHEN "000000" => p6_uid111_constMult_q <= "00000000000000000000000000000000000000000000000000";
WHEN "000001" => p6_uid111_constMult_q <= "00000010111000101010100011101100101001010111000001";
WHEN "000010" => p6_uid111_constMult_q <= "00000101110001010101000111011001010010101110000011";
WHEN "000011" => p6_uid111_constMult_q <= "00001000101001111111101011000101111100000101000100";
WHEN "000100" => p6_uid111_constMult_q <= "00001011100010101010001110110010100101011100000110";
WHEN "000101" => p6_uid111_constMult_q <= "00001110011011010100110010011111001110110011000111";
WHEN "000110" => p6_uid111_constMult_q <= "00010001010011111111010110001011111000001010001001";
WHEN "000111" => p6_uid111_constMult_q <= "00010100001100101001111001111000100001100001001010";
WHEN "001000" => p6_uid111_constMult_q <= "00010111000101010100011101100101001010111000001100";
WHEN "001001" => p6_uid111_constMult_q <= "00011001111101111111000001010001110100001111001101";
WHEN "001010" => p6_uid111_constMult_q <= "00011100110110101001100100111110011101100110001111";
WHEN "001011" => p6_uid111_constMult_q <= "00011111101111010100001000101011000110111101010000";
WHEN "001100" => p6_uid111_constMult_q <= "00100010100111111110101100010111110000010100010010";
WHEN "001101" => p6_uid111_constMult_q <= "00100101100000101001010000000100011001101011010011";
WHEN "001110" => p6_uid111_constMult_q <= "00101000011001010011110011110001000011000010010101";
WHEN "001111" => p6_uid111_constMult_q <= "00101011010001111110010111011101101100011001010110";
WHEN "010000" => p6_uid111_constMult_q <= "00101110001010101000111011001010010101110000011000";
WHEN "010001" => p6_uid111_constMult_q <= "00110001000011010011011110110110111111000111011001";
WHEN "010010" => p6_uid111_constMult_q <= "00110011111011111110000010100011101000011110011011";
WHEN "010011" => p6_uid111_constMult_q <= "00110110110100101000100110010000010001110101011100";
WHEN "010100" => p6_uid111_constMult_q <= "00111001101101010011001001111100111011001100011110";
WHEN "010101" => p6_uid111_constMult_q <= "00111100100101111101101101101001100100100011011111";
WHEN "010110" => p6_uid111_constMult_q <= "00111111011110101000010001010110001101111010100001";
WHEN "010111" => p6_uid111_constMult_q <= "01000010010111010010110101000010110111010001100010";
WHEN "011000" => p6_uid111_constMult_q <= "01000101001111111101011000101111100000101000100100";
WHEN "011001" => p6_uid111_constMult_q <= "01001000001000100111111100011100001001111111100101";
WHEN "011010" => p6_uid111_constMult_q <= "01001011000001010010100000001000110011010110100111";
WHEN "011011" => p6_uid111_constMult_q <= "01001101111001111101000011110101011100101101101000";
WHEN "011100" => p6_uid111_constMult_q <= "01010000110010100111100111100010000110000100101010";
WHEN "011101" => p6_uid111_constMult_q <= "01010011101011010010001011001110101111011011101011";
WHEN "011110" => p6_uid111_constMult_q <= "01010110100011111100101110111011011000110010101101";
WHEN "011111" => p6_uid111_constMult_q <= "01011001011100100111010010101000000010001001101110";
WHEN "100000" => p6_uid111_constMult_q <= "01011100010101010001110110010100101011100000110000";
WHEN "100001" => p6_uid111_constMult_q <= "01011111001101111100011010000001010100110111110001";
WHEN "100010" => p6_uid111_constMult_q <= "01100010000110100110111101101101111110001110110011";
WHEN "100011" => p6_uid111_constMult_q <= "01100100111111010001100001011010100111100101110100";
WHEN "100100" => p6_uid111_constMult_q <= "01100111110111111100000101000111010000111100110110";
WHEN "100101" => p6_uid111_constMult_q <= "01101010110000100110101000110011111010010011110111";
WHEN "100110" => p6_uid111_constMult_q <= "01101101101001010001001100100000100011101010111001";
WHEN "100111" => p6_uid111_constMult_q <= "01110000100001111011110000001101001101000001111010";
WHEN "101000" => p6_uid111_constMult_q <= "01110011011010100110010011111001110110011000111100";
WHEN "101001" => p6_uid111_constMult_q <= "01110110010011010000110111100110011111101111111101";
WHEN "101010" => p6_uid111_constMult_q <= "01111001001011111011011011010011001001000110111111";
WHEN "101011" => p6_uid111_constMult_q <= "01111100000100100101111110111111110010011110000000";
WHEN "101100" => p6_uid111_constMult_q <= "01111110111101010000100010101100011011110101000010";
WHEN "101101" => p6_uid111_constMult_q <= "10000001110101111011000110011001000101001100000011";
WHEN "101110" => p6_uid111_constMult_q <= "10000100101110100101101010000101101110100011000101";
WHEN "101111" => p6_uid111_constMult_q <= "10000111100111010000001101110010010111111010000110";
WHEN "110000" => p6_uid111_constMult_q <= "10001010011111111010110001011111000001010001001000";
WHEN "110001" => p6_uid111_constMult_q <= "10001101011000100101010101001011101010101000001001";
WHEN "110010" => p6_uid111_constMult_q <= "10010000010001001111111000111000010011111111001011";
WHEN "110011" => p6_uid111_constMult_q <= "10010011001001111010011100100100111101010110001100";
WHEN "110100" => p6_uid111_constMult_q <= "10010110000010100101000000010001100110101101001110";
WHEN "110101" => p6_uid111_constMult_q <= "10011000111011001111100011111110010000000100001111";
WHEN "110110" => p6_uid111_constMult_q <= "10011011110011111010000111101010111001011011010001";
WHEN "110111" => p6_uid111_constMult_q <= "10011110101100100100101011010111100010110010010010";
WHEN "111000" => p6_uid111_constMult_q <= "10100001100101001111001111000100001100001001010100";
WHEN "111001" => p6_uid111_constMult_q <= "10100100011101111001110010110000110101100000010101";
WHEN "111010" => p6_uid111_constMult_q <= "10100111010110100100010110011101011110110111010111";
WHEN "111011" => p6_uid111_constMult_q <= "10101010001111001110111010001010001000001110011000";
WHEN "111100" => p6_uid111_constMult_q <= "10101101000111111001011101110110110001100101011010";
WHEN "111101" => p6_uid111_constMult_q <= "10110000000000100100000001100011011010111100011011";
WHEN "111110" => p6_uid111_constMult_q <= "10110010111001001110100101010000000100010011011101";
WHEN "111111" => p6_uid111_constMult_q <= "10110101110001111001001000111100101101101010011110";
WHEN OTHERS =>
p6_uid111_constMult_q <= "00000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a1_uid119_constMult(ADD,118)@3
lev1_a1_uid119_constMult_a <= STD_LOGIC_VECTOR("0" & p6_uid111_constMult_q);
lev1_a1_uid119_constMult_b <= STD_LOGIC_VECTOR("0000000" & p5_uid112_constMult_q);
lev1_a1_uid119_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a1_uid119_constMult_a) + UNSIGNED(lev1_a1_uid119_constMult_b));
lev1_a1_uid119_constMult_q <= lev1_a1_uid119_constMult_o(50 downto 0);
--xv7_uid107_constMult(BITSELECT,106)@0
xv7_uid107_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(47 downto 0);
xv7_uid107_constMult_b <= xv7_uid107_constMult_in(47 downto 42);
--reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0(REG,343)@0
reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q <= xv7_uid107_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a(DELAY,522)@1
ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q, xout => ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p7_uid110_constMult(LOOKUP,109)@2
p7_uid110_constMult: PROCESS (ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q) IS
WHEN "000000" => p7_uid110_constMult_q <= "00000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p7_uid110_constMult_q <= "00000010111000101010100011101100101001010111000001100000";
WHEN "000010" => p7_uid110_constMult_q <= "00000101110001010101000111011001010010101110000011000000";
WHEN "000011" => p7_uid110_constMult_q <= "00001000101001111111101011000101111100000101000100011111";
WHEN "000100" => p7_uid110_constMult_q <= "00001011100010101010001110110010100101011100000101111111";
WHEN "000101" => p7_uid110_constMult_q <= "00001110011011010100110010011111001110110011000111011111";
WHEN "000110" => p7_uid110_constMult_q <= "00010001010011111111010110001011111000001010001000111111";
WHEN "000111" => p7_uid110_constMult_q <= "00010100001100101001111001111000100001100001001010011110";
WHEN "001000" => p7_uid110_constMult_q <= "00010111000101010100011101100101001010111000001011111110";
WHEN "001001" => p7_uid110_constMult_q <= "00011001111101111111000001010001110100001111001101011110";
WHEN "001010" => p7_uid110_constMult_q <= "00011100110110101001100100111110011101100110001110111110";
WHEN "001011" => p7_uid110_constMult_q <= "00011111101111010100001000101011000110111101010000011101";
WHEN "001100" => p7_uid110_constMult_q <= "00100010100111111110101100010111110000010100010001111101";
WHEN "001101" => p7_uid110_constMult_q <= "00100101100000101001010000000100011001101011010011011101";
WHEN "001110" => p7_uid110_constMult_q <= "00101000011001010011110011110001000011000010010100111101";
WHEN "001111" => p7_uid110_constMult_q <= "00101011010001111110010111011101101100011001010110011100";
WHEN "010000" => p7_uid110_constMult_q <= "00101110001010101000111011001010010101110000010111111100";
WHEN "010001" => p7_uid110_constMult_q <= "00110001000011010011011110110110111111000111011001011100";
WHEN "010010" => p7_uid110_constMult_q <= "00110011111011111110000010100011101000011110011010111100";
WHEN "010011" => p7_uid110_constMult_q <= "00110110110100101000100110010000010001110101011100011011";
WHEN "010100" => p7_uid110_constMult_q <= "00111001101101010011001001111100111011001100011101111011";
WHEN "010101" => p7_uid110_constMult_q <= "00111100100101111101101101101001100100100011011111011011";
WHEN "010110" => p7_uid110_constMult_q <= "00111111011110101000010001010110001101111010100000111011";
WHEN "010111" => p7_uid110_constMult_q <= "01000010010111010010110101000010110111010001100010011011";
WHEN "011000" => p7_uid110_constMult_q <= "01000101001111111101011000101111100000101000100011111010";
WHEN "011001" => p7_uid110_constMult_q <= "01001000001000100111111100011100001001111111100101011010";
WHEN "011010" => p7_uid110_constMult_q <= "01001011000001010010100000001000110011010110100110111010";
WHEN "011011" => p7_uid110_constMult_q <= "01001101111001111101000011110101011100101101101000011010";
WHEN "011100" => p7_uid110_constMult_q <= "01010000110010100111100111100010000110000100101001111001";
WHEN "011101" => p7_uid110_constMult_q <= "01010011101011010010001011001110101111011011101011011001";
WHEN "011110" => p7_uid110_constMult_q <= "01010110100011111100101110111011011000110010101100111001";
WHEN "011111" => p7_uid110_constMult_q <= "01011001011100100111010010101000000010001001101110011001";
WHEN "100000" => p7_uid110_constMult_q <= "01011100010101010001110110010100101011100000101111111000";
WHEN "100001" => p7_uid110_constMult_q <= "01011111001101111100011010000001010100110111110001011000";
WHEN "100010" => p7_uid110_constMult_q <= "01100010000110100110111101101101111110001110110010111000";
WHEN "100011" => p7_uid110_constMult_q <= "01100100111111010001100001011010100111100101110100011000";
WHEN "100100" => p7_uid110_constMult_q <= "01100111110111111100000101000111010000111100110101110111";
WHEN "100101" => p7_uid110_constMult_q <= "01101010110000100110101000110011111010010011110111010111";
WHEN "100110" => p7_uid110_constMult_q <= "01101101101001010001001100100000100011101010111000110111";
WHEN "100111" => p7_uid110_constMult_q <= "01110000100001111011110000001101001101000001111010010111";
WHEN "101000" => p7_uid110_constMult_q <= "01110011011010100110010011111001110110011000111011110110";
WHEN "101001" => p7_uid110_constMult_q <= "01110110010011010000110111100110011111101111111101010110";
WHEN "101010" => p7_uid110_constMult_q <= "01111001001011111011011011010011001001000110111110110110";
WHEN "101011" => p7_uid110_constMult_q <= "01111100000100100101111110111111110010011110000000010110";
WHEN "101100" => p7_uid110_constMult_q <= "01111110111101010000100010101100011011110101000001110110";
WHEN "101101" => p7_uid110_constMult_q <= "10000001110101111011000110011001000101001100000011010101";
WHEN "101110" => p7_uid110_constMult_q <= "10000100101110100101101010000101101110100011000100110101";
WHEN "101111" => p7_uid110_constMult_q <= "10000111100111010000001101110010010111111010000110010101";
WHEN "110000" => p7_uid110_constMult_q <= "10001010011111111010110001011111000001010001000111110101";
WHEN "110001" => p7_uid110_constMult_q <= "10001101011000100101010101001011101010101000001001010100";
WHEN "110010" => p7_uid110_constMult_q <= "10010000010001001111111000111000010011111111001010110100";
WHEN "110011" => p7_uid110_constMult_q <= "10010011001001111010011100100100111101010110001100010100";
WHEN "110100" => p7_uid110_constMult_q <= "10010110000010100101000000010001100110101101001101110100";
WHEN "110101" => p7_uid110_constMult_q <= "10011000111011001111100011111110010000000100001111010011";
WHEN "110110" => p7_uid110_constMult_q <= "10011011110011111010000111101010111001011011010000110011";
WHEN "110111" => p7_uid110_constMult_q <= "10011110101100100100101011010111100010110010010010010011";
WHEN "111000" => p7_uid110_constMult_q <= "10100001100101001111001111000100001100001001010011110011";
WHEN "111001" => p7_uid110_constMult_q <= "10100100011101111001110010110000110101100000010101010010";
WHEN "111010" => p7_uid110_constMult_q <= "10100111010110100100010110011101011110110111010110110010";
WHEN "111011" => p7_uid110_constMult_q <= "10101010001111001110111010001010001000001110011000010010";
WHEN "111100" => p7_uid110_constMult_q <= "10101101000111111001011101110110110001100101011001110010";
WHEN "111101" => p7_uid110_constMult_q <= "10110000000000100100000001100011011010111100011011010001";
WHEN "111110" => p7_uid110_constMult_q <= "10110010111001001110100101010000000100010011011100110001";
WHEN "111111" => p7_uid110_constMult_q <= "10110101110001111001001000111100101101101010011110010001";
WHEN OTHERS =>
p7_uid110_constMult_q <= "00000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv8_uid108_constMult(BITSELECT,107)@0
xv8_uid108_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b;
xv8_uid108_constMult_b <= xv8_uid108_constMult_in(53 downto 48);
--reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0(REG,342)@0
reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q <= xv8_uid108_constMult_b;
END IF;
END IF;
END PROCESS;
--p8_uid109_constMult(LOOKUP,108)@1
p8_uid109_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p8_uid109_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q) IS
WHEN "000000" => p8_uid109_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p8_uid109_constMult_q <= "00000010111000101010100011101100101001010111000001011111110001";
WHEN "000010" => p8_uid109_constMult_q <= "00000101110001010101000111011001010010101110000010111111100010";
WHEN "000011" => p8_uid109_constMult_q <= "00001000101001111111101011000101111100000101000100011111010010";
WHEN "000100" => p8_uid109_constMult_q <= "00001011100010101010001110110010100101011100000101111111000011";
WHEN "000101" => p8_uid109_constMult_q <= "00001110011011010100110010011111001110110011000111011110110100";
WHEN "000110" => p8_uid109_constMult_q <= "00010001010011111111010110001011111000001010001000111110100100";
WHEN "000111" => p8_uid109_constMult_q <= "00010100001100101001111001111000100001100001001010011110010101";
WHEN "001000" => p8_uid109_constMult_q <= "00010111000101010100011101100101001010111000001011111110000110";
WHEN "001001" => p8_uid109_constMult_q <= "00011001111101111111000001010001110100001111001101011101110111";
WHEN "001010" => p8_uid109_constMult_q <= "00011100110110101001100100111110011101100110001110111101101000";
WHEN "001011" => p8_uid109_constMult_q <= "00011111101111010100001000101011000110111101010000011101011000";
WHEN "001100" => p8_uid109_constMult_q <= "00100010100111111110101100010111110000010100010001111101001001";
WHEN "001101" => p8_uid109_constMult_q <= "00100101100000101001010000000100011001101011010011011100111010";
WHEN "001110" => p8_uid109_constMult_q <= "00101000011001010011110011110001000011000010010100111100101010";
WHEN "001111" => p8_uid109_constMult_q <= "00101011010001111110010111011101101100011001010110011100011011";
WHEN "010000" => p8_uid109_constMult_q <= "00101110001010101000111011001010010101110000010111111100001100";
WHEN "010001" => p8_uid109_constMult_q <= "00110001000011010011011110110110111111000111011001011011111101";
WHEN "010010" => p8_uid109_constMult_q <= "00110011111011111110000010100011101000011110011010111011101110";
WHEN "010011" => p8_uid109_constMult_q <= "00110110110100101000100110010000010001110101011100011011011110";
WHEN "010100" => p8_uid109_constMult_q <= "00111001101101010011001001111100111011001100011101111011001111";
WHEN "010101" => p8_uid109_constMult_q <= "00111100100101111101101101101001100100100011011111011011000000";
WHEN "010110" => p8_uid109_constMult_q <= "00111111011110101000010001010110001101111010100000111010110000";
WHEN "010111" => p8_uid109_constMult_q <= "01000010010111010010110101000010110111010001100010011010100001";
WHEN "011000" => p8_uid109_constMult_q <= "01000101001111111101011000101111100000101000100011111010010010";
WHEN "011001" => p8_uid109_constMult_q <= "01001000001000100111111100011100001001111111100101011010000011";
WHEN "011010" => p8_uid109_constMult_q <= "01001011000001010010100000001000110011010110100110111001110100";
WHEN "011011" => p8_uid109_constMult_q <= "01001101111001111101000011110101011100101101101000011001100100";
WHEN "011100" => p8_uid109_constMult_q <= "01010000110010100111100111100010000110000100101001111001010101";
WHEN "011101" => p8_uid109_constMult_q <= "01010011101011010010001011001110101111011011101011011001000110";
WHEN "011110" => p8_uid109_constMult_q <= "01010110100011111100101110111011011000110010101100111000110110";
WHEN "011111" => p8_uid109_constMult_q <= "01011001011100100111010010101000000010001001101110011000100111";
WHEN "100000" => p8_uid109_constMult_q <= "10100011101010101110001001101011010100011111010000000111101000";
WHEN "100001" => p8_uid109_constMult_q <= "10100110100011011000101101010111111101110110010001100111011001";
WHEN "100010" => p8_uid109_constMult_q <= "10101001011100000011010001000100100111001101010011000111001010";
WHEN "100011" => p8_uid109_constMult_q <= "10101100010100101101110100110001010000100100010100100110111010";
WHEN "100100" => p8_uid109_constMult_q <= "10101111001101011000011000011101111001111011010110000110101011";
WHEN "100101" => p8_uid109_constMult_q <= "10110010000110000010111100001010100011010010010111100110011100";
WHEN "100110" => p8_uid109_constMult_q <= "10110100111110101101011111110111001100101001011001000110001100";
WHEN "100111" => p8_uid109_constMult_q <= "10110111110111011000000011100011110110000000011010100101111101";
WHEN "101000" => p8_uid109_constMult_q <= "10111010110000000010100111010000011111010111011100000101101110";
WHEN "101001" => p8_uid109_constMult_q <= "10111101101000101101001010111101001000101110011101100101011111";
WHEN "101010" => p8_uid109_constMult_q <= "11000000100001010111101110101001110010000101011111000101010000";
WHEN "101011" => p8_uid109_constMult_q <= "11000011011010000010010010010110011011011100100000100101000000";
WHEN "101100" => p8_uid109_constMult_q <= "11000110010010101100110110000011000100110011100010000100110001";
WHEN "101101" => p8_uid109_constMult_q <= "11001001001011010111011001101111101110001010100011100100100010";
WHEN "101110" => p8_uid109_constMult_q <= "11001100000100000001111101011100010111100001100101000100010010";
WHEN "101111" => p8_uid109_constMult_q <= "11001110111100101100100001001001000000111000100110100100000011";
WHEN "110000" => p8_uid109_constMult_q <= "11010001110101010111000100110101101010001111101000000011110100";
WHEN "110001" => p8_uid109_constMult_q <= "11010100101110000001101000100010010011100110101001100011100101";
WHEN "110010" => p8_uid109_constMult_q <= "11010111100110101100001100001110111100111101101011000011010110";
WHEN "110011" => p8_uid109_constMult_q <= "11011010011111010110101111111011100110010100101100100011000110";
WHEN "110100" => p8_uid109_constMult_q <= "11011101011000000001010011101000001111101011101110000010110111";
WHEN "110101" => p8_uid109_constMult_q <= "11100000010000101011110111010100111001000010101111100010101000";
WHEN "110110" => p8_uid109_constMult_q <= "11100011001001010110011011000001100010011001110001000010011000";
WHEN "110111" => p8_uid109_constMult_q <= "11100110000010000000111110101110001011110000110010100010001001";
WHEN "111000" => p8_uid109_constMult_q <= "11101000111010101011100010011010110101000111110100000001111010";
WHEN "111001" => p8_uid109_constMult_q <= "11101011110011010110000110000111011110011110110101100001101011";
WHEN "111010" => p8_uid109_constMult_q <= "11101110101100000000101001110100000111110101110111000001011100";
WHEN "111011" => p8_uid109_constMult_q <= "11110001100100101011001101100000110001001100111000100001001100";
WHEN "111100" => p8_uid109_constMult_q <= "11110100011101010101110001001101011010100011111010000000111101";
WHEN "111101" => p8_uid109_constMult_q <= "11110111010110000000010100111010000011111010111011100000101110";
WHEN "111110" => p8_uid109_constMult_q <= "11111010001110101010111000100110101101010001111101000000011110";
WHEN "111111" => p8_uid109_constMult_q <= "11111101000111010101011100010011010110101000111110100000001111";
WHEN OTHERS =>
p8_uid109_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid118_constMult(ADD,117)@2
lev1_a0_uid118_constMult_a <= STD_LOGIC_VECTOR((63 downto 62 => p8_uid109_constMult_q(61)) & p8_uid109_constMult_q);
lev1_a0_uid118_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p7_uid110_constMult_q);
lev1_a0_uid118_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev1_a0_uid118_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev1_a0_uid118_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid118_constMult_a) + SIGNED(lev1_a0_uid118_constMult_b));
END IF;
END IF;
END PROCESS;
lev1_a0_uid118_constMult_q <= lev1_a0_uid118_constMult_o(62 downto 0);
--lev2_a0_uid122_constMult(ADD,121)@3
lev2_a0_uid122_constMult_a <= STD_LOGIC_VECTOR((64 downto 63 => lev1_a0_uid118_constMult_q(62)) & lev1_a0_uid118_constMult_q);
lev2_a0_uid122_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000000" & lev1_a1_uid119_constMult_q);
lev2_a0_uid122_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev2_a0_uid122_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev2_a0_uid122_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev2_a0_uid122_constMult_a) + SIGNED(lev2_a0_uid122_constMult_b));
END IF;
END IF;
END PROCESS;
lev2_a0_uid122_constMult_q <= lev2_a0_uid122_constMult_o(63 downto 0);
--lev3_a0_uid124_constMult(ADD,123)@4
lev3_a0_uid124_constMult_a <= STD_LOGIC_VECTOR((65 downto 64 => lev2_a0_uid122_constMult_q(63)) & lev2_a0_uid122_constMult_q);
lev3_a0_uid124_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000" & lev2_a1_uid123_constMult_q);
lev3_a0_uid124_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev3_a0_uid124_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev3_a0_uid124_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev3_a0_uid124_constMult_a) + SIGNED(lev3_a0_uid124_constMult_b));
END IF;
END IF;
END PROCESS;
lev3_a0_uid124_constMult_q <= lev3_a0_uid124_constMult_o(64 downto 0);
--lev4_a0_uid125_constMult(ADD,124)@5
lev4_a0_uid125_constMult_a <= STD_LOGIC_VECTOR((66 downto 65 => lev3_a0_uid124_constMult_q(64)) & lev3_a0_uid124_constMult_q);
lev4_a0_uid125_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000000000000000000000000000" & p0_uid117_constMult_q);
lev4_a0_uid125_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev4_a0_uid125_constMult_a) + SIGNED(lev4_a0_uid125_constMult_b));
lev4_a0_uid125_constMult_q <= lev4_a0_uid125_constMult_o(65 downto 0);
--sR_uid126_constMult(BITSELECT,125)@5
sR_uid126_constMult_in <= lev4_a0_uid125_constMult_q(61 downto 0);
sR_uid126_constMult_b <= sR_uid126_constMult_in(61 downto 4);
--oFracXZwE_uid39_fpExpETest(BITJOIN,38)@5
oFracXZwE_uid39_fpExpETest_q <= sR_uid126_constMult_b & cstZeroWE_uid11_fpExpETest_q;
--msbx_uid128_fxpInPostAlign_uid45_fpExpETest(BITSELECT,127)@5
msbx_uid128_fxpInPostAlign_uid45_fpExpETest_in <= oFracXZwE_uid39_fpExpETest_q;
msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b <= msbx_uid128_fxpInPostAlign_uid45_fpExpETest_in(68 downto 68);
--ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b(DELAY,581)@5
ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest(LOGICAL,169)@7
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_a <= GND_q;
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_b <= ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q;
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest(BITSELECT,170)@8
RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_in(68 downto 1);
--rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest(BITJOIN,171)@8
rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q & RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_b;
--z_uid163_fxpInPostAlign_uid45_fpExpETest(CONSTANT,162)
z_uid163_fxpInPostAlign_uid45_fpExpETest_q <= "000000";
--rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest(LOGICAL,163)@7
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_a <= z_uid163_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b(DELAY,563)@5
ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid149_fxpInPostAlign_uid45_fpExpETest(CONSTANT,148)
z_uid149_fxpInPostAlign_uid45_fpExpETest_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest(LOGICAL,149)@6
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_a <= z_uid149_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest(CONSTANT,136)
rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest(LOGICAL,137)@5
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_a <= rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((68 downto 1 => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b(0)) & msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b);
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 69, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid133_fxpInPostAlign_uid45_fpExpETest(CONSTANT,132)
z_uid133_fxpInPostAlign_uid45_fpExpETest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest(LOGICAL,133)@5
rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_a <= z_uid133_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b(0)) & msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b);
rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_b;
--X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest(BITSELECT,134)@5
X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_in <= oFracXZwE_uid39_fpExpETest_q;
X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_b <= X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_in(68 downto 64);
--rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest(BITJOIN,135)@5
rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_q & X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_b;
--reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4(REG,354)@5
reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q <= rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--z_uid129_fxpInPostAlign_uid45_fpExpETest(CONSTANT,128)
z_uid129_fxpInPostAlign_uid45_fpExpETest_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest(LOGICAL,129)@5
rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_a <= z_uid129_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b(0)) & msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b);
rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_b;
--X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest(BITSELECT,130)@5
X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_in <= oFracXZwE_uid39_fpExpETest_q;
X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_b <= X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_in(68 downto 32);
--rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest(BITJOIN,131)@5
rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_q & X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_b;
--reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3(REG,353)@5
reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q <= rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2(REG,352)@5
reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q <= oFracXZwE_uid39_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid14_fpExpETest(CONSTANT,13)
cstBiasPWE_uid14_fpExpETest_q <= "1000001";
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable(LOGICAL,884)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_a <= en;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q <= not ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_a;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor(LOGICAL,885)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_b <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_q <= not (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_a or ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_b);
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top(CONSTANT,881)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top_q <= "010";
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp(LOGICAL,882)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q);
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_q <= "1" when ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_a = ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_b else "0";
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg(REG,883)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena(REG,886)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_q = "1") THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd(LOGICAL,887)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_b <= en;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_a and ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_b;
--expX_uid6_fpExpETest(BITSELECT,5)@0
expX_uid6_fpExpETest_in <= a(62 downto 0);
expX_uid6_fpExpETest_b <= expX_uid6_fpExpETest_in(62 downto 52);
--cstBiasPWE_uid13_fpExpETest(CONSTANT,12)
cstBiasPWE_uid13_fpExpETest_q <= "10000001010";
--shiftValuePreSat_uid40_fpExpETest(SUB,39)@0
shiftValuePreSat_uid40_fpExpETest_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid13_fpExpETest_q);
shiftValuePreSat_uid40_fpExpETest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExpETest_b);
shiftValuePreSat_uid40_fpExpETest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid40_fpExpETest_a) - UNSIGNED(shiftValuePreSat_uid40_fpExpETest_b));
shiftValuePreSat_uid40_fpExpETest_q <= shiftValuePreSat_uid40_fpExpETest_o(11 downto 0);
--shiftValuePreSatRed_uid43_fpExpETest(BITSELECT,42)@0
shiftValuePreSatRed_uid43_fpExpETest_in <= shiftValuePreSat_uid40_fpExpETest_q(6 downto 0);
shiftValuePreSatRed_uid43_fpExpETest_b <= shiftValuePreSatRed_uid43_fpExpETest_in(6 downto 0);
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg(DELAY,875)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid43_fpExpETest_b, xout => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt(COUNTER,877)
-- every=1, low=0, high=2, step=1, init=1
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i = 1 THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq <= '1';
ELSE
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i - 2;
ELSE
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i,2));
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg(REG,878)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux(MUX,879)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s <= en;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux: PROCESS (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s, ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q, ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q)
BEGIN
CASE ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s IS
WHEN "0" => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q;
WHEN "1" => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q;
WHEN OTHERS => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem(DUALMEM,876)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ia <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_aa <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ab <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_iq,
address_a => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_aa,
data_a => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ia
);
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_reset0 <= areset;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_iq(6 downto 0);
--reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0(REG,341)@0
reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q <= shiftValuePreSat_uid40_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid42_fpExpETest(COMPARE,41)@1
shiftUdf_uid42_fpExpETest_cin <= GND_q;
shiftUdf_uid42_fpExpETest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q(11)) & reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q) & '0';
shiftUdf_uid42_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid14_fpExpETest_q) & shiftUdf_uid42_fpExpETest_cin(0);
shiftUdf_uid42_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid42_fpExpETest_a) - SIGNED(shiftUdf_uid42_fpExpETest_b));
shiftUdf_uid42_fpExpETest_n(0) <= not shiftUdf_uid42_fpExpETest_o(14);
--ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b(DELAY,451)@1
ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => shiftUdf_uid42_fpExpETest_n, xout => ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--shiftVal_uid44_fpExpETest(MUX,43)@5
shiftVal_uid44_fpExpETest_s <= ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b_q;
shiftVal_uid44_fpExpETest: PROCESS (shiftVal_uid44_fpExpETest_s, en, ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q, cstBiasPWE_uid14_fpExpETest_q)
BEGIN
CASE shiftVal_uid44_fpExpETest_s IS
WHEN "0" => shiftVal_uid44_fpExpETest_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q;
WHEN "1" => shiftVal_uid44_fpExpETest_q <= cstBiasPWE_uid14_fpExpETest_q;
WHEN OTHERS => shiftVal_uid44_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest(BITSELECT,138)@5
rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q;
rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1(REG,351)@5
reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q <= rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest(MUX,139)@6
rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s, en, reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q, reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q, reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q, rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "00" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q;
WHEN "01" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q;
WHEN "10" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q;
WHEN "11" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest(BITSELECT,150)@6
RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_in(68 downto 24);
--ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a(DELAY,573)@6
ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest(BITJOIN,151)@7
rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid145_fxpInPostAlign_uid45_fpExpETest(CONSTANT,144)
z_uid145_fxpInPostAlign_uid45_fpExpETest_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest(LOGICAL,145)@6
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_a <= z_uid145_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest(BITSELECT,146)@6
RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_in(68 downto 16);
--ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a(DELAY,569)@6
ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest(BITJOIN,147)@7
rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid141_fxpInPostAlign_uid45_fpExpETest(CONSTANT,140)
z_uid141_fxpInPostAlign_uid45_fpExpETest_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest(LOGICAL,141)@6
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_a <= z_uid141_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest(BITSELECT,142)@6
RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_in(68 downto 8);
--ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a(DELAY,565)@6
ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest(BITJOIN,143)@7
rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a_q;
--reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2(REG,356)@6
reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest(BITSELECT,152)@5
rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q(4 downto 0);
rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_in(4 downto 3);
--ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a(DELAY,809)@5
ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1(REG,355)@6
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q <= ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest(MUX,153)@7
rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s, en, reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q, rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "10" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "11" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest(BITSELECT,164)@7
RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_in(68 downto 6);
--ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a(DELAY,591)@7
ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest(BITJOIN,165)@8
rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid159_fxpInPostAlign_uid45_fpExpETest(CONSTANT,158)
z_uid159_fxpInPostAlign_uid45_fpExpETest_q <= "0000";
--rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest(LOGICAL,159)@7
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_a <= z_uid159_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest(BITSELECT,160)@7
RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_in(68 downto 4);
--ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a(DELAY,587)@7
ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest(BITJOIN,161)@8
rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid155_fxpInPostAlign_uid45_fpExpETest(CONSTANT,154)
z_uid155_fxpInPostAlign_uid45_fpExpETest_q <= "00";
--rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest(LOGICAL,155)@7
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_a <= z_uid155_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest(BITSELECT,156)@7
RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_in(68 downto 2);
--ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a(DELAY,583)@7
ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest(BITJOIN,157)@8
rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a_q;
--reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2(REG,358)@7
reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest(BITSELECT,166)@5
rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q(2 downto 0);
rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a(DELAY,811)@5
ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1(REG,357)@7
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q <= ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest(MUX,167)@8
rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s, en, reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q, rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "00" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q;
WHEN "01" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "10" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "11" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest(BITSELECT,172)@5
rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q(0 downto 0);
rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_in(0 downto 0);
--ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a(DELAY,813)@5
ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1(REG,359)@7
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q <= ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest(MUX,173)@8
rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s, en, rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "0" => rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "1" => rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--ePreRnd_uid46_fpExpETest(BITSELECT,45)@8
ePreRnd_uid46_fpExpETest_in <= rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q;
ePreRnd_uid46_fpExpETest_b <= ePreRnd_uid46_fpExpETest_in(68 downto 55);
--xv0_uid176_constMult(BITSELECT,175)@8
xv0_uid176_constMult_in <= ePreRnd_uid46_fpExpETest_b(5 downto 0);
xv0_uid176_constMult_b <= xv0_uid176_constMult_in(5 downto 0);
--ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a(DELAY,826)@8
ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => xv0_uid176_constMult_b, xout => ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0(REG,372)@10
reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q <= ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p0_uid181_constMult(LOOKUP,180)@11
p0_uid181_constMult: PROCESS (reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q) IS
WHEN "000000" => p0_uid181_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid181_constMult_q <= "000000101100010111001000010111111101111101000111001111011110011010110";
WHEN "000010" => p0_uid181_constMult_q <= "000001011000101110010000101111111011111010001110011110111100110101100";
WHEN "000011" => p0_uid181_constMult_q <= "000010000101000101011001000111111001110111010101101110011011010000010";
WHEN "000100" => p0_uid181_constMult_q <= "000010110001011100100001011111110111110100011100111101111001101011000";
WHEN "000101" => p0_uid181_constMult_q <= "000011011101110011101001110111110101110001100100001101011000000101110";
WHEN "000110" => p0_uid181_constMult_q <= "000100001010001010110010001111110011101110101011011100110110100000100";
WHEN "000111" => p0_uid181_constMult_q <= "000100110110100001111010100111110001101011110010101100010100111011010";
WHEN "001000" => p0_uid181_constMult_q <= "000101100010111001000010111111101111101000111001111011110011010110000";
WHEN "001001" => p0_uid181_constMult_q <= "000110001111010000001011010111101101100110000001001011010001110000110";
WHEN "001010" => p0_uid181_constMult_q <= "000110111011100111010011101111101011100011001000011010110000001011100";
WHEN "001011" => p0_uid181_constMult_q <= "000111100111111110011100000111101001100000001111101010001110100110010";
WHEN "001100" => p0_uid181_constMult_q <= "001000010100010101100100011111100111011101010110111001101101000001000";
WHEN "001101" => p0_uid181_constMult_q <= "001001000000101100101100110111100101011010011110001001001011011011110";
WHEN "001110" => p0_uid181_constMult_q <= "001001101101000011110101001111100011010111100101011000101001110110100";
WHEN "001111" => p0_uid181_constMult_q <= "001010011001011010111101100111100001010100101100101000001000010001010";
WHEN "010000" => p0_uid181_constMult_q <= "001011000101110010000101111111011111010001110011110111100110101100000";
WHEN "010001" => p0_uid181_constMult_q <= "001011110010001001001110010111011101001110111011000111000101000110110";
WHEN "010010" => p0_uid181_constMult_q <= "001100011110100000010110101111011011001100000010010110100011100001100";
WHEN "010011" => p0_uid181_constMult_q <= "001101001010110111011111000111011001001001001001100110000001111100010";
WHEN "010100" => p0_uid181_constMult_q <= "001101110111001110100111011111010111000110010000110101100000010111000";
WHEN "010101" => p0_uid181_constMult_q <= "001110100011100101101111110111010101000011011000000100111110110001110";
WHEN "010110" => p0_uid181_constMult_q <= "001111001111111100111000001111010011000000011111010100011101001100100";
WHEN "010111" => p0_uid181_constMult_q <= "001111111100010100000000100111010000111101100110100011111011100111010";
WHEN "011000" => p0_uid181_constMult_q <= "010000101000101011001000111111001110111010101101110011011010000010000";
WHEN "011001" => p0_uid181_constMult_q <= "010001010101000010010001010111001100110111110101000010111000011100110";
WHEN "011010" => p0_uid181_constMult_q <= "010010000001011001011001101111001010110100111100010010010110110111100";
WHEN "011011" => p0_uid181_constMult_q <= "010010101101110000100010000111001000110010000011100001110101010010010";
WHEN "011100" => p0_uid181_constMult_q <= "010011011010000111101010011111000110101111001010110001010011101101000";
WHEN "011101" => p0_uid181_constMult_q <= "010100000110011110110010110111000100101100010010000000110010000111110";
WHEN "011110" => p0_uid181_constMult_q <= "010100110010110101111011001111000010101001011001010000010000100010100";
WHEN "011111" => p0_uid181_constMult_q <= "010101011111001101000011100111000000100110100000011111101110111101010";
WHEN "100000" => p0_uid181_constMult_q <= "010110001011100100001011111110111110100011100111101111001101011000000";
WHEN "100001" => p0_uid181_constMult_q <= "010110110111111011010100010110111100100000101110111110101011110010110";
WHEN "100010" => p0_uid181_constMult_q <= "010111100100010010011100101110111010011101110110001110001010001101100";
WHEN "100011" => p0_uid181_constMult_q <= "011000010000101001100101000110111000011010111101011101101000101000010";
WHEN "100100" => p0_uid181_constMult_q <= "011000111101000000101101011110110110011000000100101101000111000011000";
WHEN "100101" => p0_uid181_constMult_q <= "011001101001010111110101110110110100010101001011111100100101011101110";
WHEN "100110" => p0_uid181_constMult_q <= "011010010101101110111110001110110010010010010011001100000011111000100";
WHEN "100111" => p0_uid181_constMult_q <= "011011000010000110000110100110110000001111011010011011100010010011010";
WHEN "101000" => p0_uid181_constMult_q <= "011011101110011101001110111110101110001100100001101011000000101110000";
WHEN "101001" => p0_uid181_constMult_q <= "011100011010110100010111010110101100001001101000111010011111001000110";
WHEN "101010" => p0_uid181_constMult_q <= "011101000111001011011111101110101010000110110000001001111101100011100";
WHEN "101011" => p0_uid181_constMult_q <= "011101110011100010101000000110101000000011110111011001011011111110010";
WHEN "101100" => p0_uid181_constMult_q <= "011110011111111001110000011110100110000000111110101000111010011001000";
WHEN "101101" => p0_uid181_constMult_q <= "011111001100010000111000110110100011111110000101111000011000110011110";
WHEN "101110" => p0_uid181_constMult_q <= "011111111000101000000001001110100001111011001101000111110111001110100";
WHEN "101111" => p0_uid181_constMult_q <= "100000100100111111001001100110011111111000010100010111010101101001010";
WHEN "110000" => p0_uid181_constMult_q <= "100001010001010110010001111110011101110101011011100110110100000100000";
WHEN "110001" => p0_uid181_constMult_q <= "100001111101101101011010010110011011110010100010110110010010011110110";
WHEN "110010" => p0_uid181_constMult_q <= "100010101010000100100010101110011001101111101010000101110000111001100";
WHEN "110011" => p0_uid181_constMult_q <= "100011010110011011101011000110010111101100110001010101001111010100010";
WHEN "110100" => p0_uid181_constMult_q <= "100100000010110010110011011110010101101001111000100100101101101111000";
WHEN "110101" => p0_uid181_constMult_q <= "100100101111001001111011110110010011100110111111110100001100001001110";
WHEN "110110" => p0_uid181_constMult_q <= "100101011011100001000100001110010001100100000111000011101010100100100";
WHEN "110111" => p0_uid181_constMult_q <= "100110000111111000001100100110001111100001001110010011001000111111010";
WHEN "111000" => p0_uid181_constMult_q <= "100110110100001111010100111110001101011110010101100010100111011010000";
WHEN "111001" => p0_uid181_constMult_q <= "100111100000100110011101010110001011011011011100110010000101110100110";
WHEN "111010" => p0_uid181_constMult_q <= "101000001100111101100101101110001001011000100100000001100100001111100";
WHEN "111011" => p0_uid181_constMult_q <= "101000111001010100101110000110000111010101101011010001000010101010010";
WHEN "111100" => p0_uid181_constMult_q <= "101001100101101011110110011110000101010010110010100000100001000101000";
WHEN "111101" => p0_uid181_constMult_q <= "101010010010000010111110110110000011001111111001101111111111011111110";
WHEN "111110" => p0_uid181_constMult_q <= "101010111110011010000111001110000001001101000000111111011101111010100";
WHEN "111111" => p0_uid181_constMult_q <= "101011101010110001001111100101111111001010001000001110111100010101010";
WHEN OTHERS =>
p0_uid181_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid177_constMult(BITSELECT,176)@8
xv1_uid177_constMult_in <= ePreRnd_uid46_fpExpETest_b(11 downto 0);
xv1_uid177_constMult_b <= xv1_uid177_constMult_in(11 downto 6);
--ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a(DELAY,825)@8
ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => xv1_uid177_constMult_b, xout => ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0(REG,371)@9
reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q <= ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p1_uid180_constMult(LOOKUP,179)@10
p1_uid180_constMult: PROCESS (reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q) IS
WHEN "000000" => p1_uid180_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid180_constMult_q <= "000000101100010111001000010111111101111101000111001111011110011010110000000";
WHEN "000010" => p1_uid180_constMult_q <= "000001011000101110010000101111111011111010001110011110111100110101100000000";
WHEN "000011" => p1_uid180_constMult_q <= "000010000101000101011001000111111001110111010101101110011011010000010000000";
WHEN "000100" => p1_uid180_constMult_q <= "000010110001011100100001011111110111110100011100111101111001101011000000000";
WHEN "000101" => p1_uid180_constMult_q <= "000011011101110011101001110111110101110001100100001101011000000101110000000";
WHEN "000110" => p1_uid180_constMult_q <= "000100001010001010110010001111110011101110101011011100110110100000100000000";
WHEN "000111" => p1_uid180_constMult_q <= "000100110110100001111010100111110001101011110010101100010100111011010000000";
WHEN "001000" => p1_uid180_constMult_q <= "000101100010111001000010111111101111101000111001111011110011010110000000000";
WHEN "001001" => p1_uid180_constMult_q <= "000110001111010000001011010111101101100110000001001011010001110000110000000";
WHEN "001010" => p1_uid180_constMult_q <= "000110111011100111010011101111101011100011001000011010110000001011100000000";
WHEN "001011" => p1_uid180_constMult_q <= "000111100111111110011100000111101001100000001111101010001110100110010000000";
WHEN "001100" => p1_uid180_constMult_q <= "001000010100010101100100011111100111011101010110111001101101000001000000000";
WHEN "001101" => p1_uid180_constMult_q <= "001001000000101100101100110111100101011010011110001001001011011011110000000";
WHEN "001110" => p1_uid180_constMult_q <= "001001101101000011110101001111100011010111100101011000101001110110100000000";
WHEN "001111" => p1_uid180_constMult_q <= "001010011001011010111101100111100001010100101100101000001000010001010000000";
WHEN "010000" => p1_uid180_constMult_q <= "001011000101110010000101111111011111010001110011110111100110101100000000000";
WHEN "010001" => p1_uid180_constMult_q <= "001011110010001001001110010111011101001110111011000111000101000110110000000";
WHEN "010010" => p1_uid180_constMult_q <= "001100011110100000010110101111011011001100000010010110100011100001100000000";
WHEN "010011" => p1_uid180_constMult_q <= "001101001010110111011111000111011001001001001001100110000001111100010000000";
WHEN "010100" => p1_uid180_constMult_q <= "001101110111001110100111011111010111000110010000110101100000010111000000000";
WHEN "010101" => p1_uid180_constMult_q <= "001110100011100101101111110111010101000011011000000100111110110001110000000";
WHEN "010110" => p1_uid180_constMult_q <= "001111001111111100111000001111010011000000011111010100011101001100100000000";
WHEN "010111" => p1_uid180_constMult_q <= "001111111100010100000000100111010000111101100110100011111011100111010000000";
WHEN "011000" => p1_uid180_constMult_q <= "010000101000101011001000111111001110111010101101110011011010000010000000000";
WHEN "011001" => p1_uid180_constMult_q <= "010001010101000010010001010111001100110111110101000010111000011100110000000";
WHEN "011010" => p1_uid180_constMult_q <= "010010000001011001011001101111001010110100111100010010010110110111100000000";
WHEN "011011" => p1_uid180_constMult_q <= "010010101101110000100010000111001000110010000011100001110101010010010000000";
WHEN "011100" => p1_uid180_constMult_q <= "010011011010000111101010011111000110101111001010110001010011101101000000000";
WHEN "011101" => p1_uid180_constMult_q <= "010100000110011110110010110111000100101100010010000000110010000111110000000";
WHEN "011110" => p1_uid180_constMult_q <= "010100110010110101111011001111000010101001011001010000010000100010100000000";
WHEN "011111" => p1_uid180_constMult_q <= "010101011111001101000011100111000000100110100000011111101110111101010000000";
WHEN "100000" => p1_uid180_constMult_q <= "010110001011100100001011111110111110100011100111101111001101011000000000000";
WHEN "100001" => p1_uid180_constMult_q <= "010110110111111011010100010110111100100000101110111110101011110010110000000";
WHEN "100010" => p1_uid180_constMult_q <= "010111100100010010011100101110111010011101110110001110001010001101100000000";
WHEN "100011" => p1_uid180_constMult_q <= "011000010000101001100101000110111000011010111101011101101000101000010000000";
WHEN "100100" => p1_uid180_constMult_q <= "011000111101000000101101011110110110011000000100101101000111000011000000000";
WHEN "100101" => p1_uid180_constMult_q <= "011001101001010111110101110110110100010101001011111100100101011101110000000";
WHEN "100110" => p1_uid180_constMult_q <= "011010010101101110111110001110110010010010010011001100000011111000100000000";
WHEN "100111" => p1_uid180_constMult_q <= "011011000010000110000110100110110000001111011010011011100010010011010000000";
WHEN "101000" => p1_uid180_constMult_q <= "011011101110011101001110111110101110001100100001101011000000101110000000000";
WHEN "101001" => p1_uid180_constMult_q <= "011100011010110100010111010110101100001001101000111010011111001000110000000";
WHEN "101010" => p1_uid180_constMult_q <= "011101000111001011011111101110101010000110110000001001111101100011100000000";
WHEN "101011" => p1_uid180_constMult_q <= "011101110011100010101000000110101000000011110111011001011011111110010000000";
WHEN "101100" => p1_uid180_constMult_q <= "011110011111111001110000011110100110000000111110101000111010011001000000000";
WHEN "101101" => p1_uid180_constMult_q <= "011111001100010000111000110110100011111110000101111000011000110011110000000";
WHEN "101110" => p1_uid180_constMult_q <= "011111111000101000000001001110100001111011001101000111110111001110100000000";
WHEN "101111" => p1_uid180_constMult_q <= "100000100100111111001001100110011111111000010100010111010101101001010000000";
WHEN "110000" => p1_uid180_constMult_q <= "100001010001010110010001111110011101110101011011100110110100000100000000000";
WHEN "110001" => p1_uid180_constMult_q <= "100001111101101101011010010110011011110010100010110110010010011110110000000";
WHEN "110010" => p1_uid180_constMult_q <= "100010101010000100100010101110011001101111101010000101110000111001100000000";
WHEN "110011" => p1_uid180_constMult_q <= "100011010110011011101011000110010111101100110001010101001111010100010000000";
WHEN "110100" => p1_uid180_constMult_q <= "100100000010110010110011011110010101101001111000100100101101101111000000000";
WHEN "110101" => p1_uid180_constMult_q <= "100100101111001001111011110110010011100110111111110100001100001001110000000";
WHEN "110110" => p1_uid180_constMult_q <= "100101011011100001000100001110010001100100000111000011101010100100100000000";
WHEN "110111" => p1_uid180_constMult_q <= "100110000111111000001100100110001111100001001110010011001000111111010000000";
WHEN "111000" => p1_uid180_constMult_q <= "100110110100001111010100111110001101011110010101100010100111011010000000000";
WHEN "111001" => p1_uid180_constMult_q <= "100111100000100110011101010110001011011011011100110010000101110100110000000";
WHEN "111010" => p1_uid180_constMult_q <= "101000001100111101100101101110001001011000100100000001100100001111100000000";
WHEN "111011" => p1_uid180_constMult_q <= "101000111001010100101110000110000111010101101011010001000010101010010000000";
WHEN "111100" => p1_uid180_constMult_q <= "101001100101101011110110011110000101010010110010100000100001000101000000000";
WHEN "111101" => p1_uid180_constMult_q <= "101010010010000010111110110110000011001111111001101111111111011111110000000";
WHEN "111110" => p1_uid180_constMult_q <= "101010111110011010000111001110000001001101000000111111011101111010100000000";
WHEN "111111" => p1_uid180_constMult_q <= "101011101010110001001111100101111111001010001000001110111100010101010000000";
WHEN OTHERS =>
p1_uid180_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv2_uid178_constMult(BITSELECT,177)@8
xv2_uid178_constMult_in <= ePreRnd_uid46_fpExpETest_b;
xv2_uid178_constMult_b <= xv2_uid178_constMult_in(13 downto 12);
--reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0(REG,370)@8
reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q <= xv2_uid178_constMult_b;
END IF;
END IF;
END PROCESS;
--p2_uid179_constMult(LOOKUP,178)@9
p2_uid179_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p2_uid179_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q) IS
WHEN "00" => p2_uid179_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "01" => p2_uid179_constMult_q <= "00101100010111001000010111111101111101000111001111011110011010110000000000000";
WHEN "10" => p2_uid179_constMult_q <= "10100111010001101111010000000100000101110001100001000011001010100000000000000";
WHEN "11" => p2_uid179_constMult_q <= "11010011101000110111101000000010000010111000110000100001100101010000000000000";
WHEN OTHERS =>
p2_uid179_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid182_constMult(ADD,181)@10
lev1_a0_uid182_constMult_a <= STD_LOGIC_VECTOR((78 downto 77 => p2_uid179_constMult_q(76)) & p2_uid179_constMult_q);
lev1_a0_uid182_constMult_b <= STD_LOGIC_VECTOR('0' & "000" & p1_uid180_constMult_q);
lev1_a0_uid182_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev1_a0_uid182_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev1_a0_uid182_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid182_constMult_a) + SIGNED(lev1_a0_uid182_constMult_b));
END IF;
END IF;
END PROCESS;
lev1_a0_uid182_constMult_q <= lev1_a0_uid182_constMult_o(77 downto 0);
--lev2_a0_uid183_constMult(ADD,182)@11
lev2_a0_uid183_constMult_a <= STD_LOGIC_VECTOR((79 downto 78 => lev1_a0_uid182_constMult_q(77)) & lev1_a0_uid182_constMult_q);
lev2_a0_uid183_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000" & p0_uid181_constMult_q);
lev2_a0_uid183_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev2_a0_uid183_constMult_a) + SIGNED(lev2_a0_uid183_constMult_b));
lev2_a0_uid183_constMult_q <= lev2_a0_uid183_constMult_o(78 downto 0);
--sR_uid184_constMult(BITSELECT,183)@11
sR_uid184_constMult_in <= lev2_a0_uid183_constMult_q(76 downto 0);
sR_uid184_constMult_b <= sR_uid184_constMult_in(76 downto 2);
--reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1(REG,374)@11
reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q <= sR_uid184_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b(DELAY,456)@0
ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 8 )
PORT MAP ( xin => signX_uid7_fpExpETest_b, xout => ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor(LOGICAL,898)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_b <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_q <= not (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_a or ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_b);
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top(CONSTANT,894)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top_q <= "0101";
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp(LOGICAL,895)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_a <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q);
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_q <= "1" when ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_a = ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_b else "0";
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg(REG,896)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena(REG,899)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_q = "1") THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd(LOGICAL,900)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_a <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_b <= en;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_a and ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_b;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg(DELAY,888)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oFracX_uid32_uid32_fpExpETest_q, xout => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt(COUNTER,890)
-- every=1, low=0, high=5, step=1, init=1
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i = 4 THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i - 5;
ELSE
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i,3));
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg(REG,891)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux(MUX,892)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s <= en;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux: PROCESS (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s, ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q, ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem(DUALMEM,889)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ia <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_aa <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ab <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 6,
width_b => 53,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_iq,
address_a => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_aa,
data_a => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ia
);
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_reset0 <= areset;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_iq(52 downto 0);
--cstZeroWEP1_uid12_fpExpETest(CONSTANT,11)
cstZeroWEP1_uid12_fpExpETest_q <= "000000000000";
--oFracXZwE_uid48_fpExpETest(BITJOIN,47)@8
oFracXZwE_uid48_fpExpETest_q <= GND_q & ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_q & cstZeroWEP1_uid12_fpExpETest_q;
--onesCmpFxpIn_uid49_fpExpETest(LOGICAL,48)@8
onesCmpFxpIn_uid49_fpExpETest_a <= oFracXZwE_uid48_fpExpETest_q;
onesCmpFxpIn_uid49_fpExpETest_b <= STD_LOGIC_VECTOR((65 downto 1 => ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q(0)) & ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q);
onesCmpFxpIn_uid49_fpExpETest_q <= onesCmpFxpIn_uid49_fpExpETest_a xor onesCmpFxpIn_uid49_fpExpETest_b;
--fxpInExt_uid50_fpExpETest(ADD,49)@8
fxpInExt_uid50_fpExpETest_a <= STD_LOGIC_VECTOR((67 downto 66 => onesCmpFxpIn_uid49_fpExpETest_q(65)) & onesCmpFxpIn_uid49_fpExpETest_q);
fxpInExt_uid50_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q);
fxpInExt_uid50_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid50_fpExpETest_a) + SIGNED(fxpInExt_uid50_fpExpETest_b));
fxpInExt_uid50_fpExpETest_q <= fxpInExt_uid50_fpExpETest_o(66 downto 0);
--fxpInPreAlign_uid51_fpExpETest(BITSELECT,50)@8
fxpInPreAlign_uid51_fpExpETest_in <= fxpInExt_uid50_fpExpETest_q(65 downto 0);
fxpInPreAlign_uid51_fpExpETest_b <= fxpInPreAlign_uid51_fpExpETest_in(65 downto 0);
--msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,185)@8
msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_in <= fxpInPreAlign_uid51_fpExpETest_b;
msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b <= msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 65);
--rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,227)@8
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_a <= GND_q;
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_b <= msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,670)@9
ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q, xout => ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,228)@11
RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 1);
--rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,229)@11
rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q <= ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b_q & RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_b;
--ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,650)@8
ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,221)@10
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid163_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,633)@8
ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,207)@9
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid149_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest(CONSTANT,194)
rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest_q <= "000000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,195)@8
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_a <= rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest_q;
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((65 downto 1 => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b(0)) & msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b);
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 66, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,191)@8
rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid133_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b(0)) & msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b);
rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_b;
--X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,192)@8
X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_in <= fxpInPreAlign_uid51_fpExpETest_b;
X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_b <= X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 64);
--rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,193)@8
rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_q & X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_b;
--reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4(REG,364)@8
reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q <= rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,187)@8
rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid129_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b(0)) & msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b);
rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_b;
--X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,188)@8
X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_in <= fxpInPreAlign_uid51_fpExpETest_b;
X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_b <= X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 32);
--rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,189)@8
rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_q & X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_b;
--reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3(REG,363)@8
reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q <= rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2(REG,362)@8
reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q <= fxpInPreAlign_uid51_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,628)@6
ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 3 )
PORT MAP ( xin => reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q, xout => ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest(MUX,197)@9
rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s <= ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b_q;
rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s, en, reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q, reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q, reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q, rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "00" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q;
WHEN "01" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q;
WHEN "10" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q;
WHEN "11" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,208)@9
RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 24);
--ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,643)@9
ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,209)@10
rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,203)@9
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid145_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,204)@9
RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 16);
--ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,639)@9
ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,205)@10
rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,199)@9
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid141_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,200)@9
RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 8);
--ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,635)@9
ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,201)@10
rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2(REG,366)@9
reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1(REG,365)@5
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q <= rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,645)@6
ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 4 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest(MUX,211)@10
rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s <= ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b_q;
rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s, en, reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q, rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "00" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q;
WHEN "01" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "10" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "11" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,222)@10
RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 6);
--ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,660)@10
ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,223)@11
rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,217)@10
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid159_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,218)@10
RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 4);
--ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,656)@10
ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,219)@11
rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,213)@10
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid155_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,214)@10
RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 2);
--ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,652)@10
ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,215)@11
rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2(REG,368)@10
reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a(DELAY,821)@5
ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 5 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1(REG,367)@10
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q <= ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest(MUX,225)@11
rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s <= reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q;
rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s, en, reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q, rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "00" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q;
WHEN "01" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "10" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "11" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1(REG,369)@5
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q <= rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,671)@6
ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest(MUX,231)@11
rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s <= ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b_q;
rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s, en, rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "0" => rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "1" => rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest(BITJOIN,56)@11
pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_q <= rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0(REG,373)@11
reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q <= pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--yExt_uid57_fpExpETest(SUB,57)@12
yExt_uid57_fpExpETest_a <= STD_LOGIC_VECTOR((75 downto 74 => reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q(73)) & reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q);
yExt_uid57_fpExpETest_b <= STD_LOGIC_VECTOR((75 downto 75 => reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q(74)) & reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q);
yExt_uid57_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(yExt_uid57_fpExpETest_a) - SIGNED(yExt_uid57_fpExpETest_b));
yExt_uid57_fpExpETest_q <= yExt_uid57_fpExpETest_o(75 downto 0);
--yRed_uid61_fpExpETest(BITSELECT,60)@12
yRed_uid61_fpExpETest_in <= yExt_uid57_fpExpETest_q(60 downto 0);
yRed_uid61_fpExpETest_b <= yRed_uid61_fpExpETest_in(60 downto 6);
--reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2(REG,376)@12
reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q <= yRed_uid61_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--YExt75_uid59_fpExpETest(BITSELECT,58)@12
YExt75_uid59_fpExpETest_in <= yExt_uid57_fpExpETest_q;
YExt75_uid59_fpExpETest_b <= YExt75_uid59_fpExpETest_in(75 downto 75);
--reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1(REG,375)@12
reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q <= YExt75_uid59_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--yRedPostMux_uid62_fpExpETest(MUX,61)@13
yRedPostMux_uid62_fpExpETest_s <= reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q;
yRedPostMux_uid62_fpExpETest: PROCESS (yRedPostMux_uid62_fpExpETest_s, en, reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q, zY_uid60_fpExpETest_q)
BEGIN
CASE yRedPostMux_uid62_fpExpETest_s IS
WHEN "0" => yRedPostMux_uid62_fpExpETest_q <= reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q;
WHEN "1" => yRedPostMux_uid62_fpExpETest_q <= zY_uid60_fpExpETest_q;
WHEN OTHERS => yRedPostMux_uid62_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid64_fpExpETest(BITSELECT,63)@13
addr_uid64_fpExpETest_in <= yRedPostMux_uid62_fpExpETest_q;
addr_uid64_fpExpETest_b <= addr_uid64_fpExpETest_in(54 downto 48);
--reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0(REG,378)@13
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q <= addr_uid64_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid247_exp10TabGen(LOOKUP,246)@14
memoryC5_uid247_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC5_uid247_exp10TabGen_q <= "0010001001000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC5_uid247_exp10TabGen_q <= "0010001001000001";
WHEN "0000001" => memoryC5_uid247_exp10TabGen_q <= "0010001001001000";
WHEN "0000010" => memoryC5_uid247_exp10TabGen_q <= "0010001010101001";
WHEN "0000011" => memoryC5_uid247_exp10TabGen_q <= "0010001011011100";
WHEN "0000100" => memoryC5_uid247_exp10TabGen_q <= "0010001101001010";
WHEN "0000101" => memoryC5_uid247_exp10TabGen_q <= "0010001110011101";
WHEN "0000110" => memoryC5_uid247_exp10TabGen_q <= "0010001111011110";
WHEN "0000111" => memoryC5_uid247_exp10TabGen_q <= "0010010000100001";
WHEN "0001000" => memoryC5_uid247_exp10TabGen_q <= "0010010001111001";
WHEN "0001001" => memoryC5_uid247_exp10TabGen_q <= "0010010010110011";
WHEN "0001010" => memoryC5_uid247_exp10TabGen_q <= "0010010100011101";
WHEN "0001011" => memoryC5_uid247_exp10TabGen_q <= "0010010110010001";
WHEN "0001100" => memoryC5_uid247_exp10TabGen_q <= "0010010110110101";
WHEN "0001101" => memoryC5_uid247_exp10TabGen_q <= "0010010111001010";
WHEN "0001110" => memoryC5_uid247_exp10TabGen_q <= "0010011000110010";
WHEN "0001111" => memoryC5_uid247_exp10TabGen_q <= "0010011010111110";
WHEN "0010000" => memoryC5_uid247_exp10TabGen_q <= "0010011010111110";
WHEN "0010001" => memoryC5_uid247_exp10TabGen_q <= "0010011100001100";
WHEN "0010010" => memoryC5_uid247_exp10TabGen_q <= "0010011110000010";
WHEN "0010011" => memoryC5_uid247_exp10TabGen_q <= "0010011110101001";
WHEN "0010100" => memoryC5_uid247_exp10TabGen_q <= "0010100001000000";
WHEN "0010101" => memoryC5_uid247_exp10TabGen_q <= "0010100001011000";
WHEN "0010110" => memoryC5_uid247_exp10TabGen_q <= "0010100011000011";
WHEN "0010111" => memoryC5_uid247_exp10TabGen_q <= "0010100011110110";
WHEN "0011000" => memoryC5_uid247_exp10TabGen_q <= "0010100101111001";
WHEN "0011001" => memoryC5_uid247_exp10TabGen_q <= "0010100111010011";
WHEN "0011010" => memoryC5_uid247_exp10TabGen_q <= "0010100111110111";
WHEN "0011011" => memoryC5_uid247_exp10TabGen_q <= "0010101001011010";
WHEN "0011100" => memoryC5_uid247_exp10TabGen_q <= "0010101011000110";
WHEN "0011101" => memoryC5_uid247_exp10TabGen_q <= "0010101100100101";
WHEN "0011110" => memoryC5_uid247_exp10TabGen_q <= "0010101110000010";
WHEN "0011111" => memoryC5_uid247_exp10TabGen_q <= "0010101110001011";
WHEN "0100000" => memoryC5_uid247_exp10TabGen_q <= "0010110000000101";
WHEN "0100001" => memoryC5_uid247_exp10TabGen_q <= "0010110001011010";
WHEN "0100010" => memoryC5_uid247_exp10TabGen_q <= "0010110010000000";
WHEN "0100011" => memoryC5_uid247_exp10TabGen_q <= "0010110011110100";
WHEN "0100100" => memoryC5_uid247_exp10TabGen_q <= "0010110101111111";
WHEN "0100101" => memoryC5_uid247_exp10TabGen_q <= "0010110110001011";
WHEN "0100110" => memoryC5_uid247_exp10TabGen_q <= "0010111000011100";
WHEN "0100111" => memoryC5_uid247_exp10TabGen_q <= "0010111001101110";
WHEN "0101000" => memoryC5_uid247_exp10TabGen_q <= "0010111010111100";
WHEN "0101001" => memoryC5_uid247_exp10TabGen_q <= "0010111100100000";
WHEN "0101010" => memoryC5_uid247_exp10TabGen_q <= "0010111111001011";
WHEN "0101011" => memoryC5_uid247_exp10TabGen_q <= "0010111111101000";
WHEN "0101100" => memoryC5_uid247_exp10TabGen_q <= "0011000001111110";
WHEN "0101101" => memoryC5_uid247_exp10TabGen_q <= "0011000010101011";
WHEN "0101110" => memoryC5_uid247_exp10TabGen_q <= "0011000011100011";
WHEN "0101111" => memoryC5_uid247_exp10TabGen_q <= "0011000110001011";
WHEN "0110000" => memoryC5_uid247_exp10TabGen_q <= "0011000111101010";
WHEN "0110001" => memoryC5_uid247_exp10TabGen_q <= "0011001001011010";
WHEN "0110010" => memoryC5_uid247_exp10TabGen_q <= "0011001010111110";
WHEN "0110011" => memoryC5_uid247_exp10TabGen_q <= "0011001100101111";
WHEN "0110100" => memoryC5_uid247_exp10TabGen_q <= "0011001101111011";
WHEN "0110101" => memoryC5_uid247_exp10TabGen_q <= "0011001110111001";
WHEN "0110110" => memoryC5_uid247_exp10TabGen_q <= "0011010001010100";
WHEN "0110111" => memoryC5_uid247_exp10TabGen_q <= "0011010011001110";
WHEN "0111000" => memoryC5_uid247_exp10TabGen_q <= "0011010100011010";
WHEN "0111001" => memoryC5_uid247_exp10TabGen_q <= "0011010110001011";
WHEN "0111010" => memoryC5_uid247_exp10TabGen_q <= "0011010111100000";
WHEN "0111011" => memoryC5_uid247_exp10TabGen_q <= "0011011000111110";
WHEN "0111100" => memoryC5_uid247_exp10TabGen_q <= "0011011010100100";
WHEN "0111101" => memoryC5_uid247_exp10TabGen_q <= "0011011100101101";
WHEN "0111110" => memoryC5_uid247_exp10TabGen_q <= "0011011110000100";
WHEN "0111111" => memoryC5_uid247_exp10TabGen_q <= "0011100000111010";
WHEN "1000000" => memoryC5_uid247_exp10TabGen_q <= "0011100010101001";
WHEN "1000001" => memoryC5_uid247_exp10TabGen_q <= "0011100011011011";
WHEN "1000010" => memoryC5_uid247_exp10TabGen_q <= "0011100100101101";
WHEN "1000011" => memoryC5_uid247_exp10TabGen_q <= "0011100111101001";
WHEN "1000100" => memoryC5_uid247_exp10TabGen_q <= "0011101001001000";
WHEN "1000101" => memoryC5_uid247_exp10TabGen_q <= "0011101010110010";
WHEN "1000110" => memoryC5_uid247_exp10TabGen_q <= "0011101101011011";
WHEN "1000111" => memoryC5_uid247_exp10TabGen_q <= "0011101110010100";
WHEN "1001000" => memoryC5_uid247_exp10TabGen_q <= "0011110000111010";
WHEN "1001001" => memoryC5_uid247_exp10TabGen_q <= "0011110010100100";
WHEN "1001010" => memoryC5_uid247_exp10TabGen_q <= "0011110100011110";
WHEN "1001011" => memoryC5_uid247_exp10TabGen_q <= "0011110101101011";
WHEN "1001100" => memoryC5_uid247_exp10TabGen_q <= "0011110111101011";
WHEN "1001101" => memoryC5_uid247_exp10TabGen_q <= "0011111001110000";
WHEN "1001110" => memoryC5_uid247_exp10TabGen_q <= "0011111100000010";
WHEN "1001111" => memoryC5_uid247_exp10TabGen_q <= "0011111110001010";
WHEN "1010000" => memoryC5_uid247_exp10TabGen_q <= "0011111111110011";
WHEN "1010001" => memoryC5_uid247_exp10TabGen_q <= "0100000010000111";
WHEN "1010010" => memoryC5_uid247_exp10TabGen_q <= "0100000011100011";
WHEN "1010011" => memoryC5_uid247_exp10TabGen_q <= "0100000101110000";
WHEN "1010100" => memoryC5_uid247_exp10TabGen_q <= "0100000111111001";
WHEN "1010101" => memoryC5_uid247_exp10TabGen_q <= "0100001010101100";
WHEN "1010110" => memoryC5_uid247_exp10TabGen_q <= "0100001100100110";
WHEN "1010111" => memoryC5_uid247_exp10TabGen_q <= "0100001110000000";
WHEN "1011000" => memoryC5_uid247_exp10TabGen_q <= "0100010000010100";
WHEN "1011001" => memoryC5_uid247_exp10TabGen_q <= "0100010010100001";
WHEN "1011010" => memoryC5_uid247_exp10TabGen_q <= "0100010101011001";
WHEN "1011011" => memoryC5_uid247_exp10TabGen_q <= "0100011000000001";
WHEN "1011100" => memoryC5_uid247_exp10TabGen_q <= "0100011000101011";
WHEN "1011101" => memoryC5_uid247_exp10TabGen_q <= "0100011011000001";
WHEN "1011110" => memoryC5_uid247_exp10TabGen_q <= "0100011110001011";
WHEN "1011111" => memoryC5_uid247_exp10TabGen_q <= "0100100000010001";
WHEN "1100000" => memoryC5_uid247_exp10TabGen_q <= "0100100010001001";
WHEN "1100001" => memoryC5_uid247_exp10TabGen_q <= "0100100100101000";
WHEN "1100010" => memoryC5_uid247_exp10TabGen_q <= "0100100111010100";
WHEN "1100011" => memoryC5_uid247_exp10TabGen_q <= "0100101000111000";
WHEN "1100100" => memoryC5_uid247_exp10TabGen_q <= "0100101011100001";
WHEN "1100101" => memoryC5_uid247_exp10TabGen_q <= "0100101110010110";
WHEN "1100110" => memoryC5_uid247_exp10TabGen_q <= "0100110000100110";
WHEN "1100111" => memoryC5_uid247_exp10TabGen_q <= "0100110011000110";
WHEN "1101000" => memoryC5_uid247_exp10TabGen_q <= "0100110100111001";
WHEN "1101001" => memoryC5_uid247_exp10TabGen_q <= "0100110111010000";
WHEN "1101010" => memoryC5_uid247_exp10TabGen_q <= "0100111010100101";
WHEN "1101011" => memoryC5_uid247_exp10TabGen_q <= "0100111011110011";
WHEN "1101100" => memoryC5_uid247_exp10TabGen_q <= "0100111110000101";
WHEN "1101101" => memoryC5_uid247_exp10TabGen_q <= "0101000001001101";
WHEN "1101110" => memoryC5_uid247_exp10TabGen_q <= "0101000100000110";
WHEN "1101111" => memoryC5_uid247_exp10TabGen_q <= "0101000101110010";
WHEN "1110000" => memoryC5_uid247_exp10TabGen_q <= "0101001000100011";
WHEN "1110001" => memoryC5_uid247_exp10TabGen_q <= "0101001011000111";
WHEN "1110010" => memoryC5_uid247_exp10TabGen_q <= "0101001101110100";
WHEN "1110011" => memoryC5_uid247_exp10TabGen_q <= "0101010000111001";
WHEN "1110100" => memoryC5_uid247_exp10TabGen_q <= "0101010010100101";
WHEN "1110101" => memoryC5_uid247_exp10TabGen_q <= "0101010110001010";
WHEN "1110110" => memoryC5_uid247_exp10TabGen_q <= "0101011000010010";
WHEN "1110111" => memoryC5_uid247_exp10TabGen_q <= "0101011010111100";
WHEN "1111000" => memoryC5_uid247_exp10TabGen_q <= "0101011110010101";
WHEN "1111001" => memoryC5_uid247_exp10TabGen_q <= "0101011111111010";
WHEN "1111010" => memoryC5_uid247_exp10TabGen_q <= "0101100011000011";
WHEN "1111011" => memoryC5_uid247_exp10TabGen_q <= "0101100101011100";
WHEN "1111100" => memoryC5_uid247_exp10TabGen_q <= "0101101000101110";
WHEN "1111101" => memoryC5_uid247_exp10TabGen_q <= "0101101011100111";
WHEN "1111110" => memoryC5_uid247_exp10TabGen_q <= "0101101111011111";
WHEN "1111111" => memoryC5_uid247_exp10TabGen_q <= "0101110001010100";
WHEN OTHERS =>
memoryC5_uid247_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a(DELAY,468)@13
ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => yRedPostMux_uid62_fpExpETest_q, xout => ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid65_fpExpETest(BITSELECT,64)@14
yPPolyEval_uid65_fpExpETest_in <= ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a_q(47 downto 0);
yPPolyEval_uid65_fpExpETest_b <= yPPolyEval_uid65_fpExpETest_in(47 downto 0);
--yT1_uid249_exp10PolyEval(BITSELECT,248)@14
yT1_uid249_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
yT1_uid249_exp10PolyEval_b <= yT1_uid249_exp10PolyEval_in(47 downto 32);
--reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0(REG,384)@14
reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q <= yT1_uid249_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid280_pT1_uid250_exp10PolyEval(MULT,279)@15
prodXY_uid280_pT1_uid250_exp10PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid280_pT1_uid250_exp10PolyEval_a),17)) * SIGNED(prodXY_uid280_pT1_uid250_exp10PolyEval_b);
prodXY_uid280_pT1_uid250_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_a <= (others => '0');
prodXY_uid280_pT1_uid250_exp10PolyEval_b <= (others => '0');
prodXY_uid280_pT1_uid250_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_a <= reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q;
prodXY_uid280_pT1_uid250_exp10PolyEval_b <= memoryC5_uid247_exp10TabGen_q;
prodXY_uid280_pT1_uid250_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid280_pT1_uid250_exp10PolyEval_pr,32));
END IF;
END IF;
END PROCESS;
prodXY_uid280_pT1_uid250_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_q <= prodXY_uid280_pT1_uid250_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval(BITSELECT,280)@18
prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_in <= prodXY_uid280_pT1_uid250_exp10PolyEval_q;
prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b <= prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_in(31 downto 15);
--highBBits_uid252_exp10PolyEval(BITSELECT,251)@18
highBBits_uid252_exp10PolyEval_in <= prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b;
highBBits_uid252_exp10PolyEval_b <= highBBits_uid252_exp10PolyEval_in(16 downto 1);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a(DELAY,687)@14
ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q, xout => ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid245_exp10TabGen(LOOKUP,244)@17
memoryC4_uid245_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC4_uid245_exp10TabGen_q <= "0010101010101010100110111";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a_q) IS
WHEN "0000000" => memoryC4_uid245_exp10TabGen_q <= "0010101010101010100110111";
WHEN "0000001" => memoryC4_uid245_exp10TabGen_q <= "0010101100000000100101110";
WHEN "0000010" => memoryC4_uid245_exp10TabGen_q <= "0010101101010110110010011";
WHEN "0000011" => memoryC4_uid245_exp10TabGen_q <= "0010101110101101111001001";
WHEN "0000100" => memoryC4_uid245_exp10TabGen_q <= "0010110000000101011001111";
WHEN "0000101" => memoryC4_uid245_exp10TabGen_q <= "0010110001011101101101111";
WHEN "0000110" => memoryC4_uid245_exp10TabGen_q <= "0010110010110110110100011";
WHEN "0000111" => memoryC4_uid245_exp10TabGen_q <= "0010110100010000101001111";
WHEN "0001000" => memoryC4_uid245_exp10TabGen_q <= "0010110101101011000011010";
WHEN "0001001" => memoryC4_uid245_exp10TabGen_q <= "0010110111000110010011101";
WHEN "0001010" => memoryC4_uid245_exp10TabGen_q <= "0010111000100010000011100";
WHEN "0001011" => memoryC4_uid245_exp10TabGen_q <= "0010111001111110011110010";
WHEN "0001100" => memoryC4_uid245_exp10TabGen_q <= "0010111011011100000001001";
WHEN "0001101" => memoryC4_uid245_exp10TabGen_q <= "0010111100111010011010011";
WHEN "0001110" => memoryC4_uid245_exp10TabGen_q <= "0010111110011001000101000";
WHEN "0001111" => memoryC4_uid245_exp10TabGen_q <= "0010111111111000010100011";
WHEN "0010000" => memoryC4_uid245_exp10TabGen_q <= "0011000001011001000010010";
WHEN "0010001" => memoryC4_uid245_exp10TabGen_q <= "0011000010111010001000011";
WHEN "0010010" => memoryC4_uid245_exp10TabGen_q <= "0011000100011011101101111";
WHEN "0010011" => memoryC4_uid245_exp10TabGen_q <= "0011000101111110100011110";
WHEN "0010100" => memoryC4_uid245_exp10TabGen_q <= "0011000111100001100011000";
WHEN "0010101" => memoryC4_uid245_exp10TabGen_q <= "0011001001000101111111111";
WHEN "0010110" => memoryC4_uid245_exp10TabGen_q <= "0011001010101010110100100";
WHEN "0010111" => memoryC4_uid245_exp10TabGen_q <= "0011001100010000101101011";
WHEN "0011000" => memoryC4_uid245_exp10TabGen_q <= "0011001101110110111101111";
WHEN "0011001" => memoryC4_uid245_exp10TabGen_q <= "0011001111011110010000111";
WHEN "0011010" => memoryC4_uid245_exp10TabGen_q <= "0011010001000110101010101";
WHEN "0011011" => memoryC4_uid245_exp10TabGen_q <= "0011010010101111100100001";
WHEN "0011100" => memoryC4_uid245_exp10TabGen_q <= "0011010100011001001101011";
WHEN "0011101" => memoryC4_uid245_exp10TabGen_q <= "0011010110000011110001011";
WHEN "0011110" => memoryC4_uid245_exp10TabGen_q <= "0011010111101111001100101";
WHEN "0011111" => memoryC4_uid245_exp10TabGen_q <= "0011011001011011111000011";
WHEN "0100000" => memoryC4_uid245_exp10TabGen_q <= "0011011011001000110101101";
WHEN "0100001" => memoryC4_uid245_exp10TabGen_q <= "0011011100110110110111000";
WHEN "0100010" => memoryC4_uid245_exp10TabGen_q <= "0011011110100101111111111";
WHEN "0100011" => memoryC4_uid245_exp10TabGen_q <= "0011100000010101100111000";
WHEN "0100100" => memoryC4_uid245_exp10TabGen_q <= "0011100010000101111100000";
WHEN "0100101" => memoryC4_uid245_exp10TabGen_q <= "0011100011110111110110010";
WHEN "0100110" => memoryC4_uid245_exp10TabGen_q <= "0011100101101001111011110";
WHEN "0100111" => memoryC4_uid245_exp10TabGen_q <= "0011100111011101010011110";
WHEN "0101000" => memoryC4_uid245_exp10TabGen_q <= "0011101001010001100010110";
WHEN "0101001" => memoryC4_uid245_exp10TabGen_q <= "0011101011000110101000000";
WHEN "0101010" => memoryC4_uid245_exp10TabGen_q <= "0011101100111100001111000";
WHEN "0101011" => memoryC4_uid245_exp10TabGen_q <= "0011101110110011100001000";
WHEN "0101100" => memoryC4_uid245_exp10TabGen_q <= "0011110000101011000101111";
WHEN "0101101" => memoryC4_uid245_exp10TabGen_q <= "0011110010100100001011000";
WHEN "0101110" => memoryC4_uid245_exp10TabGen_q <= "0011110100011110001001010";
WHEN "0101111" => memoryC4_uid245_exp10TabGen_q <= "0011110110011000011111110";
WHEN "0110000" => memoryC4_uid245_exp10TabGen_q <= "0011111000010100001101010";
WHEN "0110001" => memoryC4_uid245_exp10TabGen_q <= "0011111010010000110001010";
WHEN "0110010" => memoryC4_uid245_exp10TabGen_q <= "0011111100001110011011010";
WHEN "0110011" => memoryC4_uid245_exp10TabGen_q <= "0011111110001100111101101";
WHEN "0110100" => memoryC4_uid245_exp10TabGen_q <= "0100000000001100101011001";
WHEN "0110101" => memoryC4_uid245_exp10TabGen_q <= "0100000010001101100001011";
WHEN "0110110" => memoryC4_uid245_exp10TabGen_q <= "0100000100001110111000001";
WHEN "0110111" => memoryC4_uid245_exp10TabGen_q <= "0100000110010001011001101";
WHEN "0111000" => memoryC4_uid245_exp10TabGen_q <= "0100001000010101001110001";
WHEN "0111001" => memoryC4_uid245_exp10TabGen_q <= "0100001010011001110101000";
WHEN "0111010" => memoryC4_uid245_exp10TabGen_q <= "0100001100011111101101100";
WHEN "0111011" => memoryC4_uid245_exp10TabGen_q <= "0100001110100110100010011";
WHEN "0111100" => memoryC4_uid245_exp10TabGen_q <= "0100010000101110011010110";
WHEN "0111101" => memoryC4_uid245_exp10TabGen_q <= "0100010010110111001010011";
WHEN "0111110" => memoryC4_uid245_exp10TabGen_q <= "0100010101000001010010000";
WHEN "0111111" => memoryC4_uid245_exp10TabGen_q <= "0100010111001011111100111";
WHEN "1000000" => memoryC4_uid245_exp10TabGen_q <= "0100011001011000000110010";
WHEN "1000001" => memoryC4_uid245_exp10TabGen_q <= "0100011011100101101010011";
WHEN "1000010" => memoryC4_uid245_exp10TabGen_q <= "0100011101110100001011000";
WHEN "1000011" => memoryC4_uid245_exp10TabGen_q <= "0100100000000011010000011";
WHEN "1000100" => memoryC4_uid245_exp10TabGen_q <= "0100100010010011111101000";
WHEN "1000101" => memoryC4_uid245_exp10TabGen_q <= "0100100100100101110001011";
WHEN "1000110" => memoryC4_uid245_exp10TabGen_q <= "0100100110111000010110111";
WHEN "1000111" => memoryC4_uid245_exp10TabGen_q <= "0100101001001100101100000";
WHEN "1001000" => memoryC4_uid245_exp10TabGen_q <= "0100101011100001101000110";
WHEN "1001001" => memoryC4_uid245_exp10TabGen_q <= "0100101101111000000100100";
WHEN "1001010" => memoryC4_uid245_exp10TabGen_q <= "0100110000001111100110101";
WHEN "1001011" => memoryC4_uid245_exp10TabGen_q <= "0100110010101000100001110";
WHEN "1001100" => memoryC4_uid245_exp10TabGen_q <= "0100110101000010011011010";
WHEN "1001101" => memoryC4_uid245_exp10TabGen_q <= "0100110111011101100001110";
WHEN "1001110" => memoryC4_uid245_exp10TabGen_q <= "0100111001111001101111111";
WHEN "1001111" => memoryC4_uid245_exp10TabGen_q <= "0100111100010111010001010";
WHEN "1010000" => memoryC4_uid245_exp10TabGen_q <= "0100111110110110001011011";
WHEN "1010001" => memoryC4_uid245_exp10TabGen_q <= "0101000001010110000111110";
WHEN "1010010" => memoryC4_uid245_exp10TabGen_q <= "0101000011110111101000110";
WHEN "1010011" => memoryC4_uid245_exp10TabGen_q <= "0101000110011010000111110";
WHEN "1010100" => memoryC4_uid245_exp10TabGen_q <= "0101001000111101111101011";
WHEN "1010101" => memoryC4_uid245_exp10TabGen_q <= "0101001011100010110100011";
WHEN "1010110" => memoryC4_uid245_exp10TabGen_q <= "0101001110001001010100001";
WHEN "1010111" => memoryC4_uid245_exp10TabGen_q <= "0101010000110001010011000";
WHEN "1011000" => memoryC4_uid245_exp10TabGen_q <= "0101010011011010010000001";
WHEN "1011001" => memoryC4_uid245_exp10TabGen_q <= "0101010110000100101000010";
WHEN "1011010" => memoryC4_uid245_exp10TabGen_q <= "0101011000110000000100011";
WHEN "1011011" => memoryC4_uid245_exp10TabGen_q <= "0101011011011100111110111";
WHEN "1011100" => memoryC4_uid245_exp10TabGen_q <= "0101011110001011111000111";
WHEN "1011101" => memoryC4_uid245_exp10TabGen_q <= "0101100000111011101001000";
WHEN "1011110" => memoryC4_uid245_exp10TabGen_q <= "0101100011101100011101001";
WHEN "1011111" => memoryC4_uid245_exp10TabGen_q <= "0101100110011111000100111";
WHEN "1100000" => memoryC4_uid245_exp10TabGen_q <= "0101101001010011001001110";
WHEN "1100001" => memoryC4_uid245_exp10TabGen_q <= "0101101100001000011001111";
WHEN "1100010" => memoryC4_uid245_exp10TabGen_q <= "0101101110111111000101011";
WHEN "1100011" => memoryC4_uid245_exp10TabGen_q <= "0101110001110111100010111";
WHEN "1100100" => memoryC4_uid245_exp10TabGen_q <= "0101110100110001000110101";
WHEN "1100101" => memoryC4_uid245_exp10TabGen_q <= "0101110111101100000011000";
WHEN "1100110" => memoryC4_uid245_exp10TabGen_q <= "0101111010101000101010001";
WHEN "1100111" => memoryC4_uid245_exp10TabGen_q <= "0101111101100110101011001";
WHEN "1101000" => memoryC4_uid245_exp10TabGen_q <= "0110000000100110011100100";
WHEN "1101001" => memoryC4_uid245_exp10TabGen_q <= "0110000011100111100001001";
WHEN "1101010" => memoryC4_uid245_exp10TabGen_q <= "0110000110101001110010101";
WHEN "1101011" => memoryC4_uid245_exp10TabGen_q <= "0110001001101110010010001";
WHEN "1101100" => memoryC4_uid245_exp10TabGen_q <= "0110001100110011111111000";
WHEN "1101101" => memoryC4_uid245_exp10TabGen_q <= "0110001111111010111100010";
WHEN "1101110" => memoryC4_uid245_exp10TabGen_q <= "0110010011000011100101011";
WHEN "1101111" => memoryC4_uid245_exp10TabGen_q <= "0110010110001110001010101";
WHEN "1110000" => memoryC4_uid245_exp10TabGen_q <= "0110011001011010000010001";
WHEN "1110001" => memoryC4_uid245_exp10TabGen_q <= "0110011100100111100001011";
WHEN "1110010" => memoryC4_uid245_exp10TabGen_q <= "0110011111110110101000110";
WHEN "1110011" => memoryC4_uid245_exp10TabGen_q <= "0110100011000111001100001";
WHEN "1110100" => memoryC4_uid245_exp10TabGen_q <= "0110100110011001111010000";
WHEN "1110101" => memoryC4_uid245_exp10TabGen_q <= "0110101001101101101000011";
WHEN "1110110" => memoryC4_uid245_exp10TabGen_q <= "0110101101000011011111100";
WHEN "1110111" => memoryC4_uid245_exp10TabGen_q <= "0110110000011010111001111";
WHEN "1111000" => memoryC4_uid245_exp10TabGen_q <= "0110110011110011101100100";
WHEN "1111001" => memoryC4_uid245_exp10TabGen_q <= "0110110111001110110110100";
WHEN "1111010" => memoryC4_uid245_exp10TabGen_q <= "0110111010101011001101011";
WHEN "1111011" => memoryC4_uid245_exp10TabGen_q <= "0110111110001001100010010";
WHEN "1111100" => memoryC4_uid245_exp10TabGen_q <= "0111000001101001010101001";
WHEN "1111101" => memoryC4_uid245_exp10TabGen_q <= "0111000101001011000010001";
WHEN "1111110" => memoryC4_uid245_exp10TabGen_q <= "0111001000101110001001100";
WHEN "1111111" => memoryC4_uid245_exp10TabGen_q <= "0111001100010011101111011";
WHEN OTHERS =>
memoryC4_uid245_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid253_exp10PolyEval(ADD,252)@18
sumAHighB_uid253_exp10PolyEval_a <= STD_LOGIC_VECTOR((25 downto 25 => memoryC4_uid245_exp10TabGen_q(24)) & memoryC4_uid245_exp10TabGen_q);
sumAHighB_uid253_exp10PolyEval_b <= STD_LOGIC_VECTOR((25 downto 16 => highBBits_uid252_exp10PolyEval_b(15)) & highBBits_uid252_exp10PolyEval_b);
sumAHighB_uid253_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid253_exp10PolyEval_a) + SIGNED(sumAHighB_uid253_exp10PolyEval_b));
sumAHighB_uid253_exp10PolyEval_q <= sumAHighB_uid253_exp10PolyEval_o(25 downto 0);
--lowRangeB_uid251_exp10PolyEval(BITSELECT,250)@18
lowRangeB_uid251_exp10PolyEval_in <= prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b(0 downto 0);
lowRangeB_uid251_exp10PolyEval_b <= lowRangeB_uid251_exp10PolyEval_in(0 downto 0);
--s1_uid251_uid254_exp10PolyEval(BITJOIN,253)@18
s1_uid251_uid254_exp10PolyEval_q <= sumAHighB_uid253_exp10PolyEval_q & lowRangeB_uid251_exp10PolyEval_b;
--reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1(REG,387)@18
reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q <= s1_uid251_uid254_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor(LOGICAL,1157)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_b <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_q <= not (ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_a or ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_b);
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg(REG,1155)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena(REG,1158)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd(LOGICAL,1159)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_a <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_a and ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_b;
--yT2_uid255_exp10PolyEval(BITSELECT,254)@14
yT2_uid255_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
yT2_uid255_exp10PolyEval_b <= yT2_uid255_exp10PolyEval_in(47 downto 23);
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg(DELAY,1149)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => yT2_uid255_exp10PolyEval_b, xout => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt(COUNTER,1151)
-- every=1, low=0, high=1, step=1, init=1
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i,1));
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg(REG,1152)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux(MUX,1153)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s, ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q, ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem(DUALMEM,1150)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ia <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_aa <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ab <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 25,
widthad_a => 1,
numwords_a => 2,
width_b => 25,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_iq(24 downto 0);
--reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0(REG,386)@18
reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid283_pT2_uid256_exp10PolyEval(MULT,282)@19
prodXY_uid283_pT2_uid256_exp10PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid283_pT2_uid256_exp10PolyEval_a),26)) * SIGNED(prodXY_uid283_pT2_uid256_exp10PolyEval_b);
prodXY_uid283_pT2_uid256_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_a <= (others => '0');
prodXY_uid283_pT2_uid256_exp10PolyEval_b <= (others => '0');
prodXY_uid283_pT2_uid256_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_a <= reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q;
prodXY_uid283_pT2_uid256_exp10PolyEval_b <= reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q;
prodXY_uid283_pT2_uid256_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid283_pT2_uid256_exp10PolyEval_pr,52));
END IF;
END IF;
END PROCESS;
prodXY_uid283_pT2_uid256_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_q <= prodXY_uid283_pT2_uid256_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval(BITSELECT,283)@22
prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_in <= prodXY_uid283_pT2_uid256_exp10PolyEval_q;
prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b <= prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_in(51 downto 24);
--highBBits_uid258_exp10PolyEval(BITSELECT,257)@22
highBBits_uid258_exp10PolyEval_in <= prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b;
highBBits_uid258_exp10PolyEval_b <= highBBits_uid258_exp10PolyEval_in(27 downto 1);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor(LOGICAL,1055)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_b <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_q <= not (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_a or ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top(CONSTANT,1051)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top_q <= "0100";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp(LOGICAL,1052)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_q <= "1" when ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_a = ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_b else "0";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg(REG,1053)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena(REG,1056)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd(LOGICAL,1057)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_a and ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_b;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg(DELAY,1006)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q, xout => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt(COUNTER,1047)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i = 3 THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i - 4;
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg(REG,1048)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux(MUX,1049)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s, ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q, ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem(DUALMEM,1046)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ia <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ia
);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_iq(6 downto 0);
--memoryC3_uid243_exp10TabGen(LOOKUP,242)@21
memoryC3_uid243_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC3_uid243_exp10TabGen_q <= "00101010101010101010101010101101111";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_q) IS
WHEN "0000000" => memoryC3_uid243_exp10TabGen_q <= "00101010101010101010101010101101111";
WHEN "0000001" => memoryC3_uid243_exp10TabGen_q <= "00101011000000000101010101101011011";
WHEN "0000010" => memoryC3_uid243_exp10TabGen_q <= "00101011010101101010110001100001111";
WHEN "0000011" => memoryC3_uid243_exp10TabGen_q <= "00101011101011011011000010011000001";
WHEN "0000100" => memoryC3_uid243_exp10TabGen_q <= "00101100000001010110001110100011110";
WHEN "0000101" => memoryC3_uid243_exp10TabGen_q <= "00101100010111011100011010111011100";
WHEN "0000110" => memoryC3_uid243_exp10TabGen_q <= "00101100101101101101101100111110101";
WHEN "0000111" => memoryC3_uid243_exp10TabGen_q <= "00101101000100001010001010010011010";
WHEN "0001000" => memoryC3_uid243_exp10TabGen_q <= "00101101011010110001111001000001100";
WHEN "0001001" => memoryC3_uid243_exp10TabGen_q <= "00101101110001100100111110001011000";
WHEN "0001010" => memoryC3_uid243_exp10TabGen_q <= "00101110001000100011100000000110101";
WHEN "0001011" => memoryC3_uid243_exp10TabGen_q <= "00101110011111101101100100010001111";
WHEN "0001100" => memoryC3_uid243_exp10TabGen_q <= "00101110110111000011001111101001101";
WHEN "0001101" => memoryC3_uid243_exp10TabGen_q <= "00101111001110100100101000011111000";
WHEN "0001110" => memoryC3_uid243_exp10TabGen_q <= "00101111100110010001110101111100101";
WHEN "0001111" => memoryC3_uid243_exp10TabGen_q <= "00101111111110001010111101010010000";
WHEN "0010000" => memoryC3_uid243_exp10TabGen_q <= "00110000010110010000000010110000111";
WHEN "0010001" => memoryC3_uid243_exp10TabGen_q <= "00110000101110100001001110011111001";
WHEN "0010010" => memoryC3_uid243_exp10TabGen_q <= "00110001000110111110100110100000011";
WHEN "0010011" => memoryC3_uid243_exp10TabGen_q <= "00110001011111101000001111001011001";
WHEN "0010100" => memoryC3_uid243_exp10TabGen_q <= "00110001111000011110010001000100010";
WHEN "0010101" => memoryC3_uid243_exp10TabGen_q <= "00110010010001100000101111101110000";
WHEN "0010110" => memoryC3_uid243_exp10TabGen_q <= "00110010101010101111110011100001100";
WHEN "0010111" => memoryC3_uid243_exp10TabGen_q <= "00110011000100001011100001100001111";
WHEN "0011000" => memoryC3_uid243_exp10TabGen_q <= "00110011011101110100000001011100101";
WHEN "0011001" => memoryC3_uid243_exp10TabGen_q <= "00110011110111101001011000010101000";
WHEN "0011010" => memoryC3_uid243_exp10TabGen_q <= "00110100010001101011101100100010010";
WHEN "0011011" => memoryC3_uid243_exp10TabGen_q <= "00110100101011111011000101110001111";
WHEN "0011100" => memoryC3_uid243_exp10TabGen_q <= "00110101000110010111101010001110011";
WHEN "0011101" => memoryC3_uid243_exp10TabGen_q <= "00110101100001000001100000000100001";
WHEN "0011110" => memoryC3_uid243_exp10TabGen_q <= "00110101111011111000101110000101010";
WHEN "0011111" => memoryC3_uid243_exp10TabGen_q <= "00110110010110111101011010010100110";
WHEN "0100000" => memoryC3_uid243_exp10TabGen_q <= "00110110110010001111101101011010010";
WHEN "0100001" => memoryC3_uid243_exp10TabGen_q <= "00110111001101101111101100101000101";
WHEN "0100010" => memoryC3_uid243_exp10TabGen_q <= "00110111101001011101011110110010101";
WHEN "0100011" => memoryC3_uid243_exp10TabGen_q <= "00111000000101011001001100000100111";
WHEN "0100100" => memoryC3_uid243_exp10TabGen_q <= "00111000100001100010111011000111001";
WHEN "0100101" => memoryC3_uid243_exp10TabGen_q <= "00111000111101111010110001000111010";
WHEN "0100110" => memoryC3_uid243_exp10TabGen_q <= "00111001011010100000111000000010011";
WHEN "0100111" => memoryC3_uid243_exp10TabGen_q <= "00111001110111010101010100101101100";
WHEN "0101000" => memoryC3_uid243_exp10TabGen_q <= "00111010010100011000001111011100111";
WHEN "0101001" => memoryC3_uid243_exp10TabGen_q <= "00111010110001101001101111010100011";
WHEN "0101010" => memoryC3_uid243_exp10TabGen_q <= "00111011001111001001111100011010010";
WHEN "0101011" => memoryC3_uid243_exp10TabGen_q <= "00111011101100111000111011110110001";
WHEN "0101100" => memoryC3_uid243_exp10TabGen_q <= "00111100001010110110110111110001010";
WHEN "0101101" => memoryC3_uid243_exp10TabGen_q <= "00111100101001000011110101010010101";
WHEN "0101110" => memoryC3_uid243_exp10TabGen_q <= "00111101000111011111111101001100100";
WHEN "0101111" => memoryC3_uid243_exp10TabGen_q <= "00111101100110001011011000000101100";
WHEN "0110000" => memoryC3_uid243_exp10TabGen_q <= "00111110000101000110001011101110111";
WHEN "0110001" => memoryC3_uid243_exp10TabGen_q <= "00111110100100010000100000111101010";
WHEN "0110010" => memoryC3_uid243_exp10TabGen_q <= "00111111000011101010011110111011001";
WHEN "0110011" => memoryC3_uid243_exp10TabGen_q <= "00111111100011010100001110000110011";
WHEN "0110100" => memoryC3_uid243_exp10TabGen_q <= "01000000000011001101110101110010101";
WHEN "0110101" => memoryC3_uid243_exp10TabGen_q <= "01000000100011010111011101111010000";
WHEN "0110110" => memoryC3_uid243_exp10TabGen_q <= "01000001000011110001001111111000011";
WHEN "0110111" => memoryC3_uid243_exp10TabGen_q <= "01000001100100011011010010100100000";
WHEN "0111000" => memoryC3_uid243_exp10TabGen_q <= "01000010000101010101101101110001001";
WHEN "0111001" => memoryC3_uid243_exp10TabGen_q <= "01000010100110100000101010111010001";
WHEN "0111010" => memoryC3_uid243_exp10TabGen_q <= "01000011000111111100010001000011010";
WHEN "0111011" => memoryC3_uid243_exp10TabGen_q <= "01000011101001101000101001100001011";
WHEN "0111100" => memoryC3_uid243_exp10TabGen_q <= "01000100001011100101111100010101100";
WHEN "0111101" => memoryC3_uid243_exp10TabGen_q <= "01000100101101110100010010011111111";
WHEN "0111110" => memoryC3_uid243_exp10TabGen_q <= "01000101010000010011110011011101011";
WHEN "0111111" => memoryC3_uid243_exp10TabGen_q <= "01000101110011000100101001100111101";
WHEN "1000000" => memoryC3_uid243_exp10TabGen_q <= "01000110010110000110111011110001110";
WHEN "1000001" => memoryC3_uid243_exp10TabGen_q <= "01000110111001011010110010110111001";
WHEN "1000010" => memoryC3_uid243_exp10TabGen_q <= "01000111011101000000011000100111110";
WHEN "1000011" => memoryC3_uid243_exp10TabGen_q <= "01001000000000110111110110101011010";
WHEN "1000100" => memoryC3_uid243_exp10TabGen_q <= "01001000100101000001010100000000111";
WHEN "1000101" => memoryC3_uid243_exp10TabGen_q <= "01001001001001011100111010100011101";
WHEN "1000110" => memoryC3_uid243_exp10TabGen_q <= "01001001101110001010110100010011010";
WHEN "1000111" => memoryC3_uid243_exp10TabGen_q <= "01001010010011001011001000011100000";
WHEN "1001000" => memoryC3_uid243_exp10TabGen_q <= "01001010111000011110000010011000010";
WHEN "1001001" => memoryC3_uid243_exp10TabGen_q <= "01001011011110000011101001110110000";
WHEN "1001010" => memoryC3_uid243_exp10TabGen_q <= "01001100000011111100001000111111000";
WHEN "1001011" => memoryC3_uid243_exp10TabGen_q <= "01001100101010000111101000110011011";
WHEN "1001100" => memoryC3_uid243_exp10TabGen_q <= "01001101010000100110010011100000101";
WHEN "1001101" => memoryC3_uid243_exp10TabGen_q <= "01001101110111011000010010010110010";
WHEN "1001110" => memoryC3_uid243_exp10TabGen_q <= "01001110011110011101101111010011000";
WHEN "1001111" => memoryC3_uid243_exp10TabGen_q <= "01001111000101110110110011101100000";
WHEN "1010000" => memoryC3_uid243_exp10TabGen_q <= "01001111101101100011101001010010100";
WHEN "1010001" => memoryC3_uid243_exp10TabGen_q <= "01010000010101100100011010101011011";
WHEN "1010010" => memoryC3_uid243_exp10TabGen_q <= "01010000111101111001010000110011110";
WHEN "1010011" => memoryC3_uid243_exp10TabGen_q <= "01010001100110100010010111000101101";
WHEN "1010100" => memoryC3_uid243_exp10TabGen_q <= "01010010001111011111110110110000001";
WHEN "1010101" => memoryC3_uid243_exp10TabGen_q <= "01010010111000110001111010111010000";
WHEN "1010110" => memoryC3_uid243_exp10TabGen_q <= "01010011100010011000101100100001011";
WHEN "1010111" => memoryC3_uid243_exp10TabGen_q <= "01010100001100010100010110011000000";
WHEN "1011000" => memoryC3_uid243_exp10TabGen_q <= "01010100110110100101000100000100011";
WHEN "1011001" => memoryC3_uid243_exp10TabGen_q <= "01010101100001001010111111000111101";
WHEN "1011010" => memoryC3_uid243_exp10TabGen_q <= "01010110001100000110010011000111011";
WHEN "1011011" => memoryC3_uid243_exp10TabGen_q <= "01010110110111010111001001110100000";
WHEN "1011100" => memoryC3_uid243_exp10TabGen_q <= "01010111100010111101101101001011111";
WHEN "1011101" => memoryC3_uid243_exp10TabGen_q <= "01011000001110111010001010001111101";
WHEN "1011110" => memoryC3_uid243_exp10TabGen_q <= "01011000111011001100101011110000010";
WHEN "1011111" => memoryC3_uid243_exp10TabGen_q <= "01011001100111110101011011001001100";
WHEN "1100000" => memoryC3_uid243_exp10TabGen_q <= "01011010010100110100100100011100111";
WHEN "1100001" => memoryC3_uid243_exp10TabGen_q <= "01011011000010001010010011100000000";
WHEN "1100010" => memoryC3_uid243_exp10TabGen_q <= "01011011101111110110110010111100110";
WHEN "1100011" => memoryC3_uid243_exp10TabGen_q <= "01011100011101111010001101110001000";
WHEN "1100100" => memoryC3_uid243_exp10TabGen_q <= "01011101001100010100110000101110011";
WHEN "1100101" => memoryC3_uid243_exp10TabGen_q <= "01011101111011000110100110111100011";
WHEN "1100110" => memoryC3_uid243_exp10TabGen_q <= "01011110101010001111111011100011011";
WHEN "1100111" => memoryC3_uid243_exp10TabGen_q <= "01011111011001110000111010111000000";
WHEN "1101000" => memoryC3_uid243_exp10TabGen_q <= "01100000001001101001110000000101000";
WHEN "1101001" => memoryC3_uid243_exp10TabGen_q <= "01100000111001111010101000001000101";
WHEN "1101010" => memoryC3_uid243_exp10TabGen_q <= "01100001101010100011101111010001110";
WHEN "1101011" => memoryC3_uid243_exp10TabGen_q <= "01100010011011100101001111110000101";
WHEN "1101100" => memoryC3_uid243_exp10TabGen_q <= "01100011001100111111010111101111110";
WHEN "1101101" => memoryC3_uid243_exp10TabGen_q <= "01100011111110110010010011100110010";
WHEN "1101110" => memoryC3_uid243_exp10TabGen_q <= "01100100110000111110001110110101100";
WHEN "1101111" => memoryC3_uid243_exp10TabGen_q <= "01100101100011100011010101101101001";
WHEN "1110000" => memoryC3_uid243_exp10TabGen_q <= "01100110010110100001110101111100110";
WHEN "1110001" => memoryC3_uid243_exp10TabGen_q <= "01100111001001111001111011111001101";
WHEN "1110010" => memoryC3_uid243_exp10TabGen_q <= "01100111111101101011110100001100011";
WHEN "1110011" => memoryC3_uid243_exp10TabGen_q <= "01101000110001110111101100011010111";
WHEN "1110100" => memoryC3_uid243_exp10TabGen_q <= "01101001100110011101101111111111000";
WHEN "1110101" => memoryC3_uid243_exp10TabGen_q <= "01101010011011011110001110011101010";
WHEN "1110110" => memoryC3_uid243_exp10TabGen_q <= "01101011010000111001010010111011001";
WHEN "1110111" => memoryC3_uid243_exp10TabGen_q <= "01101100000110101111001011110001101";
WHEN "1111000" => memoryC3_uid243_exp10TabGen_q <= "01101100111101000000000111000100011";
WHEN "1111001" => memoryC3_uid243_exp10TabGen_q <= "01101101110011101100010000001110111";
WHEN "1111010" => memoryC3_uid243_exp10TabGen_q <= "01101110101010110011110111010100111";
WHEN "1111011" => memoryC3_uid243_exp10TabGen_q <= "01101111100010010111001000101100111";
WHEN "1111100" => memoryC3_uid243_exp10TabGen_q <= "01110000011010010110010011001011011";
WHEN "1111101" => memoryC3_uid243_exp10TabGen_q <= "01110001010010110001100011111011011";
WHEN "1111110" => memoryC3_uid243_exp10TabGen_q <= "01110010001011101001001010001001100";
WHEN "1111111" => memoryC3_uid243_exp10TabGen_q <= "01110011000100111101010001111100100";
WHEN OTHERS =>
memoryC3_uid243_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_exp10PolyEval(ADD,258)@22
sumAHighB_uid259_exp10PolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid243_exp10TabGen_q(34)) & memoryC3_uid243_exp10TabGen_q);
sumAHighB_uid259_exp10PolyEval_b <= STD_LOGIC_VECTOR((35 downto 27 => highBBits_uid258_exp10PolyEval_b(26)) & highBBits_uid258_exp10PolyEval_b);
sumAHighB_uid259_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_exp10PolyEval_a) + SIGNED(sumAHighB_uid259_exp10PolyEval_b));
sumAHighB_uid259_exp10PolyEval_q <= sumAHighB_uid259_exp10PolyEval_o(35 downto 0);
--lowRangeB_uid257_exp10PolyEval(BITSELECT,256)@22
lowRangeB_uid257_exp10PolyEval_in <= prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b(0 downto 0);
lowRangeB_uid257_exp10PolyEval_b <= lowRangeB_uid257_exp10PolyEval_in(0 downto 0);
--s2_uid257_uid260_exp10PolyEval(BITJOIN,259)@22
s2_uid257_uid260_exp10PolyEval_q <= sumAHighB_uid259_exp10PolyEval_q & lowRangeB_uid257_exp10PolyEval_b;
--yTop18Bits_uid292_pT3_uid262_exp10PolyEval(BITSELECT,291)@22
yTop18Bits_uid292_pT3_uid262_exp10PolyEval_in <= s2_uid257_uid260_exp10PolyEval_q;
yTop18Bits_uid292_pT3_uid262_exp10PolyEval_b <= yTop18Bits_uid292_pT3_uid262_exp10PolyEval_in(36 downto 19);
--reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9(REG,392)@22
reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q <= yTop18Bits_uid292_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor(LOGICAL,1068)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_b <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_q <= not (ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_a or ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_b);
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena(REG,1069)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd(LOGICAL,1070)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_a and ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg(DELAY,1058)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid65_fpExpETest_b, xout => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem(DUALMEM,1059)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_aa <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ab <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 3,
numwords_a => 6,
width_b => 48,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_iq(47 downto 0);
--yT3_uid261_exp10PolyEval(BITSELECT,260)@22
yT3_uid261_exp10PolyEval_in <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_q;
yT3_uid261_exp10PolyEval_b <= yT3_uid261_exp10PolyEval_in(47 downto 13);
--xBottomBits_uid291_pT3_uid262_exp10PolyEval(BITSELECT,290)@22
xBottomBits_uid291_pT3_uid262_exp10PolyEval_in <= yT3_uid261_exp10PolyEval_b(7 downto 0);
xBottomBits_uid291_pT3_uid262_exp10PolyEval_b <= xBottomBits_uid291_pT3_uid262_exp10PolyEval_in(7 downto 0);
--pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval(BITJOIN,293)@22
pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_q <= xBottomBits_uid291_pT3_uid262_exp10PolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7(REG,391)@22
reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q <= pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid290_pT3_uid262_exp10PolyEval(BITSELECT,289)@22
yBottomBits_uid290_pT3_uid262_exp10PolyEval_in <= s2_uid257_uid260_exp10PolyEval_q(9 downto 0);
yBottomBits_uid290_pT3_uid262_exp10PolyEval_b <= yBottomBits_uid290_pT3_uid262_exp10PolyEval_in(9 downto 0);
--spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval(BITJOIN,292)@22
spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval_q <= GND_q & yBottomBits_uid290_pT3_uid262_exp10PolyEval_b;
--pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval(BITJOIN,294)@22
pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_q <= spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6(REG,390)@22
reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q <= pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid289_pT3_uid262_exp10PolyEval(BITSELECT,288)@22
xTop18Bits_uid289_pT3_uid262_exp10PolyEval_in <= yT3_uid261_exp10PolyEval_b;
xTop18Bits_uid289_pT3_uid262_exp10PolyEval_b <= xTop18Bits_uid289_pT3_uid262_exp10PolyEval_in(34 downto 17);
--reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4(REG,389)@22
reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q <= xTop18Bits_uid289_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma(CHAINMULTADD,338)@23
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(0),19));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(1),19));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(0) * multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(0);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(1) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(1) * multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(1);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(1),38);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w(0);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x(0);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q),18);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q),18);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q),18);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval(BITSELECT,296)@26
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_in <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_q;
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_in(36 downto 7);
--highBBits_uid299_pT3_uid262_exp10PolyEval(BITSELECT,298)@26
highBBits_uid299_pT3_uid262_exp10PolyEval_in <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b;
highBBits_uid299_pT3_uid262_exp10PolyEval_b <= highBBits_uid299_pT3_uid262_exp10PolyEval_in(29 downto 1);
--yTop27Bits_uid287_pT3_uid262_exp10PolyEval(BITSELECT,286)@22
yTop27Bits_uid287_pT3_uid262_exp10PolyEval_in <= s2_uid257_uid260_exp10PolyEval_q;
yTop27Bits_uid287_pT3_uid262_exp10PolyEval_b <= yTop27Bits_uid287_pT3_uid262_exp10PolyEval_in(36 downto 10);
--reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1(REG,394)@22
reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q <= yTop27Bits_uid287_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid286_pT3_uid262_exp10PolyEval(BITSELECT,285)@22
xTop27Bits_uid286_pT3_uid262_exp10PolyEval_in <= yT3_uid261_exp10PolyEval_b;
xTop27Bits_uid286_pT3_uid262_exp10PolyEval_b <= xTop27Bits_uid286_pT3_uid262_exp10PolyEval_in(34 downto 8);
--reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0(REG,393)@22
reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q <= xTop27Bits_uid286_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid288_pT3_uid262_exp10PolyEval(MULT,287)@23
topProd_uid288_pT3_uid262_exp10PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT3_uid262_exp10PolyEval_a),28)) * SIGNED(topProd_uid288_pT3_uid262_exp10PolyEval_b);
topProd_uid288_pT3_uid262_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid288_pT3_uid262_exp10PolyEval_a <= (others => '0');
topProd_uid288_pT3_uid262_exp10PolyEval_b <= (others => '0');
topProd_uid288_pT3_uid262_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid288_pT3_uid262_exp10PolyEval_a <= reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q;
topProd_uid288_pT3_uid262_exp10PolyEval_b <= reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q;
topProd_uid288_pT3_uid262_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT3_uid262_exp10PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid288_pT3_uid262_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid288_pT3_uid262_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid288_pT3_uid262_exp10PolyEval_q <= topProd_uid288_pT3_uid262_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid300_pT3_uid262_exp10PolyEval(ADD,299)@26
sumAHighB_uid300_pT3_uid262_exp10PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid288_pT3_uid262_exp10PolyEval_q(53)) & topProd_uid288_pT3_uid262_exp10PolyEval_q);
sumAHighB_uid300_pT3_uid262_exp10PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid299_pT3_uid262_exp10PolyEval_b(28)) & highBBits_uid299_pT3_uid262_exp10PolyEval_b);
sumAHighB_uid300_pT3_uid262_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid300_pT3_uid262_exp10PolyEval_a) + SIGNED(sumAHighB_uid300_pT3_uid262_exp10PolyEval_b));
sumAHighB_uid300_pT3_uid262_exp10PolyEval_q <= sumAHighB_uid300_pT3_uid262_exp10PolyEval_o(54 downto 0);
--lowRangeB_uid298_pT3_uid262_exp10PolyEval(BITSELECT,297)@26
lowRangeB_uid298_pT3_uid262_exp10PolyEval_in <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b(0 downto 0);
lowRangeB_uid298_pT3_uid262_exp10PolyEval_b <= lowRangeB_uid298_pT3_uid262_exp10PolyEval_in(0 downto 0);
--add0_uid298_uid301_pT3_uid262_exp10PolyEval(BITJOIN,300)@26
add0_uid298_uid301_pT3_uid262_exp10PolyEval_q <= sumAHighB_uid300_pT3_uid262_exp10PolyEval_q & lowRangeB_uid298_pT3_uid262_exp10PolyEval_b;
--R_uid302_pT3_uid262_exp10PolyEval(BITSELECT,301)@26
R_uid302_pT3_uid262_exp10PolyEval_in <= add0_uid298_uid301_pT3_uid262_exp10PolyEval_q(54 downto 0);
R_uid302_pT3_uid262_exp10PolyEval_b <= R_uid302_pT3_uid262_exp10PolyEval_in(54 downto 18);
--reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1(REG,396)@26
reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q <= R_uid302_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor(LOGICAL,1042)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_b <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_q <= not (ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_a or ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top(CONSTANT,1025)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top_q <= "01000";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp(LOGICAL,1026)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_q <= "1" when ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_a = ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_b else "0";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg(REG,1027)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena(REG,1043)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_q = "1") THEN
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd(LOGICAL,1044)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_a <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_b <= en;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_q <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_a and ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_b;
--memoryC2_uid241_exp10TabGen(LOOKUP,240)@14
memoryC2_uid241_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid241_exp10TabGen_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC2_uid241_exp10TabGen_q <= "000";
WHEN "0000001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1011000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1011001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN OTHERS =>
memoryC2_uid241_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg(DELAY,1032)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid241_exp10TabGen_q, xout => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt(COUNTER,1021)
-- every=1, low=0, high=8, step=1, init=1
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i = 7 THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i - 8;
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg(REG,1022)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux(MUX,1023)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s, ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q, ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem(DUALMEM,1033)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ia <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 9,
width_b => 3,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_iq,
address_a => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_aa,
data_a => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ia
);
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_reset0 <= areset;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_q <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_iq(2 downto 0);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor(LOGICAL,1029)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_b <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_q <= not (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_a or ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena(REG,1030)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd(LOGICAL,1031)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_a and ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_b;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem(DUALMEM,1020)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ia <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 4,
numwords_a => 9,
width_b => 7,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ia
);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_iq(6 downto 0);
--memoryC2_uid240_exp10TabGen(LOOKUP,239)@25
memoryC2_uid240_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid240_exp10TabGen_q <= "1111111111111111111111111111111111111110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_q) IS
WHEN "0000000" => memoryC2_uid240_exp10TabGen_q <= "1111111111111111111111111111111111111110";
WHEN "0000001" => memoryC2_uid240_exp10TabGen_q <= "0000001000000010000000010101011000111101";
WHEN "0000010" => memoryC2_uid240_exp10TabGen_q <= "0000010000001000000010101011010101111110";
WHEN "0000011" => memoryC2_uid240_exp10TabGen_q <= "0000011000010010001001000011011001110000";
WHEN "0000100" => memoryC2_uid240_exp10TabGen_q <= "0000100000100000010101100000000100100100";
WHEN "0000101" => memoryC2_uid240_exp10TabGen_q <= "0000101000110010101010000100111010011000";
WHEN "0000110" => memoryC2_uid240_exp10TabGen_q <= "0000110001001001001000110110100000100101";
WHEN "0000111" => memoryC2_uid240_exp10TabGen_q <= "0000111001100011110011111010011111000001";
WHEN "0001000" => memoryC2_uid240_exp10TabGen_q <= "0001000010000010101101010111011111010100";
WHEN "0001001" => memoryC2_uid240_exp10TabGen_q <= "0001001010100101110111010101010001000100";
WHEN "0001010" => memoryC2_uid240_exp10TabGen_q <= "0001010011001101010011111100100101110011";
WHEN "0001011" => memoryC2_uid240_exp10TabGen_q <= "0001011011111001000101010111010101000111";
WHEN "0001100" => memoryC2_uid240_exp10TabGen_q <= "0001100100101001001101110000011100110000";
WHEN "0001101" => memoryC2_uid240_exp10TabGen_q <= "0001101101011101101111010011111110010110";
WHEN "0001110" => memoryC2_uid240_exp10TabGen_q <= "0001110110010110101100001110111111110111";
WHEN "0001111" => memoryC2_uid240_exp10TabGen_q <= "0001111111010100000110101111110001111100";
WHEN "0010000" => memoryC2_uid240_exp10TabGen_q <= "0010001000010110000001000101101110000011";
WHEN "0010001" => memoryC2_uid240_exp10TabGen_q <= "0010010001011100011101100001001111011100";
WHEN "0010010" => memoryC2_uid240_exp10TabGen_q <= "0010011010100111011110010011111100111011";
WHEN "0010011" => memoryC2_uid240_exp10TabGen_q <= "0010100011110111000101110000101010010001";
WHEN "0010100" => memoryC2_uid240_exp10TabGen_q <= "0010101101001011010110001011001100110101";
WHEN "0010101" => memoryC2_uid240_exp10TabGen_q <= "0010110110100100010001111000101101100011";
WHEN "0010110" => memoryC2_uid240_exp10TabGen_q <= "0011000000000001111011001111010111110010";
WHEN "0010111" => memoryC2_uid240_exp10TabGen_q <= "0011001001100100010100100110100111111010";
WHEN "0011000" => memoryC2_uid240_exp10TabGen_q <= "0011010011001011100000010111000010000011";
WHEN "0011001" => memoryC2_uid240_exp10TabGen_q <= "0011011100110111100000111010011011101000";
WHEN "0011010" => memoryC2_uid240_exp10TabGen_q <= "0011100110101000011000101011110100111100";
WHEN "0011011" => memoryC2_uid240_exp10TabGen_q <= "0011110000011110001010000111011001111100";
WHEN "0011100" => memoryC2_uid240_exp10TabGen_q <= "0011111010011000110111101010100111100101";
WHEN "0011101" => memoryC2_uid240_exp10TabGen_q <= "0100000100011000100011110100001010001010";
WHEN "0011110" => memoryC2_uid240_exp10TabGen_q <= "0100001110011101010001000011111100100101";
WHEN "0011111" => memoryC2_uid240_exp10TabGen_q <= "0100011000100111000001111011001011001100";
WHEN "0100000" => memoryC2_uid240_exp10TabGen_q <= "0100100010110101111000111100001111001111";
WHEN "0100001" => memoryC2_uid240_exp10TabGen_q <= "0100101101001001111000101010111001001000";
WHEN "0100010" => memoryC2_uid240_exp10TabGen_q <= "0100110111100011000011101100001000111111";
WHEN "0100011" => memoryC2_uid240_exp10TabGen_q <= "0101000010000001011100100110001111011101";
WHEN "0100100" => memoryC2_uid240_exp10TabGen_q <= "0101001100100101000110000000110011010000";
WHEN "0100101" => memoryC2_uid240_exp10TabGen_q <= "0101010111001110000010100100110010001010";
WHEN "0100110" => memoryC2_uid240_exp10TabGen_q <= "0101100001111100010100111100010110010011";
WHEN "0100111" => memoryC2_uid240_exp10TabGen_q <= "0101101100101111111111110011001000100100";
WHEN "0101000" => memoryC2_uid240_exp10TabGen_q <= "0101110111101001000101110110000001011000";
WHEN "0101001" => memoryC2_uid240_exp10TabGen_q <= "0110000010100111101001110011010011000100";
WHEN "0101010" => memoryC2_uid240_exp10TabGen_q <= "0110001101101011101110011010100101000110";
WHEN "0101011" => memoryC2_uid240_exp10TabGen_q <= "0110011000110101010110011100111100100110";
WHEN "0101100" => memoryC2_uid240_exp10TabGen_q <= "0110100100000100100100101100101110111111";
WHEN "0101101" => memoryC2_uid240_exp10TabGen_q <= "0110101111011001011011111101110100000010";
WHEN "0101110" => memoryC2_uid240_exp10TabGen_q <= "0110111010110011111111000101010111011100";
WHEN "0101111" => memoryC2_uid240_exp10TabGen_q <= "0111000110010100010000111010000000011010";
WHEN "0110000" => memoryC2_uid240_exp10TabGen_q <= "0111010001111010010100010011110110101100";
WHEN "0110001" => memoryC2_uid240_exp10TabGen_q <= "0111011101100110001100001100011001001011";
WHEN "0110010" => memoryC2_uid240_exp10TabGen_q <= "0111101001010111111011011110100111010001";
WHEN "0110011" => memoryC2_uid240_exp10TabGen_q <= "0111110101001111100101000110111011011110";
WHEN "0110100" => memoryC2_uid240_exp10TabGen_q <= "1000000001001101001100000011010001011000";
WHEN "0110101" => memoryC2_uid240_exp10TabGen_q <= "1000001101010000110011010011000011001011";
WHEN "0110110" => memoryC2_uid240_exp10TabGen_q <= "1000011001011010011101110111001000000101";
WHEN "0110111" => memoryC2_uid240_exp10TabGen_q <= "1000100101101010001110110001111100111001";
WHEN "0111000" => memoryC2_uid240_exp10TabGen_q <= "1000110010000000001001000111011110101101";
WHEN "0111001" => memoryC2_uid240_exp10TabGen_q <= "1000111110011100001111111101001001110101";
WHEN "0111010" => memoryC2_uid240_exp10TabGen_q <= "1001001010111110100110011010000010101010";
WHEN "0111011" => memoryC2_uid240_exp10TabGen_q <= "1001010111100111001111100110101100101010";
WHEN "0111100" => memoryC2_uid240_exp10TabGen_q <= "1001100100010110001110101101010011010010";
WHEN "0111101" => memoryC2_uid240_exp10TabGen_q <= "1001110001001011100110111001100101010000";
WHEN "0111110" => memoryC2_uid240_exp10TabGen_q <= "1001111110000111011011011000111010110011";
WHEN "0111111" => memoryC2_uid240_exp10TabGen_q <= "1010001011001001101111011010001101110011";
WHEN "1000000" => memoryC2_uid240_exp10TabGen_q <= "1010011000010010100110001110000110110000";
WHEN "1000001" => memoryC2_uid240_exp10TabGen_q <= "1010100101100010000011000110110011000011";
WHEN "1000010" => memoryC2_uid240_exp10TabGen_q <= "1010110010111000001001011000001000011101";
WHEN "1000011" => memoryC2_uid240_exp10TabGen_q <= "1011000000010100111100010111100111011010";
WHEN "1000100" => memoryC2_uid240_exp10TabGen_q <= "1011001101111000011111011100100000000010";
WHEN "1000101" => memoryC2_uid240_exp10TabGen_q <= "1011011011100010110101111111101001110101";
WHEN "1000110" => memoryC2_uid240_exp10TabGen_q <= "1011101001010100000011011011101000101011";
WHEN "1000111" => memoryC2_uid240_exp10TabGen_q <= "1011110111001100001011001100110011100100";
WHEN "1001000" => memoryC2_uid240_exp10TabGen_q <= "1100000101001011010000110001001000111011";
WHEN "1001001" => memoryC2_uid240_exp10TabGen_q <= "1100010011010001010111101000011100110101";
WHEN "1001010" => memoryC2_uid240_exp10TabGen_q <= "1100100001011110100011010100001111110100";
WHEN "1001011" => memoryC2_uid240_exp10TabGen_q <= "1100101111110010110111010111110101100001";
WHEN "1001100" => memoryC2_uid240_exp10TabGen_q <= "1100111110001110010111011000010010001101";
WHEN "1001101" => memoryC2_uid240_exp10TabGen_q <= "1101001100110001000110111100011110011111";
WHEN "1001110" => memoryC2_uid240_exp10TabGen_q <= "1101011011011011001001101101000101101011";
WHEN "1001111" => memoryC2_uid240_exp10TabGen_q <= "1101101010001100100011010100101001011110";
WHEN "1010000" => memoryC2_uid240_exp10TabGen_q <= "1101111001000101010111011111100000010111";
WHEN "1010001" => memoryC2_uid240_exp10TabGen_q <= "1110001000000101101001111011110110011101";
WHEN "1010010" => memoryC2_uid240_exp10TabGen_q <= "1110010111001101011110011001110010010001";
WHEN "1010011" => memoryC2_uid240_exp10TabGen_q <= "1110100110011100111000101011001110100000";
WHEN "1010100" => memoryC2_uid240_exp10TabGen_q <= "1110110101110011111100100100000011101110";
WHEN "1010101" => memoryC2_uid240_exp10TabGen_q <= "1111000101010010101101111010000001001010";
WHEN "1010110" => memoryC2_uid240_exp10TabGen_q <= "1111010100111001010000100100110101110101";
WHEN "1010111" => memoryC2_uid240_exp10TabGen_q <= "1111100100100111101000011110001001101110";
WHEN "1011000" => memoryC2_uid240_exp10TabGen_q <= "1111110100011101111001100001100000110101";
WHEN "1011001" => memoryC2_uid240_exp10TabGen_q <= "0000000100011100000111101100100001100111";
WHEN "1011010" => memoryC2_uid240_exp10TabGen_q <= "0000010100100010010110111110101101101101";
WHEN "1011011" => memoryC2_uid240_exp10TabGen_q <= "0000100100110000101011011001101011000010";
WHEN "1011100" => memoryC2_uid240_exp10TabGen_q <= "0000110101000111001001000000111111111100";
WHEN "1011101" => memoryC2_uid240_exp10TabGen_q <= "0001000101100101110011111010010000100110";
WHEN "1011110" => memoryC2_uid240_exp10TabGen_q <= "0001010110001100110000001101000111110111";
WHEN "1011111" => memoryC2_uid240_exp10TabGen_q <= "0001100110111100000010000011011000000011";
WHEN "1100000" => memoryC2_uid240_exp10TabGen_q <= "0001110111110011101101101000110011111110";
WHEN "1100001" => memoryC2_uid240_exp10TabGen_q <= "0010001000110011110111001011010101100011";
WHEN "1100010" => memoryC2_uid240_exp10TabGen_q <= "0010011001111100100010111011000000110011";
WHEN "1100011" => memoryC2_uid240_exp10TabGen_q <= "0010101011001101110101001010000001001001";
WHEN "1100100" => memoryC2_uid240_exp10TabGen_q <= "0010111100100111110010001100101001010000";
WHEN "1100101" => memoryC2_uid240_exp10TabGen_q <= "0011001110001010011110011001011001001101";
WHEN "1100110" => memoryC2_uid240_exp10TabGen_q <= "0011011111110101111110001000111101001011";
WHEN "1100111" => memoryC2_uid240_exp10TabGen_q <= "0011110001101010010101110110001100010001";
WHEN "1101000" => memoryC2_uid240_exp10TabGen_q <= "0100000011100111101001111110001101110100";
WHEN "1101001" => memoryC2_uid240_exp10TabGen_q <= "0100010101101101111111000000010101000100";
WHEN "1101010" => memoryC2_uid240_exp10TabGen_q <= "0100100111111101011001011110000111001011";
WHEN "1101011" => memoryC2_uid240_exp10TabGen_q <= "0100111010010101111101111011011110000001";
WHEN "1101100" => memoryC2_uid240_exp10TabGen_q <= "0101001100110111110000111110011111101100";
WHEN "1101101" => memoryC2_uid240_exp10TabGen_q <= "0101011111100010110111001111101000111010";
WHEN "1101110" => memoryC2_uid240_exp10TabGen_q <= "0101110010010111010101011001101101000111";
WHEN "1101111" => memoryC2_uid240_exp10TabGen_q <= "0110000101010101010000001001110100001010";
WHEN "1110000" => memoryC2_uid240_exp10TabGen_q <= "0110011000011100101100001111011011010100";
WHEN "1110001" => memoryC2_uid240_exp10TabGen_q <= "0110101011101101101110011100011010000001";
WHEN "1110010" => memoryC2_uid240_exp10TabGen_q <= "0110111111001000011011100101000001101011";
WHEN "1110011" => memoryC2_uid240_exp10TabGen_q <= "0111010010101100111000011111111100000111";
WHEN "1110100" => memoryC2_uid240_exp10TabGen_q <= "0111100110011011001010000110010011111010";
WHEN "1110101" => memoryC2_uid240_exp10TabGen_q <= "0111111010010011010101010011101001001100";
WHEN "1110110" => memoryC2_uid240_exp10TabGen_q <= "1000001110010101011111000110000010100010";
WHEN "1110111" => memoryC2_uid240_exp10TabGen_q <= "1000100010100001101100011110000000111101";
WHEN "1111000" => memoryC2_uid240_exp10TabGen_q <= "1000110110111000000010011110100110011111";
WHEN "1111001" => memoryC2_uid240_exp10TabGen_q <= "1001001011011000100110001101011100110010";
WHEN "1111010" => memoryC2_uid240_exp10TabGen_q <= "1001100000000011011100110010101000101011";
WHEN "1111011" => memoryC2_uid240_exp10TabGen_q <= "1001110100111000101011011000111010010001";
WHEN "1111100" => memoryC2_uid240_exp10TabGen_q <= "1010001001111000010111001101100011110110";
WHEN "1111101" => memoryC2_uid240_exp10TabGen_q <= "1010011111000010100101100000100001111000";
WHEN "1111110" => memoryC2_uid240_exp10TabGen_q <= "1010110100010111011011100100010110000001";
WHEN "1111111" => memoryC2_uid240_exp10TabGen_q <= "1011001001110110111110101110010001100110";
WHEN OTHERS =>
memoryC2_uid240_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--os_uid242_exp10TabGen(BITJOIN,241)@26
os_uid242_exp10TabGen_q <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_q & memoryC2_uid240_exp10TabGen_q;
--rndBit_uid263_exp10PolyEval(CONSTANT,262)
rndBit_uid263_exp10PolyEval_q <= "01";
--cIncludingRoundingBit_uid264_exp10PolyEval(BITJOIN,263)@26
cIncludingRoundingBit_uid264_exp10PolyEval_q <= os_uid242_exp10TabGen_q & rndBit_uid263_exp10PolyEval_q;
--reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0(REG,395)@26
reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q <= cIncludingRoundingBit_uid264_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid265_exp10PolyEval(ADD,264)@27
ts3_uid265_exp10PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q);
ts3_uid265_exp10PolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q(36)) & reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q);
ts3_uid265_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid265_exp10PolyEval_a) + SIGNED(ts3_uid265_exp10PolyEval_b));
ts3_uid265_exp10PolyEval_q <= ts3_uid265_exp10PolyEval_o(45 downto 0);
--s3_uid266_exp10PolyEval(BITSELECT,265)@27
s3_uid266_exp10PolyEval_in <= ts3_uid265_exp10PolyEval_q;
s3_uid266_exp10PolyEval_b <= s3_uid266_exp10PolyEval_in(45 downto 1);
--yTop27Bits_uid304_pT4_uid268_exp10PolyEval(BITSELECT,303)@27
yTop27Bits_uid304_pT4_uid268_exp10PolyEval_in <= s3_uid266_exp10PolyEval_b;
yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b <= yTop27Bits_uid304_pT4_uid268_exp10PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9(REG,400)@27
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q <= yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor(LOGICAL,1081)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_b <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_q <= not (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_a or ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_b);
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top(CONSTANT,1077)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top_q <= "01010";
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp(LOGICAL,1078)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_a <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_a = ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg(REG,1079)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena(REG,1082)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd(LOGICAL,1083)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_a and ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt(COUNTER,1073)
-- every=1, low=0, high=10, step=1, init=1
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i = 9 THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i - 10;
ELSE
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg(REG,1074)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux(MUX,1075)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem(DUALMEM,1072)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_iq(47 downto 0);
--yT4_uid267_exp10PolyEval(BITSELECT,266)@27
yT4_uid267_exp10PolyEval_in <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_q;
yT4_uid267_exp10PolyEval_b <= yT4_uid267_exp10PolyEval_in(47 downto 5);
--xBottomBits_uid307_pT4_uid268_exp10PolyEval(BITSELECT,306)@27
xBottomBits_uid307_pT4_uid268_exp10PolyEval_in <= yT4_uid267_exp10PolyEval_b(15 downto 0);
xBottomBits_uid307_pT4_uid268_exp10PolyEval_b <= xBottomBits_uid307_pT4_uid268_exp10PolyEval_in(15 downto 0);
--pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval(BITJOIN,308)@27
pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_q <= xBottomBits_uid307_pT4_uid268_exp10PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7(REG,399)@27
reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q <= pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid306_pT4_uid268_exp10PolyEval(BITSELECT,305)@27
yBottomBits_uid306_pT4_uid268_exp10PolyEval_in <= s3_uid266_exp10PolyEval_b(17 downto 0);
yBottomBits_uid306_pT4_uid268_exp10PolyEval_b <= yBottomBits_uid306_pT4_uid268_exp10PolyEval_in(17 downto 0);
--ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a(DELAY,748)@27
ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid306_pT4_uid268_exp10PolyEval_b, xout => ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval(BITJOIN,307)@28
spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_q <= GND_q & ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a_q;
--pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval(BITJOIN,309)@28
pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_q <= spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6(REG,398)@28
reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q <= pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a(DELAY,742)@27
ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid267_exp10PolyEval_b, xout => ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid303_pT4_uid268_exp10PolyEval(BITSELECT,302)@28
xTop27Bits_uid303_pT4_uid268_exp10PolyEval_in <= ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a_q;
xTop27Bits_uid303_pT4_uid268_exp10PolyEval_b <= xTop27Bits_uid303_pT4_uid268_exp10PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4(REG,397)@28
reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q <= xTop27Bits_uid303_pT4_uid268_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma(CHAINMULTADD,339)@29
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(0),28));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(1),28));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(0) * multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(1) * multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(1);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(0),56);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(1),56);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(1);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(1) + multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(1);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q),27);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q),27);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q),27);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval(BITSELECT,311)@32
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_in <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_q;
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_in(54 downto 8);
--highBBits_uid314_pT4_uid268_exp10PolyEval(BITSELECT,313)@32
highBBits_uid314_pT4_uid268_exp10PolyEval_in <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b;
highBBits_uid314_pT4_uid268_exp10PolyEval_b <= highBBits_uid314_pT4_uid268_exp10PolyEval_in(46 downto 18);
--ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a(DELAY,856)@27
ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b, xout => ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1(REG,402)@28
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q <= ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid305_pT4_uid268_exp10PolyEval(MULT,304)@29
topProd_uid305_pT4_uid268_exp10PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid305_pT4_uid268_exp10PolyEval_a),28)) * SIGNED(topProd_uid305_pT4_uid268_exp10PolyEval_b);
topProd_uid305_pT4_uid268_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid305_pT4_uid268_exp10PolyEval_a <= (others => '0');
topProd_uid305_pT4_uid268_exp10PolyEval_b <= (others => '0');
topProd_uid305_pT4_uid268_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid305_pT4_uid268_exp10PolyEval_a <= reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q;
topProd_uid305_pT4_uid268_exp10PolyEval_b <= reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q;
topProd_uid305_pT4_uid268_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid305_pT4_uid268_exp10PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid305_pT4_uid268_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid305_pT4_uid268_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid305_pT4_uid268_exp10PolyEval_q <= topProd_uid305_pT4_uid268_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid315_pT4_uid268_exp10PolyEval(ADD,314)@32
sumAHighB_uid315_pT4_uid268_exp10PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid305_pT4_uid268_exp10PolyEval_q(53)) & topProd_uid305_pT4_uid268_exp10PolyEval_q);
sumAHighB_uid315_pT4_uid268_exp10PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid314_pT4_uid268_exp10PolyEval_b(28)) & highBBits_uid314_pT4_uid268_exp10PolyEval_b);
sumAHighB_uid315_pT4_uid268_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid315_pT4_uid268_exp10PolyEval_a) + SIGNED(sumAHighB_uid315_pT4_uid268_exp10PolyEval_b));
sumAHighB_uid315_pT4_uid268_exp10PolyEval_q <= sumAHighB_uid315_pT4_uid268_exp10PolyEval_o(54 downto 0);
--lowRangeB_uid313_pT4_uid268_exp10PolyEval(BITSELECT,312)@32
lowRangeB_uid313_pT4_uid268_exp10PolyEval_in <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b(17 downto 0);
lowRangeB_uid313_pT4_uid268_exp10PolyEval_b <= lowRangeB_uid313_pT4_uid268_exp10PolyEval_in(17 downto 0);
--add0_uid313_uid316_pT4_uid268_exp10PolyEval(BITJOIN,315)@32
add0_uid313_uid316_pT4_uid268_exp10PolyEval_q <= sumAHighB_uid315_pT4_uid268_exp10PolyEval_q & lowRangeB_uid313_pT4_uid268_exp10PolyEval_b;
--R_uid317_pT4_uid268_exp10PolyEval(BITSELECT,316)@32
R_uid317_pT4_uid268_exp10PolyEval_in <= add0_uid313_uid316_pT4_uid268_exp10PolyEval_q(71 downto 0);
R_uid317_pT4_uid268_exp10PolyEval_b <= R_uid317_pT4_uid268_exp10PolyEval_in(71 downto 26);
--reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1(REG,404)@32
reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q <= R_uid317_pT4_uid268_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor(LOGICAL,1146)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_b <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_q <= not (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_a or ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_b);
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top(CONSTANT,1142)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top_q <= "01110";
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp(LOGICAL,1143)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_a <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_q <= "1" when ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_a = ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_b else "0";
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg(REG,1144)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena(REG,1147)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_q = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd(LOGICAL,1148)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_a <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_b <= en;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_a and ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_b;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg(DELAY,1123)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => addr_uid64_fpExpETest_b, xout => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt(COUNTER,1138)
-- every=1, low=0, high=14, step=1, init=1
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i = 13 THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i - 14;
ELSE
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i,4));
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg(REG,1139)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux(MUX,1140)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s <= en;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux: PROCESS (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s, ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q, ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s IS
WHEN "0" => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q;
WHEN "1" => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem(DUALMEM,1137)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ia <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_aa <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ab <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 4,
numwords_a => 15,
width_b => 7,
widthad_b => 4,
numwords_b => 15,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ia
);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_iq(6 downto 0);
--reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0(REG,379)@30
reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid238_exp10TabGen(LOOKUP,237)@31
memoryC1_uid238_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid238_exp10TabGen_q <= "00100000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC1_uid238_exp10TabGen_q <= "00100000000";
WHEN "0000001" => memoryC1_uid238_exp10TabGen_q <= "00100000010";
WHEN "0000010" => memoryC1_uid238_exp10TabGen_q <= "00100000100";
WHEN "0000011" => memoryC1_uid238_exp10TabGen_q <= "00100000110";
WHEN "0000100" => memoryC1_uid238_exp10TabGen_q <= "00100001000";
WHEN "0000101" => memoryC1_uid238_exp10TabGen_q <= "00100001010";
WHEN "0000110" => memoryC1_uid238_exp10TabGen_q <= "00100001100";
WHEN "0000111" => memoryC1_uid238_exp10TabGen_q <= "00100001110";
WHEN "0001000" => memoryC1_uid238_exp10TabGen_q <= "00100010000";
WHEN "0001001" => memoryC1_uid238_exp10TabGen_q <= "00100010010";
WHEN "0001010" => memoryC1_uid238_exp10TabGen_q <= "00100010100";
WHEN "0001011" => memoryC1_uid238_exp10TabGen_q <= "00100010110";
WHEN "0001100" => memoryC1_uid238_exp10TabGen_q <= "00100011001";
WHEN "0001101" => memoryC1_uid238_exp10TabGen_q <= "00100011011";
WHEN "0001110" => memoryC1_uid238_exp10TabGen_q <= "00100011101";
WHEN "0001111" => memoryC1_uid238_exp10TabGen_q <= "00100011111";
WHEN "0010000" => memoryC1_uid238_exp10TabGen_q <= "00100100010";
WHEN "0010001" => memoryC1_uid238_exp10TabGen_q <= "00100100100";
WHEN "0010010" => memoryC1_uid238_exp10TabGen_q <= "00100100110";
WHEN "0010011" => memoryC1_uid238_exp10TabGen_q <= "00100101000";
WHEN "0010100" => memoryC1_uid238_exp10TabGen_q <= "00100101011";
WHEN "0010101" => memoryC1_uid238_exp10TabGen_q <= "00100101101";
WHEN "0010110" => memoryC1_uid238_exp10TabGen_q <= "00100110000";
WHEN "0010111" => memoryC1_uid238_exp10TabGen_q <= "00100110010";
WHEN "0011000" => memoryC1_uid238_exp10TabGen_q <= "00100110100";
WHEN "0011001" => memoryC1_uid238_exp10TabGen_q <= "00100110111";
WHEN "0011010" => memoryC1_uid238_exp10TabGen_q <= "00100111001";
WHEN "0011011" => memoryC1_uid238_exp10TabGen_q <= "00100111100";
WHEN "0011100" => memoryC1_uid238_exp10TabGen_q <= "00100111110";
WHEN "0011101" => memoryC1_uid238_exp10TabGen_q <= "00101000001";
WHEN "0011110" => memoryC1_uid238_exp10TabGen_q <= "00101000011";
WHEN "0011111" => memoryC1_uid238_exp10TabGen_q <= "00101000110";
WHEN "0100000" => memoryC1_uid238_exp10TabGen_q <= "00101001000";
WHEN "0100001" => memoryC1_uid238_exp10TabGen_q <= "00101001011";
WHEN "0100010" => memoryC1_uid238_exp10TabGen_q <= "00101001101";
WHEN "0100011" => memoryC1_uid238_exp10TabGen_q <= "00101010000";
WHEN "0100100" => memoryC1_uid238_exp10TabGen_q <= "00101010011";
WHEN "0100101" => memoryC1_uid238_exp10TabGen_q <= "00101010101";
WHEN "0100110" => memoryC1_uid238_exp10TabGen_q <= "00101011000";
WHEN "0100111" => memoryC1_uid238_exp10TabGen_q <= "00101011011";
WHEN "0101000" => memoryC1_uid238_exp10TabGen_q <= "00101011101";
WHEN "0101001" => memoryC1_uid238_exp10TabGen_q <= "00101100000";
WHEN "0101010" => memoryC1_uid238_exp10TabGen_q <= "00101100011";
WHEN "0101011" => memoryC1_uid238_exp10TabGen_q <= "00101100110";
WHEN "0101100" => memoryC1_uid238_exp10TabGen_q <= "00101101001";
WHEN "0101101" => memoryC1_uid238_exp10TabGen_q <= "00101101011";
WHEN "0101110" => memoryC1_uid238_exp10TabGen_q <= "00101101110";
WHEN "0101111" => memoryC1_uid238_exp10TabGen_q <= "00101110001";
WHEN "0110000" => memoryC1_uid238_exp10TabGen_q <= "00101110100";
WHEN "0110001" => memoryC1_uid238_exp10TabGen_q <= "00101110111";
WHEN "0110010" => memoryC1_uid238_exp10TabGen_q <= "00101111010";
WHEN "0110011" => memoryC1_uid238_exp10TabGen_q <= "00101111101";
WHEN "0110100" => memoryC1_uid238_exp10TabGen_q <= "00110000000";
WHEN "0110101" => memoryC1_uid238_exp10TabGen_q <= "00110000011";
WHEN "0110110" => memoryC1_uid238_exp10TabGen_q <= "00110000110";
WHEN "0110111" => memoryC1_uid238_exp10TabGen_q <= "00110001001";
WHEN "0111000" => memoryC1_uid238_exp10TabGen_q <= "00110001100";
WHEN "0111001" => memoryC1_uid238_exp10TabGen_q <= "00110001111";
WHEN "0111010" => memoryC1_uid238_exp10TabGen_q <= "00110010010";
WHEN "0111011" => memoryC1_uid238_exp10TabGen_q <= "00110010101";
WHEN "0111100" => memoryC1_uid238_exp10TabGen_q <= "00110011001";
WHEN "0111101" => memoryC1_uid238_exp10TabGen_q <= "00110011100";
WHEN "0111110" => memoryC1_uid238_exp10TabGen_q <= "00110011111";
WHEN "0111111" => memoryC1_uid238_exp10TabGen_q <= "00110100010";
WHEN "1000000" => memoryC1_uid238_exp10TabGen_q <= "00110100110";
WHEN "1000001" => memoryC1_uid238_exp10TabGen_q <= "00110101001";
WHEN "1000010" => memoryC1_uid238_exp10TabGen_q <= "00110101100";
WHEN "1000011" => memoryC1_uid238_exp10TabGen_q <= "00110110000";
WHEN "1000100" => memoryC1_uid238_exp10TabGen_q <= "00110110011";
WHEN "1000101" => memoryC1_uid238_exp10TabGen_q <= "00110110110";
WHEN "1000110" => memoryC1_uid238_exp10TabGen_q <= "00110111010";
WHEN "1000111" => memoryC1_uid238_exp10TabGen_q <= "00110111101";
WHEN "1001000" => memoryC1_uid238_exp10TabGen_q <= "00111000001";
WHEN "1001001" => memoryC1_uid238_exp10TabGen_q <= "00111000100";
WHEN "1001010" => memoryC1_uid238_exp10TabGen_q <= "00111001000";
WHEN "1001011" => memoryC1_uid238_exp10TabGen_q <= "00111001011";
WHEN "1001100" => memoryC1_uid238_exp10TabGen_q <= "00111001111";
WHEN "1001101" => memoryC1_uid238_exp10TabGen_q <= "00111010011";
WHEN "1001110" => memoryC1_uid238_exp10TabGen_q <= "00111010110";
WHEN "1001111" => memoryC1_uid238_exp10TabGen_q <= "00111011010";
WHEN "1010000" => memoryC1_uid238_exp10TabGen_q <= "00111011110";
WHEN "1010001" => memoryC1_uid238_exp10TabGen_q <= "00111100010";
WHEN "1010010" => memoryC1_uid238_exp10TabGen_q <= "00111100101";
WHEN "1010011" => memoryC1_uid238_exp10TabGen_q <= "00111101001";
WHEN "1010100" => memoryC1_uid238_exp10TabGen_q <= "00111101101";
WHEN "1010101" => memoryC1_uid238_exp10TabGen_q <= "00111110001";
WHEN "1010110" => memoryC1_uid238_exp10TabGen_q <= "00111110101";
WHEN "1010111" => memoryC1_uid238_exp10TabGen_q <= "00111111001";
WHEN "1011000" => memoryC1_uid238_exp10TabGen_q <= "00111111101";
WHEN "1011001" => memoryC1_uid238_exp10TabGen_q <= "01000000001";
WHEN "1011010" => memoryC1_uid238_exp10TabGen_q <= "01000000101";
WHEN "1011011" => memoryC1_uid238_exp10TabGen_q <= "01000001001";
WHEN "1011100" => memoryC1_uid238_exp10TabGen_q <= "01000001101";
WHEN "1011101" => memoryC1_uid238_exp10TabGen_q <= "01000010001";
WHEN "1011110" => memoryC1_uid238_exp10TabGen_q <= "01000010101";
WHEN "1011111" => memoryC1_uid238_exp10TabGen_q <= "01000011001";
WHEN "1100000" => memoryC1_uid238_exp10TabGen_q <= "01000011101";
WHEN "1100001" => memoryC1_uid238_exp10TabGen_q <= "01000100010";
WHEN "1100010" => memoryC1_uid238_exp10TabGen_q <= "01000100110";
WHEN "1100011" => memoryC1_uid238_exp10TabGen_q <= "01000101010";
WHEN "1100100" => memoryC1_uid238_exp10TabGen_q <= "01000101111";
WHEN "1100101" => memoryC1_uid238_exp10TabGen_q <= "01000110011";
WHEN "1100110" => memoryC1_uid238_exp10TabGen_q <= "01000110111";
WHEN "1100111" => memoryC1_uid238_exp10TabGen_q <= "01000111100";
WHEN "1101000" => memoryC1_uid238_exp10TabGen_q <= "01001000000";
WHEN "1101001" => memoryC1_uid238_exp10TabGen_q <= "01001000101";
WHEN "1101010" => memoryC1_uid238_exp10TabGen_q <= "01001001001";
WHEN "1101011" => memoryC1_uid238_exp10TabGen_q <= "01001001110";
WHEN "1101100" => memoryC1_uid238_exp10TabGen_q <= "01001010011";
WHEN "1101101" => memoryC1_uid238_exp10TabGen_q <= "01001010111";
WHEN "1101110" => memoryC1_uid238_exp10TabGen_q <= "01001011100";
WHEN "1101111" => memoryC1_uid238_exp10TabGen_q <= "01001100001";
WHEN "1110000" => memoryC1_uid238_exp10TabGen_q <= "01001100110";
WHEN "1110001" => memoryC1_uid238_exp10TabGen_q <= "01001101010";
WHEN "1110010" => memoryC1_uid238_exp10TabGen_q <= "01001101111";
WHEN "1110011" => memoryC1_uid238_exp10TabGen_q <= "01001110100";
WHEN "1110100" => memoryC1_uid238_exp10TabGen_q <= "01001111001";
WHEN "1110101" => memoryC1_uid238_exp10TabGen_q <= "01001111110";
WHEN "1110110" => memoryC1_uid238_exp10TabGen_q <= "01010000011";
WHEN "1110111" => memoryC1_uid238_exp10TabGen_q <= "01010001000";
WHEN "1111000" => memoryC1_uid238_exp10TabGen_q <= "01010001101";
WHEN "1111001" => memoryC1_uid238_exp10TabGen_q <= "01010010010";
WHEN "1111010" => memoryC1_uid238_exp10TabGen_q <= "01010011000";
WHEN "1111011" => memoryC1_uid238_exp10TabGen_q <= "01010011101";
WHEN "1111100" => memoryC1_uid238_exp10TabGen_q <= "01010100010";
WHEN "1111101" => memoryC1_uid238_exp10TabGen_q <= "01010100111";
WHEN "1111110" => memoryC1_uid238_exp10TabGen_q <= "01010101101";
WHEN "1111111" => memoryC1_uid238_exp10TabGen_q <= "01010110010";
WHEN OTHERS =>
memoryC1_uid238_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--memoryC1_uid237_exp10TabGen(LOOKUP,236)@31
memoryC1_uid237_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid237_exp10TabGen_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC1_uid237_exp10TabGen_q <= "0000000000000000000000000000000000000000";
WHEN "0000001" => memoryC1_uid237_exp10TabGen_q <= "0000001000000001010101100000000000111010";
WHEN "0000010" => memoryC1_uid237_exp10TabGen_q <= "0000100000001010101101010101110111011110";
WHEN "0000011" => memoryC1_uid237_exp10TabGen_q <= "0001001000100100001101100100000100000110";
WHEN "0000100" => memoryC1_uid237_exp10TabGen_q <= "0010000001010110000000010001001001111011";
WHEN "0000101" => memoryC1_uid237_exp10TabGen_q <= "0011001010101000010011101001110000100000";
WHEN "0000110" => memoryC1_uid237_exp10TabGen_q <= "0100100100100011011010000010100111101010";
WHEN "0000111" => memoryC1_uid237_exp10TabGen_q <= "0110001111001111101001111010101100000101";
WHEN "0001000" => memoryC1_uid237_exp10TabGen_q <= "1000001010110101011101111101001101001110";
WHEN "0001001" => memoryC1_uid237_exp10TabGen_q <= "1010010111011101010101000011110011001011";
WHEN "0001010" => memoryC1_uid237_exp10TabGen_q <= "1100110101001111110010011000100111010001";
WHEN "0001011" => memoryC1_uid237_exp10TabGen_q <= "1111100100010101011101011000011100010001";
WHEN "0001100" => memoryC1_uid237_exp10TabGen_q <= "0010100100110111000001110100111000010010";
WHEN "0001101" => memoryC1_uid237_exp10TabGen_q <= "0101110110111101001111110110100000001001";
WHEN "0001110" => memoryC1_uid237_exp10TabGen_q <= "1001011010110000111011111111000011100110";
WHEN "0001111" => memoryC1_uid237_exp10TabGen_q <= "1101010000011010111111001011101001010000";
WHEN "0010000" => memoryC1_uid237_exp10TabGen_q <= "0001011000000100010110110110111101011001";
WHEN "0010001" => memoryC1_uid237_exp10TabGen_q <= "0101110001110110000100111011100010100010";
WHEN "0010010" => memoryC1_uid237_exp10TabGen_q <= "1010011101111001001111110110000000011101";
WHEN "0010011" => memoryC1_uid237_exp10TabGen_q <= "1111011100010111000010100111010101011010";
WHEN "0010100" => memoryC1_uid237_exp10TabGen_q <= "0100101101011000101100110111001011010010";
WHEN "0010101" => memoryC1_uid237_exp10TabGen_q <= "1010010001000111100010110110001000001100";
WHEN "0010110" => memoryC1_uid237_exp10TabGen_q <= "0000000111101100111101100000000110110001";
WHEN "0010111" => memoryC1_uid237_exp10TabGen_q <= "0110010001010010011010011110101001111111";
WHEN "0011000" => memoryC1_uid237_exp10TabGen_q <= "1100101110000001011100001011010110001100";
WHEN "0011001" => memoryC1_uid237_exp10TabGen_q <= "0011011110000011101001110010001000001011";
WHEN "0011010" => memoryC1_uid237_exp10TabGen_q <= "1010100001100010101111010011110000010000";
WHEN "0011011" => memoryC1_uid237_exp10TabGen_q <= "0001111000101000011101101000001101001011";
WHEN "0011100" => memoryC1_uid237_exp10TabGen_q <= "1001100011011110101010100001000111100100";
WHEN "0011101" => memoryC1_uid237_exp10TabGen_q <= "0001100010001111010000101100001111101101";
WHEN "0011110" => memoryC1_uid237_exp10TabGen_q <= "1001110101000100001111110101111100011111";
WHEN "0011111" => memoryC1_uid237_exp10TabGen_q <= "0010011100000111101100101011101010111111";
WHEN "0100000" => memoryC1_uid237_exp10TabGen_q <= "1011010111100011110000111110100000011101";
WHEN "0100001" => memoryC1_uid237_exp10TabGen_q <= "0100100111100010101011100101101011001010";
WHEN "0100010" => memoryC1_uid237_exp10TabGen_q <= "1110001100001110110000100001000111011110";
WHEN "0100011" => memoryC1_uid237_exp10TabGen_q <= "1000000101110010011000111100000100110111";
WHEN "0100100" => memoryC1_uid237_exp10TabGen_q <= "0010010100011000000011001111101011010111";
WHEN "0100101" => memoryC1_uid237_exp10TabGen_q <= "1100111000001010010011000101100010111111";
WHEN "0100110" => memoryC1_uid237_exp10TabGen_q <= "0111110001010011110001011010011110110011";
WHEN "0100111" => memoryC1_uid237_exp10TabGen_q <= "0010111111111111001100100001000011111001";
WHEN "0101000" => memoryC1_uid237_exp10TabGen_q <= "1110100100010111011000000100010111111100";
WHEN "0101001" => memoryC1_uid237_exp10TabGen_q <= "1010011110100111001101001010101100001001";
WHEN "0101010" => memoryC1_uid237_exp10TabGen_q <= "0110101110111001101010011000001100101111";
WHEN "0101011" => memoryC1_uid237_exp10TabGen_q <= "0011010101011001110011110001101111000101";
WHEN "0101100" => memoryC1_uid237_exp10TabGen_q <= "0000010010010010110010111111100101001101";
WHEN "0101101" => memoryC1_uid237_exp10TabGen_q <= "1101100101101111110111010000001101001010";
WHEN "0101110" => memoryC1_uid237_exp10TabGen_q <= "1011001111111100010101011011000111100000";
WHEN "0101111" => memoryC1_uid237_exp10TabGen_q <= "1001010001000011101000000011101011010001";
WHEN "0110000" => memoryC1_uid237_exp10TabGen_q <= "0111101001010001001111011011111011111001";
WHEN "0110001" => memoryC1_uid237_exp10TabGen_q <= "0110011000110000110001100111100011000100";
WHEN "0110010" => memoryC1_uid237_exp10TabGen_q <= "0101011111101101111010011110101000100111";
WHEN "0110011" => memoryC1_uid237_exp10TabGen_q <= "0100111110010100011011110000101110110000";
WHEN "0110100" => memoryC1_uid237_exp10TabGen_q <= "0100110100110000001101000111101101011011";
WHEN "0110101" => memoryC1_uid237_exp10TabGen_q <= "0101000011001101001100001010110000110011";
WHEN "0110110" => memoryC1_uid237_exp10TabGen_q <= "0101101001110111011100100001011001001110";
WHEN "0110111" => memoryC1_uid237_exp10TabGen_q <= "0110101000111011000111110110011010101000";
WHEN "0111000" => memoryC1_uid237_exp10TabGen_q <= "1000000000100100011101111011000000000000";
WHEN "0111001" => memoryC1_uid237_exp10TabGen_q <= "1001110000111111110100101001101111110010";
WHEN "0111010" => memoryC1_uid237_exp10TabGen_q <= "1011111010011001101000001001101111101100";
WHEN "0111011" => memoryC1_uid237_exp10TabGen_q <= "1110011100111110011010110001101101110011";
WHEN "0111100" => memoryC1_uid237_exp10TabGen_q <= "0001011000111010110101001011000111010110";
WHEN "0111101" => memoryC1_uid237_exp10TabGen_q <= "0100101110011011100110010101010100001010";
WHEN "0111110" => memoryC1_uid237_exp10TabGen_q <= "1000011101101101100011101000110001001110";
WHEN "0111111" => memoryC1_uid237_exp10TabGen_q <= "1100100110111101101000111010001111101111";
WHEN "1000000" => memoryC1_uid237_exp10TabGen_q <= "0001001010011000111000011110000001110001";
WHEN "1000001" => memoryC1_uid237_exp10TabGen_q <= "0110001000001100011011001011001100110100";
WHEN "1000010" => memoryC1_uid237_exp10TabGen_q <= "1011100000100101100000011110111011011101";
WHEN "1000011" => memoryC1_uid237_exp10TabGen_q <= "0001010011110001011110011111110001000001";
WHEN "1000100" => memoryC1_uid237_exp10TabGen_q <= "0111100001111101110010000000111110011000";
WHEN "1000101" => memoryC1_uid237_exp10TabGen_q <= "1110001011010111111110100101111010101100";
WHEN "1000110" => memoryC1_uid237_exp10TabGen_q <= "0101010000001101101110100101011011101100";
WHEN "1000111" => memoryC1_uid237_exp10TabGen_q <= "1100110000101100110011001101001111000101";
WHEN "1001000" => memoryC1_uid237_exp10TabGen_q <= "0100101101000011000100100101011001001000";
WHEN "1001001" => memoryC1_uid237_exp10TabGen_q <= "1101000101011110100001110011110000011001";
WHEN "1001010" => memoryC1_uid237_exp10TabGen_q <= "0101111010001101010000111111011111001100";
WHEN "1001011" => memoryC1_uid237_exp10TabGen_q <= "1111001011011101011111010100100100001011";
WHEN "1001100" => memoryC1_uid237_exp10TabGen_q <= "1000111001011101100001000111010110000110";
WHEN "1001101" => memoryC1_uid237_exp10TabGen_q <= "0011000100011011110001111000001000100101";
WHEN "1001110" => memoryC1_uid237_exp10TabGen_q <= "1101101100100110110100010110110011010110";
WHEN "1001111" => memoryC1_uid237_exp10TabGen_q <= "1000110010001101010010100110011010010111";
WHEN "1010000" => memoryC1_uid237_exp10TabGen_q <= "0100010101011101111110000000111000111010";
WHEN "1010001" => memoryC1_uid237_exp10TabGen_q <= "0000010110100111101111011010101101110110";
WHEN "1010010" => memoryC1_uid237_exp10TabGen_q <= "1100110101111001100111000110101001001101";
WHEN "1010011" => memoryC1_uid237_exp10TabGen_q <= "1001110011100010101100111001011101100011";
WHEN "1010100" => memoryC1_uid237_exp10TabGen_q <= "0111001111110010010000001101110000010000";
WHEN "1010101" => memoryC1_uid237_exp10TabGen_q <= "0101001010110111101000000111101111000000";
WHEN "1010110" => memoryC1_uid237_exp10TabGen_q <= "0011100101000010010011011001000011111010";
WHEN "1010111" => memoryC1_uid237_exp10TabGen_q <= "0010011110100001111000100100101110110000";
WHEN "1011000" => memoryC1_uid237_exp10TabGen_q <= "0001110111100110000110000010111110001011";
WHEN "1011001" => memoryC1_uid237_exp10TabGen_q <= "0001110000011110110010000101001010010000";
WHEN "1011010" => memoryC1_uid237_exp10TabGen_q <= "0010001001011011111010111001110011101101";
WHEN "1011011" => memoryC1_uid237_exp10TabGen_q <= "0011000010101101100110110000100001110010";
WHEN "1011100" => memoryC1_uid237_exp10TabGen_q <= "0100011100100100000011111110000100111100";
WHEN "1011101" => memoryC1_uid237_exp10TabGen_q <= "0110010111001111101001000000011010110011";
WHEN "1011110" => memoryC1_uid237_exp10TabGen_q <= "1000110011000000110100100010110010101001";
WHEN "1011111" => memoryC1_uid237_exp10TabGen_q <= "1011110000001000001101100001110100111001";
WHEN "1100000" => memoryC1_uid237_exp10TabGen_q <= "1111001110110110100011001111101110011101";
WHEN "1100001" => memoryC1_uid237_exp10TabGen_q <= "0011001111011100101101011000011011011101";
WHEN "1100010" => memoryC1_uid237_exp10TabGen_q <= "0111110010001011101100000101110100110000";
WHEN "1100011" => memoryC1_uid237_exp10TabGen_q <= "1100110111010100101000000100000000111000";
WHEN "1100100" => memoryC1_uid237_exp10TabGen_q <= "0010011111001000110010100101100110001010";
WHEN "1100101" => memoryC1_uid237_exp10TabGen_q <= "1000101001111001100101100111111110010101";
WHEN "1100110" => memoryC1_uid237_exp10TabGen_q <= "1111010111111000100011110111101101010110";
WHEN "1100111" => memoryC1_uid237_exp10TabGen_q <= "0110101001010111011000110100111010100000";
WHEN "1101000" => memoryC1_uid237_exp10TabGen_q <= "1110011110100111111000110111101010100011";
WHEN "1101001" => memoryC1_uid237_exp10TabGen_q <= "0110110111111100000001010100011101110011";
WHEN "1101010" => memoryC1_uid237_exp10TabGen_q <= "1111110101100101111000100000101110100001";
WHEN "1101011" => memoryC1_uid237_exp10TabGen_q <= "1001010111110111101101110111010010010010";
WHEN "1101100" => memoryC1_uid237_exp10TabGen_q <= "0011011111000011111001111100111111011110";
WHEN "1101101" => memoryC1_uid237_exp10TabGen_q <= "1110001011011100111110100101010001110110";
WHEN "1101110" => memoryC1_uid237_exp10TabGen_q <= "1001011101010101100110110110110011001000";
WHEN "1101111" => memoryC1_uid237_exp10TabGen_q <= "0101010101000000100111010000000110011111";
WHEN "1110000" => memoryC1_uid237_exp10TabGen_q <= "0001110010110000111101101100010101100001";
WHEN "1110001" => memoryC1_uid237_exp10TabGen_q <= "1110110110111001110001100111111111010101";
WHEN "1110010" => memoryC1_uid237_exp10TabGen_q <= "1100100001101110010100000101101010011001";
WHEN "1110011" => memoryC1_uid237_exp10TabGen_q <= "1010110011100001111111110010111001100100";
WHEN "1110100" => memoryC1_uid237_exp10TabGen_q <= "1001101100101000011001001101000001001110";
WHEN "1110101" => memoryC1_uid237_exp10TabGen_q <= "1001001101010101001110100110000010110100";
WHEN "1110110" => memoryC1_uid237_exp10TabGen_q <= "1001010101111100011000001001100101100100";
WHEN "1110111" => memoryC1_uid237_exp10TabGen_q <= "1010000110110001111000000001110110110011";
WHEN "1111000" => memoryC1_uid237_exp10TabGen_q <= "1011100000001001111010011100101001101110";
WHEN "1111001" => memoryC1_uid237_exp10TabGen_q <= "1101100010011000110101110000011001010011";
WHEN "1111010" => memoryC1_uid237_exp10TabGen_q <= "0000001101110011001010100001010000011101";
WHEN "1111011" => memoryC1_uid237_exp10TabGen_q <= "0011100010101101100011100110001111100011";
WHEN "1111100" => memoryC1_uid237_exp10TabGen_q <= "0111100001011100110110001110011000110111";
WHEN "1111101" => memoryC1_uid237_exp10TabGen_q <= "1100001010010110000010000101111100110011";
WHEN "1111110" => memoryC1_uid237_exp10TabGen_q <= "0001011101101110010001011011101010111011";
WHEN "1111111" => memoryC1_uid237_exp10TabGen_q <= "0111011011111010111001000110000010110110";
WHEN OTHERS =>
memoryC1_uid237_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--os_uid239_exp10TabGen(BITJOIN,238)@32
os_uid239_exp10TabGen_q <= memoryC1_uid238_exp10TabGen_q & memoryC1_uid237_exp10TabGen_q;
--cIncludingRoundingBit_uid270_exp10PolyEval(BITJOIN,269)@32
cIncludingRoundingBit_uid270_exp10PolyEval_q <= os_uid239_exp10TabGen_q & rndBit_uid263_exp10PolyEval_q;
--reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0(REG,403)@32
reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q <= cIncludingRoundingBit_uid270_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid271_exp10PolyEval(ADD,270)@33
ts4_uid271_exp10PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q);
ts4_uid271_exp10PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q(45)) & reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q);
ts4_uid271_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid271_exp10PolyEval_a) + SIGNED(ts4_uid271_exp10PolyEval_b));
ts4_uid271_exp10PolyEval_q <= ts4_uid271_exp10PolyEval_o(53 downto 0);
--s4_uid272_exp10PolyEval(BITSELECT,271)@33
s4_uid272_exp10PolyEval_in <= ts4_uid271_exp10PolyEval_q;
s4_uid272_exp10PolyEval_b <= s4_uid272_exp10PolyEval_in(53 downto 1);
--yTop27Bits_uid319_pT5_uid274_exp10PolyEval(BITSELECT,318)@33
yTop27Bits_uid319_pT5_uid274_exp10PolyEval_in <= s4_uid272_exp10PolyEval_b;
yTop27Bits_uid319_pT5_uid274_exp10PolyEval_b <= yTop27Bits_uid319_pT5_uid274_exp10PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9(REG,408)@33
reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q <= yTop27Bits_uid319_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor(LOGICAL,1107)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_b <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_q <= not (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_a or ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_b);
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top(CONSTANT,1103)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top_q <= "010000";
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp(LOGICAL,1104)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_a <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_a = ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg(REG,1105)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena(REG,1108)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd(LOGICAL,1109)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_a <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_a and ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_b;
--xBottomBits_uid322_pT5_uid274_exp10PolyEval(BITSELECT,321)@14
xBottomBits_uid322_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b(20 downto 0);
xBottomBits_uid322_pT5_uid274_exp10PolyEval_b <= xBottomBits_uid322_pT5_uid274_exp10PolyEval_in(20 downto 0);
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg(DELAY,1097)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => xBottomBits_uid322_pT5_uid274_exp10PolyEval_b, xout => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt(COUNTER,1099)
-- every=1, low=0, high=16, step=1, init=1
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i = 15 THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg(REG,1100)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux(MUX,1101)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem(DUALMEM,1098)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 5,
numwords_a => 17,
width_b => 21,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_iq(20 downto 0);
--pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval(BITJOIN,325)@33
pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((4 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7(REG,407)@33
reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q <= pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor(LOGICAL,1094)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_b <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_q <= not (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_a or ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_b);
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top(CONSTANT,1090)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top_q <= "010001";
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp(LOGICAL,1091)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_a <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_a = ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg(REG,1092)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena(REG,1095)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd(LOGICAL,1096)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_a and ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_b;
--xTop26Bits_uid323_pT5_uid274_exp10PolyEval(BITSELECT,322)@14
xTop26Bits_uid323_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b <= xTop26Bits_uid323_pT5_uid274_exp10PolyEval_in(47 downto 22);
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg(DELAY,1084)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b, xout => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt(COUNTER,1086)
-- every=1, low=0, high=17, step=1, init=1
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i = 16 THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i - 17;
ELSE
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg(REG,1087)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux(MUX,1088)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem(DUALMEM,1085)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 18,
width_b => 26,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval(BITJOIN,324)@34
spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_q <= GND_q & ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6(REG,406)@34
reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q <= spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid321_pT5_uid274_exp10PolyEval(BITSELECT,320)@33
yBottomBits_uid321_pT5_uid274_exp10PolyEval_in <= s4_uid272_exp10PolyEval_b(25 downto 0);
yBottomBits_uid321_pT5_uid274_exp10PolyEval_b <= yBottomBits_uid321_pT5_uid274_exp10PolyEval_in(25 downto 0);
--ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b(DELAY,768)@33
ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid321_pT5_uid274_exp10PolyEval_b, xout => ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval(BITJOIN,326)@34
pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_q <= ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4(REG,405)@34
reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q <= pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--VCC(CONSTANT,1)
VCC_q <= "1";
--multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma(CHAINMULTADD,340)@35
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(0),28));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(1),28));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(0) * multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(1) * multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(1);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(0),56);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(1),56);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(1);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(1) + multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(1);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q),27);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q),27);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q),27);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval(BITSELECT,328)@38
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_in <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_q;
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_in(54 downto 1);
--highBBits_uid335_pT5_uid274_exp10PolyEval(BITSELECT,334)@38
highBBits_uid335_pT5_uid274_exp10PolyEval_in <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b;
highBBits_uid335_pT5_uid274_exp10PolyEval_b <= highBBits_uid335_pT5_uid274_exp10PolyEval_in(53 downto 19);
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor(LOGICAL,1170)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_b <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_a or ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_b);
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena(REG,1171)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd(LOGICAL,1172)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_b;
--xTop27Bits_uid318_pT5_uid274_exp10PolyEval(BITSELECT,317)@14
xTop27Bits_uid318_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b <= xTop27Bits_uid318_pT5_uid274_exp10PolyEval_in(47 downto 21);
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg(DELAY,1160)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b, xout => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem(DUALMEM,1161)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_aa <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ab <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 5,
numwords_a => 17,
width_b => 27,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0(REG,411)@33
reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid320_pT5_uid274_exp10PolyEval(MULT,319)@34
topProd_uid320_pT5_uid274_exp10PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid320_pT5_uid274_exp10PolyEval_a),28)) * SIGNED(topProd_uid320_pT5_uid274_exp10PolyEval_b);
topProd_uid320_pT5_uid274_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid320_pT5_uid274_exp10PolyEval_a <= (others => '0');
topProd_uid320_pT5_uid274_exp10PolyEval_b <= (others => '0');
topProd_uid320_pT5_uid274_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid320_pT5_uid274_exp10PolyEval_a <= reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q;
topProd_uid320_pT5_uid274_exp10PolyEval_b <= reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q;
topProd_uid320_pT5_uid274_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid320_pT5_uid274_exp10PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid320_pT5_uid274_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid320_pT5_uid274_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid320_pT5_uid274_exp10PolyEval_q <= topProd_uid320_pT5_uid274_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor(LOGICAL,1120)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_b <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_q <= not (ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_a or ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_b);
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena(REG,1121)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_q = "1") THEN
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd(LOGICAL,1122)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_a <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_b <= en;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_q <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_a and ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_b;
--sSM0W_uid331_pT5_uid274_exp10PolyEval(BITSELECT,330)@14
sSM0W_uid331_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b(20 downto 0);
sSM0W_uid331_pT5_uid274_exp10PolyEval_b <= sSM0W_uid331_pT5_uid274_exp10PolyEval_in(20 downto 18);
--reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1(REG,410)@14
reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q <= sSM0W_uid331_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg(DELAY,1110)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q, xout => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem(DUALMEM,1111)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ia <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 17,
width_b => 3,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_iq,
address_a => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_aa,
data_a => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ia
);
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 <= areset;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_q <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_iq(2 downto 0);
--sSM0H_uid330_pT5_uid274_exp10PolyEval(BITSELECT,329)@33
sSM0H_uid330_pT5_uid274_exp10PolyEval_in <= s4_uid272_exp10PolyEval_b(25 downto 0);
sSM0H_uid330_pT5_uid274_exp10PolyEval_b <= sSM0H_uid330_pT5_uid274_exp10PolyEval_in(25 downto 23);
--reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0(REG,409)@33
reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q <= sSM0H_uid330_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid332_pT5_uid274_exp10PolyEval(MULT,331)@34
sm0_uid332_pT5_uid274_exp10PolyEval_pr <= UNSIGNED(sm0_uid332_pT5_uid274_exp10PolyEval_a) * UNSIGNED(sm0_uid332_pT5_uid274_exp10PolyEval_b);
sm0_uid332_pT5_uid274_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid332_pT5_uid274_exp10PolyEval_a <= (others => '0');
sm0_uid332_pT5_uid274_exp10PolyEval_b <= (others => '0');
sm0_uid332_pT5_uid274_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid332_pT5_uid274_exp10PolyEval_a <= reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q;
sm0_uid332_pT5_uid274_exp10PolyEval_b <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_q;
sm0_uid332_pT5_uid274_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid332_pT5_uid274_exp10PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid332_pT5_uid274_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid332_pT5_uid274_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid332_pT5_uid274_exp10PolyEval_q <= sm0_uid332_pT5_uid274_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval(BITJOIN,332)@37
TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q <= topProd_uid320_pT5_uid274_exp10PolyEval_q & sm0_uid332_pT5_uid274_exp10PolyEval_q;
--ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a(DELAY,778)@37
ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q, xout => ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid336_pT5_uid274_exp10PolyEval(ADD,335)@38
sumAHighB_uid336_pT5_uid274_exp10PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q);
sumAHighB_uid336_pT5_uid274_exp10PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid335_pT5_uid274_exp10PolyEval_b(34)) & highBBits_uid335_pT5_uid274_exp10PolyEval_b);
sumAHighB_uid336_pT5_uid274_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid336_pT5_uid274_exp10PolyEval_a) + SIGNED(sumAHighB_uid336_pT5_uid274_exp10PolyEval_b));
sumAHighB_uid336_pT5_uid274_exp10PolyEval_q <= sumAHighB_uid336_pT5_uid274_exp10PolyEval_o(60 downto 0);
--lowRangeB_uid334_pT5_uid274_exp10PolyEval(BITSELECT,333)@38
lowRangeB_uid334_pT5_uid274_exp10PolyEval_in <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b(18 downto 0);
lowRangeB_uid334_pT5_uid274_exp10PolyEval_b <= lowRangeB_uid334_pT5_uid274_exp10PolyEval_in(18 downto 0);
--add0_uid334_uid337_pT5_uid274_exp10PolyEval(BITJOIN,336)@38
add0_uid334_uid337_pT5_uid274_exp10PolyEval_q <= sumAHighB_uid336_pT5_uid274_exp10PolyEval_q & lowRangeB_uid334_pT5_uid274_exp10PolyEval_b;
--R_uid338_pT5_uid274_exp10PolyEval(BITSELECT,337)@38
R_uid338_pT5_uid274_exp10PolyEval_in <= add0_uid334_uid337_pT5_uid274_exp10PolyEval_q(78 downto 0);
R_uid338_pT5_uid274_exp10PolyEval_b <= R_uid338_pT5_uid274_exp10PolyEval_in(78 downto 24);
--reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1(REG,414)@38
reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q <= R_uid338_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor(LOGICAL,1016)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_b <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_q <= not (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_a or ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top(CONSTANT,1012)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top_q <= "010100";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp(LOGICAL,1013)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_q <= "1" when ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_a = ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_b else "0";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg(REG,1014)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena(REG,1017)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd(LOGICAL,1018)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_a and ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_b;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt(COUNTER,1008)
-- every=1, low=0, high=20, step=1, init=1
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i = 19 THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i - 20;
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg(REG,1009)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux(MUX,1010)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s, ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q, ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem(DUALMEM,1007)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ia <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 21,
width_b => 7,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ia
);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_iq(6 downto 0);
--memoryC0_uid235_exp10TabGen(LOOKUP,234)@37
memoryC0_uid235_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid235_exp10TabGen_q <= "001000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid235_exp10TabGen_q <= "001000000000000000";
WHEN "0000001" => memoryC0_uid235_exp10TabGen_q <= "001000000100000001";
WHEN "0000010" => memoryC0_uid235_exp10TabGen_q <= "001000001000000100";
WHEN "0000011" => memoryC0_uid235_exp10TabGen_q <= "001000001100001001";
WHEN "0000100" => memoryC0_uid235_exp10TabGen_q <= "001000010000010000";
WHEN "0000101" => memoryC0_uid235_exp10TabGen_q <= "001000010100011001";
WHEN "0000110" => memoryC0_uid235_exp10TabGen_q <= "001000011000100100";
WHEN "0000111" => memoryC0_uid235_exp10TabGen_q <= "001000011100110001";
WHEN "0001000" => memoryC0_uid235_exp10TabGen_q <= "001000100001000001";
WHEN "0001001" => memoryC0_uid235_exp10TabGen_q <= "001000100101010010";
WHEN "0001010" => memoryC0_uid235_exp10TabGen_q <= "001000101001100110";
WHEN "0001011" => memoryC0_uid235_exp10TabGen_q <= "001000101101111100";
WHEN "0001100" => memoryC0_uid235_exp10TabGen_q <= "001000110010010100";
WHEN "0001101" => memoryC0_uid235_exp10TabGen_q <= "001000110110101110";
WHEN "0001110" => memoryC0_uid235_exp10TabGen_q <= "001000111011001011";
WHEN "0001111" => memoryC0_uid235_exp10TabGen_q <= "001000111111101010";
WHEN "0010000" => memoryC0_uid235_exp10TabGen_q <= "001001000100001011";
WHEN "0010001" => memoryC0_uid235_exp10TabGen_q <= "001001001000101110";
WHEN "0010010" => memoryC0_uid235_exp10TabGen_q <= "001001001101010011";
WHEN "0010011" => memoryC0_uid235_exp10TabGen_q <= "001001010001111011";
WHEN "0010100" => memoryC0_uid235_exp10TabGen_q <= "001001010110100101";
WHEN "0010101" => memoryC0_uid235_exp10TabGen_q <= "001001011011010010";
WHEN "0010110" => memoryC0_uid235_exp10TabGen_q <= "001001100000000000";
WHEN "0010111" => memoryC0_uid235_exp10TabGen_q <= "001001100100110010";
WHEN "0011000" => memoryC0_uid235_exp10TabGen_q <= "001001101001100101";
WHEN "0011001" => memoryC0_uid235_exp10TabGen_q <= "001001101110011011";
WHEN "0011010" => memoryC0_uid235_exp10TabGen_q <= "001001110011010100";
WHEN "0011011" => memoryC0_uid235_exp10TabGen_q <= "001001111000001111";
WHEN "0011100" => memoryC0_uid235_exp10TabGen_q <= "001001111101001100";
WHEN "0011101" => memoryC0_uid235_exp10TabGen_q <= "001010000010001100";
WHEN "0011110" => memoryC0_uid235_exp10TabGen_q <= "001010000111001110";
WHEN "0011111" => memoryC0_uid235_exp10TabGen_q <= "001010001100010011";
WHEN "0100000" => memoryC0_uid235_exp10TabGen_q <= "001010010001011010";
WHEN "0100001" => memoryC0_uid235_exp10TabGen_q <= "001010010110100100";
WHEN "0100010" => memoryC0_uid235_exp10TabGen_q <= "001010011011110001";
WHEN "0100011" => memoryC0_uid235_exp10TabGen_q <= "001010100001000000";
WHEN "0100100" => memoryC0_uid235_exp10TabGen_q <= "001010100110010010";
WHEN "0100101" => memoryC0_uid235_exp10TabGen_q <= "001010101011100111";
WHEN "0100110" => memoryC0_uid235_exp10TabGen_q <= "001010110000111110";
WHEN "0100111" => memoryC0_uid235_exp10TabGen_q <= "001010110110010111";
WHEN "0101000" => memoryC0_uid235_exp10TabGen_q <= "001010111011110100";
WHEN "0101001" => memoryC0_uid235_exp10TabGen_q <= "001011000001010011";
WHEN "0101010" => memoryC0_uid235_exp10TabGen_q <= "001011000110110101";
WHEN "0101011" => memoryC0_uid235_exp10TabGen_q <= "001011001100011010";
WHEN "0101100" => memoryC0_uid235_exp10TabGen_q <= "001011010010000010";
WHEN "0101101" => memoryC0_uid235_exp10TabGen_q <= "001011010111101100";
WHEN "0101110" => memoryC0_uid235_exp10TabGen_q <= "001011011101011001";
WHEN "0101111" => memoryC0_uid235_exp10TabGen_q <= "001011100011001010";
WHEN "0110000" => memoryC0_uid235_exp10TabGen_q <= "001011101000111101";
WHEN "0110001" => memoryC0_uid235_exp10TabGen_q <= "001011101110110011";
WHEN "0110010" => memoryC0_uid235_exp10TabGen_q <= "001011110100101011";
WHEN "0110011" => memoryC0_uid235_exp10TabGen_q <= "001011111010100111";
WHEN "0110100" => memoryC0_uid235_exp10TabGen_q <= "001100000000100110";
WHEN "0110101" => memoryC0_uid235_exp10TabGen_q <= "001100000110101000";
WHEN "0110110" => memoryC0_uid235_exp10TabGen_q <= "001100001100101101";
WHEN "0110111" => memoryC0_uid235_exp10TabGen_q <= "001100010010110101";
WHEN "0111000" => memoryC0_uid235_exp10TabGen_q <= "001100011001000000";
WHEN "0111001" => memoryC0_uid235_exp10TabGen_q <= "001100011111001110";
WHEN "0111010" => memoryC0_uid235_exp10TabGen_q <= "001100100101011111";
WHEN "0111011" => memoryC0_uid235_exp10TabGen_q <= "001100101011110011";
WHEN "0111100" => memoryC0_uid235_exp10TabGen_q <= "001100110010001011";
WHEN "0111101" => memoryC0_uid235_exp10TabGen_q <= "001100111000100101";
WHEN "0111110" => memoryC0_uid235_exp10TabGen_q <= "001100111111000011";
WHEN "0111111" => memoryC0_uid235_exp10TabGen_q <= "001101000101100100";
WHEN "1000000" => memoryC0_uid235_exp10TabGen_q <= "001101001100001001";
WHEN "1000001" => memoryC0_uid235_exp10TabGen_q <= "001101010010110001";
WHEN "1000010" => memoryC0_uid235_exp10TabGen_q <= "001101011001011100";
WHEN "1000011" => memoryC0_uid235_exp10TabGen_q <= "001101100000001010";
WHEN "1000100" => memoryC0_uid235_exp10TabGen_q <= "001101100110111100";
WHEN "1000101" => memoryC0_uid235_exp10TabGen_q <= "001101101101110001";
WHEN "1000110" => memoryC0_uid235_exp10TabGen_q <= "001101110100101010";
WHEN "1000111" => memoryC0_uid235_exp10TabGen_q <= "001101111011100110";
WHEN "1001000" => memoryC0_uid235_exp10TabGen_q <= "001110000010100101";
WHEN "1001001" => memoryC0_uid235_exp10TabGen_q <= "001110001001101000";
WHEN "1001010" => memoryC0_uid235_exp10TabGen_q <= "001110010000101111";
WHEN "1001011" => memoryC0_uid235_exp10TabGen_q <= "001110010111111001";
WHEN "1001100" => memoryC0_uid235_exp10TabGen_q <= "001110011111000111";
WHEN "1001101" => memoryC0_uid235_exp10TabGen_q <= "001110100110011000";
WHEN "1001110" => memoryC0_uid235_exp10TabGen_q <= "001110101101101101";
WHEN "1001111" => memoryC0_uid235_exp10TabGen_q <= "001110110101000110";
WHEN "1010000" => memoryC0_uid235_exp10TabGen_q <= "001110111100100010";
WHEN "1010001" => memoryC0_uid235_exp10TabGen_q <= "001111000100000010";
WHEN "1010010" => memoryC0_uid235_exp10TabGen_q <= "001111001011100110";
WHEN "1010011" => memoryC0_uid235_exp10TabGen_q <= "001111010011001110";
WHEN "1010100" => memoryC0_uid235_exp10TabGen_q <= "001111011010111001";
WHEN "1010101" => memoryC0_uid235_exp10TabGen_q <= "001111100010101001";
WHEN "1010110" => memoryC0_uid235_exp10TabGen_q <= "001111101010011100";
WHEN "1010111" => memoryC0_uid235_exp10TabGen_q <= "001111110010010011";
WHEN "1011000" => memoryC0_uid235_exp10TabGen_q <= "001111111010001110";
WHEN "1011001" => memoryC0_uid235_exp10TabGen_q <= "010000000010001110";
WHEN "1011010" => memoryC0_uid235_exp10TabGen_q <= "010000001010010001";
WHEN "1011011" => memoryC0_uid235_exp10TabGen_q <= "010000010010011000";
WHEN "1011100" => memoryC0_uid235_exp10TabGen_q <= "010000011010100011";
WHEN "1011101" => memoryC0_uid235_exp10TabGen_q <= "010000100010110010";
WHEN "1011110" => memoryC0_uid235_exp10TabGen_q <= "010000101011000110";
WHEN "1011111" => memoryC0_uid235_exp10TabGen_q <= "010000110011011110";
WHEN "1100000" => memoryC0_uid235_exp10TabGen_q <= "010000111011111001";
WHEN "1100001" => memoryC0_uid235_exp10TabGen_q <= "010001000100011001";
WHEN "1100010" => memoryC0_uid235_exp10TabGen_q <= "010001001100111110";
WHEN "1100011" => memoryC0_uid235_exp10TabGen_q <= "010001010101100110";
WHEN "1100100" => memoryC0_uid235_exp10TabGen_q <= "010001011110010011";
WHEN "1100101" => memoryC0_uid235_exp10TabGen_q <= "010001100111000101";
WHEN "1100110" => memoryC0_uid235_exp10TabGen_q <= "010001101111111010";
WHEN "1100111" => memoryC0_uid235_exp10TabGen_q <= "010001111000110101";
WHEN "1101000" => memoryC0_uid235_exp10TabGen_q <= "010010000001110011";
WHEN "1101001" => memoryC0_uid235_exp10TabGen_q <= "010010001010110110";
WHEN "1101010" => memoryC0_uid235_exp10TabGen_q <= "010010010011111110";
WHEN "1101011" => memoryC0_uid235_exp10TabGen_q <= "010010011101001010";
WHEN "1101100" => memoryC0_uid235_exp10TabGen_q <= "010010100110011011";
WHEN "1101101" => memoryC0_uid235_exp10TabGen_q <= "010010101111110001";
WHEN "1101110" => memoryC0_uid235_exp10TabGen_q <= "010010111001001011";
WHEN "1101111" => memoryC0_uid235_exp10TabGen_q <= "010011000010101010";
WHEN "1110000" => memoryC0_uid235_exp10TabGen_q <= "010011001100001110";
WHEN "1110001" => memoryC0_uid235_exp10TabGen_q <= "010011010101110110";
WHEN "1110010" => memoryC0_uid235_exp10TabGen_q <= "010011011111100100";
WHEN "1110011" => memoryC0_uid235_exp10TabGen_q <= "010011101001010110";
WHEN "1110100" => memoryC0_uid235_exp10TabGen_q <= "010011110011001101";
WHEN "1110101" => memoryC0_uid235_exp10TabGen_q <= "010011111101001001";
WHEN "1110110" => memoryC0_uid235_exp10TabGen_q <= "010100000111001010";
WHEN "1110111" => memoryC0_uid235_exp10TabGen_q <= "010100010001010000";
WHEN "1111000" => memoryC0_uid235_exp10TabGen_q <= "010100011011011100";
WHEN "1111001" => memoryC0_uid235_exp10TabGen_q <= "010100100101101100";
WHEN "1111010" => memoryC0_uid235_exp10TabGen_q <= "010100110000000001";
WHEN "1111011" => memoryC0_uid235_exp10TabGen_q <= "010100111010011100";
WHEN "1111100" => memoryC0_uid235_exp10TabGen_q <= "010101000100111100";
WHEN "1111101" => memoryC0_uid235_exp10TabGen_q <= "010101001111100001";
WHEN "1111110" => memoryC0_uid235_exp10TabGen_q <= "010101011010001011";
WHEN "1111111" => memoryC0_uid235_exp10TabGen_q <= "010101100100111011";
WHEN OTHERS =>
memoryC0_uid235_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor(LOGICAL,1133)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_b <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_q <= not (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_a or ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_b);
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena(REG,1134)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_q = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd(LOGICAL,1135)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_a <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_b <= en;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_a and ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_b;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem(DUALMEM,1124)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ia <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 21,
width_b => 7,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ia
);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_iq(6 downto 0);
--reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0(REG,377)@36
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid234_exp10TabGen(LOOKUP,233)@37
memoryC0_uid234_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid234_exp10TabGen_q <= "0000000000000000000000000000000000000100";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC0_uid234_exp10TabGen_q <= "0000000000000000000000000000000000000100";
WHEN "0000001" => memoryC0_uid234_exp10TabGen_q <= "0000000010101011000000000010001000110010";
WHEN "0000010" => memoryC0_uid234_exp10TabGen_q <= "0000010101011010101011101111000111001101";
WHEN "0000011" => memoryC0_uid234_exp10TabGen_q <= "0001001000011011001000001000011011101101";
WHEN "0000100" => memoryC0_uid234_exp10TabGen_q <= "0010101100000000100010010011111101101001";
WHEN "0000101" => memoryC0_uid234_exp10TabGen_q <= "0101010000100111010011100000111110110000";
WHEN "0000110" => memoryC0_uid234_exp10TabGen_q <= "1001000110110100000101001111010001100010";
WHEN "0000111" => memoryC0_uid234_exp10TabGen_q <= "1110011111010011110101011000010011101101";
WHEN "0001000" => memoryC0_uid234_exp10TabGen_q <= "0101101010111011111010011010011101110000";
WHEN "0001001" => memoryC0_uid234_exp10TabGen_q <= "1110111010101010000111100110011000101011";
WHEN "0001010" => memoryC0_uid234_exp10TabGen_q <= "1010011111100100110001001110011010110110";
WHEN "0001011" => memoryC0_uid234_exp10TabGen_q <= "1000101010111010110000111000001101001101";
WHEN "0001100" => memoryC0_uid234_exp10TabGen_q <= "1001101110000011101001110000011001101111";
WHEN "0001101" => memoryC0_uid234_exp10TabGen_q <= "1101111010011111101101000000100100010110";
WHEN "0001110" => memoryC0_uid234_exp10TabGen_q <= "0101100001110111111110000111001111001110";
WHEN "0001111" => memoryC0_uid234_exp10TabGen_q <= "0000110101111110010111010010001011110111";
WHEN "0010000" => memoryC0_uid234_exp10TabGen_q <= "0000001000101101101101111010111001101100";
WHEN "0010001" => memoryC0_uid234_exp10TabGen_q <= "0011101100001001110111000101010011011100";
WHEN "0010010" => memoryC0_uid234_exp10TabGen_q <= "1011110010011111101100000000101100100101";
WHEN "0010011" => memoryC0_uid234_exp10TabGen_q <= "1000101110000101001110101010111111110000";
WHEN "0010100" => memoryC0_uid234_exp10TabGen_q <= "1010110001011001101110010110001111001110";
WHEN "0010101" => memoryC0_uid234_exp10TabGen_q <= "0010001111000101101100010000011000111110";
WHEN "0010110" => memoryC0_uid234_exp10TabGen_q <= "1111011001111011000000001101011110111100";
WHEN "0010111" => memoryC0_uid234_exp10TabGen_q <= "0010100100110100111101010100000101001100";
WHEN "0011000" => memoryC0_uid234_exp10TabGen_q <= "1100000010111000010110101100000110101101";
WHEN "0011001" => memoryC0_uid234_exp10TabGen_q <= "1100000111010011100100010000000010010110";
WHEN "0011010" => memoryC0_uid234_exp10TabGen_q <= "0011000101011110100111100000100000110111";
WHEN "0011011" => memoryC0_uid234_exp10TabGen_q <= "0001010000111011010000011010010101011000";
WHEN "0011100" => memoryC0_uid234_exp10TabGen_q <= "0110111101010101000010001110111001100001";
WHEN "0011101" => memoryC0_uid234_exp10TabGen_q <= "0100011110100001011000011111000110010100";
WHEN "0011110" => memoryC0_uid234_exp10TabGen_q <= "1010001000011111101011111000101011001011";
WHEN "0011111" => memoryC0_uid234_exp10TabGen_q <= "1000001111011001010111010110000100001011";
WHEN "0100000" => memoryC0_uid234_exp10TabGen_q <= "1111000111100001111101000000110000110111";
WHEN "0100001" => memoryC0_uid234_exp10TabGen_q <= "1111000101010111001011010110001100111110";
WHEN "0100010" => memoryC0_uid234_exp10TabGen_q <= "1000011101100001000010001111001100000101";
WHEN "0100011" => memoryC0_uid234_exp10TabGen_q <= "1011100100110001111000001001111001101100";
WHEN "0100100" => memoryC0_uid234_exp10TabGen_q <= "1000110000000110011111010110011110111111";
WHEN "0100101" => memoryC0_uid234_exp10TabGen_q <= "0000010100100110001011000110001111100010";
WHEN "0100110" => memoryC0_uid234_exp10TabGen_q <= "0010100111100010110100111101011110000101";
WHEN "0100111" => memoryC0_uid234_exp10TabGen_q <= "1111111110011001000010000111111011001111";
WHEN "0101000" => memoryC0_uid234_exp10TabGen_q <= "1000101110110000001000101111111110101110";
WHEN "0101001" => memoryC0_uid234_exp10TabGen_q <= "1101001110011010010101011000011101001000";
WHEN "0101010" => memoryC0_uid234_exp10TabGen_q <= "1101110011010100110000011001001011000110";
WHEN "0101011" => memoryC0_uid234_exp10TabGen_q <= "1010110011100111100011011110001111100111";
WHEN "0101100" => memoryC0_uid234_exp10TabGen_q <= "0100100101100101111111001010000110011010";
WHEN "0101101" => memoryC0_uid234_exp10TabGen_q <= "1011011111101110100000011010010100011000";
WHEN "0101110" => memoryC0_uid234_exp10TabGen_q <= "1111111000101010110110001111001110110010";
WHEN "0101111" => memoryC0_uid234_exp10TabGen_q <= "0010000111010000000111010110010111001101";
WHEN "0110000" => memoryC0_uid234_exp10TabGen_q <= "0010100010011110110111110111101101010111";
WHEN "0110001" => memoryC0_uid234_exp10TabGen_q <= "0001100001100011001111000101111000001011";
WHEN "0110010" => memoryC0_uid234_exp10TabGen_q <= "1111011011110100111101010001000111110011";
WHEN "0110011" => memoryC0_uid234_exp10TabGen_q <= "1100101000110111100001011101010001101111";
WHEN "0110100" => memoryC0_uid234_exp10TabGen_q <= "1001100000011010001111011010101000110010";
WHEN "0110101" => memoryC0_uid234_exp10TabGen_q <= "0110011010011000010101100001110010000100";
WHEN "0110110" => memoryC0_uid234_exp10TabGen_q <= "0011101110111001000010110010011000101110";
WHEN "0110111" => memoryC0_uid234_exp10TabGen_q <= "0001110110001111101100110101000001110111";
WHEN "0111000" => memoryC0_uid234_exp10TabGen_q <= "0001001000111011110110000000000010000011";
WHEN "0111001" => memoryC0_uid234_exp10TabGen_q <= "0001111111101001010011011111010101111111";
WHEN "0111010" => memoryC0_uid234_exp10TabGen_q <= "0100110011010000010011011111100000000010";
WHEN "0111011" => memoryC0_uid234_exp10TabGen_q <= "1001111100110101100011011011101011110001";
WHEN "0111100" => memoryC0_uid234_exp10TabGen_q <= "0001110101101010010110001110111001100101";
WHEN "0111101" => memoryC0_uid234_exp10TabGen_q <= "1100110111001100101010101000010011011101";
WHEN "0111110" => memoryC0_uid234_exp10TabGen_q <= "1011011011000111010001100010101100110111";
WHEN "0111111" => memoryC0_uid234_exp10TabGen_q <= "1101111011010001110100011111001111000001";
WHEN "1000000" => memoryC0_uid234_exp10TabGen_q <= "0100110001110000111100000011010011100010";
WHEN "1000001" => memoryC0_uid234_exp10TabGen_q <= "0000011000110110010110011001101110100101";
WHEN "1000010" => memoryC0_uid234_exp10TabGen_q <= "0001001011000000111101110111001010100111";
WHEN "1000011" => memoryC0_uid234_exp10TabGen_q <= "0111100010111100111111100001110111000101";
WHEN "1000100" => memoryC0_uid234_exp10TabGen_q <= "0011111011100100000001111100101011111001";
WHEN "1000101" => memoryC0_uid234_exp10TabGen_q <= "0110101111111101001011110101100011000111";
WHEN "1000110" => memoryC0_uid234_exp10TabGen_q <= "0000011011011101001010110111001010110011";
WHEN "1000111" => memoryC0_uid234_exp10TabGen_q <= "0001011001100110011010011110010000101001";
WHEN "1001000" => memoryC0_uid234_exp10TabGen_q <= "1010000110001001001010110010001000110110";
WHEN "1001001" => memoryC0_uid234_exp10TabGen_q <= "1010111101000011100111100000110010011010";
WHEN "1001010" => memoryC0_uid234_exp10TabGen_q <= "0100011010100001111110111110011010001000";
WHEN "1001011" => memoryC0_uid234_exp10TabGen_q <= "0110111010111110101001001000011110010111";
WHEN "1001100" => memoryC0_uid234_exp10TabGen_q <= "0010111011000010001110101100010101001010";
WHEN "1001101" => memoryC0_uid234_exp10TabGen_q <= "1000110111100011110000010001010110100101";
WHEN "1001110" => memoryC0_uid234_exp10TabGen_q <= "1001001101101000101101100110101101000000";
WHEN "1001111" => memoryC0_uid234_exp10TabGen_q <= "0100011010100101001100110100101101001110";
WHEN "1010000" => memoryC0_uid234_exp10TabGen_q <= "1010111011111100000001110001111000000111";
WHEN "1010001" => memoryC0_uid234_exp10TabGen_q <= "1101001111011110110101011011100111110000";
WHEN "1010010" => memoryC0_uid234_exp10TabGen_q <= "1011110011001110001101010010101001110110";
WHEN "1010011" => memoryC0_uid234_exp10TabGen_q <= "0111000101011001110010111011001001001100";
WHEN "1010100" => memoryC0_uid234_exp10TabGen_q <= "1111100100100000011011100000101000010100";
WHEN "1010101" => memoryC0_uid234_exp10TabGen_q <= "0101101111010000001111011101101110110110";
WHEN "1010110" => memoryC0_uid234_exp10TabGen_q <= "1010000100100110110010000111101011110111";
WHEN "1010111" => memoryC0_uid234_exp10TabGen_q <= "1101000011110001001001011101101110110011";
WHEN "1011000" => memoryC0_uid234_exp10TabGen_q <= "1111001100001100000101111100011001001001";
WHEN "1011001" => memoryC0_uid234_exp10TabGen_q <= "0000111101100100001010010100101010110000";
WHEN "1011010" => memoryC0_uid234_exp10TabGen_q <= "0010110111110101110011100111001010101000";
WHEN "1011011" => memoryC0_uid234_exp10TabGen_q <= "0101011011001101100001000011001110011011";
WHEN "1011100" => memoryC0_uid234_exp10TabGen_q <= "1001001000000111111100001010000010010111";
WHEN "1011101" => memoryC0_uid234_exp10TabGen_q <= "1110011111010010000000110101110011110001";
WHEN "1011110" => memoryC0_uid234_exp10TabGen_q <= "0110000001101001000101100101000000010001";
WHEN "1011111" => memoryC0_uid234_exp10TabGen_q <= "0000010000011011000011101001101011100110";
WHEN "1100000" => memoryC0_uid234_exp10TabGen_q <= "1101101101000110011111011100111110000000";
WHEN "1100001" => memoryC0_uid234_exp10TabGen_q <= "1110111001011010110000110110101101100101";
WHEN "1100010" => memoryC0_uid234_exp10TabGen_q <= "0100010111011000001011101001010100011100";
WHEN "1100011" => memoryC0_uid234_exp10TabGen_q <= "1110101001010000001000000001110101110001";
WHEN "1100100" => memoryC0_uid234_exp10TabGen_q <= "1110010001100101001011001100010100000101";
WHEN "1100101" => memoryC0_uid234_exp10TabGen_q <= "0011110011001011001111111100011010101110";
WHEN "1100110" => memoryC0_uid234_exp10TabGen_q <= "1111110001000111101111011010011100101111";
WHEN "1100111" => memoryC0_uid234_exp10TabGen_q <= "0010101110110001101001110100101011010100";
WHEN "1101000" => memoryC0_uid234_exp10TabGen_q <= "1101001111110001101111010101000110000100";
WHEN "1101001" => memoryC0_uid234_exp10TabGen_q <= "1111111000000010101000111011100111001100";
WHEN "1101010" => memoryC0_uid234_exp10TabGen_q <= "1011001011110001000001011100101101111110";
WHEN "1101011" => memoryC0_uid234_exp10TabGen_q <= "1111101111011011101110100100101001101011";
WHEN "1101100" => memoryC0_uid234_exp10TabGen_q <= "1110000111110011111001111111000111000101";
WHEN "1101101" => memoryC0_uid234_exp10TabGen_q <= "0110111001111101001010100011100011001011";
WHEN "1101110" => memoryC0_uid234_exp10TabGen_q <= "1010101011001101101101100110000101000011";
WHEN "1101111" => memoryC0_uid234_exp10TabGen_q <= "1010000001001110100000001101000001011001";
WHEN "1110000" => memoryC0_uid234_exp10TabGen_q <= "0101100001111011011000101011001001111110";
WHEN "1110001" => memoryC0_uid234_exp10TabGen_q <= "1101110011100011001111111110101011011010";
WHEN "1110010" => memoryC0_uid234_exp10TabGen_q <= "0011011100101000001011010100111011101001";
WHEN "1110011" => memoryC0_uid234_exp10TabGen_q <= "0111000011111111100101110010111011011000";
WHEN "1110100" => memoryC0_uid234_exp10TabGen_q <= "1001010000110010011010000010101101001001";
WHEN "1110101" => memoryC0_uid234_exp10TabGen_q <= "1010101010011101001100000101100100000010";
WHEN "1110110" => memoryC0_uid234_exp10TabGen_q <= "1011111000110000010011001011001101000100";
WHEN "1110111" => memoryC0_uid234_exp10TabGen_q <= "1101100011110000000011101101110101000101";
WHEN "1111000" => memoryC0_uid234_exp10TabGen_q <= "0000010011110100111001010011001110000110";
WHEN "1111001" => memoryC0_uid234_exp10TabGen_q <= "0100110001101011100000110010110110011110";
WHEN "1111010" => memoryC0_uid234_exp10TabGen_q <= "1011100110010101000010100001000100001101";
WHEN "1111011" => memoryC0_uid234_exp10TabGen_q <= "0101011011000111001100011111010111010111";
WHEN "1111100" => memoryC0_uid234_exp10TabGen_q <= "0010111001101100011100110001110101101101";
WHEN "1111101" => memoryC0_uid234_exp10TabGen_q <= "0100101100000100001011111001110010011111";
WHEN "1111110" => memoryC0_uid234_exp10TabGen_q <= "1011011100100010110111010101100100101111";
WHEN "1111111" => memoryC0_uid234_exp10TabGen_q <= "0111110101110010001100000101101110111100";
WHEN OTHERS =>
memoryC0_uid234_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--os_uid236_exp10TabGen(BITJOIN,235)@38
os_uid236_exp10TabGen_q <= memoryC0_uid235_exp10TabGen_q & memoryC0_uid234_exp10TabGen_q;
--rndBit_uid275_exp10PolyEval(CONSTANT,274)
rndBit_uid275_exp10PolyEval_q <= "001";
--cIncludingRoundingBit_uid276_exp10PolyEval(BITJOIN,275)@38
cIncludingRoundingBit_uid276_exp10PolyEval_q <= os_uid236_exp10TabGen_q & rndBit_uid275_exp10PolyEval_q;
--reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0(REG,413)@38
reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q <= cIncludingRoundingBit_uid276_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid277_exp10PolyEval(ADD,276)@39
ts5_uid277_exp10PolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q);
ts5_uid277_exp10PolyEval_b <= STD_LOGIC_VECTOR((61 downto 55 => reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q(54)) & reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q);
ts5_uid277_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid277_exp10PolyEval_a) + SIGNED(ts5_uid277_exp10PolyEval_b));
ts5_uid277_exp10PolyEval_q <= ts5_uid277_exp10PolyEval_o(61 downto 0);
--s5_uid278_exp10PolyEval(BITSELECT,277)@39
s5_uid278_exp10PolyEval_in <= ts5_uid277_exp10PolyEval_q;
s5_uid278_exp10PolyEval_b <= s5_uid278_exp10PolyEval_in(61 downto 1);
--peORExpInc_uid68_fpExpETest(BITSELECT,67)@39
peORExpInc_uid68_fpExpETest_in <= s5_uid278_exp10PolyEval_b(58 downto 0);
peORExpInc_uid68_fpExpETest_b <= peORExpInc_uid68_fpExpETest_in(58 downto 58);
--reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1(REG,415)@39
reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q <= peORExpInc_uid68_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--cstBias_uid8_fpExpETest(CONSTANT,7)
cstBias_uid8_fpExpETest_q <= "01111111111";
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor(LOGICAL,911)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_b <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_q <= not (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_a or ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_b);
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top(CONSTANT,907)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top_q <= "011011";
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp(LOGICAL,908)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_a <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q);
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_q <= "1" when ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_a = ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_b else "0";
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg(REG,909)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena(REG,912)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_q = "1") THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd(LOGICAL,913)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_a <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_b <= en;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_a and ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_b;
--reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0(REG,360)@8
reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q <= ePreRnd_uid46_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg(DELAY,901)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q, xout => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt(COUNTER,903)
-- every=1, low=0, high=27, step=1, init=1
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i = 26 THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i - 27;
ELSE
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i,5));
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg(REG,904)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux(MUX,905)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s <= en;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux: PROCESS (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s, ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q, ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q;
WHEN "1" => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem(DUALMEM,902)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ia <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_aa <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ab <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 5,
numwords_a => 28,
width_b => 14,
widthad_b => 5,
numwords_b => 28,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_iq,
address_a => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_aa,
data_a => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ia
);
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_reset0 <= areset;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_iq(13 downto 0);
--expRPostBiasPreExc0_uid69_fpExpETest(ADD,68)@39
expRPostBiasPreExc0_uid69_fpExpETest_a <= STD_LOGIC_VECTOR((15 downto 14 => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q(13)) & ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q);
expRPostBiasPreExc0_uid69_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "0000" & cstBias_uid8_fpExpETest_q);
expRPostBiasPreExc0_uid69_fpExpETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostBiasPreExc0_uid69_fpExpETest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expRPostBiasPreExc0_uid69_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc0_uid69_fpExpETest_a) + SIGNED(expRPostBiasPreExc0_uid69_fpExpETest_b));
END IF;
END IF;
END PROCESS;
expRPostBiasPreExc0_uid69_fpExpETest_q <= expRPostBiasPreExc0_uid69_fpExpETest_o(14 downto 0);
--expRPostBiasPreExc_uid70_fpExpETest(ADD,69)@40
expRPostBiasPreExc_uid70_fpExpETest_a <= STD_LOGIC_VECTOR((16 downto 15 => expRPostBiasPreExc0_uid69_fpExpETest_q(14)) & expRPostBiasPreExc0_uid69_fpExpETest_q);
expRPostBiasPreExc_uid70_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000000000000" & reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q);
expRPostBiasPreExc_uid70_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid70_fpExpETest_a) + SIGNED(expRPostBiasPreExc_uid70_fpExpETest_b));
expRPostBiasPreExc_uid70_fpExpETest_q <= expRPostBiasPreExc_uid70_fpExpETest_o(15 downto 0);
--expR_uid75_fpExpETest(BITSELECT,74)@40
expR_uid75_fpExpETest_in <= expRPostBiasPreExc_uid70_fpExpETest_q(10 downto 0);
expR_uid75_fpExpETest_b <= expR_uid75_fpExpETest_in(10 downto 0);
--ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d(DELAY,509)@40
ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid75_fpExpETest_b, xout => ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid11_fpExpETest(CONSTANT,10)
cstZeroWE_uid11_fpExpETest_q <= "00000000000";
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor(LOGICAL,1002)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_b <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_q <= not (ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_a or ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_b);
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top(CONSTANT,920)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top_q <= "0100110";
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp(LOGICAL,921)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_a <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q);
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_q <= "1" when ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_a = ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_b else "0";
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg(REG,922)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena(REG,1003)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_q = "1") THEN
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd(LOGICAL,1004)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_a <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_b <= en;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_q <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_a and ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_b;
--cstAllZWF_uid16_fpExpETest(CONSTANT,15)
cstAllZWF_uid16_fpExpETest_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid23_fpExpETest(LOGICAL,22)@0
fracXIsZero_uid23_fpExpETest_a <= frac_uid22_fpExpETest_b;
fracXIsZero_uid23_fpExpETest_b <= cstAllZWF_uid16_fpExpETest_q;
fracXIsZero_uid23_fpExpETest_q <= "1" when fracXIsZero_uid23_fpExpETest_a = fracXIsZero_uid23_fpExpETest_b else "0";
--InvFracXIsZero_uid25_fpExpETest(LOGICAL,24)@0
InvFracXIsZero_uid25_fpExpETest_a <= fracXIsZero_uid23_fpExpETest_q;
InvFracXIsZero_uid25_fpExpETest_q <= not InvFracXIsZero_uid25_fpExpETest_a;
--expXIsMax_uid21_fpExpETest(LOGICAL,20)@0
expXIsMax_uid21_fpExpETest_a <= expX_uid6_fpExpETest_b;
expXIsMax_uid21_fpExpETest_b <= cstAllOWE_uid15_fpExpETest_q;
expXIsMax_uid21_fpExpETest_q <= "1" when expXIsMax_uid21_fpExpETest_a = expXIsMax_uid21_fpExpETest_b else "0";
--exc_N_uid26_fpExpETest(LOGICAL,25)@0
exc_N_uid26_fpExpETest_a <= expXIsMax_uid21_fpExpETest_q;
exc_N_uid26_fpExpETest_b <= InvFracXIsZero_uid25_fpExpETest_q;
exc_N_uid26_fpExpETest_q <= exc_N_uid26_fpExpETest_a and exc_N_uid26_fpExpETest_b;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg(DELAY,992)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid26_fpExpETest_q, xout => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt(COUNTER,916)
-- every=1, low=0, high=38, step=1, init=1
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i = 37 THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i - 38;
ELSE
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i,6));
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg(REG,917)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux(MUX,918)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s <= en;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux: PROCESS (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s, ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q, ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q)
BEGIN
CASE ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s IS
WHEN "0" => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
WHEN "1" => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem(DUALMEM,993)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ia <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_aa <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ab <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 39,
width_b => 1,
widthad_b => 6,
numwords_b => 39,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_iq,
address_a => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_aa,
data_a => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ia
);
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_q <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_iq(0 downto 0);
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor(LOGICAL,989)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_b <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_q <= not (ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_a or ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_b);
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top(CONSTANT,933)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top_q <= "0100101";
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp(LOGICAL,934)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q);
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_q <= "1" when ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_a = ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_b else "0";
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg(REG,935)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena(REG,990)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_q = "1") THEN
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd(LOGICAL,991)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_a <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_b <= en;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_q <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_a and ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_b;
--ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c(DELAY,482)@0
ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExpETest_b, xout => ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid81_fpExpETest(LOGICAL,80)@1
InvSignX_uid81_fpExpETest_a <= ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q;
InvSignX_uid81_fpExpETest_q <= not InvSignX_uid81_fpExpETest_a;
--expOvfInitial_uid41_fpExpETest(BITSELECT,40)@0
expOvfInitial_uid41_fpExpETest_in <= shiftValuePreSat_uid40_fpExpETest_q;
expOvfInitial_uid41_fpExpETest_b <= expOvfInitial_uid41_fpExpETest_in(11 downto 11);
--reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2(REG,417)@0
reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q <= expOvfInitial_uid41_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid27_fpExpETest(LOGICAL,26)@0
InvExc_N_uid27_fpExpETest_a <= exc_N_uid26_fpExpETest_q;
InvExc_N_uid27_fpExpETest_q <= not InvExc_N_uid27_fpExpETest_a;
--exc_I_uid24_fpExpETest(LOGICAL,23)@0
exc_I_uid24_fpExpETest_a <= expXIsMax_uid21_fpExpETest_q;
exc_I_uid24_fpExpETest_b <= fracXIsZero_uid23_fpExpETest_q;
exc_I_uid24_fpExpETest_q <= exc_I_uid24_fpExpETest_a and exc_I_uid24_fpExpETest_b;
--InvExc_I_uid28_fpExpETest(LOGICAL,27)@0
InvExc_I_uid28_fpExpETest_a <= exc_I_uid24_fpExpETest_q;
InvExc_I_uid28_fpExpETest_q <= not InvExc_I_uid28_fpExpETest_a;
--expXIsZero_uid19_fpExpETest(LOGICAL,18)@0
expXIsZero_uid19_fpExpETest_a <= expX_uid6_fpExpETest_b;
expXIsZero_uid19_fpExpETest_b <= cstZeroWE_uid11_fpExpETest_q;
expXIsZero_uid19_fpExpETest_q <= "1" when expXIsZero_uid19_fpExpETest_a = expXIsZero_uid19_fpExpETest_b else "0";
--InvExpXIsZero_uid29_fpExpETest(LOGICAL,28)@0
InvExpXIsZero_uid29_fpExpETest_a <= expXIsZero_uid19_fpExpETest_q;
InvExpXIsZero_uid29_fpExpETest_q <= not InvExpXIsZero_uid29_fpExpETest_a;
--exc_R_uid30_fpExpETest(LOGICAL,29)@0
exc_R_uid30_fpExpETest_a <= InvExpXIsZero_uid29_fpExpETest_q;
exc_R_uid30_fpExpETest_b <= InvExc_I_uid28_fpExpETest_q;
exc_R_uid30_fpExpETest_c <= InvExc_N_uid27_fpExpETest_q;
exc_R_uid30_fpExpETest_q_i <= exc_R_uid30_fpExpETest_a and exc_R_uid30_fpExpETest_b and exc_R_uid30_fpExpETest_c;
exc_R_uid30_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid30_fpExpETest_q, xin => exc_R_uid30_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid82_fpExpETest(LOGICAL,81)@1
regXAndExpOverflowAndPos_uid82_fpExpETest_a <= exc_R_uid30_fpExpETest_q;
regXAndExpOverflowAndPos_uid82_fpExpETest_b <= reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q;
regXAndExpOverflowAndPos_uid82_fpExpETest_c <= InvSignX_uid81_fpExpETest_q;
regXAndExpOverflowAndPos_uid82_fpExpETest_q <= regXAndExpOverflowAndPos_uid82_fpExpETest_a and regXAndExpOverflowAndPos_uid82_fpExpETest_b and regXAndExpOverflowAndPos_uid82_fpExpETest_c;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg(DELAY,979)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid82_fpExpETest_q, xout => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt(COUNTER,929)
-- every=1, low=0, high=37, step=1, init=1
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i = 36 THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i - 37;
ELSE
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i,6));
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg(REG,930)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux(MUX,931)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s <= en;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux: PROCESS (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s, ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q, ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q)
BEGIN
CASE ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s IS
WHEN "0" => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
WHEN "1" => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem(DUALMEM,980)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ia <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_iq,
address_a => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_aa,
data_a => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ia
);
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_reset0 <= areset;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_q <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_iq(0 downto 0);
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor(LOGICAL,924)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_b <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_q <= not (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_a or ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_b);
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena(REG,925)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_q = "1") THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd(LOGICAL,926)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_a <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_b <= en;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_a and ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_b;
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg(DELAY,914)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOvfInitial_uid41_fpExpETest_b, xout => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem(DUALMEM,915)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ia <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_aa <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ab <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 39,
width_b => 1,
widthad_b => 6,
numwords_b => 39,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_iq,
address_a => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_aa,
data_a => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ia
);
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_reset0 <= areset;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_iq(0 downto 0);
--InvExpOvfInitial_uid78_fpExpETest(LOGICAL,77)@41
InvExpOvfInitial_uid78_fpExpETest_a <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_q;
InvExpOvfInitial_uid78_fpExpETest_q <= not InvExpOvfInitial_uid78_fpExpETest_a;
--reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1(REG,416)@40
reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q <= expRPostBiasPreExc_uid70_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid74_fpExpETest(COMPARE,73)@41
expOvf_uid74_fpExpETest_cin <= GND_q;
expOvf_uid74_fpExpETest_a <= STD_LOGIC_VECTOR((17 downto 16 => reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q(15)) & reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q) & '0';
expOvf_uid74_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000" & cstAllOWE_uid15_fpExpETest_q) & expOvf_uid74_fpExpETest_cin(0);
expOvf_uid74_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid74_fpExpETest_a) - SIGNED(expOvf_uid74_fpExpETest_b));
expOvf_uid74_fpExpETest_n(0) <= not expOvf_uid74_fpExpETest_o(18);
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor(LOGICAL,937)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_b <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_q <= not (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_a or ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_b);
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena(REG,938)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_q = "1") THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd(LOGICAL,939)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_b <= en;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_a and ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_b;
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg(DELAY,927)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid30_fpExpETest_q, xout => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem(DUALMEM,928)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ia <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_iq,
address_a => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_aa,
data_a => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ia
);
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_reset0 <= areset;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_iq(0 downto 0);
--regInAndOvf_uid84_fpExpETest(LOGICAL,83)@41
regInAndOvf_uid84_fpExpETest_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q;
regInAndOvf_uid84_fpExpETest_b <= expOvf_uid74_fpExpETest_n;
regInAndOvf_uid84_fpExpETest_c <= InvExpOvfInitial_uid78_fpExpETest_q;
regInAndOvf_uid84_fpExpETest_q <= regInAndOvf_uid84_fpExpETest_a and regInAndOvf_uid84_fpExpETest_b and regInAndOvf_uid84_fpExpETest_c;
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor(LOGICAL,976)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_b <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_q <= not (ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_a or ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_b);
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena(REG,977)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_q = "1") THEN
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd(LOGICAL,978)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_a <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_b <= en;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_q <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_a and ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_b;
--ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a(DELAY,497)@0
ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid24_fpExpETest_q, xout => ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid86_fpExpETest(LOGICAL,85)@1
posInf_uid86_fpExpETest_a <= ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a_q;
posInf_uid86_fpExpETest_b <= InvSignX_uid81_fpExpETest_q;
posInf_uid86_fpExpETest_q <= posInf_uid86_fpExpETest_a and posInf_uid86_fpExpETest_b;
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg(DELAY,966)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => posInf_uid86_fpExpETest_q, xout => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem(DUALMEM,967)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ia <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_iq,
address_a => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_aa,
data_a => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ia
);
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_reset0 <= areset;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_q <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_iq(0 downto 0);
--excRInf_uid87_fpExpETest(LOGICAL,86)@41
excRInf_uid87_fpExpETest_a <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_q;
excRInf_uid87_fpExpETest_b <= regInAndOvf_uid84_fpExpETest_q;
excRInf_uid87_fpExpETest_c <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_q;
excRInf_uid87_fpExpETest_q <= excRInf_uid87_fpExpETest_a or excRInf_uid87_fpExpETest_b or excRInf_uid87_fpExpETest_c;
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor(LOGICAL,963)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_b <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_q <= not (ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_a or ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_b);
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena(REG,964)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_q = "1") THEN
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd(LOGICAL,965)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_a <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_b <= en;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_q <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_a and ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_b;
--negInf_uid76_fpExpETest(LOGICAL,75)@0
negInf_uid76_fpExpETest_a <= exc_I_uid24_fpExpETest_q;
negInf_uid76_fpExpETest_b <= signX_uid7_fpExpETest_b;
negInf_uid76_fpExpETest_q <= negInf_uid76_fpExpETest_a and negInf_uid76_fpExpETest_b;
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg(DELAY,953)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => negInf_uid76_fpExpETest_q, xout => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem(DUALMEM,954)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ia <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_aa <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ab <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 39,
width_b => 1,
widthad_b => 6,
numwords_b => 39,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_iq,
address_a => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_aa,
data_a => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ia
);
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_reset0 <= areset;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_q <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_iq(0 downto 0);
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor(LOGICAL,950)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_b <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_q <= not (ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_a or ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_b);
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena(REG,951)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_q = "1") THEN
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd(LOGICAL,952)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_a <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_b <= en;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_q <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_a and ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_b;
--regXAndExpOverflowAndNeg_uid77_fpExpETest(LOGICAL,76)@1
regXAndExpOverflowAndNeg_uid77_fpExpETest_a <= exc_R_uid30_fpExpETest_q;
regXAndExpOverflowAndNeg_uid77_fpExpETest_b <= reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q;
regXAndExpOverflowAndNeg_uid77_fpExpETest_c <= ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q;
regXAndExpOverflowAndNeg_uid77_fpExpETest_q <= regXAndExpOverflowAndNeg_uid77_fpExpETest_a and regXAndExpOverflowAndNeg_uid77_fpExpETest_b and regXAndExpOverflowAndNeg_uid77_fpExpETest_c;
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg(DELAY,940)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid77_fpExpETest_q, xout => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem(DUALMEM,941)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ia <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_iq,
address_a => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_aa,
data_a => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ia
);
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_reset0 <= areset;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_q <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_iq(0 downto 0);
--expUdf_uid72_fpExpETest(COMPARE,71)@41
expUdf_uid72_fpExpETest_cin <= GND_q;
expUdf_uid72_fpExpETest_a <= STD_LOGIC_VECTOR('0' & "0000000000000000" & GND_q) & '0';
expUdf_uid72_fpExpETest_b <= STD_LOGIC_VECTOR((17 downto 16 => reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q(15)) & reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q) & expUdf_uid72_fpExpETest_cin(0);
expUdf_uid72_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid72_fpExpETest_a) - SIGNED(expUdf_uid72_fpExpETest_b));
expUdf_uid72_fpExpETest_n(0) <= not expUdf_uid72_fpExpETest_o(18);
--regXAndUdf_uid79_fpExpETest(LOGICAL,78)@41
regXAndUdf_uid79_fpExpETest_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q;
regXAndUdf_uid79_fpExpETest_b <= expUdf_uid72_fpExpETest_n;
regXAndUdf_uid79_fpExpETest_c <= InvExpOvfInitial_uid78_fpExpETest_q;
regXAndUdf_uid79_fpExpETest_q <= regXAndUdf_uid79_fpExpETest_a and regXAndUdf_uid79_fpExpETest_b and regXAndUdf_uid79_fpExpETest_c;
--excRZero_uid80_fpExpETest(LOGICAL,79)@41
excRZero_uid80_fpExpETest_a <= regXAndUdf_uid79_fpExpETest_q;
excRZero_uid80_fpExpETest_b <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_q;
excRZero_uid80_fpExpETest_c <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_q;
excRZero_uid80_fpExpETest_q <= excRZero_uid80_fpExpETest_a or excRZero_uid80_fpExpETest_b or excRZero_uid80_fpExpETest_c;
--concExc_uid88_fpExpETest(BITJOIN,87)@41
concExc_uid88_fpExpETest_q <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_q & excRInf_uid87_fpExpETest_q & excRZero_uid80_fpExpETest_q;
--reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0(REG,420)@41
reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q <= concExc_uid88_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid89_fpExpETest(LOOKUP,88)@42
excREnc_uid89_fpExpETest: PROCESS (reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q) IS
WHEN "000" => excREnc_uid89_fpExpETest_q <= "01";
WHEN "001" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "010" => excREnc_uid89_fpExpETest_q <= "10";
WHEN "011" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "100" => excREnc_uid89_fpExpETest_q <= "11";
WHEN "101" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "110" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "111" => excREnc_uid89_fpExpETest_q <= "00";
WHEN OTHERS =>
excREnc_uid89_fpExpETest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid97_fpExpETest(MUX,96)@42
expRPostExc_uid97_fpExpETest_s <= excREnc_uid89_fpExpETest_q;
expRPostExc_uid97_fpExpETest: PROCESS (expRPostExc_uid97_fpExpETest_s, en, cstZeroWE_uid11_fpExpETest_q, ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q, cstAllOWE_uid15_fpExpETest_q, cstAllOWE_uid15_fpExpETest_q)
BEGIN
CASE expRPostExc_uid97_fpExpETest_s IS
WHEN "00" => expRPostExc_uid97_fpExpETest_q <= cstZeroWE_uid11_fpExpETest_q;
WHEN "01" => expRPostExc_uid97_fpExpETest_q <= ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q;
WHEN "10" => expRPostExc_uid97_fpExpETest_q <= cstAllOWE_uid15_fpExpETest_q;
WHEN "11" => expRPostExc_uid97_fpExpETest_q <= cstAllOWE_uid15_fpExpETest_q;
WHEN OTHERS => expRPostExc_uid97_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid90_fpExpETest(CONSTANT,89)
oneFracRPostExc2_uid90_fpExpETest_q <= "0000000000000000000000000000000000000000000000000001";
--peOR_uid67_fpExpETest(BITSELECT,66)@39
peOR_uid67_fpExpETest_in <= s5_uid278_exp10PolyEval_b(57 downto 0);
peOR_uid67_fpExpETest_b <= peOR_uid67_fpExpETest_in(57 downto 5);
--fracR_uid71_fpExpETest(BITSELECT,70)@39
fracR_uid71_fpExpETest_in <= peOR_uid67_fpExpETest_b(51 downto 0);
fracR_uid71_fpExpETest_b <= fracR_uid71_fpExpETest_in(51 downto 0);
--ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg(DELAY,1005)
ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracR_uid71_fpExpETest_b, xout => ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d(DELAY,507)@39
ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg_q, xout => ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid93_fpExpETest(MUX,92)@42
fracRPostExc_uid93_fpExpETest_s <= excREnc_uid89_fpExpETest_q;
fracRPostExc_uid93_fpExpETest: PROCESS (fracRPostExc_uid93_fpExpETest_s, en, cstAllZWF_uid16_fpExpETest_q, ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q, cstAllZWF_uid16_fpExpETest_q, oneFracRPostExc2_uid90_fpExpETest_q)
BEGIN
CASE fracRPostExc_uid93_fpExpETest_s IS
WHEN "00" => fracRPostExc_uid93_fpExpETest_q <= cstAllZWF_uid16_fpExpETest_q;
WHEN "01" => fracRPostExc_uid93_fpExpETest_q <= ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q;
WHEN "10" => fracRPostExc_uid93_fpExpETest_q <= cstAllZWF_uid16_fpExpETest_q;
WHEN "11" => fracRPostExc_uid93_fpExpETest_q <= oneFracRPostExc2_uid90_fpExpETest_q;
WHEN OTHERS => fracRPostExc_uid93_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RExpE_uid98_fpExpETest(BITJOIN,97)@42
RExpE_uid98_fpExpETest_q <= GND_q & expRPostExc_uid97_fpExpETest_q & fracRPostExc_uid93_fpExpETest_q;
--xOut(GPOUT,4)@42
q <= RExpE_uid98_fpExpETest_q;
end normal;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_exp_double_s5.vhd | 10 | 750433 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_double_s5
-- VHDL created on Thu Apr 11 10:14:45 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid8_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid11_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstZeroWEP1_uid12_fpExpETest_q : std_logic_vector (11 downto 0);
signal cstBiasPWE_uid13_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExpETest_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid15_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid16_fpExpETest_q : std_logic_vector (51 downto 0);
signal exc_R_uid30_fpExpETest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_q : std_logic_vector(0 downto 0);
signal zY_uid60_fpExpETest_q : std_logic_vector (54 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_a : std_logic_vector(15 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_b : std_logic_vector(15 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_o : std_logic_vector (15 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_q : std_logic_vector (14 downto 0);
signal oneFracRPostExc2_uid90_fpExpETest_q : std_logic_vector (51 downto 0);
signal p8_uid109_constMult_q : std_logic_vector(61 downto 0);
signal p6_uid111_constMult_q : std_logic_vector(49 downto 0);
signal p4_uid113_constMult_q : std_logic_vector(37 downto 0);
signal p2_uid115_constMult_q : std_logic_vector(25 downto 0);
signal lev1_a0_uid118_constMult_a : std_logic_vector(63 downto 0);
signal lev1_a0_uid118_constMult_b : std_logic_vector(63 downto 0);
signal lev1_a0_uid118_constMult_o : std_logic_vector (63 downto 0);
signal lev1_a0_uid118_constMult_q : std_logic_vector (62 downto 0);
signal lev1_a2_uid120_constMult_a : std_logic_vector(38 downto 0);
signal lev1_a2_uid120_constMult_b : std_logic_vector(38 downto 0);
signal lev1_a2_uid120_constMult_o : std_logic_vector (38 downto 0);
signal lev1_a2_uid120_constMult_q : std_logic_vector (38 downto 0);
signal lev2_a0_uid122_constMult_a : std_logic_vector(64 downto 0);
signal lev2_a0_uid122_constMult_b : std_logic_vector(64 downto 0);
signal lev2_a0_uid122_constMult_o : std_logic_vector (64 downto 0);
signal lev2_a0_uid122_constMult_q : std_logic_vector (63 downto 0);
signal lev3_a0_uid124_constMult_a : std_logic_vector(65 downto 0);
signal lev3_a0_uid124_constMult_b : std_logic_vector(65 downto 0);
signal lev3_a0_uid124_constMult_o : std_logic_vector (65 downto 0);
signal lev3_a0_uid124_constMult_q : std_logic_vector (64 downto 0);
signal z_uid129_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (31 downto 0);
signal z_uid133_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(68 downto 0);
signal z_uid141_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(7 downto 0);
signal z_uid145_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(15 downto 0);
signal z_uid149_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(23 downto 0);
signal z_uid155_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(1 downto 0);
signal z_uid159_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(3 downto 0);
signal z_uid163_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(0 downto 0);
signal p2_uid179_constMult_q : std_logic_vector(76 downto 0);
signal lev1_a0_uid182_constMult_a : std_logic_vector(78 downto 0);
signal lev1_a0_uid182_constMult_b : std_logic_vector(78 downto 0);
signal lev1_a0_uid182_constMult_o : std_logic_vector (78 downto 0);
signal lev1_a0_uid182_constMult_q : std_logic_vector (77 downto 0);
signal rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(65 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(23 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid234_exp10TabGen_q : std_logic_vector(39 downto 0);
signal memoryC0_uid235_exp10TabGen_q : std_logic_vector(17 downto 0);
signal memoryC1_uid237_exp10TabGen_q : std_logic_vector(39 downto 0);
signal memoryC1_uid238_exp10TabGen_q : std_logic_vector(10 downto 0);
signal memoryC2_uid240_exp10TabGen_q : std_logic_vector(39 downto 0);
signal memoryC2_uid241_exp10TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid243_exp10TabGen_q : std_logic_vector(34 downto 0);
signal memoryC4_uid245_exp10TabGen_q : std_logic_vector(24 downto 0);
signal memoryC5_uid247_exp10TabGen_q : std_logic_vector(15 downto 0);
signal rndBit_uid263_exp10PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid275_exp10PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_s1 : std_logic_vector (31 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_pr : SIGNED (32 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_q : std_logic_vector (31 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_a : std_logic_vector (24 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_s1 : std_logic_vector (51 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_pr : SIGNED (52 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_q : std_logic_vector (51 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid332_pT5_uid274_exp10PolyEval_pr: signal is "logic";
signal sm0_uid332_pT5_uid274_exp10PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s_type;
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s_type;
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s_type;
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q : std_logic_vector (11 downto 0);
signal reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q : std_logic_vector (13 downto 0);
signal reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q : std_logic_vector (1 downto 0);
signal reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q : std_logic_vector (73 downto 0);
signal reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q : std_logic_vector (74 downto 0);
signal reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q : std_logic_vector (54 downto 0);
signal reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q : std_logic_vector (24 downto 0);
signal reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q : std_logic_vector (36 downto 0);
signal reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q : std_logic_vector (60 downto 0);
signal reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q : std_logic_vector (15 downto 0);
signal reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q : std_logic_vector (2 downto 0);
signal ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a_q : std_logic_vector (54 downto 0);
signal ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a_q : std_logic_vector (0 downto 0);
signal ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q : std_logic_vector (51 downto 0);
signal ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q : std_logic_vector (10 downto 0);
signal ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (52 downto 0);
signal ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (44 downto 0);
signal ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (66 downto 0);
signal ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (64 downto 0);
signal ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (62 downto 0);
signal ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (57 downto 0);
signal ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (49 downto 0);
signal ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (41 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (63 downto 0);
signal ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (61 downto 0);
signal ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (59 downto 0);
signal ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a_q : std_logic_vector (6 downto 0);
signal ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a_q : std_logic_vector (0 downto 0);
signal ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a_q : std_logic_vector (1 downto 0);
signal ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg_q : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq : std_logic;
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top_q : std_logic_vector (2 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q : signal is true;
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg_q : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq : std_logic;
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq : std_logic;
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_reset0 : std_logic;
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q : signal is true;
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg_q : std_logic_vector (51 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg_q : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ia : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_iq : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_q : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q : signal is true;
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq : std_logic;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q : signal is true;
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg_q : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ia : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_iq : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_q : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid42_fpExpETest_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid42_fpExpETest_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid42_fpExpETest_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid42_fpExpETest_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid42_fpExpETest_n : std_logic_vector (0 downto 0);
signal expUdf_uid72_fpExpETest_a : std_logic_vector(18 downto 0);
signal expUdf_uid72_fpExpETest_b : std_logic_vector(18 downto 0);
signal expUdf_uid72_fpExpETest_o : std_logic_vector (18 downto 0);
signal expUdf_uid72_fpExpETest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid72_fpExpETest_n : std_logic_vector (0 downto 0);
signal expOvf_uid74_fpExpETest_a : std_logic_vector(18 downto 0);
signal expOvf_uid74_fpExpETest_b : std_logic_vector(18 downto 0);
signal expOvf_uid74_fpExpETest_o : std_logic_vector (18 downto 0);
signal expOvf_uid74_fpExpETest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid74_fpExpETest_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal oFracXZwE_uid48_fpExpETest_q : std_logic_vector (65 downto 0);
signal InvExpOvfInitial_uid78_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid78_fpExpETest_q : std_logic_vector(0 downto 0);
signal InvSignX_uid81_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid81_fpExpETest_q : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal expX_uid6_fpExpETest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExpETest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExpETest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExpETest_b : std_logic_vector (0 downto 0);
signal frac_uid22_fpExpETest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpExpETest_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid19_fpExpETest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpExpETest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpExpETest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpExpETest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpExpETest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpExpETest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid23_fpExpETest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpExpETest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpExpETest_q : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpExpETest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpExpETest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpExpETest_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_q : std_logic_vector (11 downto 0);
signal shiftVal_uid44_fpExpETest_s : std_logic_vector (0 downto 0);
signal shiftVal_uid44_fpExpETest_q : std_logic_vector (6 downto 0);
signal onesCmpFxpIn_uid49_fpExpETest_a : std_logic_vector(65 downto 0);
signal onesCmpFxpIn_uid49_fpExpETest_b : std_logic_vector(65 downto 0);
signal onesCmpFxpIn_uid49_fpExpETest_q : std_logic_vector(65 downto 0);
signal fxpInExt_uid50_fpExpETest_a : std_logic_vector(67 downto 0);
signal fxpInExt_uid50_fpExpETest_b : std_logic_vector(67 downto 0);
signal fxpInExt_uid50_fpExpETest_o : std_logic_vector (67 downto 0);
signal fxpInExt_uid50_fpExpETest_q : std_logic_vector (66 downto 0);
signal yExt_uid57_fpExpETest_a : std_logic_vector(75 downto 0);
signal yExt_uid57_fpExpETest_b : std_logic_vector(75 downto 0);
signal yExt_uid57_fpExpETest_o : std_logic_vector (75 downto 0);
signal yExt_uid57_fpExpETest_q : std_logic_vector (75 downto 0);
signal yRedPostMux_uid62_fpExpETest_s : std_logic_vector (0 downto 0);
signal yRedPostMux_uid62_fpExpETest_q : std_logic_vector (54 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_a : std_logic_vector(16 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_b : std_logic_vector(16 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_o : std_logic_vector (16 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_q : std_logic_vector (15 downto 0);
signal negInf_uid76_fpExpETest_a : std_logic_vector(0 downto 0);
signal negInf_uid76_fpExpETest_b : std_logic_vector(0 downto 0);
signal negInf_uid76_fpExpETest_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_q : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_a : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_b : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_c : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_q : std_logic_vector(0 downto 0);
signal posInf_uid86_fpExpETest_a : std_logic_vector(0 downto 0);
signal posInf_uid86_fpExpETest_b : std_logic_vector(0 downto 0);
signal posInf_uid86_fpExpETest_q : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_a : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_b : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_c : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_q : std_logic_vector(0 downto 0);
signal excREnc_uid89_fpExpETest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid93_fpExpETest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid93_fpExpETest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid97_fpExpETest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid97_fpExpETest_q : std_logic_vector (10 downto 0);
signal p7_uid110_constMult_q : std_logic_vector(55 downto 0);
signal p5_uid112_constMult_q : std_logic_vector(43 downto 0);
signal p3_uid114_constMult_q : std_logic_vector(31 downto 0);
signal p1_uid116_constMult_q : std_logic_vector(19 downto 0);
signal p0_uid117_constMult_q : std_logic_vector(13 downto 0);
signal lev1_a1_uid119_constMult_a : std_logic_vector(50 downto 0);
signal lev1_a1_uid119_constMult_b : std_logic_vector(50 downto 0);
signal lev1_a1_uid119_constMult_o : std_logic_vector (50 downto 0);
signal lev1_a1_uid119_constMult_q : std_logic_vector (50 downto 0);
signal lev1_a3_uid121_constMult_a : std_logic_vector(26 downto 0);
signal lev1_a3_uid121_constMult_b : std_logic_vector(26 downto 0);
signal lev1_a3_uid121_constMult_o : std_logic_vector (26 downto 0);
signal lev1_a3_uid121_constMult_q : std_logic_vector (26 downto 0);
signal lev2_a1_uid123_constMult_a : std_logic_vector(39 downto 0);
signal lev2_a1_uid123_constMult_b : std_logic_vector(39 downto 0);
signal lev2_a1_uid123_constMult_o : std_logic_vector (39 downto 0);
signal lev2_a1_uid123_constMult_q : std_logic_vector (39 downto 0);
signal lev4_a0_uid125_constMult_a : std_logic_vector(66 downto 0);
signal lev4_a0_uid125_constMult_b : std_logic_vector(66 downto 0);
signal lev4_a0_uid125_constMult_o : std_logic_vector (66 downto 0);
signal lev4_a0_uid125_constMult_q : std_logic_vector (65 downto 0);
signal rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal p1_uid180_constMult_q : std_logic_vector(74 downto 0);
signal p0_uid181_constMult_q : std_logic_vector(68 downto 0);
signal lev2_a0_uid183_constMult_a : std_logic_vector(79 downto 0);
signal lev2_a0_uid183_constMult_b : std_logic_vector(79 downto 0);
signal lev2_a0_uid183_constMult_o : std_logic_vector (79 downto 0);
signal lev2_a0_uid183_constMult_q : std_logic_vector (78 downto 0);
signal rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal ts3_uid265_exp10PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid265_exp10PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid265_exp10PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid265_exp10PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid271_exp10PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid271_exp10PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid271_exp10PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid271_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid277_exp10PolyEval_a : std_logic_vector(61 downto 0);
signal ts5_uid277_exp10PolyEval_b : std_logic_vector(61 downto 0);
signal ts5_uid277_exp10PolyEval_o : std_logic_vector (61 downto 0);
signal ts5_uid277_exp10PolyEval_q : std_logic_vector (61 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal os_uid236_exp10TabGen_q : std_logic_vector (57 downto 0);
signal os_uid239_exp10TabGen_q : std_logic_vector (50 downto 0);
signal os_uid242_exp10TabGen_q : std_logic_vector (42 downto 0);
signal cIncludingRoundingBit_uid264_exp10PolyEval_q : std_logic_vector (44 downto 0);
signal cIncludingRoundingBit_uid270_exp10PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid276_exp10PolyEval_q : std_logic_vector (60 downto 0);
signal prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_in : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b : std_logic_vector (16 downto 0);
signal prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_in : std_logic_vector (51 downto 0);
signal prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b : std_logic_vector (27 downto 0);
signal TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b : std_logic_vector (29 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid65_fpExpETest_in : std_logic_vector (47 downto 0);
signal yPPolyEval_uid65_fpExpETest_b : std_logic_vector (47 downto 0);
signal xTop27Bits_uid303_pT4_uid268_exp10PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid303_pT4_uid268_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_a : std_logic_vector(2 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_b : std_logic_vector(2 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal concExc_uid88_fpExpETest_q : std_logic_vector (2 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid261_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT3_uid261_exp10PolyEval_b : std_logic_vector (34 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid267_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT4_uid267_exp10PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_uid32_fpExpETest_q : std_logic_vector (52 downto 0);
signal InvExpXIsZero_uid29_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpExpETest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpExpETest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpExpETest_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid41_fpExpETest_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid41_fpExpETest_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid43_fpExpETest_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid43_fpExpETest_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (0 downto 0);
signal fxpInPreAlign_uid51_fpExpETest_in : std_logic_vector (65 downto 0);
signal fxpInPreAlign_uid51_fpExpETest_b : std_logic_vector (65 downto 0);
signal YExt75_uid59_fpExpETest_in : std_logic_vector (75 downto 0);
signal YExt75_uid59_fpExpETest_b : std_logic_vector (0 downto 0);
signal yRed_uid61_fpExpETest_in : std_logic_vector (60 downto 0);
signal yRed_uid61_fpExpETest_b : std_logic_vector (54 downto 0);
signal addr_uid64_fpExpETest_in : std_logic_vector (54 downto 0);
signal addr_uid64_fpExpETest_b : std_logic_vector (6 downto 0);
signal expR_uid75_fpExpETest_in : std_logic_vector (10 downto 0);
signal expR_uid75_fpExpETest_b : std_logic_vector (10 downto 0);
signal RExpE_uid98_fpExpETest_q : std_logic_vector (63 downto 0);
signal sR_uid126_constMult_in : std_logic_vector (61 downto 0);
signal sR_uid126_constMult_b : std_logic_vector (57 downto 0);
signal RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (60 downto 0);
signal RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (52 downto 0);
signal RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (44 downto 0);
signal sR_uid184_constMult_in : std_logic_vector (76 downto 0);
signal sR_uid184_constMult_b : std_logic_vector (74 downto 0);
signal RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (57 downto 0);
signal RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (49 downto 0);
signal RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (41 downto 0);
signal s3_uid266_exp10PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid266_exp10PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid272_exp10PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid272_exp10PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid278_exp10PolyEval_in : std_logic_vector (61 downto 0);
signal s5_uid278_exp10PolyEval_b : std_logic_vector (60 downto 0);
signal lowRangeB_uid251_exp10PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid251_exp10PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid252_exp10PolyEval_in : std_logic_vector (16 downto 0);
signal highBBits_uid252_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal lowRangeB_uid257_exp10PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_exp10PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_exp10PolyEval_in : std_logic_vector (27 downto 0);
signal highBBits_uid258_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal lowRangeB_uid298_pT3_uid262_exp10PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid298_pT3_uid262_exp10PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid299_pT3_uid262_exp10PolyEval_in : std_logic_vector (29 downto 0);
signal highBBits_uid299_pT3_uid262_exp10PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid313_pT4_uid268_exp10PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid313_pT4_uid268_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid314_pT4_uid268_exp10PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid314_pT4_uid268_exp10PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid334_pT5_uid274_exp10PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid334_pT5_uid274_exp10PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid335_pT5_uid274_exp10PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid335_pT5_uid274_exp10PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (66 downto 0);
signal RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (64 downto 0);
signal RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (62 downto 0);
signal RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (67 downto 0);
signal RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (63 downto 0);
signal RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (61 downto 0);
signal RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (59 downto 0);
signal RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (64 downto 0);
signal yT1_uid249_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT1_uid249_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal yT2_uid255_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT2_uid255_exp10PolyEval_b : std_logic_vector (24 downto 0);
signal xTop27Bits_uid318_pT5_uid274_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal xBottomBits_uid322_pT5_uid274_exp10PolyEval_in : std_logic_vector (20 downto 0);
signal xBottomBits_uid322_pT5_uid274_exp10PolyEval_b : std_logic_vector (20 downto 0);
signal xTop26Bits_uid323_pT5_uid274_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid331_pT5_uid274_exp10PolyEval_in : std_logic_vector (20 downto 0);
signal sSM0W_uid331_pT5_uid274_exp10PolyEval_b : std_logic_vector (2 downto 0);
signal xTop27Bits_uid286_pT3_uid262_exp10PolyEval_in : std_logic_vector (34 downto 0);
signal xTop27Bits_uid286_pT3_uid262_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid289_pT3_uid262_exp10PolyEval_in : std_logic_vector (34 downto 0);
signal xTop18Bits_uid289_pT3_uid262_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid291_pT3_uid262_exp10PolyEval_in : std_logic_vector (7 downto 0);
signal xBottomBits_uid291_pT3_uid262_exp10PolyEval_b : std_logic_vector (7 downto 0);
signal xBottomBits_uid307_pT4_uid268_exp10PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid307_pT4_uid268_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal oFracX_uid33_fpExpETest_q : std_logic_vector (53 downto 0);
signal exc_N_uid26_fpExpETest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpExpETest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpExpETest_q : std_logic_vector(0 downto 0);
signal msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (0 downto 0);
signal X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (33 downto 0);
signal X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (1 downto 0);
signal oFracXZwE_uid39_fpExpETest_q : std_logic_vector (68 downto 0);
signal yTop27Bits_uid304_pT4_uid268_exp10PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid306_pT4_uid268_exp10PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid306_pT4_uid268_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid319_pT5_uid274_exp10PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid319_pT5_uid274_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid321_pT5_uid274_exp10PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid321_pT5_uid274_exp10PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid330_pT5_uid274_exp10PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid330_pT5_uid274_exp10PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid67_fpExpETest_in : std_logic_vector (57 downto 0);
signal peOR_uid67_fpExpETest_b : std_logic_vector (52 downto 0);
signal peORExpInc_uid68_fpExpETest_in : std_logic_vector (58 downto 0);
signal peORExpInc_uid68_fpExpETest_b : std_logic_vector (0 downto 0);
signal sumAHighB_uid253_exp10PolyEval_a : std_logic_vector(25 downto 0);
signal sumAHighB_uid253_exp10PolyEval_b : std_logic_vector(25 downto 0);
signal sumAHighB_uid253_exp10PolyEval_o : std_logic_vector (25 downto 0);
signal sumAHighB_uid253_exp10PolyEval_q : std_logic_vector (25 downto 0);
signal sumAHighB_uid259_exp10PolyEval_a : std_logic_vector(35 downto 0);
signal sumAHighB_uid259_exp10PolyEval_b : std_logic_vector(35 downto 0);
signal sumAHighB_uid259_exp10PolyEval_o : std_logic_vector (35 downto 0);
signal sumAHighB_uid259_exp10PolyEval_q : std_logic_vector (35 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_q : std_logic_vector (25 downto 0);
signal onesCmpFxpInX_uid34_fpExpETest_a : std_logic_vector(53 downto 0);
signal onesCmpFxpInX_uid34_fpExpETest_b : std_logic_vector(53 downto 0);
signal onesCmpFxpInX_uid34_fpExpETest_q : std_logic_vector(53 downto 0);
signal InvExc_N_uid27_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpExpETest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal msbx_uid128_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (0 downto 0);
signal X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (36 downto 0);
signal X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (4 downto 0);
signal fracR_uid71_fpExpETest_in : std_logic_vector (51 downto 0);
signal fracR_uid71_fpExpETest_b : std_logic_vector (51 downto 0);
signal s1_uid251_uid254_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal s2_uid257_uid260_exp10PolyEval_q : std_logic_vector (36 downto 0);
signal add0_uid298_uid301_pT3_uid262_exp10PolyEval_q : std_logic_vector (55 downto 0);
signal add0_uid313_uid316_pT4_uid268_exp10PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid334_uid337_pT5_uid274_exp10PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal fxpInExtX_uid35_fpExpETest_a : std_logic_vector(55 downto 0);
signal fxpInExtX_uid35_fpExpETest_b : std_logic_vector(55 downto 0);
signal fxpInExtX_uid35_fpExpETest_o : std_logic_vector (55 downto 0);
signal fxpInExtX_uid35_fpExpETest_q : std_logic_vector (54 downto 0);
signal rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal yTop27Bits_uid287_pT3_uid262_exp10PolyEval_in : std_logic_vector (36 downto 0);
signal yTop27Bits_uid287_pT3_uid262_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid290_pT3_uid262_exp10PolyEval_in : std_logic_vector (9 downto 0);
signal yBottomBits_uid290_pT3_uid262_exp10PolyEval_b : std_logic_vector (9 downto 0);
signal yTop18Bits_uid292_pT3_uid262_exp10PolyEval_in : std_logic_vector (36 downto 0);
signal yTop18Bits_uid292_pT3_uid262_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal R_uid302_pT3_uid262_exp10PolyEval_in : std_logic_vector (54 downto 0);
signal R_uid302_pT3_uid262_exp10PolyEval_b : std_logic_vector (36 downto 0);
signal R_uid317_pT4_uid268_exp10PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid317_pT4_uid268_exp10PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid338_pT5_uid274_exp10PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid338_pT5_uid274_exp10PolyEval_b : std_logic_vector (54 downto 0);
signal ePreRnd_uid46_fpExpETest_in : std_logic_vector (68 downto 0);
signal ePreRnd_uid46_fpExpETest_b : std_logic_vector (13 downto 0);
signal pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_q : std_logic_vector (73 downto 0);
signal fxpInPreAlign_uid36_fpExpETest_in : std_logic_vector (53 downto 0);
signal fxpInPreAlign_uid36_fpExpETest_b : std_logic_vector (53 downto 0);
signal spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval_q : std_logic_vector (10 downto 0);
signal xv0_uid176_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid176_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid177_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid177_constMult_b : std_logic_vector (5 downto 0);
signal xv2_uid178_constMult_in : std_logic_vector (13 downto 0);
signal xv2_uid178_constMult_b : std_logic_vector (1 downto 0);
signal xv0_uid100_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid100_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid101_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid101_constMult_b : std_logic_vector (5 downto 0);
signal xv2_uid102_constMult_in : std_logic_vector (17 downto 0);
signal xv2_uid102_constMult_b : std_logic_vector (5 downto 0);
signal xv3_uid103_constMult_in : std_logic_vector (23 downto 0);
signal xv3_uid103_constMult_b : std_logic_vector (5 downto 0);
signal xv4_uid104_constMult_in : std_logic_vector (29 downto 0);
signal xv4_uid104_constMult_b : std_logic_vector (5 downto 0);
signal xv5_uid105_constMult_in : std_logic_vector (35 downto 0);
signal xv5_uid105_constMult_b : std_logic_vector (5 downto 0);
signal xv6_uid106_constMult_in : std_logic_vector (41 downto 0);
signal xv6_uid106_constMult_b : std_logic_vector (5 downto 0);
signal xv7_uid107_constMult_in : std_logic_vector (47 downto 0);
signal xv7_uid107_constMult_b : std_logic_vector (5 downto 0);
signal xv8_uid108_constMult_in : std_logic_vector (53 downto 0);
signal xv8_uid108_constMult_b : std_logic_vector (5 downto 0);
signal pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_q : std_logic_vector (17 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid15_fpExpETest(CONSTANT,14)
cstAllOWE_uid15_fpExpETest_q <= "11111111111";
--zY_uid60_fpExpETest(CONSTANT,59)
zY_uid60_fpExpETest_q <= "0000000000000000000000000000000000000000000000000000000";
--signX_uid7_fpExpETest(BITSELECT,6)@0
signX_uid7_fpExpETest_in <= a;
signX_uid7_fpExpETest_b <= signX_uid7_fpExpETest_in(63 downto 63);
--frac_uid22_fpExpETest(BITSELECT,21)@0
frac_uid22_fpExpETest_in <= a(51 downto 0);
frac_uid22_fpExpETest_b <= frac_uid22_fpExpETest_in(51 downto 0);
--oFracX_uid32_uid32_fpExpETest(BITJOIN,31)@0
oFracX_uid32_uid32_fpExpETest_q <= VCC_q & frac_uid22_fpExpETest_b;
--oFracX_uid33_fpExpETest(BITJOIN,32)@0
oFracX_uid33_fpExpETest_q <= GND_q & oFracX_uid32_uid32_fpExpETest_q;
--onesCmpFxpInX_uid34_fpExpETest(LOGICAL,33)@0
onesCmpFxpInX_uid34_fpExpETest_a <= oFracX_uid33_fpExpETest_q;
onesCmpFxpInX_uid34_fpExpETest_b <= STD_LOGIC_VECTOR((53 downto 1 => signX_uid7_fpExpETest_b(0)) & signX_uid7_fpExpETest_b);
onesCmpFxpInX_uid34_fpExpETest_q <= onesCmpFxpInX_uid34_fpExpETest_a xor onesCmpFxpInX_uid34_fpExpETest_b;
--fxpInExtX_uid35_fpExpETest(ADD,34)@0
fxpInExtX_uid35_fpExpETest_a <= STD_LOGIC_VECTOR((55 downto 54 => onesCmpFxpInX_uid34_fpExpETest_q(53)) & onesCmpFxpInX_uid34_fpExpETest_q);
fxpInExtX_uid35_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000000000000000000000000000" & signX_uid7_fpExpETest_b);
fxpInExtX_uid35_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExtX_uid35_fpExpETest_a) + SIGNED(fxpInExtX_uid35_fpExpETest_b));
fxpInExtX_uid35_fpExpETest_q <= fxpInExtX_uid35_fpExpETest_o(54 downto 0);
--fxpInPreAlign_uid36_fpExpETest(BITSELECT,35)@0
fxpInPreAlign_uid36_fpExpETest_in <= fxpInExtX_uid35_fpExpETest_q(53 downto 0);
fxpInPreAlign_uid36_fpExpETest_b <= fxpInPreAlign_uid36_fpExpETest_in(53 downto 0);
--xv0_uid100_constMult(BITSELECT,99)@0
xv0_uid100_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(5 downto 0);
xv0_uid100_constMult_b <= xv0_uid100_constMult_in(5 downto 0);
--reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0(REG,350)@0
reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q <= xv0_uid100_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a(DELAY,529)@1
ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q, xout => ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid117_constMult(LOOKUP,116)@5
p0_uid117_constMult: PROCESS (ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q) IS
WHEN "000000" => p0_uid117_constMult_q <= "00000000000000";
WHEN "000001" => p0_uid117_constMult_q <= "00000010111001";
WHEN "000010" => p0_uid117_constMult_q <= "00000101110001";
WHEN "000011" => p0_uid117_constMult_q <= "00001000101010";
WHEN "000100" => p0_uid117_constMult_q <= "00001011100011";
WHEN "000101" => p0_uid117_constMult_q <= "00001110011011";
WHEN "000110" => p0_uid117_constMult_q <= "00010001010100";
WHEN "000111" => p0_uid117_constMult_q <= "00010100001101";
WHEN "001000" => p0_uid117_constMult_q <= "00010111000101";
WHEN "001001" => p0_uid117_constMult_q <= "00011001111110";
WHEN "001010" => p0_uid117_constMult_q <= "00011100110111";
WHEN "001011" => p0_uid117_constMult_q <= "00011111101111";
WHEN "001100" => p0_uid117_constMult_q <= "00100010101000";
WHEN "001101" => p0_uid117_constMult_q <= "00100101100001";
WHEN "001110" => p0_uid117_constMult_q <= "00101000011001";
WHEN "001111" => p0_uid117_constMult_q <= "00101011010010";
WHEN "010000" => p0_uid117_constMult_q <= "00101110001011";
WHEN "010001" => p0_uid117_constMult_q <= "00110001000011";
WHEN "010010" => p0_uid117_constMult_q <= "00110011111100";
WHEN "010011" => p0_uid117_constMult_q <= "00110110110101";
WHEN "010100" => p0_uid117_constMult_q <= "00111001101101";
WHEN "010101" => p0_uid117_constMult_q <= "00111100100110";
WHEN "010110" => p0_uid117_constMult_q <= "00111111011111";
WHEN "010111" => p0_uid117_constMult_q <= "01000010010111";
WHEN "011000" => p0_uid117_constMult_q <= "01000101010000";
WHEN "011001" => p0_uid117_constMult_q <= "01001000001001";
WHEN "011010" => p0_uid117_constMult_q <= "01001011000001";
WHEN "011011" => p0_uid117_constMult_q <= "01001101111010";
WHEN "011100" => p0_uid117_constMult_q <= "01010000110011";
WHEN "011101" => p0_uid117_constMult_q <= "01010011101011";
WHEN "011110" => p0_uid117_constMult_q <= "01010110100100";
WHEN "011111" => p0_uid117_constMult_q <= "01011001011101";
WHEN "100000" => p0_uid117_constMult_q <= "01011100010101";
WHEN "100001" => p0_uid117_constMult_q <= "01011111001110";
WHEN "100010" => p0_uid117_constMult_q <= "01100010000111";
WHEN "100011" => p0_uid117_constMult_q <= "01100100111111";
WHEN "100100" => p0_uid117_constMult_q <= "01100111111000";
WHEN "100101" => p0_uid117_constMult_q <= "01101010110001";
WHEN "100110" => p0_uid117_constMult_q <= "01101101101001";
WHEN "100111" => p0_uid117_constMult_q <= "01110000100010";
WHEN "101000" => p0_uid117_constMult_q <= "01110011011011";
WHEN "101001" => p0_uid117_constMult_q <= "01110110010011";
WHEN "101010" => p0_uid117_constMult_q <= "01111001001100";
WHEN "101011" => p0_uid117_constMult_q <= "01111100000101";
WHEN "101100" => p0_uid117_constMult_q <= "01111110111101";
WHEN "101101" => p0_uid117_constMult_q <= "10000001110110";
WHEN "101110" => p0_uid117_constMult_q <= "10000100101111";
WHEN "101111" => p0_uid117_constMult_q <= "10000111100111";
WHEN "110000" => p0_uid117_constMult_q <= "10001010100000";
WHEN "110001" => p0_uid117_constMult_q <= "10001101011001";
WHEN "110010" => p0_uid117_constMult_q <= "10010000010001";
WHEN "110011" => p0_uid117_constMult_q <= "10010011001010";
WHEN "110100" => p0_uid117_constMult_q <= "10010110000011";
WHEN "110101" => p0_uid117_constMult_q <= "10011000111011";
WHEN "110110" => p0_uid117_constMult_q <= "10011011110100";
WHEN "110111" => p0_uid117_constMult_q <= "10011110101101";
WHEN "111000" => p0_uid117_constMult_q <= "10100001100101";
WHEN "111001" => p0_uid117_constMult_q <= "10100100011110";
WHEN "111010" => p0_uid117_constMult_q <= "10100111010111";
WHEN "111011" => p0_uid117_constMult_q <= "10101010001111";
WHEN "111100" => p0_uid117_constMult_q <= "10101101001000";
WHEN "111101" => p0_uid117_constMult_q <= "10110000000001";
WHEN "111110" => p0_uid117_constMult_q <= "10110010111001";
WHEN "111111" => p0_uid117_constMult_q <= "10110101110010";
WHEN OTHERS =>
p0_uid117_constMult_q <= "00000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid101_constMult(BITSELECT,100)@0
xv1_uid101_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(11 downto 0);
xv1_uid101_constMult_b <= xv1_uid101_constMult_in(11 downto 6);
--ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a(DELAY,803)@0
ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 3 )
PORT MAP ( xin => xv1_uid101_constMult_b, xout => ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0(REG,349)@3
reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q <= ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p1_uid116_constMult(LOOKUP,115)@4
p1_uid116_constMult: PROCESS (reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q) IS
WHEN "000000" => p1_uid116_constMult_q <= "00000000000000000000";
WHEN "000001" => p1_uid116_constMult_q <= "00000010111000101011";
WHEN "000010" => p1_uid116_constMult_q <= "00000101110001010101";
WHEN "000011" => p1_uid116_constMult_q <= "00001000101010000000";
WHEN "000100" => p1_uid116_constMult_q <= "00001011100010101010";
WHEN "000101" => p1_uid116_constMult_q <= "00001110011011010101";
WHEN "000110" => p1_uid116_constMult_q <= "00010001010011111111";
WHEN "000111" => p1_uid116_constMult_q <= "00010100001100101010";
WHEN "001000" => p1_uid116_constMult_q <= "00010111000101010100";
WHEN "001001" => p1_uid116_constMult_q <= "00011001111101111111";
WHEN "001010" => p1_uid116_constMult_q <= "00011100110110101010";
WHEN "001011" => p1_uid116_constMult_q <= "00011111101111010100";
WHEN "001100" => p1_uid116_constMult_q <= "00100010100111111111";
WHEN "001101" => p1_uid116_constMult_q <= "00100101100000101001";
WHEN "001110" => p1_uid116_constMult_q <= "00101000011001010100";
WHEN "001111" => p1_uid116_constMult_q <= "00101011010001111110";
WHEN "010000" => p1_uid116_constMult_q <= "00101110001010101001";
WHEN "010001" => p1_uid116_constMult_q <= "00110001000011010011";
WHEN "010010" => p1_uid116_constMult_q <= "00110011111011111110";
WHEN "010011" => p1_uid116_constMult_q <= "00110110110100101001";
WHEN "010100" => p1_uid116_constMult_q <= "00111001101101010011";
WHEN "010101" => p1_uid116_constMult_q <= "00111100100101111110";
WHEN "010110" => p1_uid116_constMult_q <= "00111111011110101000";
WHEN "010111" => p1_uid116_constMult_q <= "01000010010111010011";
WHEN "011000" => p1_uid116_constMult_q <= "01000101001111111101";
WHEN "011001" => p1_uid116_constMult_q <= "01001000001000101000";
WHEN "011010" => p1_uid116_constMult_q <= "01001011000001010011";
WHEN "011011" => p1_uid116_constMult_q <= "01001101111001111101";
WHEN "011100" => p1_uid116_constMult_q <= "01010000110010101000";
WHEN "011101" => p1_uid116_constMult_q <= "01010011101011010010";
WHEN "011110" => p1_uid116_constMult_q <= "01010110100011111101";
WHEN "011111" => p1_uid116_constMult_q <= "01011001011100100111";
WHEN "100000" => p1_uid116_constMult_q <= "01011100010101010010";
WHEN "100001" => p1_uid116_constMult_q <= "01011111001101111100";
WHEN "100010" => p1_uid116_constMult_q <= "01100010000110100111";
WHEN "100011" => p1_uid116_constMult_q <= "01100100111111010010";
WHEN "100100" => p1_uid116_constMult_q <= "01100111110111111100";
WHEN "100101" => p1_uid116_constMult_q <= "01101010110000100111";
WHEN "100110" => p1_uid116_constMult_q <= "01101101101001010001";
WHEN "100111" => p1_uid116_constMult_q <= "01110000100001111100";
WHEN "101000" => p1_uid116_constMult_q <= "01110011011010100110";
WHEN "101001" => p1_uid116_constMult_q <= "01110110010011010001";
WHEN "101010" => p1_uid116_constMult_q <= "01111001001011111011";
WHEN "101011" => p1_uid116_constMult_q <= "01111100000100100110";
WHEN "101100" => p1_uid116_constMult_q <= "01111110111101010001";
WHEN "101101" => p1_uid116_constMult_q <= "10000001110101111011";
WHEN "101110" => p1_uid116_constMult_q <= "10000100101110100110";
WHEN "101111" => p1_uid116_constMult_q <= "10000111100111010000";
WHEN "110000" => p1_uid116_constMult_q <= "10001010011111111011";
WHEN "110001" => p1_uid116_constMult_q <= "10001101011000100101";
WHEN "110010" => p1_uid116_constMult_q <= "10010000010001010000";
WHEN "110011" => p1_uid116_constMult_q <= "10010011001001111010";
WHEN "110100" => p1_uid116_constMult_q <= "10010110000010100101";
WHEN "110101" => p1_uid116_constMult_q <= "10011000111011010000";
WHEN "110110" => p1_uid116_constMult_q <= "10011011110011111010";
WHEN "110111" => p1_uid116_constMult_q <= "10011110101100100101";
WHEN "111000" => p1_uid116_constMult_q <= "10100001100101001111";
WHEN "111001" => p1_uid116_constMult_q <= "10100100011101111010";
WHEN "111010" => p1_uid116_constMult_q <= "10100111010110100100";
WHEN "111011" => p1_uid116_constMult_q <= "10101010001111001111";
WHEN "111100" => p1_uid116_constMult_q <= "10101101000111111001";
WHEN "111101" => p1_uid116_constMult_q <= "10110000000000100100";
WHEN "111110" => p1_uid116_constMult_q <= "10110010111001001111";
WHEN "111111" => p1_uid116_constMult_q <= "10110101110001111001";
WHEN OTHERS =>
p1_uid116_constMult_q <= "00000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv2_uid102_constMult(BITSELECT,101)@0
xv2_uid102_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(17 downto 0);
xv2_uid102_constMult_b <= xv2_uid102_constMult_in(17 downto 12);
--ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a(DELAY,802)@0
ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => xv2_uid102_constMult_b, xout => ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0(REG,348)@2
reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q <= ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p2_uid115_constMult(LOOKUP,114)@3
p2_uid115_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p2_uid115_constMult_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q) IS
WHEN "000000" => p2_uid115_constMult_q <= "00000000000000000000000000";
WHEN "000001" => p2_uid115_constMult_q <= "00000010111000101010100100";
WHEN "000010" => p2_uid115_constMult_q <= "00000101110001010101000111";
WHEN "000011" => p2_uid115_constMult_q <= "00001000101001111111101011";
WHEN "000100" => p2_uid115_constMult_q <= "00001011100010101010001111";
WHEN "000101" => p2_uid115_constMult_q <= "00001110011011010100110010";
WHEN "000110" => p2_uid115_constMult_q <= "00010001010011111111010110";
WHEN "000111" => p2_uid115_constMult_q <= "00010100001100101001111010";
WHEN "001000" => p2_uid115_constMult_q <= "00010111000101010100011110";
WHEN "001001" => p2_uid115_constMult_q <= "00011001111101111111000001";
WHEN "001010" => p2_uid115_constMult_q <= "00011100110110101001100101";
WHEN "001011" => p2_uid115_constMult_q <= "00011111101111010100001001";
WHEN "001100" => p2_uid115_constMult_q <= "00100010100111111110101100";
WHEN "001101" => p2_uid115_constMult_q <= "00100101100000101001010000";
WHEN "001110" => p2_uid115_constMult_q <= "00101000011001010011110100";
WHEN "001111" => p2_uid115_constMult_q <= "00101011010001111110010111";
WHEN "010000" => p2_uid115_constMult_q <= "00101110001010101000111011";
WHEN "010001" => p2_uid115_constMult_q <= "00110001000011010011011111";
WHEN "010010" => p2_uid115_constMult_q <= "00110011111011111110000011";
WHEN "010011" => p2_uid115_constMult_q <= "00110110110100101000100110";
WHEN "010100" => p2_uid115_constMult_q <= "00111001101101010011001010";
WHEN "010101" => p2_uid115_constMult_q <= "00111100100101111101101110";
WHEN "010110" => p2_uid115_constMult_q <= "00111111011110101000010001";
WHEN "010111" => p2_uid115_constMult_q <= "01000010010111010010110101";
WHEN "011000" => p2_uid115_constMult_q <= "01000101001111111101011001";
WHEN "011001" => p2_uid115_constMult_q <= "01001000001000100111111100";
WHEN "011010" => p2_uid115_constMult_q <= "01001011000001010010100000";
WHEN "011011" => p2_uid115_constMult_q <= "01001101111001111101000100";
WHEN "011100" => p2_uid115_constMult_q <= "01010000110010100111101000";
WHEN "011101" => p2_uid115_constMult_q <= "01010011101011010010001011";
WHEN "011110" => p2_uid115_constMult_q <= "01010110100011111100101111";
WHEN "011111" => p2_uid115_constMult_q <= "01011001011100100111010011";
WHEN "100000" => p2_uid115_constMult_q <= "01011100010101010001110110";
WHEN "100001" => p2_uid115_constMult_q <= "01011111001101111100011010";
WHEN "100010" => p2_uid115_constMult_q <= "01100010000110100110111110";
WHEN "100011" => p2_uid115_constMult_q <= "01100100111111010001100001";
WHEN "100100" => p2_uid115_constMult_q <= "01100111110111111100000101";
WHEN "100101" => p2_uid115_constMult_q <= "01101010110000100110101001";
WHEN "100110" => p2_uid115_constMult_q <= "01101101101001010001001101";
WHEN "100111" => p2_uid115_constMult_q <= "01110000100001111011110000";
WHEN "101000" => p2_uid115_constMult_q <= "01110011011010100110010100";
WHEN "101001" => p2_uid115_constMult_q <= "01110110010011010000111000";
WHEN "101010" => p2_uid115_constMult_q <= "01111001001011111011011011";
WHEN "101011" => p2_uid115_constMult_q <= "01111100000100100101111111";
WHEN "101100" => p2_uid115_constMult_q <= "01111110111101010000100011";
WHEN "101101" => p2_uid115_constMult_q <= "10000001110101111011000110";
WHEN "101110" => p2_uid115_constMult_q <= "10000100101110100101101010";
WHEN "101111" => p2_uid115_constMult_q <= "10000111100111010000001110";
WHEN "110000" => p2_uid115_constMult_q <= "10001010011111111010110001";
WHEN "110001" => p2_uid115_constMult_q <= "10001101011000100101010101";
WHEN "110010" => p2_uid115_constMult_q <= "10010000010001001111111001";
WHEN "110011" => p2_uid115_constMult_q <= "10010011001001111010011101";
WHEN "110100" => p2_uid115_constMult_q <= "10010110000010100101000000";
WHEN "110101" => p2_uid115_constMult_q <= "10011000111011001111100100";
WHEN "110110" => p2_uid115_constMult_q <= "10011011110011111010001000";
WHEN "110111" => p2_uid115_constMult_q <= "10011110101100100100101011";
WHEN "111000" => p2_uid115_constMult_q <= "10100001100101001111001111";
WHEN "111001" => p2_uid115_constMult_q <= "10100100011101111001110011";
WHEN "111010" => p2_uid115_constMult_q <= "10100111010110100100010110";
WHEN "111011" => p2_uid115_constMult_q <= "10101010001111001110111010";
WHEN "111100" => p2_uid115_constMult_q <= "10101101000111111001011110";
WHEN "111101" => p2_uid115_constMult_q <= "10110000000000100100000010";
WHEN "111110" => p2_uid115_constMult_q <= "10110010111001001110100101";
WHEN "111111" => p2_uid115_constMult_q <= "10110101110001111001001001";
WHEN OTHERS =>
p2_uid115_constMult_q <= "00000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a3_uid121_constMult(ADD,120)@4
lev1_a3_uid121_constMult_a <= STD_LOGIC_VECTOR("0" & p2_uid115_constMult_q);
lev1_a3_uid121_constMult_b <= STD_LOGIC_VECTOR("0000000" & p1_uid116_constMult_q);
lev1_a3_uid121_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a3_uid121_constMult_a) + UNSIGNED(lev1_a3_uid121_constMult_b));
lev1_a3_uid121_constMult_q <= lev1_a3_uid121_constMult_o(26 downto 0);
--xv3_uid103_constMult(BITSELECT,102)@0
xv3_uid103_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(23 downto 0);
xv3_uid103_constMult_b <= xv3_uid103_constMult_in(23 downto 18);
--reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0(REG,347)@0
reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q <= xv3_uid103_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a(DELAY,526)@1
ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q, xout => ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p3_uid114_constMult(LOOKUP,113)@3
p3_uid114_constMult: PROCESS (ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q) IS
WHEN "000000" => p3_uid114_constMult_q <= "00000000000000000000000000000000";
WHEN "000001" => p3_uid114_constMult_q <= "00000010111000101010100011101101";
WHEN "000010" => p3_uid114_constMult_q <= "00000101110001010101000111011001";
WHEN "000011" => p3_uid114_constMult_q <= "00001000101001111111101011000110";
WHEN "000100" => p3_uid114_constMult_q <= "00001011100010101010001110110011";
WHEN "000101" => p3_uid114_constMult_q <= "00001110011011010100110010011111";
WHEN "000110" => p3_uid114_constMult_q <= "00010001010011111111010110001100";
WHEN "000111" => p3_uid114_constMult_q <= "00010100001100101001111001111001";
WHEN "001000" => p3_uid114_constMult_q <= "00010111000101010100011101100101";
WHEN "001001" => p3_uid114_constMult_q <= "00011001111101111111000001010010";
WHEN "001010" => p3_uid114_constMult_q <= "00011100110110101001100100111110";
WHEN "001011" => p3_uid114_constMult_q <= "00011111101111010100001000101011";
WHEN "001100" => p3_uid114_constMult_q <= "00100010100111111110101100011000";
WHEN "001101" => p3_uid114_constMult_q <= "00100101100000101001010000000100";
WHEN "001110" => p3_uid114_constMult_q <= "00101000011001010011110011110001";
WHEN "001111" => p3_uid114_constMult_q <= "00101011010001111110010111011110";
WHEN "010000" => p3_uid114_constMult_q <= "00101110001010101000111011001010";
WHEN "010001" => p3_uid114_constMult_q <= "00110001000011010011011110110111";
WHEN "010010" => p3_uid114_constMult_q <= "00110011111011111110000010100100";
WHEN "010011" => p3_uid114_constMult_q <= "00110110110100101000100110010000";
WHEN "010100" => p3_uid114_constMult_q <= "00111001101101010011001001111101";
WHEN "010101" => p3_uid114_constMult_q <= "00111100100101111101101101101010";
WHEN "010110" => p3_uid114_constMult_q <= "00111111011110101000010001010110";
WHEN "010111" => p3_uid114_constMult_q <= "01000010010111010010110101000011";
WHEN "011000" => p3_uid114_constMult_q <= "01000101001111111101011000110000";
WHEN "011001" => p3_uid114_constMult_q <= "01001000001000100111111100011100";
WHEN "011010" => p3_uid114_constMult_q <= "01001011000001010010100000001001";
WHEN "011011" => p3_uid114_constMult_q <= "01001101111001111101000011110101";
WHEN "011100" => p3_uid114_constMult_q <= "01010000110010100111100111100010";
WHEN "011101" => p3_uid114_constMult_q <= "01010011101011010010001011001111";
WHEN "011110" => p3_uid114_constMult_q <= "01010110100011111100101110111011";
WHEN "011111" => p3_uid114_constMult_q <= "01011001011100100111010010101000";
WHEN "100000" => p3_uid114_constMult_q <= "01011100010101010001110110010101";
WHEN "100001" => p3_uid114_constMult_q <= "01011111001101111100011010000001";
WHEN "100010" => p3_uid114_constMult_q <= "01100010000110100110111101101110";
WHEN "100011" => p3_uid114_constMult_q <= "01100100111111010001100001011011";
WHEN "100100" => p3_uid114_constMult_q <= "01100111110111111100000101000111";
WHEN "100101" => p3_uid114_constMult_q <= "01101010110000100110101000110100";
WHEN "100110" => p3_uid114_constMult_q <= "01101101101001010001001100100001";
WHEN "100111" => p3_uid114_constMult_q <= "01110000100001111011110000001101";
WHEN "101000" => p3_uid114_constMult_q <= "01110011011010100110010011111010";
WHEN "101001" => p3_uid114_constMult_q <= "01110110010011010000110111100110";
WHEN "101010" => p3_uid114_constMult_q <= "01111001001011111011011011010011";
WHEN "101011" => p3_uid114_constMult_q <= "01111100000100100101111111000000";
WHEN "101100" => p3_uid114_constMult_q <= "01111110111101010000100010101100";
WHEN "101101" => p3_uid114_constMult_q <= "10000001110101111011000110011001";
WHEN "101110" => p3_uid114_constMult_q <= "10000100101110100101101010000110";
WHEN "101111" => p3_uid114_constMult_q <= "10000111100111010000001101110010";
WHEN "110000" => p3_uid114_constMult_q <= "10001010011111111010110001011111";
WHEN "110001" => p3_uid114_constMult_q <= "10001101011000100101010101001100";
WHEN "110010" => p3_uid114_constMult_q <= "10010000010001001111111000111000";
WHEN "110011" => p3_uid114_constMult_q <= "10010011001001111010011100100101";
WHEN "110100" => p3_uid114_constMult_q <= "10010110000010100101000000010010";
WHEN "110101" => p3_uid114_constMult_q <= "10011000111011001111100011111110";
WHEN "110110" => p3_uid114_constMult_q <= "10011011110011111010000111101011";
WHEN "110111" => p3_uid114_constMult_q <= "10011110101100100100101011011000";
WHEN "111000" => p3_uid114_constMult_q <= "10100001100101001111001111000100";
WHEN "111001" => p3_uid114_constMult_q <= "10100100011101111001110010110001";
WHEN "111010" => p3_uid114_constMult_q <= "10100111010110100100010110011101";
WHEN "111011" => p3_uid114_constMult_q <= "10101010001111001110111010001010";
WHEN "111100" => p3_uid114_constMult_q <= "10101101000111111001011101110111";
WHEN "111101" => p3_uid114_constMult_q <= "10110000000000100100000001100011";
WHEN "111110" => p3_uid114_constMult_q <= "10110010111001001110100101010000";
WHEN "111111" => p3_uid114_constMult_q <= "10110101110001111001001000111101";
WHEN OTHERS =>
p3_uid114_constMult_q <= "00000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv4_uid104_constMult(BITSELECT,103)@0
xv4_uid104_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(29 downto 0);
xv4_uid104_constMult_b <= xv4_uid104_constMult_in(29 downto 24);
--reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0(REG,346)@0
reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q <= xv4_uid104_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a(DELAY,525)@1
ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q, xout => ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p4_uid113_constMult(LOOKUP,112)@2
p4_uid113_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p4_uid113_constMult_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a_q) IS
WHEN "000000" => p4_uid113_constMult_q <= "00000000000000000000000000000000000000";
WHEN "000001" => p4_uid113_constMult_q <= "00000010111000101010100011101100101001";
WHEN "000010" => p4_uid113_constMult_q <= "00000101110001010101000111011001010011";
WHEN "000011" => p4_uid113_constMult_q <= "00001000101001111111101011000101111100";
WHEN "000100" => p4_uid113_constMult_q <= "00001011100010101010001110110010100101";
WHEN "000101" => p4_uid113_constMult_q <= "00001110011011010100110010011111001111";
WHEN "000110" => p4_uid113_constMult_q <= "00010001010011111111010110001011111000";
WHEN "000111" => p4_uid113_constMult_q <= "00010100001100101001111001111000100010";
WHEN "001000" => p4_uid113_constMult_q <= "00010111000101010100011101100101001011";
WHEN "001001" => p4_uid113_constMult_q <= "00011001111101111111000001010001110100";
WHEN "001010" => p4_uid113_constMult_q <= "00011100110110101001100100111110011110";
WHEN "001011" => p4_uid113_constMult_q <= "00011111101111010100001000101011000111";
WHEN "001100" => p4_uid113_constMult_q <= "00100010100111111110101100010111110000";
WHEN "001101" => p4_uid113_constMult_q <= "00100101100000101001010000000100011010";
WHEN "001110" => p4_uid113_constMult_q <= "00101000011001010011110011110001000011";
WHEN "001111" => p4_uid113_constMult_q <= "00101011010001111110010111011101101100";
WHEN "010000" => p4_uid113_constMult_q <= "00101110001010101000111011001010010110";
WHEN "010001" => p4_uid113_constMult_q <= "00110001000011010011011110110110111111";
WHEN "010010" => p4_uid113_constMult_q <= "00110011111011111110000010100011101000";
WHEN "010011" => p4_uid113_constMult_q <= "00110110110100101000100110010000010010";
WHEN "010100" => p4_uid113_constMult_q <= "00111001101101010011001001111100111011";
WHEN "010101" => p4_uid113_constMult_q <= "00111100100101111101101101101001100101";
WHEN "010110" => p4_uid113_constMult_q <= "00111111011110101000010001010110001110";
WHEN "010111" => p4_uid113_constMult_q <= "01000010010111010010110101000010110111";
WHEN "011000" => p4_uid113_constMult_q <= "01000101001111111101011000101111100001";
WHEN "011001" => p4_uid113_constMult_q <= "01001000001000100111111100011100001010";
WHEN "011010" => p4_uid113_constMult_q <= "01001011000001010010100000001000110011";
WHEN "011011" => p4_uid113_constMult_q <= "01001101111001111101000011110101011101";
WHEN "011100" => p4_uid113_constMult_q <= "01010000110010100111100111100010000110";
WHEN "011101" => p4_uid113_constMult_q <= "01010011101011010010001011001110101111";
WHEN "011110" => p4_uid113_constMult_q <= "01010110100011111100101110111011011001";
WHEN "011111" => p4_uid113_constMult_q <= "01011001011100100111010010101000000010";
WHEN "100000" => p4_uid113_constMult_q <= "01011100010101010001110110010100101100";
WHEN "100001" => p4_uid113_constMult_q <= "01011111001101111100011010000001010101";
WHEN "100010" => p4_uid113_constMult_q <= "01100010000110100110111101101101111110";
WHEN "100011" => p4_uid113_constMult_q <= "01100100111111010001100001011010101000";
WHEN "100100" => p4_uid113_constMult_q <= "01100111110111111100000101000111010001";
WHEN "100101" => p4_uid113_constMult_q <= "01101010110000100110101000110011111010";
WHEN "100110" => p4_uid113_constMult_q <= "01101101101001010001001100100000100100";
WHEN "100111" => p4_uid113_constMult_q <= "01110000100001111011110000001101001101";
WHEN "101000" => p4_uid113_constMult_q <= "01110011011010100110010011111001110110";
WHEN "101001" => p4_uid113_constMult_q <= "01110110010011010000110111100110100000";
WHEN "101010" => p4_uid113_constMult_q <= "01111001001011111011011011010011001001";
WHEN "101011" => p4_uid113_constMult_q <= "01111100000100100101111110111111110010";
WHEN "101100" => p4_uid113_constMult_q <= "01111110111101010000100010101100011100";
WHEN "101101" => p4_uid113_constMult_q <= "10000001110101111011000110011001000101";
WHEN "101110" => p4_uid113_constMult_q <= "10000100101110100101101010000101101111";
WHEN "101111" => p4_uid113_constMult_q <= "10000111100111010000001101110010011000";
WHEN "110000" => p4_uid113_constMult_q <= "10001010011111111010110001011111000001";
WHEN "110001" => p4_uid113_constMult_q <= "10001101011000100101010101001011101011";
WHEN "110010" => p4_uid113_constMult_q <= "10010000010001001111111000111000010100";
WHEN "110011" => p4_uid113_constMult_q <= "10010011001001111010011100100100111101";
WHEN "110100" => p4_uid113_constMult_q <= "10010110000010100101000000010001100111";
WHEN "110101" => p4_uid113_constMult_q <= "10011000111011001111100011111110010000";
WHEN "110110" => p4_uid113_constMult_q <= "10011011110011111010000111101010111001";
WHEN "110111" => p4_uid113_constMult_q <= "10011110101100100100101011010111100011";
WHEN "111000" => p4_uid113_constMult_q <= "10100001100101001111001111000100001100";
WHEN "111001" => p4_uid113_constMult_q <= "10100100011101111001110010110000110110";
WHEN "111010" => p4_uid113_constMult_q <= "10100111010110100100010110011101011111";
WHEN "111011" => p4_uid113_constMult_q <= "10101010001111001110111010001010001000";
WHEN "111100" => p4_uid113_constMult_q <= "10101101000111111001011101110110110010";
WHEN "111101" => p4_uid113_constMult_q <= "10110000000000100100000001100011011011";
WHEN "111110" => p4_uid113_constMult_q <= "10110010111001001110100101010000000100";
WHEN "111111" => p4_uid113_constMult_q <= "10110101110001111001001000111100101110";
WHEN OTHERS =>
p4_uid113_constMult_q <= "00000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a2_uid120_constMult(ADD,119)@3
lev1_a2_uid120_constMult_a <= STD_LOGIC_VECTOR("0" & p4_uid113_constMult_q);
lev1_a2_uid120_constMult_b <= STD_LOGIC_VECTOR("0000000" & p3_uid114_constMult_q);
lev1_a2_uid120_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev1_a2_uid120_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev1_a2_uid120_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a2_uid120_constMult_a) + UNSIGNED(lev1_a2_uid120_constMult_b));
END IF;
END IF;
END PROCESS;
lev1_a2_uid120_constMult_q <= lev1_a2_uid120_constMult_o(38 downto 0);
--lev2_a1_uid123_constMult(ADD,122)@4
lev2_a1_uid123_constMult_a <= STD_LOGIC_VECTOR("0" & lev1_a2_uid120_constMult_q);
lev2_a1_uid123_constMult_b <= STD_LOGIC_VECTOR("0000000000000" & lev1_a3_uid121_constMult_q);
lev2_a1_uid123_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev2_a1_uid123_constMult_a) + UNSIGNED(lev2_a1_uid123_constMult_b));
lev2_a1_uid123_constMult_q <= lev2_a1_uid123_constMult_o(39 downto 0);
--xv5_uid105_constMult(BITSELECT,104)@0
xv5_uid105_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(35 downto 0);
xv5_uid105_constMult_b <= xv5_uid105_constMult_in(35 downto 30);
--ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a(DELAY,799)@0
ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => xv5_uid105_constMult_b, xout => ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0(REG,345)@2
reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q <= ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p5_uid112_constMult(LOOKUP,111)@3
p5_uid112_constMult: PROCESS (reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q) IS
WHEN "000000" => p5_uid112_constMult_q <= "00000000000000000000000000000000000000000000";
WHEN "000001" => p5_uid112_constMult_q <= "00000010111000101010100011101100101001010111";
WHEN "000010" => p5_uid112_constMult_q <= "00000101110001010101000111011001010010101110";
WHEN "000011" => p5_uid112_constMult_q <= "00001000101001111111101011000101111100000101";
WHEN "000100" => p5_uid112_constMult_q <= "00001011100010101010001110110010100101011100";
WHEN "000101" => p5_uid112_constMult_q <= "00001110011011010100110010011111001110110011";
WHEN "000110" => p5_uid112_constMult_q <= "00010001010011111111010110001011111000001010";
WHEN "000111" => p5_uid112_constMult_q <= "00010100001100101001111001111000100001100001";
WHEN "001000" => p5_uid112_constMult_q <= "00010111000101010100011101100101001010111000";
WHEN "001001" => p5_uid112_constMult_q <= "00011001111101111111000001010001110100001111";
WHEN "001010" => p5_uid112_constMult_q <= "00011100110110101001100100111110011101100110";
WHEN "001011" => p5_uid112_constMult_q <= "00011111101111010100001000101011000110111101";
WHEN "001100" => p5_uid112_constMult_q <= "00100010100111111110101100010111110000010100";
WHEN "001101" => p5_uid112_constMult_q <= "00100101100000101001010000000100011001101011";
WHEN "001110" => p5_uid112_constMult_q <= "00101000011001010011110011110001000011000010";
WHEN "001111" => p5_uid112_constMult_q <= "00101011010001111110010111011101101100011001";
WHEN "010000" => p5_uid112_constMult_q <= "00101110001010101000111011001010010101110000";
WHEN "010001" => p5_uid112_constMult_q <= "00110001000011010011011110110110111111000111";
WHEN "010010" => p5_uid112_constMult_q <= "00110011111011111110000010100011101000011110";
WHEN "010011" => p5_uid112_constMult_q <= "00110110110100101000100110010000010001110101";
WHEN "010100" => p5_uid112_constMult_q <= "00111001101101010011001001111100111011001100";
WHEN "010101" => p5_uid112_constMult_q <= "00111100100101111101101101101001100100100011";
WHEN "010110" => p5_uid112_constMult_q <= "00111111011110101000010001010110001101111011";
WHEN "010111" => p5_uid112_constMult_q <= "01000010010111010010110101000010110111010010";
WHEN "011000" => p5_uid112_constMult_q <= "01000101001111111101011000101111100000101001";
WHEN "011001" => p5_uid112_constMult_q <= "01001000001000100111111100011100001010000000";
WHEN "011010" => p5_uid112_constMult_q <= "01001011000001010010100000001000110011010111";
WHEN "011011" => p5_uid112_constMult_q <= "01001101111001111101000011110101011100101110";
WHEN "011100" => p5_uid112_constMult_q <= "01010000110010100111100111100010000110000101";
WHEN "011101" => p5_uid112_constMult_q <= "01010011101011010010001011001110101111011100";
WHEN "011110" => p5_uid112_constMult_q <= "01010110100011111100101110111011011000110011";
WHEN "011111" => p5_uid112_constMult_q <= "01011001011100100111010010101000000010001010";
WHEN "100000" => p5_uid112_constMult_q <= "01011100010101010001110110010100101011100001";
WHEN "100001" => p5_uid112_constMult_q <= "01011111001101111100011010000001010100111000";
WHEN "100010" => p5_uid112_constMult_q <= "01100010000110100110111101101101111110001111";
WHEN "100011" => p5_uid112_constMult_q <= "01100100111111010001100001011010100111100110";
WHEN "100100" => p5_uid112_constMult_q <= "01100111110111111100000101000111010000111101";
WHEN "100101" => p5_uid112_constMult_q <= "01101010110000100110101000110011111010010100";
WHEN "100110" => p5_uid112_constMult_q <= "01101101101001010001001100100000100011101011";
WHEN "100111" => p5_uid112_constMult_q <= "01110000100001111011110000001101001101000010";
WHEN "101000" => p5_uid112_constMult_q <= "01110011011010100110010011111001110110011001";
WHEN "101001" => p5_uid112_constMult_q <= "01110110010011010000110111100110011111110000";
WHEN "101010" => p5_uid112_constMult_q <= "01111001001011111011011011010011001001000111";
WHEN "101011" => p5_uid112_constMult_q <= "01111100000100100101111110111111110010011110";
WHEN "101100" => p5_uid112_constMult_q <= "01111110111101010000100010101100011011110101";
WHEN "101101" => p5_uid112_constMult_q <= "10000001110101111011000110011001000101001100";
WHEN "101110" => p5_uid112_constMult_q <= "10000100101110100101101010000101101110100011";
WHEN "101111" => p5_uid112_constMult_q <= "10000111100111010000001101110010010111111010";
WHEN "110000" => p5_uid112_constMult_q <= "10001010011111111010110001011111000001010001";
WHEN "110001" => p5_uid112_constMult_q <= "10001101011000100101010101001011101010101000";
WHEN "110010" => p5_uid112_constMult_q <= "10010000010001001111111000111000010011111111";
WHEN "110011" => p5_uid112_constMult_q <= "10010011001001111010011100100100111101010110";
WHEN "110100" => p5_uid112_constMult_q <= "10010110000010100101000000010001100110101101";
WHEN "110101" => p5_uid112_constMult_q <= "10011000111011001111100011111110010000000100";
WHEN "110110" => p5_uid112_constMult_q <= "10011011110011111010000111101010111001011011";
WHEN "110111" => p5_uid112_constMult_q <= "10011110101100100100101011010111100010110010";
WHEN "111000" => p5_uid112_constMult_q <= "10100001100101001111001111000100001100001001";
WHEN "111001" => p5_uid112_constMult_q <= "10100100011101111001110010110000110101100000";
WHEN "111010" => p5_uid112_constMult_q <= "10100111010110100100010110011101011110110111";
WHEN "111011" => p5_uid112_constMult_q <= "10101010001111001110111010001010001000001110";
WHEN "111100" => p5_uid112_constMult_q <= "10101101000111111001011101110110110001100101";
WHEN "111101" => p5_uid112_constMult_q <= "10110000000000100100000001100011011010111100";
WHEN "111110" => p5_uid112_constMult_q <= "10110010111001001110100101010000000100010011";
WHEN "111111" => p5_uid112_constMult_q <= "10110101110001111001001000111100101101101010";
WHEN OTHERS =>
p5_uid112_constMult_q <= "00000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv6_uid106_constMult(BITSELECT,105)@0
xv6_uid106_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(41 downto 0);
xv6_uid106_constMult_b <= xv6_uid106_constMult_in(41 downto 36);
--reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0(REG,344)@0
reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q <= xv6_uid106_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a(DELAY,523)@1
ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q, xout => ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p6_uid111_constMult(LOOKUP,110)@2
p6_uid111_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p6_uid111_constMult_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a_q) IS
WHEN "000000" => p6_uid111_constMult_q <= "00000000000000000000000000000000000000000000000000";
WHEN "000001" => p6_uid111_constMult_q <= "00000010111000101010100011101100101001010111000001";
WHEN "000010" => p6_uid111_constMult_q <= "00000101110001010101000111011001010010101110000011";
WHEN "000011" => p6_uid111_constMult_q <= "00001000101001111111101011000101111100000101000100";
WHEN "000100" => p6_uid111_constMult_q <= "00001011100010101010001110110010100101011100000110";
WHEN "000101" => p6_uid111_constMult_q <= "00001110011011010100110010011111001110110011000111";
WHEN "000110" => p6_uid111_constMult_q <= "00010001010011111111010110001011111000001010001001";
WHEN "000111" => p6_uid111_constMult_q <= "00010100001100101001111001111000100001100001001010";
WHEN "001000" => p6_uid111_constMult_q <= "00010111000101010100011101100101001010111000001100";
WHEN "001001" => p6_uid111_constMult_q <= "00011001111101111111000001010001110100001111001101";
WHEN "001010" => p6_uid111_constMult_q <= "00011100110110101001100100111110011101100110001111";
WHEN "001011" => p6_uid111_constMult_q <= "00011111101111010100001000101011000110111101010000";
WHEN "001100" => p6_uid111_constMult_q <= "00100010100111111110101100010111110000010100010010";
WHEN "001101" => p6_uid111_constMult_q <= "00100101100000101001010000000100011001101011010011";
WHEN "001110" => p6_uid111_constMult_q <= "00101000011001010011110011110001000011000010010101";
WHEN "001111" => p6_uid111_constMult_q <= "00101011010001111110010111011101101100011001010110";
WHEN "010000" => p6_uid111_constMult_q <= "00101110001010101000111011001010010101110000011000";
WHEN "010001" => p6_uid111_constMult_q <= "00110001000011010011011110110110111111000111011001";
WHEN "010010" => p6_uid111_constMult_q <= "00110011111011111110000010100011101000011110011011";
WHEN "010011" => p6_uid111_constMult_q <= "00110110110100101000100110010000010001110101011100";
WHEN "010100" => p6_uid111_constMult_q <= "00111001101101010011001001111100111011001100011110";
WHEN "010101" => p6_uid111_constMult_q <= "00111100100101111101101101101001100100100011011111";
WHEN "010110" => p6_uid111_constMult_q <= "00111111011110101000010001010110001101111010100001";
WHEN "010111" => p6_uid111_constMult_q <= "01000010010111010010110101000010110111010001100010";
WHEN "011000" => p6_uid111_constMult_q <= "01000101001111111101011000101111100000101000100100";
WHEN "011001" => p6_uid111_constMult_q <= "01001000001000100111111100011100001001111111100101";
WHEN "011010" => p6_uid111_constMult_q <= "01001011000001010010100000001000110011010110100111";
WHEN "011011" => p6_uid111_constMult_q <= "01001101111001111101000011110101011100101101101000";
WHEN "011100" => p6_uid111_constMult_q <= "01010000110010100111100111100010000110000100101010";
WHEN "011101" => p6_uid111_constMult_q <= "01010011101011010010001011001110101111011011101011";
WHEN "011110" => p6_uid111_constMult_q <= "01010110100011111100101110111011011000110010101101";
WHEN "011111" => p6_uid111_constMult_q <= "01011001011100100111010010101000000010001001101110";
WHEN "100000" => p6_uid111_constMult_q <= "01011100010101010001110110010100101011100000110000";
WHEN "100001" => p6_uid111_constMult_q <= "01011111001101111100011010000001010100110111110001";
WHEN "100010" => p6_uid111_constMult_q <= "01100010000110100110111101101101111110001110110011";
WHEN "100011" => p6_uid111_constMult_q <= "01100100111111010001100001011010100111100101110100";
WHEN "100100" => p6_uid111_constMult_q <= "01100111110111111100000101000111010000111100110110";
WHEN "100101" => p6_uid111_constMult_q <= "01101010110000100110101000110011111010010011110111";
WHEN "100110" => p6_uid111_constMult_q <= "01101101101001010001001100100000100011101010111001";
WHEN "100111" => p6_uid111_constMult_q <= "01110000100001111011110000001101001101000001111010";
WHEN "101000" => p6_uid111_constMult_q <= "01110011011010100110010011111001110110011000111100";
WHEN "101001" => p6_uid111_constMult_q <= "01110110010011010000110111100110011111101111111101";
WHEN "101010" => p6_uid111_constMult_q <= "01111001001011111011011011010011001001000110111111";
WHEN "101011" => p6_uid111_constMult_q <= "01111100000100100101111110111111110010011110000000";
WHEN "101100" => p6_uid111_constMult_q <= "01111110111101010000100010101100011011110101000010";
WHEN "101101" => p6_uid111_constMult_q <= "10000001110101111011000110011001000101001100000011";
WHEN "101110" => p6_uid111_constMult_q <= "10000100101110100101101010000101101110100011000101";
WHEN "101111" => p6_uid111_constMult_q <= "10000111100111010000001101110010010111111010000110";
WHEN "110000" => p6_uid111_constMult_q <= "10001010011111111010110001011111000001010001001000";
WHEN "110001" => p6_uid111_constMult_q <= "10001101011000100101010101001011101010101000001001";
WHEN "110010" => p6_uid111_constMult_q <= "10010000010001001111111000111000010011111111001011";
WHEN "110011" => p6_uid111_constMult_q <= "10010011001001111010011100100100111101010110001100";
WHEN "110100" => p6_uid111_constMult_q <= "10010110000010100101000000010001100110101101001110";
WHEN "110101" => p6_uid111_constMult_q <= "10011000111011001111100011111110010000000100001111";
WHEN "110110" => p6_uid111_constMult_q <= "10011011110011111010000111101010111001011011010001";
WHEN "110111" => p6_uid111_constMult_q <= "10011110101100100100101011010111100010110010010010";
WHEN "111000" => p6_uid111_constMult_q <= "10100001100101001111001111000100001100001001010100";
WHEN "111001" => p6_uid111_constMult_q <= "10100100011101111001110010110000110101100000010101";
WHEN "111010" => p6_uid111_constMult_q <= "10100111010110100100010110011101011110110111010111";
WHEN "111011" => p6_uid111_constMult_q <= "10101010001111001110111010001010001000001110011000";
WHEN "111100" => p6_uid111_constMult_q <= "10101101000111111001011101110110110001100101011010";
WHEN "111101" => p6_uid111_constMult_q <= "10110000000000100100000001100011011010111100011011";
WHEN "111110" => p6_uid111_constMult_q <= "10110010111001001110100101010000000100010011011101";
WHEN "111111" => p6_uid111_constMult_q <= "10110101110001111001001000111100101101101010011110";
WHEN OTHERS =>
p6_uid111_constMult_q <= "00000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a1_uid119_constMult(ADD,118)@3
lev1_a1_uid119_constMult_a <= STD_LOGIC_VECTOR("0" & p6_uid111_constMult_q);
lev1_a1_uid119_constMult_b <= STD_LOGIC_VECTOR("0000000" & p5_uid112_constMult_q);
lev1_a1_uid119_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a1_uid119_constMult_a) + UNSIGNED(lev1_a1_uid119_constMult_b));
lev1_a1_uid119_constMult_q <= lev1_a1_uid119_constMult_o(50 downto 0);
--xv7_uid107_constMult(BITSELECT,106)@0
xv7_uid107_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(47 downto 0);
xv7_uid107_constMult_b <= xv7_uid107_constMult_in(47 downto 42);
--reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0(REG,343)@0
reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q <= xv7_uid107_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a(DELAY,522)@1
ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q, xout => ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p7_uid110_constMult(LOOKUP,109)@2
p7_uid110_constMult: PROCESS (ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q) IS
WHEN "000000" => p7_uid110_constMult_q <= "00000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p7_uid110_constMult_q <= "00000010111000101010100011101100101001010111000001100000";
WHEN "000010" => p7_uid110_constMult_q <= "00000101110001010101000111011001010010101110000011000000";
WHEN "000011" => p7_uid110_constMult_q <= "00001000101001111111101011000101111100000101000100011111";
WHEN "000100" => p7_uid110_constMult_q <= "00001011100010101010001110110010100101011100000101111111";
WHEN "000101" => p7_uid110_constMult_q <= "00001110011011010100110010011111001110110011000111011111";
WHEN "000110" => p7_uid110_constMult_q <= "00010001010011111111010110001011111000001010001000111111";
WHEN "000111" => p7_uid110_constMult_q <= "00010100001100101001111001111000100001100001001010011110";
WHEN "001000" => p7_uid110_constMult_q <= "00010111000101010100011101100101001010111000001011111110";
WHEN "001001" => p7_uid110_constMult_q <= "00011001111101111111000001010001110100001111001101011110";
WHEN "001010" => p7_uid110_constMult_q <= "00011100110110101001100100111110011101100110001110111110";
WHEN "001011" => p7_uid110_constMult_q <= "00011111101111010100001000101011000110111101010000011101";
WHEN "001100" => p7_uid110_constMult_q <= "00100010100111111110101100010111110000010100010001111101";
WHEN "001101" => p7_uid110_constMult_q <= "00100101100000101001010000000100011001101011010011011101";
WHEN "001110" => p7_uid110_constMult_q <= "00101000011001010011110011110001000011000010010100111101";
WHEN "001111" => p7_uid110_constMult_q <= "00101011010001111110010111011101101100011001010110011100";
WHEN "010000" => p7_uid110_constMult_q <= "00101110001010101000111011001010010101110000010111111100";
WHEN "010001" => p7_uid110_constMult_q <= "00110001000011010011011110110110111111000111011001011100";
WHEN "010010" => p7_uid110_constMult_q <= "00110011111011111110000010100011101000011110011010111100";
WHEN "010011" => p7_uid110_constMult_q <= "00110110110100101000100110010000010001110101011100011011";
WHEN "010100" => p7_uid110_constMult_q <= "00111001101101010011001001111100111011001100011101111011";
WHEN "010101" => p7_uid110_constMult_q <= "00111100100101111101101101101001100100100011011111011011";
WHEN "010110" => p7_uid110_constMult_q <= "00111111011110101000010001010110001101111010100000111011";
WHEN "010111" => p7_uid110_constMult_q <= "01000010010111010010110101000010110111010001100010011011";
WHEN "011000" => p7_uid110_constMult_q <= "01000101001111111101011000101111100000101000100011111010";
WHEN "011001" => p7_uid110_constMult_q <= "01001000001000100111111100011100001001111111100101011010";
WHEN "011010" => p7_uid110_constMult_q <= "01001011000001010010100000001000110011010110100110111010";
WHEN "011011" => p7_uid110_constMult_q <= "01001101111001111101000011110101011100101101101000011010";
WHEN "011100" => p7_uid110_constMult_q <= "01010000110010100111100111100010000110000100101001111001";
WHEN "011101" => p7_uid110_constMult_q <= "01010011101011010010001011001110101111011011101011011001";
WHEN "011110" => p7_uid110_constMult_q <= "01010110100011111100101110111011011000110010101100111001";
WHEN "011111" => p7_uid110_constMult_q <= "01011001011100100111010010101000000010001001101110011001";
WHEN "100000" => p7_uid110_constMult_q <= "01011100010101010001110110010100101011100000101111111000";
WHEN "100001" => p7_uid110_constMult_q <= "01011111001101111100011010000001010100110111110001011000";
WHEN "100010" => p7_uid110_constMult_q <= "01100010000110100110111101101101111110001110110010111000";
WHEN "100011" => p7_uid110_constMult_q <= "01100100111111010001100001011010100111100101110100011000";
WHEN "100100" => p7_uid110_constMult_q <= "01100111110111111100000101000111010000111100110101110111";
WHEN "100101" => p7_uid110_constMult_q <= "01101010110000100110101000110011111010010011110111010111";
WHEN "100110" => p7_uid110_constMult_q <= "01101101101001010001001100100000100011101010111000110111";
WHEN "100111" => p7_uid110_constMult_q <= "01110000100001111011110000001101001101000001111010010111";
WHEN "101000" => p7_uid110_constMult_q <= "01110011011010100110010011111001110110011000111011110110";
WHEN "101001" => p7_uid110_constMult_q <= "01110110010011010000110111100110011111101111111101010110";
WHEN "101010" => p7_uid110_constMult_q <= "01111001001011111011011011010011001001000110111110110110";
WHEN "101011" => p7_uid110_constMult_q <= "01111100000100100101111110111111110010011110000000010110";
WHEN "101100" => p7_uid110_constMult_q <= "01111110111101010000100010101100011011110101000001110110";
WHEN "101101" => p7_uid110_constMult_q <= "10000001110101111011000110011001000101001100000011010101";
WHEN "101110" => p7_uid110_constMult_q <= "10000100101110100101101010000101101110100011000100110101";
WHEN "101111" => p7_uid110_constMult_q <= "10000111100111010000001101110010010111111010000110010101";
WHEN "110000" => p7_uid110_constMult_q <= "10001010011111111010110001011111000001010001000111110101";
WHEN "110001" => p7_uid110_constMult_q <= "10001101011000100101010101001011101010101000001001010100";
WHEN "110010" => p7_uid110_constMult_q <= "10010000010001001111111000111000010011111111001010110100";
WHEN "110011" => p7_uid110_constMult_q <= "10010011001001111010011100100100111101010110001100010100";
WHEN "110100" => p7_uid110_constMult_q <= "10010110000010100101000000010001100110101101001101110100";
WHEN "110101" => p7_uid110_constMult_q <= "10011000111011001111100011111110010000000100001111010011";
WHEN "110110" => p7_uid110_constMult_q <= "10011011110011111010000111101010111001011011010000110011";
WHEN "110111" => p7_uid110_constMult_q <= "10011110101100100100101011010111100010110010010010010011";
WHEN "111000" => p7_uid110_constMult_q <= "10100001100101001111001111000100001100001001010011110011";
WHEN "111001" => p7_uid110_constMult_q <= "10100100011101111001110010110000110101100000010101010010";
WHEN "111010" => p7_uid110_constMult_q <= "10100111010110100100010110011101011110110111010110110010";
WHEN "111011" => p7_uid110_constMult_q <= "10101010001111001110111010001010001000001110011000010010";
WHEN "111100" => p7_uid110_constMult_q <= "10101101000111111001011101110110110001100101011001110010";
WHEN "111101" => p7_uid110_constMult_q <= "10110000000000100100000001100011011010111100011011010001";
WHEN "111110" => p7_uid110_constMult_q <= "10110010111001001110100101010000000100010011011100110001";
WHEN "111111" => p7_uid110_constMult_q <= "10110101110001111001001000111100101101101010011110010001";
WHEN OTHERS =>
p7_uid110_constMult_q <= "00000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv8_uid108_constMult(BITSELECT,107)@0
xv8_uid108_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b;
xv8_uid108_constMult_b <= xv8_uid108_constMult_in(53 downto 48);
--reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0(REG,342)@0
reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q <= xv8_uid108_constMult_b;
END IF;
END IF;
END PROCESS;
--p8_uid109_constMult(LOOKUP,108)@1
p8_uid109_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p8_uid109_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q) IS
WHEN "000000" => p8_uid109_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p8_uid109_constMult_q <= "00000010111000101010100011101100101001010111000001011111110001";
WHEN "000010" => p8_uid109_constMult_q <= "00000101110001010101000111011001010010101110000010111111100010";
WHEN "000011" => p8_uid109_constMult_q <= "00001000101001111111101011000101111100000101000100011111010010";
WHEN "000100" => p8_uid109_constMult_q <= "00001011100010101010001110110010100101011100000101111111000011";
WHEN "000101" => p8_uid109_constMult_q <= "00001110011011010100110010011111001110110011000111011110110100";
WHEN "000110" => p8_uid109_constMult_q <= "00010001010011111111010110001011111000001010001000111110100100";
WHEN "000111" => p8_uid109_constMult_q <= "00010100001100101001111001111000100001100001001010011110010101";
WHEN "001000" => p8_uid109_constMult_q <= "00010111000101010100011101100101001010111000001011111110000110";
WHEN "001001" => p8_uid109_constMult_q <= "00011001111101111111000001010001110100001111001101011101110111";
WHEN "001010" => p8_uid109_constMult_q <= "00011100110110101001100100111110011101100110001110111101101000";
WHEN "001011" => p8_uid109_constMult_q <= "00011111101111010100001000101011000110111101010000011101011000";
WHEN "001100" => p8_uid109_constMult_q <= "00100010100111111110101100010111110000010100010001111101001001";
WHEN "001101" => p8_uid109_constMult_q <= "00100101100000101001010000000100011001101011010011011100111010";
WHEN "001110" => p8_uid109_constMult_q <= "00101000011001010011110011110001000011000010010100111100101010";
WHEN "001111" => p8_uid109_constMult_q <= "00101011010001111110010111011101101100011001010110011100011011";
WHEN "010000" => p8_uid109_constMult_q <= "00101110001010101000111011001010010101110000010111111100001100";
WHEN "010001" => p8_uid109_constMult_q <= "00110001000011010011011110110110111111000111011001011011111101";
WHEN "010010" => p8_uid109_constMult_q <= "00110011111011111110000010100011101000011110011010111011101110";
WHEN "010011" => p8_uid109_constMult_q <= "00110110110100101000100110010000010001110101011100011011011110";
WHEN "010100" => p8_uid109_constMult_q <= "00111001101101010011001001111100111011001100011101111011001111";
WHEN "010101" => p8_uid109_constMult_q <= "00111100100101111101101101101001100100100011011111011011000000";
WHEN "010110" => p8_uid109_constMult_q <= "00111111011110101000010001010110001101111010100000111010110000";
WHEN "010111" => p8_uid109_constMult_q <= "01000010010111010010110101000010110111010001100010011010100001";
WHEN "011000" => p8_uid109_constMult_q <= "01000101001111111101011000101111100000101000100011111010010010";
WHEN "011001" => p8_uid109_constMult_q <= "01001000001000100111111100011100001001111111100101011010000011";
WHEN "011010" => p8_uid109_constMult_q <= "01001011000001010010100000001000110011010110100110111001110100";
WHEN "011011" => p8_uid109_constMult_q <= "01001101111001111101000011110101011100101101101000011001100100";
WHEN "011100" => p8_uid109_constMult_q <= "01010000110010100111100111100010000110000100101001111001010101";
WHEN "011101" => p8_uid109_constMult_q <= "01010011101011010010001011001110101111011011101011011001000110";
WHEN "011110" => p8_uid109_constMult_q <= "01010110100011111100101110111011011000110010101100111000110110";
WHEN "011111" => p8_uid109_constMult_q <= "01011001011100100111010010101000000010001001101110011000100111";
WHEN "100000" => p8_uid109_constMult_q <= "10100011101010101110001001101011010100011111010000000111101000";
WHEN "100001" => p8_uid109_constMult_q <= "10100110100011011000101101010111111101110110010001100111011001";
WHEN "100010" => p8_uid109_constMult_q <= "10101001011100000011010001000100100111001101010011000111001010";
WHEN "100011" => p8_uid109_constMult_q <= "10101100010100101101110100110001010000100100010100100110111010";
WHEN "100100" => p8_uid109_constMult_q <= "10101111001101011000011000011101111001111011010110000110101011";
WHEN "100101" => p8_uid109_constMult_q <= "10110010000110000010111100001010100011010010010111100110011100";
WHEN "100110" => p8_uid109_constMult_q <= "10110100111110101101011111110111001100101001011001000110001100";
WHEN "100111" => p8_uid109_constMult_q <= "10110111110111011000000011100011110110000000011010100101111101";
WHEN "101000" => p8_uid109_constMult_q <= "10111010110000000010100111010000011111010111011100000101101110";
WHEN "101001" => p8_uid109_constMult_q <= "10111101101000101101001010111101001000101110011101100101011111";
WHEN "101010" => p8_uid109_constMult_q <= "11000000100001010111101110101001110010000101011111000101010000";
WHEN "101011" => p8_uid109_constMult_q <= "11000011011010000010010010010110011011011100100000100101000000";
WHEN "101100" => p8_uid109_constMult_q <= "11000110010010101100110110000011000100110011100010000100110001";
WHEN "101101" => p8_uid109_constMult_q <= "11001001001011010111011001101111101110001010100011100100100010";
WHEN "101110" => p8_uid109_constMult_q <= "11001100000100000001111101011100010111100001100101000100010010";
WHEN "101111" => p8_uid109_constMult_q <= "11001110111100101100100001001001000000111000100110100100000011";
WHEN "110000" => p8_uid109_constMult_q <= "11010001110101010111000100110101101010001111101000000011110100";
WHEN "110001" => p8_uid109_constMult_q <= "11010100101110000001101000100010010011100110101001100011100101";
WHEN "110010" => p8_uid109_constMult_q <= "11010111100110101100001100001110111100111101101011000011010110";
WHEN "110011" => p8_uid109_constMult_q <= "11011010011111010110101111111011100110010100101100100011000110";
WHEN "110100" => p8_uid109_constMult_q <= "11011101011000000001010011101000001111101011101110000010110111";
WHEN "110101" => p8_uid109_constMult_q <= "11100000010000101011110111010100111001000010101111100010101000";
WHEN "110110" => p8_uid109_constMult_q <= "11100011001001010110011011000001100010011001110001000010011000";
WHEN "110111" => p8_uid109_constMult_q <= "11100110000010000000111110101110001011110000110010100010001001";
WHEN "111000" => p8_uid109_constMult_q <= "11101000111010101011100010011010110101000111110100000001111010";
WHEN "111001" => p8_uid109_constMult_q <= "11101011110011010110000110000111011110011110110101100001101011";
WHEN "111010" => p8_uid109_constMult_q <= "11101110101100000000101001110100000111110101110111000001011100";
WHEN "111011" => p8_uid109_constMult_q <= "11110001100100101011001101100000110001001100111000100001001100";
WHEN "111100" => p8_uid109_constMult_q <= "11110100011101010101110001001101011010100011111010000000111101";
WHEN "111101" => p8_uid109_constMult_q <= "11110111010110000000010100111010000011111010111011100000101110";
WHEN "111110" => p8_uid109_constMult_q <= "11111010001110101010111000100110101101010001111101000000011110";
WHEN "111111" => p8_uid109_constMult_q <= "11111101000111010101011100010011010110101000111110100000001111";
WHEN OTHERS =>
p8_uid109_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid118_constMult(ADD,117)@2
lev1_a0_uid118_constMult_a <= STD_LOGIC_VECTOR((63 downto 62 => p8_uid109_constMult_q(61)) & p8_uid109_constMult_q);
lev1_a0_uid118_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p7_uid110_constMult_q);
lev1_a0_uid118_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev1_a0_uid118_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev1_a0_uid118_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid118_constMult_a) + SIGNED(lev1_a0_uid118_constMult_b));
END IF;
END IF;
END PROCESS;
lev1_a0_uid118_constMult_q <= lev1_a0_uid118_constMult_o(62 downto 0);
--lev2_a0_uid122_constMult(ADD,121)@3
lev2_a0_uid122_constMult_a <= STD_LOGIC_VECTOR((64 downto 63 => lev1_a0_uid118_constMult_q(62)) & lev1_a0_uid118_constMult_q);
lev2_a0_uid122_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000000" & lev1_a1_uid119_constMult_q);
lev2_a0_uid122_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev2_a0_uid122_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev2_a0_uid122_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev2_a0_uid122_constMult_a) + SIGNED(lev2_a0_uid122_constMult_b));
END IF;
END IF;
END PROCESS;
lev2_a0_uid122_constMult_q <= lev2_a0_uid122_constMult_o(63 downto 0);
--lev3_a0_uid124_constMult(ADD,123)@4
lev3_a0_uid124_constMult_a <= STD_LOGIC_VECTOR((65 downto 64 => lev2_a0_uid122_constMult_q(63)) & lev2_a0_uid122_constMult_q);
lev3_a0_uid124_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000" & lev2_a1_uid123_constMult_q);
lev3_a0_uid124_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev3_a0_uid124_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev3_a0_uid124_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev3_a0_uid124_constMult_a) + SIGNED(lev3_a0_uid124_constMult_b));
END IF;
END IF;
END PROCESS;
lev3_a0_uid124_constMult_q <= lev3_a0_uid124_constMult_o(64 downto 0);
--lev4_a0_uid125_constMult(ADD,124)@5
lev4_a0_uid125_constMult_a <= STD_LOGIC_VECTOR((66 downto 65 => lev3_a0_uid124_constMult_q(64)) & lev3_a0_uid124_constMult_q);
lev4_a0_uid125_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000000000000000000000000000" & p0_uid117_constMult_q);
lev4_a0_uid125_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev4_a0_uid125_constMult_a) + SIGNED(lev4_a0_uid125_constMult_b));
lev4_a0_uid125_constMult_q <= lev4_a0_uid125_constMult_o(65 downto 0);
--sR_uid126_constMult(BITSELECT,125)@5
sR_uid126_constMult_in <= lev4_a0_uid125_constMult_q(61 downto 0);
sR_uid126_constMult_b <= sR_uid126_constMult_in(61 downto 4);
--oFracXZwE_uid39_fpExpETest(BITJOIN,38)@5
oFracXZwE_uid39_fpExpETest_q <= sR_uid126_constMult_b & cstZeroWE_uid11_fpExpETest_q;
--msbx_uid128_fxpInPostAlign_uid45_fpExpETest(BITSELECT,127)@5
msbx_uid128_fxpInPostAlign_uid45_fpExpETest_in <= oFracXZwE_uid39_fpExpETest_q;
msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b <= msbx_uid128_fxpInPostAlign_uid45_fpExpETest_in(68 downto 68);
--ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b(DELAY,581)@5
ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest(LOGICAL,169)@7
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_a <= GND_q;
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_b <= ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q;
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest(BITSELECT,170)@8
RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_in(68 downto 1);
--rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest(BITJOIN,171)@8
rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q & RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_b;
--z_uid163_fxpInPostAlign_uid45_fpExpETest(CONSTANT,162)
z_uid163_fxpInPostAlign_uid45_fpExpETest_q <= "000000";
--rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest(LOGICAL,163)@7
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_a <= z_uid163_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b(DELAY,563)@5
ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid149_fxpInPostAlign_uid45_fpExpETest(CONSTANT,148)
z_uid149_fxpInPostAlign_uid45_fpExpETest_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest(LOGICAL,149)@6
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_a <= z_uid149_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest(CONSTANT,136)
rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest(LOGICAL,137)@5
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_a <= rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((68 downto 1 => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b(0)) & msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b);
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 69, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid133_fxpInPostAlign_uid45_fpExpETest(CONSTANT,132)
z_uid133_fxpInPostAlign_uid45_fpExpETest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest(LOGICAL,133)@5
rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_a <= z_uid133_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b(0)) & msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b);
rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_b;
--X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest(BITSELECT,134)@5
X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_in <= oFracXZwE_uid39_fpExpETest_q;
X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_b <= X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_in(68 downto 64);
--rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest(BITJOIN,135)@5
rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_q & X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_b;
--reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4(REG,354)@5
reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q <= rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--z_uid129_fxpInPostAlign_uid45_fpExpETest(CONSTANT,128)
z_uid129_fxpInPostAlign_uid45_fpExpETest_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest(LOGICAL,129)@5
rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_a <= z_uid129_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b(0)) & msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b);
rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_b;
--X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest(BITSELECT,130)@5
X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_in <= oFracXZwE_uid39_fpExpETest_q;
X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_b <= X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_in(68 downto 32);
--rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest(BITJOIN,131)@5
rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_q & X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_b;
--reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3(REG,353)@5
reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q <= rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2(REG,352)@5
reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q <= oFracXZwE_uid39_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid14_fpExpETest(CONSTANT,13)
cstBiasPWE_uid14_fpExpETest_q <= "1000001";
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable(LOGICAL,884)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_a <= en;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q <= not ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_a;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor(LOGICAL,885)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_b <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_q <= not (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_a or ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_b);
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top(CONSTANT,881)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top_q <= "010";
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp(LOGICAL,882)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q);
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_q <= "1" when ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_a = ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_b else "0";
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg(REG,883)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena(REG,886)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_q = "1") THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd(LOGICAL,887)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_b <= en;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_a and ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_b;
--expX_uid6_fpExpETest(BITSELECT,5)@0
expX_uid6_fpExpETest_in <= a(62 downto 0);
expX_uid6_fpExpETest_b <= expX_uid6_fpExpETest_in(62 downto 52);
--cstBiasPWE_uid13_fpExpETest(CONSTANT,12)
cstBiasPWE_uid13_fpExpETest_q <= "10000001010";
--shiftValuePreSat_uid40_fpExpETest(SUB,39)@0
shiftValuePreSat_uid40_fpExpETest_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid13_fpExpETest_q);
shiftValuePreSat_uid40_fpExpETest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExpETest_b);
shiftValuePreSat_uid40_fpExpETest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid40_fpExpETest_a) - UNSIGNED(shiftValuePreSat_uid40_fpExpETest_b));
shiftValuePreSat_uid40_fpExpETest_q <= shiftValuePreSat_uid40_fpExpETest_o(11 downto 0);
--shiftValuePreSatRed_uid43_fpExpETest(BITSELECT,42)@0
shiftValuePreSatRed_uid43_fpExpETest_in <= shiftValuePreSat_uid40_fpExpETest_q(6 downto 0);
shiftValuePreSatRed_uid43_fpExpETest_b <= shiftValuePreSatRed_uid43_fpExpETest_in(6 downto 0);
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg(DELAY,875)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid43_fpExpETest_b, xout => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt(COUNTER,877)
-- every=1, low=0, high=2, step=1, init=1
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i = 1 THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq <= '1';
ELSE
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i - 2;
ELSE
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i,2));
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg(REG,878)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux(MUX,879)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s <= en;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux: PROCESS (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s, ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q, ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q)
BEGIN
CASE ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s IS
WHEN "0" => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q;
WHEN "1" => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q;
WHEN OTHERS => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem(DUALMEM,876)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ia <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_aa <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ab <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_iq,
address_a => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_aa,
data_a => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ia
);
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_reset0 <= areset;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_iq(6 downto 0);
--reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0(REG,341)@0
reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q <= shiftValuePreSat_uid40_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid42_fpExpETest(COMPARE,41)@1
shiftUdf_uid42_fpExpETest_cin <= GND_q;
shiftUdf_uid42_fpExpETest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q(11)) & reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q) & '0';
shiftUdf_uid42_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid14_fpExpETest_q) & shiftUdf_uid42_fpExpETest_cin(0);
shiftUdf_uid42_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid42_fpExpETest_a) - SIGNED(shiftUdf_uid42_fpExpETest_b));
shiftUdf_uid42_fpExpETest_n(0) <= not shiftUdf_uid42_fpExpETest_o(14);
--ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b(DELAY,451)@1
ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => shiftUdf_uid42_fpExpETest_n, xout => ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--shiftVal_uid44_fpExpETest(MUX,43)@5
shiftVal_uid44_fpExpETest_s <= ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b_q;
shiftVal_uid44_fpExpETest: PROCESS (shiftVal_uid44_fpExpETest_s, en, ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q, cstBiasPWE_uid14_fpExpETest_q)
BEGIN
CASE shiftVal_uid44_fpExpETest_s IS
WHEN "0" => shiftVal_uid44_fpExpETest_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q;
WHEN "1" => shiftVal_uid44_fpExpETest_q <= cstBiasPWE_uid14_fpExpETest_q;
WHEN OTHERS => shiftVal_uid44_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest(BITSELECT,138)@5
rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q;
rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1(REG,351)@5
reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q <= rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest(MUX,139)@6
rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s, en, reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q, reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q, reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q, rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "00" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q;
WHEN "01" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q;
WHEN "10" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q;
WHEN "11" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest(BITSELECT,150)@6
RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_in(68 downto 24);
--ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a(DELAY,573)@6
ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest(BITJOIN,151)@7
rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid145_fxpInPostAlign_uid45_fpExpETest(CONSTANT,144)
z_uid145_fxpInPostAlign_uid45_fpExpETest_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest(LOGICAL,145)@6
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_a <= z_uid145_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest(BITSELECT,146)@6
RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_in(68 downto 16);
--ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a(DELAY,569)@6
ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest(BITJOIN,147)@7
rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid141_fxpInPostAlign_uid45_fpExpETest(CONSTANT,140)
z_uid141_fxpInPostAlign_uid45_fpExpETest_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest(LOGICAL,141)@6
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_a <= z_uid141_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest(BITSELECT,142)@6
RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_in(68 downto 8);
--ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a(DELAY,565)@6
ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest(BITJOIN,143)@7
rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a_q;
--reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2(REG,356)@6
reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest(BITSELECT,152)@5
rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q(4 downto 0);
rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_in(4 downto 3);
--ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a(DELAY,809)@5
ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1(REG,355)@6
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q <= ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest(MUX,153)@7
rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s, en, reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q, rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "10" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "11" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest(BITSELECT,164)@7
RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_in(68 downto 6);
--ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a(DELAY,591)@7
ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest(BITJOIN,165)@8
rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid159_fxpInPostAlign_uid45_fpExpETest(CONSTANT,158)
z_uid159_fxpInPostAlign_uid45_fpExpETest_q <= "0000";
--rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest(LOGICAL,159)@7
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_a <= z_uid159_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest(BITSELECT,160)@7
RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_in(68 downto 4);
--ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a(DELAY,587)@7
ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest(BITJOIN,161)@8
rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid155_fxpInPostAlign_uid45_fpExpETest(CONSTANT,154)
z_uid155_fxpInPostAlign_uid45_fpExpETest_q <= "00";
--rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest(LOGICAL,155)@7
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_a <= z_uid155_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest(BITSELECT,156)@7
RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_in(68 downto 2);
--ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a(DELAY,583)@7
ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest(BITJOIN,157)@8
rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a_q;
--reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2(REG,358)@7
reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest(BITSELECT,166)@5
rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q(2 downto 0);
rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a(DELAY,811)@5
ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1(REG,357)@7
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q <= ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest(MUX,167)@8
rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s, en, reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q, rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "00" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q;
WHEN "01" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "10" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "11" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest(BITSELECT,172)@5
rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q(0 downto 0);
rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_in(0 downto 0);
--ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a(DELAY,813)@5
ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1(REG,359)@7
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q <= ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest(MUX,173)@8
rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s, en, rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "0" => rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "1" => rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--ePreRnd_uid46_fpExpETest(BITSELECT,45)@8
ePreRnd_uid46_fpExpETest_in <= rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q;
ePreRnd_uid46_fpExpETest_b <= ePreRnd_uid46_fpExpETest_in(68 downto 55);
--xv0_uid176_constMult(BITSELECT,175)@8
xv0_uid176_constMult_in <= ePreRnd_uid46_fpExpETest_b(5 downto 0);
xv0_uid176_constMult_b <= xv0_uid176_constMult_in(5 downto 0);
--ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a(DELAY,826)@8
ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => xv0_uid176_constMult_b, xout => ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0(REG,372)@10
reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q <= ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p0_uid181_constMult(LOOKUP,180)@11
p0_uid181_constMult: PROCESS (reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q) IS
WHEN "000000" => p0_uid181_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid181_constMult_q <= "000000101100010111001000010111111101111101000111001111011110011010110";
WHEN "000010" => p0_uid181_constMult_q <= "000001011000101110010000101111111011111010001110011110111100110101100";
WHEN "000011" => p0_uid181_constMult_q <= "000010000101000101011001000111111001110111010101101110011011010000010";
WHEN "000100" => p0_uid181_constMult_q <= "000010110001011100100001011111110111110100011100111101111001101011000";
WHEN "000101" => p0_uid181_constMult_q <= "000011011101110011101001110111110101110001100100001101011000000101110";
WHEN "000110" => p0_uid181_constMult_q <= "000100001010001010110010001111110011101110101011011100110110100000100";
WHEN "000111" => p0_uid181_constMult_q <= "000100110110100001111010100111110001101011110010101100010100111011010";
WHEN "001000" => p0_uid181_constMult_q <= "000101100010111001000010111111101111101000111001111011110011010110000";
WHEN "001001" => p0_uid181_constMult_q <= "000110001111010000001011010111101101100110000001001011010001110000110";
WHEN "001010" => p0_uid181_constMult_q <= "000110111011100111010011101111101011100011001000011010110000001011100";
WHEN "001011" => p0_uid181_constMult_q <= "000111100111111110011100000111101001100000001111101010001110100110010";
WHEN "001100" => p0_uid181_constMult_q <= "001000010100010101100100011111100111011101010110111001101101000001000";
WHEN "001101" => p0_uid181_constMult_q <= "001001000000101100101100110111100101011010011110001001001011011011110";
WHEN "001110" => p0_uid181_constMult_q <= "001001101101000011110101001111100011010111100101011000101001110110100";
WHEN "001111" => p0_uid181_constMult_q <= "001010011001011010111101100111100001010100101100101000001000010001010";
WHEN "010000" => p0_uid181_constMult_q <= "001011000101110010000101111111011111010001110011110111100110101100000";
WHEN "010001" => p0_uid181_constMult_q <= "001011110010001001001110010111011101001110111011000111000101000110110";
WHEN "010010" => p0_uid181_constMult_q <= "001100011110100000010110101111011011001100000010010110100011100001100";
WHEN "010011" => p0_uid181_constMult_q <= "001101001010110111011111000111011001001001001001100110000001111100010";
WHEN "010100" => p0_uid181_constMult_q <= "001101110111001110100111011111010111000110010000110101100000010111000";
WHEN "010101" => p0_uid181_constMult_q <= "001110100011100101101111110111010101000011011000000100111110110001110";
WHEN "010110" => p0_uid181_constMult_q <= "001111001111111100111000001111010011000000011111010100011101001100100";
WHEN "010111" => p0_uid181_constMult_q <= "001111111100010100000000100111010000111101100110100011111011100111010";
WHEN "011000" => p0_uid181_constMult_q <= "010000101000101011001000111111001110111010101101110011011010000010000";
WHEN "011001" => p0_uid181_constMult_q <= "010001010101000010010001010111001100110111110101000010111000011100110";
WHEN "011010" => p0_uid181_constMult_q <= "010010000001011001011001101111001010110100111100010010010110110111100";
WHEN "011011" => p0_uid181_constMult_q <= "010010101101110000100010000111001000110010000011100001110101010010010";
WHEN "011100" => p0_uid181_constMult_q <= "010011011010000111101010011111000110101111001010110001010011101101000";
WHEN "011101" => p0_uid181_constMult_q <= "010100000110011110110010110111000100101100010010000000110010000111110";
WHEN "011110" => p0_uid181_constMult_q <= "010100110010110101111011001111000010101001011001010000010000100010100";
WHEN "011111" => p0_uid181_constMult_q <= "010101011111001101000011100111000000100110100000011111101110111101010";
WHEN "100000" => p0_uid181_constMult_q <= "010110001011100100001011111110111110100011100111101111001101011000000";
WHEN "100001" => p0_uid181_constMult_q <= "010110110111111011010100010110111100100000101110111110101011110010110";
WHEN "100010" => p0_uid181_constMult_q <= "010111100100010010011100101110111010011101110110001110001010001101100";
WHEN "100011" => p0_uid181_constMult_q <= "011000010000101001100101000110111000011010111101011101101000101000010";
WHEN "100100" => p0_uid181_constMult_q <= "011000111101000000101101011110110110011000000100101101000111000011000";
WHEN "100101" => p0_uid181_constMult_q <= "011001101001010111110101110110110100010101001011111100100101011101110";
WHEN "100110" => p0_uid181_constMult_q <= "011010010101101110111110001110110010010010010011001100000011111000100";
WHEN "100111" => p0_uid181_constMult_q <= "011011000010000110000110100110110000001111011010011011100010010011010";
WHEN "101000" => p0_uid181_constMult_q <= "011011101110011101001110111110101110001100100001101011000000101110000";
WHEN "101001" => p0_uid181_constMult_q <= "011100011010110100010111010110101100001001101000111010011111001000110";
WHEN "101010" => p0_uid181_constMult_q <= "011101000111001011011111101110101010000110110000001001111101100011100";
WHEN "101011" => p0_uid181_constMult_q <= "011101110011100010101000000110101000000011110111011001011011111110010";
WHEN "101100" => p0_uid181_constMult_q <= "011110011111111001110000011110100110000000111110101000111010011001000";
WHEN "101101" => p0_uid181_constMult_q <= "011111001100010000111000110110100011111110000101111000011000110011110";
WHEN "101110" => p0_uid181_constMult_q <= "011111111000101000000001001110100001111011001101000111110111001110100";
WHEN "101111" => p0_uid181_constMult_q <= "100000100100111111001001100110011111111000010100010111010101101001010";
WHEN "110000" => p0_uid181_constMult_q <= "100001010001010110010001111110011101110101011011100110110100000100000";
WHEN "110001" => p0_uid181_constMult_q <= "100001111101101101011010010110011011110010100010110110010010011110110";
WHEN "110010" => p0_uid181_constMult_q <= "100010101010000100100010101110011001101111101010000101110000111001100";
WHEN "110011" => p0_uid181_constMult_q <= "100011010110011011101011000110010111101100110001010101001111010100010";
WHEN "110100" => p0_uid181_constMult_q <= "100100000010110010110011011110010101101001111000100100101101101111000";
WHEN "110101" => p0_uid181_constMult_q <= "100100101111001001111011110110010011100110111111110100001100001001110";
WHEN "110110" => p0_uid181_constMult_q <= "100101011011100001000100001110010001100100000111000011101010100100100";
WHEN "110111" => p0_uid181_constMult_q <= "100110000111111000001100100110001111100001001110010011001000111111010";
WHEN "111000" => p0_uid181_constMult_q <= "100110110100001111010100111110001101011110010101100010100111011010000";
WHEN "111001" => p0_uid181_constMult_q <= "100111100000100110011101010110001011011011011100110010000101110100110";
WHEN "111010" => p0_uid181_constMult_q <= "101000001100111101100101101110001001011000100100000001100100001111100";
WHEN "111011" => p0_uid181_constMult_q <= "101000111001010100101110000110000111010101101011010001000010101010010";
WHEN "111100" => p0_uid181_constMult_q <= "101001100101101011110110011110000101010010110010100000100001000101000";
WHEN "111101" => p0_uid181_constMult_q <= "101010010010000010111110110110000011001111111001101111111111011111110";
WHEN "111110" => p0_uid181_constMult_q <= "101010111110011010000111001110000001001101000000111111011101111010100";
WHEN "111111" => p0_uid181_constMult_q <= "101011101010110001001111100101111111001010001000001110111100010101010";
WHEN OTHERS =>
p0_uid181_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid177_constMult(BITSELECT,176)@8
xv1_uid177_constMult_in <= ePreRnd_uid46_fpExpETest_b(11 downto 0);
xv1_uid177_constMult_b <= xv1_uid177_constMult_in(11 downto 6);
--ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a(DELAY,825)@8
ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => xv1_uid177_constMult_b, xout => ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0(REG,371)@9
reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q <= ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p1_uid180_constMult(LOOKUP,179)@10
p1_uid180_constMult: PROCESS (reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q) IS
WHEN "000000" => p1_uid180_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid180_constMult_q <= "000000101100010111001000010111111101111101000111001111011110011010110000000";
WHEN "000010" => p1_uid180_constMult_q <= "000001011000101110010000101111111011111010001110011110111100110101100000000";
WHEN "000011" => p1_uid180_constMult_q <= "000010000101000101011001000111111001110111010101101110011011010000010000000";
WHEN "000100" => p1_uid180_constMult_q <= "000010110001011100100001011111110111110100011100111101111001101011000000000";
WHEN "000101" => p1_uid180_constMult_q <= "000011011101110011101001110111110101110001100100001101011000000101110000000";
WHEN "000110" => p1_uid180_constMult_q <= "000100001010001010110010001111110011101110101011011100110110100000100000000";
WHEN "000111" => p1_uid180_constMult_q <= "000100110110100001111010100111110001101011110010101100010100111011010000000";
WHEN "001000" => p1_uid180_constMult_q <= "000101100010111001000010111111101111101000111001111011110011010110000000000";
WHEN "001001" => p1_uid180_constMult_q <= "000110001111010000001011010111101101100110000001001011010001110000110000000";
WHEN "001010" => p1_uid180_constMult_q <= "000110111011100111010011101111101011100011001000011010110000001011100000000";
WHEN "001011" => p1_uid180_constMult_q <= "000111100111111110011100000111101001100000001111101010001110100110010000000";
WHEN "001100" => p1_uid180_constMult_q <= "001000010100010101100100011111100111011101010110111001101101000001000000000";
WHEN "001101" => p1_uid180_constMult_q <= "001001000000101100101100110111100101011010011110001001001011011011110000000";
WHEN "001110" => p1_uid180_constMult_q <= "001001101101000011110101001111100011010111100101011000101001110110100000000";
WHEN "001111" => p1_uid180_constMult_q <= "001010011001011010111101100111100001010100101100101000001000010001010000000";
WHEN "010000" => p1_uid180_constMult_q <= "001011000101110010000101111111011111010001110011110111100110101100000000000";
WHEN "010001" => p1_uid180_constMult_q <= "001011110010001001001110010111011101001110111011000111000101000110110000000";
WHEN "010010" => p1_uid180_constMult_q <= "001100011110100000010110101111011011001100000010010110100011100001100000000";
WHEN "010011" => p1_uid180_constMult_q <= "001101001010110111011111000111011001001001001001100110000001111100010000000";
WHEN "010100" => p1_uid180_constMult_q <= "001101110111001110100111011111010111000110010000110101100000010111000000000";
WHEN "010101" => p1_uid180_constMult_q <= "001110100011100101101111110111010101000011011000000100111110110001110000000";
WHEN "010110" => p1_uid180_constMult_q <= "001111001111111100111000001111010011000000011111010100011101001100100000000";
WHEN "010111" => p1_uid180_constMult_q <= "001111111100010100000000100111010000111101100110100011111011100111010000000";
WHEN "011000" => p1_uid180_constMult_q <= "010000101000101011001000111111001110111010101101110011011010000010000000000";
WHEN "011001" => p1_uid180_constMult_q <= "010001010101000010010001010111001100110111110101000010111000011100110000000";
WHEN "011010" => p1_uid180_constMult_q <= "010010000001011001011001101111001010110100111100010010010110110111100000000";
WHEN "011011" => p1_uid180_constMult_q <= "010010101101110000100010000111001000110010000011100001110101010010010000000";
WHEN "011100" => p1_uid180_constMult_q <= "010011011010000111101010011111000110101111001010110001010011101101000000000";
WHEN "011101" => p1_uid180_constMult_q <= "010100000110011110110010110111000100101100010010000000110010000111110000000";
WHEN "011110" => p1_uid180_constMult_q <= "010100110010110101111011001111000010101001011001010000010000100010100000000";
WHEN "011111" => p1_uid180_constMult_q <= "010101011111001101000011100111000000100110100000011111101110111101010000000";
WHEN "100000" => p1_uid180_constMult_q <= "010110001011100100001011111110111110100011100111101111001101011000000000000";
WHEN "100001" => p1_uid180_constMult_q <= "010110110111111011010100010110111100100000101110111110101011110010110000000";
WHEN "100010" => p1_uid180_constMult_q <= "010111100100010010011100101110111010011101110110001110001010001101100000000";
WHEN "100011" => p1_uid180_constMult_q <= "011000010000101001100101000110111000011010111101011101101000101000010000000";
WHEN "100100" => p1_uid180_constMult_q <= "011000111101000000101101011110110110011000000100101101000111000011000000000";
WHEN "100101" => p1_uid180_constMult_q <= "011001101001010111110101110110110100010101001011111100100101011101110000000";
WHEN "100110" => p1_uid180_constMult_q <= "011010010101101110111110001110110010010010010011001100000011111000100000000";
WHEN "100111" => p1_uid180_constMult_q <= "011011000010000110000110100110110000001111011010011011100010010011010000000";
WHEN "101000" => p1_uid180_constMult_q <= "011011101110011101001110111110101110001100100001101011000000101110000000000";
WHEN "101001" => p1_uid180_constMult_q <= "011100011010110100010111010110101100001001101000111010011111001000110000000";
WHEN "101010" => p1_uid180_constMult_q <= "011101000111001011011111101110101010000110110000001001111101100011100000000";
WHEN "101011" => p1_uid180_constMult_q <= "011101110011100010101000000110101000000011110111011001011011111110010000000";
WHEN "101100" => p1_uid180_constMult_q <= "011110011111111001110000011110100110000000111110101000111010011001000000000";
WHEN "101101" => p1_uid180_constMult_q <= "011111001100010000111000110110100011111110000101111000011000110011110000000";
WHEN "101110" => p1_uid180_constMult_q <= "011111111000101000000001001110100001111011001101000111110111001110100000000";
WHEN "101111" => p1_uid180_constMult_q <= "100000100100111111001001100110011111111000010100010111010101101001010000000";
WHEN "110000" => p1_uid180_constMult_q <= "100001010001010110010001111110011101110101011011100110110100000100000000000";
WHEN "110001" => p1_uid180_constMult_q <= "100001111101101101011010010110011011110010100010110110010010011110110000000";
WHEN "110010" => p1_uid180_constMult_q <= "100010101010000100100010101110011001101111101010000101110000111001100000000";
WHEN "110011" => p1_uid180_constMult_q <= "100011010110011011101011000110010111101100110001010101001111010100010000000";
WHEN "110100" => p1_uid180_constMult_q <= "100100000010110010110011011110010101101001111000100100101101101111000000000";
WHEN "110101" => p1_uid180_constMult_q <= "100100101111001001111011110110010011100110111111110100001100001001110000000";
WHEN "110110" => p1_uid180_constMult_q <= "100101011011100001000100001110010001100100000111000011101010100100100000000";
WHEN "110111" => p1_uid180_constMult_q <= "100110000111111000001100100110001111100001001110010011001000111111010000000";
WHEN "111000" => p1_uid180_constMult_q <= "100110110100001111010100111110001101011110010101100010100111011010000000000";
WHEN "111001" => p1_uid180_constMult_q <= "100111100000100110011101010110001011011011011100110010000101110100110000000";
WHEN "111010" => p1_uid180_constMult_q <= "101000001100111101100101101110001001011000100100000001100100001111100000000";
WHEN "111011" => p1_uid180_constMult_q <= "101000111001010100101110000110000111010101101011010001000010101010010000000";
WHEN "111100" => p1_uid180_constMult_q <= "101001100101101011110110011110000101010010110010100000100001000101000000000";
WHEN "111101" => p1_uid180_constMult_q <= "101010010010000010111110110110000011001111111001101111111111011111110000000";
WHEN "111110" => p1_uid180_constMult_q <= "101010111110011010000111001110000001001101000000111111011101111010100000000";
WHEN "111111" => p1_uid180_constMult_q <= "101011101010110001001111100101111111001010001000001110111100010101010000000";
WHEN OTHERS =>
p1_uid180_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv2_uid178_constMult(BITSELECT,177)@8
xv2_uid178_constMult_in <= ePreRnd_uid46_fpExpETest_b;
xv2_uid178_constMult_b <= xv2_uid178_constMult_in(13 downto 12);
--reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0(REG,370)@8
reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q <= xv2_uid178_constMult_b;
END IF;
END IF;
END PROCESS;
--p2_uid179_constMult(LOOKUP,178)@9
p2_uid179_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p2_uid179_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q) IS
WHEN "00" => p2_uid179_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "01" => p2_uid179_constMult_q <= "00101100010111001000010111111101111101000111001111011110011010110000000000000";
WHEN "10" => p2_uid179_constMult_q <= "10100111010001101111010000000100000101110001100001000011001010100000000000000";
WHEN "11" => p2_uid179_constMult_q <= "11010011101000110111101000000010000010111000110000100001100101010000000000000";
WHEN OTHERS =>
p2_uid179_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid182_constMult(ADD,181)@10
lev1_a0_uid182_constMult_a <= STD_LOGIC_VECTOR((78 downto 77 => p2_uid179_constMult_q(76)) & p2_uid179_constMult_q);
lev1_a0_uid182_constMult_b <= STD_LOGIC_VECTOR('0' & "000" & p1_uid180_constMult_q);
lev1_a0_uid182_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev1_a0_uid182_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev1_a0_uid182_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid182_constMult_a) + SIGNED(lev1_a0_uid182_constMult_b));
END IF;
END IF;
END PROCESS;
lev1_a0_uid182_constMult_q <= lev1_a0_uid182_constMult_o(77 downto 0);
--lev2_a0_uid183_constMult(ADD,182)@11
lev2_a0_uid183_constMult_a <= STD_LOGIC_VECTOR((79 downto 78 => lev1_a0_uid182_constMult_q(77)) & lev1_a0_uid182_constMult_q);
lev2_a0_uid183_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000" & p0_uid181_constMult_q);
lev2_a0_uid183_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev2_a0_uid183_constMult_a) + SIGNED(lev2_a0_uid183_constMult_b));
lev2_a0_uid183_constMult_q <= lev2_a0_uid183_constMult_o(78 downto 0);
--sR_uid184_constMult(BITSELECT,183)@11
sR_uid184_constMult_in <= lev2_a0_uid183_constMult_q(76 downto 0);
sR_uid184_constMult_b <= sR_uid184_constMult_in(76 downto 2);
--reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1(REG,374)@11
reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q <= sR_uid184_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b(DELAY,456)@0
ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 8 )
PORT MAP ( xin => signX_uid7_fpExpETest_b, xout => ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor(LOGICAL,898)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_b <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_q <= not (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_a or ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_b);
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top(CONSTANT,894)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top_q <= "0101";
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp(LOGICAL,895)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_a <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q);
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_q <= "1" when ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_a = ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_b else "0";
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg(REG,896)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena(REG,899)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_q = "1") THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd(LOGICAL,900)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_a <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_b <= en;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_a and ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_b;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg(DELAY,888)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oFracX_uid32_uid32_fpExpETest_q, xout => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt(COUNTER,890)
-- every=1, low=0, high=5, step=1, init=1
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i = 4 THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i - 5;
ELSE
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i,3));
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg(REG,891)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux(MUX,892)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s <= en;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux: PROCESS (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s, ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q, ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem(DUALMEM,889)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ia <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_aa <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ab <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 6,
width_b => 53,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_iq,
address_a => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_aa,
data_a => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ia
);
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_reset0 <= areset;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_iq(52 downto 0);
--cstZeroWEP1_uid12_fpExpETest(CONSTANT,11)
cstZeroWEP1_uid12_fpExpETest_q <= "000000000000";
--oFracXZwE_uid48_fpExpETest(BITJOIN,47)@8
oFracXZwE_uid48_fpExpETest_q <= GND_q & ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_q & cstZeroWEP1_uid12_fpExpETest_q;
--onesCmpFxpIn_uid49_fpExpETest(LOGICAL,48)@8
onesCmpFxpIn_uid49_fpExpETest_a <= oFracXZwE_uid48_fpExpETest_q;
onesCmpFxpIn_uid49_fpExpETest_b <= STD_LOGIC_VECTOR((65 downto 1 => ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q(0)) & ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q);
onesCmpFxpIn_uid49_fpExpETest_q <= onesCmpFxpIn_uid49_fpExpETest_a xor onesCmpFxpIn_uid49_fpExpETest_b;
--fxpInExt_uid50_fpExpETest(ADD,49)@8
fxpInExt_uid50_fpExpETest_a <= STD_LOGIC_VECTOR((67 downto 66 => onesCmpFxpIn_uid49_fpExpETest_q(65)) & onesCmpFxpIn_uid49_fpExpETest_q);
fxpInExt_uid50_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q);
fxpInExt_uid50_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid50_fpExpETest_a) + SIGNED(fxpInExt_uid50_fpExpETest_b));
fxpInExt_uid50_fpExpETest_q <= fxpInExt_uid50_fpExpETest_o(66 downto 0);
--fxpInPreAlign_uid51_fpExpETest(BITSELECT,50)@8
fxpInPreAlign_uid51_fpExpETest_in <= fxpInExt_uid50_fpExpETest_q(65 downto 0);
fxpInPreAlign_uid51_fpExpETest_b <= fxpInPreAlign_uid51_fpExpETest_in(65 downto 0);
--msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,185)@8
msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_in <= fxpInPreAlign_uid51_fpExpETest_b;
msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b <= msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 65);
--rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,227)@8
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_a <= GND_q;
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_b <= msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,670)@9
ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q, xout => ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,228)@11
RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 1);
--rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,229)@11
rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q <= ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b_q & RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_b;
--ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,650)@8
ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,221)@10
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid163_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,633)@8
ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,207)@9
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid149_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest(CONSTANT,194)
rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest_q <= "000000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,195)@8
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_a <= rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest_q;
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((65 downto 1 => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b(0)) & msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b);
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 66, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,191)@8
rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid133_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b(0)) & msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b);
rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_b;
--X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,192)@8
X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_in <= fxpInPreAlign_uid51_fpExpETest_b;
X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_b <= X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 64);
--rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,193)@8
rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_q & X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_b;
--reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4(REG,364)@8
reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q <= rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,187)@8
rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid129_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b(0)) & msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b);
rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_b;
--X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,188)@8
X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_in <= fxpInPreAlign_uid51_fpExpETest_b;
X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_b <= X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 32);
--rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,189)@8
rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_q & X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_b;
--reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3(REG,363)@8
reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q <= rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2(REG,362)@8
reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q <= fxpInPreAlign_uid51_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,628)@6
ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 3 )
PORT MAP ( xin => reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q, xout => ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest(MUX,197)@9
rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s <= ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b_q;
rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s, en, reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q, reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q, reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q, rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "00" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q;
WHEN "01" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q;
WHEN "10" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q;
WHEN "11" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,208)@9
RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 24);
--ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,643)@9
ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,209)@10
rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,203)@9
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid145_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,204)@9
RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 16);
--ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,639)@9
ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,205)@10
rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,199)@9
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid141_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,200)@9
RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 8);
--ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,635)@9
ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,201)@10
rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2(REG,366)@9
reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1(REG,365)@5
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q <= rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,645)@6
ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 4 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest(MUX,211)@10
rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s <= ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b_q;
rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s, en, reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q, rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "00" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q;
WHEN "01" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "10" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "11" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,222)@10
RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 6);
--ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,660)@10
ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,223)@11
rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,217)@10
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid159_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,218)@10
RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 4);
--ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,656)@10
ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,219)@11
rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,213)@10
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid155_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,214)@10
RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 2);
--ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,652)@10
ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,215)@11
rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2(REG,368)@10
reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a(DELAY,821)@5
ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 5 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1(REG,367)@10
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q <= ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest(MUX,225)@11
rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s <= reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q;
rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s, en, reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q, rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "00" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q;
WHEN "01" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "10" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "11" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1(REG,369)@5
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q <= rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,671)@6
ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest(MUX,231)@11
rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s <= ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b_q;
rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s, en, rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "0" => rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "1" => rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest(BITJOIN,56)@11
pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_q <= rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0(REG,373)@11
reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q <= pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--yExt_uid57_fpExpETest(SUB,57)@12
yExt_uid57_fpExpETest_a <= STD_LOGIC_VECTOR((75 downto 74 => reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q(73)) & reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q);
yExt_uid57_fpExpETest_b <= STD_LOGIC_VECTOR((75 downto 75 => reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q(74)) & reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q);
yExt_uid57_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(yExt_uid57_fpExpETest_a) - SIGNED(yExt_uid57_fpExpETest_b));
yExt_uid57_fpExpETest_q <= yExt_uid57_fpExpETest_o(75 downto 0);
--yRed_uid61_fpExpETest(BITSELECT,60)@12
yRed_uid61_fpExpETest_in <= yExt_uid57_fpExpETest_q(60 downto 0);
yRed_uid61_fpExpETest_b <= yRed_uid61_fpExpETest_in(60 downto 6);
--reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2(REG,376)@12
reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q <= yRed_uid61_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--YExt75_uid59_fpExpETest(BITSELECT,58)@12
YExt75_uid59_fpExpETest_in <= yExt_uid57_fpExpETest_q;
YExt75_uid59_fpExpETest_b <= YExt75_uid59_fpExpETest_in(75 downto 75);
--reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1(REG,375)@12
reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q <= YExt75_uid59_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--yRedPostMux_uid62_fpExpETest(MUX,61)@13
yRedPostMux_uid62_fpExpETest_s <= reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q;
yRedPostMux_uid62_fpExpETest: PROCESS (yRedPostMux_uid62_fpExpETest_s, en, reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q, zY_uid60_fpExpETest_q)
BEGIN
CASE yRedPostMux_uid62_fpExpETest_s IS
WHEN "0" => yRedPostMux_uid62_fpExpETest_q <= reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q;
WHEN "1" => yRedPostMux_uid62_fpExpETest_q <= zY_uid60_fpExpETest_q;
WHEN OTHERS => yRedPostMux_uid62_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid64_fpExpETest(BITSELECT,63)@13
addr_uid64_fpExpETest_in <= yRedPostMux_uid62_fpExpETest_q;
addr_uid64_fpExpETest_b <= addr_uid64_fpExpETest_in(54 downto 48);
--reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0(REG,378)@13
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q <= addr_uid64_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid247_exp10TabGen(LOOKUP,246)@14
memoryC5_uid247_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC5_uid247_exp10TabGen_q <= "0010001001000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC5_uid247_exp10TabGen_q <= "0010001001000001";
WHEN "0000001" => memoryC5_uid247_exp10TabGen_q <= "0010001001001000";
WHEN "0000010" => memoryC5_uid247_exp10TabGen_q <= "0010001010101001";
WHEN "0000011" => memoryC5_uid247_exp10TabGen_q <= "0010001011011100";
WHEN "0000100" => memoryC5_uid247_exp10TabGen_q <= "0010001101001010";
WHEN "0000101" => memoryC5_uid247_exp10TabGen_q <= "0010001110011101";
WHEN "0000110" => memoryC5_uid247_exp10TabGen_q <= "0010001111011110";
WHEN "0000111" => memoryC5_uid247_exp10TabGen_q <= "0010010000100001";
WHEN "0001000" => memoryC5_uid247_exp10TabGen_q <= "0010010001111001";
WHEN "0001001" => memoryC5_uid247_exp10TabGen_q <= "0010010010110011";
WHEN "0001010" => memoryC5_uid247_exp10TabGen_q <= "0010010100011101";
WHEN "0001011" => memoryC5_uid247_exp10TabGen_q <= "0010010110010001";
WHEN "0001100" => memoryC5_uid247_exp10TabGen_q <= "0010010110110101";
WHEN "0001101" => memoryC5_uid247_exp10TabGen_q <= "0010010111001010";
WHEN "0001110" => memoryC5_uid247_exp10TabGen_q <= "0010011000110010";
WHEN "0001111" => memoryC5_uid247_exp10TabGen_q <= "0010011010111110";
WHEN "0010000" => memoryC5_uid247_exp10TabGen_q <= "0010011010111110";
WHEN "0010001" => memoryC5_uid247_exp10TabGen_q <= "0010011100001100";
WHEN "0010010" => memoryC5_uid247_exp10TabGen_q <= "0010011110000010";
WHEN "0010011" => memoryC5_uid247_exp10TabGen_q <= "0010011110101001";
WHEN "0010100" => memoryC5_uid247_exp10TabGen_q <= "0010100001000000";
WHEN "0010101" => memoryC5_uid247_exp10TabGen_q <= "0010100001011000";
WHEN "0010110" => memoryC5_uid247_exp10TabGen_q <= "0010100011000011";
WHEN "0010111" => memoryC5_uid247_exp10TabGen_q <= "0010100011110110";
WHEN "0011000" => memoryC5_uid247_exp10TabGen_q <= "0010100101111001";
WHEN "0011001" => memoryC5_uid247_exp10TabGen_q <= "0010100111010011";
WHEN "0011010" => memoryC5_uid247_exp10TabGen_q <= "0010100111110111";
WHEN "0011011" => memoryC5_uid247_exp10TabGen_q <= "0010101001011010";
WHEN "0011100" => memoryC5_uid247_exp10TabGen_q <= "0010101011000110";
WHEN "0011101" => memoryC5_uid247_exp10TabGen_q <= "0010101100100101";
WHEN "0011110" => memoryC5_uid247_exp10TabGen_q <= "0010101110000010";
WHEN "0011111" => memoryC5_uid247_exp10TabGen_q <= "0010101110001011";
WHEN "0100000" => memoryC5_uid247_exp10TabGen_q <= "0010110000000101";
WHEN "0100001" => memoryC5_uid247_exp10TabGen_q <= "0010110001011010";
WHEN "0100010" => memoryC5_uid247_exp10TabGen_q <= "0010110010000000";
WHEN "0100011" => memoryC5_uid247_exp10TabGen_q <= "0010110011110100";
WHEN "0100100" => memoryC5_uid247_exp10TabGen_q <= "0010110101111111";
WHEN "0100101" => memoryC5_uid247_exp10TabGen_q <= "0010110110001011";
WHEN "0100110" => memoryC5_uid247_exp10TabGen_q <= "0010111000011100";
WHEN "0100111" => memoryC5_uid247_exp10TabGen_q <= "0010111001101110";
WHEN "0101000" => memoryC5_uid247_exp10TabGen_q <= "0010111010111100";
WHEN "0101001" => memoryC5_uid247_exp10TabGen_q <= "0010111100100000";
WHEN "0101010" => memoryC5_uid247_exp10TabGen_q <= "0010111111001011";
WHEN "0101011" => memoryC5_uid247_exp10TabGen_q <= "0010111111101000";
WHEN "0101100" => memoryC5_uid247_exp10TabGen_q <= "0011000001111110";
WHEN "0101101" => memoryC5_uid247_exp10TabGen_q <= "0011000010101011";
WHEN "0101110" => memoryC5_uid247_exp10TabGen_q <= "0011000011100011";
WHEN "0101111" => memoryC5_uid247_exp10TabGen_q <= "0011000110001011";
WHEN "0110000" => memoryC5_uid247_exp10TabGen_q <= "0011000111101010";
WHEN "0110001" => memoryC5_uid247_exp10TabGen_q <= "0011001001011010";
WHEN "0110010" => memoryC5_uid247_exp10TabGen_q <= "0011001010111110";
WHEN "0110011" => memoryC5_uid247_exp10TabGen_q <= "0011001100101111";
WHEN "0110100" => memoryC5_uid247_exp10TabGen_q <= "0011001101111011";
WHEN "0110101" => memoryC5_uid247_exp10TabGen_q <= "0011001110111001";
WHEN "0110110" => memoryC5_uid247_exp10TabGen_q <= "0011010001010100";
WHEN "0110111" => memoryC5_uid247_exp10TabGen_q <= "0011010011001110";
WHEN "0111000" => memoryC5_uid247_exp10TabGen_q <= "0011010100011010";
WHEN "0111001" => memoryC5_uid247_exp10TabGen_q <= "0011010110001011";
WHEN "0111010" => memoryC5_uid247_exp10TabGen_q <= "0011010111100000";
WHEN "0111011" => memoryC5_uid247_exp10TabGen_q <= "0011011000111110";
WHEN "0111100" => memoryC5_uid247_exp10TabGen_q <= "0011011010100100";
WHEN "0111101" => memoryC5_uid247_exp10TabGen_q <= "0011011100101101";
WHEN "0111110" => memoryC5_uid247_exp10TabGen_q <= "0011011110000100";
WHEN "0111111" => memoryC5_uid247_exp10TabGen_q <= "0011100000111010";
WHEN "1000000" => memoryC5_uid247_exp10TabGen_q <= "0011100010101001";
WHEN "1000001" => memoryC5_uid247_exp10TabGen_q <= "0011100011011011";
WHEN "1000010" => memoryC5_uid247_exp10TabGen_q <= "0011100100101101";
WHEN "1000011" => memoryC5_uid247_exp10TabGen_q <= "0011100111101001";
WHEN "1000100" => memoryC5_uid247_exp10TabGen_q <= "0011101001001000";
WHEN "1000101" => memoryC5_uid247_exp10TabGen_q <= "0011101010110010";
WHEN "1000110" => memoryC5_uid247_exp10TabGen_q <= "0011101101011011";
WHEN "1000111" => memoryC5_uid247_exp10TabGen_q <= "0011101110010100";
WHEN "1001000" => memoryC5_uid247_exp10TabGen_q <= "0011110000111010";
WHEN "1001001" => memoryC5_uid247_exp10TabGen_q <= "0011110010100100";
WHEN "1001010" => memoryC5_uid247_exp10TabGen_q <= "0011110100011110";
WHEN "1001011" => memoryC5_uid247_exp10TabGen_q <= "0011110101101011";
WHEN "1001100" => memoryC5_uid247_exp10TabGen_q <= "0011110111101011";
WHEN "1001101" => memoryC5_uid247_exp10TabGen_q <= "0011111001110000";
WHEN "1001110" => memoryC5_uid247_exp10TabGen_q <= "0011111100000010";
WHEN "1001111" => memoryC5_uid247_exp10TabGen_q <= "0011111110001010";
WHEN "1010000" => memoryC5_uid247_exp10TabGen_q <= "0011111111110011";
WHEN "1010001" => memoryC5_uid247_exp10TabGen_q <= "0100000010000111";
WHEN "1010010" => memoryC5_uid247_exp10TabGen_q <= "0100000011100011";
WHEN "1010011" => memoryC5_uid247_exp10TabGen_q <= "0100000101110000";
WHEN "1010100" => memoryC5_uid247_exp10TabGen_q <= "0100000111111001";
WHEN "1010101" => memoryC5_uid247_exp10TabGen_q <= "0100001010101100";
WHEN "1010110" => memoryC5_uid247_exp10TabGen_q <= "0100001100100110";
WHEN "1010111" => memoryC5_uid247_exp10TabGen_q <= "0100001110000000";
WHEN "1011000" => memoryC5_uid247_exp10TabGen_q <= "0100010000010100";
WHEN "1011001" => memoryC5_uid247_exp10TabGen_q <= "0100010010100001";
WHEN "1011010" => memoryC5_uid247_exp10TabGen_q <= "0100010101011001";
WHEN "1011011" => memoryC5_uid247_exp10TabGen_q <= "0100011000000001";
WHEN "1011100" => memoryC5_uid247_exp10TabGen_q <= "0100011000101011";
WHEN "1011101" => memoryC5_uid247_exp10TabGen_q <= "0100011011000001";
WHEN "1011110" => memoryC5_uid247_exp10TabGen_q <= "0100011110001011";
WHEN "1011111" => memoryC5_uid247_exp10TabGen_q <= "0100100000010001";
WHEN "1100000" => memoryC5_uid247_exp10TabGen_q <= "0100100010001001";
WHEN "1100001" => memoryC5_uid247_exp10TabGen_q <= "0100100100101000";
WHEN "1100010" => memoryC5_uid247_exp10TabGen_q <= "0100100111010100";
WHEN "1100011" => memoryC5_uid247_exp10TabGen_q <= "0100101000111000";
WHEN "1100100" => memoryC5_uid247_exp10TabGen_q <= "0100101011100001";
WHEN "1100101" => memoryC5_uid247_exp10TabGen_q <= "0100101110010110";
WHEN "1100110" => memoryC5_uid247_exp10TabGen_q <= "0100110000100110";
WHEN "1100111" => memoryC5_uid247_exp10TabGen_q <= "0100110011000110";
WHEN "1101000" => memoryC5_uid247_exp10TabGen_q <= "0100110100111001";
WHEN "1101001" => memoryC5_uid247_exp10TabGen_q <= "0100110111010000";
WHEN "1101010" => memoryC5_uid247_exp10TabGen_q <= "0100111010100101";
WHEN "1101011" => memoryC5_uid247_exp10TabGen_q <= "0100111011110011";
WHEN "1101100" => memoryC5_uid247_exp10TabGen_q <= "0100111110000101";
WHEN "1101101" => memoryC5_uid247_exp10TabGen_q <= "0101000001001101";
WHEN "1101110" => memoryC5_uid247_exp10TabGen_q <= "0101000100000110";
WHEN "1101111" => memoryC5_uid247_exp10TabGen_q <= "0101000101110010";
WHEN "1110000" => memoryC5_uid247_exp10TabGen_q <= "0101001000100011";
WHEN "1110001" => memoryC5_uid247_exp10TabGen_q <= "0101001011000111";
WHEN "1110010" => memoryC5_uid247_exp10TabGen_q <= "0101001101110100";
WHEN "1110011" => memoryC5_uid247_exp10TabGen_q <= "0101010000111001";
WHEN "1110100" => memoryC5_uid247_exp10TabGen_q <= "0101010010100101";
WHEN "1110101" => memoryC5_uid247_exp10TabGen_q <= "0101010110001010";
WHEN "1110110" => memoryC5_uid247_exp10TabGen_q <= "0101011000010010";
WHEN "1110111" => memoryC5_uid247_exp10TabGen_q <= "0101011010111100";
WHEN "1111000" => memoryC5_uid247_exp10TabGen_q <= "0101011110010101";
WHEN "1111001" => memoryC5_uid247_exp10TabGen_q <= "0101011111111010";
WHEN "1111010" => memoryC5_uid247_exp10TabGen_q <= "0101100011000011";
WHEN "1111011" => memoryC5_uid247_exp10TabGen_q <= "0101100101011100";
WHEN "1111100" => memoryC5_uid247_exp10TabGen_q <= "0101101000101110";
WHEN "1111101" => memoryC5_uid247_exp10TabGen_q <= "0101101011100111";
WHEN "1111110" => memoryC5_uid247_exp10TabGen_q <= "0101101111011111";
WHEN "1111111" => memoryC5_uid247_exp10TabGen_q <= "0101110001010100";
WHEN OTHERS =>
memoryC5_uid247_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a(DELAY,468)@13
ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => yRedPostMux_uid62_fpExpETest_q, xout => ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid65_fpExpETest(BITSELECT,64)@14
yPPolyEval_uid65_fpExpETest_in <= ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a_q(47 downto 0);
yPPolyEval_uid65_fpExpETest_b <= yPPolyEval_uid65_fpExpETest_in(47 downto 0);
--yT1_uid249_exp10PolyEval(BITSELECT,248)@14
yT1_uid249_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
yT1_uid249_exp10PolyEval_b <= yT1_uid249_exp10PolyEval_in(47 downto 32);
--reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0(REG,384)@14
reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q <= yT1_uid249_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid280_pT1_uid250_exp10PolyEval(MULT,279)@15
prodXY_uid280_pT1_uid250_exp10PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid280_pT1_uid250_exp10PolyEval_a),17)) * SIGNED(prodXY_uid280_pT1_uid250_exp10PolyEval_b);
prodXY_uid280_pT1_uid250_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_a <= (others => '0');
prodXY_uid280_pT1_uid250_exp10PolyEval_b <= (others => '0');
prodXY_uid280_pT1_uid250_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_a <= reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q;
prodXY_uid280_pT1_uid250_exp10PolyEval_b <= memoryC5_uid247_exp10TabGen_q;
prodXY_uid280_pT1_uid250_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid280_pT1_uid250_exp10PolyEval_pr,32));
END IF;
END IF;
END PROCESS;
prodXY_uid280_pT1_uid250_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_q <= prodXY_uid280_pT1_uid250_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval(BITSELECT,280)@18
prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_in <= prodXY_uid280_pT1_uid250_exp10PolyEval_q;
prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b <= prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_in(31 downto 15);
--highBBits_uid252_exp10PolyEval(BITSELECT,251)@18
highBBits_uid252_exp10PolyEval_in <= prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b;
highBBits_uid252_exp10PolyEval_b <= highBBits_uid252_exp10PolyEval_in(16 downto 1);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a(DELAY,687)@14
ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q, xout => ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid245_exp10TabGen(LOOKUP,244)@17
memoryC4_uid245_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC4_uid245_exp10TabGen_q <= "0010101010101010100110111";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a_q) IS
WHEN "0000000" => memoryC4_uid245_exp10TabGen_q <= "0010101010101010100110111";
WHEN "0000001" => memoryC4_uid245_exp10TabGen_q <= "0010101100000000100101110";
WHEN "0000010" => memoryC4_uid245_exp10TabGen_q <= "0010101101010110110010011";
WHEN "0000011" => memoryC4_uid245_exp10TabGen_q <= "0010101110101101111001001";
WHEN "0000100" => memoryC4_uid245_exp10TabGen_q <= "0010110000000101011001111";
WHEN "0000101" => memoryC4_uid245_exp10TabGen_q <= "0010110001011101101101111";
WHEN "0000110" => memoryC4_uid245_exp10TabGen_q <= "0010110010110110110100011";
WHEN "0000111" => memoryC4_uid245_exp10TabGen_q <= "0010110100010000101001111";
WHEN "0001000" => memoryC4_uid245_exp10TabGen_q <= "0010110101101011000011010";
WHEN "0001001" => memoryC4_uid245_exp10TabGen_q <= "0010110111000110010011101";
WHEN "0001010" => memoryC4_uid245_exp10TabGen_q <= "0010111000100010000011100";
WHEN "0001011" => memoryC4_uid245_exp10TabGen_q <= "0010111001111110011110010";
WHEN "0001100" => memoryC4_uid245_exp10TabGen_q <= "0010111011011100000001001";
WHEN "0001101" => memoryC4_uid245_exp10TabGen_q <= "0010111100111010011010011";
WHEN "0001110" => memoryC4_uid245_exp10TabGen_q <= "0010111110011001000101000";
WHEN "0001111" => memoryC4_uid245_exp10TabGen_q <= "0010111111111000010100011";
WHEN "0010000" => memoryC4_uid245_exp10TabGen_q <= "0011000001011001000010010";
WHEN "0010001" => memoryC4_uid245_exp10TabGen_q <= "0011000010111010001000011";
WHEN "0010010" => memoryC4_uid245_exp10TabGen_q <= "0011000100011011101101111";
WHEN "0010011" => memoryC4_uid245_exp10TabGen_q <= "0011000101111110100011110";
WHEN "0010100" => memoryC4_uid245_exp10TabGen_q <= "0011000111100001100011000";
WHEN "0010101" => memoryC4_uid245_exp10TabGen_q <= "0011001001000101111111111";
WHEN "0010110" => memoryC4_uid245_exp10TabGen_q <= "0011001010101010110100100";
WHEN "0010111" => memoryC4_uid245_exp10TabGen_q <= "0011001100010000101101011";
WHEN "0011000" => memoryC4_uid245_exp10TabGen_q <= "0011001101110110111101111";
WHEN "0011001" => memoryC4_uid245_exp10TabGen_q <= "0011001111011110010000111";
WHEN "0011010" => memoryC4_uid245_exp10TabGen_q <= "0011010001000110101010101";
WHEN "0011011" => memoryC4_uid245_exp10TabGen_q <= "0011010010101111100100001";
WHEN "0011100" => memoryC4_uid245_exp10TabGen_q <= "0011010100011001001101011";
WHEN "0011101" => memoryC4_uid245_exp10TabGen_q <= "0011010110000011110001011";
WHEN "0011110" => memoryC4_uid245_exp10TabGen_q <= "0011010111101111001100101";
WHEN "0011111" => memoryC4_uid245_exp10TabGen_q <= "0011011001011011111000011";
WHEN "0100000" => memoryC4_uid245_exp10TabGen_q <= "0011011011001000110101101";
WHEN "0100001" => memoryC4_uid245_exp10TabGen_q <= "0011011100110110110111000";
WHEN "0100010" => memoryC4_uid245_exp10TabGen_q <= "0011011110100101111111111";
WHEN "0100011" => memoryC4_uid245_exp10TabGen_q <= "0011100000010101100111000";
WHEN "0100100" => memoryC4_uid245_exp10TabGen_q <= "0011100010000101111100000";
WHEN "0100101" => memoryC4_uid245_exp10TabGen_q <= "0011100011110111110110010";
WHEN "0100110" => memoryC4_uid245_exp10TabGen_q <= "0011100101101001111011110";
WHEN "0100111" => memoryC4_uid245_exp10TabGen_q <= "0011100111011101010011110";
WHEN "0101000" => memoryC4_uid245_exp10TabGen_q <= "0011101001010001100010110";
WHEN "0101001" => memoryC4_uid245_exp10TabGen_q <= "0011101011000110101000000";
WHEN "0101010" => memoryC4_uid245_exp10TabGen_q <= "0011101100111100001111000";
WHEN "0101011" => memoryC4_uid245_exp10TabGen_q <= "0011101110110011100001000";
WHEN "0101100" => memoryC4_uid245_exp10TabGen_q <= "0011110000101011000101111";
WHEN "0101101" => memoryC4_uid245_exp10TabGen_q <= "0011110010100100001011000";
WHEN "0101110" => memoryC4_uid245_exp10TabGen_q <= "0011110100011110001001010";
WHEN "0101111" => memoryC4_uid245_exp10TabGen_q <= "0011110110011000011111110";
WHEN "0110000" => memoryC4_uid245_exp10TabGen_q <= "0011111000010100001101010";
WHEN "0110001" => memoryC4_uid245_exp10TabGen_q <= "0011111010010000110001010";
WHEN "0110010" => memoryC4_uid245_exp10TabGen_q <= "0011111100001110011011010";
WHEN "0110011" => memoryC4_uid245_exp10TabGen_q <= "0011111110001100111101101";
WHEN "0110100" => memoryC4_uid245_exp10TabGen_q <= "0100000000001100101011001";
WHEN "0110101" => memoryC4_uid245_exp10TabGen_q <= "0100000010001101100001011";
WHEN "0110110" => memoryC4_uid245_exp10TabGen_q <= "0100000100001110111000001";
WHEN "0110111" => memoryC4_uid245_exp10TabGen_q <= "0100000110010001011001101";
WHEN "0111000" => memoryC4_uid245_exp10TabGen_q <= "0100001000010101001110001";
WHEN "0111001" => memoryC4_uid245_exp10TabGen_q <= "0100001010011001110101000";
WHEN "0111010" => memoryC4_uid245_exp10TabGen_q <= "0100001100011111101101100";
WHEN "0111011" => memoryC4_uid245_exp10TabGen_q <= "0100001110100110100010011";
WHEN "0111100" => memoryC4_uid245_exp10TabGen_q <= "0100010000101110011010110";
WHEN "0111101" => memoryC4_uid245_exp10TabGen_q <= "0100010010110111001010011";
WHEN "0111110" => memoryC4_uid245_exp10TabGen_q <= "0100010101000001010010000";
WHEN "0111111" => memoryC4_uid245_exp10TabGen_q <= "0100010111001011111100111";
WHEN "1000000" => memoryC4_uid245_exp10TabGen_q <= "0100011001011000000110010";
WHEN "1000001" => memoryC4_uid245_exp10TabGen_q <= "0100011011100101101010011";
WHEN "1000010" => memoryC4_uid245_exp10TabGen_q <= "0100011101110100001011000";
WHEN "1000011" => memoryC4_uid245_exp10TabGen_q <= "0100100000000011010000011";
WHEN "1000100" => memoryC4_uid245_exp10TabGen_q <= "0100100010010011111101000";
WHEN "1000101" => memoryC4_uid245_exp10TabGen_q <= "0100100100100101110001011";
WHEN "1000110" => memoryC4_uid245_exp10TabGen_q <= "0100100110111000010110111";
WHEN "1000111" => memoryC4_uid245_exp10TabGen_q <= "0100101001001100101100000";
WHEN "1001000" => memoryC4_uid245_exp10TabGen_q <= "0100101011100001101000110";
WHEN "1001001" => memoryC4_uid245_exp10TabGen_q <= "0100101101111000000100100";
WHEN "1001010" => memoryC4_uid245_exp10TabGen_q <= "0100110000001111100110101";
WHEN "1001011" => memoryC4_uid245_exp10TabGen_q <= "0100110010101000100001110";
WHEN "1001100" => memoryC4_uid245_exp10TabGen_q <= "0100110101000010011011010";
WHEN "1001101" => memoryC4_uid245_exp10TabGen_q <= "0100110111011101100001110";
WHEN "1001110" => memoryC4_uid245_exp10TabGen_q <= "0100111001111001101111111";
WHEN "1001111" => memoryC4_uid245_exp10TabGen_q <= "0100111100010111010001010";
WHEN "1010000" => memoryC4_uid245_exp10TabGen_q <= "0100111110110110001011011";
WHEN "1010001" => memoryC4_uid245_exp10TabGen_q <= "0101000001010110000111110";
WHEN "1010010" => memoryC4_uid245_exp10TabGen_q <= "0101000011110111101000110";
WHEN "1010011" => memoryC4_uid245_exp10TabGen_q <= "0101000110011010000111110";
WHEN "1010100" => memoryC4_uid245_exp10TabGen_q <= "0101001000111101111101011";
WHEN "1010101" => memoryC4_uid245_exp10TabGen_q <= "0101001011100010110100011";
WHEN "1010110" => memoryC4_uid245_exp10TabGen_q <= "0101001110001001010100001";
WHEN "1010111" => memoryC4_uid245_exp10TabGen_q <= "0101010000110001010011000";
WHEN "1011000" => memoryC4_uid245_exp10TabGen_q <= "0101010011011010010000001";
WHEN "1011001" => memoryC4_uid245_exp10TabGen_q <= "0101010110000100101000010";
WHEN "1011010" => memoryC4_uid245_exp10TabGen_q <= "0101011000110000000100011";
WHEN "1011011" => memoryC4_uid245_exp10TabGen_q <= "0101011011011100111110111";
WHEN "1011100" => memoryC4_uid245_exp10TabGen_q <= "0101011110001011111000111";
WHEN "1011101" => memoryC4_uid245_exp10TabGen_q <= "0101100000111011101001000";
WHEN "1011110" => memoryC4_uid245_exp10TabGen_q <= "0101100011101100011101001";
WHEN "1011111" => memoryC4_uid245_exp10TabGen_q <= "0101100110011111000100111";
WHEN "1100000" => memoryC4_uid245_exp10TabGen_q <= "0101101001010011001001110";
WHEN "1100001" => memoryC4_uid245_exp10TabGen_q <= "0101101100001000011001111";
WHEN "1100010" => memoryC4_uid245_exp10TabGen_q <= "0101101110111111000101011";
WHEN "1100011" => memoryC4_uid245_exp10TabGen_q <= "0101110001110111100010111";
WHEN "1100100" => memoryC4_uid245_exp10TabGen_q <= "0101110100110001000110101";
WHEN "1100101" => memoryC4_uid245_exp10TabGen_q <= "0101110111101100000011000";
WHEN "1100110" => memoryC4_uid245_exp10TabGen_q <= "0101111010101000101010001";
WHEN "1100111" => memoryC4_uid245_exp10TabGen_q <= "0101111101100110101011001";
WHEN "1101000" => memoryC4_uid245_exp10TabGen_q <= "0110000000100110011100100";
WHEN "1101001" => memoryC4_uid245_exp10TabGen_q <= "0110000011100111100001001";
WHEN "1101010" => memoryC4_uid245_exp10TabGen_q <= "0110000110101001110010101";
WHEN "1101011" => memoryC4_uid245_exp10TabGen_q <= "0110001001101110010010001";
WHEN "1101100" => memoryC4_uid245_exp10TabGen_q <= "0110001100110011111111000";
WHEN "1101101" => memoryC4_uid245_exp10TabGen_q <= "0110001111111010111100010";
WHEN "1101110" => memoryC4_uid245_exp10TabGen_q <= "0110010011000011100101011";
WHEN "1101111" => memoryC4_uid245_exp10TabGen_q <= "0110010110001110001010101";
WHEN "1110000" => memoryC4_uid245_exp10TabGen_q <= "0110011001011010000010001";
WHEN "1110001" => memoryC4_uid245_exp10TabGen_q <= "0110011100100111100001011";
WHEN "1110010" => memoryC4_uid245_exp10TabGen_q <= "0110011111110110101000110";
WHEN "1110011" => memoryC4_uid245_exp10TabGen_q <= "0110100011000111001100001";
WHEN "1110100" => memoryC4_uid245_exp10TabGen_q <= "0110100110011001111010000";
WHEN "1110101" => memoryC4_uid245_exp10TabGen_q <= "0110101001101101101000011";
WHEN "1110110" => memoryC4_uid245_exp10TabGen_q <= "0110101101000011011111100";
WHEN "1110111" => memoryC4_uid245_exp10TabGen_q <= "0110110000011010111001111";
WHEN "1111000" => memoryC4_uid245_exp10TabGen_q <= "0110110011110011101100100";
WHEN "1111001" => memoryC4_uid245_exp10TabGen_q <= "0110110111001110110110100";
WHEN "1111010" => memoryC4_uid245_exp10TabGen_q <= "0110111010101011001101011";
WHEN "1111011" => memoryC4_uid245_exp10TabGen_q <= "0110111110001001100010010";
WHEN "1111100" => memoryC4_uid245_exp10TabGen_q <= "0111000001101001010101001";
WHEN "1111101" => memoryC4_uid245_exp10TabGen_q <= "0111000101001011000010001";
WHEN "1111110" => memoryC4_uid245_exp10TabGen_q <= "0111001000101110001001100";
WHEN "1111111" => memoryC4_uid245_exp10TabGen_q <= "0111001100010011101111011";
WHEN OTHERS =>
memoryC4_uid245_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid253_exp10PolyEval(ADD,252)@18
sumAHighB_uid253_exp10PolyEval_a <= STD_LOGIC_VECTOR((25 downto 25 => memoryC4_uid245_exp10TabGen_q(24)) & memoryC4_uid245_exp10TabGen_q);
sumAHighB_uid253_exp10PolyEval_b <= STD_LOGIC_VECTOR((25 downto 16 => highBBits_uid252_exp10PolyEval_b(15)) & highBBits_uid252_exp10PolyEval_b);
sumAHighB_uid253_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid253_exp10PolyEval_a) + SIGNED(sumAHighB_uid253_exp10PolyEval_b));
sumAHighB_uid253_exp10PolyEval_q <= sumAHighB_uid253_exp10PolyEval_o(25 downto 0);
--lowRangeB_uid251_exp10PolyEval(BITSELECT,250)@18
lowRangeB_uid251_exp10PolyEval_in <= prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b(0 downto 0);
lowRangeB_uid251_exp10PolyEval_b <= lowRangeB_uid251_exp10PolyEval_in(0 downto 0);
--s1_uid251_uid254_exp10PolyEval(BITJOIN,253)@18
s1_uid251_uid254_exp10PolyEval_q <= sumAHighB_uid253_exp10PolyEval_q & lowRangeB_uid251_exp10PolyEval_b;
--reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1(REG,387)@18
reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q <= s1_uid251_uid254_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor(LOGICAL,1157)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_b <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_q <= not (ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_a or ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_b);
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg(REG,1155)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena(REG,1158)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd(LOGICAL,1159)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_a <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_a and ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_b;
--yT2_uid255_exp10PolyEval(BITSELECT,254)@14
yT2_uid255_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
yT2_uid255_exp10PolyEval_b <= yT2_uid255_exp10PolyEval_in(47 downto 23);
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg(DELAY,1149)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => yT2_uid255_exp10PolyEval_b, xout => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt(COUNTER,1151)
-- every=1, low=0, high=1, step=1, init=1
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i,1));
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg(REG,1152)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux(MUX,1153)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s, ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q, ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem(DUALMEM,1150)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ia <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_aa <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ab <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 25,
widthad_a => 1,
numwords_a => 2,
width_b => 25,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_iq(24 downto 0);
--reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0(REG,386)@18
reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid283_pT2_uid256_exp10PolyEval(MULT,282)@19
prodXY_uid283_pT2_uid256_exp10PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid283_pT2_uid256_exp10PolyEval_a),26)) * SIGNED(prodXY_uid283_pT2_uid256_exp10PolyEval_b);
prodXY_uid283_pT2_uid256_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_a <= (others => '0');
prodXY_uid283_pT2_uid256_exp10PolyEval_b <= (others => '0');
prodXY_uid283_pT2_uid256_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_a <= reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q;
prodXY_uid283_pT2_uid256_exp10PolyEval_b <= reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q;
prodXY_uid283_pT2_uid256_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid283_pT2_uid256_exp10PolyEval_pr,52));
END IF;
END IF;
END PROCESS;
prodXY_uid283_pT2_uid256_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_q <= prodXY_uid283_pT2_uid256_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval(BITSELECT,283)@22
prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_in <= prodXY_uid283_pT2_uid256_exp10PolyEval_q;
prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b <= prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_in(51 downto 24);
--highBBits_uid258_exp10PolyEval(BITSELECT,257)@22
highBBits_uid258_exp10PolyEval_in <= prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b;
highBBits_uid258_exp10PolyEval_b <= highBBits_uid258_exp10PolyEval_in(27 downto 1);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor(LOGICAL,1055)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_b <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_q <= not (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_a or ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top(CONSTANT,1051)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top_q <= "0100";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp(LOGICAL,1052)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_q <= "1" when ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_a = ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_b else "0";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg(REG,1053)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena(REG,1056)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd(LOGICAL,1057)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_a and ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_b;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg(DELAY,1006)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q, xout => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt(COUNTER,1047)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i = 3 THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i - 4;
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg(REG,1048)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux(MUX,1049)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s, ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q, ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem(DUALMEM,1046)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ia <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ia
);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_iq(6 downto 0);
--memoryC3_uid243_exp10TabGen(LOOKUP,242)@21
memoryC3_uid243_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC3_uid243_exp10TabGen_q <= "00101010101010101010101010101101111";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_q) IS
WHEN "0000000" => memoryC3_uid243_exp10TabGen_q <= "00101010101010101010101010101101111";
WHEN "0000001" => memoryC3_uid243_exp10TabGen_q <= "00101011000000000101010101101011011";
WHEN "0000010" => memoryC3_uid243_exp10TabGen_q <= "00101011010101101010110001100001111";
WHEN "0000011" => memoryC3_uid243_exp10TabGen_q <= "00101011101011011011000010011000001";
WHEN "0000100" => memoryC3_uid243_exp10TabGen_q <= "00101100000001010110001110100011110";
WHEN "0000101" => memoryC3_uid243_exp10TabGen_q <= "00101100010111011100011010111011100";
WHEN "0000110" => memoryC3_uid243_exp10TabGen_q <= "00101100101101101101101100111110101";
WHEN "0000111" => memoryC3_uid243_exp10TabGen_q <= "00101101000100001010001010010011010";
WHEN "0001000" => memoryC3_uid243_exp10TabGen_q <= "00101101011010110001111001000001100";
WHEN "0001001" => memoryC3_uid243_exp10TabGen_q <= "00101101110001100100111110001011000";
WHEN "0001010" => memoryC3_uid243_exp10TabGen_q <= "00101110001000100011100000000110101";
WHEN "0001011" => memoryC3_uid243_exp10TabGen_q <= "00101110011111101101100100010001111";
WHEN "0001100" => memoryC3_uid243_exp10TabGen_q <= "00101110110111000011001111101001101";
WHEN "0001101" => memoryC3_uid243_exp10TabGen_q <= "00101111001110100100101000011111000";
WHEN "0001110" => memoryC3_uid243_exp10TabGen_q <= "00101111100110010001110101111100101";
WHEN "0001111" => memoryC3_uid243_exp10TabGen_q <= "00101111111110001010111101010010000";
WHEN "0010000" => memoryC3_uid243_exp10TabGen_q <= "00110000010110010000000010110000111";
WHEN "0010001" => memoryC3_uid243_exp10TabGen_q <= "00110000101110100001001110011111001";
WHEN "0010010" => memoryC3_uid243_exp10TabGen_q <= "00110001000110111110100110100000011";
WHEN "0010011" => memoryC3_uid243_exp10TabGen_q <= "00110001011111101000001111001011001";
WHEN "0010100" => memoryC3_uid243_exp10TabGen_q <= "00110001111000011110010001000100010";
WHEN "0010101" => memoryC3_uid243_exp10TabGen_q <= "00110010010001100000101111101110000";
WHEN "0010110" => memoryC3_uid243_exp10TabGen_q <= "00110010101010101111110011100001100";
WHEN "0010111" => memoryC3_uid243_exp10TabGen_q <= "00110011000100001011100001100001111";
WHEN "0011000" => memoryC3_uid243_exp10TabGen_q <= "00110011011101110100000001011100101";
WHEN "0011001" => memoryC3_uid243_exp10TabGen_q <= "00110011110111101001011000010101000";
WHEN "0011010" => memoryC3_uid243_exp10TabGen_q <= "00110100010001101011101100100010010";
WHEN "0011011" => memoryC3_uid243_exp10TabGen_q <= "00110100101011111011000101110001111";
WHEN "0011100" => memoryC3_uid243_exp10TabGen_q <= "00110101000110010111101010001110011";
WHEN "0011101" => memoryC3_uid243_exp10TabGen_q <= "00110101100001000001100000000100001";
WHEN "0011110" => memoryC3_uid243_exp10TabGen_q <= "00110101111011111000101110000101010";
WHEN "0011111" => memoryC3_uid243_exp10TabGen_q <= "00110110010110111101011010010100110";
WHEN "0100000" => memoryC3_uid243_exp10TabGen_q <= "00110110110010001111101101011010010";
WHEN "0100001" => memoryC3_uid243_exp10TabGen_q <= "00110111001101101111101100101000101";
WHEN "0100010" => memoryC3_uid243_exp10TabGen_q <= "00110111101001011101011110110010101";
WHEN "0100011" => memoryC3_uid243_exp10TabGen_q <= "00111000000101011001001100000100111";
WHEN "0100100" => memoryC3_uid243_exp10TabGen_q <= "00111000100001100010111011000111001";
WHEN "0100101" => memoryC3_uid243_exp10TabGen_q <= "00111000111101111010110001000111010";
WHEN "0100110" => memoryC3_uid243_exp10TabGen_q <= "00111001011010100000111000000010011";
WHEN "0100111" => memoryC3_uid243_exp10TabGen_q <= "00111001110111010101010100101101100";
WHEN "0101000" => memoryC3_uid243_exp10TabGen_q <= "00111010010100011000001111011100111";
WHEN "0101001" => memoryC3_uid243_exp10TabGen_q <= "00111010110001101001101111010100011";
WHEN "0101010" => memoryC3_uid243_exp10TabGen_q <= "00111011001111001001111100011010010";
WHEN "0101011" => memoryC3_uid243_exp10TabGen_q <= "00111011101100111000111011110110001";
WHEN "0101100" => memoryC3_uid243_exp10TabGen_q <= "00111100001010110110110111110001010";
WHEN "0101101" => memoryC3_uid243_exp10TabGen_q <= "00111100101001000011110101010010101";
WHEN "0101110" => memoryC3_uid243_exp10TabGen_q <= "00111101000111011111111101001100100";
WHEN "0101111" => memoryC3_uid243_exp10TabGen_q <= "00111101100110001011011000000101100";
WHEN "0110000" => memoryC3_uid243_exp10TabGen_q <= "00111110000101000110001011101110111";
WHEN "0110001" => memoryC3_uid243_exp10TabGen_q <= "00111110100100010000100000111101010";
WHEN "0110010" => memoryC3_uid243_exp10TabGen_q <= "00111111000011101010011110111011001";
WHEN "0110011" => memoryC3_uid243_exp10TabGen_q <= "00111111100011010100001110000110011";
WHEN "0110100" => memoryC3_uid243_exp10TabGen_q <= "01000000000011001101110101110010101";
WHEN "0110101" => memoryC3_uid243_exp10TabGen_q <= "01000000100011010111011101111010000";
WHEN "0110110" => memoryC3_uid243_exp10TabGen_q <= "01000001000011110001001111111000011";
WHEN "0110111" => memoryC3_uid243_exp10TabGen_q <= "01000001100100011011010010100100000";
WHEN "0111000" => memoryC3_uid243_exp10TabGen_q <= "01000010000101010101101101110001001";
WHEN "0111001" => memoryC3_uid243_exp10TabGen_q <= "01000010100110100000101010111010001";
WHEN "0111010" => memoryC3_uid243_exp10TabGen_q <= "01000011000111111100010001000011010";
WHEN "0111011" => memoryC3_uid243_exp10TabGen_q <= "01000011101001101000101001100001011";
WHEN "0111100" => memoryC3_uid243_exp10TabGen_q <= "01000100001011100101111100010101100";
WHEN "0111101" => memoryC3_uid243_exp10TabGen_q <= "01000100101101110100010010011111111";
WHEN "0111110" => memoryC3_uid243_exp10TabGen_q <= "01000101010000010011110011011101011";
WHEN "0111111" => memoryC3_uid243_exp10TabGen_q <= "01000101110011000100101001100111101";
WHEN "1000000" => memoryC3_uid243_exp10TabGen_q <= "01000110010110000110111011110001110";
WHEN "1000001" => memoryC3_uid243_exp10TabGen_q <= "01000110111001011010110010110111001";
WHEN "1000010" => memoryC3_uid243_exp10TabGen_q <= "01000111011101000000011000100111110";
WHEN "1000011" => memoryC3_uid243_exp10TabGen_q <= "01001000000000110111110110101011010";
WHEN "1000100" => memoryC3_uid243_exp10TabGen_q <= "01001000100101000001010100000000111";
WHEN "1000101" => memoryC3_uid243_exp10TabGen_q <= "01001001001001011100111010100011101";
WHEN "1000110" => memoryC3_uid243_exp10TabGen_q <= "01001001101110001010110100010011010";
WHEN "1000111" => memoryC3_uid243_exp10TabGen_q <= "01001010010011001011001000011100000";
WHEN "1001000" => memoryC3_uid243_exp10TabGen_q <= "01001010111000011110000010011000010";
WHEN "1001001" => memoryC3_uid243_exp10TabGen_q <= "01001011011110000011101001110110000";
WHEN "1001010" => memoryC3_uid243_exp10TabGen_q <= "01001100000011111100001000111111000";
WHEN "1001011" => memoryC3_uid243_exp10TabGen_q <= "01001100101010000111101000110011011";
WHEN "1001100" => memoryC3_uid243_exp10TabGen_q <= "01001101010000100110010011100000101";
WHEN "1001101" => memoryC3_uid243_exp10TabGen_q <= "01001101110111011000010010010110010";
WHEN "1001110" => memoryC3_uid243_exp10TabGen_q <= "01001110011110011101101111010011000";
WHEN "1001111" => memoryC3_uid243_exp10TabGen_q <= "01001111000101110110110011101100000";
WHEN "1010000" => memoryC3_uid243_exp10TabGen_q <= "01001111101101100011101001010010100";
WHEN "1010001" => memoryC3_uid243_exp10TabGen_q <= "01010000010101100100011010101011011";
WHEN "1010010" => memoryC3_uid243_exp10TabGen_q <= "01010000111101111001010000110011110";
WHEN "1010011" => memoryC3_uid243_exp10TabGen_q <= "01010001100110100010010111000101101";
WHEN "1010100" => memoryC3_uid243_exp10TabGen_q <= "01010010001111011111110110110000001";
WHEN "1010101" => memoryC3_uid243_exp10TabGen_q <= "01010010111000110001111010111010000";
WHEN "1010110" => memoryC3_uid243_exp10TabGen_q <= "01010011100010011000101100100001011";
WHEN "1010111" => memoryC3_uid243_exp10TabGen_q <= "01010100001100010100010110011000000";
WHEN "1011000" => memoryC3_uid243_exp10TabGen_q <= "01010100110110100101000100000100011";
WHEN "1011001" => memoryC3_uid243_exp10TabGen_q <= "01010101100001001010111111000111101";
WHEN "1011010" => memoryC3_uid243_exp10TabGen_q <= "01010110001100000110010011000111011";
WHEN "1011011" => memoryC3_uid243_exp10TabGen_q <= "01010110110111010111001001110100000";
WHEN "1011100" => memoryC3_uid243_exp10TabGen_q <= "01010111100010111101101101001011111";
WHEN "1011101" => memoryC3_uid243_exp10TabGen_q <= "01011000001110111010001010001111101";
WHEN "1011110" => memoryC3_uid243_exp10TabGen_q <= "01011000111011001100101011110000010";
WHEN "1011111" => memoryC3_uid243_exp10TabGen_q <= "01011001100111110101011011001001100";
WHEN "1100000" => memoryC3_uid243_exp10TabGen_q <= "01011010010100110100100100011100111";
WHEN "1100001" => memoryC3_uid243_exp10TabGen_q <= "01011011000010001010010011100000000";
WHEN "1100010" => memoryC3_uid243_exp10TabGen_q <= "01011011101111110110110010111100110";
WHEN "1100011" => memoryC3_uid243_exp10TabGen_q <= "01011100011101111010001101110001000";
WHEN "1100100" => memoryC3_uid243_exp10TabGen_q <= "01011101001100010100110000101110011";
WHEN "1100101" => memoryC3_uid243_exp10TabGen_q <= "01011101111011000110100110111100011";
WHEN "1100110" => memoryC3_uid243_exp10TabGen_q <= "01011110101010001111111011100011011";
WHEN "1100111" => memoryC3_uid243_exp10TabGen_q <= "01011111011001110000111010111000000";
WHEN "1101000" => memoryC3_uid243_exp10TabGen_q <= "01100000001001101001110000000101000";
WHEN "1101001" => memoryC3_uid243_exp10TabGen_q <= "01100000111001111010101000001000101";
WHEN "1101010" => memoryC3_uid243_exp10TabGen_q <= "01100001101010100011101111010001110";
WHEN "1101011" => memoryC3_uid243_exp10TabGen_q <= "01100010011011100101001111110000101";
WHEN "1101100" => memoryC3_uid243_exp10TabGen_q <= "01100011001100111111010111101111110";
WHEN "1101101" => memoryC3_uid243_exp10TabGen_q <= "01100011111110110010010011100110010";
WHEN "1101110" => memoryC3_uid243_exp10TabGen_q <= "01100100110000111110001110110101100";
WHEN "1101111" => memoryC3_uid243_exp10TabGen_q <= "01100101100011100011010101101101001";
WHEN "1110000" => memoryC3_uid243_exp10TabGen_q <= "01100110010110100001110101111100110";
WHEN "1110001" => memoryC3_uid243_exp10TabGen_q <= "01100111001001111001111011111001101";
WHEN "1110010" => memoryC3_uid243_exp10TabGen_q <= "01100111111101101011110100001100011";
WHEN "1110011" => memoryC3_uid243_exp10TabGen_q <= "01101000110001110111101100011010111";
WHEN "1110100" => memoryC3_uid243_exp10TabGen_q <= "01101001100110011101101111111111000";
WHEN "1110101" => memoryC3_uid243_exp10TabGen_q <= "01101010011011011110001110011101010";
WHEN "1110110" => memoryC3_uid243_exp10TabGen_q <= "01101011010000111001010010111011001";
WHEN "1110111" => memoryC3_uid243_exp10TabGen_q <= "01101100000110101111001011110001101";
WHEN "1111000" => memoryC3_uid243_exp10TabGen_q <= "01101100111101000000000111000100011";
WHEN "1111001" => memoryC3_uid243_exp10TabGen_q <= "01101101110011101100010000001110111";
WHEN "1111010" => memoryC3_uid243_exp10TabGen_q <= "01101110101010110011110111010100111";
WHEN "1111011" => memoryC3_uid243_exp10TabGen_q <= "01101111100010010111001000101100111";
WHEN "1111100" => memoryC3_uid243_exp10TabGen_q <= "01110000011010010110010011001011011";
WHEN "1111101" => memoryC3_uid243_exp10TabGen_q <= "01110001010010110001100011111011011";
WHEN "1111110" => memoryC3_uid243_exp10TabGen_q <= "01110010001011101001001010001001100";
WHEN "1111111" => memoryC3_uid243_exp10TabGen_q <= "01110011000100111101010001111100100";
WHEN OTHERS =>
memoryC3_uid243_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_exp10PolyEval(ADD,258)@22
sumAHighB_uid259_exp10PolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid243_exp10TabGen_q(34)) & memoryC3_uid243_exp10TabGen_q);
sumAHighB_uid259_exp10PolyEval_b <= STD_LOGIC_VECTOR((35 downto 27 => highBBits_uid258_exp10PolyEval_b(26)) & highBBits_uid258_exp10PolyEval_b);
sumAHighB_uid259_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_exp10PolyEval_a) + SIGNED(sumAHighB_uid259_exp10PolyEval_b));
sumAHighB_uid259_exp10PolyEval_q <= sumAHighB_uid259_exp10PolyEval_o(35 downto 0);
--lowRangeB_uid257_exp10PolyEval(BITSELECT,256)@22
lowRangeB_uid257_exp10PolyEval_in <= prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b(0 downto 0);
lowRangeB_uid257_exp10PolyEval_b <= lowRangeB_uid257_exp10PolyEval_in(0 downto 0);
--s2_uid257_uid260_exp10PolyEval(BITJOIN,259)@22
s2_uid257_uid260_exp10PolyEval_q <= sumAHighB_uid259_exp10PolyEval_q & lowRangeB_uid257_exp10PolyEval_b;
--yTop18Bits_uid292_pT3_uid262_exp10PolyEval(BITSELECT,291)@22
yTop18Bits_uid292_pT3_uid262_exp10PolyEval_in <= s2_uid257_uid260_exp10PolyEval_q;
yTop18Bits_uid292_pT3_uid262_exp10PolyEval_b <= yTop18Bits_uid292_pT3_uid262_exp10PolyEval_in(36 downto 19);
--reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9(REG,392)@22
reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q <= yTop18Bits_uid292_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor(LOGICAL,1068)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_b <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_q <= not (ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_a or ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_b);
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena(REG,1069)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd(LOGICAL,1070)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_a and ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg(DELAY,1058)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid65_fpExpETest_b, xout => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem(DUALMEM,1059)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_aa <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ab <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 3,
numwords_a => 6,
width_b => 48,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_iq(47 downto 0);
--yT3_uid261_exp10PolyEval(BITSELECT,260)@22
yT3_uid261_exp10PolyEval_in <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_q;
yT3_uid261_exp10PolyEval_b <= yT3_uid261_exp10PolyEval_in(47 downto 13);
--xBottomBits_uid291_pT3_uid262_exp10PolyEval(BITSELECT,290)@22
xBottomBits_uid291_pT3_uid262_exp10PolyEval_in <= yT3_uid261_exp10PolyEval_b(7 downto 0);
xBottomBits_uid291_pT3_uid262_exp10PolyEval_b <= xBottomBits_uid291_pT3_uid262_exp10PolyEval_in(7 downto 0);
--pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval(BITJOIN,293)@22
pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_q <= xBottomBits_uid291_pT3_uid262_exp10PolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7(REG,391)@22
reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q <= pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid290_pT3_uid262_exp10PolyEval(BITSELECT,289)@22
yBottomBits_uid290_pT3_uid262_exp10PolyEval_in <= s2_uid257_uid260_exp10PolyEval_q(9 downto 0);
yBottomBits_uid290_pT3_uid262_exp10PolyEval_b <= yBottomBits_uid290_pT3_uid262_exp10PolyEval_in(9 downto 0);
--spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval(BITJOIN,292)@22
spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval_q <= GND_q & yBottomBits_uid290_pT3_uid262_exp10PolyEval_b;
--pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval(BITJOIN,294)@22
pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_q <= spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6(REG,390)@22
reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q <= pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid289_pT3_uid262_exp10PolyEval(BITSELECT,288)@22
xTop18Bits_uid289_pT3_uid262_exp10PolyEval_in <= yT3_uid261_exp10PolyEval_b;
xTop18Bits_uid289_pT3_uid262_exp10PolyEval_b <= xTop18Bits_uid289_pT3_uid262_exp10PolyEval_in(34 downto 17);
--reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4(REG,389)@22
reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q <= xTop18Bits_uid289_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma(CHAINMULTADD,338)@23
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(0),19));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(1),19));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(0) * multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(0);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(1) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(1) * multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(1);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(1),38);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w(0);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x(0);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q),18);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q),18);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q),18);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval(BITSELECT,296)@26
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_in <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_q;
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_in(36 downto 7);
--highBBits_uid299_pT3_uid262_exp10PolyEval(BITSELECT,298)@26
highBBits_uid299_pT3_uid262_exp10PolyEval_in <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b;
highBBits_uid299_pT3_uid262_exp10PolyEval_b <= highBBits_uid299_pT3_uid262_exp10PolyEval_in(29 downto 1);
--yTop27Bits_uid287_pT3_uid262_exp10PolyEval(BITSELECT,286)@22
yTop27Bits_uid287_pT3_uid262_exp10PolyEval_in <= s2_uid257_uid260_exp10PolyEval_q;
yTop27Bits_uid287_pT3_uid262_exp10PolyEval_b <= yTop27Bits_uid287_pT3_uid262_exp10PolyEval_in(36 downto 10);
--reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1(REG,394)@22
reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q <= yTop27Bits_uid287_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid286_pT3_uid262_exp10PolyEval(BITSELECT,285)@22
xTop27Bits_uid286_pT3_uid262_exp10PolyEval_in <= yT3_uid261_exp10PolyEval_b;
xTop27Bits_uid286_pT3_uid262_exp10PolyEval_b <= xTop27Bits_uid286_pT3_uid262_exp10PolyEval_in(34 downto 8);
--reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0(REG,393)@22
reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q <= xTop27Bits_uid286_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid288_pT3_uid262_exp10PolyEval(MULT,287)@23
topProd_uid288_pT3_uid262_exp10PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT3_uid262_exp10PolyEval_a),28)) * SIGNED(topProd_uid288_pT3_uid262_exp10PolyEval_b);
topProd_uid288_pT3_uid262_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid288_pT3_uid262_exp10PolyEval_a <= (others => '0');
topProd_uid288_pT3_uid262_exp10PolyEval_b <= (others => '0');
topProd_uid288_pT3_uid262_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid288_pT3_uid262_exp10PolyEval_a <= reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q;
topProd_uid288_pT3_uid262_exp10PolyEval_b <= reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q;
topProd_uid288_pT3_uid262_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT3_uid262_exp10PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid288_pT3_uid262_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid288_pT3_uid262_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid288_pT3_uid262_exp10PolyEval_q <= topProd_uid288_pT3_uid262_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid300_pT3_uid262_exp10PolyEval(ADD,299)@26
sumAHighB_uid300_pT3_uid262_exp10PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid288_pT3_uid262_exp10PolyEval_q(53)) & topProd_uid288_pT3_uid262_exp10PolyEval_q);
sumAHighB_uid300_pT3_uid262_exp10PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid299_pT3_uid262_exp10PolyEval_b(28)) & highBBits_uid299_pT3_uid262_exp10PolyEval_b);
sumAHighB_uid300_pT3_uid262_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid300_pT3_uid262_exp10PolyEval_a) + SIGNED(sumAHighB_uid300_pT3_uid262_exp10PolyEval_b));
sumAHighB_uid300_pT3_uid262_exp10PolyEval_q <= sumAHighB_uid300_pT3_uid262_exp10PolyEval_o(54 downto 0);
--lowRangeB_uid298_pT3_uid262_exp10PolyEval(BITSELECT,297)@26
lowRangeB_uid298_pT3_uid262_exp10PolyEval_in <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b(0 downto 0);
lowRangeB_uid298_pT3_uid262_exp10PolyEval_b <= lowRangeB_uid298_pT3_uid262_exp10PolyEval_in(0 downto 0);
--add0_uid298_uid301_pT3_uid262_exp10PolyEval(BITJOIN,300)@26
add0_uid298_uid301_pT3_uid262_exp10PolyEval_q <= sumAHighB_uid300_pT3_uid262_exp10PolyEval_q & lowRangeB_uid298_pT3_uid262_exp10PolyEval_b;
--R_uid302_pT3_uid262_exp10PolyEval(BITSELECT,301)@26
R_uid302_pT3_uid262_exp10PolyEval_in <= add0_uid298_uid301_pT3_uid262_exp10PolyEval_q(54 downto 0);
R_uid302_pT3_uid262_exp10PolyEval_b <= R_uid302_pT3_uid262_exp10PolyEval_in(54 downto 18);
--reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1(REG,396)@26
reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q <= R_uid302_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor(LOGICAL,1042)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_b <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_q <= not (ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_a or ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top(CONSTANT,1025)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top_q <= "01000";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp(LOGICAL,1026)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_q <= "1" when ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_a = ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_b else "0";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg(REG,1027)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena(REG,1043)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_q = "1") THEN
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd(LOGICAL,1044)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_a <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_b <= en;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_q <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_a and ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_b;
--memoryC2_uid241_exp10TabGen(LOOKUP,240)@14
memoryC2_uid241_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid241_exp10TabGen_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC2_uid241_exp10TabGen_q <= "000";
WHEN "0000001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1011000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1011001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN OTHERS =>
memoryC2_uid241_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg(DELAY,1032)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid241_exp10TabGen_q, xout => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt(COUNTER,1021)
-- every=1, low=0, high=8, step=1, init=1
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i = 7 THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i - 8;
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg(REG,1022)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux(MUX,1023)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s, ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q, ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem(DUALMEM,1033)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ia <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 9,
width_b => 3,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_iq,
address_a => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_aa,
data_a => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ia
);
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_reset0 <= areset;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_q <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_iq(2 downto 0);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor(LOGICAL,1029)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_b <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_q <= not (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_a or ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena(REG,1030)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd(LOGICAL,1031)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_a and ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_b;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem(DUALMEM,1020)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ia <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 4,
numwords_a => 9,
width_b => 7,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ia
);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_iq(6 downto 0);
--memoryC2_uid240_exp10TabGen(LOOKUP,239)@25
memoryC2_uid240_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid240_exp10TabGen_q <= "1111111111111111111111111111111111111110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_q) IS
WHEN "0000000" => memoryC2_uid240_exp10TabGen_q <= "1111111111111111111111111111111111111110";
WHEN "0000001" => memoryC2_uid240_exp10TabGen_q <= "0000001000000010000000010101011000111101";
WHEN "0000010" => memoryC2_uid240_exp10TabGen_q <= "0000010000001000000010101011010101111110";
WHEN "0000011" => memoryC2_uid240_exp10TabGen_q <= "0000011000010010001001000011011001110000";
WHEN "0000100" => memoryC2_uid240_exp10TabGen_q <= "0000100000100000010101100000000100100100";
WHEN "0000101" => memoryC2_uid240_exp10TabGen_q <= "0000101000110010101010000100111010011000";
WHEN "0000110" => memoryC2_uid240_exp10TabGen_q <= "0000110001001001001000110110100000100101";
WHEN "0000111" => memoryC2_uid240_exp10TabGen_q <= "0000111001100011110011111010011111000001";
WHEN "0001000" => memoryC2_uid240_exp10TabGen_q <= "0001000010000010101101010111011111010100";
WHEN "0001001" => memoryC2_uid240_exp10TabGen_q <= "0001001010100101110111010101010001000100";
WHEN "0001010" => memoryC2_uid240_exp10TabGen_q <= "0001010011001101010011111100100101110011";
WHEN "0001011" => memoryC2_uid240_exp10TabGen_q <= "0001011011111001000101010111010101000111";
WHEN "0001100" => memoryC2_uid240_exp10TabGen_q <= "0001100100101001001101110000011100110000";
WHEN "0001101" => memoryC2_uid240_exp10TabGen_q <= "0001101101011101101111010011111110010110";
WHEN "0001110" => memoryC2_uid240_exp10TabGen_q <= "0001110110010110101100001110111111110111";
WHEN "0001111" => memoryC2_uid240_exp10TabGen_q <= "0001111111010100000110101111110001111100";
WHEN "0010000" => memoryC2_uid240_exp10TabGen_q <= "0010001000010110000001000101101110000011";
WHEN "0010001" => memoryC2_uid240_exp10TabGen_q <= "0010010001011100011101100001001111011100";
WHEN "0010010" => memoryC2_uid240_exp10TabGen_q <= "0010011010100111011110010011111100111011";
WHEN "0010011" => memoryC2_uid240_exp10TabGen_q <= "0010100011110111000101110000101010010001";
WHEN "0010100" => memoryC2_uid240_exp10TabGen_q <= "0010101101001011010110001011001100110101";
WHEN "0010101" => memoryC2_uid240_exp10TabGen_q <= "0010110110100100010001111000101101100011";
WHEN "0010110" => memoryC2_uid240_exp10TabGen_q <= "0011000000000001111011001111010111110010";
WHEN "0010111" => memoryC2_uid240_exp10TabGen_q <= "0011001001100100010100100110100111111010";
WHEN "0011000" => memoryC2_uid240_exp10TabGen_q <= "0011010011001011100000010111000010000011";
WHEN "0011001" => memoryC2_uid240_exp10TabGen_q <= "0011011100110111100000111010011011101000";
WHEN "0011010" => memoryC2_uid240_exp10TabGen_q <= "0011100110101000011000101011110100111100";
WHEN "0011011" => memoryC2_uid240_exp10TabGen_q <= "0011110000011110001010000111011001111100";
WHEN "0011100" => memoryC2_uid240_exp10TabGen_q <= "0011111010011000110111101010100111100101";
WHEN "0011101" => memoryC2_uid240_exp10TabGen_q <= "0100000100011000100011110100001010001010";
WHEN "0011110" => memoryC2_uid240_exp10TabGen_q <= "0100001110011101010001000011111100100101";
WHEN "0011111" => memoryC2_uid240_exp10TabGen_q <= "0100011000100111000001111011001011001100";
WHEN "0100000" => memoryC2_uid240_exp10TabGen_q <= "0100100010110101111000111100001111001111";
WHEN "0100001" => memoryC2_uid240_exp10TabGen_q <= "0100101101001001111000101010111001001000";
WHEN "0100010" => memoryC2_uid240_exp10TabGen_q <= "0100110111100011000011101100001000111111";
WHEN "0100011" => memoryC2_uid240_exp10TabGen_q <= "0101000010000001011100100110001111011101";
WHEN "0100100" => memoryC2_uid240_exp10TabGen_q <= "0101001100100101000110000000110011010000";
WHEN "0100101" => memoryC2_uid240_exp10TabGen_q <= "0101010111001110000010100100110010001010";
WHEN "0100110" => memoryC2_uid240_exp10TabGen_q <= "0101100001111100010100111100010110010011";
WHEN "0100111" => memoryC2_uid240_exp10TabGen_q <= "0101101100101111111111110011001000100100";
WHEN "0101000" => memoryC2_uid240_exp10TabGen_q <= "0101110111101001000101110110000001011000";
WHEN "0101001" => memoryC2_uid240_exp10TabGen_q <= "0110000010100111101001110011010011000100";
WHEN "0101010" => memoryC2_uid240_exp10TabGen_q <= "0110001101101011101110011010100101000110";
WHEN "0101011" => memoryC2_uid240_exp10TabGen_q <= "0110011000110101010110011100111100100110";
WHEN "0101100" => memoryC2_uid240_exp10TabGen_q <= "0110100100000100100100101100101110111111";
WHEN "0101101" => memoryC2_uid240_exp10TabGen_q <= "0110101111011001011011111101110100000010";
WHEN "0101110" => memoryC2_uid240_exp10TabGen_q <= "0110111010110011111111000101010111011100";
WHEN "0101111" => memoryC2_uid240_exp10TabGen_q <= "0111000110010100010000111010000000011010";
WHEN "0110000" => memoryC2_uid240_exp10TabGen_q <= "0111010001111010010100010011110110101100";
WHEN "0110001" => memoryC2_uid240_exp10TabGen_q <= "0111011101100110001100001100011001001011";
WHEN "0110010" => memoryC2_uid240_exp10TabGen_q <= "0111101001010111111011011110100111010001";
WHEN "0110011" => memoryC2_uid240_exp10TabGen_q <= "0111110101001111100101000110111011011110";
WHEN "0110100" => memoryC2_uid240_exp10TabGen_q <= "1000000001001101001100000011010001011000";
WHEN "0110101" => memoryC2_uid240_exp10TabGen_q <= "1000001101010000110011010011000011001011";
WHEN "0110110" => memoryC2_uid240_exp10TabGen_q <= "1000011001011010011101110111001000000101";
WHEN "0110111" => memoryC2_uid240_exp10TabGen_q <= "1000100101101010001110110001111100111001";
WHEN "0111000" => memoryC2_uid240_exp10TabGen_q <= "1000110010000000001001000111011110101101";
WHEN "0111001" => memoryC2_uid240_exp10TabGen_q <= "1000111110011100001111111101001001110101";
WHEN "0111010" => memoryC2_uid240_exp10TabGen_q <= "1001001010111110100110011010000010101010";
WHEN "0111011" => memoryC2_uid240_exp10TabGen_q <= "1001010111100111001111100110101100101010";
WHEN "0111100" => memoryC2_uid240_exp10TabGen_q <= "1001100100010110001110101101010011010010";
WHEN "0111101" => memoryC2_uid240_exp10TabGen_q <= "1001110001001011100110111001100101010000";
WHEN "0111110" => memoryC2_uid240_exp10TabGen_q <= "1001111110000111011011011000111010110011";
WHEN "0111111" => memoryC2_uid240_exp10TabGen_q <= "1010001011001001101111011010001101110011";
WHEN "1000000" => memoryC2_uid240_exp10TabGen_q <= "1010011000010010100110001110000110110000";
WHEN "1000001" => memoryC2_uid240_exp10TabGen_q <= "1010100101100010000011000110110011000011";
WHEN "1000010" => memoryC2_uid240_exp10TabGen_q <= "1010110010111000001001011000001000011101";
WHEN "1000011" => memoryC2_uid240_exp10TabGen_q <= "1011000000010100111100010111100111011010";
WHEN "1000100" => memoryC2_uid240_exp10TabGen_q <= "1011001101111000011111011100100000000010";
WHEN "1000101" => memoryC2_uid240_exp10TabGen_q <= "1011011011100010110101111111101001110101";
WHEN "1000110" => memoryC2_uid240_exp10TabGen_q <= "1011101001010100000011011011101000101011";
WHEN "1000111" => memoryC2_uid240_exp10TabGen_q <= "1011110111001100001011001100110011100100";
WHEN "1001000" => memoryC2_uid240_exp10TabGen_q <= "1100000101001011010000110001001000111011";
WHEN "1001001" => memoryC2_uid240_exp10TabGen_q <= "1100010011010001010111101000011100110101";
WHEN "1001010" => memoryC2_uid240_exp10TabGen_q <= "1100100001011110100011010100001111110100";
WHEN "1001011" => memoryC2_uid240_exp10TabGen_q <= "1100101111110010110111010111110101100001";
WHEN "1001100" => memoryC2_uid240_exp10TabGen_q <= "1100111110001110010111011000010010001101";
WHEN "1001101" => memoryC2_uid240_exp10TabGen_q <= "1101001100110001000110111100011110011111";
WHEN "1001110" => memoryC2_uid240_exp10TabGen_q <= "1101011011011011001001101101000101101011";
WHEN "1001111" => memoryC2_uid240_exp10TabGen_q <= "1101101010001100100011010100101001011110";
WHEN "1010000" => memoryC2_uid240_exp10TabGen_q <= "1101111001000101010111011111100000010111";
WHEN "1010001" => memoryC2_uid240_exp10TabGen_q <= "1110001000000101101001111011110110011101";
WHEN "1010010" => memoryC2_uid240_exp10TabGen_q <= "1110010111001101011110011001110010010001";
WHEN "1010011" => memoryC2_uid240_exp10TabGen_q <= "1110100110011100111000101011001110100000";
WHEN "1010100" => memoryC2_uid240_exp10TabGen_q <= "1110110101110011111100100100000011101110";
WHEN "1010101" => memoryC2_uid240_exp10TabGen_q <= "1111000101010010101101111010000001001010";
WHEN "1010110" => memoryC2_uid240_exp10TabGen_q <= "1111010100111001010000100100110101110101";
WHEN "1010111" => memoryC2_uid240_exp10TabGen_q <= "1111100100100111101000011110001001101110";
WHEN "1011000" => memoryC2_uid240_exp10TabGen_q <= "1111110100011101111001100001100000110101";
WHEN "1011001" => memoryC2_uid240_exp10TabGen_q <= "0000000100011100000111101100100001100111";
WHEN "1011010" => memoryC2_uid240_exp10TabGen_q <= "0000010100100010010110111110101101101101";
WHEN "1011011" => memoryC2_uid240_exp10TabGen_q <= "0000100100110000101011011001101011000010";
WHEN "1011100" => memoryC2_uid240_exp10TabGen_q <= "0000110101000111001001000000111111111100";
WHEN "1011101" => memoryC2_uid240_exp10TabGen_q <= "0001000101100101110011111010010000100110";
WHEN "1011110" => memoryC2_uid240_exp10TabGen_q <= "0001010110001100110000001101000111110111";
WHEN "1011111" => memoryC2_uid240_exp10TabGen_q <= "0001100110111100000010000011011000000011";
WHEN "1100000" => memoryC2_uid240_exp10TabGen_q <= "0001110111110011101101101000110011111110";
WHEN "1100001" => memoryC2_uid240_exp10TabGen_q <= "0010001000110011110111001011010101100011";
WHEN "1100010" => memoryC2_uid240_exp10TabGen_q <= "0010011001111100100010111011000000110011";
WHEN "1100011" => memoryC2_uid240_exp10TabGen_q <= "0010101011001101110101001010000001001001";
WHEN "1100100" => memoryC2_uid240_exp10TabGen_q <= "0010111100100111110010001100101001010000";
WHEN "1100101" => memoryC2_uid240_exp10TabGen_q <= "0011001110001010011110011001011001001101";
WHEN "1100110" => memoryC2_uid240_exp10TabGen_q <= "0011011111110101111110001000111101001011";
WHEN "1100111" => memoryC2_uid240_exp10TabGen_q <= "0011110001101010010101110110001100010001";
WHEN "1101000" => memoryC2_uid240_exp10TabGen_q <= "0100000011100111101001111110001101110100";
WHEN "1101001" => memoryC2_uid240_exp10TabGen_q <= "0100010101101101111111000000010101000100";
WHEN "1101010" => memoryC2_uid240_exp10TabGen_q <= "0100100111111101011001011110000111001011";
WHEN "1101011" => memoryC2_uid240_exp10TabGen_q <= "0100111010010101111101111011011110000001";
WHEN "1101100" => memoryC2_uid240_exp10TabGen_q <= "0101001100110111110000111110011111101100";
WHEN "1101101" => memoryC2_uid240_exp10TabGen_q <= "0101011111100010110111001111101000111010";
WHEN "1101110" => memoryC2_uid240_exp10TabGen_q <= "0101110010010111010101011001101101000111";
WHEN "1101111" => memoryC2_uid240_exp10TabGen_q <= "0110000101010101010000001001110100001010";
WHEN "1110000" => memoryC2_uid240_exp10TabGen_q <= "0110011000011100101100001111011011010100";
WHEN "1110001" => memoryC2_uid240_exp10TabGen_q <= "0110101011101101101110011100011010000001";
WHEN "1110010" => memoryC2_uid240_exp10TabGen_q <= "0110111111001000011011100101000001101011";
WHEN "1110011" => memoryC2_uid240_exp10TabGen_q <= "0111010010101100111000011111111100000111";
WHEN "1110100" => memoryC2_uid240_exp10TabGen_q <= "0111100110011011001010000110010011111010";
WHEN "1110101" => memoryC2_uid240_exp10TabGen_q <= "0111111010010011010101010011101001001100";
WHEN "1110110" => memoryC2_uid240_exp10TabGen_q <= "1000001110010101011111000110000010100010";
WHEN "1110111" => memoryC2_uid240_exp10TabGen_q <= "1000100010100001101100011110000000111101";
WHEN "1111000" => memoryC2_uid240_exp10TabGen_q <= "1000110110111000000010011110100110011111";
WHEN "1111001" => memoryC2_uid240_exp10TabGen_q <= "1001001011011000100110001101011100110010";
WHEN "1111010" => memoryC2_uid240_exp10TabGen_q <= "1001100000000011011100110010101000101011";
WHEN "1111011" => memoryC2_uid240_exp10TabGen_q <= "1001110100111000101011011000111010010001";
WHEN "1111100" => memoryC2_uid240_exp10TabGen_q <= "1010001001111000010111001101100011110110";
WHEN "1111101" => memoryC2_uid240_exp10TabGen_q <= "1010011111000010100101100000100001111000";
WHEN "1111110" => memoryC2_uid240_exp10TabGen_q <= "1010110100010111011011100100010110000001";
WHEN "1111111" => memoryC2_uid240_exp10TabGen_q <= "1011001001110110111110101110010001100110";
WHEN OTHERS =>
memoryC2_uid240_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--os_uid242_exp10TabGen(BITJOIN,241)@26
os_uid242_exp10TabGen_q <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_q & memoryC2_uid240_exp10TabGen_q;
--rndBit_uid263_exp10PolyEval(CONSTANT,262)
rndBit_uid263_exp10PolyEval_q <= "01";
--cIncludingRoundingBit_uid264_exp10PolyEval(BITJOIN,263)@26
cIncludingRoundingBit_uid264_exp10PolyEval_q <= os_uid242_exp10TabGen_q & rndBit_uid263_exp10PolyEval_q;
--reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0(REG,395)@26
reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q <= cIncludingRoundingBit_uid264_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid265_exp10PolyEval(ADD,264)@27
ts3_uid265_exp10PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q);
ts3_uid265_exp10PolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q(36)) & reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q);
ts3_uid265_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid265_exp10PolyEval_a) + SIGNED(ts3_uid265_exp10PolyEval_b));
ts3_uid265_exp10PolyEval_q <= ts3_uid265_exp10PolyEval_o(45 downto 0);
--s3_uid266_exp10PolyEval(BITSELECT,265)@27
s3_uid266_exp10PolyEval_in <= ts3_uid265_exp10PolyEval_q;
s3_uid266_exp10PolyEval_b <= s3_uid266_exp10PolyEval_in(45 downto 1);
--yTop27Bits_uid304_pT4_uid268_exp10PolyEval(BITSELECT,303)@27
yTop27Bits_uid304_pT4_uid268_exp10PolyEval_in <= s3_uid266_exp10PolyEval_b;
yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b <= yTop27Bits_uid304_pT4_uid268_exp10PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9(REG,400)@27
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q <= yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor(LOGICAL,1081)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_b <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_q <= not (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_a or ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_b);
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top(CONSTANT,1077)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top_q <= "01010";
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp(LOGICAL,1078)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_a <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_a = ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg(REG,1079)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena(REG,1082)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd(LOGICAL,1083)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_a and ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt(COUNTER,1073)
-- every=1, low=0, high=10, step=1, init=1
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i = 9 THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i - 10;
ELSE
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg(REG,1074)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux(MUX,1075)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem(DUALMEM,1072)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_iq(47 downto 0);
--yT4_uid267_exp10PolyEval(BITSELECT,266)@27
yT4_uid267_exp10PolyEval_in <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_q;
yT4_uid267_exp10PolyEval_b <= yT4_uid267_exp10PolyEval_in(47 downto 5);
--xBottomBits_uid307_pT4_uid268_exp10PolyEval(BITSELECT,306)@27
xBottomBits_uid307_pT4_uid268_exp10PolyEval_in <= yT4_uid267_exp10PolyEval_b(15 downto 0);
xBottomBits_uid307_pT4_uid268_exp10PolyEval_b <= xBottomBits_uid307_pT4_uid268_exp10PolyEval_in(15 downto 0);
--pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval(BITJOIN,308)@27
pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_q <= xBottomBits_uid307_pT4_uid268_exp10PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7(REG,399)@27
reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q <= pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid306_pT4_uid268_exp10PolyEval(BITSELECT,305)@27
yBottomBits_uid306_pT4_uid268_exp10PolyEval_in <= s3_uid266_exp10PolyEval_b(17 downto 0);
yBottomBits_uid306_pT4_uid268_exp10PolyEval_b <= yBottomBits_uid306_pT4_uid268_exp10PolyEval_in(17 downto 0);
--ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a(DELAY,748)@27
ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid306_pT4_uid268_exp10PolyEval_b, xout => ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval(BITJOIN,307)@28
spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_q <= GND_q & ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a_q;
--pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval(BITJOIN,309)@28
pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_q <= spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6(REG,398)@28
reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q <= pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a(DELAY,742)@27
ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid267_exp10PolyEval_b, xout => ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid303_pT4_uid268_exp10PolyEval(BITSELECT,302)@28
xTop27Bits_uid303_pT4_uid268_exp10PolyEval_in <= ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a_q;
xTop27Bits_uid303_pT4_uid268_exp10PolyEval_b <= xTop27Bits_uid303_pT4_uid268_exp10PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4(REG,397)@28
reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q <= xTop27Bits_uid303_pT4_uid268_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma(CHAINMULTADD,339)@29
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(0),28));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(1),28));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(0) * multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(1) * multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(1);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(0),56);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(1),56);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(1);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(1) + multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(1);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q),27);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q),27);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q),27);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval(BITSELECT,311)@32
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_in <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_q;
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_in(54 downto 8);
--highBBits_uid314_pT4_uid268_exp10PolyEval(BITSELECT,313)@32
highBBits_uid314_pT4_uid268_exp10PolyEval_in <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b;
highBBits_uid314_pT4_uid268_exp10PolyEval_b <= highBBits_uid314_pT4_uid268_exp10PolyEval_in(46 downto 18);
--ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a(DELAY,856)@27
ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b, xout => ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1(REG,402)@28
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q <= ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid305_pT4_uid268_exp10PolyEval(MULT,304)@29
topProd_uid305_pT4_uid268_exp10PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid305_pT4_uid268_exp10PolyEval_a),28)) * SIGNED(topProd_uid305_pT4_uid268_exp10PolyEval_b);
topProd_uid305_pT4_uid268_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid305_pT4_uid268_exp10PolyEval_a <= (others => '0');
topProd_uid305_pT4_uid268_exp10PolyEval_b <= (others => '0');
topProd_uid305_pT4_uid268_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid305_pT4_uid268_exp10PolyEval_a <= reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q;
topProd_uid305_pT4_uid268_exp10PolyEval_b <= reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q;
topProd_uid305_pT4_uid268_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid305_pT4_uid268_exp10PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid305_pT4_uid268_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid305_pT4_uid268_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid305_pT4_uid268_exp10PolyEval_q <= topProd_uid305_pT4_uid268_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid315_pT4_uid268_exp10PolyEval(ADD,314)@32
sumAHighB_uid315_pT4_uid268_exp10PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid305_pT4_uid268_exp10PolyEval_q(53)) & topProd_uid305_pT4_uid268_exp10PolyEval_q);
sumAHighB_uid315_pT4_uid268_exp10PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid314_pT4_uid268_exp10PolyEval_b(28)) & highBBits_uid314_pT4_uid268_exp10PolyEval_b);
sumAHighB_uid315_pT4_uid268_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid315_pT4_uid268_exp10PolyEval_a) + SIGNED(sumAHighB_uid315_pT4_uid268_exp10PolyEval_b));
sumAHighB_uid315_pT4_uid268_exp10PolyEval_q <= sumAHighB_uid315_pT4_uid268_exp10PolyEval_o(54 downto 0);
--lowRangeB_uid313_pT4_uid268_exp10PolyEval(BITSELECT,312)@32
lowRangeB_uid313_pT4_uid268_exp10PolyEval_in <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b(17 downto 0);
lowRangeB_uid313_pT4_uid268_exp10PolyEval_b <= lowRangeB_uid313_pT4_uid268_exp10PolyEval_in(17 downto 0);
--add0_uid313_uid316_pT4_uid268_exp10PolyEval(BITJOIN,315)@32
add0_uid313_uid316_pT4_uid268_exp10PolyEval_q <= sumAHighB_uid315_pT4_uid268_exp10PolyEval_q & lowRangeB_uid313_pT4_uid268_exp10PolyEval_b;
--R_uid317_pT4_uid268_exp10PolyEval(BITSELECT,316)@32
R_uid317_pT4_uid268_exp10PolyEval_in <= add0_uid313_uid316_pT4_uid268_exp10PolyEval_q(71 downto 0);
R_uid317_pT4_uid268_exp10PolyEval_b <= R_uid317_pT4_uid268_exp10PolyEval_in(71 downto 26);
--reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1(REG,404)@32
reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q <= R_uid317_pT4_uid268_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor(LOGICAL,1146)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_b <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_q <= not (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_a or ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_b);
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top(CONSTANT,1142)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top_q <= "01110";
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp(LOGICAL,1143)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_a <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_q <= "1" when ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_a = ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_b else "0";
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg(REG,1144)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena(REG,1147)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_q = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd(LOGICAL,1148)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_a <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_b <= en;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_a and ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_b;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg(DELAY,1123)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => addr_uid64_fpExpETest_b, xout => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt(COUNTER,1138)
-- every=1, low=0, high=14, step=1, init=1
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i = 13 THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i - 14;
ELSE
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i,4));
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg(REG,1139)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux(MUX,1140)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s <= en;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux: PROCESS (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s, ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q, ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s IS
WHEN "0" => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q;
WHEN "1" => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem(DUALMEM,1137)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ia <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_aa <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ab <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 4,
numwords_a => 15,
width_b => 7,
widthad_b => 4,
numwords_b => 15,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ia
);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_iq(6 downto 0);
--reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0(REG,379)@30
reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid238_exp10TabGen(LOOKUP,237)@31
memoryC1_uid238_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid238_exp10TabGen_q <= "00100000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC1_uid238_exp10TabGen_q <= "00100000000";
WHEN "0000001" => memoryC1_uid238_exp10TabGen_q <= "00100000010";
WHEN "0000010" => memoryC1_uid238_exp10TabGen_q <= "00100000100";
WHEN "0000011" => memoryC1_uid238_exp10TabGen_q <= "00100000110";
WHEN "0000100" => memoryC1_uid238_exp10TabGen_q <= "00100001000";
WHEN "0000101" => memoryC1_uid238_exp10TabGen_q <= "00100001010";
WHEN "0000110" => memoryC1_uid238_exp10TabGen_q <= "00100001100";
WHEN "0000111" => memoryC1_uid238_exp10TabGen_q <= "00100001110";
WHEN "0001000" => memoryC1_uid238_exp10TabGen_q <= "00100010000";
WHEN "0001001" => memoryC1_uid238_exp10TabGen_q <= "00100010010";
WHEN "0001010" => memoryC1_uid238_exp10TabGen_q <= "00100010100";
WHEN "0001011" => memoryC1_uid238_exp10TabGen_q <= "00100010110";
WHEN "0001100" => memoryC1_uid238_exp10TabGen_q <= "00100011001";
WHEN "0001101" => memoryC1_uid238_exp10TabGen_q <= "00100011011";
WHEN "0001110" => memoryC1_uid238_exp10TabGen_q <= "00100011101";
WHEN "0001111" => memoryC1_uid238_exp10TabGen_q <= "00100011111";
WHEN "0010000" => memoryC1_uid238_exp10TabGen_q <= "00100100010";
WHEN "0010001" => memoryC1_uid238_exp10TabGen_q <= "00100100100";
WHEN "0010010" => memoryC1_uid238_exp10TabGen_q <= "00100100110";
WHEN "0010011" => memoryC1_uid238_exp10TabGen_q <= "00100101000";
WHEN "0010100" => memoryC1_uid238_exp10TabGen_q <= "00100101011";
WHEN "0010101" => memoryC1_uid238_exp10TabGen_q <= "00100101101";
WHEN "0010110" => memoryC1_uid238_exp10TabGen_q <= "00100110000";
WHEN "0010111" => memoryC1_uid238_exp10TabGen_q <= "00100110010";
WHEN "0011000" => memoryC1_uid238_exp10TabGen_q <= "00100110100";
WHEN "0011001" => memoryC1_uid238_exp10TabGen_q <= "00100110111";
WHEN "0011010" => memoryC1_uid238_exp10TabGen_q <= "00100111001";
WHEN "0011011" => memoryC1_uid238_exp10TabGen_q <= "00100111100";
WHEN "0011100" => memoryC1_uid238_exp10TabGen_q <= "00100111110";
WHEN "0011101" => memoryC1_uid238_exp10TabGen_q <= "00101000001";
WHEN "0011110" => memoryC1_uid238_exp10TabGen_q <= "00101000011";
WHEN "0011111" => memoryC1_uid238_exp10TabGen_q <= "00101000110";
WHEN "0100000" => memoryC1_uid238_exp10TabGen_q <= "00101001000";
WHEN "0100001" => memoryC1_uid238_exp10TabGen_q <= "00101001011";
WHEN "0100010" => memoryC1_uid238_exp10TabGen_q <= "00101001101";
WHEN "0100011" => memoryC1_uid238_exp10TabGen_q <= "00101010000";
WHEN "0100100" => memoryC1_uid238_exp10TabGen_q <= "00101010011";
WHEN "0100101" => memoryC1_uid238_exp10TabGen_q <= "00101010101";
WHEN "0100110" => memoryC1_uid238_exp10TabGen_q <= "00101011000";
WHEN "0100111" => memoryC1_uid238_exp10TabGen_q <= "00101011011";
WHEN "0101000" => memoryC1_uid238_exp10TabGen_q <= "00101011101";
WHEN "0101001" => memoryC1_uid238_exp10TabGen_q <= "00101100000";
WHEN "0101010" => memoryC1_uid238_exp10TabGen_q <= "00101100011";
WHEN "0101011" => memoryC1_uid238_exp10TabGen_q <= "00101100110";
WHEN "0101100" => memoryC1_uid238_exp10TabGen_q <= "00101101001";
WHEN "0101101" => memoryC1_uid238_exp10TabGen_q <= "00101101011";
WHEN "0101110" => memoryC1_uid238_exp10TabGen_q <= "00101101110";
WHEN "0101111" => memoryC1_uid238_exp10TabGen_q <= "00101110001";
WHEN "0110000" => memoryC1_uid238_exp10TabGen_q <= "00101110100";
WHEN "0110001" => memoryC1_uid238_exp10TabGen_q <= "00101110111";
WHEN "0110010" => memoryC1_uid238_exp10TabGen_q <= "00101111010";
WHEN "0110011" => memoryC1_uid238_exp10TabGen_q <= "00101111101";
WHEN "0110100" => memoryC1_uid238_exp10TabGen_q <= "00110000000";
WHEN "0110101" => memoryC1_uid238_exp10TabGen_q <= "00110000011";
WHEN "0110110" => memoryC1_uid238_exp10TabGen_q <= "00110000110";
WHEN "0110111" => memoryC1_uid238_exp10TabGen_q <= "00110001001";
WHEN "0111000" => memoryC1_uid238_exp10TabGen_q <= "00110001100";
WHEN "0111001" => memoryC1_uid238_exp10TabGen_q <= "00110001111";
WHEN "0111010" => memoryC1_uid238_exp10TabGen_q <= "00110010010";
WHEN "0111011" => memoryC1_uid238_exp10TabGen_q <= "00110010101";
WHEN "0111100" => memoryC1_uid238_exp10TabGen_q <= "00110011001";
WHEN "0111101" => memoryC1_uid238_exp10TabGen_q <= "00110011100";
WHEN "0111110" => memoryC1_uid238_exp10TabGen_q <= "00110011111";
WHEN "0111111" => memoryC1_uid238_exp10TabGen_q <= "00110100010";
WHEN "1000000" => memoryC1_uid238_exp10TabGen_q <= "00110100110";
WHEN "1000001" => memoryC1_uid238_exp10TabGen_q <= "00110101001";
WHEN "1000010" => memoryC1_uid238_exp10TabGen_q <= "00110101100";
WHEN "1000011" => memoryC1_uid238_exp10TabGen_q <= "00110110000";
WHEN "1000100" => memoryC1_uid238_exp10TabGen_q <= "00110110011";
WHEN "1000101" => memoryC1_uid238_exp10TabGen_q <= "00110110110";
WHEN "1000110" => memoryC1_uid238_exp10TabGen_q <= "00110111010";
WHEN "1000111" => memoryC1_uid238_exp10TabGen_q <= "00110111101";
WHEN "1001000" => memoryC1_uid238_exp10TabGen_q <= "00111000001";
WHEN "1001001" => memoryC1_uid238_exp10TabGen_q <= "00111000100";
WHEN "1001010" => memoryC1_uid238_exp10TabGen_q <= "00111001000";
WHEN "1001011" => memoryC1_uid238_exp10TabGen_q <= "00111001011";
WHEN "1001100" => memoryC1_uid238_exp10TabGen_q <= "00111001111";
WHEN "1001101" => memoryC1_uid238_exp10TabGen_q <= "00111010011";
WHEN "1001110" => memoryC1_uid238_exp10TabGen_q <= "00111010110";
WHEN "1001111" => memoryC1_uid238_exp10TabGen_q <= "00111011010";
WHEN "1010000" => memoryC1_uid238_exp10TabGen_q <= "00111011110";
WHEN "1010001" => memoryC1_uid238_exp10TabGen_q <= "00111100010";
WHEN "1010010" => memoryC1_uid238_exp10TabGen_q <= "00111100101";
WHEN "1010011" => memoryC1_uid238_exp10TabGen_q <= "00111101001";
WHEN "1010100" => memoryC1_uid238_exp10TabGen_q <= "00111101101";
WHEN "1010101" => memoryC1_uid238_exp10TabGen_q <= "00111110001";
WHEN "1010110" => memoryC1_uid238_exp10TabGen_q <= "00111110101";
WHEN "1010111" => memoryC1_uid238_exp10TabGen_q <= "00111111001";
WHEN "1011000" => memoryC1_uid238_exp10TabGen_q <= "00111111101";
WHEN "1011001" => memoryC1_uid238_exp10TabGen_q <= "01000000001";
WHEN "1011010" => memoryC1_uid238_exp10TabGen_q <= "01000000101";
WHEN "1011011" => memoryC1_uid238_exp10TabGen_q <= "01000001001";
WHEN "1011100" => memoryC1_uid238_exp10TabGen_q <= "01000001101";
WHEN "1011101" => memoryC1_uid238_exp10TabGen_q <= "01000010001";
WHEN "1011110" => memoryC1_uid238_exp10TabGen_q <= "01000010101";
WHEN "1011111" => memoryC1_uid238_exp10TabGen_q <= "01000011001";
WHEN "1100000" => memoryC1_uid238_exp10TabGen_q <= "01000011101";
WHEN "1100001" => memoryC1_uid238_exp10TabGen_q <= "01000100010";
WHEN "1100010" => memoryC1_uid238_exp10TabGen_q <= "01000100110";
WHEN "1100011" => memoryC1_uid238_exp10TabGen_q <= "01000101010";
WHEN "1100100" => memoryC1_uid238_exp10TabGen_q <= "01000101111";
WHEN "1100101" => memoryC1_uid238_exp10TabGen_q <= "01000110011";
WHEN "1100110" => memoryC1_uid238_exp10TabGen_q <= "01000110111";
WHEN "1100111" => memoryC1_uid238_exp10TabGen_q <= "01000111100";
WHEN "1101000" => memoryC1_uid238_exp10TabGen_q <= "01001000000";
WHEN "1101001" => memoryC1_uid238_exp10TabGen_q <= "01001000101";
WHEN "1101010" => memoryC1_uid238_exp10TabGen_q <= "01001001001";
WHEN "1101011" => memoryC1_uid238_exp10TabGen_q <= "01001001110";
WHEN "1101100" => memoryC1_uid238_exp10TabGen_q <= "01001010011";
WHEN "1101101" => memoryC1_uid238_exp10TabGen_q <= "01001010111";
WHEN "1101110" => memoryC1_uid238_exp10TabGen_q <= "01001011100";
WHEN "1101111" => memoryC1_uid238_exp10TabGen_q <= "01001100001";
WHEN "1110000" => memoryC1_uid238_exp10TabGen_q <= "01001100110";
WHEN "1110001" => memoryC1_uid238_exp10TabGen_q <= "01001101010";
WHEN "1110010" => memoryC1_uid238_exp10TabGen_q <= "01001101111";
WHEN "1110011" => memoryC1_uid238_exp10TabGen_q <= "01001110100";
WHEN "1110100" => memoryC1_uid238_exp10TabGen_q <= "01001111001";
WHEN "1110101" => memoryC1_uid238_exp10TabGen_q <= "01001111110";
WHEN "1110110" => memoryC1_uid238_exp10TabGen_q <= "01010000011";
WHEN "1110111" => memoryC1_uid238_exp10TabGen_q <= "01010001000";
WHEN "1111000" => memoryC1_uid238_exp10TabGen_q <= "01010001101";
WHEN "1111001" => memoryC1_uid238_exp10TabGen_q <= "01010010010";
WHEN "1111010" => memoryC1_uid238_exp10TabGen_q <= "01010011000";
WHEN "1111011" => memoryC1_uid238_exp10TabGen_q <= "01010011101";
WHEN "1111100" => memoryC1_uid238_exp10TabGen_q <= "01010100010";
WHEN "1111101" => memoryC1_uid238_exp10TabGen_q <= "01010100111";
WHEN "1111110" => memoryC1_uid238_exp10TabGen_q <= "01010101101";
WHEN "1111111" => memoryC1_uid238_exp10TabGen_q <= "01010110010";
WHEN OTHERS =>
memoryC1_uid238_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--memoryC1_uid237_exp10TabGen(LOOKUP,236)@31
memoryC1_uid237_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid237_exp10TabGen_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC1_uid237_exp10TabGen_q <= "0000000000000000000000000000000000000000";
WHEN "0000001" => memoryC1_uid237_exp10TabGen_q <= "0000001000000001010101100000000000111010";
WHEN "0000010" => memoryC1_uid237_exp10TabGen_q <= "0000100000001010101101010101110111011110";
WHEN "0000011" => memoryC1_uid237_exp10TabGen_q <= "0001001000100100001101100100000100000110";
WHEN "0000100" => memoryC1_uid237_exp10TabGen_q <= "0010000001010110000000010001001001111011";
WHEN "0000101" => memoryC1_uid237_exp10TabGen_q <= "0011001010101000010011101001110000100000";
WHEN "0000110" => memoryC1_uid237_exp10TabGen_q <= "0100100100100011011010000010100111101010";
WHEN "0000111" => memoryC1_uid237_exp10TabGen_q <= "0110001111001111101001111010101100000101";
WHEN "0001000" => memoryC1_uid237_exp10TabGen_q <= "1000001010110101011101111101001101001110";
WHEN "0001001" => memoryC1_uid237_exp10TabGen_q <= "1010010111011101010101000011110011001011";
WHEN "0001010" => memoryC1_uid237_exp10TabGen_q <= "1100110101001111110010011000100111010001";
WHEN "0001011" => memoryC1_uid237_exp10TabGen_q <= "1111100100010101011101011000011100010001";
WHEN "0001100" => memoryC1_uid237_exp10TabGen_q <= "0010100100110111000001110100111000010010";
WHEN "0001101" => memoryC1_uid237_exp10TabGen_q <= "0101110110111101001111110110100000001001";
WHEN "0001110" => memoryC1_uid237_exp10TabGen_q <= "1001011010110000111011111111000011100110";
WHEN "0001111" => memoryC1_uid237_exp10TabGen_q <= "1101010000011010111111001011101001010000";
WHEN "0010000" => memoryC1_uid237_exp10TabGen_q <= "0001011000000100010110110110111101011001";
WHEN "0010001" => memoryC1_uid237_exp10TabGen_q <= "0101110001110110000100111011100010100010";
WHEN "0010010" => memoryC1_uid237_exp10TabGen_q <= "1010011101111001001111110110000000011101";
WHEN "0010011" => memoryC1_uid237_exp10TabGen_q <= "1111011100010111000010100111010101011010";
WHEN "0010100" => memoryC1_uid237_exp10TabGen_q <= "0100101101011000101100110111001011010010";
WHEN "0010101" => memoryC1_uid237_exp10TabGen_q <= "1010010001000111100010110110001000001100";
WHEN "0010110" => memoryC1_uid237_exp10TabGen_q <= "0000000111101100111101100000000110110001";
WHEN "0010111" => memoryC1_uid237_exp10TabGen_q <= "0110010001010010011010011110101001111111";
WHEN "0011000" => memoryC1_uid237_exp10TabGen_q <= "1100101110000001011100001011010110001100";
WHEN "0011001" => memoryC1_uid237_exp10TabGen_q <= "0011011110000011101001110010001000001011";
WHEN "0011010" => memoryC1_uid237_exp10TabGen_q <= "1010100001100010101111010011110000010000";
WHEN "0011011" => memoryC1_uid237_exp10TabGen_q <= "0001111000101000011101101000001101001011";
WHEN "0011100" => memoryC1_uid237_exp10TabGen_q <= "1001100011011110101010100001000111100100";
WHEN "0011101" => memoryC1_uid237_exp10TabGen_q <= "0001100010001111010000101100001111101101";
WHEN "0011110" => memoryC1_uid237_exp10TabGen_q <= "1001110101000100001111110101111100011111";
WHEN "0011111" => memoryC1_uid237_exp10TabGen_q <= "0010011100000111101100101011101010111111";
WHEN "0100000" => memoryC1_uid237_exp10TabGen_q <= "1011010111100011110000111110100000011101";
WHEN "0100001" => memoryC1_uid237_exp10TabGen_q <= "0100100111100010101011100101101011001010";
WHEN "0100010" => memoryC1_uid237_exp10TabGen_q <= "1110001100001110110000100001000111011110";
WHEN "0100011" => memoryC1_uid237_exp10TabGen_q <= "1000000101110010011000111100000100110111";
WHEN "0100100" => memoryC1_uid237_exp10TabGen_q <= "0010010100011000000011001111101011010111";
WHEN "0100101" => memoryC1_uid237_exp10TabGen_q <= "1100111000001010010011000101100010111111";
WHEN "0100110" => memoryC1_uid237_exp10TabGen_q <= "0111110001010011110001011010011110110011";
WHEN "0100111" => memoryC1_uid237_exp10TabGen_q <= "0010111111111111001100100001000011111001";
WHEN "0101000" => memoryC1_uid237_exp10TabGen_q <= "1110100100010111011000000100010111111100";
WHEN "0101001" => memoryC1_uid237_exp10TabGen_q <= "1010011110100111001101001010101100001001";
WHEN "0101010" => memoryC1_uid237_exp10TabGen_q <= "0110101110111001101010011000001100101111";
WHEN "0101011" => memoryC1_uid237_exp10TabGen_q <= "0011010101011001110011110001101111000101";
WHEN "0101100" => memoryC1_uid237_exp10TabGen_q <= "0000010010010010110010111111100101001101";
WHEN "0101101" => memoryC1_uid237_exp10TabGen_q <= "1101100101101111110111010000001101001010";
WHEN "0101110" => memoryC1_uid237_exp10TabGen_q <= "1011001111111100010101011011000111100000";
WHEN "0101111" => memoryC1_uid237_exp10TabGen_q <= "1001010001000011101000000011101011010001";
WHEN "0110000" => memoryC1_uid237_exp10TabGen_q <= "0111101001010001001111011011111011111001";
WHEN "0110001" => memoryC1_uid237_exp10TabGen_q <= "0110011000110000110001100111100011000100";
WHEN "0110010" => memoryC1_uid237_exp10TabGen_q <= "0101011111101101111010011110101000100111";
WHEN "0110011" => memoryC1_uid237_exp10TabGen_q <= "0100111110010100011011110000101110110000";
WHEN "0110100" => memoryC1_uid237_exp10TabGen_q <= "0100110100110000001101000111101101011011";
WHEN "0110101" => memoryC1_uid237_exp10TabGen_q <= "0101000011001101001100001010110000110011";
WHEN "0110110" => memoryC1_uid237_exp10TabGen_q <= "0101101001110111011100100001011001001110";
WHEN "0110111" => memoryC1_uid237_exp10TabGen_q <= "0110101000111011000111110110011010101000";
WHEN "0111000" => memoryC1_uid237_exp10TabGen_q <= "1000000000100100011101111011000000000000";
WHEN "0111001" => memoryC1_uid237_exp10TabGen_q <= "1001110000111111110100101001101111110010";
WHEN "0111010" => memoryC1_uid237_exp10TabGen_q <= "1011111010011001101000001001101111101100";
WHEN "0111011" => memoryC1_uid237_exp10TabGen_q <= "1110011100111110011010110001101101110011";
WHEN "0111100" => memoryC1_uid237_exp10TabGen_q <= "0001011000111010110101001011000111010110";
WHEN "0111101" => memoryC1_uid237_exp10TabGen_q <= "0100101110011011100110010101010100001010";
WHEN "0111110" => memoryC1_uid237_exp10TabGen_q <= "1000011101101101100011101000110001001110";
WHEN "0111111" => memoryC1_uid237_exp10TabGen_q <= "1100100110111101101000111010001111101111";
WHEN "1000000" => memoryC1_uid237_exp10TabGen_q <= "0001001010011000111000011110000001110001";
WHEN "1000001" => memoryC1_uid237_exp10TabGen_q <= "0110001000001100011011001011001100110100";
WHEN "1000010" => memoryC1_uid237_exp10TabGen_q <= "1011100000100101100000011110111011011101";
WHEN "1000011" => memoryC1_uid237_exp10TabGen_q <= "0001010011110001011110011111110001000001";
WHEN "1000100" => memoryC1_uid237_exp10TabGen_q <= "0111100001111101110010000000111110011000";
WHEN "1000101" => memoryC1_uid237_exp10TabGen_q <= "1110001011010111111110100101111010101100";
WHEN "1000110" => memoryC1_uid237_exp10TabGen_q <= "0101010000001101101110100101011011101100";
WHEN "1000111" => memoryC1_uid237_exp10TabGen_q <= "1100110000101100110011001101001111000101";
WHEN "1001000" => memoryC1_uid237_exp10TabGen_q <= "0100101101000011000100100101011001001000";
WHEN "1001001" => memoryC1_uid237_exp10TabGen_q <= "1101000101011110100001110011110000011001";
WHEN "1001010" => memoryC1_uid237_exp10TabGen_q <= "0101111010001101010000111111011111001100";
WHEN "1001011" => memoryC1_uid237_exp10TabGen_q <= "1111001011011101011111010100100100001011";
WHEN "1001100" => memoryC1_uid237_exp10TabGen_q <= "1000111001011101100001000111010110000110";
WHEN "1001101" => memoryC1_uid237_exp10TabGen_q <= "0011000100011011110001111000001000100101";
WHEN "1001110" => memoryC1_uid237_exp10TabGen_q <= "1101101100100110110100010110110011010110";
WHEN "1001111" => memoryC1_uid237_exp10TabGen_q <= "1000110010001101010010100110011010010111";
WHEN "1010000" => memoryC1_uid237_exp10TabGen_q <= "0100010101011101111110000000111000111010";
WHEN "1010001" => memoryC1_uid237_exp10TabGen_q <= "0000010110100111101111011010101101110110";
WHEN "1010010" => memoryC1_uid237_exp10TabGen_q <= "1100110101111001100111000110101001001101";
WHEN "1010011" => memoryC1_uid237_exp10TabGen_q <= "1001110011100010101100111001011101100011";
WHEN "1010100" => memoryC1_uid237_exp10TabGen_q <= "0111001111110010010000001101110000010000";
WHEN "1010101" => memoryC1_uid237_exp10TabGen_q <= "0101001010110111101000000111101111000000";
WHEN "1010110" => memoryC1_uid237_exp10TabGen_q <= "0011100101000010010011011001000011111010";
WHEN "1010111" => memoryC1_uid237_exp10TabGen_q <= "0010011110100001111000100100101110110000";
WHEN "1011000" => memoryC1_uid237_exp10TabGen_q <= "0001110111100110000110000010111110001011";
WHEN "1011001" => memoryC1_uid237_exp10TabGen_q <= "0001110000011110110010000101001010010000";
WHEN "1011010" => memoryC1_uid237_exp10TabGen_q <= "0010001001011011111010111001110011101101";
WHEN "1011011" => memoryC1_uid237_exp10TabGen_q <= "0011000010101101100110110000100001110010";
WHEN "1011100" => memoryC1_uid237_exp10TabGen_q <= "0100011100100100000011111110000100111100";
WHEN "1011101" => memoryC1_uid237_exp10TabGen_q <= "0110010111001111101001000000011010110011";
WHEN "1011110" => memoryC1_uid237_exp10TabGen_q <= "1000110011000000110100100010110010101001";
WHEN "1011111" => memoryC1_uid237_exp10TabGen_q <= "1011110000001000001101100001110100111001";
WHEN "1100000" => memoryC1_uid237_exp10TabGen_q <= "1111001110110110100011001111101110011101";
WHEN "1100001" => memoryC1_uid237_exp10TabGen_q <= "0011001111011100101101011000011011011101";
WHEN "1100010" => memoryC1_uid237_exp10TabGen_q <= "0111110010001011101100000101110100110000";
WHEN "1100011" => memoryC1_uid237_exp10TabGen_q <= "1100110111010100101000000100000000111000";
WHEN "1100100" => memoryC1_uid237_exp10TabGen_q <= "0010011111001000110010100101100110001010";
WHEN "1100101" => memoryC1_uid237_exp10TabGen_q <= "1000101001111001100101100111111110010101";
WHEN "1100110" => memoryC1_uid237_exp10TabGen_q <= "1111010111111000100011110111101101010110";
WHEN "1100111" => memoryC1_uid237_exp10TabGen_q <= "0110101001010111011000110100111010100000";
WHEN "1101000" => memoryC1_uid237_exp10TabGen_q <= "1110011110100111111000110111101010100011";
WHEN "1101001" => memoryC1_uid237_exp10TabGen_q <= "0110110111111100000001010100011101110011";
WHEN "1101010" => memoryC1_uid237_exp10TabGen_q <= "1111110101100101111000100000101110100001";
WHEN "1101011" => memoryC1_uid237_exp10TabGen_q <= "1001010111110111101101110111010010010010";
WHEN "1101100" => memoryC1_uid237_exp10TabGen_q <= "0011011111000011111001111100111111011110";
WHEN "1101101" => memoryC1_uid237_exp10TabGen_q <= "1110001011011100111110100101010001110110";
WHEN "1101110" => memoryC1_uid237_exp10TabGen_q <= "1001011101010101100110110110110011001000";
WHEN "1101111" => memoryC1_uid237_exp10TabGen_q <= "0101010101000000100111010000000110011111";
WHEN "1110000" => memoryC1_uid237_exp10TabGen_q <= "0001110010110000111101101100010101100001";
WHEN "1110001" => memoryC1_uid237_exp10TabGen_q <= "1110110110111001110001100111111111010101";
WHEN "1110010" => memoryC1_uid237_exp10TabGen_q <= "1100100001101110010100000101101010011001";
WHEN "1110011" => memoryC1_uid237_exp10TabGen_q <= "1010110011100001111111110010111001100100";
WHEN "1110100" => memoryC1_uid237_exp10TabGen_q <= "1001101100101000011001001101000001001110";
WHEN "1110101" => memoryC1_uid237_exp10TabGen_q <= "1001001101010101001110100110000010110100";
WHEN "1110110" => memoryC1_uid237_exp10TabGen_q <= "1001010101111100011000001001100101100100";
WHEN "1110111" => memoryC1_uid237_exp10TabGen_q <= "1010000110110001111000000001110110110011";
WHEN "1111000" => memoryC1_uid237_exp10TabGen_q <= "1011100000001001111010011100101001101110";
WHEN "1111001" => memoryC1_uid237_exp10TabGen_q <= "1101100010011000110101110000011001010011";
WHEN "1111010" => memoryC1_uid237_exp10TabGen_q <= "0000001101110011001010100001010000011101";
WHEN "1111011" => memoryC1_uid237_exp10TabGen_q <= "0011100010101101100011100110001111100011";
WHEN "1111100" => memoryC1_uid237_exp10TabGen_q <= "0111100001011100110110001110011000110111";
WHEN "1111101" => memoryC1_uid237_exp10TabGen_q <= "1100001010010110000010000101111100110011";
WHEN "1111110" => memoryC1_uid237_exp10TabGen_q <= "0001011101101110010001011011101010111011";
WHEN "1111111" => memoryC1_uid237_exp10TabGen_q <= "0111011011111010111001000110000010110110";
WHEN OTHERS =>
memoryC1_uid237_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--os_uid239_exp10TabGen(BITJOIN,238)@32
os_uid239_exp10TabGen_q <= memoryC1_uid238_exp10TabGen_q & memoryC1_uid237_exp10TabGen_q;
--cIncludingRoundingBit_uid270_exp10PolyEval(BITJOIN,269)@32
cIncludingRoundingBit_uid270_exp10PolyEval_q <= os_uid239_exp10TabGen_q & rndBit_uid263_exp10PolyEval_q;
--reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0(REG,403)@32
reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q <= cIncludingRoundingBit_uid270_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid271_exp10PolyEval(ADD,270)@33
ts4_uid271_exp10PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q);
ts4_uid271_exp10PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q(45)) & reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q);
ts4_uid271_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid271_exp10PolyEval_a) + SIGNED(ts4_uid271_exp10PolyEval_b));
ts4_uid271_exp10PolyEval_q <= ts4_uid271_exp10PolyEval_o(53 downto 0);
--s4_uid272_exp10PolyEval(BITSELECT,271)@33
s4_uid272_exp10PolyEval_in <= ts4_uid271_exp10PolyEval_q;
s4_uid272_exp10PolyEval_b <= s4_uid272_exp10PolyEval_in(53 downto 1);
--yTop27Bits_uid319_pT5_uid274_exp10PolyEval(BITSELECT,318)@33
yTop27Bits_uid319_pT5_uid274_exp10PolyEval_in <= s4_uid272_exp10PolyEval_b;
yTop27Bits_uid319_pT5_uid274_exp10PolyEval_b <= yTop27Bits_uid319_pT5_uid274_exp10PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9(REG,408)@33
reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q <= yTop27Bits_uid319_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor(LOGICAL,1107)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_b <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_q <= not (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_a or ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_b);
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top(CONSTANT,1103)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top_q <= "010000";
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp(LOGICAL,1104)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_a <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_a = ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg(REG,1105)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena(REG,1108)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd(LOGICAL,1109)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_a <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_a and ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_b;
--xBottomBits_uid322_pT5_uid274_exp10PolyEval(BITSELECT,321)@14
xBottomBits_uid322_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b(20 downto 0);
xBottomBits_uid322_pT5_uid274_exp10PolyEval_b <= xBottomBits_uid322_pT5_uid274_exp10PolyEval_in(20 downto 0);
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg(DELAY,1097)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => xBottomBits_uid322_pT5_uid274_exp10PolyEval_b, xout => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt(COUNTER,1099)
-- every=1, low=0, high=16, step=1, init=1
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i = 15 THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg(REG,1100)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux(MUX,1101)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem(DUALMEM,1098)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 5,
numwords_a => 17,
width_b => 21,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_iq(20 downto 0);
--pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval(BITJOIN,325)@33
pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((4 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7(REG,407)@33
reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q <= pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor(LOGICAL,1094)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_b <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_q <= not (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_a or ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_b);
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top(CONSTANT,1090)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top_q <= "010001";
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp(LOGICAL,1091)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_a <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_a = ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg(REG,1092)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena(REG,1095)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd(LOGICAL,1096)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_a and ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_b;
--xTop26Bits_uid323_pT5_uid274_exp10PolyEval(BITSELECT,322)@14
xTop26Bits_uid323_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b <= xTop26Bits_uid323_pT5_uid274_exp10PolyEval_in(47 downto 22);
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg(DELAY,1084)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b, xout => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt(COUNTER,1086)
-- every=1, low=0, high=17, step=1, init=1
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i = 16 THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i - 17;
ELSE
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg(REG,1087)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux(MUX,1088)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem(DUALMEM,1085)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 18,
width_b => 26,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval(BITJOIN,324)@34
spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_q <= GND_q & ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6(REG,406)@34
reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q <= spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid321_pT5_uid274_exp10PolyEval(BITSELECT,320)@33
yBottomBits_uid321_pT5_uid274_exp10PolyEval_in <= s4_uid272_exp10PolyEval_b(25 downto 0);
yBottomBits_uid321_pT5_uid274_exp10PolyEval_b <= yBottomBits_uid321_pT5_uid274_exp10PolyEval_in(25 downto 0);
--ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b(DELAY,768)@33
ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid321_pT5_uid274_exp10PolyEval_b, xout => ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval(BITJOIN,326)@34
pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_q <= ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4(REG,405)@34
reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q <= pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--VCC(CONSTANT,1)
VCC_q <= "1";
--multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma(CHAINMULTADD,340)@35
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(0),28));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(1),28));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(0) * multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(1) * multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(1);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(0),56);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(1),56);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(1);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(1) + multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(1);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q),27);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q),27);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q),27);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval(BITSELECT,328)@38
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_in <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_q;
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_in(54 downto 1);
--highBBits_uid335_pT5_uid274_exp10PolyEval(BITSELECT,334)@38
highBBits_uid335_pT5_uid274_exp10PolyEval_in <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b;
highBBits_uid335_pT5_uid274_exp10PolyEval_b <= highBBits_uid335_pT5_uid274_exp10PolyEval_in(53 downto 19);
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor(LOGICAL,1170)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_b <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_a or ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_b);
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena(REG,1171)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd(LOGICAL,1172)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_b;
--xTop27Bits_uid318_pT5_uid274_exp10PolyEval(BITSELECT,317)@14
xTop27Bits_uid318_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b <= xTop27Bits_uid318_pT5_uid274_exp10PolyEval_in(47 downto 21);
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg(DELAY,1160)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b, xout => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem(DUALMEM,1161)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_aa <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ab <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 5,
numwords_a => 17,
width_b => 27,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0(REG,411)@33
reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid320_pT5_uid274_exp10PolyEval(MULT,319)@34
topProd_uid320_pT5_uid274_exp10PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid320_pT5_uid274_exp10PolyEval_a),28)) * SIGNED(topProd_uid320_pT5_uid274_exp10PolyEval_b);
topProd_uid320_pT5_uid274_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid320_pT5_uid274_exp10PolyEval_a <= (others => '0');
topProd_uid320_pT5_uid274_exp10PolyEval_b <= (others => '0');
topProd_uid320_pT5_uid274_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid320_pT5_uid274_exp10PolyEval_a <= reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q;
topProd_uid320_pT5_uid274_exp10PolyEval_b <= reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q;
topProd_uid320_pT5_uid274_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid320_pT5_uid274_exp10PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid320_pT5_uid274_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid320_pT5_uid274_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid320_pT5_uid274_exp10PolyEval_q <= topProd_uid320_pT5_uid274_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor(LOGICAL,1120)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_b <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_q <= not (ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_a or ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_b);
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena(REG,1121)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_q = "1") THEN
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd(LOGICAL,1122)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_a <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_b <= en;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_q <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_a and ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_b;
--sSM0W_uid331_pT5_uid274_exp10PolyEval(BITSELECT,330)@14
sSM0W_uid331_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b(20 downto 0);
sSM0W_uid331_pT5_uid274_exp10PolyEval_b <= sSM0W_uid331_pT5_uid274_exp10PolyEval_in(20 downto 18);
--reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1(REG,410)@14
reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q <= sSM0W_uid331_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg(DELAY,1110)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q, xout => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem(DUALMEM,1111)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ia <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 17,
width_b => 3,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_iq,
address_a => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_aa,
data_a => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ia
);
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 <= areset;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_q <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_iq(2 downto 0);
--sSM0H_uid330_pT5_uid274_exp10PolyEval(BITSELECT,329)@33
sSM0H_uid330_pT5_uid274_exp10PolyEval_in <= s4_uid272_exp10PolyEval_b(25 downto 0);
sSM0H_uid330_pT5_uid274_exp10PolyEval_b <= sSM0H_uid330_pT5_uid274_exp10PolyEval_in(25 downto 23);
--reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0(REG,409)@33
reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q <= sSM0H_uid330_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid332_pT5_uid274_exp10PolyEval(MULT,331)@34
sm0_uid332_pT5_uid274_exp10PolyEval_pr <= UNSIGNED(sm0_uid332_pT5_uid274_exp10PolyEval_a) * UNSIGNED(sm0_uid332_pT5_uid274_exp10PolyEval_b);
sm0_uid332_pT5_uid274_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid332_pT5_uid274_exp10PolyEval_a <= (others => '0');
sm0_uid332_pT5_uid274_exp10PolyEval_b <= (others => '0');
sm0_uid332_pT5_uid274_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid332_pT5_uid274_exp10PolyEval_a <= reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q;
sm0_uid332_pT5_uid274_exp10PolyEval_b <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_q;
sm0_uid332_pT5_uid274_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid332_pT5_uid274_exp10PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid332_pT5_uid274_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid332_pT5_uid274_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid332_pT5_uid274_exp10PolyEval_q <= sm0_uid332_pT5_uid274_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval(BITJOIN,332)@37
TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q <= topProd_uid320_pT5_uid274_exp10PolyEval_q & sm0_uid332_pT5_uid274_exp10PolyEval_q;
--ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a(DELAY,778)@37
ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q, xout => ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid336_pT5_uid274_exp10PolyEval(ADD,335)@38
sumAHighB_uid336_pT5_uid274_exp10PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q);
sumAHighB_uid336_pT5_uid274_exp10PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid335_pT5_uid274_exp10PolyEval_b(34)) & highBBits_uid335_pT5_uid274_exp10PolyEval_b);
sumAHighB_uid336_pT5_uid274_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid336_pT5_uid274_exp10PolyEval_a) + SIGNED(sumAHighB_uid336_pT5_uid274_exp10PolyEval_b));
sumAHighB_uid336_pT5_uid274_exp10PolyEval_q <= sumAHighB_uid336_pT5_uid274_exp10PolyEval_o(60 downto 0);
--lowRangeB_uid334_pT5_uid274_exp10PolyEval(BITSELECT,333)@38
lowRangeB_uid334_pT5_uid274_exp10PolyEval_in <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b(18 downto 0);
lowRangeB_uid334_pT5_uid274_exp10PolyEval_b <= lowRangeB_uid334_pT5_uid274_exp10PolyEval_in(18 downto 0);
--add0_uid334_uid337_pT5_uid274_exp10PolyEval(BITJOIN,336)@38
add0_uid334_uid337_pT5_uid274_exp10PolyEval_q <= sumAHighB_uid336_pT5_uid274_exp10PolyEval_q & lowRangeB_uid334_pT5_uid274_exp10PolyEval_b;
--R_uid338_pT5_uid274_exp10PolyEval(BITSELECT,337)@38
R_uid338_pT5_uid274_exp10PolyEval_in <= add0_uid334_uid337_pT5_uid274_exp10PolyEval_q(78 downto 0);
R_uid338_pT5_uid274_exp10PolyEval_b <= R_uid338_pT5_uid274_exp10PolyEval_in(78 downto 24);
--reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1(REG,414)@38
reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q <= R_uid338_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor(LOGICAL,1016)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_b <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_q <= not (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_a or ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top(CONSTANT,1012)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top_q <= "010100";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp(LOGICAL,1013)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_q <= "1" when ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_a = ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_b else "0";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg(REG,1014)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena(REG,1017)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd(LOGICAL,1018)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_a and ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_b;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt(COUNTER,1008)
-- every=1, low=0, high=20, step=1, init=1
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i = 19 THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i - 20;
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg(REG,1009)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux(MUX,1010)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s, ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q, ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem(DUALMEM,1007)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ia <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 21,
width_b => 7,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ia
);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_iq(6 downto 0);
--memoryC0_uid235_exp10TabGen(LOOKUP,234)@37
memoryC0_uid235_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid235_exp10TabGen_q <= "001000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid235_exp10TabGen_q <= "001000000000000000";
WHEN "0000001" => memoryC0_uid235_exp10TabGen_q <= "001000000100000001";
WHEN "0000010" => memoryC0_uid235_exp10TabGen_q <= "001000001000000100";
WHEN "0000011" => memoryC0_uid235_exp10TabGen_q <= "001000001100001001";
WHEN "0000100" => memoryC0_uid235_exp10TabGen_q <= "001000010000010000";
WHEN "0000101" => memoryC0_uid235_exp10TabGen_q <= "001000010100011001";
WHEN "0000110" => memoryC0_uid235_exp10TabGen_q <= "001000011000100100";
WHEN "0000111" => memoryC0_uid235_exp10TabGen_q <= "001000011100110001";
WHEN "0001000" => memoryC0_uid235_exp10TabGen_q <= "001000100001000001";
WHEN "0001001" => memoryC0_uid235_exp10TabGen_q <= "001000100101010010";
WHEN "0001010" => memoryC0_uid235_exp10TabGen_q <= "001000101001100110";
WHEN "0001011" => memoryC0_uid235_exp10TabGen_q <= "001000101101111100";
WHEN "0001100" => memoryC0_uid235_exp10TabGen_q <= "001000110010010100";
WHEN "0001101" => memoryC0_uid235_exp10TabGen_q <= "001000110110101110";
WHEN "0001110" => memoryC0_uid235_exp10TabGen_q <= "001000111011001011";
WHEN "0001111" => memoryC0_uid235_exp10TabGen_q <= "001000111111101010";
WHEN "0010000" => memoryC0_uid235_exp10TabGen_q <= "001001000100001011";
WHEN "0010001" => memoryC0_uid235_exp10TabGen_q <= "001001001000101110";
WHEN "0010010" => memoryC0_uid235_exp10TabGen_q <= "001001001101010011";
WHEN "0010011" => memoryC0_uid235_exp10TabGen_q <= "001001010001111011";
WHEN "0010100" => memoryC0_uid235_exp10TabGen_q <= "001001010110100101";
WHEN "0010101" => memoryC0_uid235_exp10TabGen_q <= "001001011011010010";
WHEN "0010110" => memoryC0_uid235_exp10TabGen_q <= "001001100000000000";
WHEN "0010111" => memoryC0_uid235_exp10TabGen_q <= "001001100100110010";
WHEN "0011000" => memoryC0_uid235_exp10TabGen_q <= "001001101001100101";
WHEN "0011001" => memoryC0_uid235_exp10TabGen_q <= "001001101110011011";
WHEN "0011010" => memoryC0_uid235_exp10TabGen_q <= "001001110011010100";
WHEN "0011011" => memoryC0_uid235_exp10TabGen_q <= "001001111000001111";
WHEN "0011100" => memoryC0_uid235_exp10TabGen_q <= "001001111101001100";
WHEN "0011101" => memoryC0_uid235_exp10TabGen_q <= "001010000010001100";
WHEN "0011110" => memoryC0_uid235_exp10TabGen_q <= "001010000111001110";
WHEN "0011111" => memoryC0_uid235_exp10TabGen_q <= "001010001100010011";
WHEN "0100000" => memoryC0_uid235_exp10TabGen_q <= "001010010001011010";
WHEN "0100001" => memoryC0_uid235_exp10TabGen_q <= "001010010110100100";
WHEN "0100010" => memoryC0_uid235_exp10TabGen_q <= "001010011011110001";
WHEN "0100011" => memoryC0_uid235_exp10TabGen_q <= "001010100001000000";
WHEN "0100100" => memoryC0_uid235_exp10TabGen_q <= "001010100110010010";
WHEN "0100101" => memoryC0_uid235_exp10TabGen_q <= "001010101011100111";
WHEN "0100110" => memoryC0_uid235_exp10TabGen_q <= "001010110000111110";
WHEN "0100111" => memoryC0_uid235_exp10TabGen_q <= "001010110110010111";
WHEN "0101000" => memoryC0_uid235_exp10TabGen_q <= "001010111011110100";
WHEN "0101001" => memoryC0_uid235_exp10TabGen_q <= "001011000001010011";
WHEN "0101010" => memoryC0_uid235_exp10TabGen_q <= "001011000110110101";
WHEN "0101011" => memoryC0_uid235_exp10TabGen_q <= "001011001100011010";
WHEN "0101100" => memoryC0_uid235_exp10TabGen_q <= "001011010010000010";
WHEN "0101101" => memoryC0_uid235_exp10TabGen_q <= "001011010111101100";
WHEN "0101110" => memoryC0_uid235_exp10TabGen_q <= "001011011101011001";
WHEN "0101111" => memoryC0_uid235_exp10TabGen_q <= "001011100011001010";
WHEN "0110000" => memoryC0_uid235_exp10TabGen_q <= "001011101000111101";
WHEN "0110001" => memoryC0_uid235_exp10TabGen_q <= "001011101110110011";
WHEN "0110010" => memoryC0_uid235_exp10TabGen_q <= "001011110100101011";
WHEN "0110011" => memoryC0_uid235_exp10TabGen_q <= "001011111010100111";
WHEN "0110100" => memoryC0_uid235_exp10TabGen_q <= "001100000000100110";
WHEN "0110101" => memoryC0_uid235_exp10TabGen_q <= "001100000110101000";
WHEN "0110110" => memoryC0_uid235_exp10TabGen_q <= "001100001100101101";
WHEN "0110111" => memoryC0_uid235_exp10TabGen_q <= "001100010010110101";
WHEN "0111000" => memoryC0_uid235_exp10TabGen_q <= "001100011001000000";
WHEN "0111001" => memoryC0_uid235_exp10TabGen_q <= "001100011111001110";
WHEN "0111010" => memoryC0_uid235_exp10TabGen_q <= "001100100101011111";
WHEN "0111011" => memoryC0_uid235_exp10TabGen_q <= "001100101011110011";
WHEN "0111100" => memoryC0_uid235_exp10TabGen_q <= "001100110010001011";
WHEN "0111101" => memoryC0_uid235_exp10TabGen_q <= "001100111000100101";
WHEN "0111110" => memoryC0_uid235_exp10TabGen_q <= "001100111111000011";
WHEN "0111111" => memoryC0_uid235_exp10TabGen_q <= "001101000101100100";
WHEN "1000000" => memoryC0_uid235_exp10TabGen_q <= "001101001100001001";
WHEN "1000001" => memoryC0_uid235_exp10TabGen_q <= "001101010010110001";
WHEN "1000010" => memoryC0_uid235_exp10TabGen_q <= "001101011001011100";
WHEN "1000011" => memoryC0_uid235_exp10TabGen_q <= "001101100000001010";
WHEN "1000100" => memoryC0_uid235_exp10TabGen_q <= "001101100110111100";
WHEN "1000101" => memoryC0_uid235_exp10TabGen_q <= "001101101101110001";
WHEN "1000110" => memoryC0_uid235_exp10TabGen_q <= "001101110100101010";
WHEN "1000111" => memoryC0_uid235_exp10TabGen_q <= "001101111011100110";
WHEN "1001000" => memoryC0_uid235_exp10TabGen_q <= "001110000010100101";
WHEN "1001001" => memoryC0_uid235_exp10TabGen_q <= "001110001001101000";
WHEN "1001010" => memoryC0_uid235_exp10TabGen_q <= "001110010000101111";
WHEN "1001011" => memoryC0_uid235_exp10TabGen_q <= "001110010111111001";
WHEN "1001100" => memoryC0_uid235_exp10TabGen_q <= "001110011111000111";
WHEN "1001101" => memoryC0_uid235_exp10TabGen_q <= "001110100110011000";
WHEN "1001110" => memoryC0_uid235_exp10TabGen_q <= "001110101101101101";
WHEN "1001111" => memoryC0_uid235_exp10TabGen_q <= "001110110101000110";
WHEN "1010000" => memoryC0_uid235_exp10TabGen_q <= "001110111100100010";
WHEN "1010001" => memoryC0_uid235_exp10TabGen_q <= "001111000100000010";
WHEN "1010010" => memoryC0_uid235_exp10TabGen_q <= "001111001011100110";
WHEN "1010011" => memoryC0_uid235_exp10TabGen_q <= "001111010011001110";
WHEN "1010100" => memoryC0_uid235_exp10TabGen_q <= "001111011010111001";
WHEN "1010101" => memoryC0_uid235_exp10TabGen_q <= "001111100010101001";
WHEN "1010110" => memoryC0_uid235_exp10TabGen_q <= "001111101010011100";
WHEN "1010111" => memoryC0_uid235_exp10TabGen_q <= "001111110010010011";
WHEN "1011000" => memoryC0_uid235_exp10TabGen_q <= "001111111010001110";
WHEN "1011001" => memoryC0_uid235_exp10TabGen_q <= "010000000010001110";
WHEN "1011010" => memoryC0_uid235_exp10TabGen_q <= "010000001010010001";
WHEN "1011011" => memoryC0_uid235_exp10TabGen_q <= "010000010010011000";
WHEN "1011100" => memoryC0_uid235_exp10TabGen_q <= "010000011010100011";
WHEN "1011101" => memoryC0_uid235_exp10TabGen_q <= "010000100010110010";
WHEN "1011110" => memoryC0_uid235_exp10TabGen_q <= "010000101011000110";
WHEN "1011111" => memoryC0_uid235_exp10TabGen_q <= "010000110011011110";
WHEN "1100000" => memoryC0_uid235_exp10TabGen_q <= "010000111011111001";
WHEN "1100001" => memoryC0_uid235_exp10TabGen_q <= "010001000100011001";
WHEN "1100010" => memoryC0_uid235_exp10TabGen_q <= "010001001100111110";
WHEN "1100011" => memoryC0_uid235_exp10TabGen_q <= "010001010101100110";
WHEN "1100100" => memoryC0_uid235_exp10TabGen_q <= "010001011110010011";
WHEN "1100101" => memoryC0_uid235_exp10TabGen_q <= "010001100111000101";
WHEN "1100110" => memoryC0_uid235_exp10TabGen_q <= "010001101111111010";
WHEN "1100111" => memoryC0_uid235_exp10TabGen_q <= "010001111000110101";
WHEN "1101000" => memoryC0_uid235_exp10TabGen_q <= "010010000001110011";
WHEN "1101001" => memoryC0_uid235_exp10TabGen_q <= "010010001010110110";
WHEN "1101010" => memoryC0_uid235_exp10TabGen_q <= "010010010011111110";
WHEN "1101011" => memoryC0_uid235_exp10TabGen_q <= "010010011101001010";
WHEN "1101100" => memoryC0_uid235_exp10TabGen_q <= "010010100110011011";
WHEN "1101101" => memoryC0_uid235_exp10TabGen_q <= "010010101111110001";
WHEN "1101110" => memoryC0_uid235_exp10TabGen_q <= "010010111001001011";
WHEN "1101111" => memoryC0_uid235_exp10TabGen_q <= "010011000010101010";
WHEN "1110000" => memoryC0_uid235_exp10TabGen_q <= "010011001100001110";
WHEN "1110001" => memoryC0_uid235_exp10TabGen_q <= "010011010101110110";
WHEN "1110010" => memoryC0_uid235_exp10TabGen_q <= "010011011111100100";
WHEN "1110011" => memoryC0_uid235_exp10TabGen_q <= "010011101001010110";
WHEN "1110100" => memoryC0_uid235_exp10TabGen_q <= "010011110011001101";
WHEN "1110101" => memoryC0_uid235_exp10TabGen_q <= "010011111101001001";
WHEN "1110110" => memoryC0_uid235_exp10TabGen_q <= "010100000111001010";
WHEN "1110111" => memoryC0_uid235_exp10TabGen_q <= "010100010001010000";
WHEN "1111000" => memoryC0_uid235_exp10TabGen_q <= "010100011011011100";
WHEN "1111001" => memoryC0_uid235_exp10TabGen_q <= "010100100101101100";
WHEN "1111010" => memoryC0_uid235_exp10TabGen_q <= "010100110000000001";
WHEN "1111011" => memoryC0_uid235_exp10TabGen_q <= "010100111010011100";
WHEN "1111100" => memoryC0_uid235_exp10TabGen_q <= "010101000100111100";
WHEN "1111101" => memoryC0_uid235_exp10TabGen_q <= "010101001111100001";
WHEN "1111110" => memoryC0_uid235_exp10TabGen_q <= "010101011010001011";
WHEN "1111111" => memoryC0_uid235_exp10TabGen_q <= "010101100100111011";
WHEN OTHERS =>
memoryC0_uid235_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor(LOGICAL,1133)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_b <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_q <= not (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_a or ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_b);
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena(REG,1134)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_q = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd(LOGICAL,1135)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_a <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_b <= en;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_a and ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_b;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem(DUALMEM,1124)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ia <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 21,
width_b => 7,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ia
);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_iq(6 downto 0);
--reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0(REG,377)@36
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid234_exp10TabGen(LOOKUP,233)@37
memoryC0_uid234_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid234_exp10TabGen_q <= "0000000000000000000000000000000000000100";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC0_uid234_exp10TabGen_q <= "0000000000000000000000000000000000000100";
WHEN "0000001" => memoryC0_uid234_exp10TabGen_q <= "0000000010101011000000000010001000110010";
WHEN "0000010" => memoryC0_uid234_exp10TabGen_q <= "0000010101011010101011101111000111001101";
WHEN "0000011" => memoryC0_uid234_exp10TabGen_q <= "0001001000011011001000001000011011101101";
WHEN "0000100" => memoryC0_uid234_exp10TabGen_q <= "0010101100000000100010010011111101101001";
WHEN "0000101" => memoryC0_uid234_exp10TabGen_q <= "0101010000100111010011100000111110110000";
WHEN "0000110" => memoryC0_uid234_exp10TabGen_q <= "1001000110110100000101001111010001100010";
WHEN "0000111" => memoryC0_uid234_exp10TabGen_q <= "1110011111010011110101011000010011101101";
WHEN "0001000" => memoryC0_uid234_exp10TabGen_q <= "0101101010111011111010011010011101110000";
WHEN "0001001" => memoryC0_uid234_exp10TabGen_q <= "1110111010101010000111100110011000101011";
WHEN "0001010" => memoryC0_uid234_exp10TabGen_q <= "1010011111100100110001001110011010110110";
WHEN "0001011" => memoryC0_uid234_exp10TabGen_q <= "1000101010111010110000111000001101001101";
WHEN "0001100" => memoryC0_uid234_exp10TabGen_q <= "1001101110000011101001110000011001101111";
WHEN "0001101" => memoryC0_uid234_exp10TabGen_q <= "1101111010011111101101000000100100010110";
WHEN "0001110" => memoryC0_uid234_exp10TabGen_q <= "0101100001110111111110000111001111001110";
WHEN "0001111" => memoryC0_uid234_exp10TabGen_q <= "0000110101111110010111010010001011110111";
WHEN "0010000" => memoryC0_uid234_exp10TabGen_q <= "0000001000101101101101111010111001101100";
WHEN "0010001" => memoryC0_uid234_exp10TabGen_q <= "0011101100001001110111000101010011011100";
WHEN "0010010" => memoryC0_uid234_exp10TabGen_q <= "1011110010011111101100000000101100100101";
WHEN "0010011" => memoryC0_uid234_exp10TabGen_q <= "1000101110000101001110101010111111110000";
WHEN "0010100" => memoryC0_uid234_exp10TabGen_q <= "1010110001011001101110010110001111001110";
WHEN "0010101" => memoryC0_uid234_exp10TabGen_q <= "0010001111000101101100010000011000111110";
WHEN "0010110" => memoryC0_uid234_exp10TabGen_q <= "1111011001111011000000001101011110111100";
WHEN "0010111" => memoryC0_uid234_exp10TabGen_q <= "0010100100110100111101010100000101001100";
WHEN "0011000" => memoryC0_uid234_exp10TabGen_q <= "1100000010111000010110101100000110101101";
WHEN "0011001" => memoryC0_uid234_exp10TabGen_q <= "1100000111010011100100010000000010010110";
WHEN "0011010" => memoryC0_uid234_exp10TabGen_q <= "0011000101011110100111100000100000110111";
WHEN "0011011" => memoryC0_uid234_exp10TabGen_q <= "0001010000111011010000011010010101011000";
WHEN "0011100" => memoryC0_uid234_exp10TabGen_q <= "0110111101010101000010001110111001100001";
WHEN "0011101" => memoryC0_uid234_exp10TabGen_q <= "0100011110100001011000011111000110010100";
WHEN "0011110" => memoryC0_uid234_exp10TabGen_q <= "1010001000011111101011111000101011001011";
WHEN "0011111" => memoryC0_uid234_exp10TabGen_q <= "1000001111011001010111010110000100001011";
WHEN "0100000" => memoryC0_uid234_exp10TabGen_q <= "1111000111100001111101000000110000110111";
WHEN "0100001" => memoryC0_uid234_exp10TabGen_q <= "1111000101010111001011010110001100111110";
WHEN "0100010" => memoryC0_uid234_exp10TabGen_q <= "1000011101100001000010001111001100000101";
WHEN "0100011" => memoryC0_uid234_exp10TabGen_q <= "1011100100110001111000001001111001101100";
WHEN "0100100" => memoryC0_uid234_exp10TabGen_q <= "1000110000000110011111010110011110111111";
WHEN "0100101" => memoryC0_uid234_exp10TabGen_q <= "0000010100100110001011000110001111100010";
WHEN "0100110" => memoryC0_uid234_exp10TabGen_q <= "0010100111100010110100111101011110000101";
WHEN "0100111" => memoryC0_uid234_exp10TabGen_q <= "1111111110011001000010000111111011001111";
WHEN "0101000" => memoryC0_uid234_exp10TabGen_q <= "1000101110110000001000101111111110101110";
WHEN "0101001" => memoryC0_uid234_exp10TabGen_q <= "1101001110011010010101011000011101001000";
WHEN "0101010" => memoryC0_uid234_exp10TabGen_q <= "1101110011010100110000011001001011000110";
WHEN "0101011" => memoryC0_uid234_exp10TabGen_q <= "1010110011100111100011011110001111100111";
WHEN "0101100" => memoryC0_uid234_exp10TabGen_q <= "0100100101100101111111001010000110011010";
WHEN "0101101" => memoryC0_uid234_exp10TabGen_q <= "1011011111101110100000011010010100011000";
WHEN "0101110" => memoryC0_uid234_exp10TabGen_q <= "1111111000101010110110001111001110110010";
WHEN "0101111" => memoryC0_uid234_exp10TabGen_q <= "0010000111010000000111010110010111001101";
WHEN "0110000" => memoryC0_uid234_exp10TabGen_q <= "0010100010011110110111110111101101010111";
WHEN "0110001" => memoryC0_uid234_exp10TabGen_q <= "0001100001100011001111000101111000001011";
WHEN "0110010" => memoryC0_uid234_exp10TabGen_q <= "1111011011110100111101010001000111110011";
WHEN "0110011" => memoryC0_uid234_exp10TabGen_q <= "1100101000110111100001011101010001101111";
WHEN "0110100" => memoryC0_uid234_exp10TabGen_q <= "1001100000011010001111011010101000110010";
WHEN "0110101" => memoryC0_uid234_exp10TabGen_q <= "0110011010011000010101100001110010000100";
WHEN "0110110" => memoryC0_uid234_exp10TabGen_q <= "0011101110111001000010110010011000101110";
WHEN "0110111" => memoryC0_uid234_exp10TabGen_q <= "0001110110001111101100110101000001110111";
WHEN "0111000" => memoryC0_uid234_exp10TabGen_q <= "0001001000111011110110000000000010000011";
WHEN "0111001" => memoryC0_uid234_exp10TabGen_q <= "0001111111101001010011011111010101111111";
WHEN "0111010" => memoryC0_uid234_exp10TabGen_q <= "0100110011010000010011011111100000000010";
WHEN "0111011" => memoryC0_uid234_exp10TabGen_q <= "1001111100110101100011011011101011110001";
WHEN "0111100" => memoryC0_uid234_exp10TabGen_q <= "0001110101101010010110001110111001100101";
WHEN "0111101" => memoryC0_uid234_exp10TabGen_q <= "1100110111001100101010101000010011011101";
WHEN "0111110" => memoryC0_uid234_exp10TabGen_q <= "1011011011000111010001100010101100110111";
WHEN "0111111" => memoryC0_uid234_exp10TabGen_q <= "1101111011010001110100011111001111000001";
WHEN "1000000" => memoryC0_uid234_exp10TabGen_q <= "0100110001110000111100000011010011100010";
WHEN "1000001" => memoryC0_uid234_exp10TabGen_q <= "0000011000110110010110011001101110100101";
WHEN "1000010" => memoryC0_uid234_exp10TabGen_q <= "0001001011000000111101110111001010100111";
WHEN "1000011" => memoryC0_uid234_exp10TabGen_q <= "0111100010111100111111100001110111000101";
WHEN "1000100" => memoryC0_uid234_exp10TabGen_q <= "0011111011100100000001111100101011111001";
WHEN "1000101" => memoryC0_uid234_exp10TabGen_q <= "0110101111111101001011110101100011000111";
WHEN "1000110" => memoryC0_uid234_exp10TabGen_q <= "0000011011011101001010110111001010110011";
WHEN "1000111" => memoryC0_uid234_exp10TabGen_q <= "0001011001100110011010011110010000101001";
WHEN "1001000" => memoryC0_uid234_exp10TabGen_q <= "1010000110001001001010110010001000110110";
WHEN "1001001" => memoryC0_uid234_exp10TabGen_q <= "1010111101000011100111100000110010011010";
WHEN "1001010" => memoryC0_uid234_exp10TabGen_q <= "0100011010100001111110111110011010001000";
WHEN "1001011" => memoryC0_uid234_exp10TabGen_q <= "0110111010111110101001001000011110010111";
WHEN "1001100" => memoryC0_uid234_exp10TabGen_q <= "0010111011000010001110101100010101001010";
WHEN "1001101" => memoryC0_uid234_exp10TabGen_q <= "1000110111100011110000010001010110100101";
WHEN "1001110" => memoryC0_uid234_exp10TabGen_q <= "1001001101101000101101100110101101000000";
WHEN "1001111" => memoryC0_uid234_exp10TabGen_q <= "0100011010100101001100110100101101001110";
WHEN "1010000" => memoryC0_uid234_exp10TabGen_q <= "1010111011111100000001110001111000000111";
WHEN "1010001" => memoryC0_uid234_exp10TabGen_q <= "1101001111011110110101011011100111110000";
WHEN "1010010" => memoryC0_uid234_exp10TabGen_q <= "1011110011001110001101010010101001110110";
WHEN "1010011" => memoryC0_uid234_exp10TabGen_q <= "0111000101011001110010111011001001001100";
WHEN "1010100" => memoryC0_uid234_exp10TabGen_q <= "1111100100100000011011100000101000010100";
WHEN "1010101" => memoryC0_uid234_exp10TabGen_q <= "0101101111010000001111011101101110110110";
WHEN "1010110" => memoryC0_uid234_exp10TabGen_q <= "1010000100100110110010000111101011110111";
WHEN "1010111" => memoryC0_uid234_exp10TabGen_q <= "1101000011110001001001011101101110110011";
WHEN "1011000" => memoryC0_uid234_exp10TabGen_q <= "1111001100001100000101111100011001001001";
WHEN "1011001" => memoryC0_uid234_exp10TabGen_q <= "0000111101100100001010010100101010110000";
WHEN "1011010" => memoryC0_uid234_exp10TabGen_q <= "0010110111110101110011100111001010101000";
WHEN "1011011" => memoryC0_uid234_exp10TabGen_q <= "0101011011001101100001000011001110011011";
WHEN "1011100" => memoryC0_uid234_exp10TabGen_q <= "1001001000000111111100001010000010010111";
WHEN "1011101" => memoryC0_uid234_exp10TabGen_q <= "1110011111010010000000110101110011110001";
WHEN "1011110" => memoryC0_uid234_exp10TabGen_q <= "0110000001101001000101100101000000010001";
WHEN "1011111" => memoryC0_uid234_exp10TabGen_q <= "0000010000011011000011101001101011100110";
WHEN "1100000" => memoryC0_uid234_exp10TabGen_q <= "1101101101000110011111011100111110000000";
WHEN "1100001" => memoryC0_uid234_exp10TabGen_q <= "1110111001011010110000110110101101100101";
WHEN "1100010" => memoryC0_uid234_exp10TabGen_q <= "0100010111011000001011101001010100011100";
WHEN "1100011" => memoryC0_uid234_exp10TabGen_q <= "1110101001010000001000000001110101110001";
WHEN "1100100" => memoryC0_uid234_exp10TabGen_q <= "1110010001100101001011001100010100000101";
WHEN "1100101" => memoryC0_uid234_exp10TabGen_q <= "0011110011001011001111111100011010101110";
WHEN "1100110" => memoryC0_uid234_exp10TabGen_q <= "1111110001000111101111011010011100101111";
WHEN "1100111" => memoryC0_uid234_exp10TabGen_q <= "0010101110110001101001110100101011010100";
WHEN "1101000" => memoryC0_uid234_exp10TabGen_q <= "1101001111110001101111010101000110000100";
WHEN "1101001" => memoryC0_uid234_exp10TabGen_q <= "1111111000000010101000111011100111001100";
WHEN "1101010" => memoryC0_uid234_exp10TabGen_q <= "1011001011110001000001011100101101111110";
WHEN "1101011" => memoryC0_uid234_exp10TabGen_q <= "1111101111011011101110100100101001101011";
WHEN "1101100" => memoryC0_uid234_exp10TabGen_q <= "1110000111110011111001111111000111000101";
WHEN "1101101" => memoryC0_uid234_exp10TabGen_q <= "0110111001111101001010100011100011001011";
WHEN "1101110" => memoryC0_uid234_exp10TabGen_q <= "1010101011001101101101100110000101000011";
WHEN "1101111" => memoryC0_uid234_exp10TabGen_q <= "1010000001001110100000001101000001011001";
WHEN "1110000" => memoryC0_uid234_exp10TabGen_q <= "0101100001111011011000101011001001111110";
WHEN "1110001" => memoryC0_uid234_exp10TabGen_q <= "1101110011100011001111111110101011011010";
WHEN "1110010" => memoryC0_uid234_exp10TabGen_q <= "0011011100101000001011010100111011101001";
WHEN "1110011" => memoryC0_uid234_exp10TabGen_q <= "0111000011111111100101110010111011011000";
WHEN "1110100" => memoryC0_uid234_exp10TabGen_q <= "1001010000110010011010000010101101001001";
WHEN "1110101" => memoryC0_uid234_exp10TabGen_q <= "1010101010011101001100000101100100000010";
WHEN "1110110" => memoryC0_uid234_exp10TabGen_q <= "1011111000110000010011001011001101000100";
WHEN "1110111" => memoryC0_uid234_exp10TabGen_q <= "1101100011110000000011101101110101000101";
WHEN "1111000" => memoryC0_uid234_exp10TabGen_q <= "0000010011110100111001010011001110000110";
WHEN "1111001" => memoryC0_uid234_exp10TabGen_q <= "0100110001101011100000110010110110011110";
WHEN "1111010" => memoryC0_uid234_exp10TabGen_q <= "1011100110010101000010100001000100001101";
WHEN "1111011" => memoryC0_uid234_exp10TabGen_q <= "0101011011000111001100011111010111010111";
WHEN "1111100" => memoryC0_uid234_exp10TabGen_q <= "0010111001101100011100110001110101101101";
WHEN "1111101" => memoryC0_uid234_exp10TabGen_q <= "0100101100000100001011111001110010011111";
WHEN "1111110" => memoryC0_uid234_exp10TabGen_q <= "1011011100100010110111010101100100101111";
WHEN "1111111" => memoryC0_uid234_exp10TabGen_q <= "0111110101110010001100000101101110111100";
WHEN OTHERS =>
memoryC0_uid234_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--os_uid236_exp10TabGen(BITJOIN,235)@38
os_uid236_exp10TabGen_q <= memoryC0_uid235_exp10TabGen_q & memoryC0_uid234_exp10TabGen_q;
--rndBit_uid275_exp10PolyEval(CONSTANT,274)
rndBit_uid275_exp10PolyEval_q <= "001";
--cIncludingRoundingBit_uid276_exp10PolyEval(BITJOIN,275)@38
cIncludingRoundingBit_uid276_exp10PolyEval_q <= os_uid236_exp10TabGen_q & rndBit_uid275_exp10PolyEval_q;
--reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0(REG,413)@38
reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q <= cIncludingRoundingBit_uid276_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid277_exp10PolyEval(ADD,276)@39
ts5_uid277_exp10PolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q);
ts5_uid277_exp10PolyEval_b <= STD_LOGIC_VECTOR((61 downto 55 => reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q(54)) & reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q);
ts5_uid277_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid277_exp10PolyEval_a) + SIGNED(ts5_uid277_exp10PolyEval_b));
ts5_uid277_exp10PolyEval_q <= ts5_uid277_exp10PolyEval_o(61 downto 0);
--s5_uid278_exp10PolyEval(BITSELECT,277)@39
s5_uid278_exp10PolyEval_in <= ts5_uid277_exp10PolyEval_q;
s5_uid278_exp10PolyEval_b <= s5_uid278_exp10PolyEval_in(61 downto 1);
--peORExpInc_uid68_fpExpETest(BITSELECT,67)@39
peORExpInc_uid68_fpExpETest_in <= s5_uid278_exp10PolyEval_b(58 downto 0);
peORExpInc_uid68_fpExpETest_b <= peORExpInc_uid68_fpExpETest_in(58 downto 58);
--reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1(REG,415)@39
reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q <= peORExpInc_uid68_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--cstBias_uid8_fpExpETest(CONSTANT,7)
cstBias_uid8_fpExpETest_q <= "01111111111";
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor(LOGICAL,911)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_b <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_q <= not (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_a or ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_b);
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top(CONSTANT,907)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top_q <= "011011";
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp(LOGICAL,908)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_a <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q);
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_q <= "1" when ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_a = ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_b else "0";
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg(REG,909)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena(REG,912)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_q = "1") THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd(LOGICAL,913)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_a <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_b <= en;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_a and ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_b;
--reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0(REG,360)@8
reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q <= ePreRnd_uid46_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg(DELAY,901)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q, xout => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt(COUNTER,903)
-- every=1, low=0, high=27, step=1, init=1
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i = 26 THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i - 27;
ELSE
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i,5));
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg(REG,904)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux(MUX,905)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s <= en;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux: PROCESS (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s, ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q, ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q;
WHEN "1" => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem(DUALMEM,902)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ia <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_aa <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ab <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 5,
numwords_a => 28,
width_b => 14,
widthad_b => 5,
numwords_b => 28,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_iq,
address_a => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_aa,
data_a => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ia
);
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_reset0 <= areset;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_iq(13 downto 0);
--expRPostBiasPreExc0_uid69_fpExpETest(ADD,68)@39
expRPostBiasPreExc0_uid69_fpExpETest_a <= STD_LOGIC_VECTOR((15 downto 14 => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q(13)) & ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q);
expRPostBiasPreExc0_uid69_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "0000" & cstBias_uid8_fpExpETest_q);
expRPostBiasPreExc0_uid69_fpExpETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostBiasPreExc0_uid69_fpExpETest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expRPostBiasPreExc0_uid69_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc0_uid69_fpExpETest_a) + SIGNED(expRPostBiasPreExc0_uid69_fpExpETest_b));
END IF;
END IF;
END PROCESS;
expRPostBiasPreExc0_uid69_fpExpETest_q <= expRPostBiasPreExc0_uid69_fpExpETest_o(14 downto 0);
--expRPostBiasPreExc_uid70_fpExpETest(ADD,69)@40
expRPostBiasPreExc_uid70_fpExpETest_a <= STD_LOGIC_VECTOR((16 downto 15 => expRPostBiasPreExc0_uid69_fpExpETest_q(14)) & expRPostBiasPreExc0_uid69_fpExpETest_q);
expRPostBiasPreExc_uid70_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000000000000" & reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q);
expRPostBiasPreExc_uid70_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid70_fpExpETest_a) + SIGNED(expRPostBiasPreExc_uid70_fpExpETest_b));
expRPostBiasPreExc_uid70_fpExpETest_q <= expRPostBiasPreExc_uid70_fpExpETest_o(15 downto 0);
--expR_uid75_fpExpETest(BITSELECT,74)@40
expR_uid75_fpExpETest_in <= expRPostBiasPreExc_uid70_fpExpETest_q(10 downto 0);
expR_uid75_fpExpETest_b <= expR_uid75_fpExpETest_in(10 downto 0);
--ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d(DELAY,509)@40
ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid75_fpExpETest_b, xout => ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid11_fpExpETest(CONSTANT,10)
cstZeroWE_uid11_fpExpETest_q <= "00000000000";
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor(LOGICAL,1002)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_b <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_q <= not (ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_a or ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_b);
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top(CONSTANT,920)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top_q <= "0100110";
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp(LOGICAL,921)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_a <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q);
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_q <= "1" when ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_a = ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_b else "0";
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg(REG,922)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena(REG,1003)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_q = "1") THEN
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd(LOGICAL,1004)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_a <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_b <= en;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_q <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_a and ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_b;
--cstAllZWF_uid16_fpExpETest(CONSTANT,15)
cstAllZWF_uid16_fpExpETest_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid23_fpExpETest(LOGICAL,22)@0
fracXIsZero_uid23_fpExpETest_a <= frac_uid22_fpExpETest_b;
fracXIsZero_uid23_fpExpETest_b <= cstAllZWF_uid16_fpExpETest_q;
fracXIsZero_uid23_fpExpETest_q <= "1" when fracXIsZero_uid23_fpExpETest_a = fracXIsZero_uid23_fpExpETest_b else "0";
--InvFracXIsZero_uid25_fpExpETest(LOGICAL,24)@0
InvFracXIsZero_uid25_fpExpETest_a <= fracXIsZero_uid23_fpExpETest_q;
InvFracXIsZero_uid25_fpExpETest_q <= not InvFracXIsZero_uid25_fpExpETest_a;
--expXIsMax_uid21_fpExpETest(LOGICAL,20)@0
expXIsMax_uid21_fpExpETest_a <= expX_uid6_fpExpETest_b;
expXIsMax_uid21_fpExpETest_b <= cstAllOWE_uid15_fpExpETest_q;
expXIsMax_uid21_fpExpETest_q <= "1" when expXIsMax_uid21_fpExpETest_a = expXIsMax_uid21_fpExpETest_b else "0";
--exc_N_uid26_fpExpETest(LOGICAL,25)@0
exc_N_uid26_fpExpETest_a <= expXIsMax_uid21_fpExpETest_q;
exc_N_uid26_fpExpETest_b <= InvFracXIsZero_uid25_fpExpETest_q;
exc_N_uid26_fpExpETest_q <= exc_N_uid26_fpExpETest_a and exc_N_uid26_fpExpETest_b;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg(DELAY,992)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid26_fpExpETest_q, xout => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt(COUNTER,916)
-- every=1, low=0, high=38, step=1, init=1
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i = 37 THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i - 38;
ELSE
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i,6));
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg(REG,917)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux(MUX,918)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s <= en;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux: PROCESS (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s, ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q, ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q)
BEGIN
CASE ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s IS
WHEN "0" => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
WHEN "1" => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem(DUALMEM,993)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ia <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_aa <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ab <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 39,
width_b => 1,
widthad_b => 6,
numwords_b => 39,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_iq,
address_a => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_aa,
data_a => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ia
);
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_q <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_iq(0 downto 0);
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor(LOGICAL,989)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_b <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_q <= not (ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_a or ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_b);
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top(CONSTANT,933)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top_q <= "0100101";
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp(LOGICAL,934)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q);
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_q <= "1" when ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_a = ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_b else "0";
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg(REG,935)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena(REG,990)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_q = "1") THEN
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd(LOGICAL,991)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_a <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_b <= en;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_q <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_a and ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_b;
--ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c(DELAY,482)@0
ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExpETest_b, xout => ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid81_fpExpETest(LOGICAL,80)@1
InvSignX_uid81_fpExpETest_a <= ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q;
InvSignX_uid81_fpExpETest_q <= not InvSignX_uid81_fpExpETest_a;
--expOvfInitial_uid41_fpExpETest(BITSELECT,40)@0
expOvfInitial_uid41_fpExpETest_in <= shiftValuePreSat_uid40_fpExpETest_q;
expOvfInitial_uid41_fpExpETest_b <= expOvfInitial_uid41_fpExpETest_in(11 downto 11);
--reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2(REG,417)@0
reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q <= expOvfInitial_uid41_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid27_fpExpETest(LOGICAL,26)@0
InvExc_N_uid27_fpExpETest_a <= exc_N_uid26_fpExpETest_q;
InvExc_N_uid27_fpExpETest_q <= not InvExc_N_uid27_fpExpETest_a;
--exc_I_uid24_fpExpETest(LOGICAL,23)@0
exc_I_uid24_fpExpETest_a <= expXIsMax_uid21_fpExpETest_q;
exc_I_uid24_fpExpETest_b <= fracXIsZero_uid23_fpExpETest_q;
exc_I_uid24_fpExpETest_q <= exc_I_uid24_fpExpETest_a and exc_I_uid24_fpExpETest_b;
--InvExc_I_uid28_fpExpETest(LOGICAL,27)@0
InvExc_I_uid28_fpExpETest_a <= exc_I_uid24_fpExpETest_q;
InvExc_I_uid28_fpExpETest_q <= not InvExc_I_uid28_fpExpETest_a;
--expXIsZero_uid19_fpExpETest(LOGICAL,18)@0
expXIsZero_uid19_fpExpETest_a <= expX_uid6_fpExpETest_b;
expXIsZero_uid19_fpExpETest_b <= cstZeroWE_uid11_fpExpETest_q;
expXIsZero_uid19_fpExpETest_q <= "1" when expXIsZero_uid19_fpExpETest_a = expXIsZero_uid19_fpExpETest_b else "0";
--InvExpXIsZero_uid29_fpExpETest(LOGICAL,28)@0
InvExpXIsZero_uid29_fpExpETest_a <= expXIsZero_uid19_fpExpETest_q;
InvExpXIsZero_uid29_fpExpETest_q <= not InvExpXIsZero_uid29_fpExpETest_a;
--exc_R_uid30_fpExpETest(LOGICAL,29)@0
exc_R_uid30_fpExpETest_a <= InvExpXIsZero_uid29_fpExpETest_q;
exc_R_uid30_fpExpETest_b <= InvExc_I_uid28_fpExpETest_q;
exc_R_uid30_fpExpETest_c <= InvExc_N_uid27_fpExpETest_q;
exc_R_uid30_fpExpETest_q_i <= exc_R_uid30_fpExpETest_a and exc_R_uid30_fpExpETest_b and exc_R_uid30_fpExpETest_c;
exc_R_uid30_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid30_fpExpETest_q, xin => exc_R_uid30_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid82_fpExpETest(LOGICAL,81)@1
regXAndExpOverflowAndPos_uid82_fpExpETest_a <= exc_R_uid30_fpExpETest_q;
regXAndExpOverflowAndPos_uid82_fpExpETest_b <= reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q;
regXAndExpOverflowAndPos_uid82_fpExpETest_c <= InvSignX_uid81_fpExpETest_q;
regXAndExpOverflowAndPos_uid82_fpExpETest_q <= regXAndExpOverflowAndPos_uid82_fpExpETest_a and regXAndExpOverflowAndPos_uid82_fpExpETest_b and regXAndExpOverflowAndPos_uid82_fpExpETest_c;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg(DELAY,979)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid82_fpExpETest_q, xout => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt(COUNTER,929)
-- every=1, low=0, high=37, step=1, init=1
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i = 36 THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i - 37;
ELSE
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i,6));
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg(REG,930)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux(MUX,931)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s <= en;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux: PROCESS (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s, ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q, ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q)
BEGIN
CASE ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s IS
WHEN "0" => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
WHEN "1" => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem(DUALMEM,980)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ia <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_iq,
address_a => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_aa,
data_a => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ia
);
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_reset0 <= areset;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_q <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_iq(0 downto 0);
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor(LOGICAL,924)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_b <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_q <= not (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_a or ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_b);
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena(REG,925)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_q = "1") THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd(LOGICAL,926)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_a <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_b <= en;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_a and ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_b;
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg(DELAY,914)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOvfInitial_uid41_fpExpETest_b, xout => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem(DUALMEM,915)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ia <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_aa <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ab <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 39,
width_b => 1,
widthad_b => 6,
numwords_b => 39,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_iq,
address_a => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_aa,
data_a => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ia
);
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_reset0 <= areset;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_iq(0 downto 0);
--InvExpOvfInitial_uid78_fpExpETest(LOGICAL,77)@41
InvExpOvfInitial_uid78_fpExpETest_a <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_q;
InvExpOvfInitial_uid78_fpExpETest_q <= not InvExpOvfInitial_uid78_fpExpETest_a;
--reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1(REG,416)@40
reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q <= expRPostBiasPreExc_uid70_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid74_fpExpETest(COMPARE,73)@41
expOvf_uid74_fpExpETest_cin <= GND_q;
expOvf_uid74_fpExpETest_a <= STD_LOGIC_VECTOR((17 downto 16 => reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q(15)) & reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q) & '0';
expOvf_uid74_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000" & cstAllOWE_uid15_fpExpETest_q) & expOvf_uid74_fpExpETest_cin(0);
expOvf_uid74_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid74_fpExpETest_a) - SIGNED(expOvf_uid74_fpExpETest_b));
expOvf_uid74_fpExpETest_n(0) <= not expOvf_uid74_fpExpETest_o(18);
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor(LOGICAL,937)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_b <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_q <= not (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_a or ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_b);
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena(REG,938)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_q = "1") THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd(LOGICAL,939)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_b <= en;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_a and ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_b;
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg(DELAY,927)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid30_fpExpETest_q, xout => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem(DUALMEM,928)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ia <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_iq,
address_a => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_aa,
data_a => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ia
);
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_reset0 <= areset;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_iq(0 downto 0);
--regInAndOvf_uid84_fpExpETest(LOGICAL,83)@41
regInAndOvf_uid84_fpExpETest_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q;
regInAndOvf_uid84_fpExpETest_b <= expOvf_uid74_fpExpETest_n;
regInAndOvf_uid84_fpExpETest_c <= InvExpOvfInitial_uid78_fpExpETest_q;
regInAndOvf_uid84_fpExpETest_q <= regInAndOvf_uid84_fpExpETest_a and regInAndOvf_uid84_fpExpETest_b and regInAndOvf_uid84_fpExpETest_c;
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor(LOGICAL,976)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_b <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_q <= not (ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_a or ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_b);
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena(REG,977)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_q = "1") THEN
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd(LOGICAL,978)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_a <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_b <= en;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_q <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_a and ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_b;
--ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a(DELAY,497)@0
ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid24_fpExpETest_q, xout => ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid86_fpExpETest(LOGICAL,85)@1
posInf_uid86_fpExpETest_a <= ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a_q;
posInf_uid86_fpExpETest_b <= InvSignX_uid81_fpExpETest_q;
posInf_uid86_fpExpETest_q <= posInf_uid86_fpExpETest_a and posInf_uid86_fpExpETest_b;
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg(DELAY,966)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => posInf_uid86_fpExpETest_q, xout => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem(DUALMEM,967)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ia <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_iq,
address_a => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_aa,
data_a => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ia
);
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_reset0 <= areset;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_q <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_iq(0 downto 0);
--excRInf_uid87_fpExpETest(LOGICAL,86)@41
excRInf_uid87_fpExpETest_a <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_q;
excRInf_uid87_fpExpETest_b <= regInAndOvf_uid84_fpExpETest_q;
excRInf_uid87_fpExpETest_c <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_q;
excRInf_uid87_fpExpETest_q <= excRInf_uid87_fpExpETest_a or excRInf_uid87_fpExpETest_b or excRInf_uid87_fpExpETest_c;
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor(LOGICAL,963)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_b <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_q <= not (ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_a or ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_b);
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena(REG,964)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_q = "1") THEN
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd(LOGICAL,965)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_a <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_b <= en;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_q <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_a and ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_b;
--negInf_uid76_fpExpETest(LOGICAL,75)@0
negInf_uid76_fpExpETest_a <= exc_I_uid24_fpExpETest_q;
negInf_uid76_fpExpETest_b <= signX_uid7_fpExpETest_b;
negInf_uid76_fpExpETest_q <= negInf_uid76_fpExpETest_a and negInf_uid76_fpExpETest_b;
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg(DELAY,953)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => negInf_uid76_fpExpETest_q, xout => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem(DUALMEM,954)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ia <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_aa <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ab <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 39,
width_b => 1,
widthad_b => 6,
numwords_b => 39,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_iq,
address_a => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_aa,
data_a => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ia
);
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_reset0 <= areset;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_q <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_iq(0 downto 0);
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor(LOGICAL,950)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_b <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_q <= not (ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_a or ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_b);
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena(REG,951)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_q = "1") THEN
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd(LOGICAL,952)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_a <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_b <= en;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_q <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_a and ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_b;
--regXAndExpOverflowAndNeg_uid77_fpExpETest(LOGICAL,76)@1
regXAndExpOverflowAndNeg_uid77_fpExpETest_a <= exc_R_uid30_fpExpETest_q;
regXAndExpOverflowAndNeg_uid77_fpExpETest_b <= reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q;
regXAndExpOverflowAndNeg_uid77_fpExpETest_c <= ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q;
regXAndExpOverflowAndNeg_uid77_fpExpETest_q <= regXAndExpOverflowAndNeg_uid77_fpExpETest_a and regXAndExpOverflowAndNeg_uid77_fpExpETest_b and regXAndExpOverflowAndNeg_uid77_fpExpETest_c;
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg(DELAY,940)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid77_fpExpETest_q, xout => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem(DUALMEM,941)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ia <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_iq,
address_a => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_aa,
data_a => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ia
);
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_reset0 <= areset;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_q <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_iq(0 downto 0);
--expUdf_uid72_fpExpETest(COMPARE,71)@41
expUdf_uid72_fpExpETest_cin <= GND_q;
expUdf_uid72_fpExpETest_a <= STD_LOGIC_VECTOR('0' & "0000000000000000" & GND_q) & '0';
expUdf_uid72_fpExpETest_b <= STD_LOGIC_VECTOR((17 downto 16 => reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q(15)) & reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q) & expUdf_uid72_fpExpETest_cin(0);
expUdf_uid72_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid72_fpExpETest_a) - SIGNED(expUdf_uid72_fpExpETest_b));
expUdf_uid72_fpExpETest_n(0) <= not expUdf_uid72_fpExpETest_o(18);
--regXAndUdf_uid79_fpExpETest(LOGICAL,78)@41
regXAndUdf_uid79_fpExpETest_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q;
regXAndUdf_uid79_fpExpETest_b <= expUdf_uid72_fpExpETest_n;
regXAndUdf_uid79_fpExpETest_c <= InvExpOvfInitial_uid78_fpExpETest_q;
regXAndUdf_uid79_fpExpETest_q <= regXAndUdf_uid79_fpExpETest_a and regXAndUdf_uid79_fpExpETest_b and regXAndUdf_uid79_fpExpETest_c;
--excRZero_uid80_fpExpETest(LOGICAL,79)@41
excRZero_uid80_fpExpETest_a <= regXAndUdf_uid79_fpExpETest_q;
excRZero_uid80_fpExpETest_b <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_q;
excRZero_uid80_fpExpETest_c <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_q;
excRZero_uid80_fpExpETest_q <= excRZero_uid80_fpExpETest_a or excRZero_uid80_fpExpETest_b or excRZero_uid80_fpExpETest_c;
--concExc_uid88_fpExpETest(BITJOIN,87)@41
concExc_uid88_fpExpETest_q <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_q & excRInf_uid87_fpExpETest_q & excRZero_uid80_fpExpETest_q;
--reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0(REG,420)@41
reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q <= concExc_uid88_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid89_fpExpETest(LOOKUP,88)@42
excREnc_uid89_fpExpETest: PROCESS (reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q) IS
WHEN "000" => excREnc_uid89_fpExpETest_q <= "01";
WHEN "001" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "010" => excREnc_uid89_fpExpETest_q <= "10";
WHEN "011" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "100" => excREnc_uid89_fpExpETest_q <= "11";
WHEN "101" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "110" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "111" => excREnc_uid89_fpExpETest_q <= "00";
WHEN OTHERS =>
excREnc_uid89_fpExpETest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid97_fpExpETest(MUX,96)@42
expRPostExc_uid97_fpExpETest_s <= excREnc_uid89_fpExpETest_q;
expRPostExc_uid97_fpExpETest: PROCESS (expRPostExc_uid97_fpExpETest_s, en, cstZeroWE_uid11_fpExpETest_q, ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q, cstAllOWE_uid15_fpExpETest_q, cstAllOWE_uid15_fpExpETest_q)
BEGIN
CASE expRPostExc_uid97_fpExpETest_s IS
WHEN "00" => expRPostExc_uid97_fpExpETest_q <= cstZeroWE_uid11_fpExpETest_q;
WHEN "01" => expRPostExc_uid97_fpExpETest_q <= ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q;
WHEN "10" => expRPostExc_uid97_fpExpETest_q <= cstAllOWE_uid15_fpExpETest_q;
WHEN "11" => expRPostExc_uid97_fpExpETest_q <= cstAllOWE_uid15_fpExpETest_q;
WHEN OTHERS => expRPostExc_uid97_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid90_fpExpETest(CONSTANT,89)
oneFracRPostExc2_uid90_fpExpETest_q <= "0000000000000000000000000000000000000000000000000001";
--peOR_uid67_fpExpETest(BITSELECT,66)@39
peOR_uid67_fpExpETest_in <= s5_uid278_exp10PolyEval_b(57 downto 0);
peOR_uid67_fpExpETest_b <= peOR_uid67_fpExpETest_in(57 downto 5);
--fracR_uid71_fpExpETest(BITSELECT,70)@39
fracR_uid71_fpExpETest_in <= peOR_uid67_fpExpETest_b(51 downto 0);
fracR_uid71_fpExpETest_b <= fracR_uid71_fpExpETest_in(51 downto 0);
--ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg(DELAY,1005)
ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracR_uid71_fpExpETest_b, xout => ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d(DELAY,507)@39
ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg_q, xout => ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid93_fpExpETest(MUX,92)@42
fracRPostExc_uid93_fpExpETest_s <= excREnc_uid89_fpExpETest_q;
fracRPostExc_uid93_fpExpETest: PROCESS (fracRPostExc_uid93_fpExpETest_s, en, cstAllZWF_uid16_fpExpETest_q, ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q, cstAllZWF_uid16_fpExpETest_q, oneFracRPostExc2_uid90_fpExpETest_q)
BEGIN
CASE fracRPostExc_uid93_fpExpETest_s IS
WHEN "00" => fracRPostExc_uid93_fpExpETest_q <= cstAllZWF_uid16_fpExpETest_q;
WHEN "01" => fracRPostExc_uid93_fpExpETest_q <= ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q;
WHEN "10" => fracRPostExc_uid93_fpExpETest_q <= cstAllZWF_uid16_fpExpETest_q;
WHEN "11" => fracRPostExc_uid93_fpExpETest_q <= oneFracRPostExc2_uid90_fpExpETest_q;
WHEN OTHERS => fracRPostExc_uid93_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RExpE_uid98_fpExpETest(BITJOIN,97)@42
RExpE_uid98_fpExpETest_q <= GND_q & expRPostExc_uid97_fpExpETest_q & fracRPostExc_uid93_fpExpETest_q;
--xOut(GPOUT,4)@42
q <= RExpE_uid98_fpExpETest_q;
end normal;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_log.vhd | 10 | 7973 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/hcc_normfp2x_sv.vhd | 10 | 15740 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** 20/04/09 - add NAN support, add overflow ***
--*** check in target=0 code ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff, aananff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal overflowbitnode : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal overflowcondition : STD_LOGIC;
signal overflowconditionff : STD_LOGIC;
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
aananff(1) <= aanan;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
aananff(k) <= aananff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth = 2) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
expbotdelff(2)(13 DOWNTO 1) <= expbotdelff(1)(13 DOWNTO 1) + ("000000000000" & overflowcondition);
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(2)(13 DOWNTO 1);
END GENERATE;
gxc: IF (expbotffdepth > 2) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth-1 LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
expbotdelff(expbotffdepth)(13 DOWNTO 1) <= expbotdelff(expbotffdepth-1)(13 DOWNTO 1) +
("000000000000" & overflowcondition);
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
overflowcondition <= '0'; -- 20/05/09 used in exponent calculation
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
overflowbitnode(1) <= normalaaff(1);
gova: FOR k IN 2 TO 55 GENERATE
overflowbitnode(k) <= overflowbitnode(k-1) AND normalaaff(k);
END GENERATE;
gng: IF (doublespeed = 0) GENERATE
overflowcondition <= overflowbitnode(55);
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
overflowconditionff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
overflowconditionff <= overflowbitnode(55);
END IF;
END IF;
END PROCESS;
overflowcondition <= overflowconditionff;
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & (mantissa(54) OR mantissa(53)) & mantissa(52 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
ccnan <= aananff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
-- overflow cannot happen here, dont insert
overflowcondition <= '0'; -- 20/05/09 used for exponent
pnf: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
png: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
ccnan <= aananff(latency);
END GENERATE;
end rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_fabs.vhd | 10 | 3173 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_fabs;
ARCHITECTURE rtl OF fp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 8 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(8));
expmax <= expmaxchk(8);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(23));
mannonzero <= manzerochk(23);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/dspba_library.vhd | 22 | 1907 | -- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_rsft36.vhd | 10 | 4583 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT36.VHD ***
--*** ***
--*** Function: 36 bit Unsigned Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_rsft36;
ARCHITECTURE rtl OF fp_rsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2) AND NOT(shift(1)));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND NOT(shift(2)) AND shift(1));
levone(36) <= levzip(36) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 33 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 21 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_ln1px_s5.vhd | 10 | 473588 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1px_s5
-- VHDL created on Mon Mar 11 11:48:38 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from /data/tczajkow/polyeval/p4/ip/aion/src/mip_common/hw_model.cpp:1303
entity fp_ln1px_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1px_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(23 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(8 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(8 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (8 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (24 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a : std_logic_vector (24 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_s1 : std_logic_vector (51 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_pr : SIGNED (51 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (34 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(57 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(57 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(57 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (9 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (22 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad6_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal mO_uid187_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid246_constMult_q : std_logic_vector(36 downto 0);
signal zs_uid267_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal mO_uid270_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (4 downto 0);
signal vCount_uid283_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid283_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid283_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid295_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid295_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid295_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid311_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal leftShiftStage1Idx3Pad12_uid322_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx3Pad3_uid333_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal prodXY_uid339_pT1_uid255_natLogPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid339_pT1_uid255_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid339_pT1_uid255_natLogPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid339_pT1_uid255_natLogPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid339_pT1_uid255_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid342_pT2_uid261_natLogPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid342_pT2_uid261_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid342_pT2_uid261_natLogPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid342_pT2_uid261_natLogPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid342_pT2_uid261_natLogPolyEval_q : std_logic_vector (38 downto 0);
signal memoryC0_uid251_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid251_natLogTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid251_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid251_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid251_natLogTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid251_natLogTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid252_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid252_natLogTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid252_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid252_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid252_natLogTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid252_natLogTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid253_natLogTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid253_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid253_natLogTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_natLogTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_q : std_logic_vector (2 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (4 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (47 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (47 downto 0);
signal reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (47 downto 0);
signal reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (46 downto 0);
signal reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (46 downto 0);
signal reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (46 downto 0);
signal reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (46 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (23 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (23 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (23 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1_q : std_logic_vector (26 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (7 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (7 downto 0);
signal reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0_q : std_logic_vector (2 downto 0);
signal reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (58 downto 0);
signal reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (58 downto 0);
signal reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (58 downto 0);
signal reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (58 downto 0);
signal reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (58 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (4 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (9 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (33 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (31 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_q : std_logic_vector (48 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_a_q : std_logic_vector (7 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_q : std_logic_vector (3 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_q : std_logic_vector (8 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_q : std_logic_vector (23 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (9 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (45 downto 0);
signal ld_RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (43 downto 0);
signal ld_RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (41 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (26 downto 0);
signal ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid283_countZ_uid114_fpLogE1pxTest_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (56 downto 0);
signal ld_LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC1_uid252_natLogTabGen_lutmem_0_q_to_memoryC1_uid252_natLogTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q_to_reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid277_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b_to_reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (48 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_inputreg_q : std_logic_vector (24 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (24 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (24 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (24 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (42 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (58 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (58 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (58 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (58 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q : signal is true;
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_reset0 : std_logic;
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_inputreg_q : std_logic_vector (4 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_reset0 : std_logic;
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ia : std_logic_vector (4 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_iq : std_logic_vector (4 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_q : std_logic_vector (4 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(34 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(34 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (34 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (34 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(34 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(34 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (34 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(8 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(8 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (8 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(48 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(48 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (48 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (48 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(8 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(8 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (8 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(24 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(24 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (24 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (24 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (10 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (10 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (10 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(9 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(9 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (9 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (9 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (10 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (34 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(58 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(58 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (58 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(5 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(5 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (5 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (10 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal p0_uid247_constMult_q : std_logic_vector(33 downto 0);
signal lev1_a0_uid248_constMult_a : std_logic_vector(38 downto 0);
signal lev1_a0_uid248_constMult_b : std_logic_vector(38 downto 0);
signal lev1_a0_uid248_constMult_o : std_logic_vector (38 downto 0);
signal lev1_a0_uid248_constMult_q : std_logic_vector (37 downto 0);
signal vCount_uid269_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid269_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid269_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid277_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid277_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid277_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid280_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid280_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid286_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid286_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid298_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid298_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (21 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (21 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal cStage_uid272_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_b : std_logic_vector (23 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (22 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (22 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (46 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (46 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStagei_uid274_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid274_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (22 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (4 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (46 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (4 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (24 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (22 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (22 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (22 downto 0);
signal xv0_uid244_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid244_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid245_constMult_in : std_logic_vector (8 downto 0);
signal xv1_uid245_constMult_b : std_logic_vector (2 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(35 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(35 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (35 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (35 downto 0);
signal rVStage_uid268_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (58 downto 0);
signal rVStage_uid268_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid271_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (26 downto 0);
signal vStage_uid271_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (26 downto 0);
signal X42dto0_uid306_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal X10dto0_uid312_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (9 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (45 downto 0);
signal LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (45 downto 0);
signal sR_uid249_constMult_in : std_logic_vector (36 downto 0);
signal sR_uid249_constMult_b : std_logic_vector (34 downto 0);
signal rVStage_uid282_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid282_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid284_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid284_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid288_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid288_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid290_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid290_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid300_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid300_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (57 downto 0);
signal lowRangeB_uid256_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid256_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid257_natLogPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid257_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid262_natLogPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid262_natLogPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid263_natLogPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid263_natLogPolyEval_b : std_logic_vector (21 downto 0);
signal RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (46 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (57 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (38 downto 0);
signal X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (38 downto 0);
signal X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (30 downto 0);
signal X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (30 downto 0);
signal X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (22 downto 0);
signal X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (22 downto 0);
signal yT1_uid254_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid254_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal rVStage_uid276_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid276_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid278_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid278_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (24 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal vCount_uid289_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid289_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid289_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid292_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid292_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid301_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid301_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid301_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal FullSumAB57_uid110_fpLogE1pxTest_in : std_logic_vector (57 downto 0);
signal FullSumAB57_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal sumAHighB_uid258_natLogPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid258_natLogPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid258_natLogPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid258_natLogPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid264_natLogPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid264_natLogPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid264_natLogPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid264_natLogPolyEval_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (33 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal leftShiftStage0Idx1_uid218_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal leftShiftStage0Idx2_uid221_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal leftShiftStage0Idx3_uid224_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid213_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal rVStage_uid294_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid294_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid296_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid296_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid302_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal s1_uid256_uid259_natLogPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid262_uid265_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (39 downto 0);
signal X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(8 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(8 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (8 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (46 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (24 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(9 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(9 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (9 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (9 downto 0);
signal leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (32 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (26 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (24 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (44 downto 0);
signal LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (44 downto 0);
signal LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (54 downto 0);
signal LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (54 downto 0);
signal LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (46 downto 0);
signal LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (46 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (45 downto 0);
signal RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (43 downto 0);
signal RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (41 downto 0);
signal leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable(LOGICAL,845)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_a <= en;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q <= not ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,978)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_mem_top(CONSTANT,948)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_mem_top_q <= "011011";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,949)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,950)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,979)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,980)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(31 downto 31);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,562)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "00000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,418)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(22 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(22 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(30 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(30 downto 23);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,420)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,553)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(34);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,556)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,427)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@1
excRNaN_uid140_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@1
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid141_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
END IF;
END PROCESS;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,968)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt(COUNTER,944)
-- every=1, low=0, high=27, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i = 26 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i - 27;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg(REG,945)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux(MUX,946)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,969)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 28,
width_b => 1,
widthad_b => 5,
numwords_b => 28,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,965)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,935)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "011100";
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,936)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,937)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,966)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,967)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,955)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,931)
-- every=1, low=0, high=28, step=1, init=1
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 27 THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 28;
ELSE
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,932)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,933)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,956)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 29,
width_b => 8,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(7 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,925)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,921)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "010010";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,922)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,923)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,926)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,927)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(10);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,493)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 7 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01100111";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(10);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(10);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(10);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,492)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 7 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@7
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,373)@7
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor(LOGICAL,1085)
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_b <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_q <= not (ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_a or ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_mem_top(CONSTANT,895)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,896)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,897)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena(REG,1086)
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_q = "1") THEN
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd(LOGICAL,1087)
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_a <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_b <= en;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_q <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_a and ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(8 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(4 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(4 downto 0);
--ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_inputreg(DELAY,1075)
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 5, depth => 1 )
PORT MAP ( xin => shifterAddr_uid35_fpLogE1pxTest_b, xout => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt(COUNTER,891)
-- every=1, low=0, high=4, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg(REG,892)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux(MUX,893)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem(DUALMEM,1076)
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ia <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_inputreg_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 5,
widthad_a => 3,
numwords_a => 5,
width_b => 5,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_iq,
address_a => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_aa,
data_a => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ia
);
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_reset0 <= areset;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_q <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_iq(4 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,409)@7
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@8
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(5 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,915)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,917)
-- every=1, low=0, high=18, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 17 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 18;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,918)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,919)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,916)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 19,
width_b => 6,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(5 downto 0);
--zs_uid267_countZ_uid114_fpLogE1pxTest(CONSTANT,266)
zs_uid267_countZ_uid114_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,238)@7
LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q(45 downto 0);
LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_in(45 downto 0);
--leftShiftStage2Idx1_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,239)@7
leftShiftStage2Idx1_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_b & GND_q;
--X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,222)@6
X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(22 downto 0);
X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_in(22 downto 0);
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid224_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,223)@6
leftShiftStage0Idx3_uid224_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_b & padConst_uid36_fpLogE1pxTest_q;
--X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,219)@6
X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(30 downto 0);
X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_in(30 downto 0);
--rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx2_uid221_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,220)@6
leftShiftStage0Idx2_uid221_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,216)@6
X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(38 downto 0);
X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_in(38 downto 0);
--leftShiftStage0Idx1_uid218_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,217)@6
leftShiftStage0Idx1_uid218_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_b & cstAllZWE_uid17_fpLogE1pxTest_q;
--RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 1);
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@2
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b;
--X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 24);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= padConst_uid36_fpLogE1pxTest_q & X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 16);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 8);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q & X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,351)@0
reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 6);
--ld_RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,591)@1
ld_RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad6_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 4);
--ld_RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,589)@1
ld_RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 44, depth => 1 )
PORT MAP ( xin => RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 2);
--ld_RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,587)@1
ld_RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,353)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,352)@0
reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,593)@1
ld_reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@0
rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(0 downto 0);
--ld_rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,601)@0
ld_rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest(MUX,181)@2
rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "0" => rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "1" => rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,355)@2
reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@2
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((46 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,354)@2
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@3
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(48 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,835)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a(DELAY,441)@3
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 49, depth => 2 )
PORT MAP ( xin => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@6
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_q(46 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(46 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@3
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(46 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(46 downto 23);
--rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,184)@3
rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_in(23 downto 8);
--reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1(REG,356)@3
reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid186_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,185)@4
vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--ld_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q_to_reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_a(DELAY,786)@4
ld_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q_to_reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q_to_reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4(REG,364)@5
reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_q <= ld_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q_to_reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid188_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,187)@3
vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(7 downto 0);
vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--mO_uid187_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,186)
mO_uid187_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111";
--cStage_uid189_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,188)@3
cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid187_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3(REG,358)@3
reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest(MUX,190)@4
vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,192)@4
rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid194_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,193)@4
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_b) THEN
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q <= "1";
ELSE
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,634)@5
ld_vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,194)@4
vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,360)@4
reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2(REG,359)@4
reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@5
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2(REG,363)@5
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@5
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@5
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@5
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b) THEN
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q <= "1";
ELSE
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@5
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,362)@5
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,361)@5
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@6
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@6
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@6
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid213_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,212)@6
r_uid213_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_q & ld_vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,224)@6
leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid213_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_in(4 downto 3);
--leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,225)@6
leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid218_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid221_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid224_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid218_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid221_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid224_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,233)@6
LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q(40 downto 0);
LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_in(40 downto 0);
--rightShiftStage1Idx3Pad6_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad6_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000";
--leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,234)@6
leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad6_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,369)@6
reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,230)@6
LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q(42 downto 0);
LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_in(42 downto 0);
--leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,231)@6
leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,368)@6
reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,227)@6
LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q(44 downto 0);
LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_in(44 downto 0);
--leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,228)@6
leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_b & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,367)@6
reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,366)@6
reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,235)@6
leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid213_leadingZeros_uid44_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,365)@6
reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,236)@7
leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,240)@6
leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid213_leadingZeros_uid44_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,663)@6
ld_leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,241)@7
leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx1_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@7
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(46 downto 22);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@7
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(23 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(23 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,372)@7
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor(LOGICAL,1061)
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_b <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_q <= not (ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_a or ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_mem_top(CONSTANT,868)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp(LOGICAL,869)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_mem_top_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_q <= "1" when ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_a = ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_b else "0";
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg(REG,870)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena(REG,1062)
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_q = "1") THEN
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd(LOGICAL,1063)
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_a <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_b <= en;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_q <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_a and ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@2
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(47 downto 23);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@2
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(23 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(23 downto 0);
--ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_inputreg(DELAY,1051)
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => fracXRSRange_uid81_fpLogE1pxTest_b, xout => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt(COUNTER,864)
-- every=1, low=0, high=2, step=1, init=1
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg(REG,865)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux(MUX,866)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_s, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem(DUALMEM,1052)
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ia <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_inputreg_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_aa <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ab <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_iq,
address_a => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_aa,
data_a => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ia
);
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_reset0 <= areset;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_q <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_iq(23 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,371)@7
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,872)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,873)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,874)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(8 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(4 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(4 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,349)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "100000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "00000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "100000000000000000000000";
WHEN "00001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "010000000000000000000000";
WHEN "00010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "001000000000000000000000";
WHEN "00011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000100000000000000000000";
WHEN "00100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000010000000000000000000";
WHEN "00101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000001000000000000000000";
WHEN "00110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000100000000000000000";
WHEN "00111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000010000000000000000";
WHEN "01000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000001000000000000000";
WHEN "01001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000100000000000000";
WHEN "01010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000010000000000000";
WHEN "01011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000001000000000000";
WHEN "01100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000100000000000";
WHEN "01101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000010000000000";
WHEN "01110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000001000000000";
WHEN "01111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000100000000";
WHEN "10000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000010000000";
WHEN "10001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000001000000";
WHEN "10010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000100000";
WHEN "10011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000010000";
WHEN "10100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000001000";
WHEN "10101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000000100";
WHEN "10110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000000010";
WHEN "10111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,350)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(24 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(23 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(23 downto 0);
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(22 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(22 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(24 downto 24);
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@2
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= join_uid58_fpLogE1pxTest_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,862)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,863)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(23 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,859)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_mem_top(CONSTANT,842)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_mem_top_q <= "011";
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp(LOGICAL,843)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_mem_top_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q);
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_q <= "1" when ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_a = ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_b else "0";
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg(REG,844)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,860)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,861)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,849)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt(COUNTER,838)
-- every=1, low=0, high=3, step=1, init=1
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_i <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_i,2));
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg(REG,839)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux(MUX,840)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_s, ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q, ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,850)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 2,
numwords_a => 4,
width_b => 23,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(22 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@7
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,370)@7
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10010111";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(10);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(10);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,348)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a(DELAY,477)@1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 4, depth => 5 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@6
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,485)@7
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@8
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@8
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(23 downto 16);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@8
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0(REG,374)@8
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_natLogTabGen_lutmem(DUALMEM,346)@9
memoryC2_uid253_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid253_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid253_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q;
memoryC2_uid253_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 9,
numwords_a => 512,
width_b => 13,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1px_s5_memoryC2_uid253_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid253_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid253_natLogTabGen_lutmem_ia
);
memoryC2_uid253_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid253_natLogTabGen_lutmem_q <= memoryC2_uid253_natLogTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1(REG,376)@11
reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1_q <= memoryC2_uid253_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,888)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a(DELAY,497)@8
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@11
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_q(15 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(15 downto 0);
--yT1_uid254_natLogPolyEval(BITSELECT,253)@11
yT1_uid254_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid254_natLogPolyEval_b <= yT1_uid254_natLogPolyEval_in(15 downto 3);
--reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0(REG,375)@11
reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0_q <= yT1_uid254_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid339_pT1_uid255_natLogPolyEval(MULT,338)@12
prodXY_uid339_pT1_uid255_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid339_pT1_uid255_natLogPolyEval_a),14)) * SIGNED(prodXY_uid339_pT1_uid255_natLogPolyEval_b);
prodXY_uid339_pT1_uid255_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid339_pT1_uid255_natLogPolyEval_a <= (others => '0');
prodXY_uid339_pT1_uid255_natLogPolyEval_b <= (others => '0');
prodXY_uid339_pT1_uid255_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid339_pT1_uid255_natLogPolyEval_a <= reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0_q;
prodXY_uid339_pT1_uid255_natLogPolyEval_b <= reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1_q;
prodXY_uid339_pT1_uid255_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid339_pT1_uid255_natLogPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid339_pT1_uid255_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid339_pT1_uid255_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid339_pT1_uid255_natLogPolyEval_q <= prodXY_uid339_pT1_uid255_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval(BITSELECT,339)@15
prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_in <= prodXY_uid339_pT1_uid255_natLogPolyEval_q;
prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_b <= prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_in(25 downto 12);
--highBBits_uid257_natLogPolyEval(BITSELECT,256)@15
highBBits_uid257_natLogPolyEval_in <= prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_b;
highBBits_uid257_natLogPolyEval_b <= highBBits_uid257_natLogPolyEval_in(13 downto 1);
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC1_uid252_natLogTabGen_lutmem_0_q_to_memoryC1_uid252_natLogTabGen_lutmem_a(DELAY,767)@9
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC1_uid252_natLogTabGen_lutmem_0_q_to_memoryC1_uid252_natLogTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q, xout => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC1_uid252_natLogTabGen_lutmem_0_q_to_memoryC1_uid252_natLogTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid252_natLogTabGen_lutmem(DUALMEM,345)@12
memoryC1_uid252_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid252_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid252_natLogTabGen_lutmem_ab <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC1_uid252_natLogTabGen_lutmem_0_q_to_memoryC1_uid252_natLogTabGen_lutmem_a_q;
memoryC1_uid252_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1px_s5_memoryC1_uid252_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid252_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid252_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid252_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid252_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid252_natLogTabGen_lutmem_ia
);
memoryC1_uid252_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid252_natLogTabGen_lutmem_q <= memoryC1_uid252_natLogTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0(REG,378)@14
reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0_q <= memoryC1_uid252_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid258_natLogPolyEval(ADD,257)@15
sumAHighB_uid258_natLogPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0_q(20)) & reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0_q);
sumAHighB_uid258_natLogPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid257_natLogPolyEval_b(12)) & highBBits_uid257_natLogPolyEval_b);
sumAHighB_uid258_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid258_natLogPolyEval_a) + SIGNED(sumAHighB_uid258_natLogPolyEval_b));
sumAHighB_uid258_natLogPolyEval_q <= sumAHighB_uid258_natLogPolyEval_o(21 downto 0);
--lowRangeB_uid256_natLogPolyEval(BITSELECT,255)@15
lowRangeB_uid256_natLogPolyEval_in <= prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_b(0 downto 0);
lowRangeB_uid256_natLogPolyEval_b <= lowRangeB_uid256_natLogPolyEval_in(0 downto 0);
--s1_uid256_uid259_natLogPolyEval(BITJOIN,258)@15
s1_uid256_uid259_natLogPolyEval_q <= sumAHighB_uid258_natLogPolyEval_q & lowRangeB_uid256_natLogPolyEval_b;
--reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1(REG,380)@15
reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1_q <= s1_uid256_uid259_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor(LOGICAL,1072)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_b);
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg(REG,987)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena(REG,1073)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd(LOGICAL,1074)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_inputreg(DELAY,1064)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt(COUNTER,983)
-- every=1, low=0, high=1, step=1, init=1
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_i <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_i,1));
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg(REG,984)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux(MUX,985)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_s, ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q, ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem(DUALMEM,1065)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_aa <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ab <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 1,
numwords_a => 2,
width_b => 16,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0(REG,379)@15
reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid342_pT2_uid261_natLogPolyEval(MULT,341)@16
prodXY_uid342_pT2_uid261_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid342_pT2_uid261_natLogPolyEval_a),17)) * SIGNED(prodXY_uid342_pT2_uid261_natLogPolyEval_b);
prodXY_uid342_pT2_uid261_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid342_pT2_uid261_natLogPolyEval_a <= (others => '0');
prodXY_uid342_pT2_uid261_natLogPolyEval_b <= (others => '0');
prodXY_uid342_pT2_uid261_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid342_pT2_uid261_natLogPolyEval_a <= reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_q;
prodXY_uid342_pT2_uid261_natLogPolyEval_b <= reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1_q;
prodXY_uid342_pT2_uid261_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid342_pT2_uid261_natLogPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid342_pT2_uid261_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid342_pT2_uid261_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid342_pT2_uid261_natLogPolyEval_q <= prodXY_uid342_pT2_uid261_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval(BITSELECT,342)@19
prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_in <= prodXY_uid342_pT2_uid261_natLogPolyEval_q;
prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_b <= prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_in(38 downto 15);
--highBBits_uid263_natLogPolyEval(BITSELECT,262)@19
highBBits_uid263_natLogPolyEval_in <= prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_b;
highBBits_uid263_natLogPolyEval_b <= highBBits_uid263_natLogPolyEval_in(23 downto 2);
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor(LOGICAL,1035)
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_b <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_q <= not (ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_a or ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_b);
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena(REG,1036)
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd(LOGICAL,1037)
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_a <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_q <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_a and ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_b;
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_inputreg(DELAY,1025)
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q, xout => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem(DUALMEM,1026)
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ia <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_inputreg_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ia
);
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_q <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid251_natLogTabGen_lutmem(DUALMEM,344)@16
memoryC0_uid251_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid251_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid251_natLogTabGen_lutmem_ab <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_q;
memoryC0_uid251_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 9,
numwords_a => 512,
width_b => 31,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1px_s5_memoryC0_uid251_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid251_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid251_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid251_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid251_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid251_natLogTabGen_lutmem_ia
);
memoryC0_uid251_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid251_natLogTabGen_lutmem_q <= memoryC0_uid251_natLogTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0(REG,382)@18
reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0_q <= memoryC0_uid251_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid264_natLogPolyEval(ADD,263)@19
sumAHighB_uid264_natLogPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0_q(30)) & reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0_q);
sumAHighB_uid264_natLogPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid263_natLogPolyEval_b(21)) & highBBits_uid263_natLogPolyEval_b);
sumAHighB_uid264_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid264_natLogPolyEval_a) + SIGNED(sumAHighB_uid264_natLogPolyEval_b));
sumAHighB_uid264_natLogPolyEval_q <= sumAHighB_uid264_natLogPolyEval_o(31 downto 0);
--lowRangeB_uid262_natLogPolyEval(BITSELECT,261)@19
lowRangeB_uid262_natLogPolyEval_in <= prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_b(1 downto 0);
lowRangeB_uid262_natLogPolyEval_b <= lowRangeB_uid262_natLogPolyEval_in(1 downto 0);
--s2_uid262_uid265_natLogPolyEval(BITJOIN,264)@19
s2_uid262_uid265_natLogPolyEval_q <= sumAHighB_uid264_natLogPolyEval_q & lowRangeB_uid262_natLogPolyEval_b;
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@19
peOR_uid93_fpLogE1pxTest_in <= s2_uid262_uid265_natLogPolyEval_q(32 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(32 downto 6);
--reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1(REG,383)@19
reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1_q <= peOR_uid93_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor(LOGICAL,912)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_b <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_q <= not (ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_a or ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_b);
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_mem_top(CONSTANT,908)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_mem_top_q <= "01000";
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp(LOGICAL,909)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_a <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_mem_top_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q);
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_q <= "1" when ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_a = ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_b else "0";
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg(REG,910)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena(REG,913)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_q = "1") THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd(LOGICAL,914)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_a <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_b <= en;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_a and ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_b;
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,899)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,900)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,901)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,890)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 5,
width_b => 23,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(22 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@8
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@8
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(23 downto 1);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@8
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & fracBRed_uid99_fpLogE1pxTest_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a(DELAY,499)@0
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 7 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@7
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_q;
branch3OrC_uid94_fpLogE1pxTest_b <= c_uid87_fpLogE1pxTest_q;
branch3OrC_uid94_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branch3OrC_uid94_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
branch3OrC_uid94_fpLogE1pxTest_q <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--sEz_uid102_fpLogE1pxTest(MUX,101)@8
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sEz_uid102_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_inputreg(DELAY,902)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => sEz_uid102_fpLogE1pxTest_q, xout => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt(COUNTER,904)
-- every=1, low=0, high=8, step=1, init=1
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i = 7 THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i - 8;
ELSE
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i,4));
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg(REG,905)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux(MUX,906)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_s, ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q, ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem(DUALMEM,903)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ia <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_inputreg_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_aa <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ab <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 25,
widthad_a => 4,
numwords_a => 9,
width_b => 25,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ia
);
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_iq(24 downto 0);
--postPEMul_uid103_fpLogE1pxTest(MULT,102)@20
postPEMul_uid103_fpLogE1pxTest_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_q;
postPEMul_uid103_fpLogE1pxTest_b <= reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1_q;
postPEMul_uid103_fpLogE1pxTest_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_q <= postPEMul_uid103_fpLogE1pxTest_s1;
END IF;
END IF;
END PROCESS;
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@23
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_q;
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(51 downto 22);
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "00000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,885)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,881)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "01001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,882)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,883)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,886)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,887)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@6
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0000" & r_uid213_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(8 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@6
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(7 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(7 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,387)@6
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1(REG,385)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,384)@0
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= expX_uid6_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_a(DELAY,449)@1
ld_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q, xout => ld_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_a_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(8 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d(DELAY,480)@4
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor(LOGICAL,846)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_b <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_q <= not (ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_a or ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_b);
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena(REG,847)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd(LOGICAL,848)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_a and ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_b;
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_inputreg(DELAY,836)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q, xout => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem(DUALMEM,837)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_inputreg_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_aa <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ab <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 2,
numwords_a => 4,
width_b => 8,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_iq(7 downto 0);
--expB_uid79_fpLogE1pxTest(MUX,78)@7
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,875)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,877)
-- every=1, low=0, high=9, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 8 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 9;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,4));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,878)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,879)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,876)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 4,
numwords_a => 10,
width_b => 9,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(8 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@20
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(9 downto 0);
--xv0_uid244_constMult(BITSELECT,243)@20
xv0_uid244_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid244_constMult_b <= xv0_uid244_constMult_in(5 downto 0);
--reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0(REG,389)@20
reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q <= xv0_uid244_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a(DELAY,669)@21
ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q, xout => ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid247_constMult(LOOKUP,246)@22
p0_uid247_constMult: PROCESS (ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a_q) IS
WHEN "000000" => p0_uid247_constMult_q <= "0000000000000000000000000000000000";
WHEN "000001" => p0_uid247_constMult_q <= "0000001011000101110010000110000000";
WHEN "000010" => p0_uid247_constMult_q <= "0000010110001011100100001100000000";
WHEN "000011" => p0_uid247_constMult_q <= "0000100001010001010110010010000000";
WHEN "000100" => p0_uid247_constMult_q <= "0000101100010111001000011000000000";
WHEN "000101" => p0_uid247_constMult_q <= "0000110111011100111010011110000000";
WHEN "000110" => p0_uid247_constMult_q <= "0001000010100010101100100100000000";
WHEN "000111" => p0_uid247_constMult_q <= "0001001101101000011110101010000000";
WHEN "001000" => p0_uid247_constMult_q <= "0001011000101110010000110000000000";
WHEN "001001" => p0_uid247_constMult_q <= "0001100011110100000010110110000000";
WHEN "001010" => p0_uid247_constMult_q <= "0001101110111001110100111100000000";
WHEN "001011" => p0_uid247_constMult_q <= "0001111001111111100111000010000000";
WHEN "001100" => p0_uid247_constMult_q <= "0010000101000101011001001000000000";
WHEN "001101" => p0_uid247_constMult_q <= "0010010000001011001011001110000000";
WHEN "001110" => p0_uid247_constMult_q <= "0010011011010000111101010100000000";
WHEN "001111" => p0_uid247_constMult_q <= "0010100110010110101111011010000000";
WHEN "010000" => p0_uid247_constMult_q <= "0010110001011100100001100000000000";
WHEN "010001" => p0_uid247_constMult_q <= "0010111100100010010011100110000000";
WHEN "010010" => p0_uid247_constMult_q <= "0011000111101000000101101100000000";
WHEN "010011" => p0_uid247_constMult_q <= "0011010010101101110111110010000000";
WHEN "010100" => p0_uid247_constMult_q <= "0011011101110011101001111000000000";
WHEN "010101" => p0_uid247_constMult_q <= "0011101000111001011011111110000000";
WHEN "010110" => p0_uid247_constMult_q <= "0011110011111111001110000100000000";
WHEN "010111" => p0_uid247_constMult_q <= "0011111111000101000000001010000000";
WHEN "011000" => p0_uid247_constMult_q <= "0100001010001010110010010000000000";
WHEN "011001" => p0_uid247_constMult_q <= "0100010101010000100100010110000000";
WHEN "011010" => p0_uid247_constMult_q <= "0100100000010110010110011100000000";
WHEN "011011" => p0_uid247_constMult_q <= "0100101011011100001000100010000000";
WHEN "011100" => p0_uid247_constMult_q <= "0100110110100001111010101000000000";
WHEN "011101" => p0_uid247_constMult_q <= "0101000001100111101100101110000000";
WHEN "011110" => p0_uid247_constMult_q <= "0101001100101101011110110100000000";
WHEN "011111" => p0_uid247_constMult_q <= "0101010111110011010000111010000000";
WHEN "100000" => p0_uid247_constMult_q <= "0101100010111001000011000000000000";
WHEN "100001" => p0_uid247_constMult_q <= "0101101101111110110101000110000000";
WHEN "100010" => p0_uid247_constMult_q <= "0101111001000100100111001100000000";
WHEN "100011" => p0_uid247_constMult_q <= "0110000100001010011001010010000000";
WHEN "100100" => p0_uid247_constMult_q <= "0110001111010000001011011000000000";
WHEN "100101" => p0_uid247_constMult_q <= "0110011010010101111101011110000000";
WHEN "100110" => p0_uid247_constMult_q <= "0110100101011011101111100100000000";
WHEN "100111" => p0_uid247_constMult_q <= "0110110000100001100001101010000000";
WHEN "101000" => p0_uid247_constMult_q <= "0110111011100111010011110000000000";
WHEN "101001" => p0_uid247_constMult_q <= "0111000110101101000101110110000000";
WHEN "101010" => p0_uid247_constMult_q <= "0111010001110010110111111100000000";
WHEN "101011" => p0_uid247_constMult_q <= "0111011100111000101010000010000000";
WHEN "101100" => p0_uid247_constMult_q <= "0111100111111110011100001000000000";
WHEN "101101" => p0_uid247_constMult_q <= "0111110011000100001110001110000000";
WHEN "101110" => p0_uid247_constMult_q <= "0111111110001010000000010100000000";
WHEN "101111" => p0_uid247_constMult_q <= "1000001001001111110010011010000000";
WHEN "110000" => p0_uid247_constMult_q <= "1000010100010101100100100000000000";
WHEN "110001" => p0_uid247_constMult_q <= "1000011111011011010110100110000000";
WHEN "110010" => p0_uid247_constMult_q <= "1000101010100001001000101100000000";
WHEN "110011" => p0_uid247_constMult_q <= "1000110101100110111010110010000000";
WHEN "110100" => p0_uid247_constMult_q <= "1001000000101100101100111000000000";
WHEN "110101" => p0_uid247_constMult_q <= "1001001011110010011110111110000000";
WHEN "110110" => p0_uid247_constMult_q <= "1001010110111000010001000100000000";
WHEN "110111" => p0_uid247_constMult_q <= "1001100001111110000011001010000000";
WHEN "111000" => p0_uid247_constMult_q <= "1001101101000011110101010000000000";
WHEN "111001" => p0_uid247_constMult_q <= "1001111000001001100111010110000000";
WHEN "111010" => p0_uid247_constMult_q <= "1010000011001111011001011100000000";
WHEN "111011" => p0_uid247_constMult_q <= "1010001110010101001011100010000000";
WHEN "111100" => p0_uid247_constMult_q <= "1010011001011010111101101000000000";
WHEN "111101" => p0_uid247_constMult_q <= "1010100100100000101111101110000000";
WHEN "111110" => p0_uid247_constMult_q <= "1010101111100110100001110100000000";
WHEN "111111" => p0_uid247_constMult_q <= "1010111010101100010011111010000000";
WHEN OTHERS =>
p0_uid247_constMult_q <= "0000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid245_constMult(BITSELECT,244)@20
xv1_uid245_constMult_in <= e_uid84_fpLogE1pxTest_q(8 downto 0);
xv1_uid245_constMult_b <= xv1_uid245_constMult_in(8 downto 6);
--reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0(REG,388)@20
reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0_q <= xv1_uid245_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid246_constMult(LOOKUP,245)@21
p1_uid246_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid246_constMult_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0_q) IS
WHEN "000" => p1_uid246_constMult_q <= "0000000000000000000000000000000000000";
WHEN "001" => p1_uid246_constMult_q <= "0001011000101110010000110000000000000";
WHEN "010" => p1_uid246_constMult_q <= "0010110001011100100001100000000000000";
WHEN "011" => p1_uid246_constMult_q <= "0100001010001010110010010000000000000";
WHEN "100" => p1_uid246_constMult_q <= "1010011101000110111101000000000000000";
WHEN "101" => p1_uid246_constMult_q <= "1011110101110101001101110000000000000";
WHEN "110" => p1_uid246_constMult_q <= "1101001110100011011110100000000000000";
WHEN "111" => p1_uid246_constMult_q <= "1110100111010001101111010000000000000";
WHEN OTHERS =>
p1_uid246_constMult_q <= "0000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid248_constMult(ADD,247)@22
lev1_a0_uid248_constMult_a <= STD_LOGIC_VECTOR((38 downto 37 => p1_uid246_constMult_q(36)) & p1_uid246_constMult_q);
lev1_a0_uid248_constMult_b <= STD_LOGIC_VECTOR('0' & "0000" & p0_uid247_constMult_q);
lev1_a0_uid248_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid248_constMult_a) + SIGNED(lev1_a0_uid248_constMult_b));
lev1_a0_uid248_constMult_q <= lev1_a0_uid248_constMult_o(37 downto 0);
--sR_uid249_constMult(BITSELECT,248)@22
sR_uid249_constMult_in <= lev1_a0_uid248_constMult_q(36 downto 0);
sR_uid249_constMult_b <= sR_uid249_constMult_in(36 downto 2);
--reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,390)@22
reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid249_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,509)@8
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@23
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (addTermOne_uid105_fpLogE1pxTest_s, en, reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q, wideZero_uid104_fpLogE1pxTest_q)
BEGIN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@23
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((35 downto 35 => addTermOne_uid105_fpLogE1pxTest_q(34)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((35 downto 30 => highBBits_uid107_fpLogE1pxTest_b(29)) & highBBits_uid107_fpLogE1pxTest_b);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(35 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@23
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_q(21 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(21 downto 0);
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@23
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & lowRangeB_uid106_fpLogE1pxTest_b;
--FullSumAB57_uid110_fpLogE1pxTest(BITSELECT,109)@23
FullSumAB57_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB57_uid110_fpLogE1pxTest_b <= FullSumAB57_uid110_fpLogE1pxTest_in(57 downto 57);
--ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,521)@23
ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB57_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@23
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((57 downto 1 => FullSumAB57_uid110_fpLogE1pxTest_b(0)) & FullSumAB57_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
finalSumOneComp_uid112_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
finalSumOneComp_uid112_fpLogE1pxTest_q <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@24
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((58 downto 58 => finalSumOneComp_uid112_fpLogE1pxTest_q(57)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((58 downto 1 => ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(58 downto 0);
--rVStage_uid268_countZ_uid114_fpLogE1pxTest(BITSELECT,267)@24
rVStage_uid268_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid268_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid268_countZ_uid114_fpLogE1pxTest_in(58 downto 27);
--reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1(REG,391)@24
reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid268_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid269_countZ_uid114_fpLogE1pxTest(LOGICAL,268)@25
vCount_uid269_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid269_countZ_uid114_fpLogE1pxTest_b <= zs_uid267_countZ_uid114_fpLogE1pxTest_q;
vCount_uid269_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid269_countZ_uid114_fpLogE1pxTest_a = vCount_uid269_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5(REG,401)@25
reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q <= vCount_uid269_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_f(DELAY,724)@26
ld_reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid271_countZ_uid114_fpLogE1pxTest(BITSELECT,270)@24
vStage_uid271_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(26 downto 0);
vStage_uid271_countZ_uid114_fpLogE1pxTest_b <= vStage_uid271_countZ_uid114_fpLogE1pxTest_in(26 downto 0);
--ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b(DELAY,689)@24
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => vStage_uid271_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid270_countZ_uid114_fpLogE1pxTest(CONSTANT,269)
mO_uid270_countZ_uid114_fpLogE1pxTest_q <= "11111";
--cStage_uid272_countZ_uid114_fpLogE1pxTest(BITJOIN,271)@25
cStage_uid272_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b_q & mO_uid270_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c(DELAY,691)@24
ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid268_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid274_countZ_uid114_fpLogE1pxTest(MUX,273)@25
vStagei_uid274_countZ_uid114_fpLogE1pxTest_s <= vCount_uid269_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid274_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid274_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid272_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid274_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid274_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid274_countZ_uid114_fpLogE1pxTest_q <= cStage_uid272_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid274_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid276_countZ_uid114_fpLogE1pxTest(BITSELECT,275)@25
rVStage_uid276_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid274_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid276_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid276_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1(REG,392)@25
reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid276_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid277_countZ_uid114_fpLogE1pxTest(LOGICAL,276)@26
vCount_uid277_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid277_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid277_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid277_countZ_uid114_fpLogE1pxTest_a = vCount_uid277_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid277_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_a(DELAY,822)@26
ld_vCount_uid277_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid277_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid277_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4(REG,400)@27
reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid277_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid278_countZ_uid114_fpLogE1pxTest(BITSELECT,277)@25
vStage_uid278_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid274_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid278_countZ_uid114_fpLogE1pxTest_b <= vStage_uid278_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3(REG,394)@25
reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid278_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid280_countZ_uid114_fpLogE1pxTest(MUX,279)@26
vStagei_uid280_countZ_uid114_fpLogE1pxTest_s <= vCount_uid277_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid280_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid280_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid280_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid280_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid280_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid280_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid282_countZ_uid114_fpLogE1pxTest(BITSELECT,281)@26
rVStage_uid282_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid280_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid282_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid282_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid283_countZ_uid114_fpLogE1pxTest(LOGICAL,282)@26
vCount_uid283_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid282_countZ_uid114_fpLogE1pxTest_b;
vCount_uid283_countZ_uid114_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
vCount_uid283_countZ_uid114_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid283_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid283_countZ_uid114_fpLogE1pxTest_a = vCount_uid283_countZ_uid114_fpLogE1pxTest_b) THEN
vCount_uid283_countZ_uid114_fpLogE1pxTest_q <= "1";
ELSE
vCount_uid283_countZ_uid114_fpLogE1pxTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid283_countZ_uid114_fpLogE1pxTest_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_d(DELAY,722)@27
ld_vCount_uid283_countZ_uid114_fpLogE1pxTest_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid283_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid283_countZ_uid114_fpLogE1pxTest_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid284_countZ_uid114_fpLogE1pxTest(BITSELECT,283)@26
vStage_uid284_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid280_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid284_countZ_uid114_fpLogE1pxTest_b <= vStage_uid284_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3(REG,396)@26
reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid284_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2(REG,395)@26
reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid282_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid286_countZ_uid114_fpLogE1pxTest(MUX,285)@27
vStagei_uid286_countZ_uid114_fpLogE1pxTest_s <= vCount_uid283_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid286_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid286_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid286_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid286_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid286_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid286_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid288_countZ_uid114_fpLogE1pxTest(BITSELECT,287)@27
rVStage_uid288_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid286_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid288_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid288_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid289_countZ_uid114_fpLogE1pxTest(LOGICAL,288)@27
vCount_uid289_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid288_countZ_uid114_fpLogE1pxTest_b;
vCount_uid289_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid289_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid289_countZ_uid114_fpLogE1pxTest_a = vCount_uid289_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2(REG,399)@27
reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid289_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid290_countZ_uid114_fpLogE1pxTest(BITSELECT,289)@27
vStage_uid290_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid286_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid290_countZ_uid114_fpLogE1pxTest_b <= vStage_uid290_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid292_countZ_uid114_fpLogE1pxTest(MUX,291)@27
vStagei_uid292_countZ_uid114_fpLogE1pxTest_s <= vCount_uid289_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid292_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid292_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid288_countZ_uid114_fpLogE1pxTest_b, vStage_uid290_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid292_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid292_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid288_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid292_countZ_uid114_fpLogE1pxTest_q <= vStage_uid290_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid292_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid294_countZ_uid114_fpLogE1pxTest(BITSELECT,293)@27
rVStage_uid294_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid292_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid294_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid294_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid295_countZ_uid114_fpLogE1pxTest(LOGICAL,294)@27
vCount_uid295_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid294_countZ_uid114_fpLogE1pxTest_b;
vCount_uid295_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid295_countZ_uid114_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid295_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid295_countZ_uid114_fpLogE1pxTest_a = vCount_uid295_countZ_uid114_fpLogE1pxTest_b) THEN
vCount_uid295_countZ_uid114_fpLogE1pxTest_q <= "1";
ELSE
vCount_uid295_countZ_uid114_fpLogE1pxTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid296_countZ_uid114_fpLogE1pxTest(BITSELECT,295)@27
vStage_uid296_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid292_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid296_countZ_uid114_fpLogE1pxTest_b <= vStage_uid296_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3(REG,398)@27
reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid296_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2(REG,397)@27
reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid294_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid298_countZ_uid114_fpLogE1pxTest(MUX,297)@28
vStagei_uid298_countZ_uid114_fpLogE1pxTest_s <= vCount_uid295_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid298_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid298_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid298_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid298_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid298_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid298_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid300_countZ_uid114_fpLogE1pxTest(BITSELECT,299)@28
rVStage_uid300_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid298_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid300_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid300_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid301_countZ_uid114_fpLogE1pxTest(LOGICAL,300)@28
vCount_uid301_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid300_countZ_uid114_fpLogE1pxTest_b;
vCount_uid301_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid301_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid301_countZ_uid114_fpLogE1pxTest_a = vCount_uid301_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid302_countZ_uid114_fpLogE1pxTest(BITJOIN,301)@28
r_uid302_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_f_q & reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid283_countZ_uid114_fpLogE1pxTest_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid295_countZ_uid114_fpLogE1pxTest_q & vCount_uid301_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010001001";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@28
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0000" & r_uid302_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(9 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,411)@28
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@29
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((10 downto 10 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(9)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((10 downto 6 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(5)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(10 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@29
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(9 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(9 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,529)@28
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_inputreg(DELAY,928)
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,528)@8
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_inputreg_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@29
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1011)
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1012)
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1013)
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X10dto0_uid312_normVal_uid115_fpLogE1pxTest(BITSELECT,311)@24
X10dto0_uid312_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(10 downto 0);
X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b <= X10dto0_uid312_normVal_uid115_fpLogE1pxTest_in(10 downto 0);
--ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1003)
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b, xout => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1004)
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 1,
numwords_a => 2,
width_b => 11,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(10 downto 0);
--leftShiftStage0Idx3Pad48_uid311_normVal_uid115_fpLogE1pxTest(CONSTANT,310)
leftShiftStage0Idx3Pad48_uid311_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest(BITJOIN,312)@28
leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_q <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid311_normVal_uid115_fpLogE1pxTest_q;
--ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1000)
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1001)
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1002)
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,993)
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(26 downto 0);
--leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest(BITJOIN,309)@28
leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid267_countZ_uid114_fpLogE1pxTest_q;
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,989)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,990)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,991)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X42dto0_uid306_normVal_uid115_fpLogE1pxTest(BITSELECT,305)@24
X42dto0_uid306_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(42 downto 0);
X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b <= X42dto0_uid306_normVal_uid115_fpLogE1pxTest_in(42 downto 0);
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,981)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b, xout => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,982)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 1,
numwords_a => 2,
width_b => 43,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(42 downto 0);
--leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest(BITJOIN,306)@28
leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1022)
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1023)
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1024)
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1014)
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => finalSumAbs_uid113_fpLogE1pxTest_q, xout => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1015)
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 59,
widthad_a => 1,
numwords_a => 2,
width_b => 59,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(58 downto 0);
--leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest(BITSELECT,313)@28
leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_in <= r_uid302_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest(MUX,314)@28
leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_s, en, ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_q, leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_q, leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest(BITSELECT,322)@28
LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q(46 downto 0);
LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_in(46 downto 0);
--leftShiftStage1Idx3Pad12_uid322_normVal_uid115_fpLogE1pxTest(CONSTANT,321)
leftShiftStage1Idx3Pad12_uid322_normVal_uid115_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest(BITJOIN,323)@28
leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad12_uid322_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5(REG,406)@28
reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest(BITSELECT,319)@28
LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q(50 downto 0);
LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_in(50 downto 0);
--leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest(BITJOIN,320)@28
leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_b & cstAllZWE_uid17_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4(REG,405)@28
reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest(BITSELECT,316)@28
LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q(54 downto 0);
LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_in(54 downto 0);
--leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest(BITJOIN,317)@28
leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3(REG,404)@28
reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2(REG,403)@28
reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest(BITSELECT,324)@28
leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_in <= r_uid302_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1(REG,402)@28
reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest(MUX,325)@29
leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest(BITSELECT,333)@29
LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q(55 downto 0);
LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_in(55 downto 0);
--ld_LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_b(DELAY,753)@29
ld_LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid333_normVal_uid115_fpLogE1pxTest(CONSTANT,332)
leftShiftStage2Idx3Pad3_uid333_normVal_uid115_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest(BITJOIN,334)@30
leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad3_uid333_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest(BITSELECT,330)@29
LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q(56 downto 0);
LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_in(56 downto 0);
--ld_LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_b(DELAY,751)@29
ld_LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest(BITJOIN,331)@30
leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest(BITSELECT,327)@29
LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q(57 downto 0);
LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_in(57 downto 0);
--ld_LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_b(DELAY,749)@29
ld_LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest(BITJOIN,328)@30
leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2(REG,408)@29
reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest(BITSELECT,335)@28
leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_in <= r_uid302_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b_to_reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_a(DELAY,829)@28
ld_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b_to_reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b_to_reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1(REG,407)@29
reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_q <= ld_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b_to_reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest(MUX,336)@30
leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@30
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q(57 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(57 downto 34);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@30
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,412)@30
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@31
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(34 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@31
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(31 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(31 downto 24);
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,939)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,940)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,941)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,929)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => resIsX_uid62_fpLogE1pxTest_c, xout => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,930)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@31
expR_uid128_fpLogE1pxTest_s <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expR_uid128_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= expR_uid127_fpLogE1pxTest_b;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor(LOGICAL,1048)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_mem_top(CONSTANT,1044)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_mem_top_q <= "011010";
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp(LOGICAL,1045)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg(REG,1046)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena(REG,1049)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd(LOGICAL,1050)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,548)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,549)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@1
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@1
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_inputreg(DELAY,1038)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt(COUNTER,1040)
-- every=1, low=0, high=26, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i = 25 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i - 26;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i,5));
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg(REG,1041)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux(MUX,1042)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem(DUALMEM,1039)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 27,
width_b => 3,
widthad_b => 5,
numwords_b => 27,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_iq(2 downto 0);
--reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0(REG,347)@30
reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@31
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@32
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "00000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,952)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,953)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,954)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,943)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 28,
width_b => 23,
widthad_b => 5,
numwords_b => 28,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(22 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@31
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(23 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(23 downto 1);
--fracR_uid126_fpLogE1pxTest(MUX,125)@31
fracR_uid126_fpLogE1pxTest_s <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracR_uid126_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= fracR0_uid125_fpLogE1pxTest_b;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@32
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@32
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@32
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/hcc_lsftpipe32_sv.vhd | 20 | 4030 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_clz23.vhd | 10 | 4166 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ23.VHD ***
--*** ***
--*** Function: 23 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz23 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_clz23;
ARCHITECTURE zzz of fp_clz23 IS
type positiontype IS ARRAY (4 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos51
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19) OR mantissa(18);
zerogroup(2) <= mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13) OR mantissa(12);
zerogroup(3) <= mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7) OR mantissa(6);
zerogroup(4) <= mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
pone: fp_pos51
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(23 DOWNTO 18),position=>position(1)(5 DOWNTO 1));
ptwo: fp_pos51
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(17 DOWNTO 12),position=>position(2)(5 DOWNTO 1));
pthr: fp_pos51
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(11 DOWNTO 6),position=>position(3)(5 DOWNTO 1));
pfiv: fp_pos51
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mannode,position=>position(4)(5 DOWNTO 1));
mannode <= mantissa(5 DOWNTO 1) & '0';
gma: FOR k IN 1 TO 5 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 4 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(4)(5 DOWNTO 1);
END zzz;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/hcc_usgnpos_sv.vhd | 20 | 6063 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_USGNPOS.VHD ***
--*** ***
--*** Function: Leading 0/1s for a small ***
--*** unsigned number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_usgnpos;
ARCHITECTURE rtl of hcc_usgnpos IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,6);
WHEN "000001" => position <= conv_std_logic_vector(start+5,6);
WHEN "000010" => position <= conv_std_logic_vector(start+4,6);
WHEN "000011" => position <= conv_std_logic_vector(start+4,6);
WHEN "000100" => position <= conv_std_logic_vector(start+3,6);
WHEN "000101" => position <= conv_std_logic_vector(start+3,6);
WHEN "000110" => position <= conv_std_logic_vector(start+3,6);
WHEN "000111" => position <= conv_std_logic_vector(start+3,6);
WHEN "001000" => position <= conv_std_logic_vector(start+2,6);
WHEN "001001" => position <= conv_std_logic_vector(start+2,6);
WHEN "001010" => position <= conv_std_logic_vector(start+2,6);
WHEN "001011" => position <= conv_std_logic_vector(start+2,6);
WHEN "001100" => position <= conv_std_logic_vector(start+2,6);
WHEN "001101" => position <= conv_std_logic_vector(start+2,6);
WHEN "001110" => position <= conv_std_logic_vector(start+2,6);
WHEN "001111" => position <= conv_std_logic_vector(start+2,6);
WHEN "010000" => position <= conv_std_logic_vector(start+1,6);
WHEN "010001" => position <= conv_std_logic_vector(start+1,6);
WHEN "010010" => position <= conv_std_logic_vector(start+1,6);
WHEN "010011" => position <= conv_std_logic_vector(start+1,6);
WHEN "010100" => position <= conv_std_logic_vector(start+1,6);
WHEN "010101" => position <= conv_std_logic_vector(start+1,6);
WHEN "010110" => position <= conv_std_logic_vector(start+1,6);
WHEN "010111" => position <= conv_std_logic_vector(start+1,6);
WHEN "011000" => position <= conv_std_logic_vector(start+1,6);
WHEN "011001" => position <= conv_std_logic_vector(start+1,6);
WHEN "011010" => position <= conv_std_logic_vector(start+1,6);
WHEN "011011" => position <= conv_std_logic_vector(start+1,6);
WHEN "011100" => position <= conv_std_logic_vector(start+1,6);
WHEN "011101" => position <= conv_std_logic_vector(start+1,6);
WHEN "011110" => position <= conv_std_logic_vector(start+1,6);
WHEN "011111" => position <= conv_std_logic_vector(start+1,6);
WHEN "100000" => position <= conv_std_logic_vector(start,6);
WHEN "100001" => position <= conv_std_logic_vector(start,6);
WHEN "100010" => position <= conv_std_logic_vector(start,6);
WHEN "100011" => position <= conv_std_logic_vector(start,6);
WHEN "100100" => position <= conv_std_logic_vector(start,6);
WHEN "100101" => position <= conv_std_logic_vector(start,6);
WHEN "100110" => position <= conv_std_logic_vector(start,6);
WHEN "100111" => position <= conv_std_logic_vector(start,6);
WHEN "101000" => position <= conv_std_logic_vector(start,6);
WHEN "101001" => position <= conv_std_logic_vector(start,6);
WHEN "101010" => position <= conv_std_logic_vector(start,6);
WHEN "101011" => position <= conv_std_logic_vector(start,6);
WHEN "101100" => position <= conv_std_logic_vector(start,6);
WHEN "101101" => position <= conv_std_logic_vector(start,6);
WHEN "101110" => position <= conv_std_logic_vector(start,6);
WHEN "101111" => position <= conv_std_logic_vector(start,6);
WHEN "110000" => position <= conv_std_logic_vector(start,6);
WHEN "110001" => position <= conv_std_logic_vector(start,6);
WHEN "110010" => position <= conv_std_logic_vector(start,6);
WHEN "110011" => position <= conv_std_logic_vector(start,6);
WHEN "110100" => position <= conv_std_logic_vector(start,6);
WHEN "110101" => position <= conv_std_logic_vector(start,6);
WHEN "110110" => position <= conv_std_logic_vector(start,6);
WHEN "110111" => position <= conv_std_logic_vector(start,6);
WHEN "111000" => position <= conv_std_logic_vector(start,6);
WHEN "111001" => position <= conv_std_logic_vector(start,6);
WHEN "111010" => position <= conv_std_logic_vector(start,6);
WHEN "111011" => position <= conv_std_logic_vector(start,6);
WHEN "111100" => position <= conv_std_logic_vector(start,6);
WHEN "111101" => position <= conv_std_logic_vector(start,6);
WHEN "111110" => position <= conv_std_logic_vector(start,6);
WHEN "111111" => position <= conv_std_logic_vector(start,6);
WHEN others => position <= conv_std_logic_vector(0,6);
END CASE;
END PROCESS;
END rtl;
| mit |
18545/FPGA | FPGA.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 1 | 14434 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=4,C_READ_WIDTH_A=4,C_WRITE_DEPTH_A=307200,C_READ_DEPTH_A=307200,C_ADDRA_WIDTH=19,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=4,C_READ_WIDTH_B=4,C_WRITE_DEPTH_B=307200,C_READ_DEPTH_B=307200,C_ADDRB_WIDTH=19,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=36,C_COUNT_18K_BRAM=3,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.198881 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 4,
C_READ_WIDTH_A => 4,
C_WRITE_DEPTH_A => 307200,
C_READ_DEPTH_A => 307200,
C_ADDRA_WIDTH => 19,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 4,
C_READ_WIDTH_B => 4,
C_WRITE_DEPTH_B => 307200,
C_READ_DEPTH_B => 307200,
C_ADDRB_WIDTH => 19,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "36",
C_COUNT_18K_BRAM => "3",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 16.198881 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| mit |
richjyoung/lfsr-package | test/JUNIT_TB/junit_pkg_body.vhd | 1 | 7030 | library IEEE, STD;
use IEEE.std_logic_1164.all;
use STD.textio.all;
--------------------------------------------------------------------------------
package body junit is
----------------------------------------------------------------------------
-- Procedure: JUnit XML Declaration
----------------------------------------------------------------------------
procedure junit_xml_declaration (
variable JUNIT_FILE : in text
) is
variable L : line;
begin
write(L, string'("<?xml version=""1.0"" encoding=""UTF-8"" ?>"));
writeline(JUNIT_FILE, L);
end procedure junit_xml_declaration;
----------------------------------------------------------------------------
-- Procedure: JUnit Start Testsuites
----------------------------------------------------------------------------
procedure junit_start_testsuites (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
TESTS : in natural;
FAILURES : in natural;
RUNTIME : in time
) is
variable L : line;
begin
write(L, string'("<testsuites id="""));
write(L, ID);
write(L, string'(""" name="""));
write(L, NAME);
write(L, string'(""" tests="""));
write(L, TESTS);
write(L, string'(""" failures="""));
write(L, FAILURES);
write(L, string'(""" time="""));
write(L, junit_time(RUNTIME), right, 0, 9);
write(L, string'(""">"));
writeline(JUNIT_FILE, L);
end procedure junit_start_testsuites;
----------------------------------------------------------------------------
-- Procedure: JUnit End Testsuites
----------------------------------------------------------------------------
procedure junit_end_testsuites (variable JUNIT_FILE : in text) is
variable L : line;
begin
write(L, string'("</testsuites>"));
writeline(JUNIT_FILE, L);
end procedure junit_end_testsuites;
----------------------------------------------------------------------------
-- Procedure: JUnit Start Testsuite
----------------------------------------------------------------------------
procedure junit_start_testsuite (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
TESTS : in natural;
FAILURES : in natural;
RUNTIME : in time
) is
variable L : line;
begin
write(L, string'("<testsuite id="""));
write(L, ID);
write(L, string'(""" name="""));
write(L, NAME);
write(L, string'(""" tests="""));
write(L, TESTS);
write(L, string'(""" failures="""));
write(L, FAILURES);
write(L, string'(""" time="""));
write(L, junit_time(RUNTIME), right, 0, 9);
write(L, string'(""">"));
writeline(JUNIT_FILE, L);
end procedure junit_start_testsuite;
----------------------------------------------------------------------------
-- Procedure: JUnit End Testsuite
----------------------------------------------------------------------------
procedure junit_end_testsuite (variable JUNIT_FILE : in text) is
variable L : line;
begin
write(L, string'("</testsuite>"));
writeline(JUNIT_FILE, L);
end procedure junit_end_testsuite;
----------------------------------------------------------------------------
-- Procedure: JUnit Start Testcase
----------------------------------------------------------------------------
procedure junit_start_testcase (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
RUNTIME : in time
) is
variable L : line;
begin
write(L, string'("<testcase id="""));
write(L, ID);
write(L, string'(""" name="""));
write(L, NAME);
write(L, string'(""" time="""));
write(L, junit_time(RUNTIME), right, 0, 9);
write(L, string'(""">"));
writeline(JUNIT_FILE, L);
end procedure junit_start_testcase;
----------------------------------------------------------------------------
-- Procedure: JUnit Testcase
----------------------------------------------------------------------------
procedure junit_testcase (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
RUNTIME : in time
) is
variable L : line;
begin
junit_start_testcase(JUNIT_FILE, ID, NAME, RUNTIME);
junit_end_testcase(JUNIT_FILE);
end procedure junit_testcase;
----------------------------------------------------------------------------
-- Procedure: JUnit End Testcase
----------------------------------------------------------------------------
procedure junit_end_testcase (variable JUNIT_FILE : in text) is
variable L : line;
begin
write(L, string'("</testcase>"));
writeline(JUNIT_FILE, L);
end procedure junit_end_testcase;
----------------------------------------------------------------------------
-- Procedure: JUnit Failure
----------------------------------------------------------------------------
procedure junit_failure (
variable JUNIT_FILE : in text;
MESSAGE : in string;
DETAIL : in string
) is
variable L : line;
begin
write(L, string'("<failure message="""));
write(L, MESSAGE);
write(L, string'(""">"));
write(L, DETAIL);
write(L, string'("</failure>"));
writeline(JUNIT_FILE, L);
end procedure junit_failure;
----------------------------------------------------------------------------
-- Procedure: JUnit Error
----------------------------------------------------------------------------
procedure junit_error (
variable JUNIT_FILE : in text;
MESSAGE : in string;
DETAIL : in string
) is
variable L : line;
begin
write(L, string'("<error message="""));
write(L, MESSAGE);
write(L, string'(""">"));
write(L, DETAIL);
write(L, string'("</failure>"));
writeline(JUNIT_FILE, L);
end procedure junit_error;
----------------------------------------------------------------------------
-- Procedure: JUnit Skipped
----------------------------------------------------------------------------
procedure junit_skipped (
variable JUNIT_FILE : in text
) is
variable L : line;
begin
write(L, string'("<skipped />"));
writeline(JUNIT_FILE, L);
end procedure junit_skipped;
----------------------------------------------------------------------------
-- Function: JUnit Time
----------------------------------------------------------------------------
function junit_time (
RUNTIME : in time
) return real is
begin
return real(RUNTIME/(1 fs)) / 1.0e15;
end function;
end junit; | mit |
richjyoung/lfsr-package | test/LFSR_TB/pulse_tb.vhd | 1 | 3155 | library IEEE, JUNIT_TB, LFSR, STD;
use IEEE.std_logic_1164.all;
use JUNIT_TB.junit.all;
use LFSR.lfsr_components.all;
use STD.textio.all;
--------------------------------------------------------------------------------
entity pulse_tb is
end pulse_tb;
--------------------------------------------------------------------------------
architecture tb of pulse_tb is
constant C_PERIOD : time := 10 ns;
constant C_EXPECTED : natural := 7;
constant C_EXPECTED_TIME : time := C_PERIOD * C_EXPECTED;
signal CLK : std_logic;
signal RESET : std_logic;
signal P : std_logic;
begin
stim_proc: process
variable STARTED : time;
variable FINISHED : time;
variable OUTLINE : line;
variable RUNTIME : real;
file JFILE : text open write_mode is "junit.xml";
variable JLINE : line;
begin
write(OUTLINE, string'("[+] Asserting Reset"));
writeline(OUTPUT, OUTLINE);
RESET <= '1';
wait for C_PERIOD * 10;
write(OUTLINE, string'("[+] Releasing Reset"));
writeline(OUTPUT, OUTLINE);
RESET <= '0';
wait until rising_edge(P);
write(OUTLINE, string'("[+] ("));
write(OUTLINE, now);
write(OUTLINE, string'(") First rising edge"));
writeline(OUTPUT, OUTLINE);
STARTED := now;
wait until rising_edge(P);
write(OUTLINE, string'("[+] ("));
write(OUTLINE, now);
write(OUTLINE, string'(") Second rising edge"));
writeline(OUTPUT, OUTLINE);
FINISHED := now;
write(OUTLINE, string'("[+] ("));
write(OUTLINE, FINISHED-STARTED);
write(OUTLINE, string'(") Measured duration"));
writeline(OUTPUT, OUTLINE);
junit_xml_declaration(JFILE);
if (FINISHED-STARTED) /= C_EXPECTED_TIME then
assert false report "[FAIL] Incorrect pulse period" severity failure;
else
assert false report "[PASS]" severity note;
RUNTIME := real((FINISHED-STARTED)/(1 fs)) / 1.0e15;
--RUNTIME := 0.000000070;
write(OUTLINE, RUNTIME);
writeline(OUTPUT, OUTLINE);
junit_start_testsuites(JFILE, "main", "Main", 1, 0, RUNTIME);
junit_start_testsuite(JFILE, "pulse_tb", "Pulse TB", 1, 0, RUNTIME);
junit_testcase(JFILE, "period", "Period", RUNTIME);
junit_end_testsuite(JFILE);
junit_end_testsuites(JFILE);
end if;
wait for C_PERIOD * 10;
file_close(JFILE);
assert false report "SIMULATION FINISHED" severity failure;
wait;
end process stim_proc;
clk_proc: process
begin
CLK <= '0';
wait for C_PERIOD / 2;
CLK <= '1';
wait for C_PERIOD / 2;
end process clk_proc;
U_UUT: pulse
generic map (
G_lfsr_width => 3,
G_period => 7
)
port map (
CLK => CLK,
RESET => RESET,
PULSE => P
);
end tb; | mit |
18545/FPGA | FPGA.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 41 | 20439 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
S/b+3WZyyE2NN0I2emS78G5gzXg+2HbeNQqzwGLtTu1RKu+fteo7MzjTyI9oicnaXKbXm4TdJtrL
CBdSQSW09g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oaWo0XEQxxtgWP21Pl51U+TGxBlWSne4OYZ7e6qmcKkFCHhELNUyIgcchKHVbgf2g1ekpEKv23up
e9kNBFVP8PaF46NC8zdQhdBiyHY4Fble0m+F7iRrQDFVq53YvvyZi2itfVZuL7dDvQ7rjRV6Giht
d2GSFIryCjqjBh/6DAc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
koGZRj1ONYx4dEkr8kV6F56aDfCqsX6JXZS12blfwpx5PIsZJpmuDMgIo3EW9N+IyQs4IZBMiwKe
dSc2JRW9dzyPk3KGLdehLg3ND67uw233AeitaTQNrr6Khu6xVvrozPCorKIax+/0Qimi7XwzMj7m
Xmf202/pn1cRzzbsuAytg7Rezrh0CchL179vIP4VPBKySnasBil6lSYkJcqS06VlTMjTHfRb3xfi
tafIIN5XblcMv63ip3KW4GQdVYJSfWiROSHkcNAkrJKSj4blZtQgdf2tQRwjIt/Vj1FHmqZ9SrEY
gKl/wx4gLfGe2zBgz58itJ4qyGkNFbYpd43cIQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
PdvDeCuHOT7dB2KRfG/IK54ZEWbz64WrER1IKCkqjLU8eyc+Q5B8d5SeXkSSOrUxYfGW2ZL9SNT7
xRi6Jen90/nlGOGQoHQeH4Hv2tMcpx3JZR4LJSNlvk0Fch0YJ2trGlRRUgy9/5BYSx4fpo3IduPl
cpgr7ySt5TSihkyZPms=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
MRPtR4KhdHmz3MWfpDi9vdur+0ZJ64TDHCHLQePx1vP6vpjMfLtPdYmIOUj0hNqhjhWBIqWG7vjJ
Q7u7NBs7PqXQYsEqoR/q+MOp0mJjWU6WKlEmqhrW38BvR5rCZ7u9yJx+xsMmX4wq0YjHXCc6HE8T
522tbLrKEgFXa+OBJ4AkLBo3rExrLkvYOgPupOW3BVqIZkXcv4Eld+HiJjV9reUW6AUqY3TxXDvB
PUv0fi76Uyy32UyQIXDYVqGgJ8fBKKraH7t4aeBG2IN+3c4syZtKiOd1xmPockrVtzFkbkKTsl+N
cC6PvaOYL5JLQTD4kKCcofiKg/q+bQsW64XsQA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13392)
`protect data_block
XYR5EDO4OXnfXqXXmJxxpRof2p/bzcBe/0WoxyLop8Qlv4cggmkdAVBslAsEeQtj/RtHKy+8L32k
lZbmTjfjXu8oDn/bN24hzovJaZV4GE1Raa/eskUJ1ghVUbHtu3/hZp19nSNO9crfXNsl4F55SL8U
tNiQsfMfWV5zcMnSdD+Bq6Wat0N7w03HbU9+E7Q45jSweQERqnlQZAzPdjgQ2c/9IvIKwPAXQjk8
4VTYCfSv8QiYqueJHPFdnCx7tFLp+G3Ney1SUrHqYWntiCcvZzPnLrWyuf816/FarCF5mi58XRQP
us3Y0GcgBF7VEh8KIXgGnDAcjP2Qdf1sLWSLkbyNZ94Ov4EBtMP1BuJWtlkNUOUKWnp4TcDyBXPs
jBZRza+f937VGzJ3XeaetrelHgI2V6IEZ7n01QEIpFdiBmah8HwUlN0ofHhXocEVBZZkrk7DaAnz
cPfmSx++0FWAU8D2ygEavfs7F9MLMi1oczH15ZY6BQbDtcKaBXV/ZQwADXsg0/SeQmw9E/nUGVrs
jsVohZ6bE/4CeuZzSdwQjYoEwOgCNChhTvwFTW7mptGm/1MGEYayjw15e8+CQnvwf2jt6iAap8JU
UuD+XCWRMD3QZ3coiNS0Zwlnuc2Ed3uw1US9vKtS+239Nz7qWWPRbxjoLF8Ea5sLNwDuJXbgcZTO
uW+AV7qkalRcZDRMIXMFahusuGxgRFa40YhM20sO+uOESaJjsXbF/N1iP9OTbZ2uaHELjYCj+5fd
8XN4niDQL1XYgYcNvixIZnVfuhJ3oIVb4/Pc08i1DRviYai5NrF4s8GbMQSBVmsnoJOJ0qBAgZ20
Flk9HJcjeRwTWIMY/PaV6S2eEusmj6hWfRgIFGwYoKG4ADKkCT7CllupSQ7HZ3jbjzWbHdLSjrrt
ISoIqt4iMZrKSKG9li4ACbIZuDcPtPBArj55TVsB3cSB4iNodHkc66+pYQsoLGY7E6ORwoYxh42C
Yg8/cTzGCwJgxBHsg4jzxgDgAur1pKidiyIdwwXMK51xb/ijfjO6PsmR/gYPCOu6dpVIvV2cAh5t
HXh3fl/6Dfn0H27BNH5TW1uDSI/umw2r59SsLcQ9ujPpDCBnTjH7qxh7D53CXWBoV2aTqdbdL+Dj
IAw5w6LeZ7ygbkCdQGv02oOvIdtNlQ7vf2NWt92ssen4IvgvC35TeEHqTFg+BbfnTIhwah203+Rt
ENWHDo7mrJUyjyKzKX4uNwoInLf+M6oQtFW16U/sGlfZJLJwTRUQ5Ddro3bcsfC4tl0tXmiseesj
cNW3shMf6CPcFulfCxAA3gVspVxeV8gfrQL0dOEODwPe6g4qV38mQWXenkwniyWlyEDw8q0ocf2J
aTd2ReA6OlgPkkSroctjVWa8TR9bW7IV8tIySBJSC630iMykNOep5iFCfrxh5rcEjlFXFgsKvf8R
swAyxyyvNToS16/+qd+iDOO29Ey6htPWw9zTmLvD42795302PErW8N70PCGpHjUE4uc1Bd6Jz7Q6
diqGUf6BEVm/GopMQTVlkwA5nL2S5xz2E9dozGxSCf677XzzMVwRkbt83+wGp7JG4Xv2iuct7re3
BKUVJrtwYh1+akp+nO3hgVYEn+2UApxWi0HpJyBjAZOhG97+xLmmjxN3dMSljnj1pa1UpaPooglq
2psTnc4rxpdNvMaQVdjlLUwWc6HwwbO99GP7E83ZL4RrWPLlVyZw+1KTU8wErAvksAX++noFASc6
a+E7maWcvzZMrEzMtwNJII1IRA/I2Y0552XYUDNrFvIDeCa2DAB3732zOOcj1zyVP40wza3syyKn
vv/EvIp4nS8wPXkhBGZLpB/9307T5oqLdMQ62Ui7FkQOgMCswwWiNS5nYOm8kDQYbGxu2F8S7j1f
sk+BV+XyaseLfyO4H7Y8f+mZdX0MsepeMcs76HN0ZaVnFzChc2tuU5gdtNeUpgvdpUu9ZrzAdOpK
A6Wi/siB5yPhfbqVgsJcxBgWqVsDDmg5wRMgQuUn1kozM/CZ5mlcsTJlAa4dfETazDD6dfRxGXFe
wv1rxC7LcACezRXZapsDKw7z7r0PsFlkcc37Qau1d2YD587OZ3ipMBexXOvc6dWvKoaLbFWREXiU
GbT7knkWqFlumS6UTyXAZCBp+HiNJnzVefp8MNcyg3owh5VaiwLOYHz+tb5rMHlIAj/4IVUcOeEO
l3YMRTRG8vzK9PG8mfTxn9QCTbh5cRkagUpbKYOlMnunrL+YncA7CdZSev3LIVEzvnIz6R2YpG84
JUcw5gM7Nl2dEI06gVeSGW0RhTOPJ/ZJO0bHDdFg6kPnUiRO+F3D2Png0K+V0T2P7IWNMhlLEjkS
C+sdaXFrDJiMKfErhDgVn5eyDLeTyX7B9yFOaUvDOiWNRQdMmnWsaZDXk2fr6XNLjORzJ1y6O4mw
vtVf0xCNSYkDODnU0stPUBiC1n1spV189rwplzCf66nC5tVs2GC88atONAyWQwj1dRAyVyVsaND3
Gf/36o+wZSnYXTRc5lvPVCTsAffENrYPs6DWdicGpl5ZFcr0m83KygJrk18NK7tQuIjGRAAED6Mn
bn1kKLlAFneTLfW/EijF5pgqXzSe977B7kMoSu4LxYROi5O996gux2EHMVr1GdXFW4NLW4oIVGeb
Gao3+1s+xpo4dPXITJ5vBtlr1/JoFvilbxgWj4VsutdClozDhYPpWYZnFujfZkbI+E8iDJ5q/zPb
Wf5A9kt01+ojTOddPhFyKO20YkVMtX+gPv6fSU5J5AK6uui9AVDgsE4N71GpiHkYJuZKzIzBIpro
5hHvNwv6lSZGkH4duPwH2WCQonDRIIz9LlJm3PILdRWAiMXC86EsKhuKVzsmZC8/gbLbiFbcrLBb
gCuNW4gN2XSlwgeWyKofdakFMowjvWpAHDQrpedBU9NnchjhDd8PqnizBKRRsUV0s1UEoEjmZHLA
+8AanZrNRFT0Se57vpiF9mkeCiqywS5I+SOdmUs4vTtgdznsrpAbgQ0N6NLN4rOkvc2JacceP/4D
iCnI9Cm/VEWTytVpA3We3x8M9cDuCFxGawG1tkHmyOqvZygojOj2+jhomjJOxygy6L+owE/h1+ND
5XViOE2s2eu4TzRz403OJQo+czP3dnMh02kJ5c22uf9BX3qUXGMFO3OtSYhzGjwnpSbV+FrseVi5
MT9e/G8Nyc3sMTbvO/oc1kNwfESatzAgXk9eqQWQDEs5tF6hHdjRxJJz3lmQXGGbSMJxTT2NcbsJ
RSHdqB70pkeeXe+ubb10pX6+pmDKwXOMjd2IOo/8kmHsk1525W7A81aRv8MGVooYvFz6B/rN1dUd
Ce6xX6b1zAzFG8sRd9k7CMMdw4qpOqyvxMUCVCnKOiYRatnmx4rMacVn3sBlvglGXspoWhwLkSkb
HVkiyZr/qMUxXT/h6AdS4e+ph2wGye26bZqGzrUwkOXuS20I6wnoLqtSfJJRzhnZ6Mba5WV9j7it
wROgcMVDPUiwfEwgLMrN8txsTF2XwhG6H12H8rgnidOYhI0spH40ztgiIePI9ZZzaJRD2WRzGcOu
AbzHevUCrFvJ/At+cI4uL81Y5++AZgJLJE2xX7R5hm6xWC2lTjZoOMPwT5E3ItVcVRjQZ+pLLmoq
Gt0rBSr5T8GbRr8WDXjez5FZ7A0FE5LRsVhxalqW2OzJ1TS09NXpjOgsA7Fjm8RJliqf0+ovGn2u
3HA3HyL3h76CiOTls0QUk5CFiUut4nZ6y0BiPz1nSXx5qJ/FGYMrzao2B8lXS+HkKSFvick2Z+9l
n+2Kxj94Ex06hSBaE+LmFqrDiIPIUPTpfCeMJQtojuJMz6xLhMP4XkE9/Kpr0Mo68IZuZsFUZAle
dFJl4cQtAgO2EFL/30ieERNuFwjtFjmJ102+WBrFDFohh3W404Ywr9SFQwW+XOhZsCiAMk+lmWpx
TNFCR9b8kiKj3gCSctRouxmoJEcPKLV/2bLRr2q+1WGVoyHftPWNVJmQ2BYLJR7BJ8S+0O5JLerd
tr3BR2WIvtZc7YMa2sp9BdBxXlS82XEyp/Ju2fAwCsGOLOPx5hUsPCRpkEuPGP1LDfpWzi0/kMgI
dlgiWDcBGjSDsP9B8Lf5Uf4Zs8qX4l/wNyWZAiRu9DjeiZnMCiusr25Vb4/wZgYexkcSX8I5DQ+8
ycquwBHNkNCJaD+DmMZc7u3xUZB1cxQv0ThdgPy0Jfb/lKuWnkZGveo03srjUTVkM9iV6a5uakGA
RN+ubnOKjtS+qG+hkL/ligKIugEQAY3HxYpUCpT6JnpT7C4T/sGesr4IOq4x8IQStLG4Eyfugs+u
XbN1Y0oW3Kux+dnJ+xAmh3SyPT44IY8JnADS3zF6P9u6d0Ng7rjgatBLaqIXokTW5XuzOM5N8iz9
sNT9vzSDnRSRCb+ad522MylPIkq+8JrkHchJlXi2sSPFzFbkMRjh5yXz8pHzCcQCiMVBIGZ+ndjr
jub+C4G3LrFYabznIK3ORWRMYxsxdi1inamz+M9jxKVSZ74XTxgKA7OKInpwIlbHpe8IexEJb1md
uvl+r+KPE5ARw53nqba3DLg5gDR/w5QCiA0/jHjW4eLi4mlql5UMKnVZtZe111G/IsWbGUEiZiBU
pCteLakVQkGDETQ2O87RjS9gEQtnMPpgdV5bCvtWQRfutFF+aWfRZH8pWDaZ3eJAQoYwjppTjoCF
1Rr7kS1ZRYU1kRaI3JIq6IGS8aY05Ql1+GhTJ8eFBXeW8Kd3otDqqUP1cf0Tx7kbNPNTplZKTrb2
3QvOvJaRz+KV4WEoyL9dPsD1QpH1I6J0OXhEJcDogWqh3KfyKjdpS/fVVrGWlas9Vb0T3xU5x17B
mStx7DKiD3wpi2D2VNhICP+cRBSgY51VUT5Htu3KkBmi2QbOQPp4eDXdWgL033HYseQC1bNJBiYI
sv2k2eSxnH0D8QsaTg9tkT7elaK4dAaJwyqhG+Ig8z3i1iOYnzkLkJ32EV0j5tOvbkodq6g0elzn
sP/cJSzxcI5ymJLiTYhkEjYk2KfQ3R+UZoPig09qPvBDaaOKciddZCeuJHILe7ZLGG6cHvqvagIv
q2D80XWa1cY9p/bq8wcN5UAvtw327anVMXT6FM+UAqRvdVcLxYGqI/ZDhevJLdzRTeqiwA+hvk1e
EazsnT3OcvqEOLMRcfplVjfmgemAMHzUTj4ngnU4nOCHN7moPR8dgEWP+zjqpv9CmeGU2oBg5eV/
FSWfdEocSLOz0ZipoFU9wWyvHNNZCl6fDsIMeDTv3v1oQeIEJcn6XbVs3Oh3RwvSHPOJiXcQo+7f
s4BvpT3cRX74CgSCzfjJ9LCuVAXsUs+fxv+tLIaOtpkqaqhVVvlfme7TWWU8jCXJRkvFkilPqfre
5Lc4qmfwYxqqJWKF7VrN7zTtdNaehsLlJq/7DCGo2pdXJu7HTbmrGgu4e+Lm8Dj9t+a/FqY8URie
cmL5/gKw/GZ0NdyYrQQ0FGBcFdXDStp8l5/ARbKTYN1B5CEPCDeDNT5LU2TcAKApFbn+Xylx1DgW
oYVfWQ3FOTU2rVxlhv+v7wbcn0Mn2LG2PCfEjEnEunkGIX1UbG9JphDP5Wcw6gvcsOAkrS/FpZDc
fZWlNmWYw8/Tqf047sXflqaFuoPEPcd6vWwhK/8hKGXLR2oQFN6E2LuePpVR5IfmqTBknm0L+LRx
adrUkjkWRzOsSXktTIFWzjjC4E5CC3Zw2Y/qoDlPcqxClCbi9dyneUO/84eDMBDZj3r85Ud1ZL+J
rR8mPNJfgclwLH4plDSf/9Z1FL+V44yEm0YfqRUXAGsw7gNwWB5QF3msqxqIWkOrjiLnLc/Ry9vO
MCEgfqWJJPD5G7BBey5VqhJ4hAhVp+OH6rQ4dXobEY/qFeR2py0T6/9oUFcUT4zrOYpGyyg40LC9
p7EC6uyBf/QHiofDRdfnZ3hMmUuON5DpQF2IsJ2JtCdFUIDTLfMh0z/dWwpsU/KUZuhfuIO2fyvW
Cjk6xRNP7RmExcpi4lhWV10Y6G5OoEg6ARA0T1Q0l5VNOfHDNoKi7z37tIGLza3CWtUbeKT8g/os
r7fehAV73LcDwBwFvt1BTaqAzJ6ESfS3iRRAtJfAUGmzLpJC8YpgHr2jqlikUet8+HpXUVohX7oJ
obmvM1lySLBBsSVRh3oJ78iPjp+Lx5x2cneIIIIcfP6Wp6kKxXjsYIqb3rXhHDCb+cwCnfm6Ha7m
01s8zod7Nk73FokdwSllllg/yb8maAZgIuZeFo6z1LZ7Z9WgvkzWsZhn+bq2WsmW6OWmLvGYMZ03
/5gIz8wQrjbk79jAnR0onPz7OSKQnTGKEpAX3hCh8qLmoVDiBag0z6lPbwVIg4ttIysWfyfpw2RO
g/c6qhp78jQpb49fusLcXI9QnXfOlkt2HWDdEd6blcySGoYZxe4WZxPPth6IByTLpv6HjZ0WzjEv
WwmNjBh98Sp2kc/BrcQn3kUP4aAjDDLn5iXWYVTVaBLqWHKjhfZJtwdk+ouEb70HJqGf/xZov0Gt
EBb/WIPL+CnMyqJ2iHrw8yXn+h5Wz4LQY2OslmHImNztaCAtGaTg6HaiZQ48IfniGDRQJsbLS5DT
NH/2hAsB2n6Nn8i40vMGMBGOROvJ4Kn/O5Ic0++44PUDiUJrgsPKOb2In4s4RYCkh5i8HZEaU1kX
aISH1SiysWGFwRDBoq8KKOi0g1t0QdMg5UCVaEGg+TZ1oCgpzPEezzQjH0hWAVEKjsXdVw5rblUL
AJ4BDTxVo35dekv/6n9IqXoXo55V99OeTKXIuPN7WwqQjdZb1apQXyR1Shx9D6/SeheRczDbk7MK
CfW+c8S3jfef+Ah6LDnEMCTv97LIlU9MC2ImI1KcAj6Jjdgsnv2j/Cu/PhnaTPgy6nqZ0p+T+03s
yiH+Me6dPfcyLkDaiNPYWkJ8+GIRscCTsD1zzo8IM1yEN3KlMWh2X3yUmtC9HmFfmo0pV7/b2GQC
Y2046njGtLDglPhEM2Gd8pjxYWFlNdzqOlAMA+y0sfiU/izWcwSWqWp2UXgJ23av1DATSs2+RzzQ
D+XWvBvD91rak4PwVMDfUXK3rxQayZzm3toRKt3gweOpk6Mxyt8W7NaJDmxdyha19jvTEhn3RJvo
vOL1lDqYPXM7hbcvDnHy551FtQApgKQCihOGlcFx8XMuXDfywOWQ7aKKtqhpJDFAoMiG9piYheTU
NX3+RkTmf0Vp4vtrEVn7iyjKuIfswo+8ObQEOszOUela1odwPiGYcBIMtCPbmfYw3is+vqwpxkxN
3VhkfBM9o9ncCpMVpDyQ6ZG11YS4Pob9LrmUj/Q1cPb++kx4GacgV4zE9PuP+4cN8jnIfJbnNTDg
bnjPrXObCj0O7msOY6v1CHhdAMR5FsxJ/PfBBlNeNG49qeJnt/4ugJVJd9S+W0dB57Nh2G/6WHzV
wXDu0Ugc9455b2uDWw9F4XuEdWjte3pG4kDVJ51nC67FziwRzKyfFrT1sSclI9jIATnc81P6xzkZ
130muSr8YFGjL2NG3mJZYtV4h9f/zB42ou13IMLrjuElDTLHl2F3vn/mq0y3CgpUcxYCbvixwABO
xIBTKFPv18L6CEvTK5OidN9rDeTgo65lGQCDt7twrAiduXsMEYCxlp1P2fxVy3waUOnqoUt9kqkR
Y6S+wtruIKpxA2r7DoDFs/RGEcaJufffxRZzM1tGUYsu+WBzhpIHqbgasZ6eFWm4dMapFOLF4ptc
AP1Kwvp/E0SGSWnNK8CldMnXJk734f9kycAZZ0Uh87rq3440nZSIvCg4/X4woQb6o2pj178STtxZ
q0qNgFrqbCSH6KrIxUrF0iFwfjV1ihhrtMN5XQO3ByFRBiBFqT3aKeD2/zFCOsPzHJULfogYXCmT
HME6uU3mrGtGjSpL5rUrCsi+FPU5MdxfY8/RCScA3CMxcV2F7tQ/relgFtzZ9V68QxyznbDUrYv4
/V+ulQ7bIQwGshiAYfir2hwJoDWtmP2faPiYoxkX4qYoRa5bsn65d+hevAqoUy1x3xB5TE1yVfNX
sg+NI9W/bZfYvjKTD0szBj3zS5sfySYAWDTxyiSVgxPBKNvLP1FmE5GEdXXxn8MiWZbzs4nftJ5U
+xJ9q93lOmnmlBrFLLQvkN89d5xE7vEQvec+aDPlIwtSdG64h1qetKk9NlGae7bxsQtLkDmQoSWx
sisXnRZn1IVNvCrS44vVeRyj2as4hnH+mDPBkIqu8jG3j8VPj75h6A3kXXE2BxZi+Auzy1B4Enbc
QR29J2ZD9pYcyWVlUJLkvzjoJWnaE8iqRPqKsVqgGi07pwp8c1FmyCwQlcCJXh97Wdzl2IDL0ZY9
DJJ5EwJDsFeUC3RcZN5btpjbHKo2Wu3bctFTzOcWKioYPAQCdttKFkL5zknfY8ntHEXy0L81/Hj+
24YuIBXhbn6L4kfWllHnqQnCgmvtGKbrRwRZbsghOMl8WjfvmfX1HiPfbc0wZDZLpRjyM/GVcTbW
bFXXIMap9caD1PldRZgaSXP98xcsKVbQyAiYbwfdcPuMSyURVkiKNIc5XiR1YmDL82pIvlY3ox04
Fi5ner4TjjRNzHnznQ/tse7BNsFbAp2Jkfii7UG0XradZrzBHe7PzN16hIiqRPcQxs+cep+/hUYU
K+9RDBimtHGFRWbuqtx8WOWQ6wg+piMx5qpNI74oV26QmHUqp8NubIbjaM7CT7ImSIbFkvl3su+U
fOjcQwh3tnIjBFP0N7yoqneXqZYR/KcUTuYO8d4b20hUcwrJH0ZnKTYcP0QJfgY5F5VOfE4MWUsV
qBwxUOPBfBeK/62kcKCyG84UUiCgNOLfjGdtRgP+IHRXGZTwlWtQcyeOBjgIcT7ix2rqDo7u85+t
TtgvYALj1/Wlw/0G1x+DNnreJzZ/oJypJOupx0ZQlu2oF0xoNPvxmxGzEz5BUC4cnAnmvhs6ejDK
kuaMzJSGVnOvB43tIQl6/pTX3k2BhCNnE/ZL7heKvfI+oSXSBgpB0JIt/Y8chWdsc06QOXvba9Xt
2E6b630VuaDw0suqT4mNrTwie0dxyrfR/MgZmW92TRhNOVCpKwQJi6+L/vDpyNazMrP72Q1OpawA
cPH6+7T8k4Zxq+3LqDd5eWh6QOGlQUVRsa2mQuIP8aNWXxBpCbQi1Ugp17LwlJ73YW55CTLYRP5o
dyddhuVVsYUqxuOvQ+lvIc1xU0gox48z7XhRlf4oUQWMSmJunQfwKEh56VCejS38RCwandNvE4xZ
NablEwHtjhaLIuk0XA2PKz/2aMu+ILflnfZ1u7ThtNjygE35ntplh0nVNuo97N7SE4Sr+uQxgmmm
bly8gmgEeKsNEqjLcaN0w1o3MLbLQSOVVppD7oeK/hohMd0Zx2kucrwQ+ziEDegdxFPXDPnlWCMq
OccswRWsVEXFGpoIu4AxX+9/9cxRdyW5WEZWj9DBoNAVWh7EFkiZeGAu1+2sIZ2a1vWZIobL99wA
WuCg1J1Krde/qJqsXD7eguB72b+NSh4Ez8ANudpsd2uXlf3iagl146j2yRHrd+FhbKHvirmuSa+4
Th6IqWlNLkfkFKirlEPswDc6rAEfaS4EM5yGr7arOOXnV6IEhzq9PBgVcImQFjLDsuWZ9K/HMIeh
B9AEmwxzNTrhYruhfRA9a8hA0dD2OEYyLa9F/YH9M9qHpZrehmGdS+MJ9Gk19ESRjObDuIs3MTrj
s2UpOej3cWhPjdjar/OildS6v5pnViSKiiIz9Phbi+UbRvViEgrKqz6ILJ/FmpFCfIAIPMSEzhmp
ARJgy5+x/XsT3CG8L9jkYutcRkA0+QpZhQWCNlTsuHKR/bJnh6wmxKqGre6k8S9U2jB1/EqimccH
VoNl7hfLqHx6SOZ6JDmVuIPh0DbljPtBwRGomT3vMrbfsk6aa11p5b9zG/+yG+UhV+ee+EUOxZk+
TdpWkJgJbkr1IwozdE4/Cb7nj11QfB179I62uTCfe1NflCoDg6DZC5YKlEaCMDUUaDmEPflshPgH
1ceG5HsoXRd8UKfDv+i/rREMq6i5+2Uo12VbB+aASfO0is5VoQsX7GJSogDv/5RTrLZ2P3DLj7GG
eD0ihaCE8SZSuacJVK9BgEFGYnOCEbD2KURdTFa4zZf1dzu7m1QdNXGYtoqiJ1AHm+sTXcoKObCC
UPi+uuB4W7KNMKkPnVaWLmE5i1RwOTXicMx0Al0br9vPzsvKncq7z+IDaDer3WLAlhdEOWd/3o1t
tD4mOtyWjBYDoNDpNPPV1wDmofUGaAtJri7pBf9wYQ4Wf8vGF8z7vYryuGqOYfFeQwlE0+6ihpIE
DG4tR7yTYPqj16XzrjRHCt9ovoJmgLn4If5n2UU24wz2wYlLlz58oIK0DqsXoQXB/u0eADKivQcz
UZkxMYsWdwXznLR8HZJmto+xI3bjQ82sc/myOdreShdSxj1EAi/OXqgo4EzzoDPlMpHy+z3bGZQR
iADvGd8hjBFCURmukazHWsSA6Tl8nRn+sVD4RA8TIa3KoRbwy6809+CWj4+wYAOvbQkUCFKHWrcu
aYdvVSyny0Sf8rCRtVF5uk68ZQtHT4C/nO9us2K+qCJL/wRxNHV1c14919R6mK2zG0zyehdz/9RK
/crjcikT/H988FpPhvYmBUXzm9eU2USiBRXOeVKvII660kNtt6MdgmtQyPestA3N3vpmbNQxYGRV
aRYmP1VEW3k/hsewG7mMk0TfGyNW1Zn5tUXqF5Fm447fvGYBaLs0UgWk17Ns2yAvpJNNX1/IgC3y
PYJ0vBsTui20wxdtOayZhzjdSZJGvV/2Pdxaevp6vHxS2f2Yu5shVrdSq5s1fPPQZZVSEXtntRU3
xCqEw/aKXhO4qYFhLb4m/Opf3hnj9iUhrmVIL0taxUcFPqqD/c3V4F4AbptFsriohaD1iTDDDioe
AJzvixVES5eZ7j7zUTQivg70PHlwjggcCEtTTnmfbKW1MmGkI5Ptel2Rofll0AqlIqKnVsh+V9DU
Mr4Y0TetdleHRfcR5plMhNzXKvE9Pa8DYaXXFdDOJKVEedCagzdDg4TSOcKc4y3V+W20TgicWJDa
jqDWWMXbj6c/L36rdnBkyV2ziawsa22Izt5RRyro67rZju/ifpfgEwaYUlxdMb+shj47An0uYJM3
tVnRo94TeyV3EPARAiGgIWyvyf19cdMkYbdATAIdZAdn87mfQtKxq7oPM2il5OYkpQ/Mb4Z+pdBv
AnQGOHPun7RZhzsM9dY73E+51uDAI34J8U204dsam7fC+cuTTVV9/FHXWsSK9qdeQ01zBYLojw22
mXL9tDFxywrzOHC471kK1WoDpdtbipHHeLmZ964le+485EQy+iFPE1v9kmJFF8Eysw9uBh3WRYhm
xcmS/Ap6Q9ngE5XKDDoUgWeSMSTD6jRJ4hqLPULBJiUjJnkeQoFfalRMfMKtOnOF5Mz25KEKxTMh
Y6BmCa84/rp+6jnontD2gYTwTrBE93OupwUlvYKAOho9NO5CQeenHRPlUOzJiDzfFIoAM2C+Ekbp
nTSIkIa5fIirtcuLIDPOfC5EbELU6LwXuzg3rlm1qnLlK0HjUbqIMNMtOBsAfZIlQlMT9qDH4cwj
kfQZi24RZQ225GLXjJKcoTExPPAIre5+Ip/j7Ic76jKNBpLJA0m1NYy2CZ39qYIOqFqMi/15jHNU
C2G+ijG67YLUbJoebwMxtWhNB+L0jiig9qBx0vQb6yfXzLAAyjMaYHXs6uoFn+0I9DCXb/ZS0Ddy
LQpshGBu4hs+paF3ymVerxg8G1tozF7Z9QCNfd5P9Sm53URH9u701saxdIJI7RWr2Se5JcMlz0B0
y0xL77exLvaaj0BW3/kR99tcKXtqAMZWgsVlX8+sR897pyexpcKPz8Z2qD23ukhVO3C11GrtOVM7
1/DOG9QaH8pR8tO5cyrT9BQGrzz61gq+wEckO0OqTqcllC4p7Ws6AhhWGc/n0p5IS6p9lNBiQ+DW
2i9zs2Xj/rCaKaf/6kLDcu24EeWDqsxqpuehZVOG87TJJ8dz4yG5t3L4MZFrGHWekF/kvm45wBdg
+VsWC+GCAoOLY1oNU8ANyzur2fWl8t8zw6zD4W5fkxKXpokUMliYSJYgs9QJFDsS+P8bM13Gwwe9
7qenYSaTvsqXx0LvAnlYFatK2if0/GJe1b45L3rmwmHiz4He0JBUg5+veK1TJZyADwJv/Fyt/TzM
IMlE9HtPS8BDIzGYVmVWHHWKIHUiRN0oNEsGvNDawKZFLU5eFiTvflOtTjFdHjKoexES+TbdpjG1
bfAaXGR7oyItZo2I8eu8gY4sc0VNsfaCq1TNoxchAsQUQThMHXUwkKZP7XZJ+aKSMgbpyADQLkwl
H97dRYew9QQc9NyDJyLnqBw8YaWnCnInORx1/AeeEjBPOcctR2SJR/3CD1GYLmb0mKDhv+oxB5ep
XEfs6IYhZE6WZExRegGY8SSWKH1d4lK1ht9okICDoFcD6aFQdghONEZpjnXwKS0S3MtEy81gib/b
jlBnGnAiWA73Z9It3N1sTfWZGI2atthgBVpy9AGvNxpZEHPjQTAOqcn/VBvaNA1HlQJvMnWAyAsU
GRJBjAbGS0pGzPo5d6qkX4slprdgV8s+VtN2iXBwsh2uOn84U9Fd5vQ5QMQKK46YeScergKqPpy1
gBis4FvgcaiUdoNlFreIFvKj1WeYwbiBl3b5RJVqqrSPv+Z9gDwMx+0WqUqGNtJFBFE43CG/6KkJ
AcA3RCI8JYSfjNyL39UEl37KuvXtK3Blc7M9/H0JJdKnONu7q7yOFfu9fNFBBzIT+XNerX0r1lTA
NZRh/mtB0TwjidZrDrw/iMj1mcgKQXiQ46EpMkH7oRrUW9UIAuI/TpQvEGD0u4YvMNQ2+Qu8uyJt
FXTIcMg/Mp7NNu/DxAQI1WfiE9bnOq0DNwDGKeT1XT7SxUGQqxuGUSVZ4p6/70OL6tQljc0y5xmC
ttxX69CXoixVf/VuoEqTrXhirPM3+TgqbJ/Y9if+CL1P9Z/rWQju47tIbPlZMj5Xpc+/1J8z83ih
rZVU3kQoJ4OEoFg/+7MYX/MrrURAA7uWBmYf5cr4Bi0Xx3CBIhKr/AvwcakzbCmbrgjsoJCGeFAO
aZW4P+HdAuhyjLcnGuac8x107TNBmX8QGeoN/d4+mEvTKObQaokkb0TlHb/b2FEk7tt/oSBJQMWa
814f0jFIJYWkWSqoSzM6HdrFPXs7D1SMHvplFlO1ktexYNqnfogwX8/rSCX+VqZkhTKuHPFeSPgl
PkfNQxP3+C2fvTXVF7tT5UJKd7HVY1bI0MNVzF9sOHQuYPBh9rHQ5quM/bZRxac6CisTvcuwQU9M
LNe8gCpZ4VWvzWHAnJP6j+1SqwKLBP+DM1Q4jUZZQe0u5qLERe1FMuffgm5I+FS6hVmPOqAg9uNr
OMfQyTmlfYPOR66ohLCBaYTgHnLwu8mdBIuF1sa3XbRbKvetIRmfWN/MXZLrkz+OltmQMyW2xvdK
TrFnsY75xhsyLtYjUMBNxqNXWpzkPkNJvW75fVijaZLnAiEybCrBvWQgnFcXFufICd5VQ/Op4sG5
MEBkIrH979hhj6GBL8JIq4SR8kkyTWCogCT4DjocJhGEXAsweTbY6kYFZAooNqosPa5a1ZasrPJ9
KR8iLccWQx85ujsURiiht8mqheFyNr3In7FuPPhFgt0xHP2A1f9Hdlr+3LBd7l+ptfQpjnXaPwYD
adUapAatBx1cpdXqAW76vrB2/i1YP6kXhGNrNmRjTfYwv3hVUBblH3vgr6SqFSxHqW7alHP4zHIC
bQQXuby9fmrWIghdBEBetGrU1YAfF9oxyXtBjblxsCewgW5rBI94PO2mapwzHPIy3FfXaQvIUpht
Xc2jYHhMoQAXZDQASMQ4fMF9S1SapZh374yQTLj7G+m2PfF+Gw5ltdqr6a3p9f8FhxOb07Atbxkr
Zm172W5Z62SSQa9Pgqm1XtZvEgncfESkN9jou9jywi0RbMMFZziuui082KsIYpSdRIB2G31js2lM
veMyoPp4CHDK+WBv4UricxKqrOPJLVcuUTQQO13PPm/bN1BdpfjxtdauMuWbhv1ri58+FwP6KCUg
EjUyaCu5x/pj9qOmn0+5j9iRUp2Cuq5bdcSiCyVT5SLidcyPnY9DNb3Tb/kwh2lqAC9nmGNrzasz
TzC5Se94fHNqyNtU9Mm68fqXIl+eQNMugBu7s9JF8nxS2xzA349fgvFDJzp3m2uNmvWAXfg5dGme
7p69zyVvcxWIeivVGO5jsCk3ok1NN0lKLx2vLHkeiigDou7rG0IuUzHqNgyY9nxbB+nwJHUrTOL4
cGCppD/Nk90K2+B+vuoFsRW45G5CEPRdtchUyTP8ZjCz0EUa/QSBBVWPiLVofBihAEOS/00jl/GZ
jruO7YGhhn16UlKvJdACa7rWqerLpkTXHG0pNnVwwynuBmw6yzffx92tbNs8bXjHnm2XBUItGTH4
Nrp/bSt2H4vMPl5ghpzb0FWN748bW/fw95tILnesbogBQqrwp8K1nktbq5Kk4GVQFHIVsIXJmEyc
N6vXWUeK5d12KDf5VJbsWBpwYVaT6JrSlFsKERTEqKo6D4Lb8YWbwIRjMXuOtnH/CP+d8bMeOcoe
1NHawKvaTIVQbHvusIStSSLX6Tv/aI2jsFSLz3OQI1liod+GjwP35mTrhVTtOyMzy1wKOIXbiuNU
WfP7xPBhb2HdJy9vqxhKl2sSMvG6nM7VjByE2Az5TjskhxTk9h7N6e/2Bar3hUCIritgOcvQWQAY
ugDYlK9LJRNCZvHj7PySQLnQNXlKr5YM6NnxfqUdXbqJL7NZn1iXFCJRxwVqKr46zXULWFz1ZaIM
pYcUPZDJUWls0TFJr2sLYF/oxRV8AC/j/8xu+gcKHxnYdWzJTERiRcX7E5miL2mCAkKoFV3ChPhr
gWsFkY6ez3tKgmDPGbNiGMaSninwVtZ41EikOVeM3bDF+59tSnBzlNO+h1tZcReDQSAmXQktpySx
AuTcEDpiM1MjCTUQPPiJmyvDBUR0xJ4TpSI9QTg5yZhb10FootnsTWx/40JzCfrdS4AOcTZmfJnI
gGIfmcBUOiqwF5VNan0xOA3+fY3lQw3yMFCwG+erYWpFdDI605xWlRxjllFM7dBMonW/Zo8N2Dfh
vKMm+7aDsUSvA59SSNBrcyT3BhAqJ6s8BSKnfyFFmBRhs3hz4mS5c2Rf0jwwRHQjoJdYY8i2ofOE
u47sQDFKnfcjo9gqw5QP1TL3ead6G4LSBDSaWreSh+aQP9NYYpVs8v1GSUqNLqBXFSerq4fP/Krk
e4Sx0GvT7lL5eT9pledKyJXxljztybUkrhtZvf8ub9AXBy0lxiWEWNxXmFb4fc+ZRVLiv3Wdj1xA
j7/NqMhQruR06auKMqZ9wSUPMyQmFonOXYeo2S/yyszqc1AT3nRj6lKI0jOTPIg8yphWaqxib7e7
gEqHmM14pg1u4oOKLb1tTjhmCrySeLqJ2pR3ilqhe/03sPdCeAK3cG0vzWFdO2Ela0dczUPH3wZy
RX0XwFjNXb/f1K46M2S1EqQx4C4I9Qy4CK0hOq+IljjLIScQ916eQEEYe4kTUGpO8rzuLxQ1SRYk
8HcohvEJ3ixdOzvIgfr4ZkSlGvnGxW0TeBq63bXgnsEUqR7a7MN2HBV6rksnU+0ErP2GOeHtSq1G
Wp+nMSnSKl/dzMpPmZstI2UtZ6GCjhvhtNDS1MNcjxtprGCa3A5ecnpuA6ab5kbVwrYNcMV1EFlU
HrYobMyxlR5VVyFtr1U6SEoBQsSYvGSa9/74IDZvxCzUtQOUVmzv6vnEvYWUuY6jVkBGeTv8THIV
3TSY9ZArsgY+IyNZhf6MYjTP7WFFgQS/mRd618mpfxZiS4DaJFQRsOpYCf6rJzKgBCOkZZSOe4j8
QwrAxGnctyefhGO10gTiC8AS7K/1gDnfiCdF/aSumqFB40asOthXfWJtg62QhcW/c1h8UlkJsSvD
5z3L64HuGMrFx435y++L0cUqQrMF+peMLrWxa2YbqNTopsV+9s0WJLxxl99EBceEQdlVtH/Uf7c+
xijZhjhHUun2JICEgS5BvG3Id8B2y1VCB8F8lM+hegi3TP7oycN/3oVyIoyFJy1avikIhfXEK5nQ
PBfTTnKAIPCNVby5rmLaOtiDFZpqJtjaj8odtvEC3z1jnHIiqwN4CU27DtEEmN1rDbSpf1D0o0Lv
z6K7PrLZPH7ZzXrb8gF03Qv0oN0tVz9w60uvdSj4qXOoI7PeHVjZ8aXHhLEF8Ub/jKRU7DovG6UJ
oyXp2yYUcifhKSJn6l3OKW/9vQtzjdl70DCtaaS0jGh1E9wJqiH6YRmsG4DBo2Dx8o6liAtmS9aN
MUOyBN6O+FxxxJxKBkU3XiXRvtldFBX1hC/TQNX0LDegXGYEFZWPEwNTPSdLS/ncDpb1d+A60O9C
TZ1oGBNoIwiDVUcj8rfaLu4QOwSjUEQtvzFzDcWm40DUoMX4JlojsbLDzyp/X700okaEEPo6ywPy
UZpEgOg1pev7Q7tjBbeaCuSVGSksZDar7L3en7euWcV0TGFCVJYL8yl6Fz3+0zt5gQoJQneD0pyj
/q+79I+rmxb+RoYJzWqL8Z63Ydd21ULUb6PflVigStqpP1veDapVgO51I89N+sbtZlD8O2Aqm+wD
fM98LVLNc0+etrADc1zXX+y87zEoWUE88OgLiJoU9WmNxSK3QqefjOzpCQiyuMcKZM6xAbM/X/r3
m2pkrY52hZ2NWjeMF8Y1iOyopCbX0bR0XbulH0hB8z1FzlSlo6MILooCp/15ePTRXi2Ulf6oqr/Q
NYcO31ORyEpNNq0jvKcn7sGKJZ6FH/4hshsxscivHw3DCyZlgIeAR9xK1UmCpoWWRs58JOKzwIbX
AZRE9XGoJLGiZ5hagIi9i0bBTj3PdANVW9Fxb2seq0ZkDGioO3JK/HQ2waTiiUuHSYFTT2f8CyMz
XuTqL4G1Iv6aQWrGWiGHk5T9uvifA8KHVx5SxCD2WQtPLlt1wUZwYmIAzlYAM/E2jziBnfpPU0lL
mxukfK9CbjIaMOtpmuF+fDh9iqKNWPQ+jwe6ouCR2Mo+goJ2jtREXNncr0Qi41O+EyryGyMnZobx
FgssBy0LmyZvJEOv6dPsZbZnyPWALDjAbYt70Tp3WKwyFs4JZrtk3a6NusOIo++gbAT5Y7v9zLBE
wl7pIRbKYuBBwEnfKmeQrtecnqlZ9YvmvDa/VX2ItDPder6FnkII/ERAM/J+KL1JFIfTOV50saaM
YRj70hsRpMYB55q9/n5eYuJ5zcAqsTNmELioahjFEZ1Jb7WrjdN0DvtDRBCYiILPOs7rXGNBPJqE
1QsZ+WmO2z7tZetfGQuEne78g4mbfynugV6iR/67TquQwAox+o3lLH7KijOIcotwWZbe/LrceZIC
QXM9Pqol9Vla9W/tHepEmDqQNh6MyQFpTf4V6aGP8dw0p6FWSv1VXjSmyeGP/UEhvOZe295SzJX5
LMMVeSTgCD8Mpz5fWobJakWt7EyMUZSaI7OY7IlvhSB6jewfxWa6bUCYkMQvFrewHJz8HaiS4GeQ
hk9sn0mOL3vHaOVueiqojhqTVASbdjDIfsBvnFMg7TuWXD67ovxUDYHMQn5UALKpnb+IcO67doNw
/NidH8BKKHOXn0NE7jvNLymFz1sG3D55gsTy113+45e7abbWq3FJ8dFnXuPhmWtCwfFxcJIbd0+C
U/PLOIKnF6yQY7cKqdneBBDNf2LXyutUFCl+Ec0xnRHxtWLGGuMkvedZhyar3coUpUDN0GJ0
`protect end_protected
| mit |
pedabraham/MDSM | crs/BaseDeTiempo.vhd | 1 | 454 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BaseDeTiempo is
generic(
n : integer := 9
);
port(
NewWord : IN STD_LOGIC_VECTOR(n-1 downto 0);
CE : OUT STD_LOGIC
);
end BaseDeTiempo;
architecture Behavioral of BaseDeTiempo is
begin
process (NewWord)
begin
CE<= NewWord(0) OR NewWord(1) OR NewWord(2) OR NewWord(3) OR NewWord(4) OR NewWord(5)OR NewWord(6) OR NewWord(7) OR NewWord(8);
end process;
end Behavioral; | mit |
peteg944/music-fpga | Experimental/Zedboard UART/fpga_tb.vhd | 4 | 3174 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:10:21 09/05/2013
-- Design Name:
-- Module Name: C:/Users/Shahriar Shahramian/Desktop/32x32LEDMatrix/fpga/fpga_tb.vhd
-- Project Name: fpga
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fpga_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fpga_tb IS
END fpga_tb;
ARCHITECTURE behavior OF fpga_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fpga_top
PORT(
clk : IN std_logic;
led : OUT std_logic;
bluetooth_rxd : OUT std_logic;
bluetooth_txd : IN std_logic;
display_rgb1 : OUT std_logic_vector(2 downto 0);
display_rgb2 : OUT std_logic_vector(2 downto 0);
display_addr : OUT std_logic_vector(3 downto 0);
display_clk : OUT std_logic;
display_oe : OUT std_logic;
display_lat : OUT std_logic;
usb_rxd : OUT std_logic;
usb_txd : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal bluetooth_txd : std_logic := '1';
signal usb_txd : std_logic := '1';
--Outputs
signal led : std_logic;
signal bluetooth_rxd : std_logic;
signal display_rgb1 : std_logic_vector(2 downto 0);
signal display_rgb2 : std_logic_vector(2 downto 0);
signal display_addr : std_logic_vector(3 downto 0);
signal display_clk : std_logic;
signal display_oe : std_logic;
signal display_lat : std_logic;
signal usb_rxd : std_logic;
-- Clock period definitions
constant clk_period : time := 31250 ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fpga_top PORT MAP (
clk => clk,
led => led,
bluetooth_rxd => bluetooth_rxd,
bluetooth_txd => bluetooth_txd,
display_rgb1 => display_rgb1,
display_rgb2 => display_rgb2,
display_addr => display_addr,
display_clk => display_clk,
display_oe => display_oe,
display_lat => display_lat,
usb_rxd => usb_rxd,
usb_txd => usb_txd
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
END;
| mit |
peteg944/music-fpga | Enlightened Main Project/ipcore_dir/pll_exdes.vhd | 3 | 7009 | -- file: pll_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end pll_exdes;
architecture xilinx of pll_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- When the clock goes out of lock, reset the counters
signal locked_int : std_logic;
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component pll is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Alias output to internally used signal
LOCKED <= locked_int;
-- When the clock goes out of lock, reset the counters
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : pll
port map
(-- Clock in ports
CLK_IN => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int(1),
CLK_OUT2 => clk_int(2),
-- Status and control signals
RESET => RESET,
LOCKED => locked_int);
gen_outclk_oddr:
for clk_out_pins in 1 to NUM_C generate
begin
clkout_oddr : ODDR port map
(Q => CLK_OUT(clk_out_pins),
C => clk(clk_out_pins),
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0');
end generate;
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
| mit |
peteg944/music-fpga | LED_Matrix_FPGA_Nexys 3/ipcore_dir/pll/simulation/timing/pll_tb.vhd | 1 | 7433 | -- file: pll_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity pll_tb is
end pll_tb;
architecture test of pll_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component pll_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
process (CLK_IN1)
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
if (CLK_IN1'event and CLK_IN1='1') then
timeout_counter <= timeout_counter + '1';
if (timeout_counter = "10000000000000") then
if (LOCKED /= '1') then
simtimeprint;
report "NO LOCK signal" severity failure;
end if;
end if;
end if;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : pll_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
-- Freq Check
end test;
| mit |
admk/soap | soap/flopoco/template.vhdl | 1 | 1728 | {# import os #}
-------------------------------------------------------------------------------
-- flopoco cores for the following operators:
-- {# ops #}
-------------------------------------------------------------------------------
{% for op in ops %}
-- {# op, we, wf #}
{# include(os.path.join(*flopoco(op, we, wf, dir=directory))) #}
{% end %}
-------------------------------------------------------------------------------
-- top level expression:
-- {# e #}
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
{#
data_type = 'std_logic_vector('
data_type += '+'.join(str(l) for l in (we, wf, 2))
data_type += ' downto 0)'
def op_formatter(op):
if op == '+':
return 'add'
if op == '*':
return 'mul'
#}
entity top_level is
port(
clk, rst: in std_logic;
{% for port in in_ports %}
{# port #}: in {# data_type #};{% end %}
{# out_port #}: out {# data_type #}
);
end entity;
architecture arch of top_level is
{% for s in signals %}
signal {# s #}: {# data_type #};
{% end %}
begin
{% for op, in1, in2, out in wires %}
{# op_formatter(op) #}_{# in1 #}_{# in2 #}_{# out #}:
entity
{% if op == '+' %}
work.FPAdder_{# we #}_{# wf #}_uid2
{% elif op == '*' %}
work.FPMultiplier_{# we #}_{# wf #}_{# we #}_{# wf #}_{# we #}_{# wf #}_uid2
{% end %}
port map(
clk => clk, rst => rst,
X => {# in1 #}, Y => {# in2 #}, R => {# out #}
);
{% end %}
end architecture;
| mit |
amerc/TCP3 | ipcore_dir/RxTstFIFO2K.vhd | 4 | 10205 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file RxTstFIFO2K.vhd when simulating
-- the core, RxTstFIFO2K. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY RxTstFIFO2K IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END RxTstFIFO2K;
ARCHITECTURE RxTstFIFO2K_a OF RxTstFIFO2K IS
-- synthesis translate_off
COMPONENT wrapped_RxTstFIFO2K
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_RxTstFIFO2K USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 11,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "BB",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 11,
c_implementation_type_rach => 12,
c_implementation_type_rdch => 11,
c_implementation_type_wach => 12,
c_implementation_type_wdch => 11,
c_implementation_type_wrch => 12,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "2kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 2047,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 2046,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 11,
c_wr_depth => 2048,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 11,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RxTstFIFO2K
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END RxTstFIFO2K_a;
| mit |
peteg944/music-fpga | LED_Matrix_FPGA_Nexys 3/gamma_table.vhd | 4 | 1161 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
entity gamma_table is
generic (
color_res : natural := 8;
gamma : real := 1.0);
port (
CLK : in std_logic;
val_in : in std_logic_vector(color_res-1 downto 0);
val_out : out std_logic_vector(color_res-1 downto 0));
end gamma_table;
architecture rtl of gamma_table is
type LUT_TYPE is array(2**color_res-1 downto 0) of std_logic_vector(color_res-1 downto 0);
function LUT_init (c : integer; g : real) return LUT_TYPE is
variable lut_var : LUT_TYPE;
variable lut_element : integer;
begin
for i in 0 to 2**c-1 loop
lut_element := integer(real(2**c-1) * ((real(i)/(real(2**c-1)))**g));
lut_var(i) := conv_std_logic_vector(lut_element, c);
end loop;
return lut_var;
end LUT_init;
constant gamma_lut : LUT_TYPE := LUT_init(color_res, gamma);
begin
lut_proc : process (CLK)
begin
if rising_edge(CLK) then
val_out <= gamma_lut(conv_integer(val_in));
end if;
end process lut_proc;
end rtl;
| mit |
amerc/TCP3 | testing_ethernet.vhd | 2 | 41407 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:48:07 05/19/2014
-- Design Name:
-- Module Name: /home/amer/Nexys3/TCP/testing_ethernet.vhd
-- Project Name: TCP
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ethernet
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testing_ethernet IS
END testing_ethernet;
ARCHITECTURE behavior OF testing_ethernet IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ethernet
PORT(
CLK : IN std_logic;
RST : IN std_logic;
TXCLK : IN std_logic;
TXER : OUT std_logic;
TXEN : OUT std_logic;
TXD : OUT std_logic_vector(3 downto 0);
PHY_RESET : OUT std_logic;
RXCLK : IN std_logic;
RXER : IN std_logic;
RXDV : IN std_logic;
RXD : IN std_logic_vector(3 downto 0);
COL : IN std_logic;
TX : IN std_logic_vector(15 downto 0);
TX_STB : IN std_logic;
TX_ACK : OUT std_logic;
RX : OUT std_logic_vector(15 downto 0);
RX_STB : OUT std_logic;
RX_ACK : IN std_logic;
PhyCRS : in std_logic;
BtnL : in std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal TXCLK : std_logic := '0';
signal RXCLK : std_logic := '0';
signal RXER : std_logic := '0';
signal RXDV : std_logic := '0';
signal RXD : std_logic_vector(3 downto 0) := (others => '0');
signal COL : std_logic := '0';
signal TX : std_logic_vector(15 downto 0) := (others => '0');
signal TX_STB : std_logic := '0';
signal RX_ACK : std_logic := '0';
--Outputs
signal TXER : std_logic;
signal TXEN : std_logic;
signal TXD : std_logic_vector(3 downto 0);
signal PHY_RESET : std_logic;
signal TX_ACK : std_logic;
signal RX : std_logic_vector(15 downto 0);
signal RX_STB : std_logic;
signal PhyCRS : std_logic;
signal btnL : std_logic;
-- Clock period definitions
constant CLK_period : time := 20 ns;
constant TXCLK_period : time := 40 ns;
constant RXCLK_period : time := 40 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ethernet PORT MAP (
CLK => CLK,
RST => RST,
TXCLK => TXCLK,
TXER => TXER,
TXEN => TXEN,
TXD => TXD,
PHY_RESET => PHY_RESET,
RXCLK => RXCLK,
RXER => RXER,
RXDV => RXDV,
RXD => RXD,
COL => COL,
TX => TX,
TX_STB => TX_STB,
TX_ACK => TX_ACK,
RX => RX,
RX_STB => RX_STB,
PhyCRS => PhyCRS,
BtnL => BtnL,
RX_ACK => RX_ACK
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
TXCLK_process :process
begin
TXCLK <= '0';
wait for TXCLK_period/2;
TXCLK <= '1';
wait for TXCLK_period/2;
end process;
RXCLK_process :process
begin
RXCLK <= '0';
wait for RXCLK_period/2;
RXCLK <= '1';
wait for RXCLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 40 ms;
-- insert stimulus here
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --1
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"ad63" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --2
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --3
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --4
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --5
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --6
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --7
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --8
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--9
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ; --10
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --11
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --12
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --13
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --14
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"D" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --15
wait for 10 ns; --------------------------- Data
--00-
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --8 -------------
-- 01 02 03 04 05 00 18 f3 52 f1 30 08 06 00 01
--08
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"8" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"2" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --5
--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; -- 02
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --6
--06
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"6" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; ---03
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --7
--04
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"4" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --04
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --8
--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --05
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --18
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--18
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"8" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --f3
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--f3
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"3" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --52
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"f" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--52
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"2" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --f1 -------------
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--f1
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --30
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"f" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
-- 30
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --08
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"3" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--c0
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --06
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"c" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--a8
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"8" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --7
--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--69 --
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"9" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --08
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"6" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
----00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --06
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--02
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"2" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --04
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--03
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"3" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--04
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"4" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--05
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--c0
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--18
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"c" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--a8
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"8" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--f3
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--77
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"7" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--f1
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"7" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
-- E9
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"9" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--30
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"e" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--AC
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"c" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --c0
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--AB
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"b" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --a8
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--61
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"6" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns; ----------------- End of test Rx Fame -----
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"6" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--69
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"2" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --02
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"3" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--03
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"4" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--04
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --05
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"c" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --c0
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"8" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--a8
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"7" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"7" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--77
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"9" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"e" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--e9
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"c" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--ac
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"b" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--ab
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"6" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--61
-------------------- DONE frame--------------
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '1' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;----------------- Tx
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;--------------------
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait;
end process;
END;
| mit |
peteg944/music-fpga | LED_Matrix_FPGA_Nexys 3/ipcore_dir/pll/example_design/pll_exdes.vhd | 1 | 7140 | -- file: pll_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end pll_exdes;
architecture xilinx of pll_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- When the clock goes out of lock, reset the counters
signal locked_int : std_logic;
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal clk_n : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component pll is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Alias output to internally used signal
LOCKED <= locked_int;
-- When the clock goes out of lock, reset the counters
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : pll
port map
(-- Clock in ports
CLK_IN => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int(1),
CLK_OUT2 => clk_int(2),
-- Status and control signals
RESET => RESET,
LOCKED => locked_int);
gen_outclk_oddr:
for clk_out_pins in 1 to NUM_C generate
begin
clk_n(clk_out_pins) <= not clk(clk_out_pins);
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(clk_out_pins),
C0 => clk(clk_out_pins),
C1 => clk_n(clk_out_pins),
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate;
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
| mit |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/Altera_UP_SD_Signal_Trigger.vhd | 2 | 955 | ---------------------------------------------------------------------------------------
-- This module generates a trigger pulse every time it sees a transition
-- from 0 to 1 on signal i_signal.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_Signal_Trigger is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_signal : in std_logic;
o_trigger : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Signal_Trigger is
-- Local wires
-- REGISTERED
signal local_reg : std_logic;
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
local_reg <= '0';
else
if (rising_edge(i_clock)) then
local_reg <= i_signal;
end if;
end if;
end process;
o_trigger <= '1' when ((local_reg = '0') and (i_signal = '1'))
else '0';
end rtl; | mit |
amerc/TCP3 | ipcore_dir/RxTstFIFO2K/example_design/RxTstFIFO2K_exdes.vhd | 2 | 5090 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RxTstFIFO2K_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RxTstFIFO2K_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end RxTstFIFO2K_exdes;
architecture xilinx of RxTstFIFO2K_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component RxTstFIFO2K is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : RxTstFIFO2K
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit |
peteg944/music-fpga | Experimental/RainbowMatrix and Partial Spectrum/pll.vhd | 3 | 8140 | -- file: pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___192.000______0.000______50.0______102.845_____87.180
-- CLK_OUT2___100.000______0.000______50.0______115.831_____87.180
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_____________100____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end pll;
architecture xilinx of pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "c48,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 12.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 6.250,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 12,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/spacewire/grspwm.vhd | 2 | 3863 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspwm
-- File: grspwm.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: Module to select between grspw and grspw2
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.spacewire.all;
entity grspwm is
generic(
tech : integer range 0 to NTECH := DEFFABTECH;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
sysfreq : integer := 10000; -- spw1
usegen : integer range 0 to 1 := 1; -- spw1
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
netlist : integer range 0 to 1 := 0; -- spw1
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1; -- spw2
memtech : integer range 0 to NTECH := DEFMEMTECH;
spwcore : integer range 1 to 2 := 2 -- select spw core spw1/spw2
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type
);
end entity;
architecture rtl of grspwm is
begin
spw1 : if spwcore = 1 generate
u0 : grspw
generic map(tech, hindex, pindex, paddr, pmask, pirq,
sysfreq, usegen, nsync, rmap, rmapcrc, fifosize1, fifosize2,
rxclkbuftype, rxunaligned, rmapbufs, ft, scantest, techfifo,
netlist, ports, memtech)
port map(rst, clk, txclk, ahbmi, ahbmo, apbi, apbo, swni, swno);
end generate;
spw2 : if spwcore = 2 generate
u0 : grspw2
generic map(tech, hindex, pindex, paddr, pmask, pirq,
nsync, rmap, rmapcrc, fifosize1, fifosize2, rxclkbuftype,
rxunaligned, rmapbufs, ft, scantest, techfifo, ports,
dmachan, memtech)
port map(rst, clk, txclk, ahbmi, ahbmo, apbi, apbo, swni, swno);
end generate;
end architecture;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/ssrctrl_net.vhd | 2 | 12187 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ssrctrl_net
-- file: ssrctrl_net.vhd
-- Description: Wrapper for SSRAM controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ssrctrl_net is
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end entity ssrctrl_net;
architecture rtl of ssrctrl_net is
component ssrctrl_unisim
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
begin
xil : if ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)) and bus16=1 generate
ssrctrlxil: ssrctrl_unisim
port map(
rst => rst,
clk => clk,
n_ahbsi_hsel => n_ahbsi_hsel,
n_ahbsi_haddr => n_ahbsi_haddr,
n_ahbsi_hwrite => n_ahbsi_hwrite,
n_ahbsi_htrans => n_ahbsi_htrans,
n_ahbsi_hsize => n_ahbsi_hsize,
n_ahbsi_hburst => n_ahbsi_hburst,
n_ahbsi_hwdata => n_ahbsi_hwdata,
n_ahbsi_hprot => n_ahbsi_hprot,
n_ahbsi_hready => n_ahbsi_hready,
n_ahbsi_hmaster => n_ahbsi_hmaster,
n_ahbsi_hmastlock => n_ahbsi_hmastlock,
n_ahbsi_hmbsel => n_ahbsi_hmbsel,
n_ahbsi_hcache => n_ahbsi_hcache,
n_ahbsi_hirq => n_ahbsi_hirq,
n_ahbso_hready => n_ahbso_hready,
n_ahbso_hresp => n_ahbso_hresp,
n_ahbso_hrdata => n_ahbso_hrdata,
n_ahbso_hsplit => n_ahbso_hsplit,
n_ahbso_hcache => n_ahbso_hcache,
n_ahbso_hirq => n_ahbso_hirq,
n_apbi_psel => n_apbi_psel,
n_apbi_penable => n_apbi_penable,
n_apbi_paddr => n_apbi_paddr,
n_apbi_pwrite => n_apbi_pwrite,
n_apbi_pwdata => n_apbi_pwdata,
n_apbi_pirq => n_apbi_pirq,
n_apbo_prdata => n_apbo_prdata,
n_apbo_pirq => n_apbo_pirq,
n_sri_data => n_sri_data,
n_sri_brdyn => n_sri_brdyn,
n_sri_bexcn => n_sri_bexcn,
n_sri_writen => n_sri_writen,
n_sri_wrn => n_sri_wrn,
n_sri_bwidth => n_sri_bwidth,
n_sri_sd => n_sri_sd,
n_sri_cb => n_sri_cb,
n_sri_scb => n_sri_scb,
n_sri_edac => n_sri_edac,
n_sro_address => n_sro_address,
n_sro_data => n_sro_data,
n_sro_sddata => n_sro_sddata,
n_sro_ramsn => n_sro_ramsn,
n_sro_ramoen => n_sro_ramoen,
n_sro_ramn => n_sro_ramn,
n_sro_romn => n_sro_romn,
n_sro_mben => n_sro_mben,
n_sro_iosn => n_sro_iosn,
n_sro_romsn => n_sro_romsn,
n_sro_oen => n_sro_oen,
n_sro_writen => n_sro_writen,
n_sro_wrn => n_sro_wrn,
n_sro_bdrive => n_sro_bdrive,
n_sro_vbdrive => n_sro_vbdrive,
n_sro_svbdrive => n_sro_svbdrive,
n_sro_read => n_sro_read,
n_sro_sa => n_sro_sa,
n_sro_cb => n_sro_cb,
n_sro_scb => n_sro_scb,
n_sro_vcdrive => n_sro_vcdrive,
n_sro_svcdrive => n_sro_svcdrive,
n_sro_ce => n_sro_ce);
end generate;
-- pragma translate_off
nonet : if not (((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)))
generate
err : process
begin
assert False report "ERROR : No ssrctrl netlist available for this technology!"
severity Failure;
wait;
end process;
end generate;
nobus16 : if not ( bus16=1 )
generate
err : process
begin
assert False report "ERROR : 16-bit PROM bus option not selected for ssrctrl netlist!"
severity Failure;
wait;
end process;
end generate;
-- pragma translate_on
end architecture; | mit |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/typeTest.vhd | 1 | 3032 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity typeTest is
port (
clk : in std_ulogic;
rst : in std_ulogic;
dataIn : in std_ulogic_vector(7 downto 0);
dataOut : out std_ulogic_vector(7 downto 0)
);
end entity typeTest;
architecture rtl of typeTest is
-- Scalar type declarations
type midway_up is range -5 to 5; -- Integer types using expressions and direction
type midway_down is range 5 downto -5;
type midway_express_up is range (-10 + 2) + 3 to abs(((10/2 * 4 mod 15) ** 1) * (-1));
type states_text is (start, stop, running, waiting); -- Enumerations
type states_char is ('a', 'b', 'c', 'd');
-- Composite type declarations
type word_up is array (0 to 7) of std_ulogic; -- Arrays
type word_down is array (7 downto 0) of std_ulogic;
type word_unlim is array (integer range <>) of std_ulogic;
--type typeAsRange is array (states_text range stop to waiting) of std_ulogic; -- Array that can only be indexed by the values in the index type (i.e. mapping from state to std_ulogic)
type typeAsRangeRev is array (positive range 35 downto 15) of std_ulogic;
--type midway_up2 is range word_up'RANGE; -- Integer types using range attribute (attribute must be from array type)
--type midway_down2 is range word_unlim(0 to 3)'REVERSE_RANGE;
type reg_file is record -- Records
reg1 : word_down;
reg2 : word_up;
reg3 : midway_down;
reg4 : midway_up;
reg5 : word_unlim(31 downto 0); -- Unnamed types
reg6 : natural range 0 to 15;
reg7, reg8 : word_unlim(31 downto -10);
end record;
type words_unlim is array (natural range <>) of std_logic_vector(7 downto 0);
--type nameRange is array (word_up'range) of word_down; -- Range attribute as array bounds
--type nameRangeRev is array (word_up'REVERSE_RANGE) of word_down;
--type nameBounds is array (word_up'right downto word_up'left) of word_down; -- Type attributes as array bounds
--type expressionBounds is array (2+((1+3)+5) downto dataIn'right) of std_logic; -- Expressions as array bounds with reference to non-type name
type recArray is array (3 downto 0) of reg_file; -- Array of record
-- Subtypes
subtype word_up_copy is word_up; -- Type alias
subtype word_unlim_copy is word_unlim;
subtype reg_file_2 is reg_file;
subtype word_lim is word_unlim(5 to 10); -- Simple subset of base type
subtype small_int is integer range -100 to 100;
subtype small_pos is positive range 3 to 17;
subtype states_two1 is states_text range stop to running;
subtype states_two2 is states_text range 1 to 2;
subtype small_int_rev is integer range 100 downto -100; -- Subtype different direction than base type
subtype word_lim_rev is word_unlim(10 downto 5);
subtype states_two1_rev is states_text range running downto stop;
begin
main : process(clk)
begin
if(clk'event and clk = '1')then
if(rst = '1')then
dataOut <= X"00";
else
dataOut <= dataIn;
end if;
end if;
end process;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu3ShadowBootDCE.vhd | 1 | 588892 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
signal dataToCache : std_logic_vector(31 downto 0);
signal triggerCPFault : std_ulogic;
-- Signals used for tracking if a handler fired and which one
signal dfp_trap_vector : std_logic_vector(124 downto 0);
signal or_reduce_1 : std_logic;
signal dfp_delay_start : integer range 0 to 15;
signal dfp_trap_mem : std_logic_vector(dfp_trap_vector'left downto dfp_trap_vector'right);
signal handlerTrap : std_ulogic;
-- Signals that serve as shadow signals for variables used in the pairs
signal V_A_ET_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow : STD_LOGIC_VECTOR(4 downto 3);
signal ICNT_shadow : STD_ULOGIC;
signal EX_OP1_shadow : WORD;
signal V_M_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal DE_REN1_shadow : STD_ULOGIC;
signal DE_INST_shadow : WORD;
signal V_A_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_W_S_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_RESULT6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_E_ALUCIN_shadow : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_A_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_RESULT1DOWNTO0_shadow : std_logic_vector(1 downto 0);
signal EX_SHCNT_shadow : ASI_TYPE;
signal V_M_DCI_SIZE_shadow : OP_TYPE;
signal V_X_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_MEXC_shadow : STD_ULOGIC;
signal TBUFCNTX_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_A_CTRL_WY_shadow : STD_ULOGIC;
signal NPC_shadow : PCTYPE;
signal V_M_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_MULSTART_shadow : STD_ULOGIC;
signal XC_VECTT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_TT_shadow : OP3_TYPE;
signal DSIGN_shadow : STD_ULOGIC;
signal V_E_CTRL_ANNUL_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow : PCTYPE;
signal V_A_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_RFE1_shadow : STD_ULOGIC;
signal V_W_WA_shadow : RFATYPE;
signal V_X_ANNUL_ALL_shadow : STD_ULOGIC;
signal EX_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES_shadow : STD_LOGIC_VECTOR(32 downto 0);
signal VIR_ADDR_shadow : PCTYPE;
signal EX_JUMP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_CWP_shadow : CWPTYPE;
signal V_D_INST0_shadow : std_logic_vector(31 downto 0);
signal V_A_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_DATA1_shadow : std_logic_vector(31 downto 0);
signal VP_PWD_shadow : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA00_shadow : STD_LOGIC;
signal V_M_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_PS_shadow : STD_ULOGIC;
signal V_X_CTRL_TT_shadow : OP3_TYPE;
signal V_D_STEP_shadow : STD_ULOGIC;
signal V_X_CTRL_WICC_shadow : STD_ULOGIC;
signal VIR_ADDR31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_X_RESULT_shadow : WORD;
signal V_D_CNT_shadow : OP_TYPE;
signal XC_VECTT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_W_S_EF_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow : std_logic_vector(4 downto 0);
signal V_X_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_M_NALIGN_shadow : STD_ULOGIC;
signal XC_WREG_shadow : STD_ULOGIC;
signal V_A_RFA2_shadow : RFATYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow : STD_LOGIC_VECTOR(32 downto 13);
signal EX_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_SU_shadow : STD_ULOGIC;
signal V_E_OP2_shadow : WORD;
signal EX_FORCE_A2_shadow : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_OP131_shadow : STD_LOGIC;
signal V_X_DCI_shadow : DC_IN_TYPE;
signal V_E_CTRL_WICC_shadow : STD_ULOGIC;
signal EX_OP13_shadow : STD_LOGIC;
signal V_F_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST_shadow : WORD;
signal V_E_CTRL_LD_shadow : STD_ULOGIC;
signal V_M_SU_shadow : STD_ULOGIC;
signal V_E_SARI_shadow : STD_ULOGIC;
signal V_E_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_PV_shadow : STD_ULOGIC;
signal VDSU_CRDY2_shadow : STD_LOGIC;
signal MUL_OP2_shadow : WORD;
signal XC_EXCEPTION_shadow : STD_ULOGIC;
signal V_E_OP1_shadow : WORD;
signal VP_ERROR_shadow : STD_ULOGIC;
signal V_M_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal MUL_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_M_DCI_shadow : DC_IN_TYPE;
signal EX_OP23_shadow : STD_LOGIC;
signal V_X_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_A_DIVSTART_shadow : STD_ULOGIC;
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal VDSU_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_CTRL_CNT_shadow : OP_TYPE;
signal V_E_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_RFE2_shadow : STD_ULOGIC;
signal V_E_OP13_shadow : STD_LOGIC;
signal V_A_CWP_shadow : CWPTYPE;
signal ME_SIZE_shadow : OP_TYPE;
signal V_X_MAC_shadow : STD_ULOGIC;
signal V_M_CTRL_INST_shadow : WORD;
signal VIR_ADDR31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST20_shadow : STD_LOGIC;
signal DE_REN2_shadow : STD_ULOGIC;
signal V_E_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_MAC_shadow : STD_ULOGIC;
signal V_X_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal EX_ADD_RES3_shadow : STD_LOGIC;
signal V_X_CTRL_INST_shadow : WORD;
signal V_M_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow : OP_TYPE;
signal V_M_CTRL_ANNUL_shadow : STD_ULOGIC;
signal DE_INST19_shadow : STD_LOGIC;
signal XC_HALT_shadow : STD_ULOGIC;
signal V_E_OP231_shadow : STD_LOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_M_CTRL_WICC_shadow : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow : STD_ULOGIC;
signal V_W_S_S_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CWP_shadow : CWPTYPE;
signal V_A_STEP_shadow : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_CTRL_TRAP_shadow : STD_ULOGIC;
signal NPC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_INTACK_shadow : STD_ULOGIC;
signal SIDLE_shadow : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_DATA03_shadow : STD_LOGIC;
signal V_A_CTRL_INST19_shadow : STD_LOGIC;
signal V_W_S_SVT_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_LADDR_shadow : OP_TYPE;
signal V_W_S_DWT_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_TBA_shadow : STD_LOGIC_VECTOR(19 downto 0);
signal XC_WADDR6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_M_MUL_shadow : STD_ULOGIC;
signal V_E_SU_shadow : STD_ULOGIC;
signal V_M_Y31_shadow : STD_LOGIC;
signal V_E_OP23_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal DE_RADDR17DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_X_DEBUG_shadow : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_CTRL_WREG_shadow : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow : STD_LOGIC;
signal V_D_MEXC_shadow : STD_ULOGIC;
signal V_W_RESULT_shadow : WORD;
signal VFPI_DBG_ENABLE_shadow : STD_ULOGIC;
signal EX_OP131_shadow : STD_LOGIC;
signal V_D_INST1_shadow : std_logic_vector(31 downto 0);
signal V_W_EXCEPT_shadow : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal ME_LADDR_shadow : OP_TYPE;
signal V_X_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_CTRL_RETT_shadow : STD_ULOGIC;
signal XC_WADDR7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_M_MAC_shadow : STD_ULOGIC;
signal V_D_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal VIR_ADDR3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_D_CWP_shadow : CWPTYPE;
signal DE_INST20_shadow : STD_LOGIC;
signal V_D_ANNUL_shadow : STD_ULOGIC;
signal EX_OP2_shadow : WORD;
signal EX_SARI_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DCI_SIZE_shadow : OP_TYPE;
signal V_M_Y_shadow : WORD;
signal V_X_CTRL_PC_shadow : PCTYPE;
signal V_X_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal V_A_CTRL_PC_shadow : PCTYPE;
signal V_A_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_INST20_shadow : STD_LOGIC;
signal V_E_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA0_shadow : std_logic_vector(31 downto 0);
signal V_E_CTRL_INST19_shadow : STD_LOGIC;
signal ME_SIGNED_shadow : STD_ULOGIC;
signal V_W_WREG_shadow : STD_ULOGIC;
signal V_D_PC_shadow : PCTYPE;
signal VFPI_D_ANNUL_shadow : STD_ULOGIC;
signal DE_RADDR27DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC_shadow : PCTYPE;
signal V_X_DATA031_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_X_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT_shadow : OP3_TYPE;
signal V_X_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_INST24_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_NERROR_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_W_S_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_F_BRANCH_shadow : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow : STD_ULOGIC;
signal V_A_CTRL_LD_shadow : STD_ULOGIC;
signal V_A_CTRL_TT_shadow : OP3_TYPE;
signal V_M_CTRL_LD_shadow : STD_ULOGIC;
signal V_E_SHCNT_shadow : ASI_TYPE;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST_shadow : WORD;
signal V_A_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal VIR_PWD_shadow : STD_ULOGIC;
signal XC_RESULT_shadow : WORD;
signal V_A_RFA1_shadow : RFATYPE;
signal V_E_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal ME_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal DE_INST24_shadow : STD_LOGIC;
signal XC_TRAP_shadow : STD_ULOGIC;
signal VDSU_TBUFCNT_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal XC_TRAP_ADDRESS_shadow : PCTYPE;
-- Intermediate value holding signal declarations
signal V_E_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal V_M_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_RFA1_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_4 : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_2 : STD_LOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal V_X_DATA00_shadow_intermed_3 : STD_LOGIC;
signal RIN_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WICC_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_3 : STD_ULOGIC;
signal RPIN_PWD_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal DE_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DBGI_DADDR9DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(9 downto 2);
signal R_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_STEP_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_7 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_1 : STD_LOGIC;
signal V_D_INST0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_YMSB_intermed_1 : STD_ULOGIC;
signal R_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_X_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_F_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_DATA04DOWNTO0_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal R_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal R_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal RIN_M_DCI_LOCK_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal R_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_ET_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal DBGI_STEP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_X_LADDR_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_WA_intermed_1 : std_logic_vector(7 downto 0);
signal V_D_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_2 : STD_LOGIC;
signal V_M_RESULT1DOWNTO0_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_DATA03_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_intermed_1 : DC_IN_TYPE;
signal DSUIN_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_D_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal ICO_MEXC_intermed_1 : STD_ULOGIC;
signal R_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_DCI_SIZE_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_W_S_S_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal R_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_S_ET_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal VIR_ADDR31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_8 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_X_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal DCO_DATA00_intermed_2 : STD_LOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_SU_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal R_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_X_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_X_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal IR_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_X_DATA1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal ICO_MEXC_intermed_3 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal R_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_WICC_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_5 : STD_ULOGIC;
signal RIN_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal R_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_M_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_7 : std_logic_vector(31 downto 4);
signal RIN_E_OP13_intermed_1 : STD_LOGIC;
signal RIN_A_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_OP2_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal R_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_M_Y31_intermed_2 : STD_LOGIC;
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal XC_VECTT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_4 : STD_ULOGIC;
signal RIN_W_S_TBA_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal V_D_INST1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DATA031_intermed_1 : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 13);
signal R_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_X_DATA031_intermed_1 : STD_LOGIC;
signal R_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_SARI_intermed_1 : STD_ULOGIC;
signal R_M_Y31_intermed_1 : STD_LOGIC;
signal IR_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_W_S_S_shadow_intermed_2 : STD_ULOGIC;
signal DE_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal V_A_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow_intermed_2 : std_logic_vector(4 downto 0);
signal R_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal DCO_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_X_DATA0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_E_OP131_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST19_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal V_X_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_RFE2_shadow_intermed_1 : STD_ULOGIC;
signal V_M_Y_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal DE_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_MEXC_shadow_intermed_4 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_W_S_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal R_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal IR_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal R_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow_intermed_1 : STD_ULOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_X_DATA04DOWNTO0_intermed_3 : std_logic_vector(4 downto 0);
signal V_X_NERROR_shadow_intermed_1 : STD_ULOGIC;
signal V_A_RFE1_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal ICO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal VIR_ADDR_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_W_S_DWT_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_X_NERROR_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_5 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal IRIN_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal V_X_DATA00_shadow_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_M_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal R_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_DEBUG_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PV_intermed_4 : STD_ULOGIC;
signal R_E_MAC_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal IR_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_JMPL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal RIN_M_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_X_DATA04DOWNTO0_shadow_intermed_3 : std_logic_vector(4 downto 0);
signal RIN_W_S_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_DATA031_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_3 : STD_LOGIC;
signal DCO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_X_DATA0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 : std_logic_vector(3 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RPIN_ERROR_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_W_S_S_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal V_A_RFA1_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_SU_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal V_A_CTRL_shadow_intermed_3 : PIPELINE_CTRL_TYPE;
signal R_D_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_1 : STD_LOGIC;
signal V_A_DIVSTART_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_4 : STD_ULOGIC;
signal RIN_W_S_PS_intermed_1 : STD_ULOGIC;
signal R_D_MEXC_intermed_3 : STD_ULOGIC;
signal RIN_A_RFA2_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_W_S_SVT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_4 : std_logic_vector(6 downto 0);
signal RIN_E_OP23_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_D_MEXC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_7 : std_logic_vector(31 downto 4);
signal R_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_8 : std_logic_vector(31 downto 12);
signal VP_PWD_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_NALIGN_intermed_1 : STD_ULOGIC;
signal RP_ERROR_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_W_S_TBA_shadow_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal R_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_JMPL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_SU_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_RFE2_intermed_1 : STD_ULOGIC;
signal RIN_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_M_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_E_MAC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal IRIN_ADDR_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_CWP_shadow_intermed_2 : std_logic_vector(2 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_A_MULSTART_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_M_DCI_SIGNED_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal IRIN_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal V_M_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_DCI_SIGNED_shadow_intermed_2 : STD_ULOGIC;
signal R_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST19_intermed_3 : STD_LOGIC;
signal V_E_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_X_DATA1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_CWP_intermed_2 : std_logic_vector(2 downto 0);
signal R_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_A_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal DCO_DATA031_intermed_2 : STD_LOGIC;
signal R_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_E_YMSB_shadow_intermed_1 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_M_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DE_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal VIR_ADDR3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_3 : PIPELINE_CTRL_TYPE;
signal RIN_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_A_DIVSTART_intermed_1 : STD_ULOGIC;
signal VIR_ADDR31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_X_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal DSUR_CRDY2_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST_intermed_4 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal DE_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_MULSTART_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_M_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 3);
signal V_A_CTRL_PV_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_WREG_shadow_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_W_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal R_D_ANNUL_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_E_SARI_shadow_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal R_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_M_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal DSUIN_CRDY2_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_M_DCI_SIZE_intermed_2 : std_logic_vector(1 downto 0);
signal DE_INST19_shadow_intermed_3 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_ANNUL_shadow_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal IRIN_PWD_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_5 : STD_ULOGIC;
signal RIN_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TRAP_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal R_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_DATA03_intermed_1 : STD_LOGIC;
signal R_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal R_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_X_MAC_intermed_1 : STD_ULOGIC;
signal V_E_SHCNT_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_OP23_shadow_intermed_1 : STD_LOGIC;
signal V_D_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal R_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_W_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_LADDR_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_5 : std_logic_vector(31 downto 2);
signal XC_VECTT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal V_D_STEP_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal DE_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_5 : STD_ULOGIC;
signal RIN_X_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_F_BRANCH_intermed_1 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_DATA00_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_JMPL_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal DSUR_CRDY2_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_M_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA00_intermed_3 : STD_LOGIC;
signal R_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_OP131_intermed_1 : STD_LOGIC;
signal R_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal DE_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_ET_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST20_intermed_3 : STD_LOGIC;
signal RIN_W_EXCEPT_intermed_1 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_2 : STD_LOGIC;
signal R_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal R_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal VIR_ADDR31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_M_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal VIR_ADDR3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_ANNUL_shadow_intermed_3 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal R_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal R_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_E_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST24_intermed_3 : STD_LOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal DE_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PV_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal R_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_MAC_intermed_1 : STD_ULOGIC;
signal R_X_DATA00_intermed_2 : STD_LOGIC;
signal RIN_E_MAC_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_INTACK_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_ANNUL_intermed_5 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_X_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal DE_INST20_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal IR_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_ALUCIN_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_E_OP13_shadow_intermed_1 : STD_LOGIC;
signal V_A_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_6 : std_logic_vector(3 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_7 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal R_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal R_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_WREG_intermed_4 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal R_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal IRIN_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_OP1_intermed_1 : std_logic_vector(31 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal DE_INST20_shadow_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_E_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_M_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_INTACK_intermed_1 : STD_ULOGIC;
signal RIN_E_OP231_intermed_1 : STD_LOGIC;
signal RIN_X_DATA031_intermed_3 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_F_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_ET_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_3 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal ICO_MEXC_intermed_2 : STD_ULOGIC;
signal V_X_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_STEP_intermed_1 : STD_ULOGIC;
signal V_E_ALUCIN_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_M_MUL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal R_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_D_INST0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DCO_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO12_shadow_intermed_8 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WY_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal V_M_DCI_shadow_intermed_1 : DC_IN_TYPE;
signal V_M_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal RIN_D_MEXC_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DSUIN_TBUFCNT_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 : std_logic_vector(6 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal V_D_INST1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DEBUG_intermed_1 : STD_ULOGIC;
signal RIN_M_Y_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_SHCNT_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal RIN_D_ANNUL_intermed_2 : STD_ULOGIC;
signal ICO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_MEXC_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal DSUIN_CRDY2_intermed_2 : STD_LOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_DATA031_shadow_intermed_1 : STD_LOGIC;
signal RIN_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_D_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal DCO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_S_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_LD_shadow_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal V_E_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_SU_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_F_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO2_shadow_intermed_8 : std_logic_vector(31 downto 2);
signal V_D_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal R_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_M_RESULT1DOWNTO0_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_5 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal V_X_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_5 : std_logic_vector(1 downto 0);
signal R_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_W_S_S_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_A_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal R_X_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_intermed_1 : DC_IN_TYPE;
signal R_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_EF_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_LD_intermed_3 : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal V_F_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 : STD_LOGIC_VECTOR(30 downto 11);
signal V_X_ANNUL_ALL_shadow_intermed_3 : STD_ULOGIC;
signal V_F_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal R_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RETT_intermed_3 : STD_ULOGIC;
signal R_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 3);
signal V_E_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_E_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal V_A_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_SU_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_OP231_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RPIN_ERROR_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_D_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal DCO_DATA00_intermed_1 : STD_LOGIC;
signal V_M_Y31_shadow_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal DCO_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_DATA03_shadow_intermed_1 : STD_LOGIC;
signal V_E_OP1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_2 : STD_ULOGIC;
signal V_M_Y31_shadow_intermed_2 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal R_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_RFE1_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_M_MAC_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal R_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_DATA00_intermed_1 : STD_LOGIC;
signal V_X_ANNUL_ALL_shadow_intermed_1 : STD_ULOGIC;
signal R_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_F_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_W_S_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_W_S_PS_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal R_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_MAC_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_ICC_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_MAC_intermed_1 : STD_ULOGIC;
signal RIN_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal R_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 13);
signal RIN_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal IR_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_2 : STD_LOGIC;
signal RIN_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_E_OP2_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp, triggercpfault, handlerTrap)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap or handlerTrap;
v.x.nerror := rp.error;
if(handlerTrap = '1')then
xc_vectt := "00" & TT_WATCH;
elsif(triggerCPFault = '1')then
xc_vectt := "00" & TT_CPDIS;
xc_trap := '1';
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
-- Assignments to be moved with variables
-- These assignments must be moved to process COMB/
V_A_ET_shadow <= V.A.ET;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 4 DOWNTO 3 );
ICNT_shadow <= ICNT;
EX_OP1_shadow <= EX_OP1;
V_M_CTRL_PC_shadow <= V.M.CTRL.PC;
V_E_CTRL_PC3DOWNTO2_shadow <= V.E.CTRL.PC( 3 DOWNTO 2 );
DE_REN1_shadow <= DE_REN1;
DE_INST_shadow <= DE_INST;
V_A_CTRL_CNT_shadow <= V.A.CTRL.CNT;
V_F_PC3DOWNTO2_shadow <= V.F.PC( 3 DOWNTO 2 );
V_W_S_TT_shadow <= V.W.S.TT;
V_X_RESULT6DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 );
EX_JUMP_ADDRESS3DOWNTO2_shadow <= EX_JUMP_ADDRESS( 3 DOWNTO 2 );
V_E_ALUCIN_shadow <= V.E.ALUCIN;
V_D_PC3DOWNTO2_shadow <= V.D.PC( 3 DOWNTO 2 );
V_A_CTRL_PV_shadow <= V.A.CTRL.PV;
V_E_CTRL_shadow <= V.E.CTRL;
V_M_CTRL_shadow <= V.M.CTRL;
V_M_RESULT1DOWNTO0_shadow <= V.M.RESULT ( 1 DOWNTO 0 );
EX_SHCNT_shadow <= EX_SHCNT;
V_M_DCI_SIZE_shadow <= V.M.DCI.SIZE;
V_X_CTRL_ANNUL_shadow <= V.X.CTRL.ANNUL;
V_X_MEXC_shadow <= V.X.MEXC;
TBUFCNTX_shadow <= TBUFCNTX;
V_A_CTRL_WY_shadow <= V.A.CTRL.WY;
NPC_shadow <= NPC;
V_M_CTRL_TT3DOWNTO0_shadow <= V.M.CTRL.TT( 3 DOWNTO 0 );
V_A_MULSTART_shadow <= V.A.MULSTART;
XC_VECTT3DOWNTO0_shadow <= XC_VECTT( 3 DOWNTO 0 );
V_E_CTRL_TT_shadow <= V.E.CTRL.TT;
DSIGN_shadow <= DSIGN;
V_E_CTRL_ANNUL_shadow <= V.E.CTRL.ANNUL;
EX_JUMP_ADDRESS_shadow <= EX_JUMP_ADDRESS;
V_A_CTRL_PC31DOWNTO12_shadow <= V.A.CTRL.PC( 31 DOWNTO 12 );
V_A_RFE1_shadow <= V.A.RFE1;
V_W_WA_shadow <= V.W.WA;
V_X_ANNUL_ALL_shadow <= V.X.ANNUL_ALL;
EX_YMSB_shadow <= EX_YMSB;
EX_ADD_RES_shadow <= EX_ADD_RES;
VIR_ADDR_shadow <= VIR.ADDR;
EX_JUMP_ADDRESS31DOWNTO12_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 12 );
V_W_S_CWP_shadow <= V.W.S.CWP;
V_D_INST0_shadow <= V.D.INST ( 0 );
V_A_CTRL_ANNUL_shadow <= V.A.CTRL.ANNUL;
V_X_DATA1_shadow <= V.X.DATA ( 1 );
VP_PWD_shadow <= VP.PWD;
V_M_CTRL_RD6DOWNTO0_shadow <= V.M.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA00_shadow <= V.X.DATA ( 0 )( 0 );
V_M_CTRL_RETT_shadow <= V.M.CTRL.RETT;
V_X_CTRL_RETT_shadow <= V.X.CTRL.RETT;
V_X_CTRL_PC31DOWNTO12_shadow <= V.X.CTRL.PC( 31 DOWNTO 12 );
V_W_S_PS_shadow <= V.W.S.PS;
V_X_CTRL_TT_shadow <= V.X.CTRL.TT;
V_D_STEP_shadow <= V.D.STEP;
V_X_CTRL_WICC_shadow <= V.X.CTRL.WICC;
VIR_ADDR31DOWNTO2_shadow <= VIR.ADDR( 31 DOWNTO 2 );
V_M_CTRL_RD7DOWNTO0_shadow <= V.M.CTRL.RD ( 7 DOWNTO 0 );
V_X_RESULT_shadow <= V.X.RESULT;
V_D_CNT_shadow <= V.D.CNT;
XC_VECTT_shadow <= XC_VECTT;
EX_ADD_RES32DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 );
V_W_S_EF_shadow <= V.W.S.EF;
V_A_CTRL_PC31DOWNTO2_shadow <= V.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA04DOWNTO0_shadow <= V.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DCI_SIGNED_shadow <= V.X.DCI.SIGNED;
V_M_NALIGN_shadow <= V.M.NALIGN;
XC_WREG_shadow <= XC_WREG;
V_A_RFA2_shadow <= V.A.RFA2;
V_E_CTRL_PC31DOWNTO12_shadow <= V.E.CTRL.PC( 31 DOWNTO 12 );
EX_ADD_RES32DOWNTO332DOWNTO13_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 13 );
EX_OP231_shadow <= EX_OP2( 31 );
XC_TRAP_ADDRESS31DOWNTO4_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 4 );
V_X_ICC_shadow <= V.X.ICC;
V_A_SU_shadow <= V.A.SU;
V_E_OP2_shadow <= V.E.OP2;
EX_FORCE_A2_shadow <= EX_FORCE_A2;
V_E_CTRL_PC31DOWNTO2_shadow <= V.E.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO4_shadow <= V.E.CTRL.PC( 31 DOWNTO 4 );
V_E_OP131_shadow <= V.E.OP1( 31 );
V_X_DCI_shadow <= V.X.DCI;
V_E_CTRL_WICC_shadow <= V.E.CTRL.WICC;
EX_OP13_shadow <= EX_OP1( 3 );
V_F_PC31DOWNTO12_shadow <= V.F.PC( 31 DOWNTO 12 );
V_E_CTRL_INST_shadow <= V.E.CTRL.INST;
V_E_CTRL_LD_shadow <= V.E.CTRL.LD;
V_M_SU_shadow <= V.M.SU;
V_E_SARI_shadow <= V.E.SARI;
V_E_ET_shadow <= V.E.ET;
V_M_CTRL_PV_shadow <= V.M.CTRL.PV;
VDSU_CRDY2_shadow <= VDSU.CRDY ( 2 );
MUL_OP2_shadow <= MUL_OP2;
XC_EXCEPTION_shadow <= XC_EXCEPTION;
V_E_OP1_shadow <= V.E.OP1;
VP_ERROR_shadow <= VP.ERROR;
V_M_DCI_SIGNED_shadow <= V.M.DCI.SIGNED;
V_D_PC31DOWNTO12_shadow <= V.D.PC( 31 DOWNTO 12 );
MUL_OP231_shadow <= MUL_OP2 ( 31 );
XC_TRAP_ADDRESS31DOWNTO2_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow <= V.M.CTRL.PC( 3 DOWNTO 2 );
V_M_DCI_shadow <= V.M.DCI;
EX_OP23_shadow <= EX_OP2( 3 );
V_X_CTRL_RD6DOWNTO0_shadow <= V.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_TRAP_shadow <= V.X.CTRL.TRAP;
V_A_DIVSTART_shadow <= V.A.DIVSTART;
V_X_RESULT6DOWNTO03DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
VDSU_TT_shadow <= VDSU.TT;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 5 );
V_X_CTRL_CNT_shadow <= V.X.CTRL.CNT;
V_E_YMSB_shadow <= V.E.YMSB;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 30 DOWNTO 11 );
V_A_RFE2_shadow <= V.A.RFE2;
V_E_OP13_shadow <= V.E.OP1( 3 );
V_A_CWP_shadow <= V.A.CWP;
ME_SIZE_shadow <= ME_SIZE;
V_X_MAC_shadow <= V.X.MAC;
V_M_CTRL_INST_shadow <= V.M.CTRL.INST;
VIR_ADDR31DOWNTO4_shadow <= VIR.ADDR( 31 DOWNTO 4 );
V_A_CTRL_INST20_shadow <= V.A.CTRL.INST( 20 );
DE_REN2_shadow <= DE_REN2;
V_E_CTRL_PV_shadow <= V.E.CTRL.PV;
V_E_MAC_shadow <= V.E.MAC;
V_X_CTRL_TT3DOWNTO0_shadow <= V.X.CTRL.TT( 3 DOWNTO 0 );
EX_ADD_RES3_shadow <= EX_ADD_RES ( 3 );
V_X_CTRL_INST_shadow <= V.X.CTRL.INST;
V_M_CTRL_PC31DOWNTO2_shadow <= V.M.CTRL.PC( 31 DOWNTO 2 );
V_W_S_ET_shadow <= V.W.S.ET;
V_M_CTRL_CNT_shadow <= V.M.CTRL.CNT;
V_M_CTRL_ANNUL_shadow <= V.M.CTRL.ANNUL;
DE_INST19_shadow <= DE_INST( 19 );
XC_HALT_shadow <= XC_HALT;
V_E_OP231_shadow <= V.E.OP2( 31 );
V_A_CTRL_PC3DOWNTO2_shadow <= V.A.CTRL.PC( 3 DOWNTO 2 );
VIR_ADDR31DOWNTO12_shadow <= VIR.ADDR( 31 DOWNTO 12 );
V_M_CTRL_WICC_shadow <= V.M.CTRL.WICC;
V_M_CTRL_WREG_shadow <= V.M.CTRL.WREG;
V_W_S_S_shadow <= V.W.S.S;
V_F_PC31DOWNTO2_shadow <= V.F.PC( 31 DOWNTO 2 );
V_E_CWP_shadow <= V.E.CWP;
V_A_STEP_shadow <= V.A.STEP;
V_A_CTRL_TT3DOWNTO0_shadow <= V.A.CTRL.TT( 3 DOWNTO 0 );
V_A_CTRL_TRAP_shadow <= V.A.CTRL.TRAP;
NPC31DOWNTO2_shadow <= NPC ( 31 DOWNTO 2 );
V_M_CTRL_TRAP_shadow <= V.M.CTRL.TRAP;
V_D_PC31DOWNTO4_shadow <= V.D.PC( 31 DOWNTO 4 );
V_X_INTACK_shadow <= V.X.INTACK;
SIDLE_shadow <= SIDLE;
V_A_CTRL_RETT_shadow <= V.A.CTRL.RETT;
V_X_DATA03_shadow <= V.X.DATA ( 0 )( 3 );
V_A_CTRL_INST19_shadow <= V.A.CTRL.INST( 19 );
V_W_S_SVT_shadow <= V.W.S.SVT;
V_A_CTRL_PC31DOWNTO4_shadow <= V.A.CTRL.PC( 31 DOWNTO 4 );
V_X_LADDR_shadow <= V.X.LADDR;
V_W_S_DWT_shadow <= V.W.S.DWT;
EX_JUMP_ADDRESS31DOWNTO2_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 2 );
V_W_S_TBA_shadow <= V.W.S.TBA;
XC_WADDR6DOWNTO0_shadow <= XC_WADDR ( 6 DOWNTO 0 );
V_M_MUL_shadow <= V.M.MUL;
V_E_SU_shadow <= V.E.SU;
V_M_Y31_shadow <= V.M.Y ( 31 );
V_E_OP23_shadow <= V.E.OP2( 3 );
V_M_CTRL_PC31DOWNTO4_shadow <= V.M.CTRL.PC( 31 DOWNTO 4 );
DE_RADDR17DOWNTO0_shadow <= DE_RADDR1 ( 7 DOWNTO 0 );
V_X_CTRL_PC31DOWNTO2_shadow <= V.X.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_TRAP_shadow <= V.E.CTRL.TRAP;
V_X_DEBUG_shadow <= V.X.DEBUG;
V_M_DCI_LOCK_shadow <= V.M.DCI.LOCK;
V_X_CTRL_PC3DOWNTO2_shadow <= V.X.CTRL.PC( 3 DOWNTO 2 );
V_X_CTRL_WREG_shadow <= V.X.CTRL.WREG;
V_E_CTRL_INST24_shadow <= V.E.CTRL.INST( 24 );
V_D_MEXC_shadow <= V.D.MEXC;
V_W_RESULT_shadow <= V.W.RESULT;
VFPI_DBG_ENABLE_shadow <= VFPI.DBG.ENABLE;
EX_OP131_shadow <= EX_OP1 ( 31 );
V_D_INST1_shadow <= V.D.INST ( 1 );
V_W_EXCEPT_shadow <= V.W.EXCEPT;
V_E_CTRL_TT3DOWNTO0_shadow <= V.E.CTRL.TT( 3 DOWNTO 0 );
ME_LADDR_shadow <= ME_LADDR;
V_X_CTRL_PC31DOWNTO4_shadow <= V.X.CTRL.PC( 31 DOWNTO 4 );
V_E_CTRL_RETT_shadow <= V.E.CTRL.RETT;
XC_WADDR7DOWNTO0_shadow <= XC_WADDR ( 7 DOWNTO 0 );
V_X_CTRL_PV_shadow <= V.X.CTRL.PV;
V_E_CTRL_RD6DOWNTO0_shadow <= V.E.CTRL.RD( 6 DOWNTO 0 );
V_M_MAC_shadow <= V.M.MAC;
V_D_SET_shadow <= V.D.SET;
VIR_ADDR3DOWNTO2_shadow <= VIR.ADDR( 3 DOWNTO 2 );
V_D_CWP_shadow <= V.D.CWP;
DE_INST20_shadow <= DE_INST( 20 );
V_D_ANNUL_shadow <= V.D.ANNUL;
EX_OP2_shadow <= EX_OP2;
EX_SARI_shadow <= EX_SARI;
V_D_PC31DOWNTO2_shadow <= V.D.PC( 31 DOWNTO 2 );
V_X_DCI_SIZE_shadow <= V.X.DCI.SIZE;
V_M_Y_shadow <= V.M.Y;
V_X_CTRL_PC_shadow <= V.X.CTRL.PC;
V_X_SET_shadow <= V.X.SET;
V_A_CTRL_PC_shadow <= V.A.CTRL.PC;
V_A_JMPL_shadow <= V.A.JMPL;
V_E_CTRL_PC_shadow <= V.E.CTRL.PC;
V_E_CTRL_INST20_shadow <= V.E.CTRL.INST( 20 );
V_E_CTRL_WREG_shadow <= V.E.CTRL.WREG;
V_A_CTRL_WREG_shadow <= V.A.CTRL.WREG;
V_A_CTRL_shadow <= V.A.CTRL;
V_A_CTRL_RD6DOWNTO0_shadow <= V.A.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA0_shadow <= V.X.DATA ( 0 );
V_E_CTRL_INST19_shadow <= V.E.CTRL.INST( 19 );
ME_SIGNED_shadow <= ME_SIGNED;
V_W_WREG_shadow <= V.W.WREG;
V_D_PC_shadow <= V.D.PC;
VFPI_D_ANNUL_shadow <= VFPI.D.ANNUL;
DE_RADDR27DOWNTO0_shadow <= DE_RADDR2 ( 7 DOWNTO 0 );
V_E_CTRL_CNT_shadow <= V.E.CTRL.CNT;
V_F_PC_shadow <= V.F.PC;
V_X_DATA031_shadow <= V.X.DATA ( 0 )( 31 );
V_M_CTRL_PC31DOWNTO12_shadow <= V.M.CTRL.PC( 31 DOWNTO 12 );
V_X_CTRL_RD7DOWNTO0_shadow <= V.X.CTRL.RD ( 7 DOWNTO 0 );
V_M_CTRL_TT_shadow <= V.M.CTRL.TT;
V_X_CTRL_shadow <= V.X.CTRL;
V_A_CTRL_INST24_shadow <= V.A.CTRL.INST( 24 );
XC_TRAP_ADDRESS3DOWNTO2_shadow <= XC_TRAP_ADDRESS( 3 DOWNTO 2 );
V_X_NERROR_shadow <= V.X.NERROR;
V_F_PC31DOWNTO4_shadow <= V.F.PC( 31 DOWNTO 4 );
V_W_S_TT3DOWNTO0_shadow <= V.W.S.TT( 3 DOWNTO 0 );
EX_JUMP_ADDRESS31DOWNTO4_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 4 );
EX_ADD_RES32DOWNTO332DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 3 );
V_F_BRANCH_shadow <= V.F.BRANCH;
V_A_CTRL_WICC_shadow <= V.A.CTRL.WICC;
V_A_CTRL_LD_shadow <= V.A.CTRL.LD;
V_A_CTRL_TT_shadow <= V.A.CTRL.TT;
V_M_CTRL_LD_shadow <= V.M.CTRL.LD;
V_E_SHCNT_shadow <= V.E.SHCNT;
XC_TRAP_ADDRESS31DOWNTO12_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 12 );
V_A_CTRL_INST_shadow <= V.A.CTRL.INST;
V_A_CTRL_RD7DOWNTO0_shadow <= V.A.CTRL.RD ( 7 DOWNTO 0 );
VIR_PWD_shadow <= VIR.PWD;
XC_RESULT_shadow <= XC_RESULT;
V_A_RFA1_shadow <= V.A.RFA1;
V_E_JMPL_shadow <= V.E.JMPL;
V_E_CTRL_RD7DOWNTO0_shadow <= V.E.CTRL.RD ( 7 DOWNTO 0 );
ME_ICC_shadow <= ME_ICC;
DE_INST24_shadow <= DE_INST( 24 );
XC_TRAP_shadow <= XC_TRAP;
VDSU_TBUFCNT_shadow <= VDSU.TBUFCNT;
XC_TRAP_ADDRESS_shadow <= XC_TRAP_ADDRESS;
end process;
dfp_delay : process(clk) begin
if(clk'event and clk = '1')then
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
V_W_S_S_shadow_intermed_2 <= V_W_S_S_shadow_intermed_1;
V_W_S_PS_shadow_intermed_1 <= V_W_S_PS_shadow;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
R_W_S_S_intermed_1 <= R.W.S.S;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_S_intermed_2 <= RIN_W_S_S_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_X_RESULT6DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_X_DATA0_intermed_2 <= R_X_DATA0_intermed_1;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_3 <= R_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
R_A_CTRL_TT3DOWNTO0_intermed_5 <= R_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_6 <= RIN_A_CTRL_TT3DOWNTO0_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_W_S_TT3DOWNTO0_intermed_2 <= R_W_S_TT3DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_4 <= R_E_CTRL_TT3DOWNTO0_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_M_CTRL_TT3DOWNTO0_intermed_4 <= RIN_M_CTRL_TT3DOWNTO0_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_X_CTRL_TT3DOWNTO0_intermed_3 <= RIN_X_CTRL_TT3DOWNTO0_intermed_2;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
R_X_CTRL_TT3DOWNTO0_intermed_2 <= R_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
RIN_E_CTRL_TT3DOWNTO0_intermed_5 <= RIN_E_CTRL_TT3DOWNTO0_intermed_4;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_2 <= XC_VECTT3DOWNTO0_shadow_intermed_1;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_M_DCI_LOCK_intermed_1 <= RIN.M.DCI.LOCK;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_M_DCI_LOCK_shadow_intermed_1 <= V_M_DCI_LOCK_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
DCO_DATA031_intermed_2 <= DCO_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_3 <= DE_INST19_shadow_intermed_2;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_E_CTRL_INST19_intermed_2 <= R_E_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_E_CTRL_INST20_intermed_2 <= R_E_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_3 <= DE_INST20_shadow_intermed_2;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
DCO_DATA00_intermed_2 <= DCO_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_2 <= DCO_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_4 <= R_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_5 <= RIN_M_CTRL_PC31DOWNTO2_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_7 <= RIN_A_CTRL_PC31DOWNTO2_intermed_6;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_6 <= R_A_CTRL_PC31DOWNTO2_intermed_5;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_X_CTRL_PC31DOWNTO2_intermed_3 <= R_X_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_D_PC31DOWNTO2_shadow_intermed_8 <= V_D_PC31DOWNTO2_shadow_intermed_7;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
RIN_D_PC31DOWNTO2_intermed_8 <= RIN_D_PC31DOWNTO2_intermed_7;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_CTRL_PC31DOWNTO2_intermed_4 <= RIN_X_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_3 <= IRIN_ADDR31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_5 <= R_E_CTRL_PC31DOWNTO2_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_D_PC31DOWNTO2_intermed_7 <= R_D_PC31DOWNTO2_intermed_6;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_2 <= IR_ADDR31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_6 <= RIN_E_CTRL_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
R_F_PC31DOWNTO2_intermed_2 <= R_F_PC31DOWNTO2_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
VIR_ADDR31DOWNTO2_shadow_intermed_3 <= VIR_ADDR31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
V_A_MULSTART_shadow_intermed_1 <= V_A_MULSTART_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_MULSTART_intermed_1 <= RIN.A.MULSTART;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_3 <= DE_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_E_CTRL_INST24_intermed_2 <= R_E_CTRL_INST24_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_DIVSTART_intermed_1 <= RIN.A.DIVSTART;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_DIVSTART_shadow_intermed_1 <= V_A_DIVSTART_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
RIN_M_Y_intermed_1 <= RIN.M.Y;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y_shadow_intermed_1 <= V_M_Y_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_M_Y31_intermed_1 <= R.M.Y( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
R_M_Y31_intermed_2 <= R_M_Y31_intermed_1;
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
DSUR_CRDY2_intermed_2 <= DSUR_CRDY2_intermed_1;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
VP_ERROR_shadow_intermed_2 <= VP_ERROR_shadow_intermed_1;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RPIN_ERROR_intermed_2 <= RPIN_ERROR_intermed_1;
V_X_NERROR_shadow_intermed_1 <= V_X_NERROR_shadow;
RP_ERROR_intermed_1 <= RP.ERROR;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
DCO_DATA1_intermed_1 <= DCO.DATA ( 1 );
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
R_X_DATA1_intermed_2 <= R_X_DATA1_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_A_CTRL_PC31DOWNTO12_intermed_7 <= RIN_A_CTRL_PC31DOWNTO12_intermed_6;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_6 <= RIN_E_CTRL_PC31DOWNTO12_intermed_5;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_4 <= R_M_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_3 <= IRIN_ADDR31DOWNTO12_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
R_F_PC31DOWNTO12_intermed_2 <= R_F_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
RIN_M_CTRL_PC31DOWNTO12_intermed_5 <= RIN_M_CTRL_PC31DOWNTO12_intermed_4;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
IR_ADDR31DOWNTO12_intermed_2 <= IR_ADDR31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_3 <= R_X_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_D_PC31DOWNTO12_shadow_intermed_8 <= V_D_PC31DOWNTO12_shadow_intermed_7;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_D_PC31DOWNTO12_intermed_7 <= R_D_PC31DOWNTO12_intermed_6;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_A_CTRL_PC31DOWNTO12_intermed_6 <= R_A_CTRL_PC31DOWNTO12_intermed_5;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_5 <= R_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_X_CTRL_PC31DOWNTO12_intermed_4 <= RIN_X_CTRL_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
RIN_D_PC31DOWNTO12_intermed_8 <= RIN_D_PC31DOWNTO12_intermed_7;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
VIR_ADDR31DOWNTO12_shadow_intermed_3 <= VIR_ADDR31DOWNTO12_shadow_intermed_2;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4;
ICO_DATA0_intermed_1 <= ICO.DATA ( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
R_D_INST1_intermed_2 <= R_D_INST1_intermed_1;
ICO_DATA1_intermed_1 <= ICO.DATA ( 1 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
R_X_DATA03_intermed_2 <= R_X_DATA03_intermed_1;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_E_ALUCIN_shadow_intermed_1 <= V_E_ALUCIN_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_E_ALUCIN_intermed_1 <= RIN.E.ALUCIN;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_E_YMSB_shadow_intermed_1 <= V_E_YMSB_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_E_YMSB_intermed_1 <= RIN.E.YMSB;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_E_SHCNT_shadow_intermed_1 <= V_E_SHCNT_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_E_SHCNT_intermed_1 <= RIN.E.SHCNT;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
V_E_SARI_shadow_intermed_1 <= V_E_SARI_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_E_SARI_intermed_1 <= RIN.E.SARI;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
V_X_DCI_SIGNED_shadow_intermed_1 <= V_X_DCI_SIGNED_shadow;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
V_X_DCI_SIZE_shadow_intermed_1 <= V_X_DCI_SIZE_shadow;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_3 <= V_M_RESULT1DOWNTO0_shadow_intermed_2;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_3 <= RIN_M_RESULT1DOWNTO0_intermed_2;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_X_LADDR_shadow_intermed_1 <= V_X_LADDR_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_X_CTRL_TRAP_shadow_intermed_1 <= V_X_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
V_X_MEXC_shadow_intermed_1 <= V_X_MEXC_shadow;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
DCO_MEXC_intermed_1 <= DCO.MEXC;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RPIN_PWD_intermed_1 <= RPIN.PWD;
V_X_DEBUG_shadow_intermed_1 <= V_X_DEBUG_shadow;
VP_PWD_shadow_intermed_1 <= VP_PWD_shadow;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_W_S_TBA_shadow_intermed_1 <= V_W_S_TBA_shadow;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
RIN_W_S_TBA_intermed_1 <= RIN.W.S.TBA;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
DSUIN_TT_intermed_1 <= DSUIN.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RPIN_PWD_intermed_1 <= RPIN.PWD;
IRIN_PWD_intermed_1 <= IRIN.PWD;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_W_S_TT_intermed_1 <= RIN.W.S.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD6DOWNTO0_shadow;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_W_S_CWP_shadow_intermed_1 <= V_W_S_CWP_shadow;
RIN_W_S_ET_intermed_1 <= RIN.W.S.ET;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_D_PC_intermed_6 <= RIN_D_PC_intermed_5;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
VIR_ADDR_shadow_intermed_1 <= VIR_ADDR_shadow;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
RIN_A_CTRL_PC_intermed_5 <= RIN_A_CTRL_PC_intermed_4;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_4 <= R_A_CTRL_PC_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
V_E_CTRL_PC_shadow_intermed_4 <= V_E_CTRL_PC_shadow_intermed_3;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_M_CTRL_PC_intermed_2 <= R_M_CTRL_PC_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC_intermed_1 <= R.X.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
R_E_CTRL_PC_intermed_3 <= R_E_CTRL_PC_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_3 <= RIN_M_CTRL_PC_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_X_CTRL_PC_shadow_intermed_2 <= V_X_CTRL_PC_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_M_CTRL_PC_shadow_intermed_3 <= V_M_CTRL_PC_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_5 <= V_A_CTRL_PC_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
R_D_PC_intermed_5 <= R_D_PC_intermed_4;
RIN_F_PC_intermed_1 <= RIN.F.PC;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_E_CTRL_PC_intermed_4 <= RIN_E_CTRL_PC_intermed_3;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
RIN_X_CTRL_PC_intermed_2 <= RIN_X_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
V_D_PC_shadow_intermed_6 <= V_D_PC_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
DSUIN_TBUFCNT_intermed_1 <= DSUIN.TBUFCNT;
RIN_W_EXCEPT_intermed_1 <= RIN.W.EXCEPT;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
RIN_W_RESULT_intermed_1 <= RIN.W.RESULT;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_W_WA_intermed_1 <= RIN.W.WA;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_W_WREG_intermed_1 <= RIN.W.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_W_S_SVT_intermed_1 <= RIN.W.S.SVT;
RIN_W_S_DWT_intermed_1 <= RIN.W.S.DWT;
RIN_W_S_EF_intermed_1 <= RIN.W.S.EF;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_E_CTRL_intermed_2 <= RIN_E_CTRL_intermed_1;
R_E_CTRL_intermed_1 <= R.E.CTRL;
RIN_X_CTRL_intermed_1 <= RIN.X.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
V_E_CTRL_shadow_intermed_2 <= V_E_CTRL_shadow_intermed_1;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
RIN_A_CTRL_intermed_3 <= RIN_A_CTRL_intermed_2;
V_M_CTRL_shadow_intermed_1 <= V_M_CTRL_shadow;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
V_A_CTRL_shadow_intermed_3 <= V_A_CTRL_shadow_intermed_2;
R_A_CTRL_intermed_1 <= R.A.CTRL;
R_A_CTRL_intermed_2 <= R_A_CTRL_intermed_1;
V_M_DCI_shadow_intermed_1 <= V_M_DCI_shadow;
RIN_M_DCI_intermed_1 <= RIN.M.DCI;
RIN_X_DCI_intermed_1 <= RIN.X.DCI;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_E_CTRL_RETT_shadow_intermed_2 <= V_E_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_3 <= V_A_CTRL_RETT_shadow_intermed_2;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
RIN_A_CTRL_RETT_intermed_3 <= RIN_A_CTRL_RETT_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_E_CTRL_RETT_intermed_1 <= R.E.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
RIN_E_CTRL_RETT_intermed_2 <= RIN_E_CTRL_RETT_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_X_CTRL_RETT_intermed_1 <= RIN.X.CTRL.RETT;
V_M_CTRL_RETT_shadow_intermed_1 <= V_M_CTRL_RETT_shadow;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
R_A_CTRL_RETT_intermed_2 <= R_A_CTRL_RETT_intermed_1;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
V_E_MAC_shadow_intermed_2 <= V_E_MAC_shadow_intermed_1;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
RIN_E_MAC_intermed_2 <= RIN_E_MAC_intermed_1;
R_E_MAC_intermed_1 <= R.E.MAC;
V_M_MAC_shadow_intermed_1 <= V_M_MAC_shadow;
RIN_X_MAC_intermed_1 <= RIN.X.MAC;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_X_CTRL_ANNUL_intermed_1 <= RIN.X.CTRL.ANNUL;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
RIN_X_SET_intermed_1 <= RIN.X.SET;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_X_ICC_intermed_1 <= RIN.X.ICC;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
R_A_CTRL_WICC_intermed_2 <= R_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_E_CTRL_WICC_shadow_intermed_2 <= V_E_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_3 <= V_A_CTRL_WICC_shadow_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_X_CTRL_WICC_intermed_1 <= RIN.X.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_E_CTRL_WICC_intermed_2 <= RIN_E_CTRL_WICC_intermed_1;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
R_E_CTRL_WICC_intermed_1 <= R.E.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_M_CTRL_WICC_shadow_intermed_1 <= V_M_CTRL_WICC_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_WICC_intermed_3 <= RIN_A_CTRL_WICC_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
R_A_CTRL_intermed_1 <= R.A.CTRL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
RIN_E_CWP_intermed_1 <= RIN.E.CWP;
V_A_CWP_shadow_intermed_1 <= V_A_CWP_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_D_CWP_intermed_2 <= RIN_D_CWP_intermed_1;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
V_D_CWP_shadow_intermed_2 <= V_D_CWP_shadow_intermed_1;
R_D_CWP_intermed_1 <= R.D.CWP;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_M_MUL_intermed_1 <= RIN.M.MUL;
RIN_M_NALIGN_intermed_1 <= RIN.M.NALIGN;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
R_A_CTRL_LD_intermed_2 <= R_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_3 <= RIN_A_CTRL_LD_intermed_2;
V_E_CTRL_LD_shadow_intermed_1 <= V_E_CTRL_LD_shadow;
V_E_CTRL_LD_shadow_intermed_2 <= V_E_CTRL_LD_shadow_intermed_1;
R_E_CTRL_LD_intermed_1 <= R.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_2 <= RIN_E_CTRL_LD_intermed_1;
RIN_M_CTRL_LD_intermed_1 <= RIN.M.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
V_A_CTRL_LD_shadow_intermed_3 <= V_A_CTRL_LD_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
RIN_E_JMPL_intermed_1 <= RIN.E.JMPL;
RIN_A_JMPL_intermed_1 <= RIN.A.JMPL;
V_A_JMPL_shadow_intermed_1 <= V_A_JMPL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_A_SU_intermed_1 <= RIN.A.SU;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_ET_intermed_1 <= RIN.E.ET;
RIN_A_ET_intermed_1 <= RIN.A.ET;
V_A_ET_shadow_intermed_1 <= V_A_ET_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
V_A_RFA1_shadow_intermed_1 <= V_A_RFA1_shadow;
DBGI_DADDR9DOWNTO2_intermed_1 <= DBGI.DADDR ( 9 DOWNTO 2 );
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
RIN_A_RFA2_intermed_1 <= RIN.A.RFA2;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WY_intermed_1 <= RIN.A.CTRL.WY;
ICO_MEXC_intermed_1 <= ICO.MEXC;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
R_D_ANNUL_intermed_1 <= R.D.ANNUL;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
V_D_ANNUL_shadow_intermed_2 <= V_D_ANNUL_shadow_intermed_1;
DBGI_STEP_intermed_1 <= DBGI.STEP;
V_D_STEP_shadow_intermed_1 <= V_D_STEP_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_ANNUL_intermed_2 <= RIN_D_ANNUL_intermed_1;
RIN_A_STEP_intermed_1 <= RIN.A.STEP;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
RIN_F_BRANCH_intermed_1 <= RIN.F.BRANCH;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
R_D_INST0_intermed_1 <= R.D.INST( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
RIN_D_SET_intermed_1 <= RIN.D.SET;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
R_E_CTRL_INST_intermed_2 <= R_E_CTRL_INST_intermed_1;
R_M_CTRL_INST_intermed_1 <= R.M.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
DE_INST_shadow_intermed_4 <= DE_INST_shadow_intermed_3;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_4 <= V_A_CTRL_INST_shadow_intermed_3;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
V_E_CTRL_INST_shadow_intermed_3 <= V_E_CTRL_INST_shadow_intermed_2;
RIN_X_CTRL_INST_intermed_1 <= RIN.X.CTRL.INST;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_A_CTRL_INST_intermed_4 <= RIN_A_CTRL_INST_intermed_3;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_M_CTRL_INST_intermed_2 <= RIN_M_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_3 <= RIN_E_CTRL_INST_intermed_2;
V_M_CTRL_INST_shadow_intermed_1 <= V_M_CTRL_INST_shadow;
V_M_CTRL_INST_shadow_intermed_2 <= V_M_CTRL_INST_shadow_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_3 <= R_A_CTRL_INST_intermed_2;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_CNT_shadow_intermed_3 <= V_E_CTRL_CNT_shadow_intermed_2;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
RIN_D_CNT_intermed_5 <= RIN_D_CNT_intermed_4;
R_M_CTRL_CNT_intermed_1 <= R.M.CTRL.CNT;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
V_A_CTRL_CNT_shadow_intermed_4 <= V_A_CTRL_CNT_shadow_intermed_3;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
R_A_CTRL_CNT_intermed_3 <= R_A_CTRL_CNT_intermed_2;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
V_D_CNT_shadow_intermed_5 <= V_D_CNT_shadow_intermed_4;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_D_CNT_intermed_4 <= R_D_CNT_intermed_3;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
R_E_CTRL_CNT_intermed_2 <= R_E_CTRL_CNT_intermed_1;
RIN_X_CTRL_CNT_intermed_1 <= RIN.X.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_A_CTRL_CNT_intermed_4 <= RIN_A_CTRL_CNT_intermed_3;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_M_CTRL_CNT_intermed_2 <= RIN_M_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_3 <= RIN_E_CTRL_CNT_intermed_2;
V_M_CTRL_CNT_shadow_intermed_1 <= V_M_CTRL_CNT_shadow;
V_M_CTRL_CNT_shadow_intermed_2 <= V_M_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_3 <= V_E_CTRL_PV_shadow_intermed_2;
R_M_CTRL_PV_intermed_1 <= R.M.CTRL.PV;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_E_CTRL_PV_intermed_2 <= R_E_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_3 <= R_A_CTRL_PV_intermed_2;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_3 <= RIN_E_CTRL_PV_intermed_2;
RIN_X_CTRL_PV_intermed_1 <= RIN.X.CTRL.PV;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
RIN_M_CTRL_PV_intermed_2 <= RIN_M_CTRL_PV_intermed_1;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
V_A_CTRL_PV_shadow_intermed_4 <= V_A_CTRL_PV_shadow_intermed_3;
V_M_CTRL_PV_shadow_intermed_1 <= V_M_CTRL_PV_shadow;
V_M_CTRL_PV_shadow_intermed_2 <= V_M_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
RIN_A_CTRL_PV_intermed_4 <= RIN_A_CTRL_PV_intermed_3;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
end if;
end process;
dfp_trap_vector(0) <= '1' when (RP.ERROR /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(1) <= '1' when (RP.ERROR /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(2) <= '1' when (RFI.REN1 /= DE_REN1_shadow) else '0';
dfp_trap_vector(3) <= '1' when (RFI.REN2 /= DE_REN2_shadow) else '0';
dfp_trap_vector(4) <= '1' when (RFI.DIAG(0) /= DCO.TESTEN) else '0';
dfp_trap_vector(5) <= '1' when (RFI.DIAG /= "0000") else '0';
dfp_trap_vector(6) <= '1' when (ICI.DPC(31 downto 2) /= R.D.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(7) <= '1' when (ICI.FPC(31 downto 2) /= R.F.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(8) <= '1' when (ICI.RPC(31 downto 2) /= NPC31DOWNTO2_shadow) else '0';
dfp_trap_vector(9) <= '1' when (ICI.FLUSHL /= '0') else '0';
dfp_trap_vector(10) <= '1' when (MULI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(11) <= '1' when (MULI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(12) <= '1' when (MULI.OP2(31 downto 0) /= MUL_OP2_shadow) else '0';
dfp_trap_vector(13) <= '1' when (MULI.OP2(31) /= MUL_OP231_shadow) else '0';
dfp_trap_vector(14) <= '1' when (DIVI.START /= R.A.DIVSTART) else '0';
dfp_trap_vector(15) <= '1' when (DIVI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(16) <= '1' when (DIVI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(17) <= '1' when (DIVI.OP2(31) /= EX_OP231_shadow) else '0';
dfp_trap_vector(18) <= '1' when (DIVI.OP2(31 downto 0) /= EX_OP2_shadow) else '0';
dfp_trap_vector(19) <= '1' when (DIVI.Y(31 downto 0) /= R.M.Y) else '0';
dfp_trap_vector(20) <= '1' when (DIVI.Y(31) /= R.M.Y ( 31 )) else '0';
dfp_trap_vector(21) <= '1' when (EX_JUMP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow) else '0';
dfp_trap_vector(22) <= '1' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_1) else '0';
dfp_trap_vector(23) <= '1' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0';
dfp_trap_vector(24) <= '1' when (V_A_STEP_shadow /= RIN_A_STEP_intermed_1) else '0';
dfp_trap_vector(25) <= '1' when (V_D_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(26) <= '1' when (V_D_STEP_shadow /= DBGI.STEP) else '0';
dfp_trap_vector(27) <= '1' when (V_D_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(28) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow) else '0';
dfp_trap_vector(29) <= '1' when (RIN.X.DATA ( 0 ) /= V_X_DATA0_shadow) else '0';
dfp_trap_vector(30) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(31) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(32) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow) else '0';
dfp_trap_vector(33) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow) else '0';
dfp_trap_vector(34) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(35) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(36) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow) else '0';
dfp_trap_vector(37) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(38) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R.A.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(39) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow) else '0';
dfp_trap_vector(40) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(41) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(42) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(43) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(44) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(45) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(46) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow) else '0';
dfp_trap_vector(47) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R.A.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(48) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow) else '0';
dfp_trap_vector(49) <= '1' when (RIN.M.Y ( 31 ) /= V_M_Y31_shadow) else '0';
dfp_trap_vector(50) <= '1' when (V_A_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(51) <= '1' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow) else '0';
dfp_trap_vector(52) <= '1' when (V_A_STEP_shadow /= R.A.STEP) else '0';
dfp_trap_vector(53) <= '1' when (V_A_STEP_shadow /= DBGI_STEP_intermed_1) else '0';
dfp_trap_vector(54) <= '1' when (V_A_STEP_shadow /= V_D_STEP_shadow_intermed_1) else '0';
dfp_trap_vector(55) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(56) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(57) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(58) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(59) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(60) <= '1' when (RIN.X.DATA ( 1 ) /= V_X_DATA1_shadow) else '0';
dfp_trap_vector(61) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow) else '0';
dfp_trap_vector(62) <= '1' when (RIN.D.INST ( 0 ) /= V_D_INST0_shadow) else '0';
dfp_trap_vector(63) <= '1' when (RIN.D.INST ( 1 ) /= V_D_INST1_shadow) else '0';
dfp_trap_vector(64) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow) else '0';
dfp_trap_vector(65) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow) else '0';
dfp_trap_vector(66) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow) else '0';
dfp_trap_vector(67) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow) else '0';
dfp_trap_vector(68) <= '1' when (XC_HALT_shadow /= DBGI.HALT) else '0';
dfp_trap_vector(69) <= '1' when (XC_HALT_shadow /= '0') else '0';
dfp_trap_vector(70) <= '1' when (V_A_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(71) <= '1' when (V_A_CTRL_TT_shadow /= R.A.CTRL.TT) else '0';
dfp_trap_vector(72) <= '1' when (V_A_CTRL_TT_shadow /= "000000") else '0';
dfp_trap_vector(73) <= '1' when (V_A_CTRL_INST_shadow /= DE_INST_shadow) else '0';
dfp_trap_vector(74) <= '1' when (V_A_CTRL_PC_shadow /= R.D.PC) else '0';
dfp_trap_vector(75) <= '1' when (V_A_CTRL_CNT_shadow /= R.D.CNT) else '0';
dfp_trap_vector(76) <= '1' when (V_A_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(77) <= '1' when (V_X_NERROR_shadow /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(78) <= '1' when (V_X_NERROR_shadow /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(79) <= '1' when (V_X_NERROR_shadow /= RP.ERROR) else '0';
dfp_trap_vector(80) <= '1' when (V_M_MAC_shadow /= R.E.MAC) else '0';
dfp_trap_vector(81) <= '1' when (V_M_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(82) <= '1' when (V_E_JMPL_shadow /= R.A.JMPL) else '0';
dfp_trap_vector(83) <= '1' when (V_E_CTRL_RETT_shadow /= R.A.CTRL.RETT) else '0';
dfp_trap_vector(84) <= '1' when (V_E_SU_shadow /= R.A.SU) else '0';
dfp_trap_vector(85) <= '1' when (V_E_ET_shadow /= R.A.ET) else '0';
dfp_trap_vector(86) <= '1' when (V_A_CWP_shadow /= R.D.CWP) else '0';
dfp_trap_vector(87) <= '1' when (V_A_CTRL_TRAP_shadow /= R.D.MEXC) else '0';
dfp_trap_vector(88) <= '1' when (V_A_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_1) else '0';
dfp_trap_vector(89) <= '1' when (V_A_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_1) else '0';
dfp_trap_vector(90) <= '1' when (VP_PWD_shadow /= RP.PWD) else '0';
dfp_trap_vector(91) <= '1' when (VP_PWD_shadow /= '0') else '0';
dfp_trap_vector(92) <= '1' when (VP_PWD_shadow /= RPIN_PWD_intermed_1) else '0';
dfp_trap_vector(93) <= '1' when (V_M_MUL_shadow /= R.M.MUL) else '0';
dfp_trap_vector(94) <= '1' when (V_M_MAC_shadow /= V_E_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(95) <= '1' when (V_M_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(96) <= '1' when (V_M_MAC_shadow /= RIN_E_MAC_intermed_1) else '0';
dfp_trap_vector(97) <= '1' when (VDSU_TBUFCNT_shadow /= TBUFCNTX_shadow) else '0';
dfp_trap_vector(98) <= '1' when (V_M_MUL_shadow /= RIN_M_MUL_intermed_1) else '0';
dfp_trap_vector(99) <= '1' when (V_M_MUL_shadow /= '0') else '0';
dfp_trap_vector(100) <= '1' when (V_W_RESULT_shadow /= XC_RESULT_shadow) else '0';
dfp_trap_vector(101) <= '1' when (V_W_WA_shadow /= XC_WADDR7DOWNTO0_shadow) else '0';
dfp_trap_vector(102) <= '1' when (V_W_S_SVT_shadow /= R.W.S.SVT) else '0';
dfp_trap_vector(103) <= '1' when (V_W_S_SVT_shadow /= '0') else '0';
dfp_trap_vector(104) <= '1' when (V_W_S_SVT_shadow /= RIN_W_S_SVT_intermed_1) else '0';
dfp_trap_vector(105) <= '1' when (V_W_S_DWT_shadow /= RIN_W_S_DWT_intermed_1) else '0';
dfp_trap_vector(106) <= '1' when (V_W_S_DWT_shadow /= R.W.S.DWT) else '0';
dfp_trap_vector(107) <= '1' when (V_W_S_DWT_shadow /= '0') else '0';
dfp_trap_vector(108) <= '1' when (V_M_CTRL_RETT_shadow /= R.E.CTRL.RETT) else '0';
dfp_trap_vector(109) <= '1' when (V_E_CWP_shadow /= R.A.CWP) else '0';
dfp_trap_vector(110) <= '1' when (V_M_SU_shadow /= R.E.SU) else '0';
dfp_trap_vector(111) <= '1' when (V_X_DCI_shadow /= R.M.DCI) else '0';
dfp_trap_vector(112) <= '1' when (V_X_CTRL_RETT_shadow /= R.M.CTRL.RETT) else '0';
dfp_trap_vector(113) <= '1' when (V_X_MAC_shadow /= V_E_MAC_shadow_intermed_2) else '0';
dfp_trap_vector(114) <= '1' when (V_X_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(115) <= '1' when (V_X_MAC_shadow /= RIN_E_MAC_intermed_2) else '0';
dfp_trap_vector(116) <= '1' when (V_X_MAC_shadow /= R_E_MAC_intermed_1) else '0';
dfp_trap_vector(117) <= '1' when (V_X_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(118) <= '1' when (V_X_MAC_shadow /= V_M_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(119) <= '1' when (V_X_MAC_shadow /= RIN_X_MAC_intermed_1) else '0';
dfp_trap_vector(120) <= '1' when (V_X_MAC_shadow /= R.X.MAC) else '0';
dfp_trap_vector(121) <= '1' when (V_X_LADDR_shadow /= R.M.RESULT ( 1 DOWNTO 0 )) else '0';
dfp_trap_vector(122) <= '1' when (V_X_MEXC_shadow /= DCO.MEXC) else '0';
dfp_trap_vector(123) <= '1' when (V_X_ICC_shadow /= ME_ICC_shadow) else '0';
dfp_trap_vector(124) <= '1' when (TRIGGERCPFAULT /= '0') else '0';
dfp_or_reduce : process(dfp_trap_vector)
variable or_reduce_62 : std_logic_vector(61 downto 0);
variable or_reduce_31 : std_logic_vector(30 downto 0);
variable or_reduce_16 : std_logic_vector(15 downto 0);
variable or_reduce_8 : std_logic_vector(7 downto 0);
variable or_reduce_4 : std_logic_vector(3 downto 0);
variable or_reduce_2 : std_logic_vector(1 downto 0);
begin
or_reduce_62 := dfp_trap_vector(123 downto 62) OR dfp_trap_vector(61 downto 0);
or_reduce_31 := or_reduce_62(61 downto 31) OR or_reduce_62(30 downto 0);
or_reduce_16 := or_reduce_31(30 downto 15) OR (dfp_trap_vector(124) & or_reduce_31(14 downto 0));
or_reduce_8 := or_reduce_16(15 downto 8) OR or_reduce_16(7 downto 0);
or_reduce_4 := or_reduce_8(7 downto 4) OR or_reduce_8(3 downto 0);
or_reduce_2 := or_reduce_4(3 downto 2) OR or_reduce_4(1 downto 0);
or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1);
end process;
trap_enable_delay : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_delay_start <= 15;
elsif(dfp_delay_start /= 0)then
dfp_delay_start <= dfp_delay_start - 1;
end if;
end if;
end process;
trap_mem : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_trap_mem <= (others => '0');
elsif(dfp_delay_start = 0)then
dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector;
end if;
end if;
end process;
handlerTrap <= or_reduce_1 when (dfp_delay_start = 0) else '0';
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
shadow_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
triggerCPFault <= '0';
IF(dci.write = '1')then
IF(dataToCache = X"6841_636B")THEN
triggerCPFault <= '1';
END IF;
END IF;
end if;
end process;
end;
| mit |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/leon3mp.vhd | 1 | 21368 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
signal stati : ahbstat_in_type;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-- gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
-- grgpio0: grgpio
-- generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
-- nbits => CFG_GRGPIO_WIDTH)
-- port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
--
-- pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
-- pio_pad : iopad generic map (tech => padtech)
-- port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
-- end generate;
-- end generate;
-- ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
-- ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
-- nftslv => CFG_AHBSTATN)
-- port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
-- end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_version
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/eth/core/grethc.vhd | 2 | 66506 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth
-- File: greth.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity grethc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 2 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000"
);
end entity;
architecture rtl of grethc is
procedure sel_op_mode(
capbil : in std_logic_vector(4 downto 0);
speed : out std_ulogic;
duplex : out std_ulogic) is
variable vspeed : std_ulogic;
variable vduplex : std_ulogic;
begin
vspeed := '0'; vduplex := '0';
vspeed := orv(capbil(4 downto 2));
vduplex := (vspeed and capbil(3)) or ((not vspeed) and capbil(1));
speed := vspeed;
duplex := vduplex;
end procedure;
--host constants
constant fabits : integer := log2(fifosize);
constant burstlength : integer := setburstlength(fifosize);
constant burstbits : integer := log2(burstlength);
constant ctrlopcode : std_logic_vector(15 downto 0) := X"8808";
constant broadcast : std_logic_vector(47 downto 0) := X"FFFFFFFFFFFF";
constant maxsizetx : integer := 1514;
constant index : integer := log2(edclbufsz);
constant receiveOK : std_logic_vector(3 downto 0) := "0000";
constant frameCheckError : std_logic_vector(3 downto 0) := "0100";
constant alignmentError : std_logic_vector(3 downto 0) := "0001";
constant frameTooLong : std_logic_vector(3 downto 0) := "0010";
constant overrun : std_logic_vector(3 downto 0) := "1000";
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
--mdio constants
constant divisor : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(mdcscaler, 8);
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1514, 16);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant blbits : szvct := (6, 7, 7, 8, 8, 8, 8);
constant winsz : szvct := (4, 4, 8, 8, 16, 32, 64);
constant macaddrt : std_logic_vector(47 downto 0) :=
conv_std_logic_vector(macaddrh, 24) & conv_std_logic_vector(macaddrl, 24);
constant bpbits : integer := blbits(log2(edclbufsz));
constant wsz : integer := winsz(log2(edclbufsz));
constant bselbits : integer := log2(wsz);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufmax : std_logic_vector(bpbits-1 downto 0) := (others => '1');
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant txfifosizev : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(txfifosize, txfabits+1);
constant rxburstlen : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(burstlength, fabits+1);
constant txburstlen : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(burstlength, txfabits+1);
type edclrstate_type is (idle, wrda, wrdsa, wrsa, wrtype, ip, ipdata,
oplength, arp, iplength, ipcrc, arpop, udp, spill);
type duplexstate_type is (start, waitop, nextop, selmode, done);
--host types
type txd_state_type is (idle, read_desc, check_desc, req, fill_fifo,
check_result, write_result, readhdr, start, wrbus,
etdone, getlen, ahberror);
type rxd_state_type is (idle, read_desc, check_desc, read_req, read_fifo,
discard, write_status, write_status2);
--mdio types
type mdio_state_type is (idle, preamble, startst, op, op2, phyadr, regadr,
ta, ta2, ta3, data, dataend);
type ctrl_reg_type is record
txen : std_ulogic;
rxen : std_ulogic;
tx_irqen : std_ulogic;
rx_irqen : std_ulogic;
full_duplex : std_ulogic;
prom : std_ulogic;
reset : std_ulogic;
speed : std_ulogic;
end record;
type status_reg_type is record
tx_int : std_ulogic;
rx_int : std_ulogic;
rx_err : std_ulogic;
tx_err : std_ulogic;
txahberr : std_ulogic;
rxahberr : std_ulogic;
toosmall : std_ulogic;
invaddr : std_ulogic;
end record;
type mdio_ctrl_reg_type is record
phyadr : std_logic_vector(4 downto 0);
regadr : std_logic_vector(4 downto 0);
write : std_ulogic;
read : std_ulogic;
data : std_logic_vector(15 downto 0);
busy : std_ulogic;
linkfail : std_ulogic;
end record;
subtype mac_addr_reg_type is std_logic_vector(47 downto 0);
type fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(fabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(fabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(txfabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(txfabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type edcl_ram_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(eabits-1 downto 0);
writem : std_ulogic;
writel : std_ulogic;
waddressm : std_logic_vector(eabits-1 downto 0);
waddressl : std_logic_vector(eabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type edcl_ram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type reg_type is record
--user registers
ctrl : ctrl_reg_type;
status : status_reg_type;
mdio_ctrl : mdio_ctrl_reg_type;
mac_addr : mac_addr_reg_type;
txdesc : std_logic_vector(31 downto 10);
rxdesc : std_logic_vector(31 downto 10);
edclip : std_logic_vector(31 downto 0);
--master tx interface
txdsel : std_logic_vector(9 downto 3);
tmsto : eth_tx_ahb_in_type;
txdstate : txd_state_type;
txwrap : std_ulogic;
txden : std_ulogic;
txirq : std_ulogic;
txaddr : std_logic_vector(31 downto 2);
txlength : std_logic_vector(10 downto 0);
txburstcnt : std_logic_vector(burstbits downto 0);
tfwpnt : std_logic_vector(txfabits-1 downto 0);
tfrpnt : std_logic_vector(txfabits-1 downto 0);
tfcnt : std_logic_vector(txfabits downto 0);
txcnt : std_logic_vector(10 downto 0);
txstart : std_ulogic;
txirqgen : std_ulogic;
txstatus : std_logic_vector(1 downto 0);
txvalid : std_ulogic;
txdata : std_logic_vector(31 downto 0);
writeok : std_ulogic;
txread : std_logic_vector(nsync-1 downto 0);
txrestart : std_logic_vector(nsync downto 0);
txdone : std_logic_vector(nsync downto 0);
txstart_sync : std_ulogic;
txreadack : std_ulogic;
txdataav : std_ulogic;
txburstav : std_ulogic;
--master rx interface
rxdsel : std_logic_vector(9 downto 3);
rmsto : eth_rx_ahb_in_type;
rxdstate : rxd_state_type;
rxstatus : std_logic_vector(4 downto 0);
rxaddr : std_logic_vector(31 downto 2);
rxlength : std_logic_vector(10 downto 0);
rxbytecount : std_logic_vector(10 downto 0);
rxwrap : std_ulogic;
rxirq : std_ulogic;
rfwpnt : std_logic_vector(fabits-1 downto 0);
rfrpnt : std_logic_vector(fabits-1 downto 0);
rfcnt : std_logic_vector(fabits downto 0);
rxcnt : std_logic_vector(10 downto 0);
rxdoneold : std_ulogic;
rxdoneack : std_ulogic;
rxdone : std_logic_vector(nsync-1 downto 0);
rxstart : std_logic_vector(nsync downto 0);
rxwrite : std_logic_vector(nsync-1 downto 0);
rxwriteack : std_ulogic;
rxburstcnt : std_logic_vector(burstbits downto 0);
addrnok : std_ulogic;
ctrlpkt : std_ulogic;
check : std_ulogic;
checkdata : std_logic_vector(31 downto 0);
usesizefield : std_ulogic;
rxden : std_ulogic;
gotframe : std_ulogic;
bcast : std_ulogic;
rxburstav : std_ulogic;
--mdio
mdccnt : std_logic_vector(7 downto 0);
mdioclk : std_ulogic;
mdioclkold : std_ulogic;
mdio_state : mdio_state_type;
mdioo : std_ulogic;
mdioi : std_ulogic;
mdioen : std_ulogic;
cnt : std_logic_vector(4 downto 0);
duplexstate : duplexstate_type;
ext : std_ulogic;
extcap : std_ulogic;
regaddr : std_logic_vector(4 downto 0);
phywr : std_ulogic;
rstphy : std_ulogic;
capbil : std_logic_vector(4 downto 0);
rstaneg : std_ulogic;
--edcl
edclrstate : edclrstate_type;
edclactive : std_ulogic;
nak : std_ulogic;
ewr : std_ulogic;
write : std_logic_vector(wsz-1 downto 0);
seq : std_logic_vector(13 downto 0);
abufs : std_logic_vector(bselbits downto 0);
tpnt : std_logic_vector(bselbits-1 downto 0);
rpnt : std_logic_vector(bselbits-1 downto 0);
tcnt : std_logic_vector(bpbits-1 downto 0);
rcntm : std_logic_vector(bpbits-1 downto 0);
rcntl : std_logic_vector(bpbits-1 downto 0);
ipcrc : std_logic_vector(17 downto 0);
applength : std_logic_vector(15 downto 0);
oplen : std_logic_vector(9 downto 0);
udpsrc : std_logic_vector(15 downto 0);
ecnt : std_logic_vector(3 downto 0);
tarp : std_ulogic;
tnak : std_ulogic;
tedcl : std_ulogic;
edclbcast : std_ulogic;
end record;
--host signals
signal arst : std_ulogic;
signal irst : std_ulogic;
signal vcc : std_ulogic;
signal tmsto : eth_tx_ahb_in_type;
signal tmsti : eth_tx_ahb_out_type;
signal rmsto : eth_rx_ahb_in_type;
signal rmsti : eth_rx_ahb_out_type;
signal macaddr : std_logic_vector(47 downto 0);
signal ahbmi : ahbc_mst_in_type;
signal ahbmo : ahbc_mst_out_type;
signal txi : host_tx_type;
signal txo : tx_host_type;
signal rxi : host_rx_type;
signal rxo : rx_host_type;
signal r, rin : reg_type;
attribute sync_set_reset : string;
attribute sync_set_reset of irst : signal is "true";
begin
macaddr(47 downto 4) <= macaddrt(47 downto 4);
macaddr(3 downto 0) <= macaddrt(3 downto 0) when edcl /= 2 else edcladdr;
--reset generators for transmitter and receiver
vcc <= '1';
arst <= testrst when (scanen = 1) and (testen = '1')
else rst and not r.ctrl.reset;
irst <= rst and not r.ctrl.reset;
comb : process(rst, irst, r, rmsti, tmsti, txo, rxo, psel, paddr, penable,
erdata, pwrite, pwdata, rxrdata, txrdata, mdio_i, phyrstaddr,
testen, testrst, macaddr) is
variable v : reg_type;
variable vpirq : std_ulogic;
variable vprdata : std_logic_vector(31 downto 0);
variable txvalid : std_ulogic;
variable vtxfi : tx_fifo_access_in_type;
variable vrxfi : fifo_access_in_type;
variable lengthav : std_ulogic;
variable txdone : std_ulogic;
variable txread : std_ulogic;
variable txrestart : std_ulogic;
variable rxstart : std_ulogic;
variable rxdone : std_ulogic;
variable vrxwrite : std_ulogic;
variable ovrunstop : std_ulogic;
--mdio
variable mdioindex : integer range 0 to 31;
variable mclk : std_ulogic;
--edcl
variable veri : edcl_ram_in_type;
variable swap : std_ulogic;
variable setmz : std_ulogic;
variable ipcrctmp : std_logic_vector(15 downto 0);
variable ipcrctmp2 : std_logic_vector(17 downto 0);
variable vrxenable : std_ulogic;
variable crctmp : std_ulogic;
variable vecnt : integer;
begin
v := r; vprdata := (others => '0'); vpirq := '0';
v.check := '0'; lengthav := r.rxdoneold;-- or r.usesizefield;
ovrunstop := '0';
vtxfi.datain := tmsti.data;
vtxfi.raddress := r.tfrpnt; vtxfi.write := '0';
vtxfi.waddress := r.tfwpnt; vtxfi.renable := '1';
vrxfi.datain := rxo.dataout;
vrxfi.write := '0'; vrxfi.waddress := r.rfwpnt;
vrxfi.renable := '1'; vrxenable := r.ctrl.rxen;
--synchronization
v.txdone(0) := txo.done;
v.txread(0) := txo.read;
v.txrestart(0) := txo.restart;
v.rxstart(0) := rxo.start;
v.rxdone(0) := rxo.done;
v.rxwrite(0) := rxo.write;
if nsync = 2 then
v.txdone(1) := r.txdone(0);
v.txread(1) := r.txread(0);
v.txrestart(1) := r.txrestart(0);
v.rxstart(1) := r.rxstart(0);
v.rxdone(1) := r.rxdone(0);
v.rxwrite(1) := r.rxwrite(0);
end if;
txdone := r.txdone(nsync) xor r.txdone(nsync-1);
txread := r.txreadack xor r.txread(nsync-1);
txrestart := r.txrestart(nsync) xor r.txrestart(nsync-1);
rxstart := r.rxstart(nsync) xor r.rxstart(nsync-1);
rxdone := r.rxdoneack xor r.rxdone(nsync-1);
vrxwrite := r.rxwriteack xor r.rxwrite(nsync-1);
if txdone = '1' then
v.txstatus := txo.status;
end if;
-------------------------------------------------------------------------------
-- HOST INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--SLAVE INTERFACE
--write
if (psel and penable and pwrite) = '1' then
case paddr(5 downto 2) is
when "0000" => --ctrl reg
if rmii = 1 then
v.ctrl.speed := pwdata(7);
end if;
v.ctrl.reset := pwdata(6);
v.ctrl.prom := pwdata(5);
v.ctrl.full_duplex := pwdata(4);
v.ctrl.rx_irqen := pwdata(3);
v.ctrl.tx_irqen := pwdata(2);
v.ctrl.rxen := pwdata(1);
v.ctrl.txen := pwdata(0);
when "0001" => --status/int source reg
if pwdata(7) = '1' then v.status.invaddr := '0'; end if;
if pwdata(6) = '1' then v.status.toosmall := '0'; end if;
if pwdata(5) = '1' then v.status.txahberr := '0'; end if;
if pwdata(4) = '1' then v.status.rxahberr := '0'; end if;
if pwdata(3) = '1' then v.status.tx_int := '0'; end if;
if pwdata(2) = '1' then v.status.rx_int := '0'; end if;
if pwdata(1) = '1' then v.status.tx_err := '0'; end if;
if pwdata(0) = '1' then v.status.rx_err := '0'; end if;
when "0010" => --mac addr msb
v.mac_addr(47 downto 32) := pwdata(15 downto 0);
when "0011" => --mac addr lsb
v.mac_addr(31 downto 0) := pwdata(31 downto 0);
when "0100" => --mdio ctrl/status
if enable_mdio = 1 then
v.mdio_ctrl.data := pwdata(31 downto 16);
v.mdio_ctrl.phyadr := pwdata(15 downto 11);
v.mdio_ctrl.regadr := pwdata(10 downto 6);
if r.mdio_ctrl.busy = '0' then
v.mdio_ctrl.read := pwdata(1);
v.mdio_ctrl.write := pwdata(0);
v.mdio_ctrl.busy := pwdata(1) or pwdata(0);
end if;
end if;
when "0101" => --tx descriptor
v.txdesc := pwdata(31 downto 10);
v.txdsel := pwdata(9 downto 3);
when "0110" => --rx descriptor
v.rxdesc := pwdata(31 downto 10);
v.rxdsel := pwdata(9 downto 3);
when "0111" => --edcl ip
if (edcl /= 0) then
v.edclip := pwdata;
end if;
when others => null;
end case;
end if;
--read
case paddr(5 downto 2) is
when "0000" => --ctrl reg
if (edcl /= 0) then
vprdata(31) := '1';
vprdata(30 downto 28) := bufsize;
end if;
if rmii = 1 then
vprdata(7) := r.ctrl.speed;
end if;
vprdata(6) := r.ctrl.reset;
vprdata(5) := r.ctrl.prom;
vprdata(4) := r.ctrl.full_duplex;
vprdata(3) := r.ctrl.rx_irqen;
vprdata(2) := r.ctrl.tx_irqen;
vprdata(1) := r.ctrl.rxen;
vprdata(0) := r.ctrl.txen;
when "0001" => --status/int source reg
vprdata(5) := r.status.invaddr;
vprdata(4) := r.status.toosmall;
vprdata(5) := r.status.txahberr;
vprdata(4) := r.status.rxahberr;
vprdata(3) := r.status.tx_int;
vprdata(2) := r.status.rx_int;
vprdata(1) := r.status.tx_err;
vprdata(0) := r.status.rx_err;
when "0010" => --mac addr msb/mdio address
vprdata(15 downto 0) := r.mac_addr(47 downto 32);
when "0011" => --mac addr lsb
vprdata := r.mac_addr(31 downto 0);
when "0100" => --mdio ctrl/status
vprdata(31 downto 16) := r.mdio_ctrl.data;
vprdata(15 downto 11) := r.mdio_ctrl.phyadr;
vprdata(10 downto 6) := r.mdio_ctrl.regadr;
vprdata(3) := r.mdio_ctrl.busy;
vprdata(2) := r.mdio_ctrl.linkfail;
vprdata(1) := r.mdio_ctrl.read;
vprdata(0) := r.mdio_ctrl.write;
when "0101" => --tx descriptor
vprdata(31 downto 10) := r.txdesc;
vprdata(9 downto 3) := r.txdsel;
when "0110" => --rx descriptor
vprdata(31 downto 10) := r.rxdesc;
vprdata(9 downto 3) := r.rxdsel;
when "0111" => --edcl ip
if (edcl /= 0) then
vprdata := r.edclip;
end if;
when others => null;
end case;
--MASTER INTERFACE
v.txburstav := '0';
if (txfifosizev - r.tfcnt) >= txburstlen then
v.txburstav := '1';
end if;
--tx dma fsm
case r.txdstate is
when idle =>
v.txcnt := (others => '0');
if (edcl /= 0) then
v.tedcl := '0';
end if;
if (edcl /= 0) and (conv_integer(r.abufs) /= 0) then
v.txdstate := getlen;
v.tcnt := conv_std_logic_vector(10, bpbits);
elsif r.ctrl.txen = '1' then
v.txdstate := read_desc; v.tmsto.write := '0';
v.tmsto.addr := r.txdesc & r.txdsel & "000"; v.tmsto.req := '1';
end if;
if r.txirqgen = '1' then
vpirq := '1'; v.txirqgen := '0';
end if;
if txrestart = '1' then
v.txrestart(nsync) := r.txrestart(nsync-1);
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
end if;
when read_desc =>
v.tmsto.write := '0'; v.txstatus := (others => '0');
v.tfwpnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfcnt := (others => '0');
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
end if;
if tmsti.ready = '1' then
v.txcnt := r.txcnt + 1; v.tmsto.req := '0';
case r.txcnt(1 downto 0) is
when "00" =>
v.txlength := tmsti.data(10 downto 0);
v.txden := tmsti.data(11);
v.txwrap := tmsti.data(12);
v.txirq := tmsti.data(13);
v.ctrl.txen := tmsti.data(11);
when "01" =>
v.txaddr := tmsti.data(31 downto 2);
v.txdstate := check_desc;
when others => null;
end case;
end if;
when check_desc =>
v.txstart := '0';
v.txburstcnt := (others => '0');
if r.txden = '1' then
if (conv_integer(r.txlength) > maxsizetx) or
(conv_integer(r.txlength) = 0) then
v.txdstate := write_result; v.tmsto.req := '1';
v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000";
v.tmsto.data := (others => '0');
else
v.txdstate := req;
v.tmsto.addr := r.txaddr & "00"; v.txcnt(10 downto 0) := r.txlength;
end if;
else
v.txdstate := idle;
end if;
when req =>
if txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := idle;
end if;
elsif txdone = '1' then
v.txdstate := check_result;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone;
end if;
elsif conv_integer(r.txcnt) = 0 then
v.txdstate := check_result;
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone; v.txstart_sync := not r.txstart_sync;
end if;
elsif (r.txburstav = '1') or (r.tedcl = '1') then
v.tmsto.req := '1'; v.txdstate := fill_fifo;
end if;
v.txburstcnt := (others => '0');
when fill_fifo =>
v.txburstav := '0';
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) then
v.tmsto.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
when check_result =>
if txdone = '1' then
v.txdstate := write_result; v.tmsto.req := '1'; v.txstart := '0';
v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000";
v.tmsto.data(31 downto 16) := (others => '0');
v.tmsto.data(15 downto 14) := v.txstatus;
v.tmsto.data(13 downto 0) := (others => '0');
v.txdone(nsync) := r.txdone(nsync-1);
elsif txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
end if;
when write_result =>
if tmsti.grant = '1' then
v.tmsto.req := '0'; v.tmsto.addr := r.tmsto.addr + 4;
end if;
if tmsti.ready = '1' then
v.txdstate := idle;
v.txirqgen := r.ctrl.tx_irqen and r.txirq;
if r.txwrap = '0' then v.txdsel := r.txdsel + 1;
else v.txdsel := (others => '0'); end if;
if conv_integer(r.txstatus) = 0 then v.status.tx_int := '1';
else v.status.tx_err := '1'; end if;
end if;
when ahberror =>
v.tfcnt := (others => '0'); v.tfwpnt := (others => '0');
v.tfrpnt := (others => '0');
v.status.txahberr := '1'; v.ctrl.txen := '0';
if not ((edcl /= 0) and (r.tedcl = '1')) then
if r.txstart = '1' then
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
end if;
else
v.txdstate := idle;
end if;
else
v.txdstate := idle;
v.abufs := r.abufs - 1; v.tpnt := r.tpnt + 1;
end if;
when others =>
null;
end case;
--tx fifo read
v.txdataav := '0';
if conv_integer(r.tfcnt) /= 0 then
v.txdataav := '1';
end if;
if txread = '1' then
v.txreadack := not r.txreadack;
if r.txdataav = '1' then
if conv_integer(r.tfcnt) < 2 then
v.txdataav := '0';
end if;
v.txvalid := '1';
v.tfcnt := v.tfcnt - 1; v.tfrpnt := r.tfrpnt + 1;
else
v.txvalid := '0';
end if;
v.txdata := txrdata;
end if;
v.rxburstav := '0';
if r.rfcnt >= rxburstlen then
v.rxburstav := '1';
end if;
--rx dma fsm
case r.rxdstate is
when idle =>
v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrnok := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
if r.ctrl.rxen = '1' then
v.rxdstate := read_desc; v.rmsto.req := '1';
v.rmsto.addr := r.rxdesc & r.rxdsel & "000";
elsif rxstart = '1' then
v.rxstart(nsync) := r.rxstart(nsync-1);
v.rxdstate := discard;
end if;
when read_desc =>
v.rxstatus := (others => '0');
if rmsti.grant = '1' then
v.rmsto.addr := r.rmsto.addr + 4;
end if;
if rmsti.ready = '1' then
v.rxcnt := r.rxcnt + 1; v.rmsto.req := '0';
case r.rxcnt(1 downto 0) is
when "00" =>
v.ctrl.rxen := rmsti.data(11);
v.rxden := rmsti.data(11);
v.rxwrap := rmsti.data(12);
v.rxirq := rmsti.data(13);
when "01" =>
v.rxaddr := rmsti.data(31 downto 2);
v.rxdstate := check_desc;
when others =>
null;
end case;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when check_desc =>
v.rxcnt := (others => '0'); v.usesizefield := '0'; v.rmsto.write := '1';
if r.rxden = '1' then
if rxstart = '1' then
v.rxdstate := read_req; v.rxstart(nsync) := r.rxstart(nsync-1);
end if;
else
v.rxdstate := idle;
end if;
v.rmsto.addr := r.rxaddr & "00";
when read_req =>
if r.edclactive = '1' then
v.rxdstate := discard;
elsif (r.rxdoneold and r.rxstatus(3)) = '1' then
v.rxdstate := write_status;
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
elsif (r.addrnok or r.ctrlpkt) = '1' then
v.rxdstate := discard; v.status.invaddr := '1';
elsif ((r.rxdoneold = '1') and r.rxcnt >= r.rxlength) then
if r.gotframe = '1' then
v.rxdstate := write_status;
else
v.rxdstate := discard; v.status.toosmall := '1';
end if;
elsif (r.rxburstav or r.rxdoneold) = '1' then
v.rmsto.req := '1'; v.rxdstate := read_fifo;
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
end if;
v.rxburstcnt := (others => '0'); v.rmsto.data := rxrdata;
when read_fifo =>
v.rxburstav := '0';
if rmsti.grant = '1' then
v.rmsto.addr := r.rmsto.addr + 4;
if (lengthav = '1') then
if ((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 8)) and (rmsti.ready = '1')) or
((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 4)) and (rmsti.ready = '0')) then
v.rmsto.req := '0';
end if;
end if;
v.rxburstcnt := r.rxburstcnt + 1;
if (conv_integer(r.rxburstcnt) = burstlength-1) then
v.rmsto.req := '0';
end if;
end if;
if rmsti.ready = '1' then
v.rmsto.data := rxrdata;
v.rxcnt := r.rxcnt + 4;
if r.rmsto.req = '0' then
v.rxdstate := read_req;
else
v.rfcnt := r.rfcnt - 1; v.rfrpnt := r.rfrpnt + 1;
end if;
v.check := '1'; v.checkdata := r.rmsto.data;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := discard;
v.rxcnt := r.rxcnt + 4;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when write_status =>
v.rmsto.req := '1'; v.rmsto.addr := r.rxdesc & r.rxdsel & "000";
v.rxdstate := write_status2;
v.rmsto.data := X"000" & '0' & r.rxstatus & "000" & r.rxlength;
when write_status2 =>
if rmsti.grant = '1' then
v.rmsto.req := '0'; v.rmsto.addr := r.rmsto.addr + 4;
end if;
if rmsti.ready = '1' then
if (r.rxstatus(4) or not r.rxstatus(3)) = '1' then
v.rxdstate := discard;
else
v.rxdstate := idle;
end if;
if (r.ctrl.rx_irqen and r.rxirq) = '1' then
vpirq := '1';
end if;
if conv_integer(r.rxstatus) = 0 then v.status.rx_int := '1';
else v.status.rx_err := '1'; end if;
if r.rxwrap = '1' then
v.rxdsel := (others => '0');
else
v.rxdsel := r.rxdsel + 1;
end if;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when discard =>
if (r.rxdoneold = '0') or ((r.rxdoneold = '1') and
(conv_integer(r.rxcnt) < conv_integer(r.rxbytecount))) then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
elsif (r.rxdoneold = '1') then
v.rxdstate := idle; v.ctrlpkt := '0';
end if;
when others =>
null;
end case;
--rx address/type check
if r.check = '1' and r.rxcnt(10 downto 5) = "000000" then
case r.rxcnt(4 downto 2) is
when "001" =>
if r.checkdata /= broadcast(47 downto 16) and
r.checkdata /= r.mac_addr(47 downto 16) and
(not r.ctrl.prom) = '1'then
v.addrnok := '1';
elsif r.checkdata = broadcast(47 downto 16) then
v.bcast := '1';
end if;
when "010" =>
if r.checkdata(31 downto 16) /= broadcast(15 downto 0) and
r.checkdata(31 downto 16) /= r.mac_addr(15 downto 0) and
(not r.ctrl.prom) = '1' then
v.addrnok := '1';
elsif (r.bcast = '0') and
(r.checkdata(31 downto 16) = broadcast(15 downto 0)) then
v.addrnok := '1';
end if;
when "011" =>
null;
when "100" =>
if r.checkdata(31 downto 16) = ctrlopcode then v.ctrlpkt := '1'; end if;
when others =>
null;
end case;
end if;
--rx packet done
if (rxdone and not rxstart) = '1' then
v.gotframe := rxo.gotframe; v.rxbytecount := rxo.byte_count;
v.rxstatus(3 downto 0) := rxo.status;
if (rxo.lentype > maxsizerx) or (rxo.status /= "0000") then
v.rxlength := rxo.byte_count;
else
v.rxlength := rxo.lentype(10 downto 0);
if (rxo.lentype(10 downto 0) > minpload) and
(rxo.lentype(10 downto 0) /= rxo.byte_count) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
elsif (rxo.lentype(10 downto 0) <= minpload) and
(rxo.byte_count /= minpload) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
end if;
end if;
v.rxdoneold := '1';
--if ((not rxo.status(3)) or (rxo.status(3) and ovrunstop)) = '1' then
v.rxdoneack := not r.rxdoneack;
--end if;
--if ovrunstop = '1' then
-- v.rxbytecount := (others => '0');
--end if;
end if;
--rx fifo write
if vrxwrite = '1' then
v.rxwriteack := not r.rxwriteack;
if (not r.rfcnt(fabits)) = '1' then
v.rfwpnt := r.rfwpnt + 1; v.rfcnt := v.rfcnt + 1; v.writeok := '1';
vrxfi.write := '1';
else
v.writeok := '0';
end if;
end if;
--must be placed here because it uses variable
vrxfi.raddress := v.rfrpnt;
-------------------------------------------------------------------------------
-- MDIO INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--mdio commands
if enable_mdio = 1 then
mclk := r.mdioclk and not r.mdioclkold;
v.mdioclkold := r.mdioclk;
if r.mdccnt = "00000000" then
v.mdccnt := divisor;
v.mdioclk := not r.mdioclk;
else
v.mdccnt := r.mdccnt - 1;
end if;
mdioindex := conv_integer(r.cnt); v.mdioi := mdio_i;
if mclk = '1' then
case r.mdio_state is
when idle =>
v.cnt := (others => '0');
if r.mdio_ctrl.busy = '1' then
v.mdio_ctrl.linkfail := '0';
if r.mdio_ctrl.read = '1' then
v.mdio_ctrl.write := '0';
end if;
v.mdio_state := preamble; v.mdioo := '1';
if OEPOL = 0 then v.mdioen := '0'; else v.mdioen := '1'; end if;
end if;
when preamble =>
v.cnt := r.cnt + 1;
if r.cnt = "11111" then
v.mdioo := '0'; v.mdio_state := startst;
end if;
when startst =>
v.mdioo := '1'; v.mdio_state := op; v.cnt := (others => '0');
when op =>
v.mdio_state := op2;
if r.mdio_ctrl.read = '1' then v.mdioo := '1';
else v.mdioo := '0'; end if;
when op2 =>
v.mdioo := not r.mdioo; v.mdio_state := phyadr;
v.cnt := (others => '0');
when phyadr =>
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := r.mdio_ctrl.phyadr(4);
when 1 => v.mdioo := r.mdio_ctrl.phyadr(3);
when 2 => v.mdioo := r.mdio_ctrl.phyadr(2);
when 3 => v.mdioo := r.mdio_ctrl.phyadr(1);
when 4 => v.mdioo := r.mdio_ctrl.phyadr(0);
v.mdio_state := regadr; v.cnt := (others => '0');
when others => null;
end case;
when regadr =>
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := r.mdio_ctrl.regadr(4);
when 1 => v.mdioo := r.mdio_ctrl.regadr(3);
when 2 => v.mdioo := r.mdio_ctrl.regadr(2);
when 3 => v.mdioo := r.mdio_ctrl.regadr(1);
when 4 => v.mdioo := r.mdio_ctrl.regadr(0);
v.mdio_state := ta; v.cnt := (others => '0');
when others => null;
end case;
when ta =>
v.mdio_state := ta2;
if r.mdio_ctrl.read = '1' then
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
else v.mdioo := '1'; end if;
when ta2 =>
v.cnt := "01111"; v.mdio_state := ta3;
if r.mdio_ctrl.write = '1' then v.mdioo := '0'; v.mdio_state := data; end if;
when ta3 =>
v.mdio_state := data;
if r.mdioi /= '0' then
v.mdio_ctrl.linkfail := '1';
end if;
when data =>
v.cnt := r.cnt - 1;
if r.mdio_ctrl.read = '1' then
v.mdio_ctrl.data(mdioindex) := r.mdioi;
else
v.mdioo := r.mdio_ctrl.data(mdioindex);
end if;
if r.cnt = "00000" then
v.mdio_state := dataend;
end if;
when dataend =>
v.mdio_ctrl.busy := '0'; v.mdio_ctrl.read := '0';
v.mdio_ctrl.write := '0'; v.mdio_state := idle;
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
when others =>
null;
end case;
end if;
end if;
-------------------------------------------------------------------------------
-- EDCL -----------------------------------------------------------------------
-------------------------------------------------------------------------------
if (edcl /= 0) then
veri.renable := '1'; veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
swap := '0'; vrxenable := '1'; vecnt := conv_integer(r.ecnt); setmz := '0';
veri.datain := rxo.dataout;
if vrxwrite = '1' then
v.rxwriteack := not r.rxwriteack;
end if;
--edcl receiver
case r.edclrstate is
when idle =>
v.edclbcast := '0';
if rxstart = '1' then
v.edclrstate := wrda; v.edclactive := '0';
v.rcntm := conv_std_logic_vector(2, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
end if;
when wrda =>
if vrxwrite = '1' then
v.edclrstate := wrdsa;
veri.writem := '1'; veri.writel := '1';
swap := '1';
v.rcntm := r.rcntm - 2; v.rcntl := r.rcntl + 1;
if (macaddr(47 downto 16) /= rxo.dataout) and
(X"FFFFFFFF" /= rxo.dataout) then
v.edclrstate := spill;
elsif (X"FFFFFFFF" = rxo.dataout) then
v.edclbcast := '1';
end if;
if conv_integer(r.abufs) = wsz then
v.edclrstate := spill;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrdsa =>
if vrxwrite = '1' then
v.edclrstate := wrsa; swap := '1';
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl - 2;
if (macaddr(15 downto 0) /= rxo.dataout(31 downto 16)) and
(X"FFFF" /= rxo.dataout(31 downto 16)) then
v.edclrstate := spill;
elsif (X"FFFF" = rxo.dataout(31 downto 16)) then
v.edclbcast := r.edclbcast;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrsa =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.edclrstate := wrtype; swap := '1';
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 3;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrtype =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if X"0800" = rxo.dataout(31 downto 16) and (r.edclbcast = '0') then
v.edclrstate := ip;
elsif X"0806" = rxo.dataout(31 downto 16) and (r.edclbcast = '1') then
v.edclrstate := arp;
else
v.edclrstate := spill;
end if;
end if;
v.ecnt := (others => '0'); v.ipcrc := (others => '0');
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ip =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 1 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 2;
when 2 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl - 1;
when 3 =>
v.rcntm := r.rcntm - 1; v.rcntl := r.rcntl + 2;
when 4 =>
v.udpsrc := rxo.dataout(15 downto 0);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 1;
when 5 =>
setmz := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 6 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 7 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if (rxo.dataout(31 downto 18) = r.seq) then
v.seq := r.seq + 1; v.nak := '0';
else
v.nak := '1';
veri.datain(31 downto 18) := r.seq;
end if;
veri.datain(17) := v.nak; v.ewr := rxo.dataout(17);
if (rxo.dataout(17) or v.nak) = '1' then
veri.datain(16 downto 7) := (others => '0');
end if;
v.oplen := rxo.dataout(16 downto 7);
v.applength := "000000" & veri.datain(16 downto 7);
v.ipcrc :=
crcadder(v.applength + 38, r.ipcrc);
v.write(conv_integer(r.rpnt)) := rxo.dataout(17);
when 8 =>
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc :=
crcadder(ipcrctmp, ipcrctmp2);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
v.edclrstate := ipdata;
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ipdata =>
if (vrxwrite and r.ewr and not r.nak) = '1' and
(r.rcntm /= ebufmax) then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
end if;
if rxdone = '1' then
v.edclrstate := ipcrc; v.rcntm := conv_std_logic_vector(6, bpbits);
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc := crcadder(ipcrctmp, ipcrctmp2);
if conv_integer(v.rxstatus(3 downto 0)) /= 0 then
v.edclrstate := idle;
end if;
end if;
when ipcrc =>
veri.writem := '1'; veri.datain(31 downto 16) := not r.ipcrc(15 downto 0);
v.edclrstate := udp; v.rcntm := conv_std_logic_vector(9, bpbits);
v.rcntl := conv_std_logic_vector(9, bpbits);
when udp =>
veri.writem := '1'; veri.writel := '1';
v.edclrstate := iplength;
veri.datain(31 downto 16) := r.udpsrc;
veri.datain(15 downto 0) := r.applength + 18;
v.rcntm := conv_std_logic_vector(4, bpbits);
when iplength =>
veri.writem := '1';
veri.datain(31 downto 16) := r.applength + 38;
v.edclrstate := oplength;
v.rcntm := conv_std_logic_vector(10, bpbits);
v.rcntl := conv_std_logic_vector(10, bpbits);
when oplength =>
if rxstart = '0' then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
veri.writel := '1'; veri.writem := '1';
end if;
v.edclrstate := idle;
veri.datain(31 downto 0) := (others => '0');
veri.datain(15 downto 0) := "00000" & r.nak & r.oplen;
when arp =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.rcntm := r.rcntm + 4;
when 1 =>
swap := '1'; veri.writel := '0';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 4;
when 2 =>
swap := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 3 =>
swap := '1';
v.rcntm := r.rcntm - 4; v.rcntl := r.rcntl - 4;
when 4 =>
veri.datain := macaddr(31 downto 16) & macaddr(47 downto 32);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 5 =>
v.rcntl := r.rcntl + 1;
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := macaddr(15 downto 0);
if rxo.dataout(15 downto 0) /= r.edclip(31 downto 16) then
v.edclrstate := spill;
end if;
when 6 =>
swap := '1'; veri.writem := '0';
v.rcntm := conv_std_logic_vector(5, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
if rxo.dataout(31 downto 16) /= r.edclip(15 downto 0) then
v.edclrstate := spill;
else
v.edclactive := '1';
end if;
when 7 =>
veri.writem := '0';
veri.datain(15 downto 0) := macaddr(47 downto 32);
v.rcntl := r.rcntl + 1;
v.rcntm := conv_std_logic_vector(2, bpbits);
when 8 =>
v.edclrstate := arpop;
veri.datain := macaddr(31 downto 0);
v.rcntm := conv_std_logic_vector(5, bpbits);
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when arpop =>
veri.writem := '1'; veri.datain(31 downto 16) := X"0002";
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
if conv_integer(v.rxstatus) = 0 and (rxo.gotframe = '1') then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
end if;
end if;
when spill =>
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
end case;
--edcl transmitter
case r.txdstate is
when getlen =>
v.tcnt := r.tcnt + 1;
if conv_integer(r.tcnt) = 10 then
v.txlength := '0' & erdata(9 downto 0);
v.tnak := erdata(10);
v.txcnt := v.txlength;
if (r.write(conv_integer(r.tpnt)) or v.tnak) = '1' then
v.txlength := (others => '0');
end if;
end if;
if conv_integer(r.tcnt) = 11 then
v.txdstate := readhdr;
v.tcnt := (others => '0');
end if;
when readhdr =>
v.tcnt := r.tcnt + 1; vtxfi.write := '1';
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := v.tfcnt + 1;
vtxfi.datain := erdata;
if conv_integer(r.tcnt) = 12 then
v.txaddr := erdata(31 downto 2);
end if;
if conv_integer(r.tcnt) = 3 then
if erdata(31 downto 16) = X"0806" then
v.tarp := '1'; v.txlength := conv_std_logic_vector(42, 11);
else
v.tarp := '0'; v.txlength := r.txlength + 52;
end if;
end if;
if r.tarp = '0' then
if conv_integer(r.tcnt) = 12 then
v.txdstate := start;
end if;
else
if conv_integer(r.tcnt) = 10 then
v.txdstate := start;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when start =>
v.tmsto.addr := r.txaddr & "00";
v.tmsto.write := r.write(conv_integer(r.tpnt));
if (conv_integer(r.txcnt) = 0) or (r.tarp or r.tnak) = '1' then
v.tmsto.req := '0'; v.txdstate := etdone;
v.txstart_sync := not r.txstart_sync;
elsif r.write(conv_integer(r.tpnt)) = '0' then
v.txdstate := req; v.tedcl := '1';
else
v.txstart_sync := not r.txstart_sync;
v.txdstate := wrbus; v.tmsto.req := '1'; v.tedcl := '1';
v.tmsto.data := erdata; v.tcnt := r.tcnt + 1;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when wrbus =>
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready or tmsti.error) = '1' then
v.tmsto.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti.retry = '1' then
v.tmsto.addr := r.tmsto.addr - 4; v.tmsto.req := '1';
end if;
--if (txrestart or txdone) = '1' then
-- v.txdstate := etdone; v.tmsto.req := '0';
--end if;
when etdone =>
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
v.abufs := v.abufs - 1; v.tpnt := r.tpnt + 1;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
elsif txrestart = '1' then
v.txdstate := idle;
end if;
when others =>
null;
end case;
if swap = '1' then
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := rxo.dataout(31 downto 16);
end if;
if setmz = '1' then
veri.datain(31 downto 16) := (others => '0');
end if;
veri.raddress := r.tpnt & v.tcnt;
end if;
--edcl duplex mode read
if (rmii = 1) or (edcl /= 0) then
--edcl, gbit link mode check
case r.duplexstate is
when start =>
v.mdio_ctrl.regadr := r.regaddr;
v.mdio_ctrl.busy := '1'; v.duplexstate := waitop;
if (r.phywr or r.rstphy) = '1' then
v.mdio_ctrl.write := '1';
else
v.mdio_ctrl.read := '1';
end if;
if r.rstphy = '1' then
v.mdio_ctrl.data := X"9000";
end if;
when waitop =>
if r.mdio_ctrl.busy = '0' then
if r.mdio_ctrl.linkfail = '1' then
v.duplexstate := start;
elsif r.rstphy = '1' then
v.duplexstate := start; v.rstphy := '0';
else
v.duplexstate := nextop;
end if;
end if;
when nextop =>
case r.regaddr is
when "00000" =>
if r.mdio_ctrl.data(15) = '1' then --rst not finished
v.duplexstate := start;
elsif (r.phywr and not r.rstaneg) = '1' then --forced to 10 Mbit HD
v.duplexstate := selmode;
elsif r.mdio_ctrl.data(12) = '0' then --no auto neg
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := (others => '0');
else
v.duplexstate := start; v.regaddr := "00001";
end if;
if r.rstaneg = '1' then
v.phywr := '0';
end if;
when "00001" =>
v.ext := r.mdio_ctrl.data(8); --extended status register
v.extcap := r.mdio_ctrl.data(1); --extended register capabilities
v.duplexstate := start;
if r.mdio_ctrl.data(0) = '0' then
--no extended register capabilites, unable to read aneg config
--forcing 10 Mbit
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := (others => '0');
v.regaddr := (others => '0');
elsif (r.mdio_ctrl.data(8) and not r.rstaneg) = '1' then
--phy gbit capable, disable gbit
v.regaddr := "01001";
elsif r.mdio_ctrl.data(5) = '1' then --auto neg completed
v.regaddr := "00100";
end if;
when "00100" =>
v.duplexstate := start; v.regaddr := "00101";
v.capbil(4 downto 0) := r.mdio_ctrl.data(9 downto 5);
when "00101" =>
v.duplexstate := selmode;
v.capbil(4 downto 0) :=
r.capbil(4 downto 0) and r.mdio_ctrl.data(9 downto 5);
when "01001" =>
if r.phywr = '0' then
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data(9 downto 8) := (others => '0');
else
v.regaddr := "00000";
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := X"3300"; v.rstaneg := '1';
end if;
when others =>
null;
end case;
when selmode =>
v.duplexstate := done;
if r.phywr = '1' then
v.ctrl.full_duplex := '0'; v.ctrl.speed := '0';
else
sel_op_mode(r.capbil, v.ctrl.speed, v.ctrl.full_duplex);
end if;
when done =>
null;
end case;
end if;
--transmitter retry
if tmsti.retry = '1' then
v.tmsto.req := '1'; v.tmsto.addr := r.tmsto.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto.req := '0'; v.txdstate := ahberror;
end if;
--receiver retry
if rmsti.retry = '1' then
v.rmsto.req := '1'; v.rmsto.addr := r.rmsto.addr - 4;
v.rxburstcnt := r.rxburstcnt - 1;
end if;
------------------------------------------------------------------------------
-- RESET ----------------------------------------------------------------------
-------------------------------------------------------------------------------
if irst = '0' then
v.txdstate := idle; v.rxdstate := idle; v.rfrpnt := (others => '0');
v.tmsto.req := '0'; v.tmsto.req := '0'; v.rfwpnt := (others => '0');
v.rfcnt := (others => '0'); v.mdio_ctrl.read := '0';
v.mdio_ctrl.write := '0'; v.ctrl.txen := '0';
v.mdio_ctrl.busy := '0'; v.txirqgen := '0'; v.ctrl.rxen := '0';
v.mdio_ctrl.data := (others => '0');
v.mdio_ctrl.regadr := (others => '0');
v.txdsel := (others => '0'); v.txstart_sync := '0';
v.txread := (others => '0'); v.txrestart := (others => '0');
v.txdone := (others => '0'); v.txreadack := '0';
v.rxdsel := (others => '0'); v.rxdone := (others => '0');
v.rxdoneold := '0'; v.rxdoneack := '0'; v.rxwriteack := '0';
v.rxstart := (others => '0'); v.rxwrite := (others => '0');
v.mdio_ctrl.linkfail := '1'; v.ctrl.reset := '0';
v.status.invaddr := '0'; v.status.toosmall := '0';
v.ctrl.full_duplex := '0'; v.writeok := '0';
if (enable_mdio = 1) then
v.mdccnt := (others => '0'); v.mdioclk := '0';
v.mdio_state := idle;
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
if (edcl /= 0) then
v.tpnt := (others => '0'); v.rpnt := (others => '0');
v.tcnt := (others => '0'); v.edclactive := '0';
v.tarp := '0'; v.abufs := (others => '0');
v.edclrstate := idle;
end if;
if (rmii = 1) then
v.ctrl.speed := '1';
end if;
v.ctrl.tx_irqen := '0';
v.ctrl.rx_irqen := '0';
v.ctrl.prom := '0';
end if;
if edcl = 0 then
v.edclrstate := idle; v.edclactive := '0'; v.nak := '0'; v.ewr := '0';
v.write := (others => '0'); v.seq := (others => '0'); v.abufs := (others => '0');
v.tpnt := (others => '0'); v.rpnt := (others => '0'); v.tcnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0'); v.ipcrc := (others => '0');
v.applength := (others => '0'); v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0'); v.tarp := '0';
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
end if;
--some parts of edcl are only affected by hw reset
if rst = '0' then
v.edclip := conv_std_logic_vector(ipaddrh, 16) &
conv_std_logic_vector(ipaddrl, 16);
if edcl = 2 then v.edclip(3 downto 0) := edcladdr; end if;
v.duplexstate := start; v.regaddr := (others => '0');
v.phywr := '0'; v.rstphy := '1'; v.rstaneg := '0';
if phyrstadr /= 32 then
v.mdio_ctrl.phyadr := conv_std_logic_vector(phyrstadr, 5);
else
v.mdio_ctrl.phyadr := phyrstaddr;
end if;
v.seq := (others => '0');
end if;
-------------------------------------------------------------------------------
-- SIGNAL ASSIGNMENTS ---------------------------------------------------------
-------------------------------------------------------------------------------
rin <= v;
prdata <= vprdata;
irq <= vpirq;
--rx ahb fifo
rxrenable <= vrxfi.renable;
rxraddress(10 downto fabits) <= (others => '0');
rxraddress(fabits-1 downto 0) <= vrxfi.raddress;
rxwrite <= vrxfi.write;
rxwdata <= vrxfi.datain;
rxwaddress(10 downto fabits) <= (others => '0');
rxwaddress(fabits-1 downto 0) <= vrxfi.waddress;
--tx ahb fifo
txrenable <= vtxfi.renable;
txraddress(10 downto txfabits) <= (others => '0');
txraddress(txfabits-1 downto 0) <= vtxfi.raddress;
txwrite <= vtxfi.write;
txwdata <= vtxfi.datain;
txwaddress(10 downto txfabits) <= (others => '0');
txwaddress(txfabits-1 downto 0) <= vtxfi.waddress;
--edcl buf
erenable <= veri.renable;
eraddress(15 downto eabits) <= (others => '0');
eraddress(eabits-1 downto 0) <= veri.raddress;
ewritem <= veri.writem;
ewritel <= veri.writel;
ewaddressm(15 downto eabits) <= (others => '0');
ewaddressm(eabits-1 downto 0) <= veri.waddressm(eabits-1 downto 0);
ewaddressl(15 downto eabits) <= (others => '0');
ewaddressl(eabits-1 downto 0) <= veri.waddressl(eabits-1 downto 0);
ewdata <= veri.datain;
rxi.enable <= vrxenable;
end process;
rxi.writeack <= r.rxwriteack;
rxi.doneack <= r.rxdoneack;
rxi.speed <= r.ctrl.speed;
rxi.writeok <= r.writeok;
rxi.rxd <= rxd;
rxi.rx_dv <= rx_dv;
rxi.rx_crs <= rx_crs;
rxi.rx_er <= rx_er;
txi.rx_col <= rx_col;
txi.rx_crs <= rx_crs;
txi.full_duplex <= r.ctrl.full_duplex;
txi.start <= r.txstart_sync;
txi.readack <= r.txreadack;
txi.speed <= r.ctrl.speed;
txi.data <= r.txdata;
txi.valid <= r.txvalid;
txi.len <= r.txlength;
mdc <= r.mdioclk;
mdio_o <= r.mdioo;
mdio_oe <= r.mdioen;
tmsto <= r.tmsto;
rmsto <= r.rmsto;
txd <= txo.txd;
tx_en <= txo.tx_en;
tx_er <= txo.tx_er;
ahbmi.hgrant <= hgrant;
ahbmi.hready <= hready;
ahbmi.hresp <= hresp;
ahbmi.hrdata <= hrdata;
hbusreq <= ahbmo.hbusreq;
hlock <= ahbmo.hlock;
htrans <= ahbmo.htrans;
haddr <= ahbmo.haddr;
hwrite <= ahbmo.hwrite;
hsize <= ahbmo.hsize;
hburst <= ahbmo.hburst;
hprot <= ahbmo.hprot;
hwdata <= ahbmo.hwdata;
reset <= irst;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-------------------------------------------------------------------------------
-- TRANSMITTER-----------------------------------------------------------------
-------------------------------------------------------------------------------
tx_rmii0 : if rmii = 0 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii)
port map(
rst => arst,
clk => tx_clk,
txi => txi,
txo => txo);
end generate;
tx_rmii1 : if rmii = 1 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii)
port map(
rst => arst,
clk => rmii_clk,
txi => txi,
txo => txo);
end generate;
-------------------------------------------------------------------------------
-- RECEIVER -------------------------------------------------------------------
-------------------------------------------------------------------------------
rx_rmii0 : if rmii = 0 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii)
port map(
rst => arst,
clk => rx_clk,
rxi => rxi,
rxo => rxo);
end generate;
rx_rmii1 : if rmii = 1 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii)
port map(
rst => arst,
clk => rmii_clk,
rxi => rxi,
rxo => rxo);
end generate;
-------------------------------------------------------------------------------
-- AHB MST INTERFACE ----------------------------------------------------------
-------------------------------------------------------------------------------
ahb0 : eth_ahb_mst
port map(rst, clk, ahbmi, ahbmo, tmsto, tmsti, rmsto, rmsti);
end architecture;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/uart/uart1.in.vhd | 6 | 128 | -- UART 1
constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/techmap/proasic3/buffer_apa3.vhd | 2 | 2154 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkbuf_actel
-- File: clkbuf_actel.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock buffer generator for Actel devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library proasic3;
use proasic3.clkint;
-- pragma translate_on
entity clkbuf_apa3 is
generic(
buftype : integer range 0 to 3 := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkbuf_apa3 is
signal o2, no2, nin : std_ulogic;
component clkint port(a : in std_ulogic; y : out std_ulogic); end component;
attribute syn_maxfan : integer;
attribute syn_maxfan of o2 : signal is 10000;
begin
o <= o2;
buf0 : if buftype = 0 generate
o2 <= i;
end generate;
buf1 : if buftype = 1 generate
buf : clkint port map(A => i, Y => o2);
end generate;
buf2 : if buftype = 2 generate
buf : clkint port map(A => i, Y => o2);
end generate;
buf3 : if buftype > 2 generate
nin <= not i;
buf : clkint port map(A => nin, Y => no2);
o2 <= not no2;
end generate;
end architecture;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/misc/ps2.in.vhd | 2 | 79 | -- PS/2 interface
constant CFG_PS2_ENABLE : integer := CONFIG_PS2_ENABLE;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/spacewire/grspw2.vhd | 2 | 11651 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw2
-- File: grspw2.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: GRLIB wrapper for grspw core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.spacewire.all;
library spw;
use spw.spwcomp.all;
entity grspw2 is
generic(
tech : integer range 0 to NTECH := inferred;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
memtech : integer range 0 to NTECH := DEFMEMTECH
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type
);
end entity;
architecture rtl of grspw2 is
constant fabits1 : integer := log2(fifosize1);
constant fabits2 : integer := log2(fifosize2);
constant rfifo : integer := 5 + log2(rmapbufs);
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SPW2, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SPW2, 0, REVISION, pirq),
others => zero32);
signal rxclki, nrxclki, rxclko : std_logic_vector(1 downto 0);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(4 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(4 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(4 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(4 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--nchar fifo
signal ncrenable : std_ulogic;
signal ncraddress : std_logic_vector(5 downto 0);
signal ncwrite : std_ulogic;
signal ncwdata : std_logic_vector(8 downto 0);
signal ncwaddress : std_logic_vector(5 downto 0);
signal ncrdata : std_logic_vector(8 downto 0);
--rmap buf
signal rmrenable : std_ulogic;
signal rmraddress : std_logic_vector(7 downto 0);
signal rmwrite : std_ulogic;
signal rmwdata : std_logic_vector(7 downto 0);
signal rmwaddress : std_logic_vector(7 downto 0);
signal rmrdata : std_logic_vector(7 downto 0);
--misc
signal irq : std_ulogic;
signal rxclk, nrxclk : std_logic_vector(ports-1 downto 0);
begin
grspwc0 : grspwc2
generic map(
nsync => nsync,
rmap => rmap,
rmapcrc => rmapcrc,
fifosize1 => fifosize1,
fifosize2 => fifosize2,
rxunaligned => rxunaligned,
rmapbufs => rmapbufs,
scantest => scantest,
ports => ports,
dmachan => dmachan,
tech => tech)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => ahbmi.hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => ahbmo.hwdata,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--spw in
di => swni.d,
si => swni.s,
--spw out
do => swno.d,
so => swno.s,
--time iface
tickin => swni.tickin,
tickout => swno.tickout,
--clk bufs
rxclki => rxclki,
nrxclki => nrxclki,
rxclko => rxclko,
--irq
irq => irq,
--misc
clkdiv10 => swni.clkdiv10,
dcrstval => swni.dcrstval,
timerrstval => swni.timerrstval,
--rmapen
rmapen => swni.rmapen,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => swno.linkdis,
testclk => clk,
testrst => ahbmi.testrst,
testen => ahbmi.testen
);
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
ahbmo.hirq <= (others => '0');
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
ntst: if scantest = 0 generate
cbufloop : for i in 0 to ports-1 generate
rx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
port map(i => rxclko(i), o => rxclki(i));
end generate;
end generate;
tst: if scantest = 1 generate
cloop : for i in 0 to ports-1 generate
rxclk(i) <= clk when ahbmi.testen = '1' else rxclko(i);
nrxclk(i) <= clk when ahbmi.testen = '1' else not rxclko(i);
rx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
port map(i => rxclk(i), o => rxclki(i));
nrx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
port map(i => nrxclk(i), o => nrxclki(i));
end generate;
end generate;
------------------------------------------------------------------------------
-- FIFOS ---------------------------------------------------------------------
------------------------------------------------------------------------------
nft : if ft = 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap = 1) generate
ram0 : syncram_2p generic map(memtech, rfifo, 8)
port map(clk, rmrenable, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
ft1 : if ft /= 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap = 1) generate
ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
port map(clk, rmrenable, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
-- pragma translate_off
msg0 : if (rmap = 0) generate
bootmsg : report_version
generic map ("grspw" & tost(pindex) &
": Spacewire link rev " & tost(REVISION) & ", AHB fifos 2x" &
tost(fifosize1*4) & " bytes, rx fifo " & tost(fifosize2) &
" bytes, irq " & tost(pirq));
end generate;
msg1 : if (rmap = 1) generate
bootmsg : report_version
generic map ("grspw" & tost(pindex) &
": Spacewire link rev " & tost(REVISION) & ", AHB fifos 2x " &
tost(fifosize1*4) & " bytes, rx fifo " & tost(fifosize2) &
" bytes, irq " & tost(pirq) & " , RMAP Buffer " &
tost(rmapbufs*32) & " bytes");
end generate;
-- pragma translate_on
end architecture;
| mit |
franz/pocl | examples/accel/rtl/vhdl/fu_alu_comp.vhd | 2 | 19381 | -- Module generated by TTA Codesign Environment
--
-- Generated on Sun Jul 7 16:19:19 2019
--
-- Function Unit: alu_comp
--
-- Operations:
-- add : 0
-- and : 1
-- eq : 2
-- gt : 3
-- gtu : 4
-- ior : 5
-- mul : 6
-- shl : 7
-- shr : 8
-- shru : 9
-- sub : 10
-- xor : 11
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity fu_alu_comp is
port (
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
glockreq_out : out std_logic;
operation_in : in std_logic_vector(4-1 downto 0);
data_in1t_in : in std_logic_vector(32-1 downto 0);
load_in1t_in : in std_logic;
data_in2_in : in std_logic_vector(32-1 downto 0);
load_in2_in : in std_logic;
data_out1_out : out std_logic_vector(32-1 downto 0);
data_out2_out : out std_logic_vector(32-1 downto 0);
data_out3_out : out std_logic_vector(32-1 downto 0));
end entity fu_alu_comp;
architecture rtl of fu_alu_comp is
constant op_add_c : std_logic_vector(3 downto 0) := "0000";
constant op_and_c : std_logic_vector(3 downto 0) := "0001";
constant op_eq_c : std_logic_vector(3 downto 0) := "0010";
constant op_gt_c : std_logic_vector(3 downto 0) := "0011";
constant op_gtu_c : std_logic_vector(3 downto 0) := "0100";
constant op_ior_c : std_logic_vector(3 downto 0) := "0101";
constant op_mul_c : std_logic_vector(3 downto 0) := "0110";
constant op_shl_c : std_logic_vector(3 downto 0) := "0111";
constant op_shr_c : std_logic_vector(3 downto 0) := "1000";
constant op_shru_c : std_logic_vector(3 downto 0) := "1001";
constant op_sub_c : std_logic_vector(3 downto 0) := "1010";
constant op_xor_c : std_logic_vector(3 downto 0) := "1011";
signal operation : std_logic_vector(3 downto 0);
signal mul_dsp_2cycle_1_clk : std_logic;
signal mul_dsp_2cycle_1_rstx : std_logic;
signal mul_dsp_2cycle_1_glock_in : std_logic;
signal mul_dsp_2cycle_1_load_in : std_logic;
signal mul_dsp_2cycle_1_operand_a_in : std_logic_vector(31+1-1 downto 0);
signal mul_dsp_2cycle_1_operand_b_in : std_logic_vector(31+1-1 downto 0);
signal mul_dsp_2cycle_1_operand_c_in : std_logic_vector(31+1-1 downto 0);
signal mul_dsp_2cycle_1_result_out : std_logic_vector(31+1-1 downto 0);
signal generic_sru_1_clk : std_logic;
signal generic_sru_1_opa_i : std_logic_vector(31+1-1 downto 0);
signal generic_sru_1_opb_i : std_logic_vector(31+1-1 downto 0);
signal generic_sru_1_shift_dir_i : std_logic;
signal generic_sru_1_arith_shift_i : std_logic;
signal generic_sru_1_rnd_en_i : std_logic;
signal generic_sru_1_rnd_mode_i : std_logic;
signal generic_sru_1_data_o : std_logic_vector(31+1-1 downto 0);
signal add_op1 : std_logic_vector(31 downto 0);
signal add_op2 : std_logic_vector(31 downto 0);
signal add_op3 : std_logic_vector(31 downto 0);
signal and_op1 : std_logic_vector(31 downto 0);
signal and_op2 : std_logic_vector(31 downto 0);
signal and_op3 : std_logic_vector(31 downto 0);
signal eq_op1 : std_logic_vector(31 downto 0);
signal eq_op2 : std_logic_vector(31 downto 0);
signal eq_op3 : std_logic;
signal gt_op1 : std_logic_vector(31 downto 0);
signal gt_op2 : std_logic_vector(31 downto 0);
signal gt_op3 : std_logic;
signal gtu_op1 : std_logic_vector(31 downto 0);
signal gtu_op2 : std_logic_vector(31 downto 0);
signal gtu_op3 : std_logic;
signal ior_op1 : std_logic_vector(31 downto 0);
signal ior_op2 : std_logic_vector(31 downto 0);
signal ior_op3 : std_logic_vector(31 downto 0);
signal mul_op1 : std_logic_vector(31 downto 0);
signal mul_op2 : std_logic_vector(31 downto 0);
signal mul_op3 : std_logic_vector(31 downto 0);
signal shl_op1 : std_logic_vector(31 downto 0);
signal shl_op2 : std_logic_vector(4 downto 0);
signal shl_op3 : std_logic_vector(31 downto 0);
signal shr_op1 : std_logic_vector(31 downto 0);
signal shr_op2 : std_logic_vector(4 downto 0);
signal shr_op3 : std_logic_vector(31 downto 0);
signal shru_op1 : std_logic_vector(31 downto 0);
signal shru_op2 : std_logic_vector(4 downto 0);
signal shru_op3 : std_logic_vector(31 downto 0);
signal sub_op1 : std_logic_vector(31 downto 0);
signal sub_op2 : std_logic_vector(31 downto 0);
signal sub_op3 : std_logic_vector(31 downto 0);
signal xor_op1 : std_logic_vector(31 downto 0);
signal xor_op2 : std_logic_vector(31 downto 0);
signal xor_op3 : std_logic_vector(31 downto 0);
signal data_in1t : std_logic_vector(31 downto 0);
signal data_in2 : std_logic_vector(31 downto 0);
signal shadow_in2_r : std_logic_vector(31 downto 0);
signal operation_1_r : std_logic_vector(3 downto 0);
signal optrig_1_r : std_logic;
signal operation_2_r : std_logic_vector(3 downto 0);
signal optrig_2_r : std_logic;
signal data_in1t_1_r : std_logic_vector(31 downto 0);
signal data_in2_1_r : std_logic_vector(31 downto 0);
signal trigger_in1t_1_r : std_logic;
signal trigger_in2_1_r : std_logic;
signal data_in1t_2_r : std_logic_vector(31 downto 0);
signal data_in1t_3_r : std_logic_vector(31 downto 0);
signal trigger_in1t_2_r : std_logic;
signal data_in2_2_r : std_logic_vector(31 downto 0);
signal data_in2_3_r : std_logic_vector(31 downto 0);
signal trigger_in2_2_r : std_logic;
signal optrig_3_r : std_logic;
signal operation_3_r : std_logic_vector(3 downto 0);
signal data_out1_out_r : std_logic_vector(31 downto 0);
signal data_out2_out_r : std_logic_vector(31 downto 0);
signal data_out3_out_r : std_logic_vector(31 downto 0);
component mul_dsp48 is
generic (
latency_g : integer);
port (
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
load_in : in std_logic;
operand_a_in : in std_logic_vector(31+1-1 downto 0);
operand_b_in : in std_logic_vector(31+1-1 downto 0);
operand_c_in : in std_logic_vector(31+1-1 downto 0);
result_out : out std_logic_vector(31+1-1 downto 0));
end component mul_dsp48;
component generic_sru is
port (
clk : in std_logic;
opa_i : in std_logic_vector(31+1-1 downto 0);
opb_i : in std_logic_vector(31+1-1 downto 0);
shift_dir_i : in std_logic;
arith_shift_i : in std_logic;
rnd_en_i : in std_logic;
rnd_mode_i : in std_logic;
data_o : out std_logic_vector(31+1-1 downto 0));
end component generic_sru;
begin
mul_dsp_2cycle_1 : mul_dsp48
generic map (
latency_g => 2)
port map (
clk => clk,
rstx => rstx,
glock_in => mul_dsp_2cycle_1_glock_in,
load_in => mul_dsp_2cycle_1_load_in,
operand_a_in => mul_dsp_2cycle_1_operand_a_in,
operand_b_in => mul_dsp_2cycle_1_operand_b_in,
operand_c_in => mul_dsp_2cycle_1_operand_c_in,
result_out => mul_dsp_2cycle_1_result_out);
generic_sru_1 : generic_sru
port map (
clk => clk,
opa_i => generic_sru_1_opa_i,
opb_i => generic_sru_1_opb_i,
shift_dir_i => generic_sru_1_shift_dir_i,
arith_shift_i => generic_sru_1_arith_shift_i,
rnd_en_i => generic_sru_1_rnd_en_i,
rnd_mode_i => generic_sru_1_rnd_mode_i,
data_o => generic_sru_1_data_o);
add_op1 <= data_in1t_1_r;
add_op2 <= data_in2_1_r;
and_op1 <= data_in2_1_r;
and_op2 <= data_in1t_1_r;
eq_op1 <= data_in1t_1_r;
eq_op2 <= data_in2_1_r;
gt_op1 <= data_in1t_1_r;
gt_op2 <= data_in2_1_r;
gtu_op1 <= data_in1t_1_r;
gtu_op2 <= data_in2_1_r;
ior_op1 <= data_in2_1_r;
ior_op2 <= data_in1t_1_r;
mul_op1 <= data_in2_1_r;
mul_op2 <= data_in1t_1_r;
shl_op1 <= data_in1t_2_r;
shl_op2 <= data_in2_2_r(4 downto 0);
shr_op1 <= data_in1t_2_r;
shr_op2 <= data_in2_2_r(4 downto 0);
shru_op1 <= data_in1t_2_r;
shru_op2 <= data_in2_2_r(4 downto 0);
sub_op1 <= data_in1t_1_r;
sub_op2 <= data_in2_1_r;
xor_op1 <= data_in2_1_r;
xor_op2 <= data_in1t_1_r;
data_in1t <= data_in1t_in;
shadow_in2_sp : process(clk, rstx)
begin
if rstx = '0' then
shadow_in2_r <= (others => '0');
elsif clk = '1' and clk'event then
if ((glock_in = '0') and (load_in2_in = '1')) then
shadow_in2_r <= data_in2_in;
end if;
end if;
end process shadow_in2_sp;
shadow_in2_cp : process(shadow_in2_r, data_in2_in, load_in2_in, load_in1t_in)
begin
if ((load_in1t_in = '1') and (load_in2_in = '1')) then
data_in2 <= data_in2_in;
else
data_in2 <= shadow_in2_r;
end if;
end process shadow_in2_cp;
operations_actual_cp : process(operation_2_r, shru_op2, shr_op2, generic_sru_1_data_o, shl_op2, eq_op2, eq_op1, ior_op2, and_op2, and_op1, add_op2, add_op1, gt_op2, xor_op2, glock_in, mul_op1, operation_1_r, mul_dsp_2cycle_1_result_out, mul_op2, xor_op1, gt_op1, gtu_op1, shru_op1, gtu_op2, ior_op1, sub_op2, sub_op1, shr_op1, shl_op1)
begin
add_op3 <= (others => '-');
and_op3 <= (others => '-');
eq_op3 <= '-';
gt_op3 <= '-';
gtu_op3 <= '-';
ior_op3 <= (others => '-');
mul_op3 <= (others => '-');
shl_op3 <= (others => '-');
shr_op3 <= (others => '-');
shru_op3 <= (others => '-');
sub_op3 <= (others => '-');
xor_op3 <= (others => '-');
add_op3 <= (others => '-');
and_op3 <= (others => '-');
eq_op3 <= '-';
eq_op3 <= '-';
gt_op3 <= '-';
gt_op3 <= '-';
gtu_op3 <= '-';
gtu_op3 <= '-';
ior_op3 <= (others => '-');
mul_dsp_2cycle_1_glock_in <= '-';
mul_op3 <= (others => '-');
mul_dsp_2cycle_1_load_in <= '-';
mul_dsp_2cycle_1_operand_a_in <= (others => '-');
mul_dsp_2cycle_1_operand_b_in <= (others => '-');
mul_dsp_2cycle_1_operand_c_in <= (others => '-');
mul_dsp_2cycle_1_load_in <= '-';
mul_dsp_2cycle_1_glock_in <= glock_in;
mul_op3 <= mul_dsp_2cycle_1_result_out;
mul_dsp_2cycle_1_load_in <= '0';
sub_op3 <= (others => '-');
xor_op3 <= (others => '-');
case operation_1_r is
when op_add_c =>
add_op3 <= std_logic_vector(signed(add_op1) + signed(add_op2));
when op_and_c =>
and_op3 <= and_op1 and and_op2;
when op_eq_c =>
if eq_op1 = eq_op2 then
eq_op3 <= '1';
else
eq_op3 <= '0';
end if;
when op_gt_c =>
if signed(gt_op1) > signed(gt_op2) then
gt_op3 <= '1';
else
gt_op3 <= '0';
end if;
when op_gtu_c =>
if unsigned(gtu_op1) > unsigned(gtu_op2) then
gtu_op3 <= '1';
else
gtu_op3 <= '0';
end if;
when op_ior_c =>
ior_op3 <= ior_op1 or ior_op2;
when op_mul_c =>
mul_dsp_2cycle_1_operand_a_in <= mul_op1;
mul_dsp_2cycle_1_operand_b_in <= mul_op2;
mul_dsp_2cycle_1_operand_c_in <= (others => '0');
mul_dsp_2cycle_1_load_in <= '1';
when op_sub_c =>
sub_op3 <= std_logic_vector(signed(sub_op1) - signed(sub_op2));
when op_xor_c =>
xor_op3 <= xor_op1 xor xor_op2;
when others =>
end case;
generic_sru_1_opa_i <= (others => '-');
generic_sru_1_opb_i <= (others => '-');
generic_sru_1_shift_dir_i <= '-';
generic_sru_1_arith_shift_i <= '-';
generic_sru_1_rnd_en_i <= '-';
generic_sru_1_rnd_mode_i <= '-';
shl_op3 <= (others => '-');
generic_sru_1_opa_i <= (others => '-');
generic_sru_1_opb_i <= (others => '-');
generic_sru_1_shift_dir_i <= '-';
generic_sru_1_arith_shift_i <= '-';
generic_sru_1_rnd_en_i <= '-';
generic_sru_1_rnd_mode_i <= '-';
shr_op3 <= (others => '-');
generic_sru_1_opa_i <= (others => '-');
generic_sru_1_opb_i <= (others => '-');
generic_sru_1_shift_dir_i <= '-';
generic_sru_1_arith_shift_i <= '-';
generic_sru_1_rnd_en_i <= '-';
generic_sru_1_rnd_mode_i <= '-';
shru_op3 <= (others => '-');
case operation_2_r is
when op_shl_c =>
generic_sru_1_opa_i <= shl_op1;
generic_sru_1_opb_i <= "000000000000000000000000000" & shl_op2;
generic_sru_1_shift_dir_i <= '1'; -- 0: right, 1: left (shift dreiction)
generic_sru_1_arith_shift_i <= '0'; -- 0: logical, 1: arithmetical (only for right shifts)
generic_sru_1_rnd_en_i <= '0';
generic_sru_1_rnd_mode_i <= '0';
shl_op3 <= generic_sru_1_data_o;
when op_shr_c =>
generic_sru_1_opa_i <= shr_op1;
generic_sru_1_opb_i <= "000000000000000000000000000" & shr_op2;
generic_sru_1_shift_dir_i <= '0'; -- 0: right, 1: left (shift dreiction)
generic_sru_1_arith_shift_i <= '1'; -- 0: logical, 1: arithmetical (only for right shifts)
generic_sru_1_rnd_en_i <= '0';
generic_sru_1_rnd_mode_i <= '0';
shr_op3 <= generic_sru_1_data_o;
when op_shru_c =>
generic_sru_1_opa_i <= shru_op1;
generic_sru_1_opb_i <= "000000000000000000000000000" & shru_op2;
generic_sru_1_shift_dir_i <= '0'; -- 0: right, 1: left (shift dreiction)
generic_sru_1_arith_shift_i <= '0'; -- 0: logical, 1: arithmetical (only for right shifts)
generic_sru_1_rnd_en_i <= '0';
generic_sru_1_rnd_mode_i <= '0';
shru_op3 <= generic_sru_1_data_o;
when others =>
end case;
end process operations_actual_cp;
operation <= operation_3_r;
operation_input_sp : process(clk, rstx)
begin
if rstx = '0' then
data_in2_1_r <= (others => '0');
data_in1t_1_r <= (others => '0');
operation_1_r <= (others => '0');
operation_3_r <= (others => '0');
optrig_3_r <= '0';
trigger_in2_2_r <= '0';
data_in1t_2_r <= (others => '0');
data_in2_3_r <= (others => '0');
trigger_in2_1_r <= '0';
trigger_in1t_2_r <= '0';
data_in2_2_r <= (others => '0');
operation_2_r <= (others => '0');
trigger_in1t_1_r <= '0';
data_in1t_3_r <= (others => '0');
optrig_1_r <= '0';
optrig_2_r <= '0';
elsif clk = '1' and clk'event then
if (glock_in = '0') then
trigger_in1t_1_r <= load_in1t_in;
trigger_in1t_2_r <= trigger_in1t_1_r;
trigger_in2_1_r <= load_in1t_in;
trigger_in2_2_r <= trigger_in2_1_r;
if (trigger_in1t_1_r = '1') then
data_in1t_2_r <= data_in1t_1_r;
end if;
if (trigger_in1t_2_r = '1') then
data_in1t_3_r <= data_in1t_2_r;
end if;
if (trigger_in2_1_r = '1') then
data_in2_2_r <= data_in2_1_r;
end if;
if (trigger_in2_2_r = '1') then
data_in2_3_r <= data_in2_2_r;
end if;
optrig_1_r <= '0';
optrig_2_r <= optrig_1_r;
if (optrig_1_r = '1') then
operation_2_r <= operation_1_r;
end if;
optrig_3_r <= optrig_2_r;
if (optrig_2_r = '1') then
operation_3_r <= operation_2_r;
end if;
end if;
if ((glock_in = '0') and (load_in1t_in = '1')) then
case operation_in is
when op_add_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_and_c =>
operation_1_r <= operation_in;
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
when op_eq_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_gt_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_gtu_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_ior_c =>
operation_1_r <= operation_in;
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
when op_mul_c =>
operation_1_r <= operation_in;
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
when op_shl_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_shr_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_shru_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_sub_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_xor_c =>
operation_1_r <= operation_in;
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
when others =>
end case;
end if;
end if;
end process operation_input_sp;
data_out1_out <= data_out1_out_r;
data_out2_out <= data_out2_out_r;
data_out3_out <= data_out3_out_r;
operations_output_sp : process(clk, rstx)
begin
if rstx = '0' then
data_out3_out_r <= (others => '0');
data_out2_out_r <= (others => '0');
data_out1_out_r <= (others => '0');
elsif clk = '1' and clk'event then
if ((glock_in = '0') and (optrig_1_r = '1')) then
case operation_1_r is
when op_add_c =>
data_out1_out_r <= add_op3;
when op_and_c =>
data_out1_out_r <= and_op3;
when op_eq_c =>
data_out1_out_r <= ((32-1 downto 1 => '0') & eq_op3);
when op_gt_c =>
data_out1_out_r <= ((32-1 downto 1 => '0') & gt_op3);
when op_gtu_c =>
data_out1_out_r <= ((32-1 downto 1 => '0') & gtu_op3);
when op_ior_c =>
data_out1_out_r <= ior_op3;
when op_sub_c =>
data_out1_out_r <= sub_op3;
when op_xor_c =>
data_out1_out_r <= xor_op3;
when others =>
end case;
end if;
if ((glock_in = '0') and (optrig_2_r = '1')) then
case operation_2_r is
when op_shl_c =>
data_out2_out_r <= shl_op3;
when op_shr_c =>
data_out2_out_r <= shr_op3;
when op_shru_c =>
data_out2_out_r <= shru_op3;
when others =>
end case;
end if;
if ((glock_in = '0') and (optrig_3_r = '1')) then
case operation_3_r is
when op_mul_c =>
data_out3_out_r <= mul_op3;
when others =>
end case;
end if;
end if;
end process operations_output_sp;
glockreq_out <= '0';
end architecture rtl;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/techmap/maps/allclkgen.vhd | 2 | 10347 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: libclk
-- File: libclk.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock generator interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allclkgen is
component clkgen_virtex
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_virtex2
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_spartan3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex5
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_axcelerator
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_altera_mf
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_cycloneiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_rh_lib18t
generic (
clk_mul : integer := 1;
clk_div : integer := 1);
port (
rst : in std_logic;
clkin : in std_logic;
clk : out std_logic;
sdclk : out std_logic; -- SDRAM clock
clk2x : out std_logic;
clk4x : out std_logic
);
end component;
component clkmul_virtex2
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end component;
component clkand_unisim
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut025crh
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_unisim
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_proasic3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000); -- clock frequency in KHz
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component stratix3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_dare
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic); -- unscaled 2X clock
end component;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/techmap/axcelerator/clkgen_axcelerator.vhd | 2 | 2865 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkgen_actel
-- File: clkgen_actel.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Clock generator for Actel fpga
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library axcelerator;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_axcelerator is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture struct of clkgen_axcelerator is
component hclkbuf
port( pad : in std_logic; y : out std_logic); end component;
component hclkbuf_pci
port( pad : in std_logic; y : out std_logic); end component;
signal clkint, pciclkint : std_ulogic;
begin
c0 : if (PCIEN = 0) or (PCISYSCLK=0) generate
u0 : hclkbuf port map (pad => clkin, y => clkint);
clk <= clkint;
clkn <= not clkint;
end generate;
c2 : if PCIEN/=0 generate
c1 : if PCISYSCLK=1 generate
clk <= pciclkint;
clkn <= not pciclkint;
end generate;
u0 : hclkbuf_pci port map (pad => pciclkin, y => pciclkint);
pciclk <= pciclkint;
end generate;
cgo.pcilock <= '1';
cgo.clklock <= '1';
sdclk <= '0';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_axcelerator" & ": using HCLKBUF as clock buffer");
-- pragma translate_on
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/sim/phy.vhd | 2 | 23511 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: phy
-- File: phy.vhd
-- Description: Simulation model of an Ethernet PHY
-- Author: Marko Isomaki
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
entity phy is
generic(
address : integer range 0 to 31 := 0;
extended_regs : integer range 0 to 1 := 1;
aneg : integer range 0 to 1 := 1;
base100_t4 : integer range 0 to 1 := 0;
base100_x_fd : integer range 0 to 1 := 1;
base100_x_hd : integer range 0 to 1 := 1;
fd_10 : integer range 0 to 1 := 1;
hd_10 : integer range 0 to 1 := 1;
base100_t2_fd : integer range 0 to 1 := 1;
base100_t2_hd : integer range 0 to 1 := 1;
base1000_x_fd : integer range 0 to 1 := 0;
base1000_x_hd : integer range 0 to 1 := 0;
base1000_t_fd : integer range 0 to 1 := 1;
base1000_t_hd : integer range 0 to 1 := 1
);
port(
rstn : in std_logic;
mdio : inout std_logic;
tx_clk : out std_logic;
rx_clk : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
mdc : in std_logic;
gtx_clk : in std_logic
);
end;
architecture behavioral of phy is
type mdio_state_type is (idle, start_of_frame, start_of_frame2, op, phyad, regad,
ta, rdata, wdata);
type ctrl_reg_type is record
reset : std_ulogic;
loopback : std_ulogic;
speedsel : std_logic_vector(1 downto 0);
anegen : std_ulogic;
powerdown : std_ulogic;
isolate : std_ulogic;
restartaneg : std_ulogic;
duplexmode : std_ulogic;
coltest : std_ulogic;
end record;
type status_reg_type is record
base100_t4 : std_ulogic;
base100_x_fd : std_ulogic;
base100_x_hd : std_ulogic;
fd_10 : std_ulogic;
hd_10 : std_ulogic;
base100_t2_fd : std_ulogic;
base100_t2_hd : std_ulogic;
extstat : std_ulogic;
mfpreamblesup : std_ulogic;
anegcmpt : std_ulogic;
remfault : std_ulogic;
anegability : std_ulogic;
linkstat : std_ulogic;
jabdetect : std_ulogic;
extcap : std_ulogic;
end record;
type aneg_ab_type is record
next_page : std_ulogic;
remote_fault : std_ulogic;
tech_ability : std_logic_vector(7 downto 0);
selector : std_logic_vector(4 downto 0);
end record;
type aneg_exp_type is record
par_detct_flt : std_ulogic;
lp_np_able : std_ulogic;
np_able : std_ulogic;
page_rx : std_ulogic;
lp_aneg_able : std_ulogic;
end record;
type aneg_nextpage_type is record
next_page : std_ulogic;
message_page : std_ulogic;
ack2 : std_ulogic;
toggle : std_ulogic;
message : std_logic_vector(10 downto 0);
end record;
type mst_slv_ctrl_type is record
tmode : std_logic_vector(2 downto 0);
manualcfgen : std_ulogic;
cfgval : std_ulogic;
porttype : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type mst_slv_status_type is record
cfgfault : std_ulogic;
cfgres : std_ulogic;
locrxstate : std_ulogic;
remrxstate : std_ulogic;
lpbase1000_t_fd : std_ulogic;
lpbase1000_t_hd : std_ulogic;
idlerrcnt : std_logic_vector(7 downto 0);
end record;
type extended_status_reg_type is record
base1000_x_fd : std_ulogic;
base1000_x_hd : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type reg_type is record
state : mdio_state_type;
cnt : integer;
op : std_logic_vector(1 downto 0);
phyad : std_logic_vector(4 downto 0);
regad : std_logic_vector(4 downto 0);
wr : std_ulogic;
regtmp : std_logic_vector(15 downto 0);
-- MII management registers
ctrl : ctrl_reg_type;
status : status_reg_type;
anegadv : aneg_ab_type;
aneglp : aneg_ab_type;
anegexp : aneg_exp_type;
anegnptx : aneg_nextpage_type;
anegnplp : aneg_nextpage_type;
mstslvctrl : mst_slv_ctrl_type;
mstslvstat : mst_slv_status_type;
extstatus : extended_status_reg_type;
rstcnt : integer;
anegcnt : integer;
end record;
signal r, rin : reg_type;
signal int_clk : std_ulogic := '0';
signal clkslow : std_ulogic := '0';
signal rcnt : integer;
signal anegact : std_ulogic;
begin
--mdio signal pull-up
int_clk <= not int_clk after 8 ns when r.ctrl.speedsel = "01" else
not int_clk after 40 ns when r.ctrl.speedsel = "10" else
not int_clk after 400 ns when r.ctrl.speedsel = "00";
clkslow <= not clkslow after 40 ns when r.ctrl.speedsel = "10" else
not clkslow after 400 ns;
-- rstdelay : process
-- begin
-- loop
-- rstd <= '0';
-- while r.ctrl.reset /= '1' loop
-- wait on r.ctrl.reset;
-- end loop;
-- rstd <= '1';
-- while rstn = '0' loop
-- wait on rstn;
-- end loop;
-- wait on rstn for 3 us;
-- rstd <= '0';
-- wait on rstn until r.ctrl.reset = '0' for 5 us;
-- end loop;
-- end process;
anegproc : process is
begin
loop
anegact <= '0';
while rstn /= '1' loop
wait on rstn;
end loop;
while rstn = '1' loop
if r.ctrl.anegen = '0' then
anegact <= '0';
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
else
if r.ctrl.restartaneg = '1' then
anegact <= '1';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen for 2 us;
anegact <= '0';
wait on rstn, r.ctrl.anegen until r.ctrl.restartaneg = '0';
if (rstn and r.ctrl.anegen) = '1' then
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
end if;
else
anegact <= '0';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen;
end if;
end if;
end loop;
end loop;
end process;
mdiocomb : process(rstn, r, anegact, mdio) is
variable v : reg_type;
begin
v := r;
if anegact = '0' then
v.ctrl.restartaneg := '0';
end if;
case r.state is
when idle =>
mdio <= 'Z';
if to_X01(mdio) = '1' then
v.cnt := v.cnt + 1;
if v.cnt = 31 then
v.state := start_of_frame; v.cnt := 0;
end if;
else
v.cnt := 0;
end if;
when start_of_frame =>
if to_X01(mdio) = '0' then
v.state := start_of_frame2;
elsif to_X01(mdio) /= '1' then
v.state := idle;
end if;
when start_of_frame2 =>
if to_X01(mdio) = '1' then
v.state := op;
else
v.state := idle;
end if;
when op =>
v.cnt := v.cnt + 1;
v.op := r.op(0) & to_X01(mdio);
if r.cnt = 1 then
if (v.op = "01") or (v.op = "10") then
v.state := phyad; v.cnt := 0;
else
v.state := idle; v.cnt := 0;
end if;
end if;
when phyad =>
v.phyad := r.phyad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.state := regad; v.cnt := 0;
end if;
when regad =>
v.regad := r.regad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.cnt := 0;
if conv_integer(r.phyad) = address then
v.state := ta;
else
v.state := idle;
end if;
end if;
when ta =>
v.cnt := r.cnt + 1;
if r.cnt = 0 then
if (r.op = "01") and to_X01(mdio) /= '1' then
v.cnt := 0; v.state := idle;
end if;
else
if r.op = "10" then
mdio <= '0'; v.cnt := 0; v.state := rdata;
case r.regad is
when "00000" => --ctrl (basic)
v.regtmp := r.ctrl.reset & r.ctrl.loopback &
r.ctrl.speedsel(1) & r.ctrl.anegen & r.ctrl.powerdown &
r.ctrl.isolate & r.ctrl.restartaneg & r.ctrl.duplexmode &
r.ctrl.coltest & r.ctrl.speedsel(0) & "000000";
when "00001" => --statuc (basic)
v.regtmp := r.status.base100_t4 & r.status.base100_x_fd &
r.status.base100_x_hd & r.status.fd_10 & r.status.hd_10 &
r.status.base100_t2_fd & r.status.base100_t2_hd &
r.status.extstat & '0' & r.status.mfpreamblesup &
r.status.anegcmpt & r.status.remfault & r.status.anegability &
r.status.linkstat & r.status.jabdetect & r.status.extcap;
when "00010" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"BBCD";
else
v.cnt := 0; v.state := idle;
end if;
when "00011" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"9C83";
else
v.cnt := 0; v.state := idle;
end if;
when "00100" => --Auto-neg adv. (extended)
if extended_regs = 1 then
v.regtmp := r.anegadv.next_page & '0' & r.anegadv.remote_fault &
r.anegadv.tech_ability & r.anegadv.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00101" => --Auto-neg link partner ability (extended)
if extended_regs = 1 then
v.regtmp := r.aneglp.next_page & '0' & r.aneglp.remote_fault &
r.aneglp.tech_ability & r.aneglp.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00110" => --Auto-neg expansion (extended)
if extended_regs = 1 then
v.regtmp := "00000000000" & r.anegexp.par_detct_flt &
r.anegexp.lp_np_able & r.anegexp.np_able & r.anegexp.page_rx &
r.anegexp.lp_aneg_able;
else
v.cnt := 0; v.state := idle;
end if;
when "00111" => --Auto-neg next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnptx.next_page & '0' & r.anegnptx.message_page &
r.anegnptx.ack2 & r.anegnptx.toggle & r.anegnptx.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01000" => --Auto-neg link partner received next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnplp.next_page & '0' & r.anegnplp.message_page &
r.anegnplp.ack2 & r.anegnplp.toggle & r.anegnplp.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01001" => --Master-slave control (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvctrl.tmode & r.mstslvctrl.manualcfgen &
r.mstslvctrl.cfgval & r.mstslvctrl.porttype &
r.mstslvctrl.base1000_t_fd & r.mstslvctrl.base1000_t_hd &
"00000000";
else
v.cnt := 0; v.state := idle;
end if;
when "01010" => --Master-slave status (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvstat.cfgfault & r.mstslvstat.cfgres &
r.mstslvstat.locrxstate & r.mstslvstat.remrxstate &
r.mstslvstat.lpbase1000_t_fd & r.mstslvstat.lpbase1000_t_hd &
"00" & r.mstslvstat.idlerrcnt;
else
v.cnt := 0; v.state := idle;
end if;
when "01111" =>
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(base1000_t_fd = 1) or (base1000_t_hd = 1) then
v.regtmp := r.extstatus.base1000_x_fd &
r.extstatus.base1000_x_hd &
r.extstatus.base1000_t_fd &
r.extstatus.base1000_t_hd & X"000";
else
v.regtmp := (others => '0');
end if;
when others =>
--PHY shall not drive MDIO when unimplemented registers
--are accessed
v.cnt := 0; v.state := idle;
v.regtmp := (others => '0');
end case;
if r.ctrl.reset = '1' then
if r.regad = "00000" then
v.regtmp := X"8000";
else
v.regtmp := X"0000";
end if;
end if;
else
if to_X01(mdio) /= '0'then
v.cnt := 0; v.state := idle;
else
v.cnt := 0; v.state := wdata;
end if;
end if;
end if;
when rdata =>
v.cnt := r.cnt + 1;
mdio <= r.regtmp(15-r.cnt);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
end if;
when wdata =>
v.cnt := r.cnt + 1;
v.regtmp := r.regtmp(14 downto 0) & to_X01(mdio);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
if r.ctrl.reset = '0' then
case r.regad is
when "00000" =>
v.ctrl.reset := v.regtmp(15);
v.ctrl.loopback := v.regtmp(14);
v.ctrl.speedsel(1) := v.regtmp(13);
v.ctrl.anegen := v.regtmp(12);
v.ctrl.powerdown := v.regtmp(11);
v.ctrl.isolate := v.regtmp(10);
v.ctrl.restartaneg := v.regtmp(9);
v.ctrl.duplexmode := v.regtmp(8);
v.ctrl.coltest := v.regtmp(7);
v.ctrl.speedsel(0) := v.regtmp(6);
when "00100" =>
if extended_regs = 1 then
v.anegadv.remote_fault := r.regtmp(13);
v.anegadv.tech_ability := r.regtmp(12 downto 5);
v.anegadv.selector := r.regtmp(4 downto 0);
end if;
when "00111" =>
if extended_regs = 1 then
v.anegnptx.next_page := r.regtmp(15);
v.anegnptx.message_page := r.regtmp(13);
v.anegnptx.ack2 := r.regtmp(12);
v.anegnptx.message := r.regtmp(10 downto 0);
end if;
when "01001" =>
if extended_regs = 1 then
v.mstslvctrl.tmode := r.regtmp(15 downto 13);
v.mstslvctrl.manualcfgen := r.regtmp(12);
v.mstslvctrl.cfgval := r.regtmp(11);
v.mstslvctrl.porttype := r.regtmp(10);
v.mstslvctrl.base1000_t_fd := r.regtmp(9);
v.mstslvctrl.base1000_t_hd := r.regtmp(8);
end if;
when others => --no writable bits for other regs
null;
end case;
end if;
end if;
when others =>
null;
end case;
if r.rstcnt > 19 then
v.ctrl.reset := '0'; v.rstcnt := 0;
else
v.rstcnt := r.rstcnt + 1;
end if;
if (v.ctrl.reset and not r.ctrl.reset) = '1' then
v.rstcnt := 0;
end if;
if r.ctrl.anegen = '1' then
if r.anegcnt < 10 then
v.anegcnt := r.anegcnt + 1;
else
v.status.anegcmpt := '1';
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(r.mstslvctrl.base1000_t_fd = '1') or
(r.mstslvctrl.base1000_t_hd = '1') then
v.ctrl.speedsel(1 downto 0) := "01";
elsif (r.anegadv.tech_ability(4) = '1') or
(r.anegadv.tech_ability(3) = '1') or
(r.anegadv.tech_ability(2) = '1') or
(base100_t2_fd = 1) or (base100_t2_hd = 1) then
v.ctrl.speedsel(1 downto 0) := "10";
else
v.ctrl.speedsel(1 downto 0) := "00";
end if;
if ((base1000_x_fd = 1) or (r.mstslvctrl.base1000_t_fd = '1')) or
(((base100_t2_fd = 1) or (r.anegadv.tech_ability(3) = '1')) and
(r.mstslvctrl.base1000_t_hd = '0') and (base1000_x_hd = 0)) or
((r.anegadv.tech_ability(1) = '1') and (base100_t2_hd = 0) and
(r.anegadv.tech_ability(4) = '0') and
(r.anegadv.tech_ability(2) = '0')) then
v.ctrl.duplexmode := '1';
else
v.ctrl.duplexmode := '0';
end if;
end if;
end if;
if r.ctrl.restartaneg = '1' then
v.anegcnt := 0;
v.status.anegcmpt := '0';
v.ctrl.restartaneg := '0';
end if;
rin <= v;
end process;
reg : process(rstn, mdc) is
begin
if rising_edge(mdc) then
r <= rin;
end if;
-- -- RESET DELAY
-- if rstd = '1' then
-- r.ctrl.reset <= '1';
-- else
-- r.ctrl.reset <= '0';
-- end if;
-- RESET
if (r.ctrl.reset or not rstn) = '1' then
r.ctrl.loopback <= '0'; r.anegcnt <= 0;
if (base1000_x_hd = 1) or (base1000_x_fd = 1) or (base1000_t_hd = 1) or
(base1000_t_fd = 1) then
r.ctrl.speedsel <= "01";
elsif (base100_x_hd = 1) or (base100_t2_hd = 1) or (base100_x_fd = 1) or
(base100_t2_fd = 1) or (base100_t4 = 1) then
r.ctrl.speedsel <= "10";
else
r.ctrl.speedsel <= "00";
end if;
r.ctrl.anegen <= conv_std_logic(aneg = 1);
r.ctrl.powerdown <= '0';
r.ctrl.isolate <= '0';
r.ctrl.restartaneg <= '0';
if (base100_x_hd = 0) and (hd_10 = 0) and (base100_t2_hd = 0) and
(base1000_x_hd = 0) and (base1000_t_hd = 0) then
r.ctrl.duplexmode <= '1';
else
r.ctrl.duplexmode <= '0';
end if;
r.ctrl.coltest <= '0';
r.status.base100_t4 <= conv_std_logic(base100_t4 = 1);
r.status.base100_x_fd <= conv_std_logic(base100_x_fd = 1);
r.status.base100_x_hd <= conv_std_logic(base100_x_hd = 1);
r.status.fd_10 <= conv_std_logic(fd_10 = 1);
r.status.hd_10 <= conv_std_logic(hd_10 = 1);
r.status.base100_t2_fd <= conv_std_logic(base100_t2_fd = 1);
r.status.base100_t2_hd <= conv_std_logic(base100_t2_hd = 1);
r.status.extstat <= conv_std_logic((base1000_x_fd = 1) or
(base1000_x_hd = 1) or
(base1000_t_fd = 1) or
(base1000_t_hd = 1));
r.status.mfpreamblesup <= '0';
r.status.anegcmpt <= '0';
r.status.remfault <= '0';
r.status.anegability <= conv_std_logic(aneg = 1);
r.status.linkstat <= '0';
r.status.jabdetect <= '0';
r.status.extcap <= conv_std_logic(extended_regs = 1);
r.anegadv.next_page <= '0';
r.anegadv.remote_fault <= '0';
r.anegadv.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.anegadv.selector <= "00001";
r.aneglp.next_page <= '0';
r.aneglp.remote_fault <= '0';
r.aneglp.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.aneglp.selector <= "00001";
r.anegexp.par_detct_flt <= '0';
r.anegexp.lp_np_able <= '0';
r.anegexp.np_able <= '0';
r.anegexp.page_rx <= '0';
r.anegexp.lp_aneg_able <= '0';
r.anegnptx.next_page <= '0';
r.anegnptx.message_page <= '1';
r.anegnptx.ack2 <= '0';
r.anegnptx.toggle <= '0';
r.anegnptx.message <= "00000000001";
r.anegnplp.next_page <= '0';
r.anegnplp.message_page <= '1';
r.anegnplp.ack2 <= '0';
r.anegnplp.toggle <= '0';
r.anegnplp.message <= "00000000001";
r.mstslvctrl.tmode <= (others => '0');
r.mstslvctrl.manualcfgen <= '0';
r.mstslvctrl.cfgval <= '0';
r.mstslvctrl.porttype <= '0';
r.mstslvctrl.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvctrl.base1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.cfgfault <= '0';
r.mstslvstat.cfgres <= '1';
r.mstslvstat.locrxstate <= '1';
r.mstslvstat.remrxstate <= '1';
r.mstslvstat.lpbase1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.lpbase1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.idlerrcnt <= (others => '0');
r.extstatus.base1000_x_fd <= conv_std_logic(base1000_x_fd = 1);
r.extstatus.base1000_x_hd <= conv_std_logic(base1000_x_hd = 1);
r.extstatus.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.extstatus.base1000_t_hd <= conv_std_logic(base1000_t_hd = 1);
end if;
if rstn = '0' then
r.cnt <= 0; r.state <= idle; r.rstcnt <= 0;
r.ctrl.reset <= '1';
end if;
end process;
loopback_sel : process(r.ctrl.loopback, int_clk, gtx_clk, r.ctrl.speedsel, txd, tx_en) is
begin
if r.ctrl.loopback = '1' then
rx_col <= '0'; rx_crs <= tx_en; rx_dv <= tx_en; rx_er <= tx_er;
rxd <= txd;
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
else
rx_col <= '0'; rx_crs <= '0'; rx_dv <= '0';
rxd <= (others => '0');
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk after 3 ns;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
end if;
end process;
end;
-- pragma translate_on
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/cypress/ssram/cy7c1380d.vhd | 2 | 26462 | --***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cypress.com/support
-- Company: Cypress Semiconductor
-- Part #: CY7C1380D (512K x 36)
--
-- Description: Cypress 18Mb Synburst SRAM (Pipelined SCD)
--
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright(c) Cypress Semiconductor, 2004
-- All rights reserved
--
-- Rev Date Changes
-- --- ---------- ---------------------------------------
-- 1.0 12/22/2004 - New Model
-- - New Test Bench
-- - New Test Vectors
--
--***************************************************************************************
-- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz
LIBRARY ieee, grlib, gaisler, work;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_unsigned.all;
-- Use IEEE.Std_Logic_Arith.all;
USE work.package_utility.all;
use grlib.stdlib.all;
use ieee.std_logic_1164.all;
use std.textio.all;
use gaisler.sim.all;
entity CY7C1380D is
GENERIC (
fname : string := "prom.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 225Mhz
-- Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 4.4 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 200Mhz
-- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 167Mhz
-- Cyp_tCO : TIME := 3.4 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.2 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.2 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.4 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.4 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 133Mhz
-- Cyp_tCO : TIME := 4.2 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 7.5 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.5 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.5 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 4.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 4.2 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end CY7C1380D;
ARCHITECTURE CY7C1380D_arch OF CY7C1380D IS
signal Read_reg_o1, Read_reg1 : STD_LOGIC;
signal WrN_reg1 : STD_LOGIC;
signal ADSP_N_o : STD_LOGIC;
signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC;
signal Sys_clk : STD_LOGIC := '0';
signal test : STD_LOGIC;
signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0);
signal ce : STD_LOGIC;
signal Write_n : STD_LOGIC;
signal Read : STD_LOGIC;
signal bwa_n1 : STD_LOGIC;
signal bwb_n1 : STD_LOGIC;
signal bwc_n1 : STD_LOGIC;
signal bwd_n1 : STD_LOGIC;
signal latch_addr : STD_LOGIC;
signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0);
signal OeN_HZ : STD_LOGIC;
signal OeN_DataValid : STD_LOGIC;
signal OeN_efct : STD_LOGIC;
signal WR_HZ : STD_LOGIC;
signal WR_LZ : STD_LOGIC;
signal WR_efct : STD_LOGIC;
signal CE_HZ : STD_LOGIC;
signal CE_LZ : STD_LOGIC;
signal Pipe_efct : STD_LOGIC;
signal RD_HZ : STD_LOGIC;
signal RD_LZ : STD_LOGIC;
signal RD_efct : STD_LOGIC;
begin
ce <= ((not inCE1) and (iCE2) and (not inCE3));
Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW));
Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce));
bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa))));
bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb))));
bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc))));
bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd))));
latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1)));
OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ;
WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ;
Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ;
RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ;
Process (Read_reg_o1)
begin
if (Read_reg_o1 = '0') then
RD_HZ <= '0' after Cyp_tCHZ;
RD_LZ <= '0' after Cyp_tCLZ;
elsif (Read_reg_o1 = '1') then
RD_HZ <= '1' after Cyp_tCHZ;
RD_LZ <= '1' after Cyp_tCLZ;
else
RD_HZ <= 'X' after Cyp_tCHZ;
RD_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (pipe_reg1)
begin
if (pipe_reg1 = '1') then
CE_LZ <= '1' after Cyp_tCLZ;
elsif (pipe_reg1 = '0') then
CE_LZ <= '0' after Cyp_tCLZ;
else
CE_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
-- System Clock Decode
Process (iclk)
variable Sys_clk1 : std_logic := '0';
begin
if (rising_edge (iclk)) then
Sys_clk1 := not iZZ;
end if;
if (falling_edge (iCLK)) then
Sys_clk1 := '0';
end if;
Sys_clk <= Sys_clk1;
end process;
Process (WrN_reg1)
begin
if (WrN_reg1 = '1') then
WR_HZ <= '1' after Cyp_tCHZ;
WR_LZ <= '1' after Cyp_tCLZ;
elsif (WrN_reg1 = '0') then
WR_HZ <= '0' after Cyp_tCHZ;
WR_LZ <= '0' after Cyp_tCLZ;
else
WR_HZ <= 'X' after Cyp_tCHZ;
WR_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (inOE)
begin
if (inOE = '1') then
OeN_HZ <= '1' after Cyp_tOEHZ;
OeN_DataValid <= '1' after Cyp_tOEV;
elsif (inOE = '0') then
OeN_HZ <= '0' after Cyp_tOEHZ;
OeN_DataValid <= '0' after Cyp_tOEV;
else
OeN_HZ <= 'X' after Cyp_tOEHZ;
OeN_DataValid <= 'X' after Cyp_tOEV;
end if;
end process;
process (ce_reg1, pipe_reg1)
begin
if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then
CE_HZ <= '0' after Cyp_tCHZ;
elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then
CE_HZ <= '1' after Cyp_tCHZ;
else
CE_HZ <= 'X' after Cyp_tCHZ;
end if;
end process;
Process (Sys_clk)
TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0);
variable Read_reg_o : std_logic;
variable Read_reg : std_logic;
variable pcsr_write, ctlr_write : std_logic;
variable WrN_reg : std_logic;
variable latch_addr_old, latch_addr_current : std_logic;
variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0');
variable bcount, first_addr : std_logic_vector (1 downto 0) := "00";
variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic;
variable din : std_logic_vector (data_bits-1 downto 0);
variable first_addr_int : integer;
variable bank0 : memory_array;
variable bank1 : memory_array;
variable bank2 : memory_array;
variable bank3 : memory_array;
variable FIRST : boolean := true;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable CH : character;
variable ai : integer := 0;
variable L1 : line;
begin
if FIRST then
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
std.textio.read(L1, ch);
if (ch = 'S') or (ch = 's') then
hexread(L1, rectype);
hexread(L1, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hexread(L1, recaddr(15 downto 0));
when "0010" =>
hexread(L1, recaddr(23 downto 0));
when "0011" =>
hexread(L1, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hexread(L1, recdata);
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
bank3 (ai+i) := "0000" & recdata((i*32) to (i*32+4));
bank2 (ai+i) := recdata((i*32+5) to (i*32+13));
bank1 (ai+i) := recdata((i*32+14) to (i*32+22));
bank0 (ai+i) := recdata((i*32+23) to (i*32+31));
end loop;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
if rising_edge (Sys_clk) then
if (Write_n = '0') then
Read_reg_o := '0';
else
Read_reg_o := Read_reg;
end if;
if (Write_n = '0') then
Read_reg := '0';
else
Read_reg := Read;
end if;
Read_reg1 <= Read_reg;
Read_reg_o1 <= Read_reg_o;
if (Read_reg = '1') then
pcsr_write := '0';
ctlr_write := '0';
end if;
-- Write Register
if (Read_reg_o = '1') then
WrN_reg := '1';
else
WrN_reg := Write_n;
end if;
WrN_reg1 <= WrN_reg;
latch_addr_old := latch_addr_current;
latch_addr_current := latch_addr;
if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then
pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then
ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
end if;
-- ADDRess Register
if (latch_addr = '1') then
addr_reg_in := iADDR;
bcount := iADDR (1 downto 0);
first_addr := iADDR (1 downto 0);
end if;
addr_reg_in1 <= addr_reg_in;
-- ADSP_N Previous-Cycle Register
ADSP_N_o <= inADSP;
pcsr_write1 <= pcsr_write;
ctlr_write1 <= ctlr_write;
first_addr_int := CONV_INTEGER1 (first_addr);
-- Binary Counter and Logic
if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst
bcount := (bcount + '1'); -- Advance Counter
elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst
if ((first_addr_int REM 2) = 0) then
bcount := (bcount + '1'); -- Increment Counter
elsif ((first_addr_int REM 2) = 1) then
bcount := (bcount - '1'); -- Decrement Counter
end if;
end if;
-- Read ADDRess
addr_reg_read := addr_reg_write;
addr_reg_read1 <= addr_reg_read;
-- Write ADDRess
addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0);
addr_reg_write1 <= addr_reg_write;
-- Byte Write Register
bwa_reg := not bwa_n1;
bwb_reg := not bwb_n1;
bwc_reg := not bwc_n1;
bwd_reg := not bwd_n1;
-- Enable Register
pipe_reg := ce_reg;
-- Enable Register
if (latch_addr = '1') then
ce_reg := ce;
end if;
pipe_reg1 <= pipe_reg;
ce_reg1 <= ce_reg;
-- Input Register
if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and
((pcsr_write = '1') or (ctlr_write = '1'))) then
din := ioDQ;
end if;
din1 <= din;
-- Byte Write Driver
if ((ce_reg = '1') and (bwa_reg = '1')) then
bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0);
end if;
if ((ce_reg = '1') and (bwb_reg = '1')) then
bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9);
end if;
if ((ce_reg = '1') and (bwc_reg = '1')) then
bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18);
end if;
if ((ce_reg = '1') and (bwd_reg = '1')) then
bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27);
end if;
-- Output Registers
if ((Write_n = '0') or (pipe_reg = '0')) then
dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ;
elsif (Read_reg_o = '1') then
dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
end if;
end if;
end process;
-- Output Buffers
ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1'))
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
clk_check : PROCESS
VARIABLE clk_high, clk_low : TIME := 0 ns;
BEGIN
WAIT ON iClk;
IF iClk = '1' AND NOW >= Cyp_tCYC THEN
ASSERT (NOW - clk_low >= Cyp_tCH)
REPORT "Clk width low - tCH violation"
SEVERITY ERROR;
ASSERT (NOW - clk_high >= Cyp_tCYC)
REPORT "Clk period high - tCYC violation"
SEVERITY ERROR;
clk_high := NOW;
ELSIF iClk = '0' AND NOW /= 0 ns THEN
ASSERT (NOW - clk_high >= Cyp_tCL)
REPORT "Clk width high - tCL violation"
SEVERITY ERROR;
ASSERT (NOW - clk_low >= Cyp_tCYC)
REPORT "Clk period low - tCYC violation"
SEVERITY ERROR;
clk_low := NOW;
END IF;
END PROCESS;
-- Check for Setup Timing Violation
setup_check : PROCESS
BEGIN
WAIT ON iClk;
IF iClk = '1' THEN
ASSERT (iAddr'LAST_EVENT >= Cyp_tAS)
REPORT "Addr - tAS violation"
SEVERITY ERROR;
ASSERT (inGW'LAST_EVENT >= Cyp_tWES)
REPORT "GW# - tWES violation"
SEVERITY ERROR;
ASSERT (inBWE'LAST_EVENT >= Cyp_tWES)
REPORT "BWE# - tWES violation"
SEVERITY ERROR;
ASSERT (inCe1'LAST_EVENT >= Cyp_tWES)
REPORT "CE1# - tWES violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT >= Cyp_tWES)
REPORT "CE2 - tWES violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT >= Cyp_tWES)
REPORT "CE3# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS)
REPORT "ADV# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSP# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSC# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT >= Cyp_tWES)
REPORT "BWa# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT >= Cyp_tWES)
REPORT "BWb# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT >= Cyp_tWES)
REPORT "BWc# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT >= Cyp_tWES)
REPORT "BWd# - tWES violation"
SEVERITY ERROR;
ASSERT (ioDq'LAST_EVENT >= Cyp_tDS)
REPORT "Dq - tDS violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Check for Hold Timing Violation
hold_check : PROCESS
BEGIN
WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH);
IF iClk'DELAYED(Cyp_tAH) = '1' THEN
ASSERT (iAddr'LAST_EVENT > Cyp_tAH)
REPORT "Addr - tAH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tDH) = '1' THEN
ASSERT (ioDq'LAST_EVENT > Cyp_tDH)
REPORT "Dq - tDH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tWEH) = '1' THEN
ASSERT (inCe1'LAST_EVENT > Cyp_tWEH)
REPORT "CE1# - tWEH violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT > Cyp_tWEH)
REPORT "CE2 - tWEH violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT > Cyp_tWEH)
REPORT "CE3 - tWEH violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT > Cyp_tWEH)
REPORT "ADV# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSP'LAST_EVENT > Cyp_tWEH)
REPORT "ADSP# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSC'LAST_EVENT > Cyp_tWEH)
REPORT "ADSC# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT > Cyp_tWEH)
REPORT "BWa# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT > Cyp_tWEH)
REPORT "BWb# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT > Cyp_tWEH)
REPORT "BWc# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT > Cyp_tWEH)
REPORT "BWd# - tWEH violation"
SEVERITY ERROR;
END IF;
END PROCESS;
end CY7C1380D_arch;
| mit |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/pairTest.vhd | 1 | 4679 | --EXPECTED RESULTS
--RESAB&0&0
--RESCD&0&0
--RESEF&0&0
--RESGH&0&0
--RESABCD&0&0
--RESEFGH&0&0
--RESULT&0&0
--RESAB&OPERANDA&1
--RESAB&OPERANDB&1
--RESCD&OPERANDC&1
--RESCD&OPERANDD&1
--RESEF&OPERANDE&1
--RESEF&OPERANDF&1
--RESGH&OPERANDG&1
--RESGH&OPERANDH&1
--RESABCD&OPERANDA&2
--RESABCD&OPERANDB&2
--RESABCD&OPERANDC&2
--RESABCD&OPERANDD&2
--RESEFGH&OPERANDE&2
--RESEFGH&OPERANDF&2
--RESEFGH&OPERANDG&2
--RESEFGH&OPERANDH&2
--RESULT&OPERANDA&3
--RESULT&OPERANDB&3
--RESULT&OPERANDC&3
--RESULT&OPERANDD&3
--RESULT&OPERANDE&3
--RESULT&OPERANDF&3
--RESULT&OPERANDG&3
--RESULT&OPERANDH&3
--RESABCD&RESAB&1
--RESABCD&RESCD&1
--RESEFGH&RESEF&1
--RESEFGH&RESGH&1
--RESULT&RESAB&2
--RESULT&RESCD&2
--RESULT&RESEF&2
--RESULT&RESGH&2
--RESULT&RESABCD&1
--RESULT&RESEFGH&1
--OPSABCOMBINED&???&0 -- how do we deal with this
--OPSABCOMBINED (15 DOWNTO 12)&OPERANDA&0
--OPSABCOMBINED (11 DOWNTO 8)&OPERANDB&0
--TRICKYSPLIT&OPSABCOMBINED&1
--TRICKYSPLIT (5 DOWNTO 2)&TRICKYSPLIT (9 DOWNTO 6)&1
--TRICKYSPLIT (5 DOWNTO 2)&OPSABCOMBINED (15 DOWNTO 12)&2
--TRICKYSPLIT (5 DOWNTO 2)&OPERANDA&2
--TRICKYSPLIT (5 DOWNTO 2)&OPSABCOMBINED (11 DOWNTO 8)&1
--TRICKYSPLIT (5 DOWNTO 2)&OPERANDB&1
--TRICKYSPLIT (9 DOWNTO 6)&OPSABCOMBINED (15 DOWNTO 12)&1
--TRICKYSPLIT2 (19 DOWNTO 12)&???&0 -- how do we deal with these
--TRICKYSPLIT2 (19 DOWNTO 16)&OPERANDA&0
--TRICKYSPLIT2 (15 DOWNTO 12)&OPERANDB&0
--TRICKYSPLIT2 (11 DOWNTO 4)&TRICKYSPLIT2 (19 DOWNTO 12)&1
--TRICKYSPLIT2 (11 DOWNTO 4)&???&1 -- how do we deal with these
--TRICKYSPLIT2 (7 DOWNTO 4)&TRICKYSPLIT2 (15 DOWNTO 12)&1
--TRICKYSPLIT2 (7 DOWNTO 4)&OPERANDB (3 DOWNTO 0)&1
--TRICKYSPLIT2 (7 DOWNTO 4)&TRICKYSPLIT2 (11 DOWNTO 8)&1
--TRICKYSPLIT2 (11 DOWNTO 8)&TRICKYSPLIT2 (19 DOWNTO 16)&1
--TRICKYSPLIT2 (11 DOWNTO 8)&OPERANDA&1
--TRICKYSPLIT2 (7 DOWNTO 4)&TRICKYSPLIT2 (19 DOWNTO 16)&2
--TRICKYSPLIT2 (7 DOWNTO 4)&OPERANDA&2
--TRICKYREC.A&OPERANDA&1
--TRICKYREC.B&OPERANDB&1
--TRICKYREC&???&0 -- how do we deal with these
--TRICKYREC.C&???&1 -- how do we deal with these
--TRICKYREC.C (7 DOWNTO 4)&TRICKYREC.A&1 -- how do we deal with these
--TRICKYREC.C (3 downto 0)&TRICKYREC.B&1 -- how do we deal with these
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pairTest is
port(
clk : in std_logic;
rst : in std_logic;
operandA : in unsigned(3 downto 0);
operandB : in unsigned(3 downto 0);
operandC : in unsigned(3 downto 0);
operandD : in unsigned(3 downto 0);
operandE : in unsigned(3 downto 0);
operandF : in unsigned(3 downto 0);
operandG : in unsigned(3 downto 0);
operandH : in unsigned(3 downto 0);
result : out unsigned(3 downto 0)
);
end entity pairTest;
architecture rtl of pairTest is
type My_Rec is record
a : unsigned(3 downto 0);
b : unsigned(3 downto 0);
c : unsigned(7 downto 0);
end record;
signal resAB : unsigned(3 downto 0);
signal resCD : unsigned(3 downto 0);
signal resEF : unsigned(3 downto 0);
signal resGH : unsigned(3 downto 0);
signal resABCD : unsigned(3 downto 0);
signal resEFGH : unsigned(3 downto 0);
signal opsABCombined : unsigned(15 downto 8);
signal trickySplit : unsigned(9 downto 2);
signal trickySplit2 : unsigned(19 downto 4);
signal trickyRec : My_rec;
begin
opsABCombined <= operandA & operandB;
trickySplit2(19 downto 12) <= operandA & operandB;
DoOps : process(clk)
begin
if(clk'event and clk = '1')then
if(rst = '1')then
resAB <= "0000";
resCD <= "0000";
resEF <= "0000";
resGH <= "0000";
resABCD <= "0000";
resEFGH <= "0000";
result <= "0000";
trickySplit <= opsABCombined;
trickySplit2(11 downto 4) <= trickySplit2(19 downto 12);
trickyRec <= (operandA, operandB, (operandC & operandD));
else
resAB <= operandA + operandB;
resCD <= operandC + operandD;
resEF <= operandE + operandF;
resGH <= operandG + operandH;
resABCD <= resAB + resCD;
resEFGH <= resEF + resGH;
result <= resABCD + resEFGH;
-- ts(7 4) should be added to the signal list since it is a driver, and it should be marked as a register due to it's less constrained version being marked as such
if(operandA(3) and operandB(3) and operandC(3) and operandD(3) and operandE(3) and operandF(3) and operandG(3) and operandH(3))then
trickySplit(5 downto 2) <= trickySplit(9 downto 6);
trickySplit2(7 downto 4) <= trickySplit2(11 downto 8);
trickyRec.c <= trickyRec.a & trickyRec.b;
end if;
end if;
end if;
end process;
end architecture rtl; | mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/ddr/ddrctrl.vhd | 2 | 33891 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrctrl
-- File: ddrctrl.vhd
-- Author: David Lindh - Gaisler Research
-- Description: DDR-RAM memory controller with AMBA interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use techmap.allmem.all;
use gaisler.ddrrec.all;
entity ddrctrl is
generic (
hindex1 : integer := 0;
haddr1 : integer := 0;
hmask1 : integer := 16#f80#;
hindex2 : integer := 0;
haddr2 : integer := 0;
hmask2 : integer := 16#f80#;
pindex : integer := 3;
paddr : integer := 0;
numahb : integer := 1; -- Allowed: 1, 2
ahb1sepclk : integer := 0; -- Allowed: 0, 1
ahb2sepclk : integer := 0; -- Allowed: 0, 1
modbanks : integer := 1; -- Allowed: 1, 2
numchips : integer := 2; -- Allowed: 1, 2, 4, 8, 16
chipbits : integer := 16; -- Allowed: 4, 8, 16
chipsize : integer := 256; -- Allowed: 64, 128, 256, 512, 1024 (MB)
plldelay : integer := 0; -- Allowed: 0, 1 (Use 200us start up delay)
tech : integer := virtex2;
clkperiod : integer := 10); -- (ns)
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk1 : in std_ulogic;
hclk2 : in std_ulogic;
pclk : in std_ulogic;
ahb1si : in ahb_slv_in_type;
ahb1so : out ahb_slv_out_type;
ahb2si : in ahb_slv_in_type;
ahb2so : out ahb_slv_out_type;
apbsi : in apb_slv_in_type;
apbso : out apb_slv_out_type;
ddsi : out ddrmem_in_type;
ddso : in ddrmem_out_type);
end ddrctrl;
architecture rtl of ddrctrl is
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant DELAY_15600NS : integer := (15600 / clkperiod);
constant DELAY_7800NS : integer := (7800 / clkperiod);
constant DELAY_7_15600NS : integer := (7*(15600 / clkperiod));
constant DELAY_7_7800NS : integer := (7*(7800 / clkperiod));
constant DELAY_200US : integer := (200000 / clkperiod);
constant REVISION : integer := 0;
constant pmask : integer := 16#fff#;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRMP, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant dqsize : integer := numchips*chipbits;
constant dmsize : integer := (dqsize/8);
constant strobesize : integer := (dqsize/8) * dmvector(chipbits);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal toAHB : two_ahb_ctrl_in_type;
signal fromAHB : two_ahb_ctrl_out_type;
signal fromAHB2Main : two_ahb_ctrl_out_type;
signal apbr : apb_reg_type;
signal apbri : apb_reg_type;
signal fromAPB : apb_ctrl_out_type;
signal fromAPB2Main : apb_ctrl_out_type;
signal mainr : main_reg_type;
signal mainri : main_reg_type;
signal fromMain : main_ctrl_out_type;
signal fromMain2APB : apb_ctrl_in_type;
signal fromMain2AHB : two_ahb_ctrl_in_type;
signal fromMain2HS : hs_in_type;
signal toHS : hs_in_type;
signal fromHS : hs_out_type;
begin -- achitecture rtl
-------------------------------------------------------------------------------
-- Error reports
assert (tech = virtex2 or tech = virtex4 or tech = lattice) report "Unsupported technology by DDR controller (generic tech)" severity failure;
assert (modbanks=1 or modbanks=2) report "Only 1 or 2 module banks is supported (generic modbanks)" severity failure;
assert (chipbits=4 or chipbits=8 or chipbits=16) report "DDR chips either have 4, 8 or 16 bits output (generic chipbits)" severity failure;
assert (chipsize=64 or chipsize=128 or chipsize=256 or chipsize=512 or chipsize=1024) report "DDR chips either have 64, 128, 256, 512 or 1024 Mbit size" severity failure;
assert (buffersize>=2) report "Buffer must have room for at least 2 bursts (generic buffersize)" severity failure;
assert (plldelay=0 or plldelay=1) report "Invalid setting for DDRRAM PLL delay (generic plldelay)" severity failure;
assert (numahb=1 or numahb=2) report "Only one or two AHB interfaces can be used (generic numahb)" severity failure;
-------------------------------------------------------------------------------
-- APB control
-- Controls APB bus. Contains the DDRCFG register. Clear memcmd
-- bits when a memory command requested on APB is complete.
apbcomb : process(apbr, apbsi, fromMain2APB, rst)
variable v : apb_reg_type;
begin
v:= apbr;
if rst = '0' then -- Reset
v.ddrcfg_reg := ddrcfg_reset;
elsif fromMain2APB.apb_cmd_done = '1' then -- Clear memcmd bits
v.ddrcfg_reg(28 downto 27) := "00";
elsif (apbsi.psel(pindex) and apbsi.penable and apbsi.pwrite) = '1' then -- Write
v.ddrcfg_reg := apbsi.pwdata(31 downto 1) & fromMain2APB.ready;
else
v.ddrcfg_reg(0) := fromMain2APB.ready;
end if;
apbri <= v;
fromAPB.ddrcfg_reg <= v.ddrcfg_reg;
end process apbcomb;
apbclk : process(pclk)
begin
if rising_edge(pclk) then apbr <= apbri; end if;
end process;
apbso.prdata <= fromAPB.ddrcfg_reg; apbso.pirq <= (others => '0');
apbso.pindex <= pindex; apbso.pconfig <= pconfig;
-------------------------------------------------------------------------------
-- Main controller
-------------------------------------------------------------------------------
maincomb : process(mainr, fromAHB, fromAHB2Main, fromAPB2Main, rst, fromHS)
variable v : main_reg_type;
begin
v := mainr; v.loadcmdbuffer := '0'; -- Clear Cmd loading bit
-------------------------------------------------------------------------------
-- DDRCFG control
-- Reads DDRCFG from APB controller. Handles refresh command from refresh
-- timer and memoory comand requested on APB.
case v.apbstate is
when idle =>
v.apb_cmd_done := '0';
-- Refresh timer signals refresh
if v.doRefresh = '1' and v.ddrcfg.refresh = '1' then
v.apbstate := refresh;
-- LMR cmd on APB bus
elsif fromAPB2Main.ddrcfg_reg(28 downto 27) = "11" then
v.lockAHB := "11";
v.apbstate := wait_lmr1;
-- Refresh or Precharge cmd on APB BUS
elsif fromAPB2Main.ddrcfg_reg(28 downto 27) > "00" then
v.apbstate := cmd;
-- Nothing to be done
else
v.ddrcfg.memcmd := "00";
end if;
-- Refresh from Timer
when refresh =>
if v.mainstate = idle then v.ddrcfg.memcmd := "10"; end if;
if v.dorefresh = '0' then v.ddrcfg.memcmd := "00"; v.apbstate := idle; end if;
-- Refresh or Precharge from APB BUS
when cmd =>
if v.mainstate = idle then v.ddrcfg.memcmd := fromAPB2Main.ddrcfg_reg(28 downto 27); end if;
v.apbstate := cmdDone;
-- Wait until no more cmd can arrive from AHB ctrl
when wait_lmr1 => v.apbstate := wait_lmr2;
when wait_lmr2 => v.apbstate := cmdlmr;
when cmdlmr =>
-- Check that no new R/W cmd is to be performed
if fromAHB2Main(0).rw_cmd_valid = v.rw_cmd_done(0) and
fromAHB2Main(1).rw_cmd_valid = v.rw_cmd_done(1) and v.mainstate = idle then
v.ddrcfg.memcmd := "11";
v.ddrcfg.cas := fromAPB2Main.ddrcfg_reg(30 downto 29);
v.ddrcfg.bl := fromAPB2Main.ddrcfg_reg(26 downto 25);
v.apbstate := cmdDone;
end if;
when cmdDone =>
v.lockAHB := "00";
if v.memCmdDone = '1' then
v.ddrcfg.memcmd := "00"; v.apb_cmd_done := '1'; v.apbstate := cmdDone2;
end if;
when cmdDone2 =>
if fromAPB2Main.ddrcfg_reg(28 downto 27) = "00" then
v.apb_cmd_done := '0'; v.apbstate := idle;
end if;
end case;
if v.mainstate = idle then
v.ddrcfg.refresh := fromAPB2Main.ddrcfg_reg(31);
v.ddrcfg.autopre := fromAPB2Main.ddrcfg_reg(24);
v.ddrcfg.r_predict := fromAPB2Main.ddrcfg_reg(23 downto 22);
v.ddrcfg.w_prot := fromAPB2Main.ddrcfg_reg(21 downto 20);
v.ddrcfg.ready := fromAPB2Main.ddrcfg_reg(0);
end if;
-------------------------------------------------------------------------------
-- Calcualtes burst length
case v.ddrcfg.bl is
when "00" => v.burstlength := 2;
when "01" => v.burstlength := 4;
when "10" => v.burstlength := 8;
when others => v.burstlength := 8;
end case;
-------------------------------------------------------------------------------
-- Calculates row and column address
v.tmpcoladdress := (others => (others => '0'));
v.rowaddress := (others => (others => '0'));
v.coladdress := (others => (others => '0'));
v.tmpcolbits := 0; v.colbits := 0; v.rowbits := 0;
-- Based on the size of the chip its organization can be calculated
case chipsize is
when 64 => v.tmpcolbits := 10; v.rowbits := 12; v.refreshTime := DELAY_15600NS; v.maxRefreshTime := DELAY_7_15600NS; -- 64Mbit
when 128 => v.tmpcolbits := 11; v.rowbits := 12; v.refreshTime := DELAY_15600NS; v.maxRefreshTime := DELAY_7_15600NS; -- 128Mbit
when 256 => v.tmpcolbits := 11; v.rowbits := 13; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 256Mbit
when 512 => v.tmpcolbits := 12; v.rowbits := 13; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 512Mbit
when 1024 => v.tmpcolbits := 12; v.rowbits := 14; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 1Gbit
when others => v.tmpcolbits := 10; v.rowbits := 12; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- Others 64Mbit
end case;
case chipbits is
when 4 => v.colbits := v.tmpcolbits; -- x4 bits
when 8 => v.colbits := (v.tmpcolbits-1); -- x8 bits
when 16 => v.colbits := (v.tmpcolbits-2); -- x16 bits
when others => null;
end case;
v.addressrange := v.colbits + v.rowbits;
-- AHB controller 1 --
for i in 0 to ahbadr loop
if (i < v.colbits) then
v.tmpcoladdress(0)(i) := fromAHB(0).asramso.dataout(i); end if;
if (i < (v.addressrange) and i >= v.colbits) then
v.rowaddress(0)(i-v.colbits) := fromAHB(0).asramso.dataout(i); end if;
if (i < (v.addressrange+2) and i >= v.addressrange) then
v.intbankbits(0)(i - v.addressrange) := fromAHB(0).asramso.dataout(i); end if;
end loop;
-- Inserts bank address and auto precharge bit as A10
v.coladdress(0)(adrbits-1 downto 0) := v.intbankbits(0) &
v.tmpcoladdress(0)(12 downto 10) & -- Bit 13 to 11
v.ddrcfg.autopre & -- Bit 10
v.tmpcoladdress(0)(9 downto 0); --Bit 9 to 0
v.rowaddress(0)(adrbits-1 downto (adrbits-2)) := v.intbankbits(0);
-- Calculate total numer of useable address bits
if modbanks = 2 then
-- Calculate memory module bank (CS signals)
if fromAHB(0).asramso.dataout(v.addressrange +2) = '0' then
v.bankselect(0) := BANK0;
else
v.bankselect(0) := BANK1;
end if;
else
v.bankselect(0) := BANK0;
end if;
-- This is for keeping track of which banks has a active row
v.pre_bankadr(0):= conv_integer(v.bankselect(0)(0) & v.rowaddress(0)(adrbits-1 downto (adrbits-2)));
-- AHB Controller 2 --
for i in 0 to ahbadr loop
if (i < v.colbits) then
v.tmpcoladdress(1)(i) := fromAHB(1).asramso.dataout(i); end if;
if (i < (v.addressrange) and i >= v.colbits) then
v.rowaddress(1)(i-v.colbits) := fromAHB(1).asramso.dataout(i); end if;
if (i < (v.addressrange+2) and i >= v.addressrange) then
v.intbankbits(1)(i - v.addressrange) := fromAHB(1).asramso.dataout(i); end if;
end loop;
-- Inserts bank address and auto precharge bit as A10
v.coladdress(1)(adrbits-1 downto 0) := v.intbankbits(1) &
v.tmpcoladdress(1)(12 downto 10) & -- Bit 13 to 11
v.ddrcfg.autopre & -- Bit 10
v.tmpcoladdress(1)(9 downto 0); --Bit 9 to 0
v.rowaddress(1)(adrbits-1 downto (adrbits-2)) := v.intbankbits(1);
-- Calculate total numer of useable address bits
if modbanks = 2 then
-- Calculate memory module bank (CS signals)
if fromAHB(1).asramso.dataout(v.addressrange +2) = '0' then
v.bankselect(1) := BANK0;
else
v.bankselect(1) := BANK1;
end if;
else
v.bankselect(1) := BANK0;
end if;
-- This is for keeping track of which banks has a active row
v.pre_bankadr(1):= conv_integer(v.bankselect(1)(0) & v.rowaddress(1)(adrbits-1 downto (adrbits-2)));
-- ((1bit(Lower/upper half if 32 bit mode))) + 1bit(module bank select) +
-- 2bits(Chip bank selekt) + Xbits(address, depending on chip size)
-------------------------------------------------------------------------------
-- Calculate LMR command address
v.lmradr(adrbits-1 downto 7) := (others => '0');
-- CAS value
case v.ddrcfg.cas is
when "00" => v.lmradr(6 downto 4) := "010";
when "01" => v.lmradr(6 downto 4) := "110";
when "10" => v.lmradr(6 downto 4) := "011";
when others => v.lmradr(6 downto 4) := "010";
end case;
-- Burst type, seqencial or interleaved (fixed att seqencial)
v.lmradr(3) := '0';
-- Burst length
case v.ddrcfg.bl is
when "00" => v.lmradr(2 downto 0) := "001";
when "01" => v.lmradr(2 downto 0) := "010";
when "10" => v.lmradr(2 downto 0) := "011";
when others => v.lmradr(2 downto 0) := "010";
end case;
-------------------------------------------------------------------------------
-- Auto refresh timer
case v.timerstate is
when t1 =>
v.doRefresh := '0'; v.refreshcnt := v.refreshTime; v.timerstate := t2;
when t2 =>
v.doRefresh := '0'; v.refreshcnt := mainr.refreshcnt -1;
if v.refreshcnt < 50 then v.timerstate := t3; end if;
when t3 =>
if mainr.refreshcnt > 1 then v.refreshcnt := mainr.refreshcnt -1; end if;
v.doRefresh := '1';
if v.refreshDone = '1' then
v.refreshcnt := mainr.refreshcnt + v.refreshTime;
v.timerstate := t4;
end if;
when t4 =>
v.doRefresh := '0'; v.timerstate := t2; when others => null;
end case;
-------------------------------------------------------------------------------
-- Init statemachine
case v.initstate is
when idle =>
v.memInitDone := '0';
if v.doMemInit = '1' then
if plldelay = 1 then
-- Using refrshtimer for initial wait
v.refreshcnt := DELAY_200US +50; v.timerstate := t2; v.initstate := i1;
else v.initstate := i2; end if;
end if;
when i1 =>
if v.doRefresh = '1' then v.initstate := i2; end if;
when i2 =>
v.cs := "00";
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_NOP; v.loadcmdbuffer := '1'; v.initstate := i3;
end if;
when i3 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_PRE; v.loadcmdbuffer := '1';
v.adrbufferdata(10) := '1'; v.initstate := i4;
end if;
when i4 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1';
v.adrbufferdata(adrbits-1 downto (adrbits-2)) := "01";
v.adrbufferdata((adrbits -3) downto 0) := (others => '0');
v.initstate := i5;
end if;
when i5 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1'; v.adrbufferdata := v.lmradr;
v.refreshcnt := 250; v.timerstate := t2; --200 cycle count
v.adrbufferdata(8) := '1'; v.initstate := i6;
end if;
when i6 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_PRE; v.loadcmdbuffer := '1';
v.adrbufferdata(10) := '1'; v.initstate := i7;
end if;
when i7 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_AR; v.loadcmdbuffer := '1'; v.initstate := i8;
end if;
when i8 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_AR; v.loadcmdbuffer := '1'; v.initstate := i9;
end if;
when i9 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1'; v.adrbufferdata := v.lmradr;
v.initstate := i10;
end if;
when i10 =>
if v.doRefresh = '1' then v.initstate := i11; end if;
when i11 =>
v.memInitDone := '1';
if v.doMemInit = '0' then v.initstate := idle; end if;
when others => null;
end case;
-------------------------------------------------------------------------------
-- Main controller statemachine
case v.mainstate is
-- Initialize memory
when init =>
v.doMemInit := '1';
v.ready := '0';
if v.memInitDone = '1' then
v.mainstate := idle;
end if;
-- Await command
when idle =>
v.doMemInit := '0';
v.RefreshDone := '0';
v.memCmdDone := '0';
v.ready := '1';
v.use_bl := mainr.burstlength;
v.use_cas := mainr.ddrcfg.cas;
if v.ddrcfg.memcmd /= "00" then
v.mainstate := c1;
elsif fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) or
fromAHB2Main(1).rw_cmd_valid /= v.rw_cmd_done(1) then
-- This code is to add read priority between the ahb controllers
-- if fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) and
-- fromAHB(0).asramso.dataout(ahbadr) = '0' then
-- v.use_ahb := 0;
-- v.use_buf := v.rw_cmd_done(0)+1;
-- elsif fromAHB2Main(1).rw_cmd_valid /= v.rw_cmd_done(1) and
-- fromAHB(1).asramso.dataout(ahbadr) = '0' then
-- v.use_ahb := 1;
-- v.use_buf := v.rw_cmd_done(1)+1;
if fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) then
v.use_ahb := 0;
v.use_buf := v.rw_cmd_done(0)+1;
else
v.use_ahb := 1;
v.use_buf := v.rw_cmd_done(1)+1;
end if;
-- Check if the chip bank which is to be R/W has a row open
if mainr.pre_chg(v.pre_bankadr(v.use_ahb)) = '1' then
-- Check if the row which is open is the same that will be R/W
if mainr.pre_row(v.pre_bankadr(v.use_ahb)) = v.rowaddress(v.use_ahb) then
v.mainstate := rw;
-- R/W to a different row then the one open, has to precharge and
-- activate new row
else
v.mainstate := pre1;
end if;
-- No row open, has to activate row
else
v.mainstate := act1;
end if;
end if;
-- Nothing to do, if 10 idle cycles, run Refreash (if needed)
if v.idlecnt = 10 and v.refreshcnt < v.maxRefreshTime then
v.doRefresh := '1';
v.idlecnt := 0;
v.timerstate := t3;
v.refreshcnt := mainr.refreshcnt + v.refreshTime;
elsif v.idlecnt = 10 then
v.idlecnt := 0;
else
v.idlecnt := mainr.idlecnt + 1;
end if;
-- Precharge memory
when pre1 =>
if fromHS.hs_busy = '0' then
v.cs := v.bankselect(mainr.use_ahb);
-- Select chip bank to precharge
v.adrbufferdata := (others => '0');
v.adrbufferdata(adrbits-1 downto (adrbits-2)) := v.rowaddress(mainr.use_ahb)(adrbits-1 downto (adrbits-2));
v.cmdbufferdata := CMD_PRE;
-- Clear bit in register for active rows
v.pre_chg(v.pre_bankadr(mainr.use_ahb)):= '0';
v.loadcmdbuffer := '1';
v.mainstate := act1;
end if;
-- Activate row in memory
when act1 => -- Get adr and cmd from AHB, set to HS
if fromHS.hs_busy = '0' then
v.cs := v.bankselect(mainr.use_ahb);
v.cmdbufferdata := CMD_ACTIVE;
v.adrbufferdata := v.rowaddress(mainr.use_ahb);
v.loadcmdbuffer := '1';
-- Set bit in register for active row if auto-precharge is disabled
if v.ddrcfg.autopre = '0' then
v.pre_chg(v.pre_bankadr(mainr.use_ahb)) := '1';
v.pre_row(v.pre_bankadr(mainr.use_ahb)) := v.rowaddress(mainr.use_ahb);
end if;
v.mainstate := rw;
end if;
-- Issu read or write to HS part
when rw =>
if fromAHB(mainr.use_ahb).asramso.dataout(ahbadr) = '1' then
v.cmdbufferdata := CMD_WRITE;
else
v.cmdbufferdata := CMD_READ;
end if;
if v.ddrcfg.autopre = '1' then
v.pre_chg(v.pre_bankadr(mainr.use_ahb)) := '0';
end if;
v.adrbufferdata := v.coladdress(mainr.use_ahb);
v.cs := v.bankselect(mainr.use_ahb);
v.idlecnt := 0;
if fromHS.hs_busy = '0' then
if fromAHB2Main(mainr.use_ahb).w_data_valid /= v.rw_cmd_done(mainr.use_ahb) then
v.loadcmdbuffer := '1';
v.rw_cmd_done(mainr.use_ahb) := v.rw_cmd_done(mainr.use_ahb)+1;
v.sync2_adr(mainr.use_ahb) := v.rw_cmd_done(mainr.use_ahb)+1;
v.mainstate := idle;
end if;
end if;
-- Issue prechare, auto refresh or LMR to HS part
when c1 =>
v.idlecnt := 0;
if fromHS.hs_busy = '0' then
v.cs := BANK01;
case v.ddrcfg.memCmd is
when "01" => -- Precharge all
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.memCmdDone := '1';
v.mainstate := c2;
when "10" => -- AutoRefresh
-- All banks have to be precharged before AR
if v.pre_chg = "00000000" then
v.cmdbufferdata := CMD_AR;
v.memCmdDone := '1';
v.mainstate := c2;
v.refreshDone := '1';
else -- Run Precharge, and let AR begin when finished
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.mainstate := idle;
end if;
when "11" => -- LMR
-- All banks have to be precharged before LMR
if v.pre_chg = "00000000" then
v.cmdbufferdata := CMD_LMR;
v.adrbufferdata := v.lmradr;
v.memCmdDone := '1';
v.mainstate := c2;
else
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.mainstate := idle;
end if;
when others => null;
end case;
v.loadcmdbuffer := '1';
end if;
when c2 =>
if v.ddrcfg.memCmd = "00" then
v.refreshDone := '0';
v.mainstate := idle;
end if;
when others =>
v.mainstate := init;
end case;
-- Reset
if rst = '0' then
-- Main controller
v.mainstate := init;
v.loadcmdbuffer := '0';
v.cmdbufferdata := CMD_NOP;
v.adrbufferdata := (others => '0');
v.use_ahb := 0;
v.use_bl := 4;
v.use_cas := "00";
v.use_buf := (others => '1');
v.burstlength := 8;
v.rw_cmd_done := (others => (others => '1'));
v.lmradr := (others => '0');
v.memCmdDone := '0';
v.lockAHB := "00";
v.pre_row := (others => (others => '0'));
v.pre_chg := (others => '0');
v.pre_bankadr := (0,0);
v.sync2_adr := (others =>(others => '0'));
-- For init statemachine
v.initstate := idle;
v.doMemInit := '0';
v.memInitDone := '0';
v.initDelay := 0;
v.cs := "11";
-- For address calculator
v.coladdress := (others => (others => '0'));
v.tmpcoladdress := (others => (others => '0'));
v.rowaddress := (others => (others => '0'));
v.addressrange := 0;
v.tmpcolbits := 0;
v.colbits := 0;
v.rowbits := 0;
v.bankselect := ("11","11");
v.intbankbits := ("00","00");
-- For refresh timer statemachine
v.timerstate := t2;
v.doRefresh := '0';
v.refreshDone := '0';
v.refreshTime := 0;
v.maxRefreshTime := 0;
v.idlecnt := 0;
v.refreshcnt := DELAY_200us;
-- For DDRCFG register
v.apbstate := idle;
v.apb_cmd_done := '0';
v.ready := '0';
v.ddrcfg := (ddrcfg_reset(31),ddrcfg_reset(30 downto 29),ddrcfg_reset(28 downto 27),
ddrcfg_reset(26 downto 25),ddrcfg_reset(24),ddrcfg_reset(23 downto 22),
ddrcfg_reset(21 downto 20),'0');
end if;
-- Set output signals
mainri <= v;
fromMain.hssi.bl <= v.use_bl;
fromMain.hssi.ml <= fromAHB(mainr.use_ahb).burst_dm(conv_integer(mainr.use_buf));
fromMain.hssi.cas <= v.use_cas;
fromMain.hssi.buf <= v.use_buf;
fromMain.hssi.ahb <= v.use_ahb;
fromMain.hssi.cs <= v.cs;
fromMain.hssi.cmd <= v.cmdbufferdata;
fromMain.hssi.cmd_valid <= v.loadcmdbuffer;
fromMain.hssi.adr <= v.adrbufferdata;
fromMain.ahbctrlsi(0).burstlength <= v.burstlength;
fromMain.ahbctrlsi(1).burstlength <= v.burstlength;
fromMain.ahbctrlsi(0).r_predict <= v.ddrcfg.r_predict(0);
fromMain.ahbctrlsi(1).r_predict <= v.ddrcfg.r_predict(1);
fromMain.ahbctrlsi(0).w_prot <= v.ddrcfg.w_prot(0);
fromMain.ahbctrlsi(1).w_prot <= v.ddrcfg.w_prot(1);
fromMain.ahbctrlsi(0).locked <= v.lockAHB(0);
fromMain.ahbctrlsi(1).locked <= v.lockAHB(1);
fromMain.ahbctrlsi(0).asramsi.raddress <= v.sync2_adr(0);
fromMain.ahbctrlsi(1).asramsi.raddress <= v.sync2_adr(1);
fromMain.apbctrlsi.apb_cmd_done <= v.apb_cmd_done;
fromMain.apbctrlsi.ready <= v.ready;
end process;
--Main clocked register
mainclk : process(clk0)
begin
if rising_edge(clk0) then
mainr <= mainri;
-- Register to sync between different clock domains
fromAPB2Main.ddrcfg_reg <= fromAPB.ddrcfg_reg;
-- Makes signals from main to AHB, ABP, HS registerd
fromMain2AHB <= fromMain.ahbctrlsi;
fromMain2APB <= fromMain.apbctrlsi;
fromMain2HS <= fromMain.hssi;
end if;
end process;
-- Sync of incoming data valid signals from AHB
-- Either if separate clock domains or if syncram_2p
-- doesn't support write through (write first)
a1rt : if ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0 generate
regip1 : process(clk0)
begin
if rising_edge(clk0) then
fromAHB2Main(0).rw_cmd_valid <= fromAHB(0).rw_cmd_valid;
fromAHB2Main(0).w_data_valid <= fromAHB(0).w_data_valid;
end if;
end process;
end generate;
arf : if not (ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0) generate
fromAHB2Main(0).rw_cmd_valid <= fromAHB(0).rw_cmd_valid;
fromAHB2Main(0).w_data_valid <= fromAHB(0).w_data_valid;
end generate;
a2rt : if ahb2sepclk = 1 or syncram_2p_write_through(tech) = 0 generate
regip2 : process(clk0)
begin
if rising_edge(clk0) then
fromAHB2Main(1).rw_cmd_valid <= fromAHB(1).rw_cmd_valid;
fromAHB2Main(1).w_data_valid <= fromAHB(1).w_data_valid;
end if;
end process;
end generate;
a2rf : if not (ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0) generate
fromAHB2Main(1).rw_cmd_valid <= fromAHB(1).rw_cmd_valid;
fromAHB2Main(1).w_data_valid <= fromAHB(1).w_data_valid;
end generate;
-------------------------------------------------------------------------------
-- High speed interface (Physical layer towards memory)
-------------------------------------------------------------------------------
D0 : hs
generic map(
tech => tech,
dqsize => dqsize,
dmsize => dmsize,
strobesize => strobesize,
clkperiod => clkperiod)
port map(
rst => rst,
clk0 => clk0,
clk90 => clk90,
clk180 => clk180,
clk270 => clk270,
hclk => pclk,
hssi => toHS,
hsso => fromHS);
A0 : ahb_slv
generic map(
hindex => hindex1,
haddr => haddr1,
hmask => hmask1,
sepclk => ahb1sepclk,
dqsize => dqsize,
dmsize => dmsize,
tech => tech)
port map (
rst => rst,
hclk => hclk1,
clk0 => clk0,
csi => toAHB(0),
cso => fromAHB(0));
B1: if numahb = 2 generate
A1 : ahb_slv
generic map(
hindex => hindex2,
haddr => haddr2,
hmask => hmask2,
sepclk => ahb2sepclk,
dqsize => dqsize,
dmsize => dmsize)
port map (
rst => rst,
hclk => hclk2,
clk0 => clk0,
csi => toAHB(1),
cso => fromAHB(1));
end generate;
B2 : if numahb /= 2 generate
fromAHB(1).rw_cmd_valid <= (others => '1');
end generate;
-------------------------------------------------------------------------------
-- Mapping signals
-- Signals to HS
toHS.bl <= fromMain.hssi.bl;
toHS.ml <= fromMain.hssi.ml;
toHS.cas <= fromMain.hssi.cas;
toHS.buf <= fromMain.hssi.buf;
toHS.ahb <= fromMain.hssi.ahb;
toHS.cs <= fromMain.hssi.cs;
toHS.adr <= fromMain.hssi.adr;
toHS.cmd <= fromMain.hssi.cmd;
toHS.cmd_valid <= fromMain.hssi.cmd_valid;
toHS.dsramso(0) <= fromAHB(0).dsramso;
toHS.dsramso(1) <= fromAHB(1).dsramso;
toHS.ddso <= ddso;
-- Signals to AHB ctrl 1
toAHB(0).ahbsi <= ahb1si;
toAHB(0).asramsi <= fromMain.ahbctrlsi(0).asramsi;
toAHB(0).dsramsi <= fromHS.dsramsi(0);
toAHB(0).burstlength <= fromMain2AHB(0).burstlength;
toAHB(0).r_predict <= fromMain2AHB(0).r_predict;
toAHB(0).w_prot <= fromMain2AHB(0).w_prot;
toAHB(0).locked <= fromMain2AHB(0).locked;
toAHB(0).rw_cmd_done <= fromHS.cmdDone(0);
-- Signals to AHB ctrl 2
toAHB(1).ahbsi <= ahb2si;
toAHB(1).asramsi <= fromMain.ahbctrlsi(1).asramsi;
toAHB(1).dsramsi <= fromHS.dsramsi(1);
toAHB(1).burstlength <= fromMain2AHB(1).burstlength;
toAHB(1).r_predict <= fromMain2AHB(1).r_predict;
toAHB(1).w_prot <= fromMain2AHB(1).w_prot;
toAHB(1).locked <= fromMain2AHB(1).locked;
toAHB(1).rw_cmd_done <= fromHS.cmdDone(1);
-- Ouput signals
ahb1so <= fromAHB(0).ahbso;
ahb2so <= fromAHB(1).ahbso;
ddsi <= fromHS.ddsi;
end rtl;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/memctrl/ssrctrl.in.vhd | 6 | 134 | -- SSRAM controller
constant CFG_SSCTRL : integer := CONFIG_SSCTRL;
constant CFG_SSCTRLP16 : integer := CONFIG_SSCTRL_PROM16;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/ahbram.vhd | 2 | 4241 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram is
constant abits : integer := log2(kbytes) + 8;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits+1 downto 0);
size : std_logic_vector(1 downto 0);
end record;
signal r, c : reg_type;
signal ramsel : std_ulogic;
signal write : std_logic_vector(3 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(31 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(3 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
begin
v := r; v.hready := '1'; bs := (others => '0');
if (r.hwrite or not r.hready) = '1' then haddr := r.addr(abits+1 downto 2);
else
haddr := ahbsi.haddr(abits+1 downto 2); bs := (others => '0');
end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.hwrite := ahbsi.hwrite and v.hsel;
v.addr := ahbsi.haddr(abits+1 downto 0);
v.size := ahbsi.hsize(1 downto 0);
end if;
if r.hwrite = '1' then
case r.size(1 downto 0) is
when "00" => bs (conv_integer(r.addr(1 downto 0))) := '1';
when "01" => bs := r.addr(1) & r.addr(1) & not (r.addr(1) & r.addr(1));
when others => bs := (others => '1');
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
if rst = '0' then v.hwrite := '0'; v.hready := '1'; end if;
write <= bs; ramsel <= v.hsel or r.hwrite; ahbso.hready <= r.hready;
ramaddr <= haddr; c <= v; ahbso.hrdata <= ramdata;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hcache <= '1';
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
ra : for i in 0 to 3 generate
aram : syncram generic map (tech, abits, 8) port map (
clk, ramaddr, ahbsi.hwdata(i*8+7 downto i*8),
ramdata(i*8+7 downto i*8), ramsel, write(3-i));
end generate;
reg : process (clk)
begin
if rising_edge(clk ) then r <= c; end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/leon3/mmulru.vhd | 2 | 5263 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmulru
-- File: mmulru.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU LRU logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmulru is
generic (
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end mmulru;
architecture rtl of mmulru is
constant entries_log : integer := log2(entries);
component mmulrue
generic (
position : integer;
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lruei : in mmulrue_in_type;
lrueo : out mmulrue_out_type
);
end component;
type lru_rtype is record
bar : std_logic_vector(1 downto 0);
clear : std_logic_vector(M_ENT_MAX-1 downto 0);
-- pragma translate_off
reinit : std_logic;
pos : std_logic_vector(entries_log-1 downto 0);
-- pragma translate_on
end record;
signal c,r : lru_rtype;
signal lruei : mmulruei_a (entries-1 downto 0);
signal lrueo : mmulrueo_a (entries-1 downto 0);
begin
p0: process (rst, r, c, lrui, lrueo)
variable v : lru_rtype;
variable reinit : std_logic;
variable v_lruei_clk : std_logic;
variable pos : std_logic_vector(entries_log-1 downto 0);
variable touch : std_logic;
begin
v := r;
-- #init
reinit := '0';
v_lruei_clk := rst;
--# eather element in luri or element 0 to top
pos := lrui.pos(entries_log-1 downto 0);
touch := lrui.touch;
if (lrui.touchmin) = '1' then
pos := lrueo(0).pos(entries_log-1 downto 0);
touch := '1';
end if;
for i in entries-1 downto 0 loop
lruei(i).pos <= (others => '0'); -- this is really ugly ...
lruei(i).left <= (others => '0');
lruei(i).right <= (others => '0');
lruei(i).pos(entries_log-1 downto 0) <= pos;
lruei(i).touch <= touch;
lruei(i).clear <= r.clear((entries-1)-i); -- reverse order
lruei(i).flush <= lrui.flush;
end loop;
lruei(entries-1).fromleft <= '0';
lruei(entries-1).fromright <= lrueo(entries-2).movetop;
lruei(entries-1).right(entries_log-1 downto 0) <= lrueo(entries-2).pos(entries_log-1 downto 0);
for i in entries-2 downto 1 loop
lruei(i).left(entries_log-1 downto 0) <= lrueo(i+1).pos(entries_log-1 downto 0);
lruei(i).right(entries_log-1 downto 0) <= lrueo(i-1).pos(entries_log-1 downto 0);
lruei(i).fromleft <= lrueo(i+1).movetop;
lruei(i).fromright <= lrueo(i-1).movetop;
end loop;
lruei(0).fromleft <= lrueo(1).movetop;
lruei(0).fromright <= '0';
lruei(0).left(entries_log-1 downto 0) <= lrueo(1).pos(entries_log-1 downto 0);
if not (r.bar = lrui.mmctrl1.bar) then
reinit := '1';
end if;
-- pragma translate_off
-- pragma translate_on
if (rst) = '0' then
v.bar := lrui.mmctrl1.bar;
reinit := '1';
end if;
if (reinit) = '1' then
v.bar := lrui.mmctrl1.bar;
v.clear := (others => '0');
case lrui.mmctrl1.bar is
when "01" =>
v.clear(1 downto 0) := "11"; -- reverse order
when "10" =>
v.clear(2 downto 0) := "111"; -- reverse order
when "11" =>
v.clear(4 downto 0) := "11111"; -- reverse order
when others =>
v.clear(0) := '1';
end case;
end if;
--# drive signals
-- pragma translate_off
v.reinit := reinit;
v.pos := pos;
-- pragma translate_on
lruo.pos <= lrueo(0).pos;
c <= v;
end process p0;
p1: process (clk)
begin if rising_edge(clk) then r <= c; end if;
end process p1;
--# lru entries
lrue0: for i in entries-1 downto 0 generate
l1 : mmulrue
generic map ( position => i,
entries => entries )
port map (rst, clk, lruei(i), lrueo(i));
end generate lrue0;
end rtl;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/sim/sram16.vhd | 2 | 2251 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram16
-- File: sram16.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 16-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram16 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram16 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+1, abits, tacc, fname)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index, abits, tacc, fname)
port map (a, d(15 downto 8), cex(1), we, oe);
end sim;
-- pragma translate_on
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/tech/proasic3/components/proasic3.vhd | 2 | 115108 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Actel proasic3 RAM component declarations
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
package components is
-- Proasic3 rams
component RAM4K9
generic (abits : integer range 9 to 12 := 9);
port(
ADDRA0, ADDRA1, ADDRA2, ADDRA3, ADDRA4, ADDRA5, ADDRA6, ADDRA7,
ADDRA8, ADDRA9, ADDRA10, ADDRA11 : in std_logic;
ADDRB0, ADDRB1, ADDRB2, ADDRB3, ADDRB4, ADDRB5, ADDRB6, ADDRB7,
ADDRB8, ADDRB9, ADDRB10, ADDRB11 : in std_logic;
BLKA, WENA, PIPEA, WMODEA, WIDTHA0, WIDTHA1, WENB, BLKB,
PIPEB, WMODEB, WIDTHB1, WIDTHB0 : in std_logic;
DINA0, DINA1, DINA2, DINA3, DINA4, DINA5, DINA6, DINA7, DINA8 : in std_logic;
DINB0, DINB1, DINB2, DINB3, DINB4, DINB5, DINB6, DINB7, DINB8 : in std_logic;
RESET, CLKA, CLKB : in std_logic;
DOUTA0, DOUTA1, DOUTA2, DOUTA3, DOUTA4, DOUTA5, DOUTA6, DOUTA7, DOUTA8 : out std_logic;
DOUTB0, DOUTB1, DOUTB2, DOUTB3, DOUTB4, DOUTB5, DOUTB6, DOUTB7, DOUTB8 : out std_logic
);
end component;
component RAM512X18
port(
RADDR8, RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_logic;
WADDR8, WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_logic;
WD17, WD16, WD15, WD14, WD13, WD12, WD11, WD10, WD9,
WD8, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0 : in std_logic;
REN, WEN, RESET, RW0, RW1, WW1, WW0, PIPE, RCLK, WCLK : in std_logic;
RD17, RD16, RD15, RD14, RD13, RD12, RD11, RD10, RD9,
RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0 : out std_logic
);
end component;
component PLL
generic(
VCOFREQUENCY : Real := 0.0;
f_CLKA_LOCK : Integer := 3; -- Number of CLKA pulses after which LOCK is raised
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
Xon : Boolean := False;
MsgOn : Boolean := True;
tipd_CLKA : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_EXTFB : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_POWERDOWN : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OADIV0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OADIV1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OADIV2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OADIV3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OADIV4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OAMUX0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OAMUX1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OAMUX2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLA0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLA1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLA2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLA3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLA4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBDIV0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBDIV1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBDIV2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBDIV3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBDIV4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBMUX0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBMUX1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBMUX2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYB0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYB1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYB2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYB3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYB4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLB0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLB1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLB2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLB3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLB4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCDIV0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCDIV1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCDIV2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCDIV3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCDIV4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCMUX0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCMUX1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCMUX2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYC0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYC1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYC2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYC3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYC4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLC0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLC1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLC2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLC3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLC4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV5 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV6 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV5 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV6 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDLY0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDLY1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDLY2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDLY3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDLY4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBSEL0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBSEL1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_XDLYSEL : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_VCOSEL0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_VCOSEL1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_VCOSEL2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tpd_CLKA_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_EXTFB_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_POWERDOWN_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_CLKA_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_EXTFB_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_POWERDOWN_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_CLKA_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_EXTFB_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_POWERDOWN_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_CLKA_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_EXTFB_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_POWERDOWN_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_CLKA_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_EXTFB_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_POWERDOWN_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_CLKA_LOCK : VitalDelayType01 := ( 0.100 ns, 0.100 ns));
port (
CLKA : in STD_ULOGIC;
EXTFB : in STD_ULOGIC;
POWERDOWN : in STD_ULOGIC;
OADIV0 : in STD_ULOGIC;
OADIV1 : in STD_ULOGIC;
OADIV2 : in STD_ULOGIC;
OADIV3 : in STD_ULOGIC;
OADIV4 : in STD_ULOGIC;
OAMUX0 : in STD_ULOGIC;
OAMUX1 : in STD_ULOGIC;
OAMUX2 : in STD_ULOGIC;
DLYGLA0 : in STD_ULOGIC;
DLYGLA1 : in STD_ULOGIC;
DLYGLA2 : in STD_ULOGIC;
DLYGLA3 : in STD_ULOGIC;
DLYGLA4 : in STD_ULOGIC;
OBDIV0 : in STD_ULOGIC;
OBDIV1 : in STD_ULOGIC;
OBDIV2 : in STD_ULOGIC;
OBDIV3 : in STD_ULOGIC;
OBDIV4 : in STD_ULOGIC;
OBMUX0 : in STD_ULOGIC;
OBMUX1 : in STD_ULOGIC;
OBMUX2 : in STD_ULOGIC;
DLYYB0 : in STD_ULOGIC;
DLYYB1 : in STD_ULOGIC;
DLYYB2 : in STD_ULOGIC;
DLYYB3 : in STD_ULOGIC;
DLYYB4 : in STD_ULOGIC;
DLYGLB0 : in STD_ULOGIC;
DLYGLB1 : in STD_ULOGIC;
DLYGLB2 : in STD_ULOGIC;
DLYGLB3 : in STD_ULOGIC;
DLYGLB4 : in STD_ULOGIC;
OCDIV0 : in STD_ULOGIC;
OCDIV1 : in STD_ULOGIC;
OCDIV2 : in STD_ULOGIC;
OCDIV3 : in STD_ULOGIC;
OCDIV4 : in STD_ULOGIC;
OCMUX0 : in STD_ULOGIC;
OCMUX1 : in STD_ULOGIC;
OCMUX2 : in STD_ULOGIC;
DLYYC0 : in STD_ULOGIC;
DLYYC1 : in STD_ULOGIC;
DLYYC2 : in STD_ULOGIC;
DLYYC3 : in STD_ULOGIC;
DLYYC4 : in STD_ULOGIC;
DLYGLC0 : in STD_ULOGIC;
DLYGLC1 : in STD_ULOGIC;
DLYGLC2 : in STD_ULOGIC;
DLYGLC3 : in STD_ULOGIC;
DLYGLC4 : in STD_ULOGIC;
FINDIV0 : in STD_ULOGIC;
FINDIV1 : in STD_ULOGIC;
FINDIV2 : in STD_ULOGIC;
FINDIV3 : in STD_ULOGIC;
FINDIV4 : in STD_ULOGIC;
FINDIV5 : in STD_ULOGIC;
FINDIV6 : in STD_ULOGIC;
FBDIV0 : in STD_ULOGIC;
FBDIV1 : in STD_ULOGIC;
FBDIV2 : in STD_ULOGIC;
FBDIV3 : in STD_ULOGIC;
FBDIV4 : in STD_ULOGIC;
FBDIV5 : in STD_ULOGIC;
FBDIV6 : in STD_ULOGIC;
FBDLY0 : in STD_ULOGIC;
FBDLY1 : in STD_ULOGIC;
FBDLY2 : in STD_ULOGIC;
FBDLY3 : in STD_ULOGIC;
FBDLY4 : in STD_ULOGIC;
FBSEL0 : in STD_ULOGIC;
FBSEL1 : in STD_ULOGIC;
XDLYSEL : in STD_ULOGIC;
VCOSEL0 : in STD_ULOGIC;
VCOSEL1 : in STD_ULOGIC;
VCOSEL2 : in STD_ULOGIC;
GLA : out STD_ULOGIC;
LOCK : out STD_ULOGIC;
GLB : out STD_ULOGIC;
YB : out STD_ULOGIC;
GLC : out STD_ULOGIC;
YC : out STD_ULOGIC);
end component;
component CLKBUF port(Y : out std_logic; PAD : in std_logic); end component;
component CLKBUF_LVCMOS18 port(Y : out std_logic; PAD : in std_logic); end component;
component CLKBUF_LVCMOS25 port(Y : out std_logic; PAD : in std_logic); end component;
component CLKBUF_LVCMOS33 port(Y : out std_logic; PAD : in std_logic); end component;
component CLKBUF_LVCMOS5 port(Y : out std_logic; PAD : in std_logic); end component;
component CLKBUF_PCI port(Y : out std_logic; PAD : in std_logic); end component;
component CLKINT port( A : in std_logic; Y :out std_logic); end component;
component PLLINT port( A : in std_logic; Y :out std_logic); end component;
component UJTAG
port(
UTDO : in STD_ULOGIC;
TMS : in STD_ULOGIC;
TDI : in STD_ULOGIC;
TCK : in STD_ULOGIC;
TRSTB : in STD_ULOGIC;
UIREG0 : out STD_ULOGIC;
UIREG1 : out STD_ULOGIC;
UIREG2 : out STD_ULOGIC;
UIREG3 : out STD_ULOGIC;
UIREG4 : out STD_ULOGIC;
UIREG5 : out STD_ULOGIC;
UIREG6 : out STD_ULOGIC;
UIREG7 : out STD_ULOGIC;
UTDI : out STD_ULOGIC;
URSTB : out STD_ULOGIC;
UDRCK : out STD_ULOGIC;
UDRCAP : out STD_ULOGIC;
UDRSH : out STD_ULOGIC;
UDRUPD : out STD_ULOGIC;
TDO : out STD_ULOGIC);
end component;
end;
library ieee;
use ieee.std_logic_1164.all;
entity PLLINT is port(Y : out std_logic; A : in std_logic); end;
architecture rtl of PLLINT is begin Y <= A; end;
library ieee;
use ieee.std_logic_1164.all;
entity CLKINT is port(Y : out std_logic; A : in std_logic); end;
architecture rtl of CLKINT is begin Y <= A; end;
library ieee;
use ieee.std_logic_1164.all;
entity CLKBUF is port(Y : out std_logic; PAD : in std_logic); end;
architecture rtl of CLKBUF is begin Y <= PAD; end;
library ieee;
use ieee.std_logic_1164.all;
entity CLKBUF_PCI is port(Y : out std_logic; PAD : in std_logic); end;
architecture rtl of CLKBUF_PCI is begin Y <= PAD; end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM4K9 is generic (abits : integer range 9 to 12 := 9);
port(
ADDRA0, ADDRA1, ADDRA2, ADDRA3, ADDRA4, ADDRA5, ADDRA6, ADDRA7,
ADDRA8, ADDRA9, ADDRA10, ADDRA11 : in std_logic;
ADDRB0, ADDRB1, ADDRB2, ADDRB3, ADDRB4, ADDRB5, ADDRB6, ADDRB7,
ADDRB8, ADDRB9, ADDRB10, ADDRB11 : in std_logic;
BLKA, WENA, PIPEA, WMODEA, WIDTHA0, WIDTHA1, WENB, BLKB,
PIPEB, WMODEB, WIDTHB1, WIDTHB0 : in std_logic;
DINA0, DINA1, DINA2, DINA3, DINA4, DINA5, DINA6, DINA7, DINA8 : in std_logic;
DINB0, DINB1, DINB2, DINB3, DINB4, DINB5, DINB6, DINB7, DINB8 : in std_logic;
RESET, CLKA, CLKB : in std_logic;
DOUTA0, DOUTA1, DOUTA2, DOUTA3, DOUTA4, DOUTA5, DOUTA6, DOUTA7, DOUTA8 : out std_logic;
DOUTB0, DOUTB1, DOUTB2, DOUTB3, DOUTB4, DOUTB5, DOUTB6, DOUTB7, DOUTB8 : out std_logic
);
end ;
architecture sim of RAM4K9 is
type dwarrtype is array (9 to 12) of integer;
constant dwarr : dwarrtype := (9, 4, 2, 1);
constant dwidth : integer := dwarr(abits);
subtype memword is std_logic_vector(dwidth-1 downto 0);
type memtype is array (0 to 2**abits-1) of memword;
begin
p1 : process(CLKA, CLKB, RESET)
variable mem : memtype;
variable ra, rb : std_logic_vector(11 downto 0);
variable da, db : std_logic_vector(8 downto 0);
variable qa, qb : std_logic_vector(8 downto 0);
variable qal, qbl : std_logic_vector(8 downto 0);
variable qao, qbo : std_logic_vector(8 downto 0);
begin
if rising_edge(CLKA) then
ra := ADDRA11 & ADDRA10 & ADDRA9 & ADDRA8 & ADDRA7 & ADDRA6 & ADDRA5 &
ADDRA4 & ADDRA3 & ADDRA2 & ADDRA1 & ADDRA0;
da := DINA8 & DINA7 & DINA6 & DINA5 & DINA4 & DINA3 & DINA2 &
DINA1 & DINA0;
if BLKA = '0' then
if not (is_x (ra(abits-1 downto 0))) then
qa(dwidth-1 downto 0) := mem(to_integer(unsigned(ra(abits-1 downto 0))));
else qa := (others => 'X'); end if;
if WENA = '0' and not (is_x (ra(abits-1 downto 0))) then
mem(to_integer(unsigned(ra(abits-1 downto 0)))) := da(dwidth-1 downto 0);
if WMODEA = '1' then qa := da(dwidth-1 downto 0); end if;
end if;
elsif is_x(BLKA) then qa := (others => 'X'); end if;
if PIPEA = '1' then qao := qal; else qao := qa; end if;
qal := qa;
end if;
if reset = '0' then qao := (others => '0'); end if;
(DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2,
DOUTA1, DOUTA0) <= qao;
if rising_edge(CLKB) then
rb := ADDRB11 & ADDRB10 & ADDRB9 & ADDRB8 & ADDRB7 & ADDRB6 & ADDRB5 &
ADDRB4 & ADDRB3 & ADDRB2 & ADDRB1 & ADDRB0;
db := DINB8 & DINB7 & DINB6 & DINB5 & DINB4 & DINB3 & DINB2 &
DINB1 & DINB0;
if BLKB = '0' then
if not (is_x (rb(abits-1 downto 0))) then
qb(dwidth-1 downto 0) := mem(to_integer(unsigned(rb(abits-1 downto 0))));
else qb := (others => 'X'); end if;
if WENB = '0' and not (is_x (rb(abits-1 downto 0))) then
mem(to_integer(unsigned(rb(abits-1 downto 0)))) := db(dwidth-1 downto 0);
if WMODEB = '1' then qb := db(dwidth-1 downto 0); end if;
end if;
elsif is_x(BLKB) then qb := (others => 'X'); end if;
if PIPEB = '1' then qbo := qbl; else qbo := qb; end if;
qbl := qb;
end if;
if reset = '0' then qbo := (others => '0'); end if;
(DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2,
DOUTB1, DOUTB0) <= qbo;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM512X18 is
port(
RADDR8, RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_logic;
WADDR8, WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_logic;
WD17, WD16, WD15, WD14, WD13, WD12, WD11, WD10, WD9,
WD8, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0 : in std_logic;
REN, WEN, RESET, RW0, RW1, WW1, WW0, PIPE, RCLK, WCLK : in std_logic;
RD17, RD16, RD15, RD14, RD13, RD12, RD11, RD10, RD9,
RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0 : out std_logic
);
end ;
architecture sim of RAM512X18 is
constant abits : integer := 8;
constant dwidth : integer := 18;
subtype memword is std_logic_vector(dwidth-1 downto 0);
type memtype is array (0 to 2**abits-1) of memword;
begin
p1 : process(RCLK, WCLK, RESET)
variable mem : memtype;
variable ra, rb : std_logic_vector(8 downto 0);
variable da : std_logic_vector(17 downto 0);
variable qb : std_logic_vector(17 downto 0);
variable qbl : std_logic_vector(17 downto 0);
variable qbo : std_logic_vector(17 downto 0);
begin
if rising_edge(WCLK) then
ra := '0' & WADDR7 & WADDR6 & WADDR5 &
WADDR4 & WADDR3 & WADDR2 & WADDR1 & WADDR0;
da := WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 &
Wd10 & WD9 & WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 &
WD1 & WD0;
if WEN = '0' and not (is_x (ra(abits-1 downto 0))) then
mem(to_integer(unsigned(ra(abits-1 downto 0)))) := da(dwidth-1 downto 0);
end if;
end if;
if rising_edge(RCLK) then
rb := '0' & RADDR7 & RADDR6 & RADDR5 &
RADDR4 & RADDR3 & RADDR2 & RADDR1 & RADDR0;
if REN = '0' then
if not (is_x (rb(abits-1 downto 0))) then
qb := mem(to_integer(unsigned(rb(abits-1 downto 0))));
else qb := (others => 'X'); end if;
elsif is_x(REN) then qb := (others => 'X'); end if;
if PIPE = '1' then qbo := qbl; else qbo := qb; end if;
qbl := qb;
end if;
if RESET = '0' then qbo := (others => '0'); end if;
(RD17, RD16, RD15, RD14, RD13, RD12, RD11, RD10, RD9,
RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0) <= qbo;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity PLLPRIM is
generic (
VCOFREQUENCY : Real := 0.0;
f_CLKA_LOCK : Integer := 3; -- Number of CLKA pulses after which LOCK is raised
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
Xon : Boolean := False;
MsgOn : Boolean := True;
EMULATED_SYSTEM_DELAY : Time := 2.290 ns; -- Delay Tap Additional CLK delay
IN_DIV_DELAY : Time := 0.335 ns; -- Input Divider intrinsic delay
OUT_DIV_DELAY : Time := 0.770 ns; -- Output Divider intrinsic delay
MUX_DELAY : Time := 1.200 ns; -- MUXA/MUXB/MUXC intrinsic delay
IN_DELAY_BYP1 : Time := 1.523 ns; -- Input delay for CLKDIVDLY bypass mode
BYP_MUX_DELAY : Time := 0.040 ns; -- Bypass MUX intrinsic delay, not used for Ys
GL_DRVR_DELAY : Time := 0.060 ns; -- Global Driver intrinsic delay
Y_DRVR_DELAY : Time := 0.285 ns; -- Y Driver intrinsic delay
FB_MUX_DELAY : Time := 0.145 ns; -- FBSEL MUX intrinsic delay
X_MUX_DELAY : Time := 0.625 ns; -- XDLYSEL MUX intrinsic delay
FIN_LOCK_DELAY : Time := 0.300 ns; -- FIN to LOCK propagation delay
LOCK_OUT_DELAY : Time := 0.120 ns; -- LOCK to OUT propagation delay
PROG_INIT_DELAY : Time := 0.535 ns;
PROG_STEP_INCREMENT : Time := 0.200 ns;
BYP0_CLK_GL : Time := 0.200 ns; -- Intrinsic delay for CLKDLY bypass mode
CLKA_TO_REF_DELAY : Time := 0.395 ns;
tipd_DYNSYNC : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_CLKA : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_EXTFB : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_POWERDOWN : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_CLKB : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_CLKC : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIVRST : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIVHALF : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIVRST : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIVHALF : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIVRST : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIVHALF : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV5 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV6 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV5 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV6 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBSEL0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBSEL1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_XDLYSEL : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tpd_CLKA_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_LOCK : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_LOCK : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_LOCK : VitalDelayType01 := ( 0.100 ns, 0.100 ns )
);
port (
DYNSYNC : in std_ulogic;
CLKA : in std_ulogic;
EXTFB : in std_ulogic;
POWERDOWN : in std_ulogic;
CLKB : in std_ulogic;
CLKC : in std_ulogic;
OADIVRST : in std_ulogic;
OADIVHALF : in std_ulogic;
OADIV0 : in std_ulogic;
OADIV1 : in std_ulogic;
OADIV2 : in std_ulogic;
OADIV3 : in std_ulogic;
OADIV4 : in std_ulogic;
OAMUX0 : in std_ulogic;
OAMUX1 : in std_ulogic;
OAMUX2 : in std_ulogic;
DLYGLA0 : in std_ulogic;
DLYGLA1 : in std_ulogic;
DLYGLA2 : in std_ulogic;
DLYGLA3 : in std_ulogic;
DLYGLA4 : in std_ulogic;
OBDIVRST : in std_ulogic;
OBDIVHALF : in std_ulogic;
OBDIV0 : in std_ulogic;
OBDIV1 : in std_ulogic;
OBDIV2 : in std_ulogic;
OBDIV3 : in std_ulogic;
OBDIV4 : in std_ulogic;
OBMUX0 : in std_ulogic;
OBMUX1 : in std_ulogic;
OBMUX2 : in std_ulogic;
DLYYB0 : in std_ulogic;
DLYYB1 : in std_ulogic;
DLYYB2 : in std_ulogic;
DLYYB3 : in std_ulogic;
DLYYB4 : in std_ulogic;
DLYGLB0 : in std_ulogic;
DLYGLB1 : in std_ulogic;
DLYGLB2 : in std_ulogic;
DLYGLB3 : in std_ulogic;
DLYGLB4 : in std_ulogic;
OCDIVRST : in std_ulogic;
OCDIVHALF : in std_ulogic;
OCDIV0 : in std_ulogic;
OCDIV1 : in std_ulogic;
OCDIV2 : in std_ulogic;
OCDIV3 : in std_ulogic;
OCDIV4 : in std_ulogic;
OCMUX0 : in std_ulogic;
OCMUX1 : in std_ulogic;
OCMUX2 : in std_ulogic;
DLYYC0 : in std_ulogic;
DLYYC1 : in std_ulogic;
DLYYC2 : in std_ulogic;
DLYYC3 : in std_ulogic;
DLYYC4 : in std_ulogic;
DLYGLC0 : in std_ulogic;
DLYGLC1 : in std_ulogic;
DLYGLC2 : in std_ulogic;
DLYGLC3 : in std_ulogic;
DLYGLC4 : in std_ulogic;
FINDIV0 : in std_ulogic;
FINDIV1 : in std_ulogic;
FINDIV2 : in std_ulogic;
FINDIV3 : in std_ulogic;
FINDIV4 : in std_ulogic;
FINDIV5 : in std_ulogic;
FINDIV6 : in std_ulogic;
FBDIV0 : in std_ulogic;
FBDIV1 : in std_ulogic;
FBDIV2 : in std_ulogic;
FBDIV3 : in std_ulogic;
FBDIV4 : in std_ulogic;
FBDIV5 : in std_ulogic;
FBDIV6 : in std_ulogic;
FBDLY0 : in std_ulogic;
FBDLY1 : in std_ulogic;
FBDLY2 : in std_ulogic;
FBDLY3 : in std_ulogic;
FBDLY4 : in std_ulogic;
FBSEL0 : in std_ulogic;
FBSEL1 : in std_ulogic;
XDLYSEL : in std_ulogic;
VCOSEL0 : in std_ulogic;
VCOSEL1 : in std_ulogic;
VCOSEL2 : in std_ulogic;
GLA : out std_ulogic;
LOCK : out std_ulogic;
GLB : out std_ulogic;
YB : out std_ulogic;
GLC : out std_ulogic;
YC : out std_ulogic
);
attribute VITAL_LEVEL0 of PLLPRIM : entity is TRUE;
end PLLPRIM;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL_ACT of PLLPRIM is
attribute VITAL_LEVEL1 of VITAL_ACT : architecture is FALSE;
signal DYNSYNC_ipd : std_ulogic;
signal CLKA_ipd : std_ulogic;
signal EXTFB_ipd : std_ulogic;
signal POWERDOWN_ipd : std_ulogic;
signal CLKB_ipd : std_ulogic;
signal CLKC_ipd : std_ulogic;
signal OADIVRST_ipd : std_ulogic;
signal OADIVHALF_ipd : std_ulogic;
signal OADIV0_ipd : std_ulogic;
signal OADIV1_ipd : std_ulogic;
signal OADIV2_ipd : std_ulogic;
signal OADIV3_ipd : std_ulogic;
signal OADIV4_ipd : std_ulogic;
signal OAMUX0_ipd : std_ulogic;
signal OAMUX1_ipd : std_ulogic;
signal OAMUX2_ipd : std_ulogic;
signal DLYGLA0_ipd : std_ulogic;
signal DLYGLA1_ipd : std_ulogic;
signal DLYGLA2_ipd : std_ulogic;
signal DLYGLA3_ipd : std_ulogic;
signal DLYGLA4_ipd : std_ulogic;
signal OBDIVRST_ipd : std_ulogic;
signal OBDIVHALF_ipd : std_ulogic;
signal OBDIV0_ipd : std_ulogic;
signal OBDIV1_ipd : std_ulogic;
signal OBDIV2_ipd : std_ulogic;
signal OBDIV3_ipd : std_ulogic;
signal OBDIV4_ipd : std_ulogic;
signal OBMUX0_ipd : std_ulogic;
signal OBMUX1_ipd : std_ulogic;
signal OBMUX2_ipd : std_ulogic;
signal DLYYB0_ipd : std_ulogic;
signal DLYYB1_ipd : std_ulogic;
signal DLYYB2_ipd : std_ulogic;
signal DLYYB3_ipd : std_ulogic;
signal DLYYB4_ipd : std_ulogic;
signal DLYGLB0_ipd : std_ulogic;
signal DLYGLB1_ipd : std_ulogic;
signal DLYGLB2_ipd : std_ulogic;
signal DLYGLB3_ipd : std_ulogic;
signal DLYGLB4_ipd : std_ulogic;
signal OCDIVRST_ipd : std_ulogic;
signal OCDIVHALF_ipd : std_ulogic;
signal OCDIV0_ipd : std_ulogic;
signal OCDIV1_ipd : std_ulogic;
signal OCDIV2_ipd : std_ulogic;
signal OCDIV3_ipd : std_ulogic;
signal OCDIV4_ipd : std_ulogic;
signal OCMUX0_ipd : std_ulogic;
signal OCMUX1_ipd : std_ulogic;
signal OCMUX2_ipd : std_ulogic;
signal DLYYC0_ipd : std_ulogic;
signal DLYYC1_ipd : std_ulogic;
signal DLYYC2_ipd : std_ulogic;
signal DLYYC3_ipd : std_ulogic;
signal DLYYC4_ipd : std_ulogic;
signal DLYGLC0_ipd : std_ulogic;
signal DLYGLC1_ipd : std_ulogic;
signal DLYGLC2_ipd : std_ulogic;
signal DLYGLC3_ipd : std_ulogic;
signal DLYGLC4_ipd : std_ulogic;
signal FINDIV0_ipd : std_ulogic;
signal FINDIV1_ipd : std_ulogic;
signal FINDIV2_ipd : std_ulogic;
signal FINDIV3_ipd : std_ulogic;
signal FINDIV4_ipd : std_ulogic;
signal FINDIV5_ipd : std_ulogic;
signal FINDIV6_ipd : std_ulogic;
signal FBDIV0_ipd : std_ulogic;
signal FBDIV1_ipd : std_ulogic;
signal FBDIV2_ipd : std_ulogic;
signal FBDIV3_ipd : std_ulogic;
signal FBDIV4_ipd : std_ulogic;
signal FBDIV5_ipd : std_ulogic;
signal FBDIV6_ipd : std_ulogic;
signal FBDLY0_ipd : std_ulogic;
signal FBDLY1_ipd : std_ulogic;
signal FBDLY2_ipd : std_ulogic;
signal FBDLY3_ipd : std_ulogic;
signal FBDLY4_ipd : std_ulogic;
signal FBSEL0_ipd : std_ulogic;
signal FBSEL1_ipd : std_ulogic;
signal XDLYSEL_ipd : std_ulogic;
signal VCOSEL0_ipd : std_ulogic;
signal VCOSEL1_ipd : std_ulogic;
signal VCOSEL2_ipd : std_ulogic;
signal AOUT : std_logic := 'X';
signal BOUT : std_logic := 'X';
signal COUT : std_logic := 'X';
signal PLLCLK : std_logic := 'X'; -- PLL Core Output Clock
-- with DIVN and DIVM applied
signal CLKA_period : Time := 0.000 ns; -- Current CLKA period
signal PLLCLK_pw : Time := 10.0 ns; -- PLLCLK pulse width
signal PLLCLK_period : Time := 10.0 ns;
signal DIVN : Integer := 1; -- Divide by N divisor - range 1 to 128
signal DIVM : Integer := 1; -- Multiply by M multiplier - range 1 to 128
signal DIVU : Integer := 1; -- Divide by U divisor - range 1 to 32
signal DIVV : Integer := 1; -- Divide by V divisor - range 1 to 32
signal DIVW : Integer := 1; -- Divide by W divisor - range 1 to 32
signal fb_loop_div : Integer := 1; -- Total division of feedback loop
signal halveA : std_logic := 'X';
signal halveB : std_logic := 'X';
signal halveC : std_logic := 'X';
signal CLKA2X : std_logic := 'X';
signal CLKB2X : std_logic := 'X';
signal CLKC2X : std_logic := 'X';
signal UIN : std_logic := 'X'; -- Output of MUXA
signal VIN : std_logic := 'X'; -- Output of MUXB
signal WIN : std_logic := 'X'; -- Output of MUXC
signal FBDELAY : Time := 0.000 ns; -- Feedback delay
signal DTDELAY : Time := 0.000 ns; -- Delay Tap delay
signal PLLDELAY : Time := 0.000 ns; -- Sum of Feedback and Delay Tap delays
signal YBDELAY : Time := 0.000 ns; -- Additional Global B Delay
signal GLBDELAY : Time := 0.000 ns; -- Additional Global B Delay
signal YCDELAY : Time := 0.000 ns; -- Additional Global C Delay
signal GLCDELAY : Time := 0.000 ns; -- Additional Global C Delay
signal GLADELAY : Time := 0.000 ns; -- Additional Global A Delay
signal FBSEL : std_logic_vector( 1 downto 0 ) := "XX";
signal FBSEL_illegal : Boolean := False; -- True when FBSEL = 00
signal OAMUX_config : integer := -1;
signal OBMUX_config : integer := -1;
signal OCMUX_config : integer := -1;
signal internal_lock : boolean := false;
signal fin_period : Time := 0.000 ns;
signal extfbin_fin_drift : time := 0 ps;
signal locked : std_logic := '0'; -- 1 when PLL is externally locked as well as internally locked
signal locked_vco0_edges : integer := -1;
signal vco0_divu : std_logic := '0';
signal vco0_divv : std_logic := '0';
signal vco0_divw : std_logic := '0';
signal fin : std_logic := '0';
signal CLKA_period_stable : boolean := false;
signal using_EXTFB : std_logic := 'X';
signal EXTFB_delay_dtrmd : Boolean := false;
signal calibrate_EXTFB_delay : std_logic := '0';
signal GLA_free_running : std_logic := '1';
signal AOUT_using_EXTFB : std_logic := '1';
signal GLA_pw : time := 10.0 ns; -- Only used for external feedback
signal GLA_EXTFB_rise_dly : time := 0.0 ns; -- Only meaningful for external feedback
signal GLA_EXTFB_fall_dly : time := 0.0 ns; -- Only meaningful for external feedback
signal EXTFB_period : time := 20.0 ns; -- Only meaningful for external feedback
signal expected_EXTFB : std_logic := 'X';
signal external_dly_correct : std_logic := 'X';
signal gla_muxed_delay : time := 0.000 ns;
signal glb_muxed_delay : time := 0.000 ns;
signal glc_muxed_delay : time := 0.000 ns;
signal internal_fb_delay : time := 0.000 ns;
signal external_fb_delay : time := 0.000 ns;
signal normalized_fb_delay : time := 0.000 ns; -- Sum of all delays in the feedback loop from VCO to FBIN normalized to be less than or equal to fin period so that no negative delay assignments are made.
signal CLKA_2_GLA_dly : time := 0.000 ns;
signal CLKA_2_GLA_bypass0_dly : time := 0.000 ns;
signal CLKA_2_GLA_bypass1_dly : time := 0.000 ns;
signal CLKA_2_GLB_dly : time := 0.000 ns;
signal CLKB_2_GLB_bypass0_dly : time := 0.000 ns;
signal CLKB_2_GLB_bypass1_dly : time := 0.000 ns;
signal CLKA_2_YB_dly : time := 0.000 ns;
signal CLKB_2_YB_bypass1_dly : time := 0.000 ns;
signal CLKA_2_GLC_dly : time := 0.000 ns;
signal CLKC_2_GLC_bypass0_dly : time := 0.000 ns;
signal CLKC_2_GLC_bypass1_dly : time := 0.000 ns;
signal CLKA_2_YC_dly : time := 0.000 ns;
signal CLKC_2_YC_bypass1_dly : time := 0.000 ns;
signal CLKA_2_LOCK_dly : time := 0.000 ns;
-- Use this instead of CONV_INTEGER to avoid ambiguous warnings
function ulogic2int(
vec : std_ulogic_vector )
return integer is
variable result : integer;
variable i : integer;
begin
result := 0;
for i in vec'range loop
result := result * 2;
if vec(i) = '1' then
result := result + 1;
end if;
end loop;
return result;
end function ulogic2int;
function output_mux_delay(
outmux : integer;
vcobit2 : std_logic;
vcobit1 : std_logic;
fbdly_delay : time;
vco_pw : time )
return time is
variable result : time;
begin
case outmux is
when 1 => result := IN_DELAY_BYP1;
when 2 => result := MUX_DELAY + fbdly_delay;
when 5 => if ( ( vcobit2 = '1') and ( vcobit1 = '1') ) then
result := MUX_DELAY + ( vco_pw / 2.0 );
else
result := MUX_DELAY + ( vco_pw * 1.5 );
end if;
when 6 => result := MUX_DELAY + vco_pw;
when 7 => if ( ( vcobit2 = '1') and ( vcobit1 = '1') ) then
result := MUX_DELAY + ( vco_pw * 1.5 );
else
result := MUX_DELAY + ( vco_pw / 2.0 );
end if;
when others => result := MUX_DELAY;
end case;
return result;
end function output_mux_delay;
function output_mux_driver(
outmux : integer;
halved : std_logic;
bypass : std_logic;
bypass2x : std_logic;
vco : std_logic )
return std_logic is
variable result : std_logic;
begin
case outmux is
when 1 => if ( '1' = halved ) then
result := bypass2x;
elsif ( '0' = halved ) then
result := bypass;
else
result := 'X';
end if;
when 2 => result := vco;
when 4 => result := vco;
when 5 => result := vco;
when 6 => result := vco;
when 7 => result := vco;
when others => result := 'X';
end case;
return result;
end function output_mux_driver;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay ( DYNSYNC_ipd, DYNSYNC, tipd_DYNSYNC );
VitalWireDelay ( CLKA_ipd, CLKA, tipd_CLKA );
VitalWireDelay ( EXTFB_ipd, EXTFB, tipd_EXTFB );
VitalWireDelay ( POWERDOWN_ipd, POWERDOWN, tipd_POWERDOWN );
VitalWireDelay ( CLKB_ipd, CLKB, tipd_CLKB );
VitalWireDelay ( CLKC_ipd, CLKC, tipd_CLKC );
VitalWireDelay ( OADIVRST_ipd, OADIVRST, tipd_OADIVRST );
VitalWireDelay ( OADIVHALF_ipd, OADIVHALF, tipd_OADIVHALF );
VitalWireDelay ( OADIV0_ipd, OADIV0, tipd_OADIV0 );
VitalWireDelay ( OADIV1_ipd, OADIV1, tipd_OADIV1 );
VitalWireDelay ( OADIV2_ipd, OADIV2, tipd_OADIV2 );
VitalWireDelay ( OADIV3_ipd, OADIV3, tipd_OADIV3 );
VitalWireDelay ( OADIV4_ipd, OADIV4, tipd_OADIV4 );
VitalWireDelay ( OAMUX0_ipd, OAMUX0, tipd_OAMUX0 );
VitalWireDelay ( OAMUX1_ipd, OAMUX1, tipd_OAMUX1 );
VitalWireDelay ( OAMUX2_ipd, OAMUX2, tipd_OAMUX2 );
VitalWireDelay ( DLYGLA0_ipd, DLYGLA0, tipd_DLYGLA0 );
VitalWireDelay ( DLYGLA1_ipd, DLYGLA1, tipd_DLYGLA1 );
VitalWireDelay ( DLYGLA2_ipd, DLYGLA2, tipd_DLYGLA2 );
VitalWireDelay ( DLYGLA3_ipd, DLYGLA3, tipd_DLYGLA3 );
VitalWireDelay ( DLYGLA4_ipd, DLYGLA4, tipd_DLYGLA4 );
VitalWireDelay ( OBDIVRST_ipd, OBDIVRST, tipd_OBDIVRST );
VitalWireDelay ( OBDIVHALF_ipd, OBDIVHALF, tipd_OBDIVHALF );
VitalWireDelay ( OBDIV0_ipd, OBDIV0, tipd_OBDIV0 );
VitalWireDelay ( OBDIV1_ipd, OBDIV1, tipd_OBDIV1 );
VitalWireDelay ( OBDIV2_ipd, OBDIV2, tipd_OBDIV2 );
VitalWireDelay ( OBDIV3_ipd, OBDIV3, tipd_OBDIV3 );
VitalWireDelay ( OBDIV4_ipd, OBDIV4, tipd_OBDIV4 );
VitalWireDelay ( OBMUX0_ipd, OBMUX0, tipd_OBMUX0 );
VitalWireDelay ( OBMUX1_ipd, OBMUX1, tipd_OBMUX1 );
VitalWireDelay ( OBMUX2_ipd, OBMUX2, tipd_OBMUX2 );
VitalWireDelay ( DLYYB0_ipd, DLYYB0, tipd_DLYYB0 );
VitalWireDelay ( DLYYB1_ipd, DLYYB1, tipd_DLYYB1 );
VitalWireDelay ( DLYYB2_ipd, DLYYB2, tipd_DLYYB2 );
VitalWireDelay ( DLYYB3_ipd, DLYYB3, tipd_DLYYB3 );
VitalWireDelay ( DLYYB4_ipd, DLYYB4, tipd_DLYYB4 );
VitalWireDelay ( DLYGLB0_ipd, DLYGLB0, tipd_DLYGLB0 );
VitalWireDelay ( DLYGLB1_ipd, DLYGLB1, tipd_DLYGLB1 );
VitalWireDelay ( DLYGLB2_ipd, DLYGLB2, tipd_DLYGLB2 );
VitalWireDelay ( DLYGLB3_ipd, DLYGLB3, tipd_DLYGLB3 );
VitalWireDelay ( DLYGLB4_ipd, DLYGLB4, tipd_DLYGLB4 );
VitalWireDelay ( OCDIVRST_ipd, OCDIVRST, tipd_OCDIVRST );
VitalWireDelay ( OCDIVHALF_ipd, OCDIVHALF, tipd_OCDIVHALF );
VitalWireDelay ( OCDIV0_ipd, OCDIV0, tipd_OCDIV0 );
VitalWireDelay ( OCDIV1_ipd, OCDIV1, tipd_OCDIV1 );
VitalWireDelay ( OCDIV2_ipd, OCDIV2, tipd_OCDIV2 );
VitalWireDelay ( OCDIV3_ipd, OCDIV3, tipd_OCDIV3 );
VitalWireDelay ( OCDIV4_ipd, OCDIV4, tipd_OCDIV4 );
VitalWireDelay ( OCMUX0_ipd, OCMUX0, tipd_OCMUX0 );
VitalWireDelay ( OCMUX1_ipd, OCMUX1, tipd_OCMUX1 );
VitalWireDelay ( OCMUX2_ipd, OCMUX2, tipd_OCMUX2 );
VitalWireDelay ( DLYYC0_ipd, DLYYC0, tipd_DLYYC0 );
VitalWireDelay ( DLYYC1_ipd, DLYYC1, tipd_DLYYC1 );
VitalWireDelay ( DLYYC2_ipd, DLYYC2, tipd_DLYYC2 );
VitalWireDelay ( DLYYC3_ipd, DLYYC3, tipd_DLYYC3 );
VitalWireDelay ( DLYYC4_ipd, DLYYC4, tipd_DLYYC4 );
VitalWireDelay ( DLYGLC0_ipd, DLYGLC0, tipd_DLYGLC0 );
VitalWireDelay ( DLYGLC1_ipd, DLYGLC1, tipd_DLYGLC1 );
VitalWireDelay ( DLYGLC2_ipd, DLYGLC2, tipd_DLYGLC2 );
VitalWireDelay ( DLYGLC3_ipd, DLYGLC3, tipd_DLYGLC3 );
VitalWireDelay ( DLYGLC4_ipd, DLYGLC4, tipd_DLYGLC4 );
VitalWireDelay ( FINDIV0_ipd, FINDIV0, tipd_FINDIV0 );
VitalWireDelay ( FINDIV1_ipd, FINDIV1, tipd_FINDIV1 );
VitalWireDelay ( FINDIV2_ipd, FINDIV2, tipd_FINDIV2 );
VitalWireDelay ( FINDIV3_ipd, FINDIV3, tipd_FINDIV3 );
VitalWireDelay ( FINDIV4_ipd, FINDIV4, tipd_FINDIV4 );
VitalWireDelay ( FINDIV5_ipd, FINDIV5, tipd_FINDIV5 );
VitalWireDelay ( FINDIV6_ipd, FINDIV6, tipd_FINDIV6 );
VitalWireDelay ( FBDIV0_ipd, FBDIV0, tipd_FBDIV0 );
VitalWireDelay ( FBDIV1_ipd, FBDIV1, tipd_FBDIV1 );
VitalWireDelay ( FBDIV2_ipd, FBDIV2, tipd_FBDIV2 );
VitalWireDelay ( FBDIV3_ipd, FBDIV3, tipd_FBDIV3 );
VitalWireDelay ( FBDIV4_ipd, FBDIV4, tipd_FBDIV4 );
VitalWireDelay ( FBDIV5_ipd, FBDIV5, tipd_FBDIV5 );
VitalWireDelay ( FBDIV6_ipd, FBDIV6, tipd_FBDIV6 );
VitalWireDelay ( FBDLY0_ipd, FBDLY0, tipd_FBDLY0 );
VitalWireDelay ( FBDLY1_ipd, FBDLY1, tipd_FBDLY1 );
VitalWireDelay ( FBDLY2_ipd, FBDLY2, tipd_FBDLY2 );
VitalWireDelay ( FBDLY3_ipd, FBDLY3, tipd_FBDLY3 );
VitalWireDelay ( FBDLY4_ipd, FBDLY4, tipd_FBDLY4 );
VitalWireDelay ( FBSEL0_ipd, FBSEL0, tipd_FBSEL0 );
VitalWireDelay ( FBSEL1_ipd, FBSEL1, tipd_FBSEL1 );
VitalWireDelay ( XDLYSEL_ipd, XDLYSEL, tipd_XDLYSEL );
VitalWireDelay ( VCOSEL0_ipd, VCOSEL0, tipd_VCOSEL0 );
VitalWireDelay ( VCOSEL1_ipd, VCOSEL1, tipd_VCOSEL1 );
VitalWireDelay ( VCOSEL2_ipd, VCOSEL2, tipd_VCOSEL2 );
end block WireDelay;
-- #########################################################
-- # Behavior Section
-- #########################################################
OAMUX_config <= ulogic2int( OAMUX2_ipd & OAMUX1_ipd & OAMUX0_ipd );
OBMUX_config <= ulogic2int( OBMUX2_ipd & OBMUX1_ipd & OBMUX0_ipd );
OCMUX_config <= ulogic2int( OCMUX2_ipd & OCMUX1_ipd & OCMUX0_ipd );
FBSEL <= TO_X01( FBSEL1_ipd & FBSEL0_ipd );
CLKA_2_GLA_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + gla_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLADELAY + GL_DRVR_DELAY;
CLKA_2_GLA_bypass0_dly <= BYP0_CLK_GL + GLADELAY;
CLKA_2_GLA_bypass1_dly <= gla_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLADELAY + GL_DRVR_DELAY;
CLKA_2_GLB_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glb_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLBDELAY + GL_DRVR_DELAY;
CLKB_2_GLB_bypass0_dly <= BYP0_CLK_GL + GLBDELAY;
CLKB_2_GLB_bypass1_dly <= glb_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLBDELAY + GL_DRVR_DELAY;
CLKA_2_YB_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glb_muxed_delay + OUT_DIV_DELAY + YBDELAY + Y_DRVR_DELAY;
CLKB_2_YB_bypass1_dly <= glb_muxed_delay + OUT_DIV_DELAY + YBDELAY + Y_DRVR_DELAY;
CLKA_2_GLC_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glc_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLCDELAY + GL_DRVR_DELAY;
CLKC_2_GLC_bypass0_dly <= BYP0_CLK_GL + GLCDELAY;
CLKC_2_GLC_bypass1_dly <= glc_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLCDELAY + GL_DRVR_DELAY;
CLKA_2_YC_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glc_muxed_delay + OUT_DIV_DELAY + YCDELAY + Y_DRVR_DELAY;
CLKC_2_YC_bypass1_dly <= glc_muxed_delay + OUT_DIV_DELAY + YCDELAY + Y_DRVR_DELAY;
CLKA_2_LOCK_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + LOCK_OUT_DELAY;
delay_LOCK: process( locked )
begin
if ( '1' = locked ) then
LOCK <= transport locked after CLKA_2_LOCK_dly;
else
LOCK <= locked;
end if;
end process delay_LOCK;
Deskew : process ( XDLYSEL_ipd )
variable DelayVal : Time := 0.000 ns;
begin
if (XDLYSEL_ipd = '1') then
DelayVal := EMULATED_SYSTEM_DELAY;
else
DelayVal := 0.0 ns;
end if;
DTDELAY <= DelayVal;
end process Deskew;
GetFBDelay : process ( FBDLY0_ipd, FBDLY1_ipd, FBDLY2_ipd, FBDLY3_ipd, FBDLY4_ipd )
variable step : integer;
begin
step := ulogic2int( FBDLY4_ipd & FBDLY3_ipd & FBDLY2_ipd & FBDLY1_ipd & FBDLY0_ipd );
FBDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end process GetFBDelay;
GetGLBDelay : process ( DLYGLB0_ipd, DLYGLB1_ipd, DLYGLB2_ipd, DLYGLB3_ipd, DLYGLB4_ipd )
variable step : integer;
begin
step := ulogic2int( DLYGLB4_ipd & DLYGLB3_ipd & DLYGLB2_ipd & DLYGLB1_ipd & DLYGLB0_ipd );
if ( step = 0 ) then
GLBDELAY <= 0.0 ns;
else
GLBDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end if;
end process GetGLBDelay;
GetYBDelay : process ( DLYYB0_ipd, DLYYB1_ipd, DLYYB2_ipd, DLYYB3_ipd, DLYYB4_ipd )
variable step : integer;
begin
step := ulogic2int( DLYYB4_ipd & DLYYB3_ipd & DLYYB2_ipd & DLYYB1_ipd & DLYYB0_ipd );
YBDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end process GetYBDelay;
GetGLCDelay : process ( DLYGLC0_ipd, DLYGLC1_ipd, DLYGLC2_ipd, DLYGLC3_ipd, DLYGLC4_ipd )
variable step : integer;
begin
step := ulogic2int( DLYGLC4_ipd & DLYGLC3_ipd & DLYGLC2_ipd & DLYGLC1_ipd & DLYGLC0_ipd );
if ( step = 0 ) then
GLCDELAY <= 0.0 ns;
else
GLCDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end if;
end process GetGLCDelay;
GetYCDelay : process ( DLYYC0_ipd, DLYYC1_ipd, DLYYC2_ipd, DLYYC3_ipd, DLYYC4_ipd )
variable step : integer;
begin
step := ulogic2int( DLYYC4_ipd & DLYYC3_ipd & DLYYC2_ipd & DLYYC1_ipd & DLYYC0_ipd );
YCDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end process GetYCDelay;
GetGLADelay : process ( DLYGLA0_ipd, DLYGLA1_ipd, DLYGLA2_ipd, DLYGLA3_ipd, DLYGLA4_ipd )
variable step : integer;
begin
step := ulogic2int( DLYGLA4_ipd & DLYGLA3_ipd & DLYGLA2_ipd & DLYGLA1_ipd & DLYGLA0_ipd );
if ( step = 0 ) then
GLADELAY <= 0.0 ns;
else
GLADELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end if;
end process GetGLADelay;
DIVM <= ulogic2int( FBDIV6_ipd & FBDIV5_ipd & FBDIV4_ipd & FBDIV3_ipd &
FBDIV2_ipd & FBDIV1_ipd & FBDIV0_ipd ) + 1;
DIVN <= ulogic2int( FINDIV6_ipd & FINDIV5_ipd & FINDIV4_ipd & FINDIV3_ipd &
FINDIV2_ipd & FINDIV1_ipd & FINDIV0_ipd ) + 1;
DIVU <= ulogic2int( OADIV4_ipd & OADIV3_ipd & OADIV2_ipd & OADIV1_ipd & OADIV0_ipd ) + 1;
DIVV <= ulogic2int( OBDIV4_ipd & OBDIV3_ipd & OBDIV2_ipd & OBDIV1_ipd & OBDIV0_ipd ) + 1;
DIVW <= ulogic2int( OCDIV4_ipd & OCDIV3_ipd & OCDIV2_ipd & OCDIV1_ipd & OCDIV0_ipd ) + 1;
check_OADIVHALF : process
begin
wait on OADIVHALF_ipd, DIVU, OAMUX_config;
if ( '1' = TO_X01( OADIVHALF_ipd ) ) then
if ( 1 /= OAMUX_config ) then
assert false
report "Illegal configuration. OADIVHALF can only be used when OAMUX = 001. OADIVHALF ignored."
severity warning;
halveA <= '0';
elsif ( ( DIVU < 3 ) or ( DIVU > 29 ) or ( ( DIVU mod 2 ) /= 1 ) ) then
assert false
report "Illegal configuration. Only even OADIV values from 2 to 28 (inclusive) are allowed with OADIVHALF."
severity warning;
halveA <= 'X';
else
halveA <= '1';
end if;
elsif ( OADIVHALF_ipd'event and ( 'X' = TO_X01( OADIVHALF_ipd ) ) ) then
assert false
report "OADIVHALF unknown."
severity warning;
halveA <= 'X';
else
halveA <= '0';
end if;
end process check_OADIVHALF;
check_OBDIVHALF : process
begin
wait on OBDIVHALF_ipd, DIVV, OBMUX_config;
if ( '1' = TO_X01( OBDIVHALF_ipd ) ) then
if ( 1 /= OBMUX_config ) then
assert false
report "Illegal configuration. OBDIVHALF can only be used when OBMUX = 001. OBDIVHALF ignored."
severity warning;
halveB <= '0';
elsif ( ( DIVV < 3 ) or ( DIVV > 29 ) or ( ( DIVV mod 2 ) /= 1 ) ) then
assert false
report "Illegal configuration. Only even OBDIV values from 2 to 28 (inclusive) are allowed with OBDIVHALF."
severity warning;
halveB <= 'X';
else
halveB <= '1';
end if;
elsif ( OBDIVHALF_ipd'event and ( 'X' = TO_X01( OBDIVHALF_ipd ) ) ) then
assert false
report "OBDIVHALF unknown."
severity warning;
halveB <= 'X';
else
halveB <= '0';
end if;
end process check_OBDIVHALF;
check_OCDIVHALF : process
begin
wait on OCDIVHALF_ipd, DIVW, OCMUX_config;
if ( '1' = TO_X01( OCDIVHALF_ipd ) ) then
if ( 1 /= OCMUX_config ) then
assert false
report "Illegal configuration. OCDIVHALF can only be used when OCMUX = 001. OCDIVHALF ignored."
severity warning;
halveC <= '0';
elsif ( ( DIVW < 3 ) or ( DIVW > 29 ) or ( ( DIVW mod 2 ) /= 1 ) ) then
assert false
report "Illegal configuration. Only even OCDIV values from 2 to 28 (inclusive) are allowed with OCDIVHALF."
severity warning;
halveC <= 'X';
else
halveC <= '1';
end if;
elsif ( OCDIVHALF_ipd'event and ( 'X' = TO_X01( OCDIVHALF_ipd ) ) ) then
assert false
report "OCDIVHALF unknown."
severity warning;
halveC <= 'X';
else
halveC <= '0';
end if;
end process check_OCDIVHALF;
gla_muxed_delay <= output_mux_delay( OAMUX_config, VCOSEL2_ipd, VCOSEL1_ipd, FBDELAY, PLLCLK_pw );
glb_muxed_delay <= output_mux_delay( OBMUX_config, VCOSEL2_ipd, VCOSEL1_ipd, FBDELAY, PLLCLK_pw );
glc_muxed_delay <= output_mux_delay( OCMUX_config, VCOSEL2_ipd, VCOSEL1_ipd, FBDELAY, PLLCLK_pw );
get_internal_fb_dly : process( FBSEL, FBDELAY, DTDELAY, fin_period )
variable fb_delay : time;
begin
fb_delay := IN_DIV_DELAY + X_MUX_DELAY + DTDELAY + FB_MUX_DELAY;
if ( "10" = FBSEL ) then
fb_delay := fb_delay + FBDELAY;
end if;
internal_fb_delay <= fb_delay;
end process get_internal_fb_dly;
external_fb_delay <= IN_DIV_DELAY + X_MUX_DELAY + DTDELAY + FB_MUX_DELAY + GL_DRVR_DELAY + GLADELAY + BYP_MUX_DELAY + OUT_DIV_DELAY + gla_muxed_delay + GLA_EXTFB_rise_dly;
normalize_fb_dly : process( using_EXTFB, internal_fb_delay, external_fb_delay, fin_period )
variable norm : time;
begin
if ( using_EXTFB = '1' ) then
norm := external_fb_delay;
else
norm := internal_fb_delay;
end if;
if ( 0 ns >= fin_period ) then
norm := 0 ns;
else
while ( norm > fin_period ) loop
norm := norm - fin_period;
end loop;
end if;
normalized_fb_delay <= norm;
end process normalize_fb_dly;
check_FBSEL : process
begin
wait on FBSEL, OAMUX_config, OBMUX_config, OCMUX_config, DIVM, DIVU, DIVN, CLKA_period_stable, PLLCLK_period, external_fb_delay;
if ( IS_X( FBSEL ) ) then
FBSEL_illegal <= true;
assert ( not FBSEL'event )
report "Warning: FBSEL is unknown."
severity Warning;
elsif ( "00" = FBSEL ) then -- Grounded.
FBSEL_illegal <= true;
assert ( not FBSEL'event )
report "Warning: Illegal FBSEL configuration 00."
severity Warning;
elsif ( "11" = FBSEL ) then -- External feedback
if ( 2 > OAMUX_config ) then
FBSEL_illegal <= true;
assert ( not ( FBSEL'event or OAMUX_config'event ) )
report "Illegal configuration. GLA cannot be in bypass mode (OAMUX = 000 or OAMUX = 001) when using external feedback (FBSEL = 11)."
severity Warning;
elsif ( DIVM < 5 ) then
FBSEL_illegal <= true;
assert ( not ( FBSEL'event or DIVM'event ) )
report "Error: FBDIV must be greater than 4 when using external feedback (FBSEL = 11)."
severity Error;
elsif ( ( DIVM * DIVU ) > 232 ) then
FBSEL_illegal <= true;
assert ( not ( FBSEL'event or DIVM'event or DIVU'event ) )
report "Error: Product of FBDIV and OADIV must be less than 233 when using external feedback (FBSEL = 11)."
severity Error;
elsif ( ( DIVN mod DIVU ) /= 0 ) then
FBSEL_illegal <= true;
assert ( not ( FBSEL'event or DIVN'event or DIVU'event ) )
report "Error: Division factor FINDIV must be a multiple of OADIV when using external feedback (FBSEL = 11)."
severity Error;
elsif ( CLKA_period_stable and EXTFB_delay_dtrmd and
( ( 1 < OBMUX_config ) or ( 1 < OCMUX_config ) ) and
( ( external_fb_delay >= CLKA_period ) or ( external_fb_delay >= PLLCLK_period ) ) ) then
FBSEL_illegal <= true;
assert ( not ( FBSEL'event or CLKA_period_stable'event or external_fb_delay'event or PLLCLK_period'event ) )
report "Error: Total sum of delays in the feedback path must be less than 1 VCO period AND less than 1 CLKA period when V and/or W dividers when using external feedback (FBSEL = 11)."
severity Error;
else
FBSEL_illegal <= false;
end if;
else
FBSEL_illegal <= false;
end if;
end process check_FBSEL;
-- Mimicing silicon - no need for a 50/50 duty cycle and this way fin only changes on rising edge of CLKA (except when DIVN is 1)
gen_fin: process
variable num_CLKA_re : integer;
begin
wait until rising_edge( CLKA_ipd );
fin <= '1';
num_CLKA_re := 0;
while ( 'X' /= TO_X01( CLKA_ipd ) ) loop
wait on CLKA_ipd;
if ( 1 = DIVN )then
fin <= CLKA_ipd;
elsif ( '1' = CLKA_ipd ) then
num_CLKA_re := num_CLKA_re + 1;
if ( ( num_CLKA_re mod DIVN ) = 0 ) then
fin <= '1';
num_CLKA_re := 0;
elsif ( ( num_CLKA_re mod DIVN ) = 1 ) then
fin <= '0';
end if;
end if;
end loop;
end process gen_fin;
GetCLKAPeriod : process ( CLKA_ipd, POWERDOWN_ipd, FBSEL_illegal, normalized_fb_delay, DIVN, DIVM, locked_vco0_edges, external_dly_correct )
-- locked_vco0_edges is in the sensitivity list so that we periodically check for CLKA stopped
variable re : Time := 0.000 ns; -- Current CLKA rising edge
variable CLKA_num_re_stable : Integer := -1; -- Number of CLKA rising edges that PLL config stable
begin
if (( TO_X01( POWERDOWN_ipd ) = '1' ) and ( FBSEL_illegal = False )) then
if ( normalized_fb_delay'event or DIVN'event or DIVM'event or
( ( '1' = using_EXTFB ) and ( '1' /= external_dly_correct ) ) ) then
internal_lock <= false;
CLKA_num_re_stable := -1;
end if;
if ( CLKA_ipd'event and ( '1' = TO_X01( CLKA_ipd ) ) ) then
if ( CLKA_period /= ( NOW - re ) ) then
CLKA_period <= ( NOW - re );
CLKA_num_re_stable := -1;
internal_lock <= false;
CLKA_period_stable <= false;
else
if ( f_CLKA_LOCK > CLKA_num_re_stable ) then
CLKA_num_re_stable := CLKA_num_re_stable + 1;
elsif ( f_CLKA_LOCK = CLKA_num_re_stable ) then
internal_lock <= true;
end if;
CLKA_period_stable <= true;
end if;
re := NOW;
elsif ( CLKA_period < ( NOW - re ) ) then
CLKA_num_re_stable := -1;
internal_lock <= false;
CLKA_period_stable <= false;
end if;
else
CLKA_num_re_stable := -1;
internal_lock <= false;
CLKA_period_stable <= false;
end if;
end process GetCLKAPeriod;
fin_period <= CLKA_period * DIVN;
GLA_pw <= PLLCLK_pw * DIVU;
extfbin_fin_drift <= ( GLA_pw * DIVM * 2.0 ) - fin_period;
PLLCLK_period <= fin_period / real( fb_loop_div );
PLLCLK_pw <= PLLCLK_period / 2.0;
calc_fb_loop_div : process( DIVM, DIVU, using_EXTFB )
begin
if ( using_EXTFB = '1' ) then
fb_loop_div <= DIVM * DIVU;
else
fb_loop_div <= DIVM;
end if;
end process calc_fb_loop_div;
sync_pll : process( fin, internal_lock, DYNSYNC )
begin
if ( not( internal_lock ) or ( '1' = DYNSYNC ) ) then
locked <= '0';
elsif ( rising_edge( fin ) ) then
locked <= '1';
end if;
end process sync_pll;
count_locked_vco0_edges: process( locked, locked_vco0_edges )
begin
if ( locked'event ) then
if ( locked = '1' ) then
locked_vco0_edges <= 0;
else
locked_vco0_edges <= -1;
end if;
elsif ( locked = '1' ) then
if ( ( locked_vco0_edges mod( DIVU * DIVV * DIVW * DIVM * 2 ) ) = 0 ) then
locked_vco0_edges <= 1 after PLLCLK_pw;
else
locked_vco0_edges <= ( locked_vco0_edges + 1 ) after PLLCLK_pw;
end if;
end if;
end process count_locked_vco0_edges;
gen_vco0_div: process( locked_vco0_edges )
begin
if ( locked_vco0_edges = -1 ) then
vco0_divu <= '0';
vco0_divv <= '0';
vco0_divw <= '0';
else
if ( ( locked_vco0_edges mod DIVU ) = 0 ) then
vco0_divu <= not vco0_divu;
end if;
if ( ( locked_vco0_edges mod DIVV ) = 0 ) then
vco0_divv <= not vco0_divv;
end if;
if ( ( locked_vco0_edges mod DIVW ) = 0 ) then
vco0_divw <= not vco0_divw;
end if;
end if;
end process gen_vco0_div;
UIN <= output_mux_driver( OAMUX_config, halveA, CLKA_ipd, CLKA2X, vco0_divu );
VIN <= output_mux_driver( OBMUX_config, halveB, CLKB_ipd, CLKB2X, vco0_divv );
WIN <= output_mux_driver( OCMUX_config, halveC, CLKC_ipd, CLKC2X, vco0_divw );
double_CLKA: process( CLKA_ipd )
variable re : Time := 0 ns;
variable prev_re : Time := 0 ns;
variable period : Time := 0 ns;
begin
if ( TO_X01( CLKA_ipd ) = '1' ) then
prev_re := re;
re := NOW;
period := re - prev_re;
if ( period > 0 ns ) then
CLKA2X <= '1';
CLKA2X <= transport '0' after ( period / 4.0 );
CLKA2X <= transport '1' after ( period / 2.0 );
CLKA2X <= transport '0' after ( period * 3.0 / 4.0 );
end if;
end if;
end process double_CLKA;
double_CLKB: process( CLKB_ipd )
variable re : Time := 0 ns;
variable prev_re : Time := 0 ns;
variable period : Time := 0 ns;
begin
if ( TO_X01( CLKB_ipd ) = '1' ) then
prev_re := re;
re := NOW;
period := re - prev_re;
if ( period > 0 ns ) then
CLKB2X <= '1';
CLKB2X <= transport '0' after ( period / 4.0 );
CLKB2X <= transport '1' after ( period / 2.0 );
CLKB2X <= transport '0' after ( period * 3.0 / 4.0 );
end if;
end if;
end process double_CLKB;
double_CLKC: process( CLKC_ipd )
variable re : Time := 0 ns;
variable prev_re : Time := 0 ns;
variable period : Time := 0 ns;
begin
if ( TO_X01( CLKC_ipd ) = '1' ) then
prev_re := re;
re := NOW;
period := re - prev_re;
if ( period > 0 ns ) then
CLKC2X <= '1';
CLKC2X <= transport '0' after ( period / 4.0 );
CLKC2X <= transport '1' after ( period / 2.0 );
CLKC2X <= transport '0' after ( period * 3.0 / 4.0 );
end if;
end if;
end process double_CLKC;
--
-- AOUT Output of Divider U
--
DividerU : process ( UIN, CLKA_ipd, OADIVRST_ipd, OADIVHALF_ipd,
POWERDOWN_ipd )
variable force_0 : Boolean := True;
variable num_edges : Integer := -1;
variable res_post_reset1 : Integer := 0;
variable fes_post_reset1 : Integer := 0;
variable res_post_reset0 : Integer := 0;
variable fes_post_reset0 : Integer := 0;
begin
if ( 1 = OAMUX_config ) then -- PLL core bypassed. OADIVRST active.
if ( CLKA_ipd'event ) then
if ( TO_X01( CLKA_ipd ) = '1' and TO_X01( CLKA_ipd'last_value ) = '0' ) then
if ( 4 > res_post_reset1 ) then
res_post_reset1 := res_post_reset1 + 1;
end if;
if ( 4 > res_post_reset0 ) then
res_post_reset0 := res_post_reset0 + 1;
end if;
if ( res_post_reset1 = 3 ) then
force_0 := False;
num_edges := -1;
end if;
elsif ( TO_X01( CLKA_ipd ) = '0' and TO_X01( CLKA_ipd'last_value ) = '1' ) then
if ( 4 > fes_post_reset1 ) then
fes_post_reset1 := fes_post_reset1 + 1;
end if;
if ( 4 > fes_post_reset0 ) then
fes_post_reset0 := fes_post_reset0 + 1;
end if;
if ( fes_post_reset1 = 1 ) then
force_0 := True;
end if;
end if;
end if;
if ( OADIVRST_ipd'event ) then
if ( TO_X01( OADIVRST_ipd ) = '1' ) then
if ( ( TO_X01( OADIVRST_ipd'last_value ) = '0' ) and
( ( res_post_reset0 < 1 ) or ( fes_post_reset0 < 1 ) ) ) then
assert false
report "OADIVRST must be held low for at least one CLKA period for the reset operation to work correctly: reset operation may not be successful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset1 := 0;
fes_post_reset1 := 0;
elsif ( TO_X01( OADIVRST_ipd ) = '0' ) then
if ( ( TO_X01( OADIVRST_ipd'last_value ) = '1' ) and
( ( res_post_reset1 < 3 ) or ( fes_post_reset1 < 3 ) ) ) then
assert false
report "OADIVRST must be held high for at least three CLKA periods for the reset operation to work correctly: reset operation may not be succesful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset0 := 0;
fes_post_reset0 := 0;
else
assert false
report "OADIVRST is unknown. Edge alignment unpredictable."
severity warning;
end if;
end if;
if ( UIN'event ) then
num_edges := num_edges + 1;
if ( force_0 ) then
AOUT <= '0';
elsif ( TO_X01( UIN ) = 'X' ) then
AOUT <= 'X';
elsif ( ( num_edges mod DIVU ) = 0 ) then
num_edges := 0;
if ( TO_X01 ( AOUT ) = 'X' ) then
AOUT <= UIN;
else
AOUT <= not AOUT;
end if;
end if;
end if;
else -- PLL not bypassed
if ( TO_X01 ( POWERDOWN_ipd ) = '0' ) then
AOUT <= '0';
elsif ( TO_X01 ( POWERDOWN_ipd ) = '1' ) then
AOUT <= UIN;
else -- POWERDOWN unknown
AOUT <= 'X';
end if;
end if;
end process DividerU;
--
-- BOUT Output of Divider V
--
DividerV : process ( VIN, CLKB_ipd, OBDIVRST_ipd, OBDIVHALF_ipd,
POWERDOWN_ipd )
variable force_0 : Boolean := True;
variable num_edges : Integer := -1;
variable res_post_reset1 : Integer := 0;
variable fes_post_reset1 : Integer := 0;
variable res_post_reset0 : Integer := 0;
variable fes_post_reset0 : Integer := 0;
begin
if ( 0 = OBMUX_config ) then
BOUT <= 'X';
elsif ( 1 = OBMUX_config ) then -- PLL core bypassed. OBDIVRST active.
if ( CLKB_ipd'event ) then
if ( TO_X01( CLKB_ipd ) = '1' and TO_X01( CLKB_ipd'last_value ) = '0' ) then
if ( 4 > res_post_reset1 ) then
res_post_reset1 := res_post_reset1 + 1;
end if;
if ( 4 > res_post_reset0 ) then
res_post_reset0 := res_post_reset0 + 1;
end if;
if ( res_post_reset1 = 3 ) then
force_0 := False;
num_edges := -1;
end if;
elsif ( TO_X01( CLKB_ipd ) = '0' and TO_X01( CLKB_ipd'last_value ) = '1' ) then
if ( 4 > fes_post_reset1 ) then
fes_post_reset1 := fes_post_reset1 + 1;
end if;
if ( 4 > fes_post_reset0 ) then
fes_post_reset0 := fes_post_reset0 + 1;
end if;
if ( fes_post_reset1 = 1 ) then
force_0 := True;
end if;
end if;
end if;
if ( OBDIVRST_ipd'event ) then
if ( TO_X01( OBDIVRST_ipd ) = '1' ) then
if ( ( TO_X01( OBDIVRST_ipd'last_value ) = '0' ) and
( ( res_post_reset0 < 1 ) or ( fes_post_reset0 < 1 ) ) ) then
assert false
report "OBDIVRST must be held low for at least one CLKB period for the reset operation to work correctly: reset operation may not be successful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset1 := 0;
fes_post_reset1 := 0;
elsif ( TO_X01( OBDIVRST_ipd ) = '0' ) then
if ( ( TO_X01( OBDIVRST_ipd'last_value ) = '1' ) and
( ( res_post_reset1 < 3 ) or ( fes_post_reset1 < 3 ) ) ) then
assert false
report "OBDIVRST must be held high for at least three CLKB periods for the reset operation to work correctly: reset operation may not be succesful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset0 := 0;
fes_post_reset0 := 0;
else
assert false
report "OBDIVRST is unknown. Edge alignment unpredictable."
severity warning;
end if;
end if;
if ( VIN'event ) then
num_edges := num_edges + 1;
if ( force_0 ) then
BOUT <= '0';
elsif ( TO_X01( VIN ) = 'X' ) then
BOUT <= 'X';
elsif ( ( num_edges mod DIVV ) = 0 ) then
num_edges := 0;
if ( TO_X01 ( BOUT ) = 'X' ) then
BOUT <= VIN;
else
BOUT <= not BOUT;
end if;
end if;
end if;
else -- PLL not bypassed
if ( TO_X01 ( POWERDOWN_ipd ) = '0' ) then
BOUT <= '0';
elsif ( TO_X01 ( POWERDOWN_ipd ) = '1' ) then
BOUT <= VIN;
else -- POWERDOWN unknown
BOUT <= 'X';
end if;
end if;
end process DividerV;
--
-- COUT Output of Divider W
--
DividerW : process ( WIN, CLKC_ipd, OCDIVRST_ipd, OCDIVHALF_ipd,
POWERDOWN_ipd )
variable force_0 : Boolean := True;
variable num_edges : Integer := -1;
variable res_post_reset1 : Integer := 0;
variable fes_post_reset1 : Integer := 0;
variable res_post_reset0 : Integer := 0;
variable fes_post_reset0 : Integer := 0;
begin
if ( 0 = OCMUX_config ) then
COUT <= 'X';
elsif ( 1 = OCMUX_config ) then -- PLL core bypassed. OCDIVRST active.
if ( CLKC_ipd'event ) then
if ( TO_X01( CLKC_ipd ) = '1' and TO_X01( CLKC_ipd'last_value ) = '0' ) then
if ( 4 > res_post_reset1 ) then
res_post_reset1 := res_post_reset1 + 1;
end if;
if ( 4 > res_post_reset0 ) then
res_post_reset0 := res_post_reset0 + 1;
end if;
if ( res_post_reset1 = 3 ) then
force_0 := False;
num_edges := -1;
end if;
elsif ( TO_X01( CLKC_ipd ) = '0' and TO_X01( CLKC_ipd'last_value ) = '1' ) then
if ( 4 > fes_post_reset1 ) then
fes_post_reset1 := fes_post_reset1 + 1;
end if;
if ( 4 > fes_post_reset0 ) then
fes_post_reset0 := fes_post_reset0 + 1;
end if;
if ( fes_post_reset1 = 1 ) then
force_0 := True;
end if;
end if;
end if;
if ( OCDIVRST_ipd'event ) then
if ( TO_X01( OCDIVRST_ipd ) = '1' ) then
if ( ( TO_X01( OCDIVRST_ipd'last_value ) = '0' ) and
( ( res_post_reset0 < 1 ) or ( fes_post_reset0 < 1 ) ) ) then
assert false
report "OCDIVRST must be held low for at least one CLKC period for the reset operation to work correctly: reset operation may not be successful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset1 := 0;
fes_post_reset1 := 0;
elsif ( TO_X01( OCDIVRST_ipd ) = '0' ) then
if ( ( TO_X01( OCDIVRST_ipd'last_value ) = '1' ) and
( ( res_post_reset1 < 3 ) or ( fes_post_reset1 < 3 ) ) ) then
assert false
report "OCDIVRST must be held high for at least three CLKC periods for the reset operation to work correctly: reset operation may not be succesful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset0 := 0;
fes_post_reset0 := 0;
else
assert false
report "OCDIVRST is unknown. Edge alignment unpredictable."
severity warning;
end if;
end if;
if ( WIN'event ) then
num_edges := num_edges + 1;
if ( force_0 ) then
COUT <= '0';
elsif ( TO_X01( WIN ) = 'X' ) then
COUT <= 'X';
elsif ( ( num_edges mod DIVW ) = 0 ) then
num_edges := 0;
if ( TO_X01 ( COUT ) = 'X' ) then
COUT <= WIN;
else
COUT <= not COUT;
end if;
end if;
end if;
else -- PLL not bypassed
if ( TO_X01 ( POWERDOWN_ipd ) = '0' ) then
COUT <= '0';
elsif ( TO_X01 ( POWERDOWN_ipd ) = '1' ) then
COUT <= WIN;
else -- POWERDOWN unknown
COUT <= 'X';
end if;
end if;
end process DividerW;
using_EXTFB <= TO_X01( FBSEL1_ipd and FBSEL0_ipd );
external_dly_correct <= expected_EXTFB xnor EXTFB_ipd after 1 ps;
get_EXTFB_period : process
variable previous_re : time := 0.000 ns; -- Previous EXTFB rising edge
begin
wait until rising_edge( EXTFB );
EXTFB_period <= NOW - previous_re;
previous_re := NOW;
end process get_EXTFB_period;
calculate_extfb_delay : process
variable CLKA_edge : time := 0 ns;
begin
EXTFB_delay_dtrmd <= false;
if ( ( '1' /= using_EXTFB ) or ( not CLKA_period_stable ) ) then
wait until ( ( '1' = using_EXTFB ) and CLKA_period_stable );
end if;
wait for GLA_EXTFB_rise_dly;
GLA_EXTFB_fall_dly <= 0 ps;
GLA_EXTFB_rise_dly <= 0 ps;
wait for ( CLKA_2_GLA_dly * 2);
calibrate_EXTFB_delay <= '1';
if ( '1' /= EXTFB_ipd ) then
wait until ( EXTFB_ipd = '1' );
end if;
wait until falling_edge( CLKA_ipd );
CLKA_edge := NOW;
calibrate_EXTFB_delay <= '0';
wait until falling_edge( EXTFB_ipd );
GLA_EXTFB_fall_dly <= NOW - CLKA_edge - CLKA_2_GLA_dly;
wait until rising_edge( CLKA_ipd );
CLKA_edge := NOW;
calibrate_EXTFB_delay <= '1';
wait until rising_edge( EXTFB_ipd );
GLA_EXTFB_rise_dly <= NOW - CLKA_edge - CLKA_2_GLA_dly;
wait until falling_edge( CLKA_ipd );
wait until ( CLKA_period_stable and rising_edge( fin ) );
EXTFB_delay_dtrmd <= true;
wait until falling_edge( expected_EXTFB );
if ( '1' /= external_dly_correct ) then
assert false
report "ERROR: EXTFB must be a simple, time-delayed derivative of GLA. Simulation cannot continue until user-logic is corrected"
severity failure;
wait;
end if;
wait until ( '1' /= external_dly_correct );
end process calculate_extfb_delay;
external_feedback : process
variable edges : integer := 1;
begin
wait on GLA_free_running, EXTFB_delay_dtrmd;
if ( EXTFB_delay_dtrmd ) then
if ( ( edges mod ( DIVM * 2 ) ) = 0 ) then
GLA_free_running <= not GLA_free_running after ( GLA_pw - extfbin_fin_drift );
edges := 0;
else
GLA_free_running <= not GLA_free_running after GLA_pw;
end if;
edges := edges + 1;
else
edges := 1;
GLA_free_running <= '1' after GLA_pw;
end if;
end process external_feedback;
gen_AOUT_using_EXTFB : process( AOUT, GLA_free_running, calibrate_EXTFB_delay, locked_vco0_edges, EXTFB_delay_dtrmd )
begin
if ( 0 <= locked_vco0_edges ) then
AOUT_using_EXTFB <= AOUT;
elsif ( EXTFB_delay_dtrmd ) then
AOUT_using_EXTFB <= GLA_free_running;
else
AOUT_using_EXTFB <= calibrate_EXTFB_delay;
end if;
end process gen_AOUT_using_EXTFB;
gen_expected_EXTFB: process( AOUT_using_EXTFB, EXTFB_delay_dtrmd )
begin
if ( not EXTFB_delay_dtrmd ) then
expected_EXTFB <= 'X';
elsif ( '1' = AOUT_using_EXTFB ) then
expected_EXTFB <= transport AOUT_using_EXTFB after ( CLKA_2_GLA_dly + GLA_EXTFB_rise_dly );
else
expected_EXTFB <= transport AOUT_using_EXTFB after ( CLKA_2_GLA_dly + GLA_EXTFB_fall_dly );
end if;
end process gen_expected_EXTFB;
Aoutputs: process( AOUT, CLKA_ipd, AOUT_using_EXTFB, OAMUX_config )
begin
if ( 0 = OAMUX_config ) then
GLA <= transport CLKA_ipd after CLKA_2_GLA_bypass0_dly;
elsif ( ( 1 = OAMUX_config ) or ( 3 = OAMUX_config ) ) then
GLA <= transport 'X' after CLKA_2_GLA_dly;
assert ( not OAMUX_config'event )
report "WARNING: Illegal OAMUX configuration."
severity warning;
elsif ( '1' = using_EXTFB ) then
GLA <= transport AOUT_using_EXTFB after CLKA_2_GLA_dly;
else
GLA <= transport AOUT after CLKA_2_GLA_dly;
end if;
end process Aoutputs;
Boutputs: process ( BOUT, CLKB_ipd, OBMUX_config )
begin
if ( 0 = OBMUX_config ) then
GLB <= transport CLKB_ipd after CLKB_2_GLB_bypass0_dly;
YB <= 'X';
elsif ( ( 1 = OBMUX_config ) or ( 3 = OBMUX_config ) ) then
GLB <= transport 'X' after CLKA_2_GLB_dly;
YB <= transport 'X' after CLKA_2_YB_dly;
assert ( not OBMUX_config'event )
report "WARNING: Illegal OBMUX configuration."
severity warning;
else
GLB <= transport BOUT after CLKA_2_GLB_dly;
YB <= transport BOUT after CLKA_2_YB_dly;
end if;
end process Boutputs;
Coutputs: process ( COUT, CLKC_ipd, OCMUX_config )
begin
if ( 0 = OCMUX_config ) then
GLC <= transport CLKC_ipd after CLKC_2_GLC_bypass0_dly;
YC <= 'X';
elsif ( ( 1 = OCMUX_config ) or ( 3 = OCMUX_config ) ) then
GLC <= transport 'X' after CLKA_2_GLC_dly;
YC <= transport 'X' after CLKA_2_YC_dly;
assert ( not OCMUX_config'event )
report "WARNING: Illegal OCMUX configuration."
severity warning;
else
GLC <= transport COUT after CLKA_2_GLC_dly;
YC <= transport COUT after CLKA_2_YC_dly;
end if;
end process Coutputs;
end VITAL_ACT;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity PLL is
generic(
VCOFREQUENCY : Real := 0.0;
f_CLKA_LOCK : Integer := 3; -- Number of CLKA pulses after which LOCK is raised
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
Xon : Boolean := False;
MsgOn : Boolean := True;
tipd_CLKA : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_EXTFB : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_POWERDOWN : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV5 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV6 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV5 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV6 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBSEL0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBSEL1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_XDLYSEL : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tpd_CLKA_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_LOCK : VitalDelayType01 := ( 0.100 ns, 0.100 ns )
);
port (
CLKA : in std_ulogic;
EXTFB : in std_ulogic;
POWERDOWN : in std_ulogic;
OADIV0 : in std_ulogic;
OADIV1 : in std_ulogic;
OADIV2 : in std_ulogic;
OADIV3 : in std_ulogic;
OADIV4 : in std_ulogic;
OAMUX0 : in std_ulogic;
OAMUX1 : in std_ulogic;
OAMUX2 : in std_ulogic;
DLYGLA0 : in std_ulogic;
DLYGLA1 : in std_ulogic;
DLYGLA2 : in std_ulogic;
DLYGLA3 : in std_ulogic;
DLYGLA4 : in std_ulogic;
OBDIV0 : in std_ulogic;
OBDIV1 : in std_ulogic;
OBDIV2 : in std_ulogic;
OBDIV3 : in std_ulogic;
OBDIV4 : in std_ulogic;
OBMUX0 : in std_ulogic;
OBMUX1 : in std_ulogic;
OBMUX2 : in std_ulogic;
DLYYB0 : in std_ulogic;
DLYYB1 : in std_ulogic;
DLYYB2 : in std_ulogic;
DLYYB3 : in std_ulogic;
DLYYB4 : in std_ulogic;
DLYGLB0 : in std_ulogic;
DLYGLB1 : in std_ulogic;
DLYGLB2 : in std_ulogic;
DLYGLB3 : in std_ulogic;
DLYGLB4 : in std_ulogic;
OCDIV0 : in std_ulogic;
OCDIV1 : in std_ulogic;
OCDIV2 : in std_ulogic;
OCDIV3 : in std_ulogic;
OCDIV4 : in std_ulogic;
OCMUX0 : in std_ulogic;
OCMUX1 : in std_ulogic;
OCMUX2 : in std_ulogic;
DLYYC0 : in std_ulogic;
DLYYC1 : in std_ulogic;
DLYYC2 : in std_ulogic;
DLYYC3 : in std_ulogic;
DLYYC4 : in std_ulogic;
DLYGLC0 : in std_ulogic;
DLYGLC1 : in std_ulogic;
DLYGLC2 : in std_ulogic;
DLYGLC3 : in std_ulogic;
DLYGLC4 : in std_ulogic;
FINDIV0 : in std_ulogic;
FINDIV1 : in std_ulogic;
FINDIV2 : in std_ulogic;
FINDIV3 : in std_ulogic;
FINDIV4 : in std_ulogic;
FINDIV5 : in std_ulogic;
FINDIV6 : in std_ulogic;
FBDIV0 : in std_ulogic;
FBDIV1 : in std_ulogic;
FBDIV2 : in std_ulogic;
FBDIV3 : in std_ulogic;
FBDIV4 : in std_ulogic;
FBDIV5 : in std_ulogic;
FBDIV6 : in std_ulogic;
FBDLY0 : in std_ulogic;
FBDlY1 : in std_ulogic;
FBDLY2 : in std_ulogic;
FBDLY3 : in std_ulogic;
FBDlY4 : in std_ulogic;
FBSEL0 : in std_ulogic;
FBSEL1 : in std_ulogic;
XDLYSEL : in std_ulogic;
VCOSEL0 : in std_ulogic;
VCOSEL1 : in std_ulogic;
VCOSEL2 : in std_ulogic;
GLA : out std_ulogic;
LOCK : out std_ulogic;
GLB : out std_ulogic;
YB : out std_ulogic;
GLC : out std_ulogic;
YC : out std_ulogic
);
attribute VITAL_LEVEL0 of PLL : entity is TRUE;
end PLL;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library proasic3;
use proasic3.components.all;
architecture VITAL_ACT of PLL is
attribute VITAL_LEVEL1 of VITAL_ACT : architecture is FALSE;
signal CLKA_ipd : std_ulogic;
signal EXTFB_ipd : std_ulogic;
signal POWERDOWN_ipd : std_ulogic;
signal OADIV0_ipd : std_ulogic;
signal OADIV1_ipd : std_ulogic;
signal OADIV2_ipd : std_ulogic;
signal OADIV3_ipd : std_ulogic;
signal OADIV4_ipd : std_ulogic;
signal OAMUX0_ipd : std_ulogic;
signal OAMUX1_ipd : std_ulogic;
signal OAMUX2_ipd : std_ulogic;
signal DLYGLA0_ipd : std_ulogic;
signal DLYGLA1_ipd : std_ulogic;
signal DLYGLA2_ipd : std_ulogic;
signal DLYGLA3_ipd : std_ulogic;
signal DLYGLA4_ipd : std_ulogic;
signal OBDIV0_ipd : std_ulogic;
signal OBDIV1_ipd : std_ulogic;
signal OBDIV2_ipd : std_ulogic;
signal OBDIV3_ipd : std_ulogic;
signal OBDIV4_ipd : std_ulogic;
signal OBMUX0_ipd : std_ulogic;
signal OBMUX1_ipd : std_ulogic;
signal OBMUX2_ipd : std_ulogic;
signal DLYYB0_ipd : std_ulogic;
signal DLYYB1_ipd : std_ulogic;
signal DLYYB2_ipd : std_ulogic;
signal DLYYB3_ipd : std_ulogic;
signal DLYYB4_ipd : std_ulogic;
signal DLYGLB0_ipd : std_ulogic;
signal DLYGLB1_ipd : std_ulogic;
signal DLYGLB2_ipd : std_ulogic;
signal DLYGLB3_ipd : std_ulogic;
signal DLYGLB4_ipd : std_ulogic;
signal OCDIV0_ipd : std_ulogic;
signal OCDIV1_ipd : std_ulogic;
signal OCDIV2_ipd : std_ulogic;
signal OCDIV3_ipd : std_ulogic;
signal OCDIV4_ipd : std_ulogic;
signal OCMUX0_ipd : std_ulogic;
signal OCMUX1_ipd : std_ulogic;
signal OCMUX2_ipd : std_ulogic;
signal DLYYC0_ipd : std_ulogic;
signal DLYYC1_ipd : std_ulogic;
signal DLYYC2_ipd : std_ulogic;
signal DLYYC3_ipd : std_ulogic;
signal DLYYC4_ipd : std_ulogic;
signal DLYGLC0_ipd : std_ulogic;
signal DLYGLC1_ipd : std_ulogic;
signal DLYGLC2_ipd : std_ulogic;
signal DLYGLC3_ipd : std_ulogic;
signal DLYGLC4_ipd : std_ulogic;
signal FINDIV0_ipd : std_ulogic;
signal FINDIV1_ipd : std_ulogic;
signal FINDIV2_ipd : std_ulogic;
signal FINDIV3_ipd : std_ulogic;
signal FINDIV4_ipd : std_ulogic;
signal FINDIV5_ipd : std_ulogic;
signal FINDIV6_ipd : std_ulogic;
signal FBDIV0_ipd : std_ulogic;
signal FBDIV1_ipd : std_ulogic;
signal FBDIV2_ipd : std_ulogic;
signal FBDIV3_ipd : std_ulogic;
signal FBDIV4_ipd : std_ulogic;
signal FBDIV5_ipd : std_ulogic;
signal FBDIV6_ipd : std_ulogic;
signal FBDLY0_ipd : std_ulogic;
signal FBDlY1_ipd : std_ulogic;
signal FBDLY2_ipd : std_ulogic;
signal FBDLY3_ipd : std_ulogic;
signal FBDlY4_ipd : std_ulogic;
signal FBSEL0_ipd : std_ulogic;
signal FBSEL1_ipd : std_ulogic;
signal XDLYSEL_ipd : std_ulogic;
signal VCOSEL0_ipd : std_ulogic;
signal VCOSEL1_ipd : std_ulogic;
signal VCOSEL2_ipd : std_ulogic;
signal GND : std_logic := '0';
signal UNUSED : std_logic := 'X';
component PLLPRIM
generic (
VCOFREQUENCY : Real;
f_CLKA_LOCK : Integer
);
port (
DYNSYNC : in std_ulogic;
CLKA : in std_ulogic;
EXTFB : in std_ulogic;
POWERDOWN : in std_ulogic;
CLKB : in std_ulogic;
CLKC : in std_ulogic;
OADIVRST : in std_ulogic;
OADIVHALF : in std_ulogic;
OADIV0 : in std_ulogic;
OADIV1 : in std_ulogic;
OADIV2 : in std_ulogic;
OADIV3 : in std_ulogic;
OADIV4 : in std_ulogic;
OAMUX0 : in std_ulogic;
OAMUX1 : in std_ulogic;
OAMUX2 : in std_ulogic;
DLYGLA0 : in std_ulogic;
DLYGLA1 : in std_ulogic;
DLYGLA2 : in std_ulogic;
DLYGLA3 : in std_ulogic;
DLYGLA4 : in std_ulogic;
OBDIVRST : in std_ulogic;
OBDIVHALF : in std_ulogic;
OBDIV0 : in std_ulogic;
OBDIV1 : in std_ulogic;
OBDIV2 : in std_ulogic;
OBDIV3 : in std_ulogic;
OBDIV4 : in std_ulogic;
OBMUX0 : in std_ulogic;
OBMUX1 : in std_ulogic;
OBMUX2 : in std_ulogic;
DLYYB0 : in std_ulogic;
DLYYB1 : in std_ulogic;
DLYYB2 : in std_ulogic;
DLYYB3 : in std_ulogic;
DLYYB4 : in std_ulogic;
DLYGLB0 : in std_ulogic;
DLYGLB1 : in std_ulogic;
DLYGLB2 : in std_ulogic;
DLYGLB3 : in std_ulogic;
DLYGLB4 : in std_ulogic;
OCDIVRST : in std_ulogic;
OCDIVHALF : in std_ulogic;
OCDIV0 : in std_ulogic;
OCDIV1 : in std_ulogic;
OCDIV2 : in std_ulogic;
OCDIV3 : in std_ulogic;
OCDIV4 : in std_ulogic;
OCMUX0 : in std_ulogic;
OCMUX1 : in std_ulogic;
OCMUX2 : in std_ulogic;
DLYYC0 : in std_ulogic;
DLYYC1 : in std_ulogic;
DLYYC2 : in std_ulogic;
DLYYC3 : in std_ulogic;
DLYYC4 : in std_ulogic;
DLYGLC0 : in std_ulogic;
DLYGLC1 : in std_ulogic;
DLYGLC2 : in std_ulogic;
DLYGLC3 : in std_ulogic;
DLYGLC4 : in std_ulogic;
FINDIV0 : in std_ulogic;
FINDIV1 : in std_ulogic;
FINDIV2 : in std_ulogic;
FINDIV3 : in std_ulogic;
FINDIV4 : in std_ulogic;
FINDIV5 : in std_ulogic;
FINDIV6 : in std_ulogic;
FBDIV0 : in std_ulogic;
FBDIV1 : in std_ulogic;
FBDIV2 : in std_ulogic;
FBDIV3 : in std_ulogic;
FBDIV4 : in std_ulogic;
FBDIV5 : in std_ulogic;
FBDIV6 : in std_ulogic;
FBDLY0 : in std_ulogic;
FBDlY1 : in std_ulogic;
FBDLY2 : in std_ulogic;
FBDLY3 : in std_ulogic;
FBDlY4 : in std_ulogic;
FBSEL0 : in std_ulogic;
FBSEL1 : in std_ulogic;
XDLYSEL : in std_ulogic;
VCOSEL0 : in std_ulogic;
VCOSEL1 : in std_ulogic;
VCOSEL2 : in std_ulogic;
GLA : out std_ulogic;
LOCK : out std_ulogic;
GLB : out std_ulogic;
YB : out std_ulogic;
GLC : out std_ulogic;
YC : out std_ulogic
);
end component;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay ( CLKA_ipd, CLKA, tipd_CLKA );
VitalWireDelay ( EXTFB_ipd, EXTFB, tipd_EXTFB );
VitalWireDelay ( POWERDOWN_ipd, POWERDOWN, tipd_POWERDOWN );
VitalWireDelay ( OADIV0_ipd, OADIV0, tipd_OADIV0 );
VitalWireDelay ( OADIV1_ipd, OADIV1, tipd_OADIV1 );
VitalWireDelay ( OADIV2_ipd, OADIV2, tipd_OADIV2 );
VitalWireDelay ( OADIV3_ipd, OADIV3, tipd_OADIV3 );
VitalWireDelay ( OADIV4_ipd, OADIV4, tipd_OADIV4 );
VitalWireDelay ( OAMUX0_ipd, OAMUX0, tipd_OAMUX0 );
VitalWireDelay ( OAMUX1_ipd, OAMUX1, tipd_OAMUX1 );
VitalWireDelay ( OAMUX2_ipd, OAMUX2, tipd_OAMUX2 );
VitalWireDelay ( DLYGLA0_ipd, DLYGLA0, tipd_DLYGLA0 );
VitalWireDelay ( DLYGLA1_ipd, DLYGLA1, tipd_DLYGLA1 );
VitalWireDelay ( DLYGLA2_ipd, DLYGLA2, tipd_DLYGLA2 );
VitalWireDelay ( DLYGLA3_ipd, DLYGLA3, tipd_DLYGLA3 );
VitalWireDelay ( DLYGLA4_ipd, DLYGLA4, tipd_DLYGLA4 );
VitalWireDelay ( OBDIV0_ipd, OBDIV0, tipd_OBDIV0 );
VitalWireDelay ( OBDIV1_ipd, OBDIV1, tipd_OBDIV1 );
VitalWireDelay ( OBDIV2_ipd, OBDIV2, tipd_OBDIV2 );
VitalWireDelay ( OBDIV3_ipd, OBDIV3, tipd_OBDIV3 );
VitalWireDelay ( OBDIV4_ipd, OBDIV4, tipd_OBDIV4 );
VitalWireDelay ( OBMUX0_ipd, OBMUX0, tipd_OBMUX0 );
VitalWireDelay ( OBMUX1_ipd, OBMUX1, tipd_OBMUX1 );
VitalWireDelay ( OBMUX2_ipd, OBMUX2, tipd_OBMUX2 );
VitalWireDelay ( DLYYB0_ipd, DLYYB0, tipd_DLYYB0 );
VitalWireDelay ( DLYYB1_ipd, DLYYB1, tipd_DLYYB1 );
VitalWireDelay ( DLYYB2_ipd, DLYYB2, tipd_DLYYB2 );
VitalWireDelay ( DLYYB3_ipd, DLYYB3, tipd_DLYYB3 );
VitalWireDelay ( DLYYB4_ipd, DLYYB4, tipd_DLYYB4 );
VitalWireDelay ( DLYGLB0_ipd, DLYGLB0, tipd_DLYGLB0 );
VitalWireDelay ( DLYGLB1_ipd, DLYGLB1, tipd_DLYGLB1 );
VitalWireDelay ( DLYGLB2_ipd, DLYGLB2, tipd_DLYGLB2 );
VitalWireDelay ( DLYGLB3_ipd, DLYGLB3, tipd_DLYGLB3 );
VitalWireDelay ( DLYGLB4_ipd, DLYGLB4, tipd_DLYGLB4 );
VitalWireDelay ( OCDIV0_ipd, OCDIV0, tipd_OCDIV0 );
VitalWireDelay ( OCDIV1_ipd, OCDIV1, tipd_OCDIV1 );
VitalWireDelay ( OCDIV2_ipd, OCDIV2, tipd_OCDIV2 );
VitalWireDelay ( OCDIV3_ipd, OCDIV3, tipd_OCDIV3 );
VitalWireDelay ( OCDIV4_ipd, OCDIV4, tipd_OCDIV4 );
VitalWireDelay ( OCMUX0_ipd, OCMUX0, tipd_OCMUX0 );
VitalWireDelay ( OCMUX1_ipd, OCMUX1, tipd_OCMUX1 );
VitalWireDelay ( OCMUX2_ipd, OCMUX2, tipd_OCMUX2 );
VitalWireDelay ( DLYYC0_ipd, DLYYC0, tipd_DLYYC0 );
VitalWireDelay ( DLYYC1_ipd, DLYYC1, tipd_DLYYC1 );
VitalWireDelay ( DLYYC2_ipd, DLYYC2, tipd_DLYYC2 );
VitalWireDelay ( DLYYC3_ipd, DLYYC3, tipd_DLYYC3 );
VitalWireDelay ( DLYYC4_ipd, DLYYC4, tipd_DLYYC4 );
VitalWireDelay ( DLYGLC0_ipd, DLYGLC0, tipd_DLYGLC0 );
VitalWireDelay ( DLYGLC1_ipd, DLYGLC1, tipd_DLYGLC1 );
VitalWireDelay ( DLYGLC2_ipd, DLYGLC2, tipd_DLYGLC2 );
VitalWireDelay ( DLYGLC3_ipd, DLYGLC3, tipd_DLYGLC3 );
VitalWireDelay ( DLYGLC4_ipd, DLYGLC4, tipd_DLYGLC4 );
VitalWireDelay ( FINDIV0_ipd, FINDIV0, tipd_FINDIV0 );
VitalWireDelay ( FINDIV1_ipd, FINDIV1, tipd_FINDIV1 );
VitalWireDelay ( FINDIV2_ipd, FINDIV2, tipd_FINDIV2 );
VitalWireDelay ( FINDIV3_ipd, FINDIV3, tipd_FINDIV3 );
VitalWireDelay ( FINDIV4_ipd, FINDIV4, tipd_FINDIV4 );
VitalWireDelay ( FINDIV5_ipd, FINDIV5, tipd_FINDIV5 );
VitalWireDelay ( FINDIV6_ipd, FINDIV6, tipd_FINDIV6 );
VitalWireDelay ( FBDIV0_ipd, FBDIV0, tipd_FBDIV0 );
VitalWireDelay ( FBDIV1_ipd, FBDIV1, tipd_FBDIV1 );
VitalWireDelay ( FBDIV2_ipd, FBDIV2, tipd_FBDIV2 );
VitalWireDelay ( FBDIV3_ipd, FBDIV3, tipd_FBDIV3 );
VitalWireDelay ( FBDIV4_ipd, FBDIV4, tipd_FBDIV4 );
VitalWireDelay ( FBDIV5_ipd, FBDIV5, tipd_FBDIV5 );
VitalWireDelay ( FBDIV6_ipd, FBDIV6, tipd_FBDIV6 );
VitalWireDelay ( FBDLY0_ipd, FBDLY0, tipd_FBDLY0 );
VitalWireDelay ( FBDLY1_ipd, FBDLY1, tipd_FBDLY1 );
VitalWireDelay ( FBDLY2_ipd, FBDLY2, tipd_FBDLY2 );
VitalWireDelay ( FBDLY3_ipd, FBDLY3, tipd_FBDLY3 );
VitalWireDelay ( FBDLY4_ipd, FBDLY4, tipd_FBDLY4 );
VitalWireDelay ( FBSEL0_ipd, FBSEL0, tipd_FBSEL0 );
VitalWireDelay ( FBSEL1_ipd, FBSEL1, tipd_FBSEL1 );
VitalWireDelay ( XDLYSEL_ipd, XDLYSEL, tipd_XDLYSEL );
VitalWireDelay ( VCOSEL0_ipd, VCOSEL0, tipd_VCOSEL0 );
VitalWireDelay ( VCOSEL1_ipd, VCOSEL1, tipd_VCOSEL1 );
VitalWireDelay ( VCOSEL2_ipd, VCOSEL2, tipd_VCOSEL2 );
end block WireDelay;
P1: PLLPRIM
generic map (
VCOFREQUENCY => VCOFREQUENCY,
f_CLKA_LOCK => f_CLKA_LOCK
)
port map (
DYNSYNC => GND,
CLKA => CLKA_ipd,
EXTFB => EXTFB_ipd,
POWERDOWN => POWERDOWN_ipd,
CLKB => UNUSED,
CLKC => UNUSED,
OADIVRST => GND,
OADIVHALF => GND,
OADIV0 => OADIV0_ipd,
OADIV1 => OADIV1_ipd,
OADIV2 => OADIV2_ipd,
OADIV3 => OADIV3_ipd,
OADIV4 => OADIV4_ipd,
OAMUX0 => OAMUX0_ipd,
OAMUX1 => OAMUX1_ipd,
OAMUX2 => OAMUX2_ipd,
DLYGLA0 => DLYGLA0_ipd,
DLYGLA1 => DLYGLA1_ipd,
DLYGLA2 => DLYGLA2_ipd,
DLYGLA3 => DLYGLA3_ipd,
DLYGLA4 => DLYGLA4_ipd,
OBDIVRST => GND,
OBDIVHALF => GND,
OBDIV0 => OBDIV0_ipd,
OBDIV1 => OBDIV1_ipd,
OBDIV2 => OBDIV2_ipd,
OBDIV3 => OBDIV3_ipd,
OBDIV4 => OBDIV4_ipd,
OBMUX0 => OBMUX0_ipd,
OBMUX1 => OBMUX1_ipd,
OBMUX2 => OBMUX2_ipd,
DLYYB0 => DLYYB0_ipd,
DLYYB1 => DLYYB1_ipd,
DLYYB2 => DLYYB2_ipd,
DLYYB3 => DLYYB3_ipd,
DLYYB4 => DLYYB4_ipd,
DLYGLB0 => DLYGLB0_ipd,
DLYGLB1 => DLYGLB1_ipd,
DLYGLB2 => DLYGLB2_ipd,
DLYGLB3 => DLYGLB3_ipd,
DLYGLB4 => DLYGLB4_ipd,
OCDIVRST => GND,
OCDIVHALF => GND,
OCDIV0 => OCDIV0_ipd,
OCDIV1 => OCDIV1_ipd,
OCDIV2 => OCDIV2_ipd,
OCDIV3 => OCDIV3_ipd,
OCDIV4 => OCDIV4_ipd,
OCMUX0 => OCMUX0_ipd,
OCMUX1 => OCMUX1_ipd,
OCMUX2 => OCMUX2_ipd,
DLYYC0 => DLYYC0_ipd,
DLYYC1 => DLYYC1_ipd,
DLYYC2 => DLYYC2_ipd,
DLYYC3 => DLYYC3_ipd,
DLYYC4 => DLYYC4_ipd,
DLYGLC0 => DLYGLC0_ipd,
DLYGLC1 => DLYGLC1_ipd,
DLYGLC2 => DLYGLC2_ipd,
DLYGLC3 => DLYGLC3_ipd,
DLYGLC4 => DLYGLC4_ipd,
FINDIV0 => FINDIV0_ipd,
FINDIV1 => FINDIV1_ipd,
FINDIV2 => FINDIV2_ipd,
FINDIV3 => FINDIV3_ipd,
FINDIV4 => FINDIV4_ipd,
FINDIV5 => FINDIV5_ipd,
FINDIV6 => FINDIV6_ipd,
FBDIV0 => FBDIV0_ipd,
FBDIV1 => FBDIV1_ipd,
FBDIV2 => FBDIV2_ipd,
FBDIV3 => FBDIV3_ipd,
FBDIV4 => FBDIV4_ipd,
FBDIV5 => FBDIV5_ipd,
FBDIV6 => FBDIV6_ipd,
FBDLY0 => FBDLY0_ipd,
FBDlY1 => FBDlY1_ipd,
FBDLY2 => FBDLY2_ipd,
FBDLY3 => FBDLY3_ipd,
FBDlY4 => FBDlY4_ipd,
FBSEL0 => FBSEL0_ipd,
FBSEL1 => FBSEL1_ipd,
XDLYSEL => XDLYSEL_ipd,
VCOSEL0 => VCOSEL0_ipd,
VCOSEL1 => VCOSEL1_ipd,
VCOSEL2 => VCOSEL2_ipd,
GLA => GLA,
LOCK => LOCK,
GLB => GLB,
YB => YB,
GLC => GLC,
YC => YC
);
end VITAL_ACT;
library IEEE;
use IEEE.std_logic_1164.all;
entity UJTAG is
port(
UTDO : in STD_ULOGIC;
TMS : in STD_ULOGIC;
TDI : in STD_ULOGIC;
TCK : in STD_ULOGIC;
TRSTB : in STD_ULOGIC;
UIREG0 : out STD_ULOGIC;
UIREG1 : out STD_ULOGIC;
UIREG2 : out STD_ULOGIC;
UIREG3 : out STD_ULOGIC;
UIREG4 : out STD_ULOGIC;
UIREG5 : out STD_ULOGIC;
UIREG6 : out STD_ULOGIC;
UIREG7 : out STD_ULOGIC;
UTDI : out STD_ULOGIC;
URSTB : out STD_ULOGIC;
UDRCK : out STD_ULOGIC;
UDRCAP : out STD_ULOGIC;
UDRSH : out STD_ULOGIC;
UDRUPD : out STD_ULOGIC;
TDO : out STD_ULOGIC);
end;
library IEEE;
use IEEE.std_logic_1164.all;
architecture behav of UJTAG is
begin
UIREG0 <= '0';
UIREG1 <= '0';
UIREG2 <= '0';
UIREG3 <= '0';
UIREG4 <= '0';
UIREG5 <= '0';
UIREG6 <= '0';
UIREG7 <= '0';
UTDI <= '0';
URSTB <= '0';
UDRCK <= '0';
UDRCAP <= '0';
UDRSH <= '0';
UDRUPD <= '0';
TDO <= '0';
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mmutw.vhd | 2 | 8278 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutw
-- File: mmutw.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU table-walk logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmutw is
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end mmutw;
architecture rtl of mmutw is
type write_buffer_type is record -- write buffer
addr, data : std_logic_vector(31 downto 0);
read : std_logic;
end record;
type states is (idle, waitm, pte, lv1, lv2, lv3, lv4);
type tw_rtype is record
state : states;
wb : write_buffer_type;
req : std_logic;
walk_op : std_logic;
--#dump
-- pragma translate_off
finish : std_logic;
index : std_logic_vector(31-2 downto 0);
lvl : std_logic_vector(1 downto 0);
fault_mexc : std_logic;
fault_trans : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
pte,ptd,inv,rvd : std_logic;
goon, found : std_logic;
base : std_logic_vector(31 downto 0);
-- pragma translate_on
end record;
signal c,r : tw_rtype;
begin
p0: process (rst, r, c, twi, mcmmo, mmctrl1)
variable v : tw_rtype;
variable finish : std_logic;
variable index : std_logic_vector(31-2 downto 0);
variable lvl : std_logic_vector(1 downto 0);
variable fault_mexc : std_logic;
variable fault_trans : std_logic;
variable fault_inv : std_logic;
variable fault_lvl : std_logic_vector(1 downto 0);
variable pte,ptd,inv,rvd : std_logic;
variable goon, found : std_logic;
variable base : std_logic_vector(31 downto 0);
begin
v := r;
--#init
finish := '0';
index := (others => '0');
lvl := (others => '0');
fault_mexc := '0';
fault_trans := '0';
fault_inv := '0';
fault_lvl := (others => '0');
pte := '0';ptd := '0';inv := '0';rvd := '0';
goon := '0'; found := '0';
base := (others => '0');
base(PADDR_PTD_U downto PADDR_PTD_D) := mcmmo.data(PTD_PTP32_U downto PTD_PTP32_D);
if mcmmo.grant = '1' then
v.req := '0';
end if;
if mcmmo.retry = '1' then v.req := '1'; end if;
-- # pte/ptd
if ((mcmmo.ready and not r.req)= '1') then -- context
case mcmmo.data(PT_ET_U downto PT_ET_D) is
when ET_INV => inv := '1';
when ET_PTD => ptd := '1'; goon := '1';
when ET_PTE => pte := '1'; found := '1';
when ET_RVD => rvd := '1'; null;
when others => null;
end case;
end if;
fault_trans := (rvd);
fault_inv := inv;
-- # state machine
case r.state is
when idle =>
if (twi.walk_op_ur) = '1' then
v.walk_op := '1';
index(M_CTX_SZ-1 downto 0) := mmctrl1.ctx;
base := (others => '0');
base(PADDR_PTD_U downto PADDR_PTD_D) := mmctrl1.ctxp(MMCTRL_PTP32_U downto MMCTRL_PTP32_D);
v.wb.addr := base or (index&"00");
v.wb.read := '1';
v.req := '1';
v.state := lv1;
elsif (twi.areq_ur) = '1' then
index := (others => '0');
v.wb.addr := twi.aaddr;
v.wb.data := twi.adata;
v.wb.read := '0';
v.req := '1';
v.state := waitm;
end if;
when waitm =>
if ((mcmmo.ready and not r.req)= '1') then -- amba: result ready current cycle
fault_mexc := mcmmo.mexc;
v.state := idle;
finish := '1';
end if;
when lv1 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_CTX; fault_lvl := FS_L_CTX;
index(VA_I1_SZ-1 downto 0) := twi.data(VA_I1_U downto VA_I1_D);
v.state := lv2;
end if;
when lv2 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_REGION; fault_lvl := FS_L_L1;
index(VA_I2_SZ-1 downto 0) := twi.data(VA_I2_U downto VA_I2_D);
v.state := lv3;
end if;
when lv3 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_SEGMENT; fault_lvl := FS_L_L2;
index(VA_I3_SZ-1 downto 0) := twi.data(VA_I3_U downto VA_I3_D);
v.state := lv4;
end if;
when lv4 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_PAGE; fault_lvl := FS_L_L3;
fault_trans := fault_trans or ptd;
v.state := idle;
finish := '1';
end if;
when others =>
v.state := idle;
finish := '0';
end case;
base := base or (index&"00");
if r.walk_op = '1' then
if (mcmmo.ready and (not r.req)) = '1' then
fault_mexc := mcmmo.mexc;
if (( ptd and
(not fault_mexc ) and
(not fault_trans) and
(not fault_inv )) = '1') then -- tw : break table walk?
v.wb.addr := base;
v.req := '1';
else
v.walk_op := '0';
finish := '1';
v.state := idle;
end if;
end if;
end if;
-- # reset
if ( rst = '0' ) then
v.state := idle;
v.req := '0';
v.walk_op := '0';
v.wb.read := '0';
end if;
--# drive signals
two.finish <= finish;
two.data <= mcmmo.data;
two.addr <= r.wb.addr(31 downto 0);
two.lvl <= lvl;
two.fault_mexc <= fault_mexc;
two.fault_trans <= fault_trans;
two.fault_inv <= fault_inv;
two.fault_lvl <= fault_lvl;
mcmmi.address <= r.wb.addr;
mcmmi.data <= r.wb.data;
mcmmi.burst <= '0';
mcmmi.size <= "10";
mcmmi.read <= r.wb.read;
mcmmi.lock <= '0';
mcmmi.req <= r.req;
--#dump
-- pragma translate_off
v.finish := finish;
v.index := index;
v.lvl := lvl;
v.fault_mexc := fault_mexc;
v.fault_trans := fault_trans;
v.fault_lvl := fault_lvl;
v.pte := pte;
v.ptd := ptd;
v.inv := inv;
v.rvd := rvd;
v.goon := goon;
v.found := found;
v.base := base;
-- pragma translate_on
c <= v;
end process p0;
p1: process (clk)
begin if rising_edge(clk) then r <= c; end if;
end process p1;
end rtl;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/leon3/grfpwxsh.vhd | 2 | 9517 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwxsh
-- File: grfpwxsh.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity grfpwxsh is
generic (tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end;
architecture rtl of grfpwxsh is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
component grfpwsh
generic (tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0);
start : out std_logic;
nonstd : out std_logic;
flop : out std_logic_vector(8 downto 0);
op1 : out std_logic_vector(63 downto 0);
op2 : out std_logic_vector(63 downto 0);
opid : out std_logic_vector(7 downto 0);
flush : out std_logic;
flushid : out std_logic_vector(5 downto 0);
rndmode : out std_logic_vector(1 downto 0);
req : out std_logic;
res : in std_logic_vector(63 downto 0);
exc : in std_logic_vector(5 downto 0);
allow : in std_logic_vector(2 downto 0);
rdy : in std_logic;
cc : in std_logic_vector(1 downto 0);
idout : in std_logic_vector(7 downto 0)
);
end component;
begin
x0 : grfpwsh generic map (tech, pclow, dsu, disas, id)
port map (rst,
clk,
holdn,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2 ,
fpui.start ,
fpui.nonstd ,
fpui.flop ,
fpui.op1 ,
fpui.op2 ,
fpui.opid ,
fpui.flush ,
fpui.flushid ,
fpui.rndmode ,
fpui.req ,
fpuo.res ,
fpuo.exc ,
fpuo.allow ,
fpuo.rdy ,
fpuo.cc ,
fpuo.idout
);
rf1 : regfile_3p generic map (tech, 4, 32, 1, 16)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr, rfi1.ren1, rfo1.data1,
rfi1.rd2addr, rfi1.ren2, rfo1.data2);
rf2 : regfile_3p generic map (tech, 4, 32, 1, 16)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr, rfi2.ren1, rfo2.data1,
rfi2.rd2addr, rfi2.ren2, rfo2.data2);
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/work/debug/grtestmod.vhd | 1 | 4683 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
use std.textio.all;
entity grtestmod is
generic (halt : integer := 0);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : in std_ulogic;
address : in std_logic_vector(21 downto 2);
data : inout std_logic_vector(31 downto 0);
iosn : in std_ulogic;
oen : in std_ulogic;
writen : in std_ulogic;
brdyn : out std_ulogic := '1'
);
end;
architecture sim of grtestmod is
subtype msgtype is string(1 to 40);
constant ntests : integer := 2;
type msgarr is array (0 to ntests) of msgtype;
constant msg : msgarr := (
"*** Starting GRLIB system test *** ", -- 0
"Test completed OK, halting simulation ", -- 1
"Test FAILED " -- 2
);
signal ior, iow : std_ulogic;
begin
ior <= iosn or oen;
iow <= iosn or writen;
data <= (others => 'Z');
log : process(ior, iow, clk)
variable errno, errcnt, subtest, vendorid, deviceid : integer;
variable addr : std_logic_vector(21 downto 2);
variable ldata : std_logic_vector(31 downto 0);
begin
if rising_edge(clk) then
addr := to_X01(address);
ldata := to_X01(data);
end if;
if falling_edge (ior) then
brdyn <= '1', '0' after 100 ns;
elsif rising_edge (ior) then
brdyn <= '1';
elsif falling_edge(iow) then
brdyn <= '1', '0' after 100 ns;
elsif rising_edge(iow) then
brdyn <= '1';
-- addr := to_X01(address);
case addr(7 downto 2) is
when "000000" =>
vendorid := conv_integer(ldata(31 downto 24));
deviceid := conv_integer(ldata(23 downto 12));
print(iptable(vendorid).device_table(deviceid));
when "000001" =>
errno := conv_integer(ldata(15 downto 0));
if (halt = 0) then
assert false
report "test failed, error (" & tost(errno) & ")"
severity failure;
else
assert false
report "test failed, error (" & tost(errno) & ")"
severity warning;
end if;
when "000010" =>
subtest := conv_integer(ldata(7 downto 0));
if vendorid = VENDOR_GAISLER then
case deviceid is
when GAISLER_LEON3 => leon3_subtest(subtest);
when GAISLER_FTMCTRL => mctrl_subtest(subtest);
when GAISLER_GPTIMER => gptimer_subtest(subtest);
when GAISLER_LEON3DSU => dsu3_subtest(subtest);
when GAISLER_SPW => spw_subtest(subtest);
when GAISLER_SPICTRL => spictrl_subtest(subtest);
when GAISLER_I2CMST => i2cmst_subtest(subtest);
when GAISLER_UHCI => uhc_subtest(subtest);
when GAISLER_EHCI => ehc_subtest(subtest);
when others =>
print (" subtest " & tost(subtest));
end case;
elsif vendorid = VENDOR_ESA then
case deviceid is
when ESA_LEON2 => leon3_subtest(subtest);
when ESA_MCTRL => mctrl_subtest(subtest);
when ESA_TIMER => gptimer_subtest(subtest);
when others =>
print ("subtest " & tost(subtest));
end case;
else
print ("subtest " & tost(subtest));
end if;
when "000100" =>
print ("");
print ("**** GRLIB system test starting ****");
errcnt := 0;
when "000101" =>
if errcnt = 0 then
print ("Test passed, halting with IU error mode");
elsif errcnt = 1 then
print ("1 error detected, halting with IU error mode");
else
print (tost(errcnt) & " errors detected, halting with IU error mode");
end if;
print ("");
when others =>
end case;
end if;
end process;
end;
-- pragma translate_on
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/esa/memoryctrl/memoryctrl.vhd | 2 | 2150 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
------------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.memctrl.all;
package memoryctrl is
component mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/eth/wrapper/greth_gen.vhd | 2 | 10341 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gen
-- File: greth_gen.vhd
-- Author: Marko Isomaki
-- Description: Generic Ethernet MAC
------------------------------------------------------------------------------
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library eth;
use eth.ethcomp.all;
entity greth_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 31 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic
);
end entity;
architecture rtl of greth_gen is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl = 1) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => rmii_clk,
tx_clk => tx_clk,
rx_clk => rx_clk,
rxd => rxd(3 downto 0),
rx_dv => rx_dv,
rx_er => rx_er,
rx_col => rx_col,
rx_crs => rx_crs,
mdio_i => mdio_i,
phyrstaddr => phyrstaddr,
--ethernet output signals
reset => reset,
txd => txd(3 downto 0),
tx_en => tx_en,
tx_er => tx_er,
mdc => mdc,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
--scantest
testrst => testrst,
testen => testen);
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclram : if (edcl = 1) generate
rloopm : for i in 0 to 1 generate
r0 : syncram_2p generic map (memtech, eabits, 8) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(i*8+23 downto i*8+16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(i*8+23 downto i*8+16));
end generate;
rloopl : for i in 0 to 1 generate
r0 : syncram_2p generic map (memtech, eabits, 8) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(i*8+7 downto i*8), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(i*8+7 downto i*8));
end generate;
end generate;
end architecture;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/techmap/maps/clkpad.vhd | 2 | 3185 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkpad
-- File: clkpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity clkpad is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; arch : integer := 0;
hf : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1');
end;
architecture rtl of clkpad is
begin
gen0 : if has_pads(tech) = 0 generate
o <= to_X01(pad);
end generate;
xcv : if (tech = virtex) generate
u0 : virtex_clkpad generic map (level, voltage, 0, 0) port map (pad, o, rstn);
end generate;
xcv2 : if (tech = virtex2) or (tech = spartan3) or (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate
u0 : virtex_clkpad generic map (level, voltage, arch, hf) port map (pad, o, rstn);
end generate;
axc : if (tech = axcel) generate
u0 : axcel_clkpad generic map (level, voltage) port map (pad, o);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
u0 : apa3_clkpad generic map (level, voltage) port map (pad, o);
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_clkpad generic map (level, voltage) port map (pad, o);
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_clkpad generic map (level, voltage) port map (pad, o);
end generate;
um : if (tech = umc) generate
u0 : umc_inpad generic map (level, voltage) port map (pad, o);
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_inpad generic map (level, voltage) port map (pad, o);
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_clkpad generic map (level, voltage) port map (pad, o);
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad port map (pad, o);
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_inpad port map (pad, o);
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_inpad port map (pad, o);
end generate;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcitb_master.vhd | 2 | 11031 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_master
-- File: pcitb_master.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI Master emulator. Can act as a system host
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.pcitb.all;
use gaisler.pcilib.all;
use gaisler.ambatest.all;
library grlib;
use grlib.stdlib.xorv;
entity pcitb_master is
generic (
slot : integer := 0;
tval : time := 7 ns;
dbglevel : integer := 1);
port (
-- PCI signals
pciin : in pci_type;
pciout : out pci_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end pcitb_master;
architecture tb of pcitb_master is
constant T_O : integer := 9;
type filedata_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
command : std_logic_vector(3 downto 0);
last : std_logic;
openrfile : std_logic;
openwfile : std_logic;
end record;
type state_type is(idle,active,done);
type reg_type is record
state : state_type;
pcien : std_logic_vector(3 downto 0);
paren : std_logic;
read : std_logic;
burst : std_logic;
grant : std_logic;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
current_word : natural;
tocnt : integer;
running : std_logic;
pci : pci_type;
status : status_type;
end record;
signal r,rin : reg_type;
signal filedata : filedata_type;
begin
comb : process(pciin)
variable vpci : pci_type;
variable v : reg_type;
variable i,count,dataintrans : integer;
variable status : status_type;
variable ready,stop : std_logic;
variable comm : std_logic_vector(3 downto 0);
begin
v := r; count := count+1; v.tocnt := 0; ready := '0'; stop := '0';
v.pcien(0) := '1'; v.pcien(3 downto 1) := r.pcien(2 downto 0);
if tbi.start = '1' then
if (r.running = '0' and r.state = idle) then
v.address := tbi.address(31 downto 2) & "00";
status := OK;
v.running := '1';
end if;
case tbi.command is
when M_READ => v.burst := '0'; v.read := '1'; comm := MEM_READ;
when M_READ_MULT => v.burst := '1'; v.read := '1'; comm := MEM_R_MULT;
when M_READ_LINE => v.burst := '1'; v.read := '1'; comm := MEM_R_LINE;
when M_WRITE =>
if tbi.no_words = 1 then v.burst := '0'; else v.burst := '1'; end if;
v.read := '0'; comm := MEM_WRITE;
when M_WRITE_INV => v.burst := '1'; v.read := '0'; comm := MEM_W_INV;
when C_READ => v.burst := '0'; v.read := '1'; comm := CONF_READ;
when C_WRITE => v.burst := '0'; v.read := '0'; comm := CONF_WRITE;
when others =>
end case;
if not tbi.userfile then v.pci.ad.ad := tbi.data; end if;
end if;
if tbi.userfile then
v.address := (filedata.address(31 downto 2) + conv_std_logic_vector(v.current_word,30)) & "00";
comm := filedata.command;
v.pci.ad.ad := filedata.data;
v.burst := not filedata.last;
stop := filedata.last;
end if;
v.pci.ad.par := xorv(r.pci.ad.ad & r.pci.ad.cbe);
v.paren := r.read;
if (pciin.ifc.devsel and not pciin.ifc.stop) = '1' and r.running = '1' then
status := ERR;
elsif r.tocnt = T_O then
status := TIMEOUT;
else
status := OK;
end if;
case r.state is
when idle =>
v.pci.arb.req(slot) := not (r.running and r.pcien(1));
v.pci.ifc.irdy := '1'; dataintrans := 0;
if r.grant = '1' then
v.state := active; v.pci.ifc.frame := '0'; v.read := '0';
v.pcien(0) := '0'; v.pci.ad.ad := v.address; v.pci.ad.cbe := comm;
end if;
when active =>
v.tocnt := r.tocnt + 1; v.pcien(0) := '0';
v.pci.ifc.irdy := '0';
v.pci.ad.cbe := (others => '0');
v.pci.arb.req(slot) := not (r.burst and not pciin.ifc.frame);
if (pciin.ifc.irdy or (pciin.ifc.trdy and pciin.ifc.stop)) = '0' then
if pciin.ifc.trdy = '0' then
v.current_word := r.current_word+1; v.data := pciin.ad.ad;
dataintrans := dataintrans+1;
end if;
end if;
if pciin.ifc.devsel = '0' then v.tocnt := 0; end if;
if ((v.current_word+conv_integer(r.burst)) >= tbi.no_words and tbi.userfile = false) then
stop := '1';
if pciin.ifc.frame = '1' then
if pciin.ifc.trdy = '0' then
v.running := '0'; v.pci.ifc.irdy := '1'; v.pcien(0) := '1';
elsif (pciin.ifc.trdy and not pciin.ifc.stop) = '1' then
v.state := idle; v.pci.ifc.irdy := '1'; v.pcien(0) := '1';
if dataintrans > 0 then
v.address := (tbi.address(31 downto 2) + conv_std_logic_vector(v.current_word,30)) & "00";
end if;
end if;
end if;
elsif pciin.ifc.stop = '0' then
v.pcien(0) := pciin.ifc.frame; stop := '1'; v.state := idle; v.pci.ifc.irdy := pciin.ifc.frame;
if not tbi.userfile then v.address := (tbi.address(31 downto 2) + conv_std_logic_vector(v.current_word,30)) & "00"; end if;
end if;
-- if (status /= OK or (r.running = '0' and ((pciin.ifc.irdy or not (pciin.ifc.trdy and pciin.ifc.stop)) = '1' or tbi.userfile = true))) then
if (r.status /= OK or ((pciin.ifc.frame and not pciin.ifc.irdy and not pciin.ifc.trdy) = '1')) then
v.state := done; v.pci.ifc.irdy := '1'; v.pcien(0) := '1'; v.pci.arb.req(slot) := '1';
end if;
v.pci.ifc.frame := not (r.burst and not stop);
when done =>
v.running := '0'; ready := '1';
if tbi.start = '0' then
v.state := idle;
v.current_word := 0;
end if;
when others =>
end case;
v.grant := to_x01(pciin.ifc.frame) and to_x01(pciin.ifc.irdy) and not r.pci.arb.req(slot) and not to_x01(pciin.arb.gnt(slot));
if pciin.syst.rst = '0' then
v.pcien := (others => '1');
v.state := idle;
v.read := '0';
v.burst := '0';
v.grant := '0';
v.address := (others => '0');
v.data := (others => '0');
v.current_word := 0;
v.running := '0';
v.pci := pci_idle;
end if;
tbo.ready <= ready;
v.status := status;
tbo.status <= status;
tbo.data <= r.data;
rin <= v;
end process;
clockreg : process(pciin.syst)
file readfile,writefile : text;
variable L : line;
variable datahex : string(1 to 8);
variable count : integer;
begin
if pciin.syst.rst = '0' then
filedata.address <= (others => '0');
filedata.data <= (others => '0');
filedata.command <= (others => '0');
filedata.last <= '0';
filedata.openrfile <= '0';
filedata.openwfile <= '0';
elsif rising_edge(pciin.syst.clk) then
-- r <= rin;
if tbi.usewfile then
case r.state is
when idle =>
if (tbi.start and not filedata.openwfile) = '1' then
file_open(writefile, external_name => tbi.wfile(18 downto trimlen(tbi.wfile)), open_kind => write_mode);
filedata.openwfile <= '1';
count := 0;
end if;
when active =>
if (pciin.ifc.trdy or pciin.ifc.irdy) = '0' then
if (tbi.userfile = false or count > 0) then
write(L,printhex(pciin.ad.ad,32));
writeline(writefile,L);
end if;
count := count+1;
end if;
if rin.state = done then
file_close(writefile);
filedata.openwfile <= '0';
end if;
when others =>
end case;
end if;
if tbi.userfile then
case r.state is
when idle =>
if (tbi.start and not filedata.openrfile) = '1' then
filedata.last <= '0'; filedata.openrfile <= '1';
file_open(readfile,external_name => tbi.rfile(18 downto trimlen(tbi.rfile)), open_kind => read_mode);
readline(readfile,L); -- Dummy read for header
readline(readfile,L); read(L,datahex);
filedata.address <= conv_std_logic_vector(datahex,32);
readline(readfile,L); read(L,datahex);
filedata.command <= conv_std_logic_vector(datahex,4);
readline(readfile,L); -- Dummy read for header
readline(readfile,L); read(L,datahex);
filedata.data <= conv_std_logic_vector(datahex,32);
end if;
when active =>
if (pciin.ifc.trdy or pciin.ifc.irdy) = '0' then
if not endfile(readfile) then
readline(readfile,L); read(L,datahex);
filedata.data <= conv_std_logic_vector(datahex,32);
r.pci.ad.ad <= conv_std_logic_vector(datahex,32);
end if;
if endfile(readfile) then filedata.last <= '1'; r.pci.ifc.frame <= '1'; r.running <= '0'; end if;
end if;
when done =>
if tbi.start = '0' then
file_close(readfile); filedata.openrfile <= '0';
end if;
when others =>
end case;
end if;
end if;
if rising_edge(pciin.syst.clk) then
r <= rin;
end if;
end process;
pciout.ad.ad <= r.pci.ad.ad after tval when (r.read or r.pcien(0)) = '0' else (others => 'Z') after tval;
pciout.ad.cbe <= r.pci.ad.cbe after tval when r.pcien(0) = '0' else (others => 'Z') after tval;
pciout.ad.par <= r.pci.ad.par after tval when (r.paren or r.pcien(1)) = '0' else 'Z' after tval;
pciout.ifc.frame <= r.pci.ifc.frame after tval when r.pcien(0) = '0' else 'Z' after tval;
pciout.ifc.irdy <= r.pci.ifc.irdy after tval when r.pcien(1) = '0' else 'Z' after tval;
pciout.err.perr <= r.pci.err.perr after tval when r.pcien(2) = '0' else 'Z' after tval;
pciout.err.serr <= r.pci.err.serr after tval when r.pcien(2) = '0' else 'Z' after tval;
pciout.arb.req(slot) <= r.pci.arb.req(slot) after tval;
end;
-- pragma translate_on
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/apa/memory_apa.vhd | 2 | 6545 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_apa_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Actel Proasic rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library apa;
use apa.RAM256x9SST;
-- pragma translate_on
entity proasic_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of proasic_syncram_2p is
component RAM256x9SST port(
DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 : out std_logic;
WPE, RPE, DOS : out std_logic;
WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_logic;
RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_logic;
WCLKS, RCLKS : in std_logic;
DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0 : in std_logic;
WRB, RDB, WBLKB, RBLKB, PARODD, DIS : in std_logic);
end component;
type powarr is array (1 to 19) of integer;
constant ntbl : powarr := (1, 1, 1, 1, 1, 1, 1, 1, 2, 4, 8, 16, 32, others => 64);
constant dw : integer := dbits + 8;
subtype dword is std_logic_vector(dw downto 0);
type qarr is array (0 to 63) of dword;
signal gnd, wen, ren : std_ulogic;
signal q : qarr;
signal d : dword;
signal rra : std_logic_vector (20 downto 0);
signal ra, wa : std_logic_vector (63 downto 0);
signal wenv : std_logic_vector (63 downto 0);
signal renv : std_logic_vector (63 downto 0);
begin
gnd <= '0';
wa(63 downto abits) <= (others => '0'); wa(abits-1 downto 0) <= waddr;
ra(63 downto abits) <= (others => '0'); ra(abits-1 downto 0) <= raddr;
d(dw downto dbits) <= (others => '0'); d(dbits-1 downto 0) <= din;
wen <= not write; ren <= not rena;
x0 : if abits < 15 generate
b0 : for j in 0 to ntbl(abits)-1 generate
g0 : for i in 0 to (dbits-1)/9 generate
u0 : RAM256x9SST port map (
DO0 => q(j)(i*9+0), DO1 => q(j)(i*9+1), DO2 => q(j)(i*9+2),
DO3 => q(j)(i*9+3), DO4 => q(j)(i*9+4), DO5 => q(j)(i*9+5),
DO6 => q(j)(i*9+6), DO7 => q(j)(i*9+7), DO8 => q(j)(i*9+8),
DOS => open, RPE => open, WPE => open,
WADDR0 => wa(0), WADDR1 => wa(1), WADDR2 => wa(2),
WADDR3 => wa(3), WADDR4 => wa(4), WADDR5 => wa(5),
WADDR6 => wa(6), WADDR7 => wa(7),
RADDR0 => ra(0), RADDR1 => ra(1), RADDR2 => ra(2),
RADDR3 => ra(3), RADDR4 => ra(4), RADDR5 => ra(5),
RADDR6 => ra(6), RADDR7 => ra(7),
WCLKS => wclk, RCLKS => rclk,
DI0 => d(i*9+0), DI1 => d(i*9+1), DI2 => d(i*9+2),
DI3 => d(i*9+3), DI4 => d(i*9+4), DI5 => d(i*9+5),
DI6 => d(i*9+6), DI7 => d(i*9+7), DI8 => d(i*9+8),
RDB => ren, WRB => wen, RBLKB => renv(j), WBLKB => wenv(j),
PARODD => gnd, DIS => gnd
);
end generate;
end generate;
rra(20 downto abits) <= (others => '0');
reg : process(rclk)
begin
if rising_edge(rclk) then
rra(abits-1 downto 0) <= raddr(abits-1 downto 0);
rra(7 downto 0) <= (others => '0');
end if;
end process;
ctrl : process(write, waddr, q, rra, rena, raddr)
variable we,z,re : std_logic_vector(63 downto 0);
variable wea,rea : std_logic_vector(63 downto 0);
begin
we := (others => '0'); z := (others => '0'); re := (others => '0');
wea := (others => '0'); rea := (others => '0');
wea(abits-1 downto 0) := waddr(abits-1 downto 0); wea(7 downto 0) := (others => '0');
rea(abits-1 downto 0) := raddr(abits-1 downto 0); wea(7 downto 0) := (others => '0');
z(dbits-1 downto 0) :=
q(conv_integer(rra(19 downto 8)))(dbits-1 downto 0);
we (conv_integer(wea(19 downto 8))) := write;
re (conv_integer(rea(19 downto 8))) := rena;
wenv <= not we; renv <= not re; dout <= z(dbits-1 downto 0);
end process;
end generate;
-- pragma translate_off
unsup : if abits > 14 generate
x : process
begin
assert false
report "Address depth larger than 14 not supported for ProAsic rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
entity proasic_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of proasic_syncram is
component proasic_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
begin
u0 : proasic_syncram_2p generic map (abits, dbits)
port map (clk, enable, address, dataout, clk, address, datain, write);
end;
| mit |
franz/pocl | examples/accel/rtl/vhdl/rf_1wr_1rd_always_1_guarded_0.vhd | 2 | 6851 | -- Copyright (c) 2002-2009 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-- Title : File for TTA
-- Project : FlexDSP
-------------------------------------------------------------------------------
--
-- VHDL Entity of Guarded_RF.rf_1wr_1rd_always_1.symbol
--
-- Created: 13:42:41 02/14/06
-- by - tpitkane.tpitkane (elros)
-- at - 13:42:41 02/14/06
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2004.1 (Build 41)
---------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 02/14/06 1.0 tpitkane Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--LIBRARY work;
--USE work.util.all;
use work.util.all;
ENTITY rf_1wr_1rd_always_1_guarded_0 IS
GENERIC(
dataw : integer := 32;
rf_size : integer := 8
);
PORT(
clk : IN std_logic;
glock : IN std_logic;
r1load : IN std_logic;
r1opcode : IN std_logic_vector ( bit_width(rf_size)-1 DOWNTO 0 );
rstx : IN std_logic;
t1data : IN std_logic_vector (dataw-1 DOWNTO 0);
t1load : IN std_logic;
t1opcode : IN std_logic_vector ( bit_width(rf_size)-1 DOWNTO 0 );
r1data : OUT std_logic_vector (dataw-1 DOWNTO 0);
guard : OUT std_logic_vector (rf_size-1 DOWNTO 0)
);
-- Declarations
END rf_1wr_1rd_always_1_guarded_0 ;
---------------------------------------------------------------------------------
-- Title : File for TTA
-- Project : FlexDSP
-------------------------------------------------------------------------------
--
-- VHDL Architecture Guarded_RF.rf_1wr_1rd_always_1.rtl
--
-- Created: 13:42:41 02/14/06
-- by - tpitkane.tpitkane (elros)
-- at - 13:42:41 02/14/06
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2004.1 (Build 41)
---------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 02/14/06 1.0 tpitkane Created
---------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE rtl OF rf_1wr_1rd_always_1_guarded_0 IS
-- Architecture declarations
type reg_type is array (natural range <>) of std_logic_vector(dataw-1 downto 0 );
subtype rf_index is integer range 0 to rf_size-1;
signal reg : reg_type (rf_size-1 downto 0);
--signal temp : std_logic_vector(0 downto 0);
BEGIN
-----------------------------------------------------------------
input : PROCESS (clk, rstx)
-----------------------------------------------------------------
-- Process declarations
variable opc : integer;
variable idx : integer;
BEGIN
-- Asynchronous Reset
IF (rstx = '0') THEN
-- Reset Actions
idx := rf_size-1;
for idx in rf_size-1 downto 0 loop
reg(idx) <= (others => '0');
end loop; -- idx
ELSIF (clk'EVENT AND clk = '1') THEN
IF glock = '0' THEN
IF t1load = '1' THEN
opc := conv_integer(unsigned(t1opcode));
reg(opc) <= t1data;
END IF;
END IF;
END IF;
END PROCESS input;
-----------------------------------------------------------------
--output : PROCESS (glock, r1load, r1opcode, reg, rstx)
-----------------------------------------------------------------
r1data <= reg(conv_integer(unsigned(r1opcode)));
-----------------------------------------------------------------
guard_out : PROCESS (reg,t1load,t1opcode,t1data)
-----------------------------------------------------------------
-- Process declarations
variable guard_var : std_logic_vector(0 downto 0);
BEGIN
for i in rf_size-1 downto 0 loop
if dataw > 1 then
if t1load = '1' then
if i = conv_integer(unsigned(t1opcode)) then
guard_var :=
t1data(dataw-1 downto dataw-1)
or t1data(dataw-2 downto dataw-2);
for j in dataw-2 downto 0 loop
guard_var := t1data(j downto j)
or guard_var;
end loop;
else
guard_var :=
reg(i)(dataw-1 downto dataw-1)
or reg(i)(dataw-2 downto dataw-2);
for j in dataw-2 downto 0 loop
guard_var := reg(i)(j downto j)
or guard_var;
end loop;
end if;
else
guard_var :=
reg(i)(dataw-1 downto dataw-1)
or reg(i)(dataw-2 downto dataw-2);
for j in dataw-2 downto 0 loop
guard_var := reg(i)(j downto j)
or guard_var;
end loop;
end if;
-- temp <= reg(i)(1 downto 1)
-- or reg(i)(0 downto 0);
else
if t1load = '1' then
if i = conv_integer(unsigned(t1opcode)) then
guard_var(0 downto 0) := t1data(0 downto 0);
else
guard_var(0 downto 0) := reg(i)(0 downto 0);
end if;
else
guard_var(0 downto 0) := reg(i)(0 downto 0);
end if;
end if;
--temp <= reg(i)(1 downto 1)
-- or reg(i)(0 downto 0);
guard(i downto i) <= guard_var(0 downto 0);
end loop;
END PROCESS guard_out;
END rtl;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/tech/axcelerator/components/axcelerator.vhd | 2 | 34835 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM64K36 is
-- pragma translate_off
generic (MEMORYFILE:string := "");
-- pragma translate_on
port(
DEPTH3, DEPTH2, DEPTH1, DEPTH0,
WRAD15, WRAD14, WRAD13, WRAD12, WRAD11, WRAD10, WRAD9 ,
WRAD8 , WRAD7 , WRAD6 , WRAD5 , WRAD4 , WRAD3 , WRAD2 ,
WRAD1 , WRAD0 , WD35 , WD34 , WD33 , WD32 , WD31 ,
WD30 , WD29 , WD28 , WD27 , WD26 , WD25 , WD24 ,
WD23 , WD22 , WD21 , WD20 , WD19 , WD18 , WD17 ,
WD16 , WD15 , WD14 , WD13 , WD12 , WD11 , WD10 ,
WD9 , WD8 , WD7 , WD6 , WD5 , WD4 , WD3 ,
WD2 , WD1 , WD0 , WW2 , WW1 , WW0 , WEN ,
WCLK , RDAD15, RDAD14, RDAD13, RDAD12, RDAD11, RDAD10,
RDAD9 , RDAD8 , RDAD7 , RDAD6 , RDAD5 , RDAD4 , RDAD3 ,
RDAD2 , RDAD1 , RDAD0 , RW2 , RW1 , RW0 , REN ,
RCLK : in std_ulogic ;
RD35 , RD34 , RD33 , RD32 , RD31 , RD30 , RD29 ,
RD28 , RD27 , RD26 , RD25 , RD24 , RD23 , RD22 ,
RD21 , RD20 , RD19 , RD18 , RD17 , RD16 , RD15 ,
RD14 , RD13 , RD12 , RD11 , RD10 , RD9 , RD8 ,
RD7 , RD6 , RD5 , RD4 , RD3 , RD2 , RD1 ,
RD0 : out std_ulogic);
end;
architecture rtl of RAM64K36 is
signal re : std_ulogic;
begin
rp : process(RCLK, WCLK)
constant words : integer := 2**16;
subtype word is std_logic_vector(35 downto 0);
type dregtype is array (0 to words - 1) of word;
variable rfd : dregtype;
variable wa, ra : std_logic_vector(15 downto 0);
variable q : std_logic_vector(35 downto 0);
begin
if rising_edge(RCLK) then
ra := RDAD15 & RDAD14 & RDAD13 & RDAD12 & RDAD11 & RDAD10 & RDAD9 &
RDAD8 & RDAD7 & RDAD6 & RDAD5 & RDAD4 & RDAD3 & RDAD2 & RDAD1 & RDAD0;
if not (is_x (ra)) and REN = '1' then
q := rfd(to_integer(unsigned(ra)) mod words);
else q := (others => 'X'); end if;
end if;
if rising_edge(WCLK) and (wen = '1') then
wa := WRAD15 & WRAD14 & WRAD13 & WRAD12 & WRAD11 & WRAD10 & WRAD9 &
WRAD8 & WRAD7 & WRAD6 & WRAD5 & WRAD4 & WRAD3 & WRAD2 & WRAD1 & WRAD0;
if not is_x (wa) then
rfd(to_integer(unsigned(wa)) mod words) :=
WD35 & WD34 & WD33 & WD32 & WD31 & WD30 & WD29 & WD28 & WD27 &
WD26 & WD25 & WD24 & WD23 & WD22 & WD21 & WD20 & WD19 & WD18 &
WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 & WD10 & WD9 &
WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 & WD1 & WD0;
end if;
if ra = wa then q := (others => 'X'); end if; -- no write-through
end if;
RD35 <= q(35); RD34 <= q(34); RD33 <= q(33); RD32 <= q(32); RD31 <= q(31);
RD30 <= q(30); RD29 <= q(29); RD28 <= q(28); RD27 <= q(27); RD26 <= q(26);
RD25 <= q(25); RD24 <= q(24); RD23 <= q(23); RD22 <= q(22); RD21 <= q(21);
RD20 <= q(20); RD19 <= q(19); RD18 <= q(18); RD17 <= q(17); RD16 <= q(16);
RD15 <= q(15); RD14 <= q(14); RD13 <= q(13); RD12 <= q(12); RD11 <= q(11);
RD10 <= q(10); RD9 <= q(9); RD8 <= q(8); RD7 <= q(7); RD6 <= q(6);
RD5 <= q(5); RD4 <= q(4); RD3 <= q(3); RD2 <= q(2); RD1 <= q(1);
RD0 <= q(0);
end process;
end;
-- PCI PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf_pci is begin y <= to_X01(pad) after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf_pci is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf_pci is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff_pci is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff_pci is begin
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_pci is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_pci is begin pad <= d after 5 ns; end;
-- STANDARD PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in_u is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in_u is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in_u is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in_u is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_bi is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of iopad_bi is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_tri is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopad_tri is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_tri_u is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopad_tri_u is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadp_tri is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopadp_tri is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadp_in is port (n2pin, pad : in std_logic; y : out std_logic ); end;
architecture struct of iopadp_in is begin
y <= pad after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadn_in is port ( pad : in std_logic; n2pout : out std_logic ); end;
architecture struct of iopadn_in is begin
n2pout <= pad after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadn_tri is port (db, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopadn_tri is begin
pad <= not db after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_8 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_8 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_12 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_12 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_16 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_16 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_24 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_24 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_lvds is port( y : out std_logic; padp, padn : in std_logic); end;
architecture struct of inbuf_lvds is
signal yn : std_ulogic := '0';
begin
yn <= to_X01(padp) after 1 ns when to_x01(padp xor padn) = '1' else yn after 1 ns;
y <= yn;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_lvds is port (d : in std_logic; padp, padn : out std_logic ); end;
architecture struct of outbuf_lvds is begin
padp <= d after 1 ns;
padn <= not d after 1 ns;
end;
-- clock buffers ----------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of hclkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of clkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity IOFIFO_BIBUF is
port( AIN : in std_logic;
AOUT : in std_logic;
YIN : out std_logic;
YOUT : out std_logic
);
end ;
architecture struct of IOFIFO_BIBUF is begin
YIN <= to_X01(AIN);
YOUT <= to_X01(AOUT);
end;
library ieee;
use ieee.std_logic_1164.all;
entity add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end add1;
architecture beh of add1 is
signal un1_fco : std_logic;
signal un2_fco : std_logic;
signal un3_fco : std_logic;
begin
s <= a xor b xor fci;
un1_fco <= a and b;
un2_fco <= a and fci;
un3_fco <= b and fci;
fco <= un1_fco or un2_fco or un3_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2;
architecture beh of and2 is
begin
y <= b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2a;
architecture beh of and2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2b;
architecture beh of and2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3;
architecture beh of and3 is
begin
y <= c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3a;
architecture beh of and3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3b;
architecture beh of and3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3c;
architecture beh of and3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4;
architecture beh of and4 is
begin
y <= d and c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4a;
architecture beh of and4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d and c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4b;
architecture beh of and4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d and c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4c;
architecture beh of and4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d and ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity buff is
port(
a : in std_logic;
y : out std_logic);
end buff;
architecture beh of buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ioi_buff is
port(
a : in std_logic;
y : out std_logic);
end ioi_buff;
architecture beh of ioi_buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_buff is
port(
a : in std_logic;
y : out std_logic);
end iooe_buff;
architecture beh of iooe_buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iofifo_outbuf is
port(
a : in std_logic;
y : out std_logic);
end iofifo_outbuf;
architecture beh of iofifo_outbuf is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8buff is
port(
a : in std_logic;
y : out std_logic);
end cm8buff;
architecture beh of cm8buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity hclkmux is
port(
a : in std_logic;
y : out std_logic);
end hclkmux;
architecture beh of hclkmux is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity rclkmux is
port(
a : in std_logic;
y : out std_logic);
end rclkmux;
architecture beh of rclkmux is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity IOFIFO_INBUF is
port(
a : in std_logic;
y : out std_logic);
end IOFIFO_INBUF;
architecture beh of IOFIFO_INBUF is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity CLKINT_W is
port(
a : in std_logic;
y : out std_logic);
end CLKINT_W;
architecture beh of CLKINT_W is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity fcend_buff is
port(
fci : in std_logic;
co : out std_logic);
end fcend_buff;
architecture beh of fcend_buff is
begin
co <= fci;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity fcinit_buff is
port(
a : in std_logic;
fco : out std_logic);
end fcinit_buff;
architecture beh of fcinit_buff is
begin
fco <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end cm8;
architecture beh of cm8 is
signal s0 : std_logic;
signal s1 : std_logic;
signal m0 : std_logic;
signal m1 : std_logic;
begin
s0 <= s01 and s00;
s1 <= s11 or s10;
m0 <= d0 when s0 = '0' else d1;
m1 <= d2 when s0 = '0' else d3;
y <= m0 when s1 = '0' else m1;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8inv is
port(
a : in std_logic;
y : out std_logic);
end cm8inv;
architecture beh of cm8inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end df1;
architecture beh of df1 is
begin
ff : process (clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity df1b is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end df1b;
architecture beh of df1b is
begin
ff : process (clk)
begin
if falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1b;
architecture beh of dfc1b is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1c;
architecture beh of dfc1c is
begin
ff : process (clk, clr)
begin
if clr = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= not d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1d;
architecture beh of dfc1d is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end dfe1b;
architecture beh of dfe1b is
signal q_int_1 : std_logic;
signal nq : std_logic;
begin
nq <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk)
begin
if rising_edge(clk) then
q_int_1 <= nq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfe3c;
architecture beh of dfe3c is
signal q_int_0 : std_logic;
signal md : std_logic;
begin
md <= d when e = '0' else q_int_0;
q <= q_int_0;
ff : process (clk, clr)
begin
if clr = '0' then
q_int_0 <= '0';
elsif rising_edge(clk) then
q_int_0 <= md;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfe4f;
architecture beh of dfe4f is
signal q_int_1 : std_logic;
signal un1 : std_logic;
begin
un1 <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk, pre)
begin
if pre = '0' then
q_int_1 <= '1';
elsif rising_edge(clk) then
q_int_1 <= un1;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1;
architecture beh of dfp1 is
begin
ff : process (clk, pre)
begin
if pre = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1b;
architecture beh of dfp1b is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1d;
architecture beh of dfp1d is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfeh is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end dfeh;
architecture beh of dfeh is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif falling_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_dfeh is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic;
yout : out std_logic);
end iooe_dfeh;
architecture beh of iooe_dfeh is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
yout <= '0';
elsif pre = '0' then
q <= '1';
yout <= '1';
elsif falling_edge(clk) and (e = '0') then
q <= d;
yout <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end dfeg;
architecture beh of dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfmeg is
port(
a : in std_logic;
b : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
s : in std_logic;
q : out std_logic);
end dfmeg;
architecture beh of dfmeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
if s = '0' then q <= a; else q <= b; end if;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ioi_dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end ioi_dfeg;
architecture beh of ioi_dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic;
yout : out std_logic);
end iooe_dfeg;
architecture beh of iooe_dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
yout <= '0';
elsif pre = '0' then
q <= '1';
yout <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
yout <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity gnd is
port(
y : out std_logic);
end gnd;
architecture beh of gnd is
begin
y <= '0';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfm is
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end dfm;
architecture beh of dfm is
begin
ff : process (clk)
begin
if rising_edge(clk) then
if s = '0' then q <= a;
else q <= b; end if;
end if;
end process ff;
end beh;
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity hclkbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end hclkbuf;
--architecture beh of hclkbuf is
--begin
-- y <= pad;
--end beh;
--
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity inbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end inbuf;
--architecture beh of inbuf is
--begin
-- y <= pad;
--end beh;
library ieee;
use ieee.std_logic_1164.all;
entity inv is
port(
a : in std_logic;
y : out std_logic);
end inv;
architecture beh of inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity nand2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end nand2;
architecture beh of nand2 is
signal yx : std_logic;
begin
yx <= b and a;
y <= not yx;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end nand4;
architecture beh of nand4 is
signal yx : std_logic;
begin
yx <= d and c and b and a;
y <= not yx;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2;
architecture beh of or2 is
begin
y <= b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2a;
architecture beh of or2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2b;
architecture beh of or2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3;
architecture beh of or3 is
begin
y <= c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3a;
architecture beh of or3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3b;
architecture beh of or3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3c;
architecture beh of or3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4;
architecture beh of or4 is
begin
y <= d or c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4a;
architecture beh of or4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d or c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4b;
architecture beh of or4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d or c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4c;
architecture beh of or4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4d;
architecture beh of or4d is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
signal di : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
di <= not d;
y <= di or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end sub1;
architecture beh of sub1 is
signal un1_b : std_logic;
signal un3_fco : std_logic;
signal un1_fco : std_logic;
signal un4_fco : std_logic;
begin
un1_b <= not b;
un3_fco <= a and fci;
s <= a xor fci xor un1_b;
un1_fco <= a and un1_b;
un4_fco <= fci and un1_b;
fco <= un1_fco or un3_fco or un4_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity vcc is
port(
y : out std_logic);
end vcc;
architecture beh of vcc is
begin
y <= '1';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xa1;
architecture beh of xa1 is
signal xab : std_logic;
begin
xab <= b xor a;
y <= c and xab;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xnor2;
architecture beh of xnor2 is
signal yi : std_logic;
begin
yi <= b xor a;
y <= not yi;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xor2;
architecture beh of xor2 is
begin
y <= b xor a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xor3;
architecture beh of xor3 is
begin
y <= (c xor b) xor a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end xor4;
architecture beh of xor4 is
signal xab, xcd : std_logic;
begin
xab <= b xor a;
xcd <= c xor d;
y <= xab xor xcd;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor4_fci is
port(a,b,c,fci : in std_logic;
y : out std_logic);
end xor4_fci;
architecture beh of xor4_fci is
signal xab, xcd : std_logic;
begin
xab <= b xor a;
xcd <= c xor fci;
y <= xab xor xcd;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity mx2 is
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end mx2;
architecture beh of mx2 is
signal xab : std_logic;
begin
y <= b when s = '0' else a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity mx4 is
port(
d0 : in std_logic;
s0 : in std_logic;
d1 : in std_logic;
s1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
y : out std_logic);
end mx4;
architecture beh of mx4 is
begin
y <= d0 when (s1 = '0' and s0 = '0') else
d1 when (s1 = '0' and s0 = '1') else
d2 when (s1 = '1' and s0 = '0') else d3;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity bufd is
port(
a : in std_logic;
y : out std_logic);
end bufd;
architecture beh of bufd is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xai1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xai1;
architecture beh of xai1 is
begin
y <= not (c and not (a xor b));
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ax1c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end ;
architecture beh of ax1c is
begin
y <= (a and b) xor c;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ax1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end ax1;
architecture beh of ax1 is
begin
y <= (((not a) and b) xor c);
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cy2a is
port(
a1 : in std_logic;
b1 : in std_logic;
a0 : in std_logic;
b0 : in std_logic;
y : out std_logic);
end cy2a;
architecture beh of cy2a is
begin
y <= ((( a1 AND b1 ) OR (( a0 AND b0 ) AND a1 )) OR (( a0 AND b0 ) AND b1 ));
end beh;
-- pragma translate_on
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/i2c/i2c_master_bit_ctrl.vhd | 2 | 20013 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]):
-- * Added two start states to fulfill Set-up time for
-- repeated START condition.
-- * Modified synchronization of SCL and SDA. START and STOP detection
-- is now performed after a two stage synchronizer and is also
-- filtered.
-- * Changed evaluation order of 'slave_wait', 'en' and 'cnt' in
-- generation of clk_en signal to prevent clk_en assertion when
-- slave_wait is asserted.
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e, start_f, start_g,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal disda_oen : std_logic; -- delayed isda_oen
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic_vector(1 downto 0); -- delayed scl_oen signals
-- synchronized SCL and SDA inputs
signal sSCL, sSDA : std_logic_vector(5 downto 0);
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : std_logic_vector(15 downto 0); -- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
dscl_oen <= dscl_oen(0) & iscl_oen;
end if;
end process;
slave_wait <= dscl_oen(1) and not sSCL(1);
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif (ena = '0') then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
elsif (cnt = X"0000") then
cnt <= clk_cnt;
clk_en <= '1';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
--signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= (others => '1');
sSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= (others => '1');
sSDA <= (others => '1');
else
sSCL <= sSCL(4 downto 0) & scl_i;
sSDA <= sSDA(4 downto 0) & sda_i;
end if;
end if;
end process synch_SCL_SDA;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
if sSCL(5 downto 2) = "1111" and sSDA(5 downto 2) = "1100" then
sta_condition <= '1';
else
sta_condition <= '0';
end if;
if sSCL(5 downto 2) = "1111" and sSDA(5 downto 2) = "0011" then
sto_condition <= '1';
else
sto_condition <= '0';
end if;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not sSDA(1) and disda_oen);
else
ial <= (sda_chk and not sSDA(1) and disda_oen) or
(sto_condition and not cmd_stop);
end if;
disda_oen <= isda_oen;
end if;
end if;
end process gen_al;
al <= ial;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if sSCL(3 downto 2) = "01" then
dout <= sSDA(2);
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; -- default no acknowledge
if (clk_en = '1') then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle; -- NOP command
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= start_f;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_f =>
c_state <= start_g;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_g =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
| mit |
lxp32/lxp32-cpu | rtl/lxp32_divider.vhd | 1 | 3915 | ---------------------------------------------------------------------
-- Divider
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Based on the NRD (Non Restoring Division) algorithm. Takes
-- 36 cycles to calculate quotient (37 for remainder).
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_divider is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
op1_i: in std_logic_vector(31 downto 0);
op2_i: in std_logic_vector(31 downto 0);
signed_i: in std_logic;
rem_i: in std_logic;
ce_o: out std_logic;
result_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_divider is
-- Complementor signals
signal compl_inv: std_logic;
signal compl_mux: std_logic_vector(31 downto 0);
signal compl_out: std_logic_vector(31 downto 0);
signal inv_res: std_logic;
-- Divider FSM signals
signal fsm_ce: std_logic:='0';
signal dividend: unsigned(31 downto 0);
signal divisor: unsigned(32 downto 0);
signal want_remainder: std_logic;
signal partial_remainder: unsigned(32 downto 0);
signal addend: unsigned(32 downto 0);
signal sum: unsigned(32 downto 0);
signal sum_positive: std_logic;
signal sum_subtract: std_logic;
signal cnt: integer range 0 to 34:=0;
signal ceo: std_logic:='0';
-- Output restoration signals
signal remainder_corrector: unsigned(31 downto 0);
signal remainder_corrector_1: std_logic;
signal remainder_pos: unsigned(31 downto 0);
signal result_pos: unsigned(31 downto 0);
begin
compl_inv<=op1_i(31) and signed_i when ce_i='1' else inv_res;
compl_mux<=op1_i when ce_i='1' else std_logic_vector(result_pos);
compl_op1_inst: entity work.lxp32_compl(rtl)
port map(
clk_i=>clk_i,
compl_i=>compl_inv,
d_i=>compl_mux,
d_o=>compl_out
);
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
fsm_ce<='0';
want_remainder<='-';
inv_res<='-';
else
fsm_ce<=ce_i;
if ce_i='1' then
want_remainder<=rem_i;
if rem_i='1' then
inv_res<=op1_i(31) and signed_i;
else
inv_res<=(op1_i(31) xor op2_i(31)) and signed_i;
end if;
end if;
end if;
end if;
end process;
-- Main adder/subtractor
addend_gen: for i in addend'range generate
addend(i)<=divisor(i) xor sum_subtract;
end generate;
sum<=partial_remainder+addend+(to_unsigned(0,32)&sum_subtract);
sum_positive<=not sum(32);
-- Divider state machine
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
cnt<=0;
ceo<='0';
divisor<=(others=>'-');
dividend<=(others=>'-');
partial_remainder<=(others=>'-');
sum_subtract<='-';
else
if cnt=1 then
ceo<='1';
else
ceo<='0';
end if;
if ce_i='1' then
divisor(31 downto 0)<=unsigned(op2_i);
divisor(32)<=op2_i(31) and signed_i;
end if;
if fsm_ce='1' then
dividend<=unsigned(compl_out(30 downto 0)&"0");
partial_remainder<=to_unsigned(0,32)&compl_out(31);
sum_subtract<=not divisor(32);
if want_remainder='1' then
cnt<=34;
else
cnt<=33;
end if;
else
partial_remainder<=sum(31 downto 0)÷nd(31);
sum_subtract<=sum_positive xor divisor(32);
dividend<=dividend(30 downto 0)&sum_positive;
if cnt>0 then
cnt<=cnt-1;
end if;
end if;
end if;
end if;
end process;
-- Output restoration circuit
process (clk_i) is
begin
if rising_edge(clk_i) then
for i in remainder_corrector'range loop
remainder_corrector(i)<=(divisor(i) xor divisor(32)) and not sum_positive;
end loop;
remainder_corrector_1<=divisor(32) and not sum_positive;
remainder_pos<=partial_remainder(32 downto 1)+remainder_corrector+
(to_unsigned(0,31)&remainder_corrector_1);
end if;
end process;
result_pos<=remainder_pos when want_remainder='1' else dividend;
result_o<=compl_out;
ce_o<=ceo;
end architecture;
| mit |
amerc/phimii | source/nexys3.vhd | 1 | 25661 | --------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: [email protected]
--- :license: MIT
--- :
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
--- :Modified by Amer Al-Canaan, June 2014
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> (100 MHz) |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (25MHz) ->+ ODDR2 +-->[GTXCLK] *** Not used in Nexys3
--- | | | **not |
--- | +-- CLK3_N (25MHZ) ->+ used |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+ +--------------+
--- | SERVER | | USER DESIGN |
--- +-------------+ +--------------+
--- | | | |
--- | >-----> <-------< SWITCHES
--- | | | |
--- | <-----< >-------> LEDS
--- | | | |
--- | | | <-------< BUTTONS
--- | | | |
--- | | +----^----v----+
--- | | | |
--- | | +----^----v----+
--- | | | UART |
--- | | +--------------+
--- | | | >-------> RS232-TX
--- | | | |
--- +---v-----^---+ | <-------< RS232-RX
--- | | +--------------+
--- +---v-----^---+
--- | ETHERNET |
--- | MAC |
--- +-------------+
--- | +------> [PHY_RESET]
--- | |
---[RXCLK]<----->+ (25 MHz) |
--- | |
---[TXCLK] ----->+ (25 MHz) |
--- | |
--- [RXD]<----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER]<----->+ +<------> [TXER]
--- | |
--- | |
--- +-------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity NEXYS3 is
port(
CLK_IN : in std_logic;
RST : in std_logic;
--PHY INTERFACE
TX : out std_logic;
RX : in std_logic;
PHY_RESET : out std_logic;
RXDV : in std_logic;
RXER : inout std_logic; --* inout
RXCLK : inout std_logic; --* inout
RXD : inout std_logic_vector(3 downto 0); --* inout
TXCLK : in std_logic;
TXD : out std_logic_vector(3 downto 0);
TXEN : out std_logic;
TXER : out std_logic;
PhyCol : inout std_logic; --* inout
CRS : in std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(7 downto 0);
GPIO_SWITCHES : in std_logic_vector(7 downto 0);
GPIO_BUTTONS : in std_logic_vector(3 downto 0);
--RS232 INTERFACE
fx2Clk_pin : in std_logic;
RS232_RX : in std_logic;
RS232_TX : out std_logic;
-- 7 seg out
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anodes_out : out std_logic_vector(3 downto 0) -- seven-segment display anodes (one for each digit)
);
end entity NEXYS3;
architecture RTL of NEXYS3 is
component ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
--Ethernet Clock
--MII IF
TXCLK : in std_logic; --
TXER : out std_logic; --
TXEN : out std_logic; --
TXD : out std_logic_vector(3 downto 0); --
RXCLK : in std_logic; --
RXER : in std_logic;--
RXDV : in std_logic; --
RXD : in std_logic_vector(3 downto 0); --
COL : in std_logic;-- *input Added .. Collision indication
PhyCRS : in std_logic;-- *input Added .. Carrier sense
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic;
-- LEDS --AMER
GPIO_LEDS : out std_logic_vector(3 downto 0);
BtnL : in std_logic;
SW0 : in std_logic;
--7 seg
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anodes_out : out std_logic_vector(3 downto 0) -- seven-segment display anodes (one for each digit)
);
end component ethernet;
component SERVER is
port(
CLK : in std_logic;
RST : in std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(15 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
output_eth_tx : out std_logic_vector(15 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic
);
end component;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
OUTPUT_LEDS : out std_logic_vector(15 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SWITCHES : in std_logic_vector(15 downto 0);
INPUT_SWITCHES_STB : in std_logic;
INPUT_SWITCHES_ACK : out std_logic;
INPUT_BUTTONS : in std_logic_vector(15 downto 0);
INPUT_BUTTONS_STB : in std_logic;
INPUT_BUTTONS_ACK : out std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic;
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(15 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(15 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
component SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end component SERIAL_INPUT;
component serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic
);
end component serial_output;
component initPhyNexys3 is
port(
clk : in std_logic;
reset : in std_logic;
phy_reset : out std_logic;
out_en : out std_logic
);
end component initPhyNexys3;
--chips signals
signal CLK : std_logic;
signal RST_INV : std_logic;
signal nOEN : std_logic;
--signal toPhyReset : std_logic;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clk50 : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal CLK_OUT1 : std_logic;
signal CLK_OUT50 : std_logic;
signal CLK_OUT3 : std_logic;
signal CLK_OUT3_N : std_logic;
signal CLK_OUT2 : std_logic;
signal CLK_OUT4 : std_logic;
signal NOT_LOCKED : std_logic;
signal INTERNAL_RST : std_logic;
--signal RXD1 : std_logic;
signal TX_LOCKED : std_logic;
signal INTERNAL_TXCLK : std_logic;
signal INTERNAL_TXCLK_BUF: std_logic;
signal INTERNAL_TXCLK_BUF_N : std_logic;
-- signal INTERNAL_TXCLK_BUF_180 : std_logic;
signal TXCLK_BUF : std_logic;
signal INTERNAL_RXCLK : std_logic;
signal RXCLK_INT : std_logic; -- Here
signal INTERNAL_RXCLK_BUF: std_logic;
signal RXCLK_BUF : std_logic;
signal RXER_BUF : std_logic; --Added signal
signal RXD_BUF : std_logic_vector(3 downto 0); --Added signal
---Below added by AMER
signal INTERNAL_TXD : std_logic_vector(3 downto 0);
signal INTERNAL_TXEN : std_logic;
signal INTERNAL_TXER : std_logic;
---Up added by AMER
signal COL_BUF : std_logic; --Added signal
signal ToEXTERNAL_TXER : std_logic; --Added signal
-- signal nINT : std_logic; --Added signal
signal OUTPUT_LEDS : std_logic_vector(15 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SWITCHES : std_logic_vector(15 downto 0);
signal INPUT_SWITCHES_STB : std_logic;
signal INPUT_SWITCHES_ACK : std_logic;
signal GPIO_SWITCHES_D : std_logic_vector(7 downto 0);
signal INPUT_BUTTONS : std_logic_vector(15 downto 0);
signal INPUT_BUTTONS_STB : std_logic;
signal INPUT_BUTTONS_ACK : std_logic;
signal GPIO_BUTTONS_D : std_logic_vector(3 downto 0);
--ETH RX STREAM
signal ETH_RX : std_logic_vector(15 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(15 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(15 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
signal fx2Clk : std_logic;
signal OUTPUT_RS232_TX : std_logic_vector(15 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--SOCKET RX STREAM
signal INPUT_SOCKET : std_logic_vector(15 downto 0);
signal INPUT_SOCKET_STB : std_logic;
signal INPUT_SOCKET_ACK : std_logic;
--SOCKET TX STREAM
signal OUTPUT_SOCKET : std_logic_vector(15 downto 0);
signal OUTPUT_SOCKET_STB : std_logic;
signal OUTPUT_SOCKET_ACK : std_logic;
-- --SSeg output
-- signal Tosseg_dat : std_logic_vector(15 downto 0);
-- signal ssflags : std_logic_vector;
begin
initPhyNexys3_inst1 : initPhyNexys3 port map (
clk => CLK,
reset => RST,
phy_reset => PHY_RESET,
out_en => nOEN
);
ethernet_inst_1 : ethernet port map(
CLK => CLK,
RST => INTERNAL_RST,
--MII IF
TXCLK => TXCLK,
TXER => INTERNAL_TXER,
TXEN => INTERNAL_TXEN,
TXD => INTERNAL_TXD,
RXCLK => INTERNAL_RXCLK,--ok
RXER => RXER_BUF,
RXDV => RXDV,
RXD => RXD_BUF, -- ok
COL => COL_BUF, -- ok
PhyCRS => CRS, -- ok
--RX STREAM
TX => ETH_TX,
TX_STB => ETH_TX_STB,
TX_ACK => ETH_TX_ACK,
--RX STREAM
RX => ETH_RX,
RX_STB => ETH_RX_STB,
RX_ACK => ETH_RX_ACK,
BtnL => GPIO_BUTTONS(0),
SW0 => GPIO_SWITCHES(0),
--LEDs and 7seg AMER
GPIO_LEDS => GPIO_LEDS(7 downto 4),
sseg_out => sseg_out,
anodes_out => anodes_out
);
SERVER_INST_1 : SERVER port map(
CLK => CLK,
RST => INTERNAL_RST,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => INPUT_SOCKET,
INPUT_SOCKET_STB => INPUT_SOCKET_STB,
INPUT_SOCKET_ACK => INPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => OUTPUT_SOCKET,
OUTPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK
);
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK,
RST => INTERNAL_RST,
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SWITCHES => INPUT_SWITCHES,
INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
INPUT_BUTTONS => INPUT_BUTTONS,
INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => OUTPUT_SOCKET,
INPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
INPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => INPUT_SOCKET,
OUTPUT_SOCKET_STB => INPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => INPUT_SOCKET_ACK
);
SERIAL_OUTPUT_INST_1 : serial_output generic map(
CLOCK_FREQUENCY => 48000000,--48000000,
BAUD_RATE => 115200
)port map(
CLK => CLK,--fx2Clk, --AMER
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,--48000000,
BAUD_RATE => 115200
) port map (
CLK => CLK,--fx2Clk, -- AMER
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(15 downto 8) <= (others => '0');
process
begin
wait until rising_edge(CLK);
NOT_LOCKED <= not LOCKED_INTERNAL;
INTERNAL_RST <= NOT_LOCKED;
-- Desactivated the following to be used as test indicators
if OUTPUT_LEDS_STB = '1' then --AMER
GPIO_LEDS(3 downto 0) <= OUTPUT_LEDS(3 downto 0); -- AMER
end if;-- AMER
OUTPUT_LEDS_ACK <= '1';
INPUT_SWITCHES_STB <= '1';
GPIO_SWITCHES_D <= GPIO_SWITCHES;
INPUT_SWITCHES(7 downto 0) <= GPIO_SWITCHES_D;
INPUT_SWITCHES(15 downto 8) <= (others => '0');
INPUT_BUTTONS_STB <= '1';
GPIO_BUTTONS_D <= GPIO_BUTTONS;
INPUT_BUTTONS(3 downto 0) <= GPIO_BUTTONS_D;
INPUT_BUTTONS(15 downto 4) <= (others => '0');
end process;
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT2 100.000
-- CLK_OUT3 25.000
-- CLK_OUT4 200.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 100.000 ****** the main clock on Nexys3 is 100 Mhz
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
BUFG_INST9 : BUFG
port map
(O => RXCLK_BUF,
I => RXCLK_INT);
fx2Clk_in_buf : IBUFG
port map
(O => fx2Clk,
I => fx2Clk_pin);
--- The DCM has an active high RST input so RST_INV hould be same as RST
RST_INV <= RST;------------not RST; -- AMER
dcm_sp_inst: DCM_SP ----------------------------
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 8, -- to get 25 MHz
CLKFX_MULTIPLY => 2, -- to get 25 MHz
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0, -- input main clock = 100 MHz
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1, -- main clock input = 100 MHz
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0, -- 100 MHz
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,-- 200 MHz
CLK2X180 => open,
CLKFX => clkfx, -- 25 MHz
CLKFX180 => clkfx180, -- 25 MHz @ 180 deg.
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => TX_LOCKED,
STATUS => status_internal,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
----------------------------------------------------------- AMER
dcm_sp_inst2: DCM_SP -------------RXCLK----------
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 40.0, -- for rxclk = 25 MHz
CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 14,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => RXCLK_BUF, -- 25 MHz from Phy
CLKFB => INTERNAL_RXCLK, --ok
-- Output clocks
CLK0 => INTERNAL_RXCLK_BUF,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => open,
STATUS => open,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
--------------------------------------------------------- AMER
-- Output buffering
-------------------------------------
clkfb <= CLK_OUT2; -- 100 MHz
BUFG_INST7 : BUFG
port map
(O => INTERNAL_RXCLK,
I => INTERNAL_RXCLK_BUF);
BUFG_INST1 : BUFG
port map
(O => CLK_OUT1,
I => clkdv);
BUFG_INST2 : BUFG
port map
(O => CLK_OUT2, -- 100 MHz
I => clk0);
BUFG_INST3 : BUFG
port map
(O => CLK_OUT3,
I => clkfx);
BUFG_INST4 : BUFG
port map
(O => CLK_OUT3_N,
I => clkfx180);
BUFG_INST5 : BUFG
port map
(O => CLK_OUT4,
I => clk2x);
-- Input buffering
-------------------- RXCLK/PHYAD1 io pin --------
IOBUF_INST1 : IOBUF
port map
(O => RXCLK_INT,
IO => RXCLK, -- RXCLK/PHYAD1 io pin
I => '1', ---PhyAddress 1
T => nOEN); --3-state enable input
-------------------------- RXER/RXD4/PHYAD0 --------------------------
IOBUF_INST2 : IOBUF
port map
(O => RXER_BUF,
IO => RXER,
I => '1', ---(PhyAddress bit 0) = 1
T => nOEN); --3-state enable input
---------------------------- COL/CRS_DV/MODE2 -------------------------------------
IOBUF_INST3 : IOBUF
port map
(O => COL_BUF,
IO => PhyCol, --COL_BUF
I => '0', ---(MODE2 bit) = 0
T => nOEN); --3-state enable input
------------------------------- nINT/TXER/TXD4-----------------------
-----------------------------------------------------------------
IOBUF_INST5 : IOBUF ------- RXD0/MODE0----
port map
(O => RXD_BUF(0), ---RXD0 input pin
IO => RXD(0), -- RXD0/MODE0 io pin
I => '1', -- MODE0 (mode bit0) = 1
T => nOEN); --3-state enable input
-----------------------------------------------------------------
IOBUF_INST6 : IOBUF ------- RXD1/MODE1----
port map
(O => RXD_BUF(1), ---(interrupt input) = 1, not used
IO => RXD(1), -- RXD1/MODE1 io pin
I => '1', -- MODE1 (mode bit1) = 1
T => nOEN); --3-state enable input
-----------------------------------------------------------------
IOBUF_INST7 : IOBUF ------- RXD2/RMIISEL----
port map
(O => RXD_BUF(2), ---(interrupt input) = 1, not used
IO => RXD(2), -- RXD2/RMIISEL io pin
I => '0', -- RMIISEL = 0 (MII mode is selected)
T => nOEN); --3-state enable input
-----------------------------------------------------------------
IOBU_INST8 : IOBUF ------- RXD3/PHYAD2----
port map
(O => RXD_BUF(3), ---(interrupt input) = 1, not used
IO => RXD(3), -- RXD3/PHYAD2 io pin
I => '0', -- PHYAD2 (Phy address bit 2)= 0
T => nOEN); --3-state enable input
-----------------------------------------------------------------
LOCKED_INTERNAL <= TX_LOCKED;
------------------------------------------------------ AMER
-- Use ODDRs for clock/data forwarding
--------------------------------------
ODDR2_INST2_GENERATE : for I in 0 to 3 generate
ODDR2_INST2 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXD(I), -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXD(I), -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXD(I), -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate;
ODDR2_INST3 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXEN, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXEN, -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXEN, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
ODDR2_INST4 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXER, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXER, --ok -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXER, --ok -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
------------------------------------------------------ AMER
-- Chips CLK frequency selection
-------------------------------------
CLK <= CLK_OUT1; --50 MHz
--CLK <= CLK_OUT2; --100 MHz
--CLK <= CLK_OUT3; --25 MHz
--CLK <= CLK_OUT4; --200 MHz
end architecture RTL;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/spacewire/spacewire.vhd | 2 | 6484 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package spacewire is
type grspw_in_type is record
d : std_logic_vector(1 downto 0);
s : std_logic_vector(1 downto 0);
tickin : std_ulogic;
clkdiv10 : std_logic_vector(7 downto 0);
rmapen : std_ulogic;
dcrstval : std_logic_vector(9 downto 0);
timerrstval : std_logic_vector(11 downto 0);
end record;
type grspw_out_type is record
d : std_logic_vector(1 downto 0);
s : std_logic_vector(1 downto 0);
tickout : std_ulogic;
linkdis : std_ulogic;
end record;
component grspw2 is
generic(
tech : integer range 0 to NTECH := inferred;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
memtech : integer range 0 to NTECH := DEFMEMTECH
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type
);
end component;
component grspw is
generic(
tech : integer range 0 to NTECH := DEFFABTECH;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
netlist : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
memtech : integer range 0 to NTECH := DEFMEMTECH
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type);
end component;
type grspw_in_type_vector is array (natural range <>) of grspw_in_type;
type grspw_out_type_vector is array (natural range <>) of grspw_out_type;
component grspwm is
generic(
tech : integer range 0 to NTECH := DEFFABTECH;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
netlist : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
memtech : integer range 0 to NTECH := DEFMEMTECH;
spwcore : integer range 1 to 2 := 2
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type
);
end component;
end package;
| mit |
lxp32/lxp32-cpu | verify/lxp32/src/tb/tb_pkg.vhd | 2 | 1638 | ---------------------------------------------------------------------
-- LXP32 testbench package
--
-- Part of the LXP32 testbench
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Auxiliary package declaration for the LXP32 testbench
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package tb_pkg is
constant c_max_program_size: integer:=8192;
type soc_globals_type is record
rst_i: std_logic;
cpu_rst_i: std_logic;
end record;
type soc_wbs_in_type is record
cyc: std_logic;
stb: std_logic;
we: std_logic;
sel: std_logic_vector(3 downto 0);
adr: std_logic_vector(31 downto 2);
dat: std_logic_vector(31 downto 0);
end record;
type soc_wbs_out_type is record
ack: std_logic;
dat: std_logic_vector(31 downto 0);
end record;
type soc_wbm_in_type is record
ack: std_logic;
dat: std_logic_vector(31 downto 0);
end record;
type soc_wbm_out_type is record
cyc: std_logic;
stb: std_logic;
we: std_logic;
sel: std_logic_vector(3 downto 0);
adr: std_logic_vector(27 downto 2);
dat: std_logic_vector(31 downto 0);
end record;
type monitor_out_type is record
data: std_logic_vector(31 downto 0);
valid: std_logic;
end record;
procedure load_ram(
filename: string;
signal clk: in std_logic;
signal soc_in: out soc_wbs_in_type;
signal soc_out: in soc_wbs_out_type
);
procedure run_test(
filename: string;
signal clk: in std_logic;
signal globals: out soc_globals_type;
signal soc_in: out soc_wbs_in_type;
signal soc_out: in soc_wbs_out_type;
signal result: in monitor_out_type
);
end package;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/techmap/unisim/clkgen_unisim.vhd | 2 | 29179 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex2 clock generator ---------------------------------------
------------------------------------------------------------------
entity clkgen_virtex2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex2 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "20.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
bufg3 : BUFG port map (I => clk_x, O => clk_i2);
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex2" & ": virtex-2 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex2" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.CLKDLL;
use unisim.BUFGDLL;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture rtl of clkgen_virtex is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, dll0rst, dll0lock, dll1lock : std_logic;
signal dll1rst : std_logic_vector(0 to 3);
signal clk0B, clkint, CLK2XL, CLKDV, CLK180, pciclkint : std_logic;
begin
gnd <= '0'; clk <= clk_i; clkn <= not clk_i;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0rst <= not cgi.pllrst;
dll0 : CLKDLL
port map (CLKIN => clkint, CLKFB => clk_k, CLK0 => clk_j, CLK180 => CLK180,
CLK2X => CLK2XL, CLKDV => CLKDV, LOCKED => dll0lock, RST => dll0rst);
clk0B <= CLK2XL when clk_mul/clk_div = 2
else CLKDV when clk_div/clk_mul = 2 else clk_j;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB = 0) generate
cgo.clklock <= dll1lock;
dll1 : CLKDLL
port map (CLKIN => clk_i, CLKFB => cgi.pllref, RST => dll1rst(0), CLK0 => sdclk,
CLK2X => clk2x, LOCKED => dll1lock);
rstdel : process (clk_i)
begin
if dll0lock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_i) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if not ((SDRAMEN /= 0) and (NOCLKFB = 0)) generate
sdclk <= clk_i; cgo.clklock <= dll0lock;
end generate;
cgo.pcilock <= '1';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkmul_virtex2 is
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end;
architecture struct of clkmul_virtex2 is
-- attribute CLKFX_MULTIPLY : string;
-- attribute CLKFX_DIVIDE : string;
attribute CLKIN_PERIOD : string;
--
-- attribute CLKFX_MULTIPLY of dll0: label is "5";
-- attribute CLKFX_DIVIDE of dll0: label is "4";
attribute CLKIN_PERIOD of dll0: label is "20";
--
-- attribute CLKFX_MULTIPLY of dll1: label is "4";
-- attribute CLKFX_DIVIDE of dll1: label is "4";
-- attribute CLKIN_PERIOD of dll1: label is "25";
--
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, clk_l : std_logic;
signal clk0B, clk_FB, dll0rst, lock : std_logic;
begin
gnd <= '0'; clk <= clk_i;
dll0rst <= not resetin;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkin, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
LOCKED => resetout, CLKFX => clk0B );
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_spartan3 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 50000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_spartan3 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "20.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= not clk_i when (CLK2XEN = 0) else not clk_p;
clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_j;
clk2xu <= clk_k;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_x, O => clk_k);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "2X")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_k;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_spartan3e" & ": spartan3/e sdram/pci clock generator, version " & tost(VERSION),
"clkgen_spartan3e" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
------------------------------------------------------------------
-- Virtex5 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex5 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex5 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "20.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, lsdclk : std_logic;
signal clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r: std_logic;
signal dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_x;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
bufgx : BUFG port map (I => lsdclk, O => sdclk);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex5" & ": virtex-5 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex5" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkand_unisim is
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkand_unisim is
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC
);
end component;
begin
buf : bufgce port map(I => i, CE => en, O => o);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_unisim is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_unisim is
component bufgmux is
port(
i0, i1 : in std_ulogic;
s : in std_ulogic;
o : out std_ulogic);
end component;
signal sel0, sel1, cg0, cg1 : std_ulogic;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/unisim/clkgen_unisim.vhd | 2 | 29179 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex2 clock generator ---------------------------------------
------------------------------------------------------------------
entity clkgen_virtex2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex2 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "20.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
bufg3 : BUFG port map (I => clk_x, O => clk_i2);
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex2" & ": virtex-2 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex2" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.CLKDLL;
use unisim.BUFGDLL;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture rtl of clkgen_virtex is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, dll0rst, dll0lock, dll1lock : std_logic;
signal dll1rst : std_logic_vector(0 to 3);
signal clk0B, clkint, CLK2XL, CLKDV, CLK180, pciclkint : std_logic;
begin
gnd <= '0'; clk <= clk_i; clkn <= not clk_i;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0rst <= not cgi.pllrst;
dll0 : CLKDLL
port map (CLKIN => clkint, CLKFB => clk_k, CLK0 => clk_j, CLK180 => CLK180,
CLK2X => CLK2XL, CLKDV => CLKDV, LOCKED => dll0lock, RST => dll0rst);
clk0B <= CLK2XL when clk_mul/clk_div = 2
else CLKDV when clk_div/clk_mul = 2 else clk_j;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB = 0) generate
cgo.clklock <= dll1lock;
dll1 : CLKDLL
port map (CLKIN => clk_i, CLKFB => cgi.pllref, RST => dll1rst(0), CLK0 => sdclk,
CLK2X => clk2x, LOCKED => dll1lock);
rstdel : process (clk_i)
begin
if dll0lock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_i) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if not ((SDRAMEN /= 0) and (NOCLKFB = 0)) generate
sdclk <= clk_i; cgo.clklock <= dll0lock;
end generate;
cgo.pcilock <= '1';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkmul_virtex2 is
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end;
architecture struct of clkmul_virtex2 is
-- attribute CLKFX_MULTIPLY : string;
-- attribute CLKFX_DIVIDE : string;
attribute CLKIN_PERIOD : string;
--
-- attribute CLKFX_MULTIPLY of dll0: label is "5";
-- attribute CLKFX_DIVIDE of dll0: label is "4";
attribute CLKIN_PERIOD of dll0: label is "20";
--
-- attribute CLKFX_MULTIPLY of dll1: label is "4";
-- attribute CLKFX_DIVIDE of dll1: label is "4";
-- attribute CLKIN_PERIOD of dll1: label is "25";
--
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, clk_l : std_logic;
signal clk0B, clk_FB, dll0rst, lock : std_logic;
begin
gnd <= '0'; clk <= clk_i;
dll0rst <= not resetin;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkin, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
LOCKED => resetout, CLKFX => clk0B );
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_spartan3 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 50000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_spartan3 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "20.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= not clk_i when (CLK2XEN = 0) else not clk_p;
clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_j;
clk2xu <= clk_k;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_x, O => clk_k);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "2X")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_k;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_spartan3e" & ": spartan3/e sdram/pci clock generator, version " & tost(VERSION),
"clkgen_spartan3e" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
------------------------------------------------------------------
-- Virtex5 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex5 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex5 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "20.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, lsdclk : std_logic;
signal clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r: std_logic;
signal dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_x;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
bufgx : BUFG port map (I => lsdclk, O => sdclk);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex5" & ": virtex-5 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex5" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkand_unisim is
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkand_unisim is
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC
);
end component;
begin
buf : bufgce port map(I => i, CE => en, O => o);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_unisim is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_unisim is
component bufgmux is
port(
i0, i1 : in std_ulogic;
s : in std_ulogic;
o : out std_ulogic);
end component;
signal sel0, sel1, cg0, cg1 : std_ulogic;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/techmap/maps/lvds_combo.vhd | 2 | 3315 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: lvds_combo.vhd
-- File: lvds_combo.vhd.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Differential input/output pads with IREF/OREF logic wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic := '1'
);
end ;
architecture rtl of lvds_combo is
signal gnd : std_ulogic;
signal oen : std_logic_vector(0 to width-1);
constant level : integer := lvds;
begin
gnd <= '0';
gen0 : if has_ds_combo(tech) = 0 generate
swloop : for i in 0 to width-1 generate
od0 : outpad_ds generic map (tech, level, voltage, oepol) port map (odpadp(i), odpadn(i), odval(i), en(i));
os0 : outpad_ds generic map (tech, level, voltage, oepol) port map (ospadp(i), ospadn(i), osval(i), en(i));
id0 : inpad_ds generic map (tech, level, voltage) port map (idpadp(i), idpadn(i), idval(i));
is0 : inpad_ds generic map (tech, level, voltage) port map (ispadp(i), ispadn(i), isval(i));
end generate;
end generate;
combo : if has_ds_combo(tech) /= 0 generate
oen <= not en when oepol /= padoen_polarity(tech) else en;
ut025 : if tech = ut25 generate
u0: ut025crh_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval);
end generate;
um : if tech = umc generate
u0: umc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, lvdsref);
end generate;
rhu : if tech = rhumc generate
u0: rhumc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, lvdsref);
end generate;
end generate;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/leon3/mmu_cache.vhd | 2 | 4966 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cache
-- File: cache.vhd
-- Author: Jiri Gaisler
-- Description: Complete cache sub-system with controllers and rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu_cache is
generic (
hindex : integer := 0;
memtech : integer range 0 to NTECH := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_cache is
signal icol : icache_out_type;
signal dcol : dcache_out_type;
signal mcii : memory_ic_in_type;
signal mcio : memory_ic_out_type;
signal mcdi : memory_dc_in_type;
signal mcdo : memory_dc_out_type;
signal mcmmi : memory_mm_in_type;
signal mcmmo : memory_mm_out_type;
signal mmudci : mmudc_in_type;
signal mmudco : mmudc_out_type;
signal mmuici : mmuic_in_type;
signal mmuico : mmuic_out_type;
signal ahbsi2 : ahb_slv_in_type;
signal ahbi2 : ahb_mst_in_type;
signal ahbo2 : ahb_mst_out_type;
begin
-- instruction cache controller
icache0 : mmu_icache
generic map (irepl=>irepl, isets=>isets, ilinesize=>ilinesize, isetsize=>isetsize, isetlock=>isetlock)
port map ( rst, clk, ici, icol, dci, dcol, mcii, mcio,
crami.icramin, cramo.icramo, fpuholdn, mmudci, mmuici, mmuico);
-- data cache controller
dcache0 : mmu_dcache
generic map (dsu=>dsu, drepl=>drepl, dsets=>dsets, dlinesize=>dlinesize, dsetsize=>dsetsize, dsetlock=>dsetlock, dsnoop=>dsnoop,
itlbnum=>itlbnum, dtlbnum=>dtlbnum, tlb_type=>tlb_type, memtech=>memtech, cached => cached)
port map ( rst, clk, dci, dcol, icol, mcdi, mcdo, ahbsi2,
crami.dcramin, cramo.dcramo, fpuholdn, mmudci, mmudco, sclk);
-- AMBA AHB interface
a0 : mmu_acache
generic map (hindex, ilinesize, cached, clk2x, scantest)
port map (rst, clk, mcii, mcio, mcdi, mcdo, mcmmi, mcmmo, ahbi2, ahbo2, ahbso, hclken);
-- MMU
m0 : mmu
generic map (memtech, itlbnum, dtlbnum, tlb_type, tlb_rep)
port map (rst, clk, mmudci, mmudco, mmuici, mmuico, mcmmo, mcmmi);
ico <= icol;
dco <= dcol;
clk2xgen: if clk2x /= 0 generate
sync0 : clk2xsync generic map (hindex, clk2x)
port map (rst, hclk, clk, ahbi, ahbi2, ahbo2, ahbo, ahbsi, ahbsi2, mcii, mcdi, mcdo, mcmmi.req, mcmmo.grant, hclken);
end generate;
noclk2x : if clk2x = 0 generate
ahbsi2 <= ahbsi;
ahbi2 <= ahbi;
ahbo <= ahbo2;
end generate;
end ;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/techmap/maps/syncram64.vhd | 2 | 4010 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram64
-- File: syncram64.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 64-bit syncronous 1-port ram with 32-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity syncram64 is
generic (tech : integer := 0; abits : integer := 6);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000");
end;
architecture rtl of syncram64 is
component virtex2_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
component artisan_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
component custom1_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
begin
s64 : if has_sram64(tech) = 1 generate
xc2v : if (tech = virtex2) or (tech = spartan3) or (tech = virtex4)
or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex2_syncram64 generic map (abits)
port map (clk, address, datain, dataout, enable, write);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram64 generic map (abits)
port map (clk, address, datain, dataout, enable, write);
end generate;
cust1: if tech = custom1 generate
x0 : custom1_syncram64 generic map (abits)
port map (clk, address, datain, dataout, enable, write);
end generate;
end generate;
nos64 : if has_sram64(tech) = 0 generate
x0 : syncram generic map (tech, abits, 32)
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
enable(1), write(1), testin);
x1 : syncram generic map (tech, abits, 32)
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
enable(0), write(0), testin);
end generate;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/grlib/amba/apbctrl.vhd | 2 | 9001 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbctrl
-- File: apbctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AMBA AHB/APB bridge with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity apbctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
debug : integer range 0 to 2 := 2;
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector
);
end;
architecture rtl of apbctrl is
constant apbmax : integer := 19;
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( 1, 6, 0, VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(haddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(hmask, 12);
type reg_type is record
haddr : std_logic_vector(apbmax downto 0); -- address bus
hwrite : std_logic; -- read/write
hready : std_logic; -- ready
penable : std_logic;
psel : std_logic;
prdata : std_logic_vector(31 downto 0); -- read data
pwdata : std_logic_vector(31 downto 0); -- write data
state : std_logic_vector(1 downto 0); -- state
cfgsel : std_ulogic;
end record;
signal r, rin : reg_type;
--pragma translate_off
signal lapbi : apb_slv_in_type;
--pragma translate_on
begin
comb : process(ahbi, apbo, r, rst)
variable v : reg_type;
variable psel : std_logic_vector(0 to 31);
variable pwdata : std_logic_vector(31 downto 0);
variable apbaddr : std_logic_vector(apbmax downto 0);
variable apbaddr2 : std_logic_vector(31 downto 0);
variable hirq, pirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nslave : integer range 0 to nslaves-1;
variable bnslave : std_logic_vector(3 downto 0);
begin
v := r; v.psel := '0'; v.penable := '0'; psel := (others => '0');
hirq := (others => '0'); pirq := (others => '0');
-- detect start of cycle
if (ahbi.hready = '1') then
if ((ahbi.htrans = HTRANS_NONSEQ) or (ahbi.htrans = HTRANS_SEQ)) and
(ahbi.hsel(hindex) = '1')
then
v.hready := '0'; v.hwrite := ahbi.hwrite;
v.haddr(apbmax downto 0) := ahbi.haddr(apbmax downto 0);
v.state := "01"; v.psel := not ahbi.hwrite;
end if;
end if;
case r.state is
when "00" => null; -- idle
when "01" =>
if r.hwrite = '0' then v.penable := '1';
else v.pwdata := ahbi.hwdata; end if;
v.psel := '1'; v.state := "10";
when others =>
if r.penable = '0' then v.psel := '1'; v.penable := '1'; end if;
v.state := "00"; v.hready := '1';
end case;
psel := (others => '0');
for i in 0 to nslaves-1 loop
if ((apbo(i).pconfig(1)(1 downto 0) = "01") and
((apbo(i).pconfig(1)(31 downto 20) and apbo(i).pconfig(1)(15 downto 4)) =
(r.haddr(19 downto 8) and apbo(i).pconfig(1)(15 downto 4))))
then psel(i) := '1'; end if;
end loop;
bnslave(0) := psel(1) or psel(3) or psel(5) or psel(7) or
psel(9) or psel(11) or psel(13) or psel(15);
bnslave(1) := psel(2) or psel(3) or psel(6) or psel(7) or
psel(10) or psel(11) or psel(14) or psel(15);
bnslave(2) := psel(4) or psel(5) or psel(6) or psel(7) or
psel(12) or psel(13) or psel(14) or psel(15);
bnslave(3) := psel(8) or psel(9) or psel(10) or psel(11) or
psel(12) or psel(13) or psel(14) or psel(15);
nslave := conv_integer(bnslave);
if (r.haddr(19 downto 12) = "11111111") then
v.cfgsel := '1'; psel := (others => '0'); v.penable := '0';
else v.cfgsel := '0'; end if;
v.prdata := apbo(nslave).prdata;
if r.cfgsel = '1' then
v.prdata := apbo(conv_integer(r.haddr(log2x(nslaves)+2 downto 3))).pconfig(conv_integer(r.haddr(2 downto 2)));
end if;
for i in 0 to nslaves-1 loop pirq := pirq or apbo(i).pirq; end loop;
-- AHB respons
ahbo.hready <= r.hready;
ahbo.hrdata <= r.prdata;
ahbo.hirq <= pirq;
if rst = '0' then
v.penable := '0'; v.hready := '1'; v.psel := '0'; v.state := "00";
v.hwrite := '0';
-- pragma translate_off
v.haddr := (others => '0');
-- pragma translate_on
end if;
rin <= v;
-- drive APB bus
apbaddr2 := (others => '0');
apbaddr2(apbmax downto 0) := r.haddr(apbmax downto 0);
apbi.paddr <= apbaddr2;
apbi.pwdata <= r.pwdata;
apbi.pwrite <= r.hwrite;
apbi.penable <= r.penable;
apbi.pirq <= ahbi.hirq;
apbi.testen <= ahbi.testen;
apbi.testoen <= ahbi.testoen;
apbi.scanen <= ahbi.scanen;
apbi.testrst <= ahbi.testrst;
for i in 0 to nslaves-1 loop apbi.psel(i) <= psel(i) and r.psel; end loop;
--pragma translate_off
lapbi.paddr <= apbaddr2;
lapbi.pwdata <= r.pwdata;
lapbi.pwrite <= r.hwrite;
lapbi.penable <= r.penable;
lapbi.pirq <= ahbi.hirq;
for i in 0 to nslaves-1 loop lapbi.psel(i) <= psel(i) and r.psel; end loop;
--pragma translate_on
end process;
ahbo.hindex <= hindex;
ahbo.hconfig <= hconfig;
ahbo.hcache <= '0';
ahbo.hsplit <= (others => '0');
ahbo.hresp <= HRESP_OKAY;
reg : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- pragma translate_off
mon0 : if enbusmon /= 0 generate
mon : apbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
pslvdisable => pslvdisable,
napb => nslaves)
port map(
rst => rst,
clk => clk,
apbi => lapbi,
apbo => apbo,
err => open);
end generate;
diag : process
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable vendori : integer;
variable iosize : integer;
variable iounit : string(1 to 5) := "byte ";
variable memstart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable L1 : line := new string'("");
begin
wait for 3 ns;
if debug = 0 then wait; end if;
print("apbctrl: APB Bridge at " & tost(memstart) & "00000 rev 1");
if debug = 1 then wait; end if;
for i in 0 to nslaves-1 loop
vendor := apbo(i).pconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
device := apbo(i).pconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "apbctrl: slv" & tost(i) & ": " &
iptable(vendori).vendordesc & iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
mask := apbo(i).pconfig(1)(15 downto 4);
k := 0;
while (k<15) and (mask(k) = '0') loop k := k+1; end loop;
iosize := 256 * 2**k; iounit := "byte ";
if (iosize > 1023) then iosize := iosize/1024; iounit := "kbyte"; end if;
print("apbctrl: I/O ports at " &
tost(memstart & (apbo(i).pconfig(1)(31 downto 20) and apbo(i).pconfig(1)(15 downto 4))) &
"00, size " & tost(iosize) & " " & iounit);
assert (apbo(i).pindex = i) or (icheck = 0)
report "APB slave index error on slave " & tost(i) severity failure;
end if;
end loop;
wait;
end process;
-- pragma translate_on
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/amba/apbctrl.vhd | 2 | 9001 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbctrl
-- File: apbctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AMBA AHB/APB bridge with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity apbctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
debug : integer range 0 to 2 := 2;
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector
);
end;
architecture rtl of apbctrl is
constant apbmax : integer := 19;
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( 1, 6, 0, VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(haddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(hmask, 12);
type reg_type is record
haddr : std_logic_vector(apbmax downto 0); -- address bus
hwrite : std_logic; -- read/write
hready : std_logic; -- ready
penable : std_logic;
psel : std_logic;
prdata : std_logic_vector(31 downto 0); -- read data
pwdata : std_logic_vector(31 downto 0); -- write data
state : std_logic_vector(1 downto 0); -- state
cfgsel : std_ulogic;
end record;
signal r, rin : reg_type;
--pragma translate_off
signal lapbi : apb_slv_in_type;
--pragma translate_on
begin
comb : process(ahbi, apbo, r, rst)
variable v : reg_type;
variable psel : std_logic_vector(0 to 31);
variable pwdata : std_logic_vector(31 downto 0);
variable apbaddr : std_logic_vector(apbmax downto 0);
variable apbaddr2 : std_logic_vector(31 downto 0);
variable hirq, pirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nslave : integer range 0 to nslaves-1;
variable bnslave : std_logic_vector(3 downto 0);
begin
v := r; v.psel := '0'; v.penable := '0'; psel := (others => '0');
hirq := (others => '0'); pirq := (others => '0');
-- detect start of cycle
if (ahbi.hready = '1') then
if ((ahbi.htrans = HTRANS_NONSEQ) or (ahbi.htrans = HTRANS_SEQ)) and
(ahbi.hsel(hindex) = '1')
then
v.hready := '0'; v.hwrite := ahbi.hwrite;
v.haddr(apbmax downto 0) := ahbi.haddr(apbmax downto 0);
v.state := "01"; v.psel := not ahbi.hwrite;
end if;
end if;
case r.state is
when "00" => null; -- idle
when "01" =>
if r.hwrite = '0' then v.penable := '1';
else v.pwdata := ahbi.hwdata; end if;
v.psel := '1'; v.state := "10";
when others =>
if r.penable = '0' then v.psel := '1'; v.penable := '1'; end if;
v.state := "00"; v.hready := '1';
end case;
psel := (others => '0');
for i in 0 to nslaves-1 loop
if ((apbo(i).pconfig(1)(1 downto 0) = "01") and
((apbo(i).pconfig(1)(31 downto 20) and apbo(i).pconfig(1)(15 downto 4)) =
(r.haddr(19 downto 8) and apbo(i).pconfig(1)(15 downto 4))))
then psel(i) := '1'; end if;
end loop;
bnslave(0) := psel(1) or psel(3) or psel(5) or psel(7) or
psel(9) or psel(11) or psel(13) or psel(15);
bnslave(1) := psel(2) or psel(3) or psel(6) or psel(7) or
psel(10) or psel(11) or psel(14) or psel(15);
bnslave(2) := psel(4) or psel(5) or psel(6) or psel(7) or
psel(12) or psel(13) or psel(14) or psel(15);
bnslave(3) := psel(8) or psel(9) or psel(10) or psel(11) or
psel(12) or psel(13) or psel(14) or psel(15);
nslave := conv_integer(bnslave);
if (r.haddr(19 downto 12) = "11111111") then
v.cfgsel := '1'; psel := (others => '0'); v.penable := '0';
else v.cfgsel := '0'; end if;
v.prdata := apbo(nslave).prdata;
if r.cfgsel = '1' then
v.prdata := apbo(conv_integer(r.haddr(log2x(nslaves)+2 downto 3))).pconfig(conv_integer(r.haddr(2 downto 2)));
end if;
for i in 0 to nslaves-1 loop pirq := pirq or apbo(i).pirq; end loop;
-- AHB respons
ahbo.hready <= r.hready;
ahbo.hrdata <= r.prdata;
ahbo.hirq <= pirq;
if rst = '0' then
v.penable := '0'; v.hready := '1'; v.psel := '0'; v.state := "00";
v.hwrite := '0';
-- pragma translate_off
v.haddr := (others => '0');
-- pragma translate_on
end if;
rin <= v;
-- drive APB bus
apbaddr2 := (others => '0');
apbaddr2(apbmax downto 0) := r.haddr(apbmax downto 0);
apbi.paddr <= apbaddr2;
apbi.pwdata <= r.pwdata;
apbi.pwrite <= r.hwrite;
apbi.penable <= r.penable;
apbi.pirq <= ahbi.hirq;
apbi.testen <= ahbi.testen;
apbi.testoen <= ahbi.testoen;
apbi.scanen <= ahbi.scanen;
apbi.testrst <= ahbi.testrst;
for i in 0 to nslaves-1 loop apbi.psel(i) <= psel(i) and r.psel; end loop;
--pragma translate_off
lapbi.paddr <= apbaddr2;
lapbi.pwdata <= r.pwdata;
lapbi.pwrite <= r.hwrite;
lapbi.penable <= r.penable;
lapbi.pirq <= ahbi.hirq;
for i in 0 to nslaves-1 loop lapbi.psel(i) <= psel(i) and r.psel; end loop;
--pragma translate_on
end process;
ahbo.hindex <= hindex;
ahbo.hconfig <= hconfig;
ahbo.hcache <= '0';
ahbo.hsplit <= (others => '0');
ahbo.hresp <= HRESP_OKAY;
reg : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- pragma translate_off
mon0 : if enbusmon /= 0 generate
mon : apbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
pslvdisable => pslvdisable,
napb => nslaves)
port map(
rst => rst,
clk => clk,
apbi => lapbi,
apbo => apbo,
err => open);
end generate;
diag : process
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable vendori : integer;
variable iosize : integer;
variable iounit : string(1 to 5) := "byte ";
variable memstart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable L1 : line := new string'("");
begin
wait for 3 ns;
if debug = 0 then wait; end if;
print("apbctrl: APB Bridge at " & tost(memstart) & "00000 rev 1");
if debug = 1 then wait; end if;
for i in 0 to nslaves-1 loop
vendor := apbo(i).pconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
device := apbo(i).pconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "apbctrl: slv" & tost(i) & ": " &
iptable(vendori).vendordesc & iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
mask := apbo(i).pconfig(1)(15 downto 4);
k := 0;
while (k<15) and (mask(k) = '0') loop k := k+1; end loop;
iosize := 256 * 2**k; iounit := "byte ";
if (iosize > 1023) then iosize := iosize/1024; iounit := "kbyte"; end if;
print("apbctrl: I/O ports at " &
tost(memstart & (apbo(i).pconfig(1)(31 downto 20) and apbo(i).pconfig(1)(15 downto 4))) &
"00, size " & tost(iosize) & " " & iounit);
assert (apbo(i).pindex = i) or (icheck = 0)
report "APB slave index error on slave " & tost(i) severity failure;
end if;
end loop;
wait;
end process;
-- pragma translate_on
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/tech/cycloneiii/simprims/cycloneiii_atoms.vhd | 2 | 320097 | -- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 7.1 Build 156 04/30/2007
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
end cycloneiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
end cycloneiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiii_pllpack;
package body cycloneiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1300;
constant MIN_VCO : integer := 300;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
begin
loop_iter := 0;
i_max_iter := MAX_N;
vco_period := vco_phase_shift_step * 8;
while (loop_iter < i_max_iter) loop
loop_iter := loop_iter+1;
i_pre_m := i_m;
i_pre_n := i_n;
find_simple_integer_fraction(inclock_period, vco_period,
loop_iter, i_m, i_n);
if (((clk0_div * i_m) rem (clk0_mult * i_n) /= 0) or
((clk1_div * i_m) rem (clk1_mult * i_n) /= 0) or
((clk2_div * i_m) rem (clk2_mult * i_n) /= 0) or
((clk3_div * i_m) rem (clk3_mult * i_n) /= 0) or
((clk4_div * i_m) rem (clk4_mult * i_n) /= 0) or
((clk5_div * i_m) rem (clk5_mult * i_n) /= 0) or
((clk6_div * i_m) rem (clk6_mult * i_n) /= 0) or
((clk7_div * i_m) rem (clk7_mult * i_n) /= 0) or
((clk8_div * i_m) rem (clk8_mult * i_n) /= 0) or
((clk9_div * i_m) rem (clk9_mult * i_n) /= 0) )
then
if (loop_iter = 1)
then
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
else
m := i_pre_m;
n := i_pre_n;
end if;
i_max_iter := loop_iter;
else
m := i_m;
n := i_n;
end if;
pfd_freq := 1000000 / (inclock_period * i_n);
vco_freq := (1000000 * i_m) / (inclock_period * i_n);
vco_ps_step_value := (inclock_period * i_n) / (8 * i_m);
if ( (i_m < max_m) and (i_n < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) and
(abs(vco_ps_step_value - vco_phase_shift_step) <= 2) )
then
i_max_iter := loop_iter;
end if;
end loop;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif ((M9 <= 10) and (M9 >= 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable R: integer := 1;
begin
R := (clk_divide * M)/(clk_mult * N);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.5;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := (integer(real(tap_phase * m / n)+ 0.5) REM 360)/45;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_dffe : entity is TRUE;
end cycloneiii_dffe;
-- architecture body --
architecture behave of cycloneiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiii_mux21 : entity is TRUE;
end cycloneiii_mux21;
architecture AltVITAL of cycloneiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_mux41 : entity is TRUE;
end cycloneiii_mux41;
architecture AltVITAL of cycloneiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
-- entity declaration --
entity cycloneiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_and1 : entity is TRUE;
end cycloneiii_and1;
-- architecture body --
architecture AltVITAL of cycloneiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_lcell_comb : entity is TRUE;
end cycloneiii_lcell_comb;
architecture vital_lcell_comb of cycloneiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_routing_wire
--
-- Description : Cyclone III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_routing_wire : entity is TRUE;
end cycloneiii_routing_wire;
ARCHITECTURE behave of cycloneiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiii_mn_cntr;
ARCHITECTURE behave of cycloneiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiii_scale_cntr;
ARCHITECTURE behave of cycloneiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiii_pll_reg;
ARCHITECTURE behave of cycloneiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll
--
-- Description : Timing simulation model for the Cyclone III PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_pllpack.all;
USE work.cycloneiii_mn_cntr;
USE work.cycloneiii_scale_cntr;
USE work.cycloneiii_dffe;
USE work.cycloneiii_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := 0;
vco_range_detector_low_bits : integer := 0;
-- Simulation only generics
family_name : string := "Cyclone III";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '0';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiii_pll;
ARCHITECTURE vital_pll of cycloneiii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer;
signal i_vco_max : integer;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : std_logic_vector(14 to 16) := (OTHERS => '0');
signal cp_curr_val_bit_setting : std_logic_vector(14 to 16) := (OTHERS => '0');
signal lfr_old_bit_setting : std_logic_vector(3 to 7) := (OTHERS => '0');
signal lfr_val_bit_setting : std_logic_vector(3 to 7) := (OTHERS => '0');
signal lfc_old_bit_setting : std_logic_vector(1 to 2) := (OTHERS => '0');
signal lfc_val_bit_setting : std_logic_vector(1 to 2) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
COMPONENT cycloneiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if (input_value = '0') then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(cp_curr_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(lfc_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(lfr_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= cp_curr_val_bit_setting;
lfc_old_bit_setting <= lfc_val_bit_setting;
lfr_old_bit_setting <= lfr_val_bit_setting;
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
IF (NOT (((scan_data(4 TO 8) = "00000") OR (scan_data(4 TO 8) = "00100")) OR ((scan_data(4 TO 8) = "10000") OR (scan_data(4 TO 8) = "10100")) OR ((scan_data(4 TO 8) = "11000") OR (scan_data(4 TO 8) = "11011")) OR ((scan_data(4 TO 8) = "11100") OR (scan_data(4 TO 8) = "11110")))) THEN
WRITE(buf, string'("Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000 to 001111, 011000 to 011111, 101000 to 101111 and 111000 to 111111. Reconfiguration may not work."));
writeline(output,buf);
reconfig_err <= TRUE;
END IF;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF ((m_hi /= m_lo) AND (scan_data(18) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
END IF;
-- N counter value
IF ((n_hi /= n_lo) AND (scan_data(36) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
locked_tmp := '0';
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion.";
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion.";
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (vco_max /= 0 and vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_and1;
entity cycloneiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ff : entity is TRUE;
end cycloneiii_ff;
architecture vital_lcell_ff of cycloneiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '1')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiii_ram_register;
ARCHITECTURE reg_arch OF cycloneiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
-- REMCYCLONEIII PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiii_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiii_ram_pulse_generator IS
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_ram_register;
USE work.cycloneiii_ram_pulse_generator;
ENTITY cycloneiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiii_ram_block;
ARCHITECTURE block_arch OF cycloneiii_ram_block IS
COMPONENT cycloneiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init_std := to_stdlogicvector(mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0)((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiii_mac_data_reg;
ARCHITECTURE vital_cycloneiii_mac_data_reg OF cycloneiii_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd, data_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge,
SetupLow => tsetup_data_clk_noedge_posedge,
HoldHigh => thold_data_clk_noedge_posedge,
HoldLow => thold_data_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneiii_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiii_mac_sign_reg;
ARCHITECTURE cycloneiii_mac_sign_reg OF cycloneiii_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiii_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datab_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signb_dataout : VitalDelayType01 := DefPropDelay01;
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiii_mac_mult_internal;
ARCHITECTURE vital_cycloneiii_mac_mult_internal OF cycloneiii_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout, TRUE),
2 => (signa'last_event, tpd_signa_dataout, TRUE),
3 => (signb'last_event, tpd_signb_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneiii_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_mac_data_reg;
USE work.cycloneiii_mac_sign_reg;
USE work.cycloneiii_mac_mult_internal;
ENTITY cycloneiii_mac_mult IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_mult;
ARCHITECTURE vital_cycloneiii_mac_mult OF cycloneiii_mac_mult IS
COMPONENT cycloneiii_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiii_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiii_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datab_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signb_dataout : VitalDelayType01 := DefPropDelay01;
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneiii_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_out IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_out;
ARCHITECTURE vital_cycloneiii_mac_out OF cycloneiii_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout, use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
VITALtiming : process (clk_ipd, aclr_ipd, dataa_ipd)
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge,
SetupLow => tsetup_dataa_clk_noedge_posedge,
HoldHigh => thold_dataa_clk_noedge_posedge,
HoldLow => thold_dataa_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneiii_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_ibuf
--
-- Description : Cyclone III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiii_io_ibuf;
ARCHITECTURE arch OF cycloneiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_obuf
--
-- Description : Cyclone III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_io_obuf;
ARCHITECTURE arch OF cycloneiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_oe
--
-- Description : Cyclone III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.altera_primitives_components.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_oe;
ARCHITECTURE arch OF cycloneiii_ddio_oe IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_out
--
-- Description : Cyclone III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.altera_primitives_components.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_out;
ARCHITECTURE arch OF cycloneiii_ddio_out IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_lo : std_logic;
Signal sel_mux_lo_in : std_logic;
Signal sel_mux_select : std_logic;
signal clk1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
--DDIO OE Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
mux_sel <= clk1;
mux_lo <= dfflo_tmp;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_select <= mux_sel;
sel_mux : cycloneiii_mux21
port map (
A => sel_mux_lo_in,
B => dffhi_tmp,
S => sel_mux_select,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_io_pad
-- Description : Simulation model for cycloneiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_io_pad IS
GENERIC (
lpm_type : string := "cycloneiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiii_io_pad;
ARCHITECTURE arch OF cycloneiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ena_reg : entity is TRUE;
end cycloneiii_ena_reg;
ARCHITECTURE behave of cycloneiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_ena_reg;
entity cycloneiii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_clkctrl : entity is TRUE;
end cycloneiii_clkctrl;
architecture vital_clkctrl of cycloneiii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk <= ena_out AND clkmux_out;
end vital_clkctrl;
--
--
-- CYCLONEIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiii_rublock;
architecture architecture_rublock of cycloneiii_rublock is
begin
end architecture_rublock;
--
--
-- CYCLONEIII_APFCONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_apfcontroller is
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end cycloneiii_apfcontroller;
architecture architecture_apfcontroller of cycloneiii_apfcontroller is
begin
end architecture_apfcontroller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_termination
--
-- Description : Cyclone III Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiii_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiii_termination;
ARCHITECTURE cycloneiii_termination_arch OF cycloneiii_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiii_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_jtag
--
-- Description : Cyclone III JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_jtag is
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiii_jtag;
architecture architecture_jtag of cycloneiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_crcblock
--
-- Description : Cyclone III CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
ldsrc : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
end cycloneiii_crcblock;
architecture architecture_crcblock of cycloneiii_crcblock is
begin
end architecture_crcblock;
--
--
-- CYCLONEIII_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_oscillator is
generic
(
lpm_type: string := "cycloneiii_oscillator"
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end cycloneiii_oscillator;
architecture architecture_oscillator of cycloneiii_oscillator is
begin
end architecture_oscillator;
| mit |
christakissgeo/Matrix-Vector-Multiplication | VHDL Files/project2.vhd | 1 | 11178 | -- Project 2
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
------------------------------------
entity project2 is
port (
clock : in std_logic;
reset : in std_logic;
valid : in std_logic;
hold_me : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (18 downto 0);
hold_prev : out std_logic
);
end entity project2;
-------------------------------------
architecture project_2 of project2 is
-------------counter address generator----------------
component counter_address_generator is
port (
clock : in std_logic;
reset : in std_logic;
need_to_reset : in std_logic;
enable : in std_logic;
read_enable : in std_logic;
address : out std_logic_vector (7 downto 0)
);
end component;
-------------ramA----------------
component ramA is
port(
clock : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
address : in std_logic_vector (2 downto 0);
datain : in std_logic_vector (7 downto 0);
dataout : out std_logic_vector (7 downto 0)
);
end component;
-------------ramR----------------
component ramR is
port(
clock : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
address : in std_logic_vector (2 downto 0);
datain : in std_logic_vector (18 downto 0);
dataout : out std_logic_vector (18 downto 0)
);
end component;
-------------rom-----------------
component rom is
port (
clock : in std_logic;
address : in std_logic_vector (5 downto 0);
rom_enable : in std_logic;
data : out std_logic_vector (7 downto 0)
);
end component;
-------------fsm-----------------
component fsm
port (
clock : in std_logic;
reset : in std_logic;
ramA_address : in std_logic_vector (4 downto 0);
ramR_address : in std_logic_vector (7 downto 0);
rom_address : in std_logic_vector (7 downto 0);
hold_me : in std_logic;
ramR_readEnable : out std_logic;
ramA_writeEnable : out std_logic;
ramA_readEnable : out std_logic;
ramR_writeEnable : out std_logic;
rom_enable : out std_logic;
counterAddressGen_H_enable : out std_logic;
counterAddressGen_R_enable : out std_logic;
counterAddressGen_A_restart : out std_logic;
counterAddressGen_R_restart : out std_logic;
counterAddressGen_H_restart : out std_logic;
mac_clean : out std_logic;
reset_fsm : out std_logic;
hold_prev : out std_logic
);
end component fsm;
-------------mac-----------------
component mac is
port (
clock : in std_logic;
ai : in std_logic_vector(7 downto 0);
xi : in std_logic_vector(7 downto 0);
mac_clean : in std_logic;
data_out : out std_logic_vector (18 downto 0)
);
end component;
-------------------------------------
signal Ai : std_logic_vector (7 downto 0);
signal Hi : std_logic_vector (7 downto 0);
signal Ri : std_logic_vector (18 downto 0);
signal addressA : std_logic_vector (7 downto 0);
signal addressH : std_logic_vector (7 downto 0);
signal addressR : std_logic_vector (7 downto 0);
signal CAG_A_restart : std_logic;
signal CAG_H_restart : std_logic;
signal CAG_R_restart : std_logic;
signal ramA_write_enable : std_logic;
signal ramA_read_enable : std_logic;
signal ramR_write_enable : std_logic;
signal ramR_read_enable : std_logic;
signal romH_enable : std_logic;
signal clear_register : std_logic;
signal CAG_H_enable : std_logic;
signal CAG_R_enable : std_logic;
signal reset_fsm : std_logic;
begin
counterAddressGenA : counter_address_generator port map ( clock => clock,
reset => reset_fsm,
need_to_reset => CAG_A_restart,
enable => valid,
read_enable => ramA_read_enable,
address => addressA
);
-------------------------------
RAMA_UNIT : ramA port map ( clock => clock,
write_enable => ramA_write_enable,
read_enable => ramA_read_enable,
address => addressA(2 downto 0),
datain => data_in,
dataout => Ai
);
-------------------------------
counterAddressGenH : counter_address_generator port map ( clock => clock,
reset => reset_fsm,
need_to_reset => CAG_H_restart,
enable => CAG_H_enable,
read_enable => CAG_H_enable,
address => addressH
);
--------------------------------
ROMH : rom port map ( clock => clock,
address => addressH(5 downto 0),
rom_enable => romH_enable,
data => Hi
);
--------------------------------
MAC_UNIT : mac port map ( clock => clock,
ai => Ai,
xi => Hi,
mac_clean => clear_register,
data_out => Ri
);
---------------------------------
FSM_UNIT : fsm port map ( clock => clock,
reset => reset,
ramA_address => addressA(7 downto 3),
ramR_address => addressR,
rom_address => addressH,
hold_me => hold_me,
ramR_readEnable => ramR_read_enable,
ramA_writeEnable => ramA_write_enable,
ramA_readEnable => ramA_read_enable,
ramR_writeEnable => ramR_write_enable,
rom_enable => romH_enable,
counterAddressGen_H_enable => CAG_H_enable,
counterAddressGen_R_enable => CAG_R_enable,
counterAddressGen_A_restart => CAG_A_restart,
counterAddressGen_R_restart => CAG_R_restart,
counterAddressGen_H_restart => CAG_H_restart,
mac_clean => clear_register,
reset_fsm => reset_fsm,
hold_prev => hold_prev
);
---------------------------------
counterAddressGenR : counter_address_generator port map ( clock => clock,
reset => reset_fsm,
need_to_reset => CAG_R_restart,
enable => CAG_R_enable,
read_enable => ramR_read_enable,
address => addressR
);
----------------------------------
RAMR_UNIT : ramR port map ( clock => clock,
write_enable => ramR_write_enable,
read_enable => ramR_read_enable,
address => addressR(2 downto 0),
datain => Ri,
dataout => data_out
);
end architecture project_2;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/ata/ocidec2_amba_slave.vhd | 2 | 14461 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ocidec2_amba_slave
-- File: ocidec2_amba_slave.vhd
-- Author: Nils-Johan Wessman, Gaisler Research
-- Description: ATA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity ocidec2_amba_slave is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
DeviceID : integer := 0;
RevisionNo : integer := 0;
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
cf_power: out std_logic;
-- ata controller signals
-- PIO control input
PIOsel : out std_logic;
PIOtip, -- PIO transfer in progress
PIOack : in std_logic; -- PIO acknowledge signal
PIOq : in std_logic_vector(15 downto 0); -- PIO data input
PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
irq : in std_logic; -- interrupt signal input
PIOa : out std_logic_vector(3 downto 0);
PIOd : out std_logic_vector(15 downto 0);
PIOwe : out std_logic;
-- DMA control inputs
DMAsel : out std_logic;
DMAtip, -- DMA transfer in progress
DMAack, -- DMA transfer acknowledge
DMARxEmpty, -- DMA receive buffer empty
DMATxFull, -- DMA transmit buffer full
DMA_dmarq : in std_logic; -- wishbone DMA request
DMAq : in std_logic_vector(31 downto 0);
-- outputs
-- control register outputs
IDEctrl_rst,
IDEctrl_IDEen,
IDEctrl_FATR1,
IDEctrl_FATR0,
IDEctrl_ppen,
DMActrl_DMAen,
DMActrl_dir,
DMActrl_BeLeC0,
DMActrl_BeLeC1 : out std_logic;
-- CMD port timing registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : out std_logic_vector(7 downto 0);
PIO_cmdport_IORDYen : out std_logic;
-- data-port0 timing registers
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : out std_logic_vector(7 downto 0);
PIO_dport0_IORDYen : out std_logic;
-- data-port1 timing registers
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : out std_logic_vector(7 downto 0);
PIO_dport1_IORDYen : out std_logic;
-- DMA device0 timing registers
DMA_dev0_Tm,
DMA_dev0_Td,
DMA_dev0_Teoc : out std_logic_vector(7 downto 0);
-- DMA device1 timing registers
DMA_dev1_Tm,
DMA_dev1_Td,
DMA_dev1_Teoc : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of ocidec2_amba_slave is
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_ATACTRL, 0, VERSION, pirq),
4 => ahb_iobar(haddr, hmask),
others => zero32);
type PIOtiming_type is record
T1,T2,T4,Teoc : std_logic_vector(7 downto 0);
end record;
type DMAtiming_type is record
Tm,Td,Teoc : std_logic_vector(7 downto 0);
end record;
-- local registers
type reg_type is record
-- AHB signal
hready : std_ulogic; -- Hready
hsel : std_ulogic; -- Hsel
hmbsel : std_logic_vector(0 to 2); -- Mem map select
haddr : std_logic_vector(31 downto 0); -- Haddr
hrdata : std_logic_vector(31 downto 0); -- Hreaddata
hwdata : std_logic_vector(31 downto 0); -- Hwritedata
hwrite : std_ulogic; -- Hwrite
htrans : std_logic_vector(1 downto 0); -- Htrans type
hburst : std_logic_vector(2 downto 0); -- Hburst type
hresp : std_logic_vector(1 downto 0); -- Hresp type
size : std_logic_vector(1 downto 0); -- Part of Hsize
piosel : std_logic;
irq : std_logic;
irqv : std_logic_vector(NAHBIRQ-1 downto 0);
pioack : std_logic;
atasel : std_logic;
-- reg signal
ctrlreg : std_logic_vector(31 downto 0);
statreg : std_logic_vector(31 downto 0);
pio_cmd : PIOtiming_type;
pio_dp0 : PIOtiming_type;
pio_dp1 : PIOtiming_type;
dma_dev0 : DMAtiming_type;
dma_dev1 : DMAtiming_type;
end record;
signal r, ri : reg_type;
begin
ctrl : process(rst, ahbsi, r, PIOack, PIOtip, PIOpp_full, irq, PIOq,
DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq)
variable v : reg_type; -- local variables for registers
variable int : std_logic;
begin
-- Variable default settings to avoid latches
v := r;
v.hresp := HRESP_OKAY;
v.irqv := (others => '0');
int := '1';
v.irq := irq;
v.irqv(pirq) := v.irq and not r.irq;
v.pioack := PIOack;
if (ahbsi.hready = '1') and (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.size := ahbsi.hsize(1 downto 0);
v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
v.hburst := ahbsi.hburst;
v.hsel := '1';
v.haddr := ahbsi.haddr;
v.piosel := ahbsi.haddr(6);
v.atasel := ahbsi.haddr(6);
if ahbsi.hwrite = '0' or ahbsi.haddr(6) = '1' then -- Read or ATA
v.hready := '0';
else -- Write
v.hready := '1';
end if;
else
v.hsel := '0';
if PIOack = '1' then
v.piosel := '0';
end if;
v.hready := r.pioack or not r.atasel;
if r.pioack = '1' then
v.atasel := '0';
end if;
end if;
if r.hsel = '1' and r.atasel = '0' and r.hwrite = '1' then -- Write
case r.haddr(5 downto 2) is
when "0000" => -- Control register 0x0
v.ctrlreg := ahbsi.hwdata;
when "0001" => -- Status register 0x4
int := ahbsi.hwdata(0); -- irq bit in status reg
when "0010" => -- PIO Compatible timing register 0x8
v.pio_cmd.T1 := ahbsi.hwdata(7 downto 0);
v.pio_cmd.T2 := ahbsi.hwdata(15 downto 8);
v.pio_cmd.T4 := ahbsi.hwdata(23 downto 16);
v.pio_cmd.Teoc := ahbsi.hwdata(31 downto 24);
when "0011" => -- PIO Fast timing register device 0 0xc
v.pio_dp0.T1 := ahbsi.hwdata(7 downto 0);
v.pio_dp0.T2 := ahbsi.hwdata(15 downto 8);
v.pio_dp0.T4 := ahbsi.hwdata(23 downto 16);
v.pio_dp0.Teoc := ahbsi.hwdata(31 downto 24);
when "0100" => -- PIO Fast timing register device 1 0x10
v.pio_dp1.T1 := ahbsi.hwdata(7 downto 0);
v.pio_dp1.T2 := ahbsi.hwdata(15 downto 8);
v.pio_dp1.T4 := ahbsi.hwdata(23 downto 16);
v.pio_dp1.Teoc := ahbsi.hwdata(31 downto 24);
when "0101" => -- DMA timing register device 0 0x14
v.dma_dev0.Tm := ahbsi.hwdata(7 downto 0);
v.dma_dev0.Td := ahbsi.hwdata(15 downto 8);
v.dma_dev0.Teoc := ahbsi.hwdata(31 downto 24);
when "0110" => -- DMA timing register device 1 0x18
v.dma_dev1.Tm := ahbsi.hwdata(7 downto 0);
v.dma_dev1.Td := ahbsi.hwdata(15 downto 8);
v.dma_dev1.Teoc := ahbsi.hwdata(31 downto 24);
when others => null;
end case;
elsif r.hsel = '1' and r.atasel = '1' and r.hwrite = '1' then -- ATA IO device 0x40-
v.hwdata := ahbsi.hwdata;
end if;
if r.hsel = '1' and r.atasel = '0' and r.hwrite = '0' then -- Read
case r.haddr(5 downto 2) is
when "0000" => -- Control register 0x0
v.hrdata := r.ctrlreg;
when "0001" => -- Status register 0x4
v.hrdata := r.statreg;
when "0010" => -- PIO Compatible timing register 0x8
v.hrdata := (r.pio_cmd.Teoc & r.pio_cmd.T4 & r.pio_cmd.T2 &
r.pio_cmd.T1);
when "0011" => -- PIO Fast timing register device 0 0xc
v.hrdata := (r.pio_dp0.Teoc & r.pio_dp0.T4 & r.pio_dp0.T2 &
r.pio_dp0.T1);
when "0100" => -- PIO Fast timing register device 1 0x10
v.hrdata := (r.pio_dp1.Teoc & r.pio_dp1.T4 & r.pio_dp1.T2 &
r.pio_dp1.T1);
when "0101" => -- DMA timing register device 0 0x14
v.hrdata := (r.dma_dev0.Teoc & x"00" & r.dma_dev0.Td &
r.dma_dev0.Tm);
when "0110" => -- DMA timing register device 1 0x18
v.hrdata := (r.dma_dev1.Teoc & x"00" & r.dma_dev1.Td &
r.dma_dev1.Tm);
when others =>
v.hrdata := x"aaaaaaaa";
end case;
elsif r.atasel = '1' then -- ATA IO device 0x40-
v.hrdata := (x"0000" & PIOq);
end if;
-- Status register
v.statreg(31 downto 0) := (others => '0'); -- clear all bits (read unused bits as '0')
v.statreg(31 downto 28) := std_logic_vector(to_unsigned(DeviceId,4)); -- set Device ID
v.statreg(27 downto 24) := std_logic_vector(to_unsigned(RevisionNo,4)); -- set revision number
v.statreg(15) := DMAtip;
v.statreg(10) := DMARxEmpty;
v.statreg(9) := DMATxFull;
v.statreg(8) := DMA_dmarq;
v.statreg(7) := PIOtip;
v.statreg(6) := PIOpp_full;
v.statreg(0) := (r.statreg(0) or (v.irq and not r.irq)) and int;
-- reset
if rst = '0' then
v.ctrlreg := (0 => '1', others => '0');
v.statreg(0) := '0';
v.haddr := (others => '0');
v.hwrite := '0';
v.hready := '1';
v.pioack := '0';
v.atasel := '0';
v.piosel := '0';
v.pio_cmd.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
v.pio_cmd.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
v.pio_cmd.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
v.pio_cmd.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
v.pio_dp0.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
v.pio_dp0.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
v.pio_dp0.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
v.pio_dp0.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
v.pio_dp1.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
v.pio_dp1.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
v.pio_dp1.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
v.pio_dp1.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
v.dma_dev0.Tm := conv_std_logic_vector(DMA_mode0_Tm,8);
v.dma_dev0.Td := conv_std_logic_vector(DMA_mode0_Td,8);
v.dma_dev0.Teoc := conv_std_logic_vector(DMA_mode0_Teoc,8);
v.dma_dev1.Tm := conv_std_logic_vector(DMA_mode0_Tm,8);
v.dma_dev1.Td := conv_std_logic_vector(DMA_mode0_Td,8);
v.dma_dev1.Teoc := conv_std_logic_vector(DMA_mode0_Teoc,8);
end if;
-- assign control bits
cf_power <= r.ctrlreg(31);
DMActrl_DMAen <= r.ctrlreg(15);
DMActrl_dir <= r.ctrlreg(13);
DMActrl_BeLeC1 <= r.ctrlreg(9);
DMActrl_BeLeC0 <= r.ctrlreg(8);
IDEctrl_IDEen <= r.ctrlreg(7);
IDEctrl_FATR1 <= r.ctrlreg(6);
IDEctrl_FATR0 <= r.ctrlreg(5);
IDEctrl_ppen <= r.ctrlreg(4);
PIO_dport1_IORDYen <= r.ctrlreg(3);
PIO_dport0_IORDYen <= r.ctrlreg(2);
PIO_cmdport_IORDYen <= r.ctrlreg(1);
IDEctrl_rst <= r.ctrlreg(0);
-- CMD port timing
PIO_cmdport_T1 <= r.pio_cmd.T1; PIO_cmdport_T2 <= r.pio_cmd.T2;
PIO_cmdport_T4 <= r.pio_cmd.T4; PIO_cmdport_Teoc <= r.pio_cmd.Teoc;
-- data-port0 timing
PIO_dport0_T1 <= r.pio_dp0.T1; PIO_dport0_T2 <= r.pio_dp0.T2;
PIO_dport0_T4 <= r.pio_dp0.T4; PIO_dport0_Teoc <= r.pio_dp0.Teoc;
-- data-port1 timing
PIO_dport1_T1 <= r.pio_dp1.T1; PIO_dport1_T2 <= r.pio_dp1.T2;
PIO_dport1_T4 <= r.pio_dp1.T4; PIO_dport1_Teoc <= r.pio_dp1.Teoc;
-- DMA device0 timing
DMA_dev0_Tm <= r.dma_dev0.Tm; DMA_dev0_Td <= r.dma_dev0.Td;
DMA_dev0_Teoc <= r.dma_dev0.Teoc;
-- DMA device1 timing
DMA_dev1_Tm <= r.dma_dev0.Tm; DMA_dev1_Td <= r.dma_dev0.Td;
DMA_dev1_Teoc <= r.dma_dev0.Teoc;
ri <= v;
PIOa <= r.haddr(5 downto 2);
PIOd <= r.hwdata(15 downto 0);
PIOsel <= r.piosel;
PIOwe <= r.hwrite;
DMAsel <= '0'; -- temp ***
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hcache <= '0';
ahbso.hirq <= r.irqv;
ahbso.hindex <= hindex;
end process;
regs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri;
end if;
if rst = '0' then
end if;
end process;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/opencores/can/can_top_core_sync.vhd | 2 | 157516 | ----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_btl_core_sync
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_btl_core_sync.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_btl_core_sync.v,v $
-- Revision 1.30 2004/10/27 18:51:37 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.29 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.28 2004/02/08 14:25:26 mohor
-- Header changed.
--
-- Revision 1.27 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.26 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.25 2003/07/16 13:40:35 mohor
-- Fixed according to the linter.
--
-- Revision 1.24 2003/07/10 15:32:28 mohor
-- Unused signal removed.
--
-- Revision 1.23 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.22 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.21 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.20 2003/06/20 14:51:11 mohor
-- Previous change removed. When resynchronization occurs we go to seg1
-- stage. sync stage does not cause another start of seg1 stage.
--
-- Revision 1.19 2003/06/20 14:28:20 mohor
-- When hard_sync or resync occure we need to go to seg1 segment. Going to
-- sync segment is in that case blocked.
--
-- Revision 1.18 2003/06/17 15:53:33 mohor
-- clk_cnt reduced from [8:0] to [6:0].
--
-- Revision 1.17 2003/06/17 14:32:17 mohor
-- Removed few signals.
--
-- Revision 1.16 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.15 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.14 2003/06/13 14:55:11 mohor
-- Counters width changed.
--
-- Revision 1.13 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.12 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.11 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.10 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.9 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.8 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.6 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.5 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.4 2002/12/26 01:33:05 mohor
-- Tripple sampling supported.
--
-- Revision 1.3 2002/12/25 23:44:16 mohor
-- Commented lines removed.
--
-- Revision 1.2 2002/12/25 14:17:00 mohor
-- Synchronization working.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_btl_core_sync IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
-- Bus Timing 0 register
baud_r_presc : IN std_logic_vector(10 DOWNTO 0); --##
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
-- Output signals from this module
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
-- Output from can_bsp_core_sync module
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END ENTITY can_btl_core_sync;
ARCHITECTURE RTL OF can_btl_core_sync IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL clk_cnt : std_logic_vector(10 DOWNTO 0); --##
SIGNAL clk_en : std_logic;
SIGNAL clk_en_q : std_logic;
SIGNAL sync_blocked : std_logic;
SIGNAL hard_sync_blocked : std_logic;
SIGNAL quant_cnt : std_logic_vector(4 DOWNTO 0);
SIGNAL delay : std_logic_vector(3 DOWNTO 0);
SIGNAL sync : std_logic;
SIGNAL seg1 : std_logic;
SIGNAL seg2 : std_logic;
SIGNAL resync_latched : std_logic;
SIGNAL sample : std_logic_vector(1 DOWNTO 0);
SIGNAL tx_next_sp : std_logic;
SIGNAL go_sync : std_logic;
SIGNAL go_seg1 : std_logic;
SIGNAL go_seg2 : std_logic;
SIGNAL preset_cnt : std_logic_vector(10 DOWNTO 0); --##
SIGNAL sync_window : std_logic;
SIGNAL resync : std_logic;
-- when transmitting 0 with positive error delay is set to 0
SIGNAL temp_xhdl6 : std_logic_vector(4 DOWNTO 0);
SIGNAL sample_point_xhdl1 : std_logic;
SIGNAL sampled_bit_xhdl2 : std_logic;
SIGNAL sampled_bit_q_xhdl3 : std_logic;
SIGNAL tx_point_xhdl4 : std_logic;
SIGNAL hard_sync_xhdl5 : std_logic;
signal time_segment1_ext, delay_ext, add_ext: std_logic_vector(4 DOWNTO 0); --##
BEGIN
sample_point <= sample_point_xhdl1;
sampled_bit <= sampled_bit_xhdl2;
sampled_bit_q <= sampled_bit_q_xhdl3;
tx_point <= tx_point_xhdl4;
hard_sync <= hard_sync_xhdl5;
-- preset_cnt <= (('0' & baud_r_presc) + 1) & "0" ;
--## preset_cnt <= "00" & baud_r_presc + '1';
preset_cnt <= baud_r_presc; --## --## extend scaler
hard_sync_xhdl5 <= (((rx_idle OR rx_inter) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT hard_sync_blocked) ;
resync <= ((((NOT rx_idle) AND (NOT rx_inter)) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT sync_blocked) ;
-- Generating general enable signal that defines baud rate.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- clk_cnt <= "0000000";
IF (clk'EVENT AND clk = '1') THEN
IF (rst = '1') THEN
clk_cnt <= (others => '0'); --##
ELSIF (clk_cnt >= preset_cnt) then --##
clk_cnt <= (others => '0'); --##
ELSE
clk_cnt <= clk_cnt + '1' ; --##
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- clk_en <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (rst = '1') THEN
clk_en <= '0';
ELSIF (clk_cnt = preset_cnt) then --##
clk_en <= '1' ;
ELSE
clk_en <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- clk_en_q <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (rst = '1') THEN
clk_en_q <= '0';
ELSE
clk_en_q <= clk_en ;
END IF;
END IF;
END PROCESS;
-- Changing states
go_sync <= (((clk_en_q AND seg2) AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) AND (NOT hard_sync_xhdl5)) AND (NOT resync) ;
go_seg1 <= clk_en_q AND (sync OR hard_sync_xhdl5 OR ((resync AND seg2) AND sync_window) OR (resync_latched AND sync_window)) ;
time_segment1_ext <= '0' & time_segment1; --## fix comparison for max values
delay_ext <= '0' & delay; --##
add_ext <= time_segment1_ext + delay_ext; --##
go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = add_ext)) ;--##
--## go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = ( '0' & (time_segment1 + delay)))) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_point_xhdl4 <= '0';
IF (clk'EVENT AND clk = '1') THEN
tx_point_xhdl4 <= (NOT tx_point_xhdl4 AND seg2) AND ((clk_en AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) OR ((clk_en OR clk_en_q) AND (resync OR hard_sync_xhdl5))) ; -- When transmitter we should transmit as soon as possible.
IF (rst = '1') THEN
tx_point_xhdl4 <= '0';
END IF;
END IF;
END PROCESS;
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- SJW is reached
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- resync_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg2) AND (NOT sync_window)) = '1') THEN
resync_latched <= '1' ;
ELSE
IF (go_seg1 = '1') THEN
resync_latched <= '0';
END IF;
END IF;
IF (rst = '1') THEN
resync_latched <= '0';
END IF;
END IF;
END PROCESS;
-- Synchronization stage/segment
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- sync <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sync <= go_sync ;
END IF;
IF (rst = '1') THEN
sync <= '0';
END IF;
END IF;
END PROCESS;
-- Seg1 stage/segment (together with propagation segment which is 1 quant long)
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- seg1 <= '1';
IF (clk'EVENT AND clk = '1') THEN
IF (go_seg1 = '1') THEN
seg1 <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
seg1 <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
seg1 <= '1';
END IF;
END IF;
END PROCESS;
-- Seg2 stage/segment
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- seg2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (go_seg2 = '1') THEN
seg2 <= '1' ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
seg2 <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
seg2 <= '0';
END IF;
END IF;
END PROCESS;
-- Quant counter
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- quant_cnt <= "00000";
IF (clk'EVENT AND clk = '1') THEN
IF ((go_sync OR go_seg1 OR go_seg2) = '1') THEN
quant_cnt <= "00000" ;
ELSE
IF (clk_en_q = '1') THEN
quant_cnt <= quant_cnt + "00001" ;
END IF;
END IF;
IF (rst = '1') THEN
quant_cnt <= "00000";
END IF;
END IF;
END PROCESS;
temp_xhdl6 <= ("0" & ("00" & sync_jump_width + "0001")) WHEN (quant_cnt > "000" & sync_jump_width) ELSE (quant_cnt + "00001");
-- When late edge is detected (in seg1 stage), stage seg1 is prolonged.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- delay <= "0000";
IF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg1) AND (NOT transmitting OR (transmitting AND (tx_next_sp OR (tx AND (NOT rx)))))) = '1') THEN
delay <= temp_xhdl6(3 DOWNTO 0) ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
delay <= "0000" ;
END IF;
END IF;
IF (rst = '1') THEN
delay <= "0000";
END IF;
END IF;
END PROCESS;
-- If early edge appears within this window (in seg2 stage), phase error is fully compensated
sync_window <= CONV_STD_LOGIC((time_segment2 - quant_cnt(2 DOWNTO 0)) < ('0' & (sync_jump_width + "01"))) ;
-- Sampling data (memorizing two samples all the time).
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- sample <= "11";
IF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sample <= sample(0) & rx;
END IF;
IF (rst = '1') THEN
sample <= "11";
END IF;
END IF;
END PROCESS;
-- When enabled, tripple sampling is done here.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- sampled_bit_xhdl2 <= '1';
-- sampled_bit_q_xhdl3 <= '1';
-- sample_point_xhdl1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame = '1') THEN
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
sample_point_xhdl1 <= '0' ;
ELSE
IF ((clk_en_q AND (NOT hard_sync_xhdl5)) = '1') THEN
--## IF ((seg1 AND CONV_STD_LOGIC(quant_cnt = ('0' & (time_segment1 + delay)))) = '1') THEN
IF ((seg1 AND CONV_STD_LOGIC(quant_cnt = add_ext )) = '1') then --##
sample_point_xhdl1 <= '1' ;
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
IF (triple_sampling = '1') THEN
sampled_bit_xhdl2 <= (sample(0) AND sample(1)) OR (sample(0) AND rx) OR (sample(1) AND rx) ;
ELSE
sampled_bit_xhdl2 <= rx ;
END IF;
-- kc fix
ELSE
sample_point_xhdl1 <= '0' ;
--
END IF;
ELSE
sample_point_xhdl1 <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
sampled_bit_xhdl2 <= '1';
sampled_bit_q_xhdl3 <= '1';
sample_point_xhdl1 <= '0';
END IF;
END IF;
END PROCESS;
-- tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
-- need to synchronize (even when we are a transmitter)
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_next_sp <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((go_overload_frame OR (go_error_frame AND (NOT node_error_passive)) OR go_tx OR send_ack) = '1') THEN
tx_next_sp <= '0' ;
ELSE
IF ((go_error_frame AND node_error_passive) = '1') THEN
tx_next_sp <= '1' ;
ELSE
IF (sample_point_xhdl1 = '1') THEN
tx_next_sp <= tx_next ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
tx_next_sp <= '0';
END IF;
END IF;
END PROCESS;
-- Blocking synchronization (can occur only once in a bit time)
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- sync_blocked <= '1' ;
IF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
IF (resync = '1') THEN
sync_blocked <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
sync_blocked <= '0' ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
sync_blocked <= '1' ;
END IF;
END IF;
END PROCESS;
-- Blocking hard synchronization when occurs once or when we are transmitting a msg
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- hard_sync_blocked <= '0' ;
IF (clk'EVENT AND clk = '1') THEN
IF (((hard_sync_xhdl5 AND clk_en_q) OR ((((transmitting AND transmitter) OR go_tx) AND tx_point_xhdl4) AND (NOT tx_next))) = '1') THEN
hard_sync_blocked <= '1' ;
ELSE
IF ((go_rx_inter OR (((rx_idle OR rx_inter) AND sample_point_xhdl1) AND sampled_bit_xhdl2)) = '1') THEN
-- When a glitch performed synchronization
hard_sync_blocked <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
hard_sync_blocked <= '0' ;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_crc_core_sync
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_crc_core_sync.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_crc_core_sync.v,v $
-- Revision 1.5 2004/02/08 14:25:57 mohor
-- Header changed.
--
-- Revision 1.4 2003/07/16 13:16:51 mohor
-- Fixed according to the linter.
--
-- Revision 1.3 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/01/08 02:10:54 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_crc_core_sync IS
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END ENTITY can_crc_core_sync;
ARCHITECTURE RTL OF can_crc_core_sync IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL crc_next : std_logic;
SIGNAL crc_tmp : std_logic_vector(14 DOWNTO 0);
SIGNAL crc_xhdl1 : std_logic_vector(14 DOWNTO 0);
BEGIN
crc <= crc_xhdl1;
crc_next <= data XOR crc_xhdl1(14) ;
crc_tmp <= crc_xhdl1(13 DOWNTO 0) & '0' ;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (initialize = '1') THEN
crc_xhdl1 <= "000000000000000";
ELSE
IF (enable = '1') THEN
IF (crc_next = '1') THEN
crc_xhdl1 <= crc_tmp XOR "100010110011001";
ELSE
crc_xhdl1 <= crc_tmp ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_ibo_core_sync
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_ibo_core_sync.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_ibo_core_sync.v,v $
-- Revision 1.3 2004/02/08 14:31:44 mohor
-- Header changed.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
-- This module only inverts bit order
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_ibo_core_sync IS
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_ibo_core_sync;
ARCHITECTURE RTL OF can_ibo_core_sync IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL do_xhdl1 : std_logic_vector(7 DOWNTO 0);
BEGIN
do <= do_xhdl1;
do_xhdl1(0) <= di(7) ;
do_xhdl1(1) <= di(6) ;
do_xhdl1(2) <= di(5) ;
do_xhdl1(3) <= di(4) ;
do_xhdl1(4) <= di(3) ;
do_xhdl1(5) <= di(2) ;
do_xhdl1(6) <= di(1) ;
do_xhdl1(7) <= di(0) ;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_bsp_core_sync
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_bsp_core_sync.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_bsp_core_sync.v,v $
-- Revision 1.52 2004/11/18 12:39:21 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.51 2004/11/15 18:23:21 igorm
-- When CAN was reset by setting the reset_mode signal in mode register, it
-- was possible that CAN was blocked for a short period of time. Problem
-- occured very rarly.
--
-- Revision 1.50 2004/10/27 18:51:36 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.49 2004/10/25 06:37:51 igorm
-- Arbitration bug fixed.
--
-- Revision 1.48 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.47 2004/02/08 14:24:10 mohor
-- Error counters changed.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 21:14:33 mohor
-- Error counters changed.
--
-- Revision 1.44 2003/09/30 00:55:12 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.43 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.42 2003/08/29 07:01:14 mohor
-- When detecting bus-free, signal bus_free_cnt_en was cleared to zero
-- although the last sampled bit was zero instead of one.
--
-- Revision 1.41 2003/07/18 15:23:31 tadejm
-- Tx and rx length are limited to 8 bytes regardless to the DLC value.
--
-- Revision 1.40 2003/07/16 15:10:17 mohor
-- Fixed according to the linter.
--
-- Revision 1.39 2003/07/16 13:12:46 mohor
-- Fixed according to the linter.
--
-- Revision 1.38 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.37 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.36 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.35 2003/06/27 20:56:12 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.34 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.33 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.32 2003/06/17 14:28:32 mohor
-- Form error was detected when stuff bit occured at the end of crc.
--
-- Revision 1.31 2003/06/16 14:31:29 tadejm
-- Bit stuffing corrected when stuffing comes at the end of the crc.
--
-- Revision 1.30 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.29 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.28 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.27 2003/02/20 00:26:02 mohor
-- When a dominant bit was detected at the third bit of the intermission and
-- node had a message to transmit, bit_stuff error could occur. Fixed.
--
-- Revision 1.26 2003/02/19 23:21:54 mohor
-- When bit error occured while active error flag was transmitted, counter was
-- not incremented.
--
-- Revision 1.25 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.24 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.23 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.22 2003/02/12 14:23:59 mohor
-- abort_tx added. Bit destuff fixed.
--
-- Revision 1.21 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.20 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.19 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.18 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.17 2003/02/04 17:24:41 mohor
-- Backup.
--
-- Revision 1.16 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.15 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.14 2003/01/16 13:36:19 mohor
-- Form error supported. When receiving messages, last bit of the end-of-frame
-- does not generate form error. Receiver goes to the idle mode one bit sooner.
-- (CAN specification ver 2.0, part B, page 57).
--
-- Revision 1.13 2003/01/15 21:59:45 mohor
-- Data is stored to fifo at the end of ack stage.
--
-- Revision 1.12 2003/01/15 21:05:11 mohor
-- CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
--
-- Revision 1.11 2003/01/15 14:40:23 mohor
-- RX state machine fixed to receive "remote request" frames correctly.
-- No data bytes are written to fifo when such frames are received.
--
-- Revision 1.10 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.9 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.8 2003/01/10 17:51:33 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.6 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.5 2003/01/08 13:30:31 mohor
-- Temp version.
--
-- Revision 1.4 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_bsp_core_sync IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
restart : in std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
self_test_mode : IN std_logic;
-- Command register
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic; -- When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
overload_frame : OUT std_logic; -- be send in a row. This is not implemented, yet, because host can not send an overload request.
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: IN std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
-- Error Warning Limit register
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
node_bus_off : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
rcv_msg_data : out std_logic_vector(63 downto 0);
rcv_id : out std_logic_vector(28 downto 0);
rcv_dlc : out std_logic_vector(3 downto 0);
rcv_rtr : out std_logic;
rcv_ide : out std_logic;
rcv_msg_valid : out std_logic;
form_error : out std_logic;
crc_error : out std_logic;
ack_error : out std_logic;
stuff_error : out std_logic;
bit_error : out std_logic;
arb_loss : out std_logic;
tx : OUT std_logic;
tx_next : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic);
END ENTITY can_bsp_core_sync;
ARCHITECTURE RTL OF can_bsp_core_sync IS
COMPONENT can_crc_core_sync
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END COMPONENT;
COMPONENT can_ibo_core_sync
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
------------------------------
SIGNAL reset_mode_q : std_logic;
SIGNAL bit_cnt : std_logic_vector(5 DOWNTO 0);
SIGNAL data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL id : std_logic_vector(28 DOWNTO 0);
SIGNAL bit_stuff_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_tx : std_logic_vector(2 DOWNTO 0);
SIGNAL tx_point_q : std_logic;
SIGNAL rx_id1 : std_logic;
SIGNAL rx_rtr1 : std_logic;
SIGNAL rx_ide : std_logic;
SIGNAL rx_id2 : std_logic;
SIGNAL rx_rtr2 : std_logic;
SIGNAL rx_r1 : std_logic;
SIGNAL rx_r0 : std_logic;
SIGNAL rx_dlc : std_logic;
SIGNAL rx_data : std_logic;
SIGNAL rx_crc : std_logic;
SIGNAL rx_crc_lim : std_logic;
SIGNAL rx_ack : std_logic;
SIGNAL rx_ack_lim : std_logic;
SIGNAL rx_eof : std_logic;
SIGNAL go_early_tx_latched : std_logic;
SIGNAL rtr1 : std_logic;
SIGNAL ide : std_logic;
SIGNAL rtr2 : std_logic;
SIGNAL crc_in : std_logic_vector(14 DOWNTO 0);
SIGNAL tmp_data : std_logic_vector(7 DOWNTO 0);
SIGNAL tmp_fifo : xhdl_46;
SIGNAL write_data_to_tmp_fifo : std_logic;
SIGNAL byte_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_en : std_logic;
SIGNAL crc_enable : std_logic;
SIGNAL eof_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL passive_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_frame : std_logic;
SIGNAL enable_error_cnt2 : std_logic;
SIGNAL error_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL error_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL delayed_dominant_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL enable_overload_cnt2 : std_logic;
SIGNAL overload_frame_blocked : std_logic;
SIGNAL overload_request_cnt : std_logic_vector(1 DOWNTO 0);
SIGNAL overload_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL overload_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL crc_err : std_logic;
SIGNAL arbitration_lost : std_logic;
SIGNAL arbitration_lost_q : std_logic;
SIGNAL read_arbitration_lost_capture_reg_q: std_logic;
signal read_error_code_capture_reg_q : std_logic;
signal reset_error_code_capture_reg : std_logic;
SIGNAL arbitration_cnt_en : std_logic;
SIGNAL arbitration_blocked : std_logic;
SIGNAL tx_q : std_logic;
SIGNAL data_cnt : std_logic_vector(3 DOWNTO 0); -- Counting the data bytes that are written to FIFO
SIGNAL header_cnt : std_logic_vector(2 DOWNTO 0); -- Counting header length
SIGNAL wr_fifo : std_logic; -- Write data and header to 64-byte fifo
SIGNAL wr_fifo2 : std_logic;
SIGNAL data_for_fifo : std_logic_vector(7 DOWNTO 0); -- Multiplexed data that is stored to 64-byte fifo
SIGNAL tx_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL tx_bit : std_logic;
SIGNAL finish_msg : std_logic;
SIGNAL bus_free_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL bus_free_cnt_en : std_logic;
SIGNAL bus_free : std_logic;
SIGNAL waiting_for_bus_free : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL ack_err_latched : std_logic;
SIGNAL bit_err_latched : std_logic;
SIGNAL stuff_err_latched : std_logic;
SIGNAL form_err_latched : std_logic;
SIGNAL rule3_exc1_1 : std_logic;
SIGNAL rule3_exc1_2 : std_logic;
SIGNAL suspend : std_logic;
SIGNAL susp_cnt_en : std_logic;
SIGNAL susp_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_flag_over_latched : std_logic;
SIGNAL error_capture_code_type : std_logic_vector(7 DOWNTO 6);
SIGNAL error_capture_code_blocked : std_logic;
SIGNAL first_compare_bit : std_logic;
SIGNAL error_capture_code_segment : std_logic_vector(4 DOWNTO 0);
SIGNAL error_capture_code_direction : std_logic;
SIGNAL bit_de_stuff : std_logic;
SIGNAL bit_de_stuff_tx : std_logic;
SIGNAL rule5 : std_logic;
-- Rx state machine
SIGNAL go_rx_idle : std_logic;
SIGNAL go_rx_id1 : std_logic;
SIGNAL go_rx_rtr1 : std_logic;
SIGNAL go_rx_ide : std_logic;
SIGNAL go_rx_id2 : std_logic;
SIGNAL go_rx_rtr2 : std_logic;
SIGNAL go_rx_r1 : std_logic;
SIGNAL go_rx_r0 : std_logic;
SIGNAL go_rx_dlc : std_logic;
SIGNAL go_rx_data : std_logic;
SIGNAL go_rx_crc : std_logic;
SIGNAL go_rx_crc_lim : std_logic;
SIGNAL go_rx_ack : std_logic;
SIGNAL go_rx_ack_lim : std_logic;
SIGNAL go_rx_eof : std_logic;
SIGNAL last_bit_of_inter : std_logic;
SIGNAL go_crc_enable : std_logic;
SIGNAL rst_crc_enable : std_logic;
SIGNAL bit_de_stuff_set : std_logic;
SIGNAL bit_de_stuff_reset : std_logic;
SIGNAL go_early_tx : std_logic;
SIGNAL calculated_crc : std_logic_vector(14 DOWNTO 0);
SIGNAL r_calculated_crc : std_logic_vector(15 DOWNTO 0);
SIGNAL remote_rq : std_logic;
SIGNAL limited_data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL form_err : std_logic;
SIGNAL error_frame_ended : std_logic;
SIGNAL overload_frame_ended : std_logic;
SIGNAL bit_err : std_logic;
SIGNAL ack_err : std_logic;
SIGNAL stuff_err : std_logic;
SIGNAL id_ok : std_logic; -- If received ID matches ID set in registers
SIGNAL no_byte0 : std_logic; -- There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
SIGNAL no_byte1 : std_logic; -- There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
SIGNAL header_len : std_logic_vector(2 DOWNTO 0);
SIGNAL storing_header : std_logic;
SIGNAL limited_data_len_minus1 : std_logic_vector(3 DOWNTO 0);
SIGNAL reset_wr_fifo : std_logic;
SIGNAL err : std_logic;
SIGNAL arbitration_field : std_logic;
SIGNAL basic_chain : std_logic_vector(18 DOWNTO 0);
SIGNAL basic_chain_data : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_std : std_logic_vector(18 DOWNTO 0);
SIGNAL extended_chain_ext : std_logic_vector(38 DOWNTO 0);
SIGNAL extended_chain_data_std : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_data_ext : std_logic_vector(63 DOWNTO 0);
SIGNAL rst_tx_pointer : std_logic;
SIGNAL r_tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_12 : std_logic_vector(7 DOWNTO 0);
SIGNAL bit_err_exc1 : std_logic;
SIGNAL bit_err_exc2 : std_logic;
SIGNAL bit_err_exc3 : std_logic;
SIGNAL bit_err_exc4 : std_logic;
SIGNAL bit_err_exc5 : std_logic;
SIGNAL bit_err_exc6 : std_logic;
SIGNAL error_flag_over : std_logic;
SIGNAL overload_flag_over : std_logic;
SIGNAL limited_tx_cnt_ext : std_logic_vector(5 DOWNTO 0);
SIGNAL limited_tx_cnt_std : std_logic_vector(5 DOWNTO 0);
-- Instantiation of the RX CRC module
SIGNAL xhdl_49 : std_logic;
-- Mode register
-- Clock Divider register
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for EXTENDED mode
SIGNAL temp_xhdl47 : std_logic_vector(3 DOWNTO 0);
SIGNAL port_xhdl73 : std_logic_vector(7 DOWNTO 0);
SIGNAL port_xhdl74 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl75 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl76 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl77 : std_logic_vector(3 DOWNTO 0);
SIGNAL temp_xhdl78 : std_logic_vector(3 DOWNTO 0); -- - 1 because counter counts from 0
SIGNAL xhdl_106 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl108 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl109 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl110 : boolean;
SIGNAL temp_xhdl111 : std_logic;
SIGNAL tx_state_xhdl2 : std_logic;
SIGNAL tx_state_q_xhdl3 : std_logic;
SIGNAL overload_frame_xhdl4 : std_logic;
SIGNAL error_capture_code_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_idle_xhdl6 : std_logic;
SIGNAL transmitting_xhdl7 : std_logic;
SIGNAL transmitter_xhdl8 : std_logic;
SIGNAL go_rx_inter_xhdl9 : std_logic;
SIGNAL not_first_bit_of_inter_xhdl10 : std_logic;
SIGNAL rx_inter_xhdl11 : std_logic;
SIGNAL node_bus_off_xhdl13 : std_logic;
SIGNAL rx_err_cnt_xhdl15 : std_logic_vector(8 DOWNTO 0);
SIGNAL tx_err_cnt_xhdl16 : std_logic_vector(8 DOWNTO 0);
SIGNAL transmit_status_xhdl17 : std_logic;
SIGNAL receive_status_xhdl18 : std_logic;
SIGNAL tx_successful_xhdl19 : std_logic;
SIGNAL need_to_tx_xhdl20 : std_logic;
SIGNAL overrun_xhdl21 : std_logic;
SIGNAL set_bus_error_irq_xhdl23 : std_logic;
SIGNAL set_arbitration_lost_irq_xhdl24 : std_logic;
SIGNAL arbitration_lost_capture_xhdl25 : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive_xhdl26: std_logic;
SIGNAL node_error_active_xhdl27 : std_logic;
SIGNAL tx_xhdl29 : std_logic;
SIGNAL tx_next_xhdl30 : std_logic;
SIGNAL go_overload_frame_xhdl32 : std_logic;
SIGNAL go_error_frame_xhdl33 : std_logic;
SIGNAL go_tx_xhdl34 : std_logic;
SIGNAL send_ack_xhdl35 : std_logic;
signal rx_msg_data : std_logic_vector(63 downto 0);
SIGNAL set_reset_mode_xhdl12 : std_logic;
BEGIN
form_error <= form_err_latched;
crc_error <= crc_err;
ack_error <= ack_err_latched;
stuff_error <= stuff_err_latched;
bit_error <= bit_err_latched;
arb_loss <= arbitration_lost;
tx_state <= tx_state_xhdl2;
tx_state_q <= tx_state_q_xhdl3;
overload_frame <= overload_frame_xhdl4;
error_capture_code <= error_capture_code_xhdl5;
rx_idle <= rx_idle_xhdl6;
transmitting <= transmitting_xhdl7;
transmitter <= transmitter_xhdl8;
go_rx_inter <= go_rx_inter_xhdl9;
not_first_bit_of_inter <= not_first_bit_of_inter_xhdl10;
rx_inter <= rx_inter_xhdl11;
node_bus_off <= node_bus_off_xhdl13;
rx_err_cnt <= rx_err_cnt_xhdl15;
tx_err_cnt <= tx_err_cnt_xhdl16;
transmit_status <= transmitter_xhdl8;
-- transmit_status <= transmit_status_xhdl17;
receive_status <= receive_status_xhdl18;
tx_successful <= tx_successful_xhdl19;
need_to_tx <= need_to_tx_xhdl20;
overrun <= overrun_xhdl21;
set_bus_error_irq <= set_bus_error_irq_xhdl23;
set_arbitration_lost_irq <= set_arbitration_lost_irq_xhdl24;
arbitration_lost_capture <= arbitration_lost_capture_xhdl25;
node_error_passive <= node_error_passive_xhdl26;
node_error_active <= node_error_active_xhdl27;
tx <= tx_xhdl29;
tx_next <= tx_next_xhdl30;
go_overload_frame <= go_overload_frame_xhdl32;
go_error_frame <= go_error_frame_xhdl33;
go_tx <= go_tx_xhdl34;
send_ack <= send_ack_xhdl35;
go_rx_idle <= ((sample_point AND sampled_bit) AND last_bit_of_inter) OR (bus_free AND (NOT node_bus_off_xhdl13)) ;
go_rx_id1 <= (sample_point AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_rx_rtr1 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id1) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1010") ;
go_rx_ide <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr1 ;
go_rx_id2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_ide) AND sampled_bit ;
go_rx_rtr2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id2) AND CONV_STD_LOGIC(bit_cnt(4 DOWNTO 0) = "10001") ;
go_rx_r1 <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr2 ;
go_rx_r0 <= ((NOT bit_de_stuff) AND sample_point) AND ((rx_ide AND (NOT sampled_bit)) OR rx_r1) ;
go_rx_dlc <= ((NOT bit_de_stuff) AND sample_point) AND rx_r0 ;
go_rx_data <= (((((NOT bit_de_stuff) AND sample_point) AND rx_dlc) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (sampled_bit OR (orv(data_len(2 DOWNTO 0))))) AND (NOT remote_rq) ;
go_rx_crc <= ((NOT bit_de_stuff) AND sample_point) AND (((rx_dlc AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (((NOT sampled_bit) AND (NOT (orv(data_len(2 DOWNTO 0))))) OR remote_rq)) OR (rx_data AND CONV_STD_LOGIC('0' & bit_cnt(5 DOWNTO 0) = ((limited_data_len & "000") - 1)))) ;
go_rx_crc_lim <= (((NOT bit_de_stuff) AND sample_point) AND rx_crc) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1110") ;
go_rx_ack <= ((NOT bit_de_stuff) AND sample_point) AND rx_crc_lim ;
go_rx_ack_lim <= sample_point AND rx_ack ;
go_rx_eof <= sample_point AND rx_ack_lim ;
go_rx_inter_xhdl9 <= (((sample_point AND rx_eof) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended) AND (NOT overload_request) ;
go_error_frame_xhdl33 <= form_err OR stuff_err OR bit_err OR ack_err OR (crc_err AND go_rx_eof) ;
error_frame_ended <= CONV_STD_LOGIC(error_cnt2 = "111") AND tx_point ;
overload_frame_ended <= CONV_STD_LOGIC(overload_cnt2 = "111") AND tx_point ;
go_overload_frame_xhdl32 <= (((sample_point AND ((NOT sampled_bit) OR overload_request)) AND (((rx_eof AND (NOT transmitter_xhdl8)) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended)) OR (((sample_point AND (NOT sampled_bit)) AND rx_inter_xhdl11) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) < "10")) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt2 = "111") OR (overload_cnt2 = "111")))) AND (NOT overload_frame_blocked) ;
go_crc_enable <= hard_sync OR go_tx_xhdl34 ;
rst_crc_enable <= go_rx_crc ;
bit_de_stuff_set <= go_rx_id1 AND (NOT go_error_frame_xhdl33) ;
bit_de_stuff_reset <= go_rx_ack OR reset_mode OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 ;
remote_rq <= ((NOT ide) AND rtr1) OR (ide AND rtr2) ;
temp_xhdl47 <= data_len WHEN (data_len < "1000") ELSE "1000";
limited_data_len <= temp_xhdl47 ;
ack_err <= (((rx_ack AND sample_point) AND sampled_bit) AND tx_state_xhdl2) AND (NOT self_test_mode) ;
bit_err <= ((((((((tx_state_xhdl2 OR error_frame OR overload_frame_xhdl4 OR rx_ack) AND sample_point) AND CONV_STD_LOGIC(tx_xhdl29 /= sampled_bit)) AND (NOT bit_err_exc1)) AND (NOT bit_err_exc2)) AND (NOT bit_err_exc3)) AND (NOT bit_err_exc4)) AND (NOT bit_err_exc5)) AND (NOT bit_err_exc6) ;
bit_err_exc1 <= (tx_state_xhdl2 AND arbitration_field) AND tx_xhdl29 ;
bit_err_exc2 <= rx_ack AND tx_xhdl29 ;
bit_err_exc3 <= (error_frame AND node_error_passive_xhdl26) AND CONV_STD_LOGIC(error_cnt1 < "111") ;
bit_err_exc4 <= ((error_frame AND CONV_STD_LOGIC(error_cnt1 = "111")) AND (NOT enable_error_cnt2)) OR ((overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2)) ;
bit_err_exc5 <= (error_frame AND CONV_STD_LOGIC(error_cnt2 = "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt2 = "111")) ;
bit_err_exc6 <= (CONV_STD_LOGIC(eof_cnt = "110") AND rx_eof) AND (NOT transmitter_xhdl8) ;
arbitration_field <= rx_id1 OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 ;
last_bit_of_inter <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "10") ;
not_first_bit_of_inter_xhdl10 <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) /= "00") ;
-- Rx idle state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_idle_xhdl6 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_id1 OR go_error_frame_xhdl33) = '1') THEN
rx_idle_xhdl6 <= '0' ;
ELSE
IF (go_rx_idle = '1') THEN
rx_idle_xhdl6 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_idle_xhdl6 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx id1 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_id1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr1 OR go_error_frame_xhdl33) = '1') THEN
rx_id1 <= '0' ;
ELSE
IF (go_rx_id1 = '1') THEN
rx_id1 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_id1 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx rtr1 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_rtr1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ide OR go_error_frame_xhdl33) = '1') THEN
rx_rtr1 <= '0' ;
ELSE
IF (go_rx_rtr1 = '1') THEN
rx_rtr1 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_rtr1 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx ide state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_ide <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_rx_id2 OR go_error_frame_xhdl33) = '1') THEN
rx_ide <= '0' ;
ELSE
IF (go_rx_ide = '1') THEN
rx_ide <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_ide <= '0';
END IF;
END IF;
END PROCESS;
-- Rx id2 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_id2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr2 OR go_error_frame_xhdl33) = '1') THEN
rx_id2 <= '0' ;
ELSE
IF (go_rx_id2 = '1') THEN
rx_id2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_id2 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx rtr2 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_rtr2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r1 OR go_error_frame_xhdl33) = '1') THEN
rx_rtr2 <= '0' ;
ELSE
IF (go_rx_rtr2 = '1') THEN
rx_rtr2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_rtr2 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_r1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_error_frame_xhdl33) = '1') THEN
rx_r1 <= '0' ;
ELSE
IF (go_rx_r1 = '1') THEN
rx_r1 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_r1 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_r0 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_dlc OR go_error_frame_xhdl33) = '1') THEN
rx_r0 <= '0' ;
ELSE
IF (go_rx_r0 = '1') THEN
rx_r0 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_r0 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx dlc state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_dlc <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_data OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_dlc <= '0' ;
ELSE
IF (go_rx_dlc = '1') THEN
rx_dlc <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_dlc <= '0';
END IF;
END IF;
END PROCESS;
-- Rx data state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_data <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_data <= '0' ;
ELSE
IF (go_rx_data = '1') THEN
rx_data <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_data <= '0';
END IF;
END IF;
END PROCESS;
-- Rx crc state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_crc <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc_lim OR go_error_frame_xhdl33) = '1') THEN
rx_crc <= '0' ;
ELSE
IF (go_rx_crc = '1') THEN
rx_crc <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_crc <= '0';
END IF;
END IF;
END PROCESS;
-- Rx crc delimiter state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_crc_lim <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack OR go_error_frame_xhdl33) = '1') THEN
rx_crc_lim <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
rx_crc_lim <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_crc_lim <= '0';
END IF;
END IF;
END PROCESS;
-- Rx ack state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_ack <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack_lim OR go_error_frame_xhdl33) = '1') THEN
rx_ack <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
rx_ack <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_ack <= '0';
END IF;
END IF;
END PROCESS;
-- Rx ack delimiter state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_ack_lim <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_eof OR go_error_frame_xhdl33) = '1') THEN
rx_ack_lim <= '0' ;
ELSE
IF (go_rx_ack_lim = '1') THEN
rx_ack_lim <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_ack_lim <= '0';
END IF;
END IF;
END PROCESS;
-- Rx eof state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_eof <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
rx_eof <= '0' ;
ELSE
IF (go_rx_eof = '1') THEN
rx_eof <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_eof <= '0';
END IF;
END IF;
END PROCESS;
-- Interframe space
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_inter_xhdl11 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_idle OR go_rx_id1 OR go_overload_frame_xhdl32 OR go_error_frame_xhdl33) = '1') THEN
rx_inter_xhdl11 <= '0' ;
ELSE
IF (go_rx_inter_xhdl9 = '1') THEN
rx_inter_xhdl11 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_inter_xhdl11 <= '0';
END IF;
END IF;
END PROCESS;
-- ID register
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- id <= "00000000000000000000000000000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
id <= "00000000000000000000000000000";
ELSE
IF (((sample_point AND (rx_id1 OR rx_id2)) AND (NOT bit_de_stuff)) = '1') THEN
id <= id(27 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
id <= "00000000000000000000000000000";
END IF;
END IF;
END PROCESS;
-- rtr1 bit
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rtr1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr1 <= '0';
ELSE
IF (((sample_point AND rx_rtr1) AND (NOT bit_de_stuff)) = '1') THEN
rtr1 <= sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
rtr1 <= '0';
END IF;
END IF;
END PROCESS;
-- rtr2 bit
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rtr2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr2 <= '0';
ELSE
IF (((sample_point AND rx_rtr2) AND (NOT bit_de_stuff)) = '1') THEN
rtr2 <= sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
rtr2 <= '0';
END IF;
END IF;
END PROCESS;
-- ide bit
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- ide <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
ide <= '0';
ELSE
IF (((sample_point AND rx_ide) AND (NOT bit_de_stuff)) = '1') THEN
ide <= sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
ide <= '0';
END IF;
END IF;
END PROCESS;
-- Data length
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- data_len <= "0000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
data_len <= "0000";
ELSE
IF (((sample_point AND rx_dlc) AND (NOT bit_de_stuff)) = '1') THEN
data_len <= data_len(2 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
data_len <= "0000";
END IF;
END IF;
END PROCESS;
-- Data
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tmp_data <= "00000000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tmp_data <= "00000000";
ELSE
IF (((sample_point AND rx_data) AND (NOT bit_de_stuff)) = '1') THEN
tmp_data <= tmp_data(6 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
tmp_data <= "00000000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- write_data_to_tmp_fifo <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSE
IF ((((sample_point AND rx_data) AND (NOT bit_de_stuff)) AND (andv(bit_cnt(2 DOWNTO 0)))) = '1') THEN
write_data_to_tmp_fifo <= '1' ;
ELSE
write_data_to_tmp_fifo <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
write_data_to_tmp_fifo <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
-- IF (rst = '1') THEN
-- byte_cnt <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode or rst) = '1') THEN
byte_cnt <= "000";
ELSE
IF (write_data_to_tmp_fifo = '1') THEN
byte_cnt <= byte_cnt + "001" ;
ELSE
IF ((sample_point AND go_rx_crc_lim) = '1') THEN
byte_cnt <= "000" ;
END IF;
END IF;
END IF;
-- IF (rst = '1') THENbyte_cnt <= "000";END IF;
END IF;
END PROCESS;
process (clk, rst)
begin
if rising_edge(clk) then
wr_fifo2 <= wr_fifo;
end if;
if rst = '1' then
wr_fifo2 <= '0';
end if;
end process;
rcv_msg_valid <= wr_fifo and not wr_fifo2;
rcv_id <= id when ide = '1' else id(10 downto 0) & "11" & X"FFFF";
rcv_rtr <= rtr2 when ide = '1' else rtr1;
rcv_dlc <= data_len;
rcv_ide <= ide;
rcv_msg_data <= rx_msg_data;
process (clk)
begin
if (clk'EVENT AND clk = '1') then
if (write_data_to_tmp_fifo = '1') then
case byte_cnt is
when "000" => rx_msg_data(63 downto 56) <= tmp_data;
when "001" => rx_msg_data(55 downto 48) <= tmp_data;
when "010" => rx_msg_data(47 downto 40) <= tmp_data;
when "011" => rx_msg_data(39 downto 32) <= tmp_data;
when "100" => rx_msg_data(31 downto 24) <= tmp_data;
when "101" => rx_msg_data(23 downto 16) <= tmp_data;
when "110" => rx_msg_data(15 downto 8) <= tmp_data;
when "111" => rx_msg_data(7 downto 0) <= tmp_data;
when others => null;
end case;
end if;
if (rst = '1') then
rx_msg_data <= (others => '0');
end if;
end if;
end process;
-- CRC
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- crc_in <= "000000000000000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
crc_in <= "000000000000000";
ELSE
IF (((sample_point AND rx_crc) AND (NOT bit_de_stuff)) = '1') THEN
crc_in <= crc_in(13 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
crc_in <= "000000000000000";
END IF;
END IF;
END PROCESS;
-- bit_cnt
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bit_cnt <= "000000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_cnt <= "000000";
ELSE
IF ((go_rx_id1 OR go_rx_id2 OR go_rx_dlc OR go_rx_data OR go_rx_crc OR go_rx_ack OR go_rx_eof OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
bit_cnt <= "000000" ;
ELSE
IF ((sample_point AND (NOT bit_de_stuff)) = '1') THEN
bit_cnt <= bit_cnt + "000001" ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
bit_cnt <= "000000";
END IF;
END IF;
END PROCESS;
-- eof_cnt
PROCESS (clk)
BEGIN
-- IF (rst = '1') THEN
-- eof_cnt <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode or rst) = '1') THEN
eof_cnt <= "000";
ELSE
IF (sample_point = '1') THEN
IF ((go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
eof_cnt <= "000" ;
ELSE
IF (rx_eof = '1') THEN
eof_cnt <= eof_cnt + "001" ;
END IF;
END IF;
END IF;
END IF;
-- IF (rst = '1') THENeof_cnt <= "000";END IF;
END IF;
END PROCESS;
-- Enabling bit de-stuffing
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bit_stuff_cnt_en <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_en <= '0';
ELSE
IF (bit_de_stuff_set = '1') THEN
bit_stuff_cnt_en <= '1' ;
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_en <= '0' ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
bit_stuff_cnt_en <= '0';
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bit_stuff_cnt <= "001";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt <= "001" ;
ELSE
IF ((sample_point AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt = "101") THEN
bit_stuff_cnt <= "001" ;
ELSE
IF (sampled_bit = sampled_bit_q) THEN
bit_stuff_cnt <= bit_stuff_cnt + "001" ;
ELSE
bit_stuff_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
bit_stuff_cnt <= "001";
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt_tx
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bit_stuff_cnt_tx <= "001";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF ((tx_point_q AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt_tx = "101") THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF (tx_xhdl29 = tx_q) THEN
bit_stuff_cnt_tx <= bit_stuff_cnt_tx + "001" ;
ELSE
bit_stuff_cnt_tx <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
bit_stuff_cnt_tx <= "001";
END IF;
END IF;
END PROCESS;
bit_de_stuff <= CONV_STD_LOGIC(bit_stuff_cnt = "101") ;
bit_de_stuff_tx <= CONV_STD_LOGIC(bit_stuff_cnt_tx = "101") ;
-- stuff_err
stuff_err <= ((sample_point AND bit_stuff_cnt_en) AND bit_de_stuff) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q) ;
-- Generating delayed signals
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- reset_mode_q <= '0' ;
-- node_bus_off_q <= '0' ;
IF (clk'EVENT AND clk = '1') THEN
reset_mode_q <= reset_mode ;
node_bus_off_q <= node_bus_off_xhdl13 ;
IF (rst = '1') THEN
reset_mode_q <= '0' ;
node_bus_off_q <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- crc_enable <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR rst_crc_enable) = '1') THEN
crc_enable <= '0' ;
ELSE
IF (go_crc_enable = '1') THEN
crc_enable <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
crc_enable <= '0';
END IF;
END IF;
END PROCESS;
-- CRC error generation
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- crc_err <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended) = '1') THEN
crc_err <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
crc_err <= CONV_STD_LOGIC(crc_in /= calculated_crc) ;
END IF;
END IF;
IF (rst = '1') THEN
crc_err <= '0';
END IF;
END IF;
END PROCESS;
-- Conditions for form error
form_err <= sample_point AND ((((NOT bit_de_stuff) AND rx_crc_lim) AND (NOT sampled_bit)) OR (rx_ack_lim AND (NOT sampled_bit)) OR (((CONV_STD_LOGIC(eof_cnt < "110") AND rx_eof) AND (NOT sampled_bit)) AND (NOT transmitter_xhdl8)) OR (((rx_eof) AND (NOT sampled_bit)) AND transmitter_xhdl8)) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- ack_err_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
ack_err_latched <= '0' ;
ELSE
IF (ack_err = '1') THEN
ack_err_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
ack_err_latched <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bit_err_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
bit_err_latched <= '0' ;
ELSE
IF (bit_err = '1') THEN
bit_err_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
bit_err_latched <= '0';
END IF;
END IF;
END PROCESS;
-- Rule 5 (Fault confinement).
rule5 <= bit_err AND ((((NOT node_error_passive_xhdl26) AND error_frame) AND CONV_STD_LOGIC(error_cnt1 < "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 < "111"))) ;
-- Rule 3 exception 1 - first part (Fault confinement).
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rule3_exc1_1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_flag_over OR rule3_exc1_2) = '1') THEN
rule3_exc1_1 <= '0' ;
ELSE
IF (((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err) = '1') THEN
rule3_exc1_1 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rule3_exc1_1 <= '0';
END IF;
END IF;
END PROCESS;
-- Rule 3 exception 1 - second part (Fault confinement).
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rule3_exc1_2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR rule3_exc1_2) = '1') THEN
rule3_exc1_2 <= '0' ;
ELSE
IF ((((rule3_exc1_1 AND CONV_STD_LOGIC(error_cnt1 < "111")) AND sample_point) AND (NOT sampled_bit)) = '1') THEN
rule3_exc1_2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rule3_exc1_2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- stuff_err_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
stuff_err_latched <= '0' ;
ELSE
IF (stuff_err = '1') THEN
stuff_err_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
stuff_err_latched <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- form_err_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
form_err_latched <= '0' ;
ELSE
IF (form_err = '1') THEN
form_err_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
form_err_latched <= '0';
END IF;
END IF;
END PROCESS;
xhdl_49 <= ((crc_enable AND sample_point) AND (NOT bit_de_stuff));
i_can_crc_core_sync_rx : can_crc_core_sync
PORT MAP (
clk => clk,
data => sampled_bit,
enable => xhdl_49,
initialize => go_crc_enable,
crc => calculated_crc);
no_byte0 <= rtr1 OR CONV_STD_LOGIC(data_len < "0001") ;
no_byte1 <= rtr1 OR CONV_STD_LOGIC(data_len < "0010") ;
temp_xhdl75 <= "101" WHEN ide = '1' ELSE "011";
temp_xhdl76 <= (temp_xhdl75) WHEN extended_mode = '1' ELSE "010";
header_len(2 DOWNTO 0) <= temp_xhdl76 ;
storing_header <= CONV_STD_LOGIC(header_cnt < header_len) ;
temp_xhdl77 <= (data_len - "0001") WHEN (data_len < "1000") ELSE "0111";
temp_xhdl78 <= "1111" WHEN remote_rq = '1' ELSE (temp_xhdl77);
limited_data_len_minus1(3 DOWNTO 0) <= temp_xhdl78 ;
reset_wr_fifo <= CONV_STD_LOGIC(data_cnt = (limited_data_len_minus1 + ('0' & header_len))) OR reset_mode ;
err <= form_err OR stuff_err OR bit_err OR ack_err OR form_err_latched OR stuff_err_latched OR bit_err_latched OR ack_err_latched OR crc_err ;
id_ok <= '1';
-- Write enable signal for 64-byte rx fifo
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- wr_fifo <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
wr_fifo <= '0' ;
ELSE
IF ((((go_rx_inter_xhdl9 AND id_ok) AND (NOT error_frame_ended)) AND ((NOT tx_state_xhdl2) OR self_rx_request)) = '1') THEN
wr_fifo <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
wr_fifo <= '0';
END IF;
END IF;
END PROCESS;
-- Header counter. Header length depends on the mode of operation and frame format.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- header_cnt <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
header_cnt <= "000" ;
ELSE
IF ((wr_fifo AND storing_header) = '1') THEN
header_cnt <= header_cnt + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
header_cnt <= "000";
END IF;
END IF;
END PROCESS;
-- Data counter. Length of the data is limited to 8 bytes.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- data_cnt <= "0000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
data_cnt <= "0000" ;
ELSE
IF (wr_fifo = '1') THEN
data_cnt <= data_cnt + "0001" ;
END IF;
END IF;
IF (rst = '1') THEN
data_cnt <= "0000";
END IF;
END IF;
END PROCESS;
-- Transmitting error frame.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_frame <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
error_frame <= '0' ;
ELSE
IF (go_error_frame_xhdl33 = '1') THEN
error_frame <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
error_frame <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_cnt1 <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt1 <= "000" ;
ELSE
IF (((error_frame AND tx_point) AND CONV_STD_LOGIC(error_cnt1 < "111")) = '1') THEN
error_cnt1 <= error_cnt1 + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
error_cnt1 <= "000";
END IF;
END IF;
END PROCESS;
error_flag_over <= ((((NOT node_error_passive_xhdl26) AND sample_point) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR ((node_error_passive_xhdl26 AND sample_point) AND CONV_STD_LOGIC(passive_cnt = "110"))) AND (NOT enable_error_cnt2) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_flag_over_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_flag_over_latched <= '0' ;
ELSE
IF (error_flag_over = '1') THEN
error_flag_over_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
error_flag_over_latched <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- enable_error_cnt2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_error_cnt2 <= '0' ;
ELSE
IF ((error_frame AND (error_flag_over AND sampled_bit)) = '1') THEN
enable_error_cnt2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
enable_error_cnt2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_cnt2 <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt2 <= "000" ;
ELSE
IF ((enable_error_cnt2 AND tx_point) = '1') THEN
error_cnt2 <= error_cnt2 + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
error_cnt2 <= "000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- delayed_dominant_cnt <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR enable_error_cnt2 OR go_error_frame_xhdl33 OR enable_overload_cnt2 OR go_overload_frame_xhdl32) = '1') THEN
delayed_dominant_cnt <= "000" ;
ELSE
IF (((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt1 = "111") OR (overload_cnt1 = "111"))) = '1') THEN
delayed_dominant_cnt <= delayed_dominant_cnt + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
delayed_dominant_cnt <= "000";
END IF;
END IF;
END PROCESS;
-- passive_cnt
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- passive_cnt <= "001";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR first_compare_bit) = '1') THEN
passive_cnt <= "001" ;
ELSE
IF ((sample_point AND CONV_STD_LOGIC(passive_cnt < "110")) = '1') THEN
IF (((error_frame AND (NOT enable_error_cnt2)) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q)) = '1') THEN
passive_cnt <= passive_cnt + "001" ;
ELSE
passive_cnt <= "001" ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
passive_cnt <= "001";
END IF;
END IF;
END PROCESS;
-- When comparing 6 equal bits, first is always equal
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- first_compare_bit <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame_xhdl33 = '1') THEN
first_compare_bit <= '1' ;
ELSE
IF (sample_point = '1') THEN
first_compare_bit <= '0';
END IF;
END IF;
IF (rst = '1') THEN
first_compare_bit <= '0';
END IF;
END IF;
END PROCESS;
-- Transmitting overload frame.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- overload_frame_xhdl4 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33) = '1') THEN
overload_frame_xhdl4 <= '0' ;
ELSE
IF (go_overload_frame_xhdl32 = '1') THEN
overload_frame_xhdl4 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
overload_frame_xhdl4 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- overload_cnt1 <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt1 <= "000" ;
ELSE
IF (((overload_frame_xhdl4 AND tx_point) AND CONV_STD_LOGIC(overload_cnt1 < "111")) = '1') THEN
overload_cnt1 <= overload_cnt1 + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
overload_cnt1 <= "000";
END IF;
END IF;
END PROCESS;
overload_flag_over <= (sample_point AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- enable_overload_cnt2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_overload_cnt2 <= '0' ;
ELSE
IF ((overload_frame_xhdl4 AND (overload_flag_over AND sampled_bit)) = '1') THEN
enable_overload_cnt2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
enable_overload_cnt2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- overload_cnt2 <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt2 <= "000" ;
ELSE
IF ((enable_overload_cnt2 AND tx_point) = '1') THEN
overload_cnt2 <= overload_cnt2 + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
overload_cnt2 <= "000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- overload_request_cnt <= "00";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_request_cnt <= "00" ;
ELSE
IF ((overload_request AND overload_frame_xhdl4) = '1') THEN
overload_request_cnt <= overload_request_cnt + "01" ;
END IF;
END IF;
IF (rst = '1') THEN
overload_request_cnt <= "00";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- overload_frame_blocked <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_frame_blocked <= '0' ;
ELSE
IF (((overload_request AND overload_frame_xhdl4) AND CONV_STD_LOGIC(overload_request_cnt = "10")) = '1') THEN
-- This is a second sequential overload_request
overload_frame_blocked <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
overload_frame_blocked <= '0';
END IF;
END IF;
END PROCESS;
send_ack_xhdl35 <= (((NOT tx_state_xhdl2) AND rx_ack) AND (NOT err)) AND (NOT listen_only_mode) ;
PROCESS (reset_mode, node_bus_off_xhdl13, tx_state_xhdl2, go_tx_xhdl34, bit_de_stuff_tx, tx_bit, tx_q, send_ack_xhdl35, go_overload_frame_xhdl32, overload_frame_xhdl4, overload_cnt1, go_error_frame_xhdl33, error_frame, error_cnt1, node_error_passive_xhdl26)
VARIABLE tx_next_xhdl30_xhdl105 : std_logic;
BEGIN
IF ((reset_mode OR node_bus_off_xhdl13) = '1') THEN
-- Reset or node_bus_off
tx_next_xhdl30_xhdl105 := '1';
ELSE
IF ((go_error_frame_xhdl33 OR error_frame) = '1') THEN
-- Transmitting error frame
IF (error_cnt1 < "110") THEN
IF (node_error_passive_xhdl26 = '1') THEN
tx_next_xhdl30_xhdl105 := '1';
ELSE
tx_next_xhdl30_xhdl105 := '0';
END IF;
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_overload_frame_xhdl32 OR overload_frame_xhdl4) = '1') THEN
-- Transmitting overload frame
IF (overload_cnt1 < "110") THEN
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_tx_xhdl34 OR tx_state_xhdl2) = '1') THEN
-- Transmitting message
tx_next_xhdl30_xhdl105 := ((NOT bit_de_stuff_tx) AND tx_bit) OR (bit_de_stuff_tx AND (NOT tx_q));
ELSE
IF (send_ack_xhdl35 = '1') THEN
-- Acknowledge
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
END IF;
END IF;
END IF;
END IF;
tx_next_xhdl30 <= tx_next_xhdl30_xhdl105;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_xhdl29 <= '1';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_xhdl29 <= '1';
ELSE
IF (tx_point = '1') THEN
tx_xhdl29 <= tx_next_xhdl30 ;
END IF;
END IF;
IF (rst = '1') THEN
tx_xhdl29 <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_q <= '0' ;
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_q <= '0' ;
ELSE
IF (tx_point = '1') THEN
tx_q <= tx_xhdl29 AND (NOT go_early_tx_latched) ;
END IF;
END IF;
IF (rst = '1') THEN
tx_q <= '0' ;
END IF;
END IF;
END PROCESS;
-- Delayed tx point
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_point_q <= '0' ;
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_point_q <= '0' ;
ELSE
tx_point_q <= tx_point ;
END IF;
IF (rst = '1') THEN
tx_point_q <= '0' ;
END IF;
END IF;
END PROCESS;
-- Changing bit order from [7:0] to [0:7]
i_ibo_tx_data_0 : can_ibo_core_sync
PORT MAP (
di => tx_data_0,
do => r_tx_data_0);
i_ibo_tx_data_1 : can_ibo_core_sync
PORT MAP (
di => tx_data_1,
do => r_tx_data_1);
i_ibo_tx_data_2 : can_ibo_core_sync
PORT MAP (
di => tx_data_2,
do => r_tx_data_2);
i_ibo_tx_data_3 : can_ibo_core_sync
PORT MAP (
di => tx_data_3,
do => r_tx_data_3);
i_ibo_tx_data_4 : can_ibo_core_sync
PORT MAP (
di => tx_data_4,
do => r_tx_data_4);
i_ibo_tx_data_5 : can_ibo_core_sync
PORT MAP (
di => tx_data_5,
do => r_tx_data_5);
i_ibo_tx_data_6 : can_ibo_core_sync
PORT MAP (
di => tx_data_6,
do => r_tx_data_6);
i_ibo_tx_data_7 : can_ibo_core_sync
PORT MAP (
di => tx_data_7,
do => r_tx_data_7);
i_ibo_tx_data_8 : can_ibo_core_sync
PORT MAP (
di => tx_data_8,
do => r_tx_data_8);
i_ibo_tx_data_9 : can_ibo_core_sync
PORT MAP (
di => tx_data_9,
do => r_tx_data_9);
i_ibo_tx_data_10 : can_ibo_core_sync
PORT MAP (
di => tx_data_10,
do => r_tx_data_10);
i_ibo_tx_data_11 : can_ibo_core_sync
PORT MAP (
di => tx_data_11,
do => r_tx_data_11);
i_ibo_tx_data_12 : can_ibo_core_sync
PORT MAP (
di => tx_data_12,
do => r_tx_data_12);
-- Changing bit order from [14:0] to [0:14]
i_calculated_crc0 : can_ibo_core_sync
PORT MAP (
di => calculated_crc(14 DOWNTO 7),
do => r_calculated_crc(7 DOWNTO 0));
xhdl_106 <= calculated_crc(6 DOWNTO 0) & '0';
i_calculated_crc1 : can_ibo_core_sync
PORT MAP (
di => xhdl_106,
do => r_calculated_crc(15 DOWNTO 8));
basic_chain <= r_tx_data_1(7 DOWNTO 4) & "00" & r_tx_data_1(3 DOWNTO 0) & r_tx_data_0(7 DOWNTO 0) & '0' ;
basic_chain_data <= r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 & r_tx_data_2 ;
extended_chain_std <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_ext <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_4(4 DOWNTO 0) & r_tx_data_3(7 DOWNTO 0) & r_tx_data_2(7 DOWNTO 3) & '1' & '1' & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_data_std <= r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 ;
extended_chain_data_ext <= r_tx_data_12 & r_tx_data_11 & r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 ;
PROCESS (extended_mode, rx_data, tx_pointer, extended_chain_data_std, extended_chain_data_ext, rx_crc, r_calculated_crc, r_tx_data_0, extended_chain_ext, extended_chain_std, basic_chain_data, basic_chain, finish_msg)
VARIABLE tx_bit_xhdl107 : std_logic;
BEGIN
IF (extended_mode = '1') THEN
IF (rx_data = '1') THEN
-- data stage
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_data_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_data_std(conv_integer(tx_pointer));
END IF;
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer(3 downto 0)));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_std(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
ELSE
-- Basic mode
IF (rx_data = '1') THEN
-- data stage
tx_bit_xhdl107 := basic_chain_data(conv_integer(tx_pointer));
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
tx_bit_xhdl107 := basic_chain(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
tx_bit <= tx_bit_xhdl107;
END PROCESS;
temp_xhdl108 <= "111111" WHEN tx_data_0(3) = '1' ELSE ((tx_data_0(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_ext <= temp_xhdl108 ;
temp_xhdl109 <= "111111" WHEN tx_data_1(3) = '1' ELSE ((tx_data_1(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_std <= temp_xhdl109 ;
-- arbitration + control for extended format
-- arbitration + control for extended format
-- arbitration + control for standard format
-- data (overflow is OK here)
-- data (overflow is OK here)
-- crc
-- at the end
rst_tx_pointer <= ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND r_tx_data_0(0)) AND CONV_STD_LOGIC(tx_pointer = "100110")) OR ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND (NOT r_tx_data_0(0))) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND extended_mode) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_ext)) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_std)) OR (tx_point AND rx_crc_lim) OR (go_rx_idle) OR (reset_mode) OR (overload_frame_xhdl4) OR (error_frame) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_pointer <= "000000";
IF (clk'EVENT AND clk = '1') THEN
IF (rst_tx_pointer = '1') THEN
tx_pointer <= "000000" ;
ELSE
IF ((go_early_tx OR ((tx_point AND (tx_state_xhdl2 OR go_tx_xhdl34)) AND (NOT bit_de_stuff_tx))) = '1') THEN
tx_pointer <= tx_pointer + "000001" ;
END IF;
END IF;
IF (rst = '1') THEN
tx_pointer <= "000000";
END IF;
END IF;
END PROCESS;
tx_successful_xhdl19 <= ((((transmitter_xhdl8 AND go_rx_inter_xhdl9) AND (NOT go_error_frame_xhdl33)) AND (NOT error_frame_ended)) AND (NOT overload_frame_ended)) AND (NOT arbitration_lost) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- need_to_tx_xhdl20 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((tx_successful_xhdl19 OR reset_mode OR (abort_tx AND (NOT transmitting_xhdl7)) OR (((NOT tx_state_xhdl2) AND tx_state_q_xhdl3) AND single_shot_transmission)) = '1') THEN
need_to_tx_xhdl20 <= '0' ;
ELSE
IF ((tx_request AND sample_point) = '1') THEN
need_to_tx_xhdl20 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
need_to_tx_xhdl20 <= '0';
END IF;
END IF;
END PROCESS;
go_early_tx <= ((((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR CONV_STD_LOGIC(susp_cnt = "111"))) AND sample_point) AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_tx_xhdl34 <= ((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111")))) AND (go_early_tx OR rx_idle_xhdl6) ;
-- go_early_tx latched (for proper bit_de_stuff generation)
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- go_early_tx_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR tx_point) = '1') THEN
go_early_tx_latched <= '0' ;
ELSE
IF (go_early_tx = '1') THEN
go_early_tx_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
go_early_tx_latched <= '0';
END IF;
END IF;
END PROCESS;
-- Tx state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_state_xhdl2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR error_frame OR arbitration_lost) = '1') THEN
tx_state_xhdl2 <= '0' ;
ELSE
IF (go_tx_xhdl34 = '1') THEN
tx_state_xhdl2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
tx_state_xhdl2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_state_q_xhdl3 <= '0' ;
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSE
tx_state_q_xhdl3 <= tx_state_xhdl2 ;
END IF;
IF (rst = '1') THEN
tx_state_q_xhdl3 <= '0' ;
END IF;
END IF;
END PROCESS;
-- Node is a transmitter
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- transmitter_xhdl8 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (go_tx_xhdl34 = '1') THEN
transmitter_xhdl8 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle or (suspend AND go_rx_id1)) = '1') THEN
transmitter_xhdl8 <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
transmitter_xhdl8 <= '0';
END IF;
END IF;
END PROCESS;
-- Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
-- Node might be both transmitter or receiver (sending error or overload frame)
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- transmitting_xhdl7 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR go_tx_xhdl34 OR send_ack_xhdl35) = '1') THEN
transmitting_xhdl7 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (go_rx_id1 AND (NOT tx_state_xhdl2)) OR (arbitration_lost AND tx_state_xhdl2)) = '1') THEN
transmitting_xhdl7 <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
transmitting_xhdl7 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- suspend <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
suspend <= '0' ;
ELSE
IF (((not_first_bit_of_inter_xhdl10 AND transmitter_xhdl8) AND node_error_passive_xhdl26) = '1') THEN
suspend <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
suspend <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- susp_cnt_en <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt_en <= '0' ;
ELSE
IF (((suspend AND sample_point) AND last_bit_of_inter) = '1') THEN
susp_cnt_en <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
susp_cnt_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- susp_cnt <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt <= "000" ;
ELSE
IF ((susp_cnt_en AND sample_point) = '1') THEN
susp_cnt <= susp_cnt + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
susp_cnt <= "000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- finish_msg <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR go_rx_id1 OR error_frame OR reset_mode) = '1') THEN
finish_msg <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
finish_msg <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
finish_msg <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- arbitration_lost <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR error_frame_ended OR reset_mode) = '1') THEN
arbitration_lost <= '0' ;
ELSE
IF (((((transmitter_xhdl8 AND sample_point) AND tx_xhdl29) AND arbitration_field) AND NOT sampled_bit) = '1') THEN
arbitration_lost <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
arbitration_lost <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- arbitration_lost_q <= '0' ;
-- read_arbitration_lost_capture_reg_q <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
arbitration_lost_q <= '0';
read_arbitration_lost_capture_reg_q <= '0';
ELSE
arbitration_lost_q <= arbitration_lost;
read_arbitration_lost_capture_reg_q <= read_arbitration_lost_capture_reg ;
END IF;
IF (rst = '1') THEN
arbitration_lost_q <= '0' ;
read_arbitration_lost_capture_reg_q <= '0';
END IF;
END IF;
END PROCESS;
set_arbitration_lost_irq_xhdl24 <= (arbitration_lost AND (NOT arbitration_lost_q)) AND (NOT arbitration_blocked) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- read_error_code_capture_reg_q <= '0';
IF (clk'EVENT AND clk = '1') THEN
read_error_code_capture_reg_q <= read_error_code_capture_reg;
IF (rst = '1') THEN
read_error_code_capture_reg_q <= '0';
END IF;
END IF;
END PROCESS;
reset_error_code_capture_reg <= read_error_code_capture_reg_q and not read_error_code_capture_reg;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- arbitration_cnt_en <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR arbitration_blocked) = '1') THEN
arbitration_cnt_en <= '0' ;
ELSE
IF (((rx_id1 AND sample_point) AND (NOT arbitration_blocked)) = '1') THEN
arbitration_cnt_en <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
arbitration_cnt_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- arbitration_blocked <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR read_arbitration_lost_capture_reg) = '1') THEN
arbitration_blocked <= '0' ;
ELSE
IF (set_arbitration_lost_irq_xhdl24 = '1') THEN
arbitration_blocked <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
arbitration_blocked <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- arbitration_lost_capture_xhdl25 <= "00000";
IF (clk'EVENT AND clk = '1') THEN
IF (read_arbitration_lost_capture_reg_q = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000" ;
ELSE
IF ((((sample_point AND (NOT arbitration_blocked)) AND arbitration_cnt_en) AND (NOT bit_de_stuff)) = '1') THEN
arbitration_lost_capture_xhdl25 <= arbitration_lost_capture_xhdl25 + "00001" ;
END IF;
END IF;
IF (rst = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_err_cnt_xhdl15 <= "000000000";
IF (clk'EVENT AND clk = '1') THEN
IF (set_reset_mode_xhdl12 = '1') THEN
rx_err_cnt_xhdl15 <= "000000000" ;
else
IF (((NOT listen_only_mode) AND (NOT transmitter_xhdl8 OR arbitration_lost)) = '1') THEN
IF ((((go_rx_ack_lim AND (NOT go_error_frame_xhdl33)) AND (NOT crc_err)) AND CONV_STD_LOGIC(rx_err_cnt_xhdl15 > "000000000")) = '1') THEN
IF (rx_err_cnt_xhdl15 > "001111111") THEN
rx_err_cnt_xhdl15 <= "001111111" ;
ELSE
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 - "000000001" ;
END IF;
ELSE
IF (rx_err_cnt_xhdl15 < "010000000") THEN
IF ((go_error_frame_xhdl33 AND (NOT rule5)) = '1') THEN
-- 1 (rule 5 is just the opposite then rule 1 exception
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000000001" ;
ELSE
IF ((((((error_flag_over AND (NOT error_flag_over_latched)) AND sample_point) AND (NOT sampled_bit)) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111"))) = '1') THEN
-- 2
-- 5
-- 6
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
end if;
IF (rst = '1') THEN
rx_err_cnt_xhdl15 <= "000000000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_err_cnt_xhdl16 <= "000000000";
IF (clk'EVENT AND clk = '1') THEN
IF (set_reset_mode_xhdl12 = '1') THEN
tx_err_cnt_xhdl16 <= "010000000" ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 > "000000000") AND (tx_successful_xhdl19 OR bus_free)) = '1') THEN
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 - "000000001" ;
ELSE
IF ((transmitter_xhdl8 AND (NOT arbitration_lost)) = '1') THEN
IF ((((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((go_error_frame_xhdl33 AND (NOT ((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err))) AND (NOT (((((transmitter_xhdl8 AND stuff_err) AND arbitration_field) AND sample_point) AND tx_xhdl29) AND (NOT sampled_bit)))) OR (error_frame AND rule3_exc1_2)) = '1') THEN
-- 6
-- 4 (rule 5 is the same as rule 4)
-- 3
-- 3
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 + "000001000" ;
END IF;
END IF;
END IF;
end if;
IF (rst = '1') THEN
tx_err_cnt_xhdl16 <= "000000000";
END IF;
END IF;
END PROCESS;
set_reset_mode_xhdl12 <= node_bus_off_xhdl13 AND (NOT node_bus_off_q) ; --##
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- node_error_passive_xhdl26 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((rx_err_cnt_xhdl15 < "010000000") AND (tx_err_cnt_xhdl16 < "010000000")) THEN
node_error_passive_xhdl26 <= '0' ;
ELSE
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 >= "010000000") OR (tx_err_cnt_xhdl16 >= "010000000")) AND (error_frame_ended OR go_error_frame_xhdl33 OR ((NOT reset_mode) AND reset_mode_q))) AND (NOT node_bus_off_xhdl13)) = '1') THEN
node_error_passive_xhdl26 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
node_error_passive_xhdl26 <= '0';
END IF;
END IF;
END PROCESS;
node_error_active_xhdl27 <= NOT (node_error_passive_xhdl26 OR node_bus_off_xhdl13) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- node_bus_off_xhdl13 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ( (CONV_STD_LOGIC((rx_err_cnt_xhdl15 = "000000000") AND (tx_err_cnt_xhdl16 = "000000000")) AND (NOT reset_mode)) = '1' or restart = '1') THEN
node_bus_off_xhdl13 <= '0' ;
ELSE
IF (CONV_STD_LOGIC(tx_err_cnt_xhdl16 >= "100000000") = '1') THEN
node_bus_off_xhdl13 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
node_bus_off_xhdl13 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bus_free_cnt <= "0000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free_cnt <= "0000" ;
ELSE
IF (sample_point = '1') THEN
IF (((sampled_bit AND bus_free_cnt_en) AND CONV_STD_LOGIC(bus_free_cnt < "1010")) = '1') THEN
bus_free_cnt <= bus_free_cnt + "0001" ;
ELSE
bus_free_cnt <= "0000" ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
bus_free_cnt <= "0000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bus_free_cnt_en <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
bus_free_cnt_en <= '1' ;
ELSE
IF ((((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) AND (NOT node_bus_off_xhdl13)) = '1') THEN
bus_free_cnt_en <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
bus_free_cnt_en <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bus_free <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free <= '0';
ELSE
IF (((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) = '1') THEN
bus_free <= '1' ;
ELSE
bus_free <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
bus_free <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- waiting_for_bus_free <= '1';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
waiting_for_bus_free <= '1';
ELSE
IF ((bus_free AND (NOT node_bus_off_xhdl13)) = '1') THEN
waiting_for_bus_free <= '0' ;
ELSE
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
waiting_for_bus_free <= '1' ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
waiting_for_bus_free <= '1';
END IF;
END IF;
END PROCESS;
transmit_status_xhdl17 <= transmitting_xhdl7 OR (extended_mode AND waiting_for_bus_free) ;
temp_xhdl111 <= (waiting_for_bus_free OR ((NOT rx_idle_xhdl6) AND (NOT transmitting_xhdl7))) WHEN extended_mode = '1' ELSE (((NOT waiting_for_bus_free) AND (NOT rx_idle_xhdl6)) AND (NOT transmitting_xhdl7));
receive_status_xhdl18 <= temp_xhdl111 ;
-- Error code capture register
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_capture_code_xhdl5 <= "00000000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_error_code_capture_reg = '1') THEN
error_capture_code_xhdl5 <= "00000000" ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_xhdl5 <= error_capture_code_type(7 DOWNTO 6) & error_capture_code_direction & error_capture_code_segment(4 DOWNTO 0) ;
END IF;
END IF;
IF (rst = '1') THEN
error_capture_code_xhdl5 <= "00000000";
END IF;
END IF;
END PROCESS;
error_capture_code_segment(0) <= rx_idle_xhdl6 OR rx_ide OR (rx_id2 AND CONV_STD_LOGIC(bit_cnt < "001101")) OR rx_r1 OR rx_r0 OR rx_dlc OR rx_ack OR rx_ack_lim OR (error_frame AND node_error_active_xhdl27) ;
error_capture_code_segment(1) <= rx_idle_xhdl6 OR rx_id1 OR rx_id2 OR rx_dlc OR rx_data OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR (error_frame AND node_error_passive_xhdl26) ;
error_capture_code_segment(2) <= (rx_id1 AND CONV_STD_LOGIC(bit_cnt > "000111")) OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 OR rx_r1 OR (error_frame AND node_error_passive_xhdl26) OR overload_frame_xhdl4 ;
error_capture_code_segment(3) <= (rx_id2 AND CONV_STD_LOGIC(bit_cnt > "000100")) OR rx_rtr2 OR rx_r1 OR rx_r0 OR rx_dlc OR rx_data OR rx_crc OR rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR overload_frame_xhdl4 ;
error_capture_code_segment(4) <= rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR error_frame OR overload_frame_xhdl4 ;
error_capture_code_direction <= NOT transmitting_xhdl7 ;
PROCESS (bit_err, form_err, stuff_err)
VARIABLE error_capture_code_type_xhdl112 : std_logic_vector(7 DOWNTO 6);
BEGIN
IF (bit_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "00";
ELSE
IF (form_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "01";
ELSE
IF (stuff_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "10";
ELSE
error_capture_code_type_xhdl112(7 DOWNTO 6) := "11";
END IF;
END IF;
END IF;
error_capture_code_type <= error_capture_code_type_xhdl112;
END PROCESS;
set_bus_error_irq_xhdl23 <= go_error_frame_xhdl33 AND (NOT error_capture_code_blocked) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_capture_code_blocked <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (read_error_code_capture_reg = '1') THEN
error_capture_code_blocked <= '0' ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_blocked <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
error_capture_code_blocked <= '0';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_top
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_top.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_top.v,v $
-- Revision 1.48 2004/10/25 11:44:47 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.47 2004/02/08 14:53:54 mohor
-- Header changed. Address latched to posedge. bus_off_on signal added.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.44 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.43 2003/08/20 09:57:39 mohor
-- Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
-- to be joined together on higher level.
--
-- Revision 1.42 2003/07/16 15:11:28 mohor
-- Fixed according to the linter.
--
-- Revision 1.41 2003/07/10 15:32:27 mohor
-- Unused signal removed.
--
-- Revision 1.40 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.39 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.38 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.37 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.36 2003/06/17 14:30:30 mohor
-- "chip select" signal cs_can_i is used only when not using WISHBONE
-- interface.
--
-- Revision 1.35 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.34 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.33 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.32 2003/06/09 11:32:36 mohor
-- Ports added for the CAN_BIST.
--
-- Revision 1.31 2003/03/26 11:19:46 mohor
-- CAN interrupt is active low.
--
-- Revision 1.30 2003/03/20 17:01:17 mohor
-- unix.
--
-- Revision 1.28 2003/03/14 19:36:48 mohor
-- can_cs signal used for generation of the cs.
--
-- Revision 1.27 2003/03/12 05:56:33 mohor
-- Bidirectional port_0_i changed to port_0_io.
-- input cs_can changed to cs_can_i.
--
-- Revision 1.26 2003/03/12 04:39:40 mohor
-- rd_i and wr_i are active high signals. If 8051 is connected, these two signals
-- need to be negated one level higher.
--
-- Revision 1.25 2003/03/12 04:17:36 mohor
-- 8051 interface added (besides WISHBONE interface). Selection is made in
-- can_defines.v file.
--
-- Revision 1.24 2003/03/10 17:24:40 mohor
-- wire declaration added.
--
-- Revision 1.23 2003/03/05 15:33:13 mohor
-- tx_o is now tristated signal. tx_oen and tx_o combined together.
--
-- Revision 1.22 2003/03/05 15:01:56 mohor
-- Top level signal names changed.
--
-- Revision 1.21 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.20 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.19 2003/02/19 15:04:14 mohor
-- Typo fixed.
--
-- Revision 1.18 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.17 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.16 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.15 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.14 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.13 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.12 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.11 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.6 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.5 2003/01/08 02:10:56 mohor
-- Acceptance filter added.
--
-- Revision 1.4 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_top_core_sync IS
PORT (
clk : IN std_logic;
reset_n : IN std_logic;
-- Config
sjw : IN std_logic_vector(1 DOWNTO 0);
bitrate : IN std_logic_vector(10 DOWNTO 0); --##
tseg1 : IN std_logic_vector(3 DOWNTO 0);
tseg2 : IN std_logic_vector(2 DOWNTO 0);
auto_restart : IN std_logic;
sampling : IN std_logic;
edge_mode : IN std_logic;
-- Transmit buffer
tx_data : IN std_logic_vector(63 DOWNTO 0);
tx_id : IN std_logic_vector(28 DOWNTO 0);
tx_dlc : IN std_logic_vector(3 DOWNTO 0);
tx_rtr : IN std_logic;
tx_ide : IN std_logic;
tx_msg_rdy : OUT std_logic;
tx_request : IN std_logic;
-- start-stop control
clr_stop : IN std_logic;
set_stop : IN std_logic;
-- start-stop status
want_stop : OUT std_logic;
grant_stop : OUT std_logic;
-- Receive buffer
rx_data : OUT std_logic_vector(63 DOWNTO 0);
rx_id : OUT std_logic_vector(28 DOWNTO 0);
rx_dlc : OUT std_logic_vector(3 DOWNTO 0);
rx_rtr : OUT std_logic;
rx_ide : OUT std_logic;
rx_msg_rdy : OUT std_logic;
-- Interrupt events
crc_err : OUT std_logic;
form_err : OUT std_logic;
ack_err : OUT std_logic;
stuff_err : OUT std_logic;
bit_err : OUT std_logic;
arb_loss : OUT std_logic;
overload : OUT std_logic;
-- Status and error counters
error_state : OUT std_logic_vector(1 DOWNTO 0);
rx_err_gte96 : OUT std_logic;
tx_err_gte96 : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(7 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
-- CAN frame reference
rx_mode : OUT std_logic;
tx_mode : OUT std_logic;
field : OUT std_logic_vector(4 DOWNTO 0);
bit_nr : OUT std_logic_vector(5 DOWNTO 0);
stuff_ind : OUT std_logic;
remote_ind : OUT std_logic;
extended_ind : OUT std_logic;
-- CAN physical layer interface
can_rx_bus : IN std_logic;
can_tx_bus : OUT std_logic;
can_bus_ebl_n : OUT std_logic);
END ENTITY can_top_core_sync;
ARCHITECTURE RTL OF can_top_core_sync IS
COMPONENT can_bsp_core_sync
PORT (
clk : IN std_logic;
rst : IN std_logic;
restart : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
self_test_mode : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic;
overload_frame : OUT std_logic;
read_arbitration_lost_capture_reg: IN std_logic;
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
node_bus_off : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
rcv_msg_data : out std_logic_vector(63 downto 0);
rcv_id : out std_logic_vector(28 downto 0);
rcv_dlc : out std_logic_vector(3 downto 0);
rcv_rtr : out std_logic;
rcv_ide : out std_logic;
rcv_msg_valid : out std_logic;
form_error : out std_logic;
crc_error : out std_logic;
ack_error : out std_logic;
stuff_error : out std_logic;
bit_error : out std_logic;
arb_loss : out std_logic;
tx : OUT std_logic;
tx_next : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic);
END COMPONENT;
COMPONENT can_btl_core_sync
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
baud_r_presc : IN std_logic_vector(10 DOWNTO 0); --##
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END COMPONENT;
SIGNAL reset_mode : std_logic;
SIGNAL listen_only_mode : std_logic;
SIGNAL self_test_mode : std_logic;
SIGNAL abort_tx : std_logic;
SIGNAL self_rx_request : std_logic;
SIGNAL single_shot_transmission : std_logic;
SIGNAL tx_state : std_logic;
SIGNAL tx_state_q : std_logic;
SIGNAL overload_request : std_logic;
SIGNAL overload_frame : std_logic;
SIGNAL error_capture_code : std_logic_vector(7 DOWNTO 0);
-- Clock Divider register
SIGNAL extended_mode : std_logic;
-- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
SIGNAL tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12 : std_logic_vector(7 DOWNTO 0);
-- Output signals from can_btl_core_sync module
SIGNAL sample_point : std_logic;
SIGNAL sampled_bit : std_logic;
SIGNAL sampled_bit_q : std_logic;
SIGNAL tx_point : std_logic;
SIGNAL hard_sync : std_logic;
-- output from can_bsp_core_sync module
SIGNAL rx_idle : std_logic;
SIGNAL transmitting : std_logic;
SIGNAL transmitter : std_logic;
SIGNAL go_rx_inter : std_logic;
SIGNAL not_first_bit_of_inter : std_logic;
SIGNAL node_bus_off : std_logic;
SIGNAL transmit_status : std_logic;
SIGNAL receive_status : std_logic;
SIGNAL tx_successful : std_logic;
SIGNAL need_to_tx : std_logic;
SIGNAL overrun : std_logic;
SIGNAL node_error_passive : std_logic;
SIGNAL node_error_active : std_logic;
SIGNAL tx_next : std_logic;
SIGNAL go_overload_frame : std_logic;
SIGNAL go_error_frame : std_logic;
SIGNAL go_tx : std_logic;
SIGNAL send_ack : std_logic;
-- SIGNAL rst : std_logic;
SIGNAL rx_sync_tmp : std_logic;
SIGNAL rx_sync : std_logic;
SIGNAL xhdl_148 : std_logic_vector(8 DOWNTO 0);
SIGNAL xhdl_150 : std_logic_vector(8 DOWNTO 0);
SIGNAL tx_o_xhdl3 : std_logic;
SIGNAL rx_inter : std_logic;
signal rst, restart : std_logic;
signal ide, rtr : std_logic;
signal tx_req, tx_request_q, tx_success : std_logic;
BEGIN
rst <= not reset_n;
-- outputs
can_tx_bus <= tx_o_xhdl3;
can_bus_ebl_n <= '1' when reset_n = '0' else '1';
rx_err_cnt <= xhdl_148(7 DOWNTO 0);
tx_err_cnt <= xhdl_150(8 DOWNTO 0);
rx_err_gte96 <= '1' when unsigned(xhdl_148) >= 96 else '0';
tx_err_gte96 <= '1' when unsigned(xhdl_150) >= 96 else '0';
error_state(0) <= '0' when (node_error_active = '1') else '1';
error_state(1) <= '0' when (node_bus_off = '0') else '1';
tx_msg_rdy <= tx_success;
rx_rtr <= rtr;
rx_ide <= ide;
rx_mode <= receive_status;
tx_mode <= tx_state or tx_success; --## transmit_status;
remote_ind <= rtr;
extended_ind <= ide;
stuff_ind <= '0';
bit_nr <= (others => '0');
field <= (others => '0');
overload <= overload_frame;
want_stop <= '0';
grant_stop <= '0';
i_can_btl_core_sync : can_btl_core_sync
PORT MAP (
clk => clk,
rst => rst,
rx => rx_sync,
tx => tx_o_xhdl3,
baud_r_presc => bitrate, --##
sync_jump_width => sjw,
time_segment1 => tseg1,
time_segment2 => tseg2,
triple_sampling => sampling,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
rx_idle => rx_idle,
rx_inter => rx_inter,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
tx_next => tx_next,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
node_error_passive => node_error_passive);
-- TX format conversion
tx_data_0 <= tx_ide & tx_rtr & "00" & tx_dlc;
tx_data_1 <= tx_id(28 downto 21);
tx_data_2 <= tx_id(20 downto 18) & "00000" when tx_ide = '0' else tx_id(20 downto 13);
tx_data_3 <= tx_data(63 downto 56) when tx_ide = '0' else tx_id(12 downto 5);
tx_data_4 <= tx_data(55 downto 48) when tx_ide = '0' else tx_id(4 downto 0) & "000";
tx_data_5 <= tx_data(47 downto 40) when tx_ide = '0' else tx_data(63 downto 56);
tx_data_6 <= tx_data(39 downto 32) when tx_ide = '0' else tx_data(55 downto 48);
tx_data_7 <= tx_data(31 downto 24) when tx_ide = '0' else tx_data(47 downto 40);
tx_data_8 <= tx_data(23 downto 16) when tx_ide = '0' else tx_data(39 downto 32);
tx_data_9 <= tx_data(15 downto 8) when tx_ide = '0' else tx_data(31 downto 24);
tx_data_10 <= tx_data(7 downto 0) when tx_ide = '0' else tx_data(23 downto 16);
tx_data_11 <= tx_data(15 downto 8);
tx_data_12 <= tx_data(7 downto 0);
reset_mode <= '1' when rst = '1' else '0';
listen_only_mode <= '0';
self_test_mode <= '0';
extended_mode <= '1';
overload_request <= '0';
abort_tx <= '0';
self_rx_request <= '0';
single_shot_transmission <= '1'; --##
restart <= '1' when (auto_restart = '0' and clr_stop = '1') else '0';
-- generate pulse
process(clk,rst)
begin
if rst='1' then
tx_req <= '0';
elsif Rising_Edge(clk) then
if tx_request='1' and transmit_status='0' then
tx_req <= '1';
elsif transmit_status='1' then
tx_req <= '0';
end if;
end if;
end process;
i_can_bsp_core_sync : can_bsp_core_sync
PORT MAP (
clk => clk,
rst => rst,
restart => restart,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
self_test_mode => self_test_mode,
tx_request => tx_req, --## tx_request, --##
abort_tx => abort_tx,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => '0',
read_error_code_capture_reg => '0',
error_capture_code => open,
extended_mode => extended_mode,
rx_idle => rx_idle,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
not_first_bit_of_inter => not_first_bit_of_inter,
rx_inter => rx_inter,
node_bus_off => node_bus_off,
rx_err_cnt => xhdl_148,
tx_err_cnt => xhdl_150,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
set_bus_error_irq => open,
set_arbitration_lost_irq => open,
arbitration_lost_capture => open,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12,
rcv_msg_data => rx_data,
rcv_id => rx_id,
rcv_dlc => rx_dlc,
rcv_rtr => rtr,
rcv_ide => ide,
rcv_msg_valid => rx_msg_rdy,
form_error => form_err,
crc_error => crc_err,
ack_error => ack_err,
stuff_error => stuff_err,
bit_error => bit_err,
arb_loss => arb_loss,
tx => tx_o_xhdl3,
tx_next => tx_next,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack);
PROCESS (clk, rst)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (rst = '1') THEN
-- rx_sync_tmp <= '1';
rx_sync <= '1';
tx_request_q <= '0';
tx_success <= '0';
ELSE
-- rx_sync_tmp <= can_rx_bus;
-- rx_sync <= rx_sync_tmp ;
rx_sync <= can_rx_bus;
tx_request_q <= tx_request;
tx_success <= tx_successful;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/cache.vhd | 2 | 4459 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cache
-- File: cache.vhd
-- Author: Jiri Gaisler
-- Description: Cache controllers and AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
entity cache is
generic (
hindex : integer := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
cached : integer := 0;
clk2x : integer := 0;
memtech : integer range 0 to NTECH := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of cache is
signal icol : icache_out_type;
signal dcol : dcache_out_type;
signal mcii : memory_ic_in_type;
signal mcio : memory_ic_out_type;
signal mcdi : memory_dc_in_type;
signal mcdo : memory_dc_out_type;
signal ahbsi2 : ahb_slv_in_type;
signal ahbi2 : ahb_mst_in_type;
signal ahbo2 : ahb_mst_out_type;
signal gnd : std_ulogic;
begin
icache0 : icache
generic map (icen, irepl, isets, ilinesize, isetsize, isetlock, ilram,
ilramsize, ilramstart)
port map ( rst, clk, ici, icol, dci, dcol, mcii, mcio,
crami.icramin, cramo.icramo, fpuholdn);
dcache0 : dcache
generic map (dsu, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop,
dlram, dlramsize, dlramstart, ilram, ilramstart, memtech, cached)
port map ( rst, clk, dci, dcol, icol, mcdi, mcdo, ahbsi2,
crami.dcramin, cramo.dcramo, fpuholdn, sclk);
a0 : acache
generic map (hindex, ilinesize, cached, clk2x, scantest)
port map (rst, clk, mcii, mcio, mcdi, mcdo, ahbi2, ahbo2, ahbso, hclken);
ico <= icol;
dco <= dcol;
clk2xgen: if clk2x /= 0 generate
sync0 : clk2xsync generic map (hindex, clk2x)
port map (rst, hclk, clk, ahbi, ahbi2, ahbo2, ahbo, ahbsi, ahbsi2, mcii, mcdi, mcdo, gnd, gnd, hclken);
gnd <= '0';
end generate;
noclk2x : if clk2x = 0 generate
ahbsi2 <= ahbsi;
ahbi2 <= ahbi;
ahbo <= ahbo2;
end generate;
end ;
| mit |
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