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masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/user_logic.vhd | 8 | 29499 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library fsl_v20_v2_11_c;
use fsl_v20_v2_11_c.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_TM_BASE : std_logic_vector := x"11000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
-- Added in by Xilinx even though XST doesn't even recognize these attributes
--attribute SIGIS : string;
--attribute SIGIS of Bus2IP_Clk : signal is "CLK";
--attribute SIGIS of Bus2IP_Reset : signal is "RST";
--attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
-- Define the memory map for each command register, Address[13 to 14]
-- This value is the offset from the base address assigned to this module
constant OPCODE_ENQUEUE : std_logic_vector(0 to 2-1) := "10"; --conv_std_logic_vector(2, 2); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to 2-1) := "01"; --conv_std_logic_vector(1, 2); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to 2-1) := "11"; --conv_std_logic_vector(3, 2); -- Opcode for "broadcast" dequeue
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Reset Signals
-- FIXME: It would be nice to eliminate the default values here
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal Enqueue_Request : std_logic;
signal Dequeue_Request : std_logic;
signal Dequeue_All_Request : std_logic;
signal Error_Request : std_logic;
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_core,
reset_wait_4_ack,
enqueue_begin,
enqueue_finish,
dequeue_begin,
dequeue_finish,
dequeueAll_begin,
dequeueAll_finish
);
signal current_state, next_state : master_state_type := idle;
--cvCore Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to 1) := (others => '0');
signal cvar : std_logic_vector(0 to 7) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal reset_sig : std_logic := '0';
-- cvCore Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
-- Message channels signals
signal FSL_S_Read : std_logic;
signal FSL_S_Exists : std_logic;
signal FSL_Has_Data : std_logic;
signal FSL_Data : std_logic_vector(0 to 7);
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstRdReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
component fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer;
C_ASYNC_CLKS : integer;
C_IMPL_STYLE : integer;
C_USE_CONTROL : integer;
C_FSL_DWIDTH : integer;
C_FSL_DEPTH : integer;
C_READ_CLOCK_PERIOD : integer
);
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
component condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component condvar;
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
function getCVAR( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return "00" & addr(24 to 29);
end function;
function getTID( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return addr(16 to 23);
end function;
function form_tm_addr( tid : in std_logic_vector(0 to 7)) return std_logic_vector is
variable mask : std_logic_vector(0 to 31);
begin
mask := x"00001" & "00" & tid & "00";
return C_TM_BASE or mask;
end function;
--*************************************************
-- Beginning of user_logic ARCHITECTURE
--*************************************************
begin
-- Instantiate the CV Core
cvCore: condvar PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
cmd => cmd,
opcode => opcode,
cvar => cvar,
tid => tid,
ack => ack,
clock_sig => Bus2IP_Clk,
reset_sig => reset_sig
);
message_channel : fsl_v20
generic map (
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 1,
C_USE_CONTROL => 0,
C_FSL_DWIDTH => 8,
C_FSL_DEPTH => 256,
C_READ_CLOCK_PERIOD => 0
)
port map (
FSL_Clk => Bus2IP_Clk,
SYS_Rst => Bus2IP_Reset,
FSL_Rst => open,
FSL_M_Clk => Bus2IP_Clk,
FSL_M_Data => msg_chan_channelDataIn,
FSL_M_Control => '0',
FSL_M_Write => msg_chan_channelWrite,
FSL_M_Full => msg_chan_full,
FSL_S_Clk => Bus2IP_Clk,
FSL_S_Data => FSL_Data,
FSL_S_Control => open,
FSL_S_Read => FSL_S_Read,
FSL_S_Exists => FSL_S_Exists,
FSL_Full => open,
FSL_Has_Data => FSL_Has_Data,
FSL_Control_IRQ => open
);
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= FSL_S_Exists; -- Start master transaction when data exists in the FSL
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
FSL_S_Read <= '0';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '1'; -- Perform a write (rd = '1', wr = '0')
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_ip2bus_addr <= form_tm_addr(FSL_Data); -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Enqueue_Request <= '0';
Dequeue_Request <= '0';
Dequeue_All_Request <= '0';
Error_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
Error_Request <= '1';
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(13 to 14) is
when OPCODE_ENQUEUE => Enqueue_Request <= '1';
when OPCODE_DEQUEUE => Dequeue_Request <= '1';
when OPCODE_DEQUEUE_ALL => Dequeue_All_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC: process(
Bus2IP_Clk, Soft_Reset, inside_reset, inside_reset_next, next_state) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state <= reset;
inside_reset <= '1';
else
-- Assign all signals to their next state...
current_state <= next_state;
inside_reset <= inside_reset_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC: process (
current_state, inside_reset, Enqueue_Request, Dequeue_Request,
Dequeue_All_Request, Error_Request, Bus2IP_Data, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, Bus2IP_Addr, ack ) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 3);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
next_state <= current_state;
inside_reset_next <= inside_reset;
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
reset_sig <= '0';
case current_state is
when idle =>
-- Assign to variable for case statement
idle_concat := (Enqueue_Request & Dequeue_Request & Dequeue_All_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "1000" => next_state <= enqueue_begin; -- Enqueue
when "0100" => next_state <= dequeue_begin; -- Dequeue
when "0010" => next_state <= dequeueAll_begin; -- DequeueAll
when "0001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others => next_state <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state <= idle;
end if;
----------------------------
-- RESET: begin
----------------------------
when reset =>
reset_sig <= '1'; -- begin reset on cvCore
Reset_Done <= '0'; -- De-assert Reset_Done
next_state <= reset_core;
when reset_core =>
if (ack = '1') then
next_state <= reset_wait_4_ack;
else
next_state <= reset_core;
end if;
when reset_wait_4_ack =>
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
next_state <= idle; -- return to idle stage
end if;
----------------------------
-- RESET: end
----------------------------
----------------------------
-- ENQ: begin
----------------------------
when enqueue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_ENQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= enqueue_finish;
else
-- Persist with request and remain
next_state <= enqueue_begin;
end if;
when enqueue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- DEQ: begin
----------------------------
when dequeue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeue_finish;
else
-- Persist with request and remain
next_state <= dequeue_begin;
end if;
when dequeue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- DEQ: begin
----------------------------
when dequeueAll_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE_ALL;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeueAll_finish;
else
-- Persist with request and remain
next_state <= dequeueAll_begin;
end if;
when dequeueAll_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others =>
next_state <= idle;
end case; -- END CASE (current_state)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/pr_6smp/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/user_logic.vhd | 8 | 29499 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library fsl_v20_v2_11_c;
use fsl_v20_v2_11_c.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_TM_BASE : std_logic_vector := x"11000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
-- Added in by Xilinx even though XST doesn't even recognize these attributes
--attribute SIGIS : string;
--attribute SIGIS of Bus2IP_Clk : signal is "CLK";
--attribute SIGIS of Bus2IP_Reset : signal is "RST";
--attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
-- Define the memory map for each command register, Address[13 to 14]
-- This value is the offset from the base address assigned to this module
constant OPCODE_ENQUEUE : std_logic_vector(0 to 2-1) := "10"; --conv_std_logic_vector(2, 2); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to 2-1) := "01"; --conv_std_logic_vector(1, 2); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to 2-1) := "11"; --conv_std_logic_vector(3, 2); -- Opcode for "broadcast" dequeue
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Reset Signals
-- FIXME: It would be nice to eliminate the default values here
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal Enqueue_Request : std_logic;
signal Dequeue_Request : std_logic;
signal Dequeue_All_Request : std_logic;
signal Error_Request : std_logic;
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_core,
reset_wait_4_ack,
enqueue_begin,
enqueue_finish,
dequeue_begin,
dequeue_finish,
dequeueAll_begin,
dequeueAll_finish
);
signal current_state, next_state : master_state_type := idle;
--cvCore Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to 1) := (others => '0');
signal cvar : std_logic_vector(0 to 7) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal reset_sig : std_logic := '0';
-- cvCore Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
-- Message channels signals
signal FSL_S_Read : std_logic;
signal FSL_S_Exists : std_logic;
signal FSL_Has_Data : std_logic;
signal FSL_Data : std_logic_vector(0 to 7);
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstRdReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
component fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer;
C_ASYNC_CLKS : integer;
C_IMPL_STYLE : integer;
C_USE_CONTROL : integer;
C_FSL_DWIDTH : integer;
C_FSL_DEPTH : integer;
C_READ_CLOCK_PERIOD : integer
);
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
component condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component condvar;
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
function getCVAR( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return "00" & addr(24 to 29);
end function;
function getTID( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return addr(16 to 23);
end function;
function form_tm_addr( tid : in std_logic_vector(0 to 7)) return std_logic_vector is
variable mask : std_logic_vector(0 to 31);
begin
mask := x"00001" & "00" & tid & "00";
return C_TM_BASE or mask;
end function;
--*************************************************
-- Beginning of user_logic ARCHITECTURE
--*************************************************
begin
-- Instantiate the CV Core
cvCore: condvar PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
cmd => cmd,
opcode => opcode,
cvar => cvar,
tid => tid,
ack => ack,
clock_sig => Bus2IP_Clk,
reset_sig => reset_sig
);
message_channel : fsl_v20
generic map (
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 1,
C_USE_CONTROL => 0,
C_FSL_DWIDTH => 8,
C_FSL_DEPTH => 256,
C_READ_CLOCK_PERIOD => 0
)
port map (
FSL_Clk => Bus2IP_Clk,
SYS_Rst => Bus2IP_Reset,
FSL_Rst => open,
FSL_M_Clk => Bus2IP_Clk,
FSL_M_Data => msg_chan_channelDataIn,
FSL_M_Control => '0',
FSL_M_Write => msg_chan_channelWrite,
FSL_M_Full => msg_chan_full,
FSL_S_Clk => Bus2IP_Clk,
FSL_S_Data => FSL_Data,
FSL_S_Control => open,
FSL_S_Read => FSL_S_Read,
FSL_S_Exists => FSL_S_Exists,
FSL_Full => open,
FSL_Has_Data => FSL_Has_Data,
FSL_Control_IRQ => open
);
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= FSL_S_Exists; -- Start master transaction when data exists in the FSL
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
FSL_S_Read <= '0';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '1'; -- Perform a write (rd = '1', wr = '0')
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_ip2bus_addr <= form_tm_addr(FSL_Data); -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Enqueue_Request <= '0';
Dequeue_Request <= '0';
Dequeue_All_Request <= '0';
Error_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
Error_Request <= '1';
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(13 to 14) is
when OPCODE_ENQUEUE => Enqueue_Request <= '1';
when OPCODE_DEQUEUE => Dequeue_Request <= '1';
when OPCODE_DEQUEUE_ALL => Dequeue_All_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC: process(
Bus2IP_Clk, Soft_Reset, inside_reset, inside_reset_next, next_state) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state <= reset;
inside_reset <= '1';
else
-- Assign all signals to their next state...
current_state <= next_state;
inside_reset <= inside_reset_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC: process (
current_state, inside_reset, Enqueue_Request, Dequeue_Request,
Dequeue_All_Request, Error_Request, Bus2IP_Data, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, Bus2IP_Addr, ack ) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 3);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
next_state <= current_state;
inside_reset_next <= inside_reset;
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
reset_sig <= '0';
case current_state is
when idle =>
-- Assign to variable for case statement
idle_concat := (Enqueue_Request & Dequeue_Request & Dequeue_All_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "1000" => next_state <= enqueue_begin; -- Enqueue
when "0100" => next_state <= dequeue_begin; -- Dequeue
when "0010" => next_state <= dequeueAll_begin; -- DequeueAll
when "0001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others => next_state <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state <= idle;
end if;
----------------------------
-- RESET: begin
----------------------------
when reset =>
reset_sig <= '1'; -- begin reset on cvCore
Reset_Done <= '0'; -- De-assert Reset_Done
next_state <= reset_core;
when reset_core =>
if (ack = '1') then
next_state <= reset_wait_4_ack;
else
next_state <= reset_core;
end if;
when reset_wait_4_ack =>
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
next_state <= idle; -- return to idle stage
end if;
----------------------------
-- RESET: end
----------------------------
----------------------------
-- ENQ: begin
----------------------------
when enqueue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_ENQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= enqueue_finish;
else
-- Persist with request and remain
next_state <= enqueue_begin;
end if;
when enqueue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- DEQ: begin
----------------------------
when dequeue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeue_finish;
else
-- Persist with request and remain
next_state <= dequeue_begin;
end if;
when dequeue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- DEQ: begin
----------------------------
when dequeueAll_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE_ALL;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeueAll_finish;
else
-- Persist with request and remain
next_state <= dequeueAll_begin;
end if;
when dequeueAll_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others =>
next_state <= idle;
end case; -- END CASE (current_state)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/addsub.vhd | 2 | 10864 | -------------------------------------------------------------------------------
-- $Id: addsub.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Either add an ArgA or subtract an ArgS from an ArgD.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: addsub.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description:
-- Either add an ArgA or subtract an ArgS from an ArgD. The
-- output, Result, can be optionally combinatorial or registered.
--
-- When C_REGISTERED is false, Result will take on one of
-- two values:
--
-- ArgD - ArgS, when Sub is asserted, or
-- ArgD + ArgA, when Sub is not asserted.
--
-- Cry_BrwN will be '1' if ArgD + ArgA produces a carry
-- and it will be '0' if ArgD - ArgS produces a borrow.
--
-- The signals Clk, Rst and CE are meaningful and used only
-- if C_REGISTERED is true. These may be "tied off" to any
-- std_logic value in combinatorial instantiations (e.g.
-- connected to '0').
--
-- This table details the operation in registered mode:
--
-- Clk Rst CE Sub <Cry_BrwN, Result>
-- --- --- -- --- ------------------
-- _
-- _| 1 x x 0
--
-- _
-- _| 0 1 0 ArgD + ArgA
--
-- _
-- _| 0 1 1 ArgD - ArgS
--
-- _
-- _| 0 0 x No change
--
-- _
-- not _| x x x No change
--
-------------------------------------------------------------------------------
-- Structure:
--
-- addsub.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/14/2003 -- First version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity addsub is
generic (
C_WIDTH : natural := 8;
C_REGISTERED : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic; -- Reset Result and Cry_BrwN to zero
CE : in std_logic;
ArgD : in std_logic_vector(0 to C_WIDTH-1);
ArgA : in std_logic_vector(0 to C_WIDTH-1);
ArgS : in std_logic_vector(0 to C_WIDTH-1);
Sub : in std_logic;
Cry_BrwN : out std_logic;
Result : out std_logic_vector(0 to C_WIDTH-1)
);
end addsub;
library unisim;
use unisim.VCOMPONENTS.FDRE;
use unisim.VCOMPONENTS.MUXCY;
use unisim.VCOMPONENTS.XORCY;
library ieee;
use ieee.numeric_std.all;
architecture imp of addsub is
signal lutout,
xorcy_out : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
begin
cry(C_WIDTH) <= Sub;
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
begin
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
lutout(j) <= ArgD(j) xor ArgA(j) when Sub = '0' else
ArgD(j) xnor ArgS(j);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => ArgD(j),
CI => cry(j+1),
S => lutout(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lutout(j),
CI => cry(j+1),
O => xorcy_out(j)
);
------------------------------------------------------------------------
-- Result, combinatorial or registered.
------------------------------------------------------------------------
COM_GEN : if not C_REGISTERED generate
Result(j) <= xorcy_out(j);
end generate;
-- else
REG_GEN : if C_REGISTERED generate
FDRE_I1: FDRE
port map (
Q => Result(j),
C => Clk,
CE => CE,
D => xorcy_out(j),
R => Rst
);
end generate;
end generate;
----------------------------------------------------------------------------
-- Cry_BrwN, combinatorial or registered.
----------------------------------------------------------------------------
COM_GEN : if not C_REGISTERED generate
Cry_BrwN <= cry(0);
end generate;
-- else
REG_GEN : if C_REGISTERED generate
FDRE_I1: FDRE
port map (
Q => Cry_BrwN,
C => Clk,
CE => CE,
D => cry(0),
R => Rst
);
end generate;
end imp;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_v20_v1_10_d/hdl/vhdl/park_lock_logic.vhd | 3 | 24460 | -------------------------------------------------------------------------------
-- $Id: park_lock_logic.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- park_lock_logic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: park_lock_logic.vhd
-- Version: v1.02e
-- Description:
-- This file contains the grant_last_register logic, the park
-- logic, and the grant_logic which determines the final grant
-- signal to the Masters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/24/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- Modified the code so that the arbitration cycle and/or the internal grant
-- register enables are based off the external grants, i.e., grants output
-- to the bus taking into account buslock and park.
-- This file now generates Any_mgrant which indicates when any external grant
-- is asserted and Bus_park which indicates when the bus is parked. Also,
-- OPB_buslock now gates the internal grant signals and bus parking.
-- ~~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- LCW 02/04/05 - update library statements
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
-- Package file that contains constant definition for RESET_ACTIVE and function
-- pad_4
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_MASTERS -- number of Masters
-- C_NUM_MID_BITS -- number of bits required for master IDs
-- C_PARK -- parking supported
-- C_REG_GRANTS -- register grant outputs
--
-- Definition of Ports:
--
-- input Arb_cycle -- Valid arbitration cycle
-- input OPB_buslock -- Bus is locked
--
-- -- Control register interface
-- input Park_master_notlast -- Park on Master not last
-- input Park_master_id -- Master ID to park on
-- input Park_enable -- Enable parking
--
-- -- Intermediate grant signals from arbitration logic
-- input Grant
--
-- -- Master request signals
-- input M_request
--
-- -- Final Master grant signals
-- output Opb_mgrant -- output grants to masters
-- -- may be registered if C_REG_GRANTS=true
-- output MGrant -- cmb grant outputs to priority reg logic
-- output MGrant_n -- cmb active low grant signals to
-- -- priority reg logic
--
-- -- Clock and reset
-- input Clk;
-- input Rst;
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity park_lock_logic is
generic( C_NUM_MASTERS : integer := 8;
C_NUM_MID_BITS : integer := 3;
C_PARK : boolean := false;
C_REG_GRANTS : boolean := true );
port (
Arb_cycle : in std_logic;
OPB_buslock : in std_logic;
Park_master_notlast : in std_logic;
Park_master_id : in std_logic_vector(0 to C_NUM_MID_BITS-1);
Park_enable : in std_logic;
Grant : in std_logic_vector(0 to C_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1);
Bus_park : out std_logic;
Any_mgrant : out std_logic;
OPB_Mgrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
Mgrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
MGrant_n : out std_logic_vector(0 to C_NUM_MASTERS-1);
Clk : in std_logic;
Rst : in std_logic
);
end park_lock_logic;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of park_lock_logic is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- pad number of masters(requests) and Park_enable to nearest multiple of 4
constant NUM_REQ_PAD : integer := pad_4(C_NUM_MASTERS);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- 1-hot register indicating which master was granted the bus
signal grant_last_reg : std_logic_vector(0 to C_NUM_MASTERS-1);
-- Signal indicating that a grant was asserted
signal any_grant : std_logic;
-- 1-hot bus indicating which master has locked the bus
signal locked : std_logic_vector(0 to C_NUM_MASTERS-1);
-- 1-hot bus indicating which master the bus is parked on
signal park : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal park_d1 : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal park_fe : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- signal indicating if other masters are parked
signal others_park : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- signals indicating if other masters are requesting the bus
signal pend_req_cmb : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal pend_req : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- indicates if any master is requesting the bus
signal any_request : std_logic_vector(0 to 0) := (others => '0');
-- internal grant signals
signal mgrant_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal mgrant_n_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal mgrant_reg_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Xilinx primitives are used to generate the PARK signals
-- OR_BITS is used to OR all of the Grant signals so that the Grant_last_reg
-- can be updated.
-- OR_GATE is used to determine if there are any pending requests for the
-- park logic and to determine if any master is parked
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- GRANT_LAST_REGISTER registers the grant signals for use in determining
-- parking and locking.
-- This register is clock enabled by the OR of all the Master grant signals,
-- i.e. only register the grant signals when a new grant has been issued.
-- Note that the GRANT_LAST_REGISTER uses registered internal grant signals
-- when design is configured for registered grant outputs. It uses combinational
-- grant signals when configured for combinational internal grant outputs
-------------------------------------------------------------------------------
REGGRNTS_LASTGRNT: if C_REG_GRANTS generate
begin
-- use internal registered grant signals
OR_GRANTS_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => mgrant_reg_i,
Sig => '0',
Or_out => any_grant
);
LASTGRNT_REG_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
grant_last_reg <= (others => '0');
elsif any_grant = '1' then
grant_last_reg <= mgrant_reg_i;
else
grant_last_reg <= grant_last_reg;
end if;
end if;
end process LASTGRNT_REG_PROCESS;
end generate REGGRNTS_LASTGRNT;
CMBGRNTS_LASTGRNT: if not(C_REG_GRANTS) generate
begin
-- use internal combinational grant signals
OR_GRANTS_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => mgrant_i,
Sig => '0',
Or_out => any_grant
);
LASTGRNT_REG_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
grant_last_reg <= (others => '0');
elsif any_grant = '1' then
grant_last_reg <= mgrant_i;
else
grant_last_reg <= grant_last_reg;
end if;
end if;
end process LASTGRNT_REG_PROCESS;
end generate CMBGRNTS_LASTGRNT;
-------------------------------------------------------------------------------
-- LOCK signals indicate which Master (if any) has locked the bus. Only a Master
-- which has been granted the bus and is still requesting can lock it.
-------------------------------------------------------------------------------
LOCK_GEN: for i in 0 to C_NUM_MASTERS-1 generate
locked(i) <= '1' when grant_last_reg(i) = '1' and OPB_buslock = '1'
else '0';
end generate LOCK_GEN;
-------------------------------------------------------------------------------
-- PARK signals indicate which Master to park the bus on based on the Park
-- Enable, Park Master Not Last, and Park Master ID bits in the Control
-- Register. This code is only implemented if C_PARK=true indicating that
-- parking is supported. If C_PARK=false, the park bus and all OPB park signals
-- stay at their default values of 0.
-------------------------------------------------------------------------------
PARKLOGIC_GEN: if C_PARK generate
-- For each master, must determine if there are any other requests and if parking is enabled
PENDREQ_GEN: for i in 0 to C_NUM_MASTERS-1 generate
signal or_gate_input : std_logic_vector(0 to C_NUM_MASTERS-2);
begin
OR_ALL_BUT_SELF_PROCESS: process (M_request) is
variable k : integer := 0;
begin
for j in 0 to i-1 loop
or_gate_input(j) <= M_request(j);
end loop;
for j in i+1 to C_NUM_MASTERS-1 loop
or_gate_input(j-1) <= M_request(j);
end loop;
end process OR_ALL_BUT_SELF_PROCESS;
PENDREQ_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS-1,1,TRUE)
port map (or_gate_input,pend_req(i to i));
end generate PENDREQ_GEN;
-- If parking is enabled and there are no pending requests, then determine
-- which master to park on based on the PMNL bit.
-- If park on master not last = 0, then park on last master, i.e, park =
-- grant_last_reg. Otherwise, park on master whose ID is set in control register.
-- Register the master's park signals
PARK_GEN: for i in 0 to C_NUM_MASTERS-1 generate
signal park_or_gate_input : std_logic_vector(0 to C_NUM_MASTERS-2);
begin
PARK_PROCESS: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
park(i) <= '0';
elsif pend_req(i) = '0' and Park_enable = '1' then
if Park_master_notlast = '1' then
if Park_master_id = conv_std_logic_vector(i, C_NUM_MID_BITS) then
park(i) <= '1';
else
park(i) <= '0';
end if;
else
park(i) <= grant_last_reg(i);
end if;
else
park(i) <= '0';
end if;
end if;
end process PARK_PROCESS;
-- When the grant outputs are registered, the parked master's grant won't negate
-- until a clock after parking is disabled. Since the park bus is registered,
-- the grant signal must negate as soon as possible after the park bus negates,
-- therefore, use the falling edge of each masters' park to asynchronously reset
-- that master's OPB_MGrant register.
PARK_D1_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
park_d1(i) <= '0';
else
park_d1(i) <= park(i);
end if;
end if;
end process PARK_D1_PROCESS;
park_fe(i) <= '1' when park(i) = '0' and park_d1(i) = '1'
else '0';
-- determine if other masters are parked so that the grant from the arbitration
-- logic can be properly gated.
OR_ALLPARK_BUT_SELF_PROCESS: process (park) is
variable k : integer := 0;
begin
for j in 0 to i-1 loop
park_or_gate_input(j) <= park(j);
end loop;
for j in i+1 to C_NUM_MASTERS-1 loop
park_or_gate_input(j-1) <= park(j);
end loop;
end process OR_ALLPARK_BUT_SELF_PROCESS;
OTHERSPARK_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS-1,1,TRUE)
port map (park_or_gate_input,others_park(i to i));
end generate PARK_GEN;
-- determine if parked on any master
OR_PARK_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => park,
Sig => '0',
Or_out => Bus_park
);
end generate PARKLOGIC_GEN;
NOPARK_GEN: if not(C_PARK) generate
Bus_park <= '0';
park <= (others => '0');
others_park <= (others => '0');
park_fe <= (others => '0');
end generate NOPARK_GEN;
-------------------------------------------------------------------------------
-- GRANT_LOGIC determines the final Master grant signals based on the park/lock
-- signals and the intermediate grant signals from the arbitration logic.
-- The MGrant signals are always combinatorial and are used by the priority
-- register logic.
-------------------------------------------------------------------------------
GRANT_GEN: for i in 0 to C_NUM_MASTERS-1 generate
mgrant_i(i) <= '1' when arb_cycle = '1' and
((grant(i)='1' and others_park(i)='0' and OPB_buslock = '0')
or (park(i) = '1' and OPB_buslock = '0')
or (locked(i) = '1' and M_request(i)='1'))
else '0';
mgrant_n_i(i) <= '0' when arb_cycle = '1' and
((grant(i)='1' and others_park(i)='0' and OPB_buslock = '0')
or (park(i) = '1' and OPB_buslock = '0')
or (locked(i) = '1' and M_request(i)='1'))
else '1';
-- Register the grant signals if registered grant outputs
-- reset this register with park_fe
REGGRNT_GEN: if (C_REG_GRANTS) generate
REGGRNT_PROCESS: process (Clk, park_fe(i))
begin
-- asynchronously reset when park negates
if park_fe(i) = '1' then
mgrant_reg_i(i) <= '0';
elsif Clk'event and Clk='1' then
if Rst = RESET_ACTIVE then
mgrant_reg_i(i) <= '0';
else
mgrant_reg_i(i) <= mgrant_i(i);
end if;
end if;
end process REGGRNT_PROCESS;
end generate REGGRNT_GEN;
end generate GRANT_GEN;
-------------------------------------------------------------------------------
-- Assign internal signals to outputs
-- Master grant signal outputs are registered or combinatorial based on the
-- C_REG_GRANTS parameter.
-------------------------------------------------------------------------------
MGrant <= mgrant_i;
MGrant_n <= mgrant_n_i;
Any_mgrant <= any_grant;
REGGRANT_GEN: if C_REG_GRANTS generate
OPB_MGrant <= mgrant_reg_i;
end generate REGGRANT_GEN;
CMBGRANT_GEN: if not(C_REG_GRANTS) generate
OPB_MGrant <= mgrant_i;
end generate CMBGRANT_GEN;
end implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/opb_SynchManager_v1_00_c/hdl/vhdl/lock_fsm.vhd | 11 | 8253 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity lock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end lock_fsm;
architecture behavioral of lock_fsm is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
READ,
DONE,
UPDATE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
else
lock_cs <= lock_ns;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast,minext) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case lock_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
lock_ns <= READ;
end if;
when READ =>
lock_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
finish <= '1';
lock_ns <= IDLE;
else
if( mikind = SYNCH_ERROR and miowner = thread ) then
data(0) <= '1';
finish <= '1';
lock_ns <= IDLE;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
finish <= '1';
lock_ns <= IDLE;
elsif( minext = miowner ) then
toaddr <= thread;
toena <= '1';
towea <= '1';
tonext <= thread;
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= thread;
molast <= thread;
mocount <= micount;
mokind <= mikind;
finish <= '1';
data(1) <= '1';
lock_ns <= IDLE;
else
toaddr <= milast;
toena <= '1';
towea <= '1';
tonext <= thread;
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= thread;
mocount <= micount;
mokind <= mikind;
finish <= '0';
lock_ns <= UPDATE;
end if;
end if;
when UPDATE =>
toaddr <= thread;
toena <= '1';
towea <= '1';
tonext <= thread;
finish <= '1';
data(1) <= '1';
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/lock_fsm.vhd | 11 | 8253 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity lock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end lock_fsm;
architecture behavioral of lock_fsm is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
READ,
DONE,
UPDATE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
else
lock_cs <= lock_ns;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast,minext) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case lock_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
lock_ns <= READ;
end if;
when READ =>
lock_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
finish <= '1';
lock_ns <= IDLE;
else
if( mikind = SYNCH_ERROR and miowner = thread ) then
data(0) <= '1';
finish <= '1';
lock_ns <= IDLE;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
finish <= '1';
lock_ns <= IDLE;
elsif( minext = miowner ) then
toaddr <= thread;
toena <= '1';
towea <= '1';
tonext <= thread;
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= thread;
molast <= thread;
mocount <= micount;
mokind <= mikind;
finish <= '1';
data(1) <= '1';
lock_ns <= IDLE;
else
toaddr <= milast;
toena <= '1';
towea <= '1';
tonext <= thread;
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= thread;
mocount <= micount;
mokind <= mikind;
finish <= '0';
lock_ns <= UPDATE;
end if;
end if;
when UPDATE =>
toaddr <= thread;
toena <= '1';
towea <= '1';
tonext <= thread;
finish <= '1';
data(1) <= '1';
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
| bsd-3-clause |
jevinskie/aes-over-pcie | source/key_scheduler.vhd | 1 | 9583 | -- File name: key_scheduler.vhd
-- Created: 2009-03-30
-- Author: Matt Swanson
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: Rijndael KeyScheduler
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity key_scheduler is
port (
clk : in std_logic;
nrst : in std_logic;
go : in std_logic;
round : in round_type;
key_data : in byte;
key_index : in g_index;
key_load : in std_logic;
round_key : out key_type;
done : out std_logic
);
type rcon_array is array (0 to 10) of byte;
constant rcon_tbl : rcon_array :=
(
x"8d", x"01", x"02", x"04", x"08", x"10", x"20", x"40",
x"80", x"1b", x"36"
);
end key_scheduler;
architecture behavioral of key_scheduler is
type state_type is (
idle, load_key, rotate, sub_bytes, add_cols, rcon, be_done
);
signal state : state_type;
signal next_state : state_type;
signal cur_key : key_type;
signal next_cur_key : key_type;
signal new_key : key_type;
signal next_new_key : key_type;
signal c : index;
signal next_c : index;
signal c_clr : std_logic;
signal c_up : std_logic;
signal r : index;
signal next_r : index;
signal r_clr : std_logic;
signal sbox_return_reged : byte;
signal sbox_lookup, sbox_return : byte;
begin
sbox_b : entity work.sbox(dataflow) port map (
clk => clk, a => sbox_lookup, b => sbox_return
);
-- leda C_1406 off
state_reg : process(clk, nrst)
begin
if (nrst = '0') then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
cur_key <= next_cur_key;
new_key <= next_new_key;
end if;
end process state_reg;
-- leda C_1406 on
state_nsl : process(state, go, r, c, round)
begin
next_state <= idle;
case state is
when idle =>
if (go = '1' and round = 0) then
next_state <= load_key;
elsif (go = '1') then
next_state <= rotate;
else
next_state <= idle;
end if;
when load_key =>
next_state <= be_done;
when rotate =>
next_state <= sub_bytes;
when sub_bytes =>
if (r /= 3) then
next_state <= sub_bytes;
else
next_state <= rcon;
end if;
when rcon =>
next_state <= add_cols;
when add_cols =>
if (r = 3 and c = 3) then
next_state <= be_done;
else
next_state <= add_cols;
end if;
when be_done =>
next_state <= idle;
end case;
end process state_nsl;
state_out : process(state, cur_key, new_key, key_data,
key_index, key_load,
sbox_return_reged, c, r, round)
variable temp_index : index;
begin
next_cur_key <= cur_key;
next_new_key <= new_key;
c_up <= '0';
c_clr <= '0';
r_clr <= '0';
done <= '0';
sbox_lookup <= (others => '-');
case state is
when idle =>
if (key_load = '1') then
next_new_key(key_index mod 4, key_index / 4) <= key_data;
end if;
when load_key =>
-- nothing
when rotate =>
r_clr <= '1';
c_clr <= '1';
sbox_lookup <= cur_key(1, 3);
for i in index loop
next_new_key(i, 0) <= cur_key(to_integer(to_unsigned(i, 2) + 1), 3);
end loop;
when sub_bytes =>
sbox_lookup <= new_key(to_integer(to_unsigned(r, 2) + 1), 0);
next_new_key(r, c) <= sbox_return_reged;
when rcon =>
-- leda DFT_021 off
next_new_key(0, 0) <= new_key(0, 0) xor rcon_tbl(round);
-- leda DFT_021 on
c_clr <= '1';
r_clr <= '1';
when add_cols =>
if (c = 0) then
temp_index := 0;
else
temp_index := c - 1;
end if;
next_new_key(r, c) <= new_key(r, temp_index) xor cur_key(r, c);
if (r = 3) then
c_up <= '1';
end if;
when be_done =>
next_cur_key <= new_key;
done <= '1';
end case;
end process state_out;
-- leda C_1406 off
c_counter_reg : process(clk)
begin
if rising_edge(clk) then
c <= next_c;
end if;
end process c_counter_reg;
-- leda C_1406 on
c_counter_nsl : process(c, c_up, c_clr)
begin
if (c_clr = '1') then
next_c <= 0;
elsif (c_up = '1') then
next_c <= to_integer(to_unsigned(c, 2) + 1);
else
next_c <= c;
end if;
end process c_counter_nsl;
-- leda C_1406 off
r_counter_reg : process(clk)
begin
if rising_edge(clk) then
r <= next_r;
end if;
end process r_counter_reg;
-- leda C_1406 on
-- leda C_1406 off
sbox_return_reg : process(clk)
begin
if rising_edge(clk) then
sbox_return_reged <= sbox_return;
end if;
end process sbox_return_reg;
-- leda C_1406 on
r_counter_nsl : process(r, r_clr)
begin
if (r_clr = '1') then
next_r <= 0;
else
next_r <= to_integer(to_unsigned(r, 2) + 1);
end if;
end process r_counter_nsl;
round_key <= cur_key;
end behavioral;
architecture behavioral_p of key_scheduler is
type state_type is (
idle, load_key, rot_sub_rcon, add_cols, be_done
);
signal state : state_type;
signal next_state : state_type;
signal cur_key : key_type;
signal next_cur_key : key_type;
signal new_key : key_type;
signal next_new_key : key_type;
signal c : index;
signal next_c : index;
signal c_clr : std_logic;
signal c_up : std_logic;
signal sbox_lookup, sbox_return : col;
begin
gen_sbox : for i in index generate
sbox_b : entity work.sbox(dataflow) port map (
clk => clk, a => sbox_lookup(i), b => sbox_return(i)
);
end generate gen_sbox;
process(cur_key)
begin
for i in index loop
sbox_lookup(i) <= cur_key(to_integer(to_unsigned(i, 2) + 1), 3);
end loop;
end process;
-- leda C_1406 off
state_reg : process(clk, nrst)
begin
if (nrst = '0') then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
cur_key <= next_cur_key;
new_key <= next_new_key;
end if;
end process state_reg;
-- leda C_1406 on
state_nsl : process(state, go, c, round)
begin
next_state <= idle;
case state is
when idle =>
if (go = '1' and round = 0) then
next_state <= load_key;
elsif (go = '1') then
next_state <= rot_sub_rcon;
else
next_state <= idle;
end if;
when load_key =>
next_state <= be_done;
when rot_sub_rcon =>
next_state <= add_cols;
when add_cols =>
if (c = 3) then
next_state <= be_done;
else
next_state <= add_cols;
end if;
when be_done =>
next_state <= idle;
end case;
end process state_nsl;
state_out : process(state, cur_key, new_key, key_data,
key_index, key_load,
sbox_return, c, round)
variable temp_index : index;
begin
next_cur_key <= cur_key;
next_new_key <= new_key;
c_up <= '0';
c_clr <= '0';
done <= '0';
case state is
when idle =>
if (key_load = '1') then
next_new_key(key_index mod 4, key_index / 4) <= key_data;
end if;
when load_key =>
-- nothing
when rot_sub_rcon =>
for i in index loop
if (i = 0) then
next_new_key(i, 0) <= sbox_return(i) xor rcon_tbl(round);
else
next_new_key(i, 0) <= sbox_return(i);
end if;
end loop;
c_clr <= '1';
when add_cols =>
if (c = 0) then
temp_index := 0;
else
temp_index := c - 1;
end if;
for r in index loop
next_new_key(r, c) <= new_key(r, temp_index) xor cur_key(r, c);
end loop;
c_up <= '1';
when be_done =>
next_cur_key <= new_key;
done <= '1';
end case;
end process state_out;
-- leda C_1406 off
c_counter_reg : process(clk)
begin
if rising_edge(clk) then
c <= next_c;
end if;
end process c_counter_reg;
-- leda C_1406 on
c_counter_nsl : process(c, c_up, c_clr)
begin
if (c_clr = '1') then
next_c <= 0;
elsif (c_up = '1') then
next_c <= to_integer(to_unsigned(c, 2) + 1);
else
next_c <= c;
end if;
end process c_counter_nsl;
round_key <= cur_key;
end behavioral_p;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter_bit.vhd | 3 | 6738 | -------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1 2003/03/15 01:05:26 ostlerf Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/03/15 01:05:26 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v1_00_b;
Use proc_common_v1_00_b.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_bit is
port (
Clk : in std_logic;
Rst : In std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
component inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component inferred_lut4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"36C6"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => count_AddSub,
--- xst wrk around I0 => Count_In,
--- xst wrk around I1 => Count_Down,
--- xst wrk around I2 => Count_Load,
--- xst wrk around I3 => Load_In);
I_ALU_LUT : inferred_lut4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub,
I0 => Count_In,
I1 => Count_Down,
I2 => Count_Load,
I3 => Load_In);
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg,
C => Clk,
CE => Clock_Enable,
D => count_Result,
R => Rst
);
Result <= count_Result_Reg;
end implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/slave.vhd | 10 | 27202 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/slave.vhd | 10 | 27202 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
| bsd-3-clause |
jevinskie/aes-over-pcie | source/sbox.vhd | 1 | 7850 | -- File name: sbox.vhd
-- Created: 2009-02-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: Rijndael S-Box
use work.aes.all;
use work.reduce_pack.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sbox is
port (
clk : in std_logic;
a : in byte;
b : out byte
);
type matrix_type is array (7 downto 0) of byte;
function square_gf4 (q : nibble)
return nibble
is
variable k : nibble;
begin
k(3) := q(3);
k(2) := q(3) xor q(2);
k(1) := q(2) xor q(1);
k(0) := q(3) xor q(1) xor q(0);
return k;
end function square_gf4;
function mullambda_gf4 (q : nibble)
return nibble
is
variable k : nibble;
begin
k(3) := q(2) xor q(0);
k(2) := q(3) xor q(2) xor q(1) xor q(0);
k(1) := q(3);
k(0) := q(2);
return k;
end function mullambda_gf4;
function mul_gf2(q : pair; w : pair)
return pair
is
variable k : pair;
begin
k(1) := (q(1) and w(1)) xor (q(0) and w(1)) xor (q(1) and w(0));
k(0) := (q(1) and w(1)) xor (q(0) and w(0));
return k;
end function mul_gf2;
function mul_alt_gf2(q : pair; w : pair)
return pair
is
variable k : pair;
begin
k(1) := ((q(1) xor q(0)) and (w(1) xor w(0))) xor (q(0) and w(0));
k(0) := (q(1) and w(1)) xor (q(0) and w(0));
return k;
end function mul_alt_gf2;
function mulphi_gf2(q : pair)
return pair
is
variable k : pair;
begin
k(1) := q(1) xor q(0);
k(0) := q(1);
return k;
end function mulphi_gf2;
function mul_gf4(q : nibble; w : nibble)
return nibble
is
variable qh, ql, wh, wl : pair;
variable res_top, res_mid, res_bot : pair;
variable k : nibble;
begin
qh := q(3 downto 2);
ql := q(1 downto 0);
wh := w(3 downto 2);
wl := w(1 downto 0);
res_top := mulphi_gf2(mul_gf2(qh, wh));
res_mid := mul_alt_gf2(qh xor ql, wh xor wl);
res_bot := mul_alt_gf2(ql, wl);
k(3 downto 2) := res_mid xor res_bot;
k(1 downto 0) := res_top xor res_bot;
return k;
end function mul_gf4;
function iso_map(q : byte)
return byte
is
variable k : byte;
constant iso : matrix_type :=
("10100000",
"11011110",
"10101100",
"10101110",
"11000110",
"10011110",
"01010010",
"01000011");
begin
for i in iso'range loop
k(i) := xor_reduce(q and iso(i));
end loop;
return k;
end function iso_map;
function inv_iso_map(q : byte)
return byte
is
variable k : byte;
constant iso_inv : matrix_type :=
("11100010",
"01000100",
"01100010",
"01110110",
"00111110",
"10011110",
"00110000",
"01110101");
begin
for i in iso_inv'range loop
k(i) := xor_reduce(q and iso_inv(i));
end loop;
return k;
end function inv_iso_map;
function mulinv_gf4(q : nibble)
return nibble
is
variable k : nibble;
begin
k(3) := q(3) xor (q(3) and q(2) and q(1)) xor (q(3) and q(0)) xor q(2);
k(2) := (q(3) and q(2) and q(1)) xor (q(3) and q(2) and q(0)) xor
(q(3) and q(0)) xor q(2) xor (q(2) and q(1));
k(1) := q(3) xor (q(3) and q(2) and q(1)) xor (q(3) and q(1) and q(0)) xor
q(2) xor (q(2) and q(0)) xor q(1);
k(0) := (q(3) and q(2) and q(1)) xor (q(3) and q(2) and q(0)) xor
(q(3) and q(1)) xor (q(3) and q(1) and q(0)) xor (q(3) and q(0)) xor
q(2) xor (q(2) and q(1)) xor (q(2) and q(1) and q(0)) xor q(1) xor q(0);
return k;
end function mulinv_gf4;
function mulinv_lut_gf4(q : nibble)
return nibble
is
variable k : nibble;
begin
case q is
when x"0" => k := x"0";
when x"1" => k := x"1";
when x"2" => k := x"3";
when x"3" => k := x"2";
when x"4" => k := x"f";
when x"5" => k := x"c";
when x"6" => k := x"9";
when x"7" => k := x"b";
when x"8" => k := x"a";
when x"9" => k := x"6";
when x"a" => k := x"8";
when x"b" => k := x"7";
when x"c" => k := x"5";
when x"d" => k := x"e";
when x"e" => k := x"d";
when x"f" => k := x"4";
when others => k := x"0";
end case;
return k;
end function mulinv_lut_gf4;
function af(a : byte)
return byte
is
variable b : byte;
variable d : byte;
constant m : matrix_type :=
("11111000",
"01111100",
"00111110",
"00011111",
"10001111",
"11000111",
"11100011",
"11110001");
constant c : byte := "01100011";
begin
for i in m'range loop
b(i) := xor_reduce(a and m(i));
end loop;
b := b xor c;
return b;
end function af;
function iso_inv_af(a : byte)
return byte
is
variable b : byte;
variable d : byte;
constant m : matrix_type :=
("10001100",
"11110000",
"10000100",
"10010011",
"00000111",
"01111101",
"10000001",
"11000111");
constant c : byte := "01100011";
begin
for i in m'range loop
b(i) := xor_reduce(a and m(i));
end loop;
b := b xor c;
return b;
end function iso_inv_af;
end entity sbox;
architecture dataflow of sbox is
signal iso : byte;
signal isoh, isol : nibble;
signal left_top, left_bot : nibble;
signal right_top, right_bot : nibble;
signal mulinv : nibble;
begin
process(clk)
begin
if rising_edge(clk) then
end if;
end process;
iso <= iso_map(a);
isoh <= iso(7 downto 4);
isol <= iso(3 downto 0);
left_top <= mullambda_gf4(square_gf4(isoh));
left_bot <= mul_gf4(isoh xor isol, isol);
mulinv <= mulinv_lut_gf4(left_top xor left_bot);
right_top <= mul_gf4(mulinv, isoh);
right_bot <= mul_gf4(mulinv, isoh xor isol);
b <= iso_inv_af(right_top & right_bot);
end architecture dataflow;
architecture pipelined of sbox is
signal iso : byte;
signal isoh, isol : nibble;
signal isoh_q, isol_q : nibble;
signal left_top, left_bot : nibble;
signal left_top_q, left_bot_q : nibble;
signal right_top, right_bot : nibble;
signal mulinv : nibble;
signal subbyte : byte;
begin
process(clk)
begin
if (rising_edge(clk)) then
isoh_q <= isoh;
isol_q <= isol;
left_top_q <= left_top;
left_bot_q <= left_bot;
b <= subbyte;
end if;
end process;
iso <= iso_map(a);
isoh <= iso(7 downto 4);
isol <= iso(3 downto 0);
left_top <= mullambda_gf4(square_gf4(isoh));
left_bot <= mul_gf4(isoh xor isol, isol);
mulinv <= mulinv_lut_gf4(left_top_q xor left_bot_q);
right_top <= mul_gf4(mulinv, isoh_q);
right_bot <= mul_gf4(mulinv, isoh_q xor isol_q);
subbyte <= iso_inv_af(right_top & right_bot);
end architecture pipelined;
architecture lut of sbox is
begin
process(clk)
begin
if rising_edge(clk) then
end if;
end process;
b <= work.aes.sbox(to_integer(a));
end architecture lut;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_acc_mergesort_v1_00_a/hdl/vhdl/user_logic_hwtul.vhd | 2 | 13607 | -- ************************************
-- Automatically Generated FSM
-- mergesort
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity mergesort is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32
);
port
(
array0_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
array0_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
array0_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
array0_rENA0 : out std_logic;
array0_wENA0 : out std_logic;
array1_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
array1_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
array1_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
array1_rENA0 : out std_logic;
array1_wENA0 : out std_logic;
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity mergesort;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of mergesort is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
idle,
decode,
dispatch,
begin_sort,
extra1,
begin_merge,
halt,
extra2,
merge_loop,
extra3,
extra4,
extra5,
for_loop,
extra6,
cond_check,
cond_body
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal swapped, swapped_next : std_logic;
signal n, n_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal n_new, n_new_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal i, i_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal data1, data1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal data2, data2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal size, size_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal ptr1, ptr1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal ptr2, ptr2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal arg1, arg1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal arg2, arg2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal opcode, opcode_next : std_logic_vector(0 to 1);
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
swapped_next,
n_next,
n_new_next,
i_next,
data1_next,
data2_next,
size_next,
ptr1_next,
ptr2_next,
arg1_next,
arg2_next,
opcode_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
swapped <= '0';
n <= (others => '0');
n_new <= (others => '0');
i <= (others => '0');
data1 <= (others => '0');
data2 <= (others => '0');
size <= (others => '0');
ptr1 <= (others => '0');
ptr2 <= (others => '0');
arg1 <= (others => '0');
arg2 <= (others => '0');
opcode <= (others => '0');
current_state <= reset;
else
-- Transition to next state
swapped <= swapped_next;
n <= n_next;
n_new <= n_new_next;
i <= i_next;
data1 <= data1_next;
data2 <= data2_next;
size <= size_next;
ptr1 <= ptr1_next;
ptr2 <= ptr2_next;
arg1 <= arg1_next;
arg2 <= arg2_next;
opcode <= opcode_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
array0_dOUT0,
array1_dOUT0,
chan1_channelDataOut, chan1_full, chan1_exists,
swapped,
n,
n_new,
i,
data1,
data2,
size,
ptr1,
ptr2,
arg1,
arg2,
opcode,
current_state) is
begin
-- Default signal assignments
swapped_next <= swapped;
n_next <= n;
n_new_next <= n_new;
i_next <= i;
data1_next <= data1;
data2_next <= data2;
size_next <= size;
ptr1_next <= ptr1;
ptr2_next <= ptr2;
arg1_next <= arg1;
arg2_next <= arg2;
opcode_next <= opcode;
array0_addr0 <= (others => '0');
array0_dIN0 <= (others => '0');
array0_rENA0 <= '0';
array0_wENA0 <= '0';
array1_addr0 <= (others => '0');
array1_dIN0 <= (others => '0');
array1_rENA0 <= '0';
array1_wENA0 <= '0';
chan1_channelDataIn <= (others => '0');
chan1_channelRead <= '0';
chan1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when begin_merge =>
array0_addr0 <= arg2;
array0_rENA0 <= '1';
next_state <= extra2;
when begin_sort =>
if ( swapped = '0' ) then
next_state <= halt;
elsif ( swapped = '1' ) then
array0_addr0 <= arg1;
array0_rENA0 <= '1';
next_state <= extra5;
end if;
when cond_body =>
i_next <= i + 1;
swapped_next <= '1';
n_new_next <= i;
array0_addr0 <= i + 1;
array0_dIN0 <= data1;
array0_wENA0 <= '1';
array0_rENA0 <= '1';
next_state <= for_loop;
when cond_check =>
if ( data1 <= data2 ) then
i_next <= i + 1;
data1_next <= data2;
next_state <= for_loop;
elsif ( data1 > data2 ) then
array0_addr0 <= i;
array0_dIN0 <= data2;
array0_wENA0 <= '1';
array0_rENA0 <= '1';
next_state <= cond_body;
end if;
when decode =>
opcode_next <= n(0 to 1);
arg2_next <= "00000000000000000" & n(2 to 16);
arg1_next <= "00000000000000000" & n(17 to 31);
next_state <= dispatch;
when dispatch =>
if ( opcode = "00" ) then
swapped_next <= '1';
n_next <= arg2;
n_new_next <= arg2;
next_state <= begin_sort;
elsif ( opcode = "01" ) then
array0_addr0 <= arg1;
array0_rENA0 <= '1';
next_state <= extra1;
else
next_state <= halt;
end if;
when extra1 =>
if chan1_exists = '0' then
next_state <= extra1;
elsif chan1_exists /= '0' then
data1_next <= array0_dOUT0;
i_next <= (others => '0');
size_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
ptr2_next <= arg2 + 1;
ptr1_next <= arg1 + 1;
next_state <= begin_merge;
end if;
when extra2 =>
data2_next <= array0_dOUT0;
next_state <= merge_loop;
when extra3 =>
i_next <= i + 1;
data1_next <= array0_dOUT0;
array1_addr0 <= i;
array1_dIN0 <= data1;
array1_wENA0 <= '1';
array1_rENA0 <= '1';
ptr1_next <= ptr1 + 1;
next_state <= merge_loop;
when extra4 =>
i_next <= i + 1;
data2_next <= array0_dOUT0;
array1_addr0 <= i;
array1_dIN0 <= data2;
array1_wENA0 <= '1';
array1_rENA0 <= '1';
ptr2_next <= ptr2 + 1;
next_state <= merge_loop;
when extra5 =>
data1_next <= array0_dOUT0;
i_next <= arg1;
swapped_next <= '0';
next_state <= for_loop;
when extra6 =>
data2_next <= array0_dOUT0;
next_state <= cond_check;
when for_loop =>
if ( i >= n ) then
n_next <= n_new;
next_state <= begin_sort;
elsif ( i < n ) then
array0_addr0 <= i + 1;
array0_rENA0 <= '1';
next_state <= extra6;
end if;
when halt =>
if chan1_full /= '0' then
next_state <= halt;
elsif chan1_full = '0' then
chan1_channelDataIn <= (others => '0');
chan1_channelWrite <= '1';
next_state <= idle;
end if;
when idle =>
if chan1_exists = '0' then
next_state <= idle;
elsif chan1_exists /= '0' then
n_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= decode;
end if;
when merge_loop =>
if ( ( i < size ) and ( ( ( data1 < data2 ) and ( ptr1 - ('0' & size(0 to 30)) <= arg1 ) ) or ( ptr2 - ('0' & size(0 to 30)) > arg2 ) ) ) then
array0_addr0 <= ptr1;
array0_rENA0 <= '1';
next_state <= extra3;
elsif ( ( i < size ) and ( ( ( data1 >= data2 ) and ( ptr2 - ('0' & size(0 to 30)) <= arg2 ) ) or ( ptr1 - ('0' & size(0 to 30)) > arg1 ) ) ) then
array0_addr0 <= ptr2;
array0_rENA0 <= '1';
next_state <= extra4;
else
next_state <= halt;
end if;
when reset =>
next_state <= idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_v20_v1_10_d/hdl/vhdl/arb2bus_data_mux.vhd | 3 | 13208 | -------------------------------------------------------------------------------
-- $Id: arb2bus_data_mux.vhd,v 1.1.2.1 2009/10/06 21:14:59 gburch Exp $
-------------------------------------------------------------------------------
-- arb2bus_data_mux.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Filename: arb2bus_data_mux.vhd
-- Version: v1.02e
-- Description:
-- This file muxes the priority register and control register
-- data to the IP2BUS data bus during a read cycle.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- LCW 02/04/05 - update library statements
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_MASTERS -- number of masters
-- C_OPBDATA_WIDTH -- width of OPB data bus
--
-- Definition of Ports:
--
-- -- IPIF interface signals
-- input Bus2IP_Reg_RdCE -- Read clock enables for registers
-- input Bus2IP_Reg_WrCE -- Write clock enables for registers
--
-- -- Data from control register
-- input Ctrl_reg
--
-- -- Data from priority registers
-- input Priority_regs
--
-- -- Multiplexed outputs based on register clock enables and
-- -- read/write requests
-- output Arb2bus_wrack -- mux'd output from register wracks
-- output Arb2bus_rdack -- register read acknowledge
-- output Arb2bus_data -- mux'd output data
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity arb2bus_data_mux is
generic ( C_NUM_MASTERS : integer := 4;
C_OPBDATA_WIDTH : integer := 32
);
port ( Bus2IP_Reg_RdCE : in std_logic_vector(0 to C_NUM_MASTERS);
Bus2IP_Reg_WrCE : in std_logic_vector(0 to C_NUM_MASTERS);
Ctrl_reg : in std_logic_vector(0 to C_OPBDATA_WIDTH-1);
Priority_regs : in std_logic_vector (0 to C_NUM_MASTERS*C_OPBDATA_WIDTH-1);
Arb2bus_wrack : out std_logic ;
Arb2bus_rdack : out std_logic ;
Arb2bus_data : out std_logic_vector (0 to C_OPBDATA_WIDTH-1)
);
end arb2bus_data_mux;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of arb2bus_data_mux is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal all_registers : std_logic_vector(0 to (C_NUM_MASTERS+1)*C_OPBDATA_WIDTH -1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- ARB2BUS_DATA_PROCESS
-------------------------------------------------------------------------------
-- This process multiplexes the data from the priority registers and the
-- control register based on the register chip enables to generate
-- ARB2BUS_DATA
-------------------------------------------------------------------------------
all_registers <= Ctrl_reg & Priority_regs;
ARB2BUS_DATAMUX_I: entity opb_v20_v1_10_d.mux_onehot
generic map ( C_DW => C_OPBDATA_WIDTH,
C_NB => C_NUM_MASTERS+1)
port map (
D => all_registers,
S => Bus2IP_Reg_RdCE,
Y => Arb2bus_data
);
-------------------------------------------------------------------------------
-- ARB2BUS_RDACK
-------------------------------------------------------------------------------
-- ARB2BUS_RDACK is simply the OR of all Bus2IP read register chip enables
-- Use the OR_BITS component to perform the OR of these bits most efficiently
-------------------------------------------------------------------------------
ARB2BUS_RDACK_I: entity opb_v20_v1_10_d.or_bits
generic map ( C_NUM_BITS => C_NUM_MASTERS+1,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS+1)
port map (
In_bus => Bus2Ip_Reg_RdCE,
Sig => '0',
Or_out => Arb2bus_rdack
);
-------------------------------------------------------------------------------
-- ARB2BUS_WRACK generation
-------------------------------------------------------------------------------
-- This process ORs the wrack from the priority register logic and the
-- control register logic to generate ARB2BUS_WRACK
-------------------------------------------------------------------------------
ARB2BUS_WRACK_I: entity opb_v20_v1_10_d.or_bits
generic map ( C_NUM_BITS => C_NUM_MASTERS+1,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS+1)
port map (
In_bus => Bus2Ip_Reg_WrCE,
Sig => '0',
Or_out => Arb2bus_wrack
);
end implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_v20_v1_10_d/hdl/vhdl/counter_bit.vhd | 3 | 8843 | -------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:00 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_occ_counter.vhd | 3 | 6847 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter.vhd
--
-- Description: Implements packet fifo occupancy counter. This special
-- counter provides these functions:
-- - up/down count control
-- - pre-increment/pre-decrement of input load value
-- - count by 2
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- D. Thorpe 2001-09-07 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst signal connect to the pf_counter_bit module
-- LCW Nov 8, 2004 -- updated for NCSim
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Cnt_by_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_occ_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal i_mux_Count_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal count_clock_en : std_logic;
signal carry_out_lsb : std_logic;
signal carry_in_lsb : std_logic;
signal count_out_lsb : std_logic;
Signal mux_cnt_in_lsb : std_logic;
Signal carry_out_select_di: std_logic;
Signal carry_start : std_logic;
Signal carry_start_select : std_logic;
Signal by_2_carry_start : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
count_clock_en <= Count_Enable or Count_Load;
MUX_THE_LSB_INPUT : process (count_out_lsb, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
mux_cnt_in_lsb <= count_out_lsb;
else
mux_cnt_in_lsb <= Load_In(C_COUNT_WIDTH-1);
End if;
End process MUX_THE_LSB_INPUT;
carry_start <= Count_Down xor Count_Enable;
by_2_carry_start <= Cnt_by_2 and Count_Down;
carry_start_select <= not(Cnt_by_2);
I_MUXCY_LSB_IN : MUXCY_L
port map (
DI => by_2_carry_start,
CI => carry_start,
S => carry_start_select,
LO => carry_in_lsb);
I_COUNTER_BIT_LSB : entity opb_ipif_v2_00_h.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => mux_cnt_in_lsb,
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => carry_in_lsb,
Clock_Enable => count_clock_en,
Result => count_out_lsb,
Carry_Out => carry_out_lsb);
carry_out_select_di <= Count_Down xor Cnt_by_2;
I_MUXCY_LSB_OUT : MUXCY_L
port map (
DI => carry_out_select_di,
CI => carry_out_lsb,
S => carry_start_select,
LO => alu_cy(C_COUNT_WIDTH-1));
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-2 generate
begin
MUX_THE_INPUT : process (iCount_Out, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
i_mux_Count_Out(i) <= iCount_Out(i);
else
i_mux_Count_Out(i) <= Load_In(i);
End if;
End process MUX_THE_INPUT;
Counter_Bit_I : entity opb_ipif_v2_00_h.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => i_mux_Count_Out(i),
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => alu_cy(i+1),
Clock_Enable => count_clock_en,
Result => iCount_Out(i),
Carry_Out => alu_cy(i));
end generate I_ADDSUB_GEN;
Count_Out <= iCount_Out & count_out_lsb;
Carry_Out <= '0';
end architecture implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/XilinxProcessorIP/pcores/opb_ac97_v1_00_a/hdl/vhdl/TESTBENCH_ac97_core.vhd | 4 | 14277 | -------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_core.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
--
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read_strobe, reg_write_strobe : std_logic := '0';
signal reg_error : std_logic := '0';
signal reg_busy, reg_data_valid : std_logic;
signal play_left_accept, play_right_accept : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15) := (others =>'0');
signal PCM_Playback_Right: std_logic_vector(0 to 15) := (others => '0');
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
model : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Strobe => reg_read_strobe, --
AC97_Reg_Write_Strobe => reg_write_strobe, --
AC97_Reg_Busy => reg_busy, --
AC97_Reg_Error => reg_error, -- d
AC97_Reg_Read_Data_Valid => reg_data_valid, -- d
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Playback_Left_Accept => play_left_accept, -- d
PCM_Playback_Right_Accept => play_right_accept, -- d
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
CODEC_RDY => CODEC_RDY
);
-- simulate a 20 ns reset pulse
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
register_if_process: process
begin
--PCM_Playback_Right_Valid <= '0';
--PCM_Playback_Left_Valid <= '0';
reg_read_strobe <= '0';
reg_write_strobe <= '0';
reg_addr <= (others => '0');
--PCM_Playback_Left <= (others => '0');
--PCM_Playback_Right <= (others => '0');
-- wait for codec ready
test_no <= 0;
wait until CODEC_RDY='1';
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Perform a register write (to reset register)
test_no <= 1;
reg_addr <= "0000010";
reg_write_data <= X"A5A5";
wait until clk'event and clk='1';
reg_write_strobe <= '1';
wait until clk'event and clk='1';
reg_write_strobe <= '0';
reg_addr <= "0000000";
reg_write_data <= X"0000";
wait until clk'event and clk='1';
wait until reg_busy = '0';
-- Perform a register read
test_no <= 2;
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
reg_addr <= "0000010";
wait until clk'event and clk='1';
reg_read_strobe <= '1';
wait until clk'event and clk='1';
reg_read_strobe <= '0';
reg_addr <= "0000000";
wait until clk'event and clk='1';
wait until reg_busy = '0';
test_no <= 3;
-- -- set default values
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- test_no <= 1;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- test_no <= 2;
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- test_no <= 3;
-- -- send a read command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_read <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_read <= '0';
-- wait;
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- Test process
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
play_data_process: process
type register_type is array(0 to 31) of std_logic_vector(15 downto 0);
variable play_data : register_type := (
X"0001", X"0002", X"0004", X"0008", X"0010", X"0020", X"0040", X"0080",
X"0100", X"0200", X"0400", X"0800", X"1000", X"2000", X"4000", X"8000",
X"0001", X"0002", X"0004", X"0008", X"0010", X"0020", X"0040", X"0080",
X"0100", X"0200", X"0400", X"0800", X"1000", X"2000", X"4000", X"8000"
);
variable count : integer := 0;
begin
wait until codec_rdy = '1';
for count in 0 to 31 loop
PCM_Playback_Left <= play_data(count);
PCM_Playback_Right <= play_data(count);
wait until play_left_accept = '1' and
play_right_accept = '1' and clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
end loop;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
| bsd-3-clause |
akhatnya/testing | vendor/bower/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_occ_counter.vhd | 3 | 10830 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter.vhd
--
-- Description: Implements packet fifo occupancy counter. This special
-- counter provides these functions:
-- - up/down count control
-- - pre-increment/pre-decrement of input load value
-- - count by 2
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- D. Thorpe 2001-09-07 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst signal connect to the pf_counter_bit module
--
-- DET 2002-02-24
-- - Changed the use of MUXCY_L to MUXCY.
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Cnt_by_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_occ_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal i_mux_Count_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal count_clock_en : std_logic;
signal carry_out_lsb : std_logic;
signal carry_in_lsb : std_logic;
signal count_out_lsb : std_logic;
Signal mux_cnt_in_lsb : std_logic;
Signal carry_out_select_di: std_logic;
Signal carry_start : std_logic;
Signal carry_start_select : std_logic;
Signal by_2_carry_start : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
count_clock_en <= Count_Enable or Count_Load;
MUX_THE_LSB_INPUT : process (count_out_lsb, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
mux_cnt_in_lsb <= count_out_lsb;
else
mux_cnt_in_lsb <= Load_In(C_COUNT_WIDTH-1);
End if;
End process MUX_THE_LSB_INPUT;
carry_start <= Count_Down xor Count_Enable;
by_2_carry_start <= Cnt_by_2 and Count_Down;
carry_start_select <= not(Cnt_by_2);
I_MUXCY_LSB_IN : MUXCY
port map (
DI => by_2_carry_start,
CI => carry_start,
S => carry_start_select,
O => carry_in_lsb);
I_COUNTER_BIT_LSB : entity opb_v20_v1_10_d.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => mux_cnt_in_lsb,
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => carry_in_lsb,
Clock_Enable => count_clock_en,
Result => count_out_lsb,
Carry_Out => carry_out_lsb);
carry_out_select_di <= Count_Down xor Cnt_by_2;
I_MUXCY_LSB_OUT : MUXCY
port map (
DI => carry_out_select_di,
CI => carry_out_lsb,
S => carry_start_select,
O => alu_cy(C_COUNT_WIDTH-1));
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-2 generate
begin
MUX_THE_INPUT : process (iCount_Out, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
i_mux_Count_Out(i) <= iCount_Out(i);
else
i_mux_Count_Out(i) <= Load_In(i);
End if;
End process MUX_THE_INPUT;
Counter_Bit_I : entity opb_v20_v1_10_d.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => i_mux_Count_Out(i),
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => alu_cy(i+1),
Clock_Enable => count_clock_en,
Result => iCount_Out(i),
Carry_Out => alu_cy(i));
end generate I_ADDSUB_GEN;
Count_Out <= iCount_Out & count_out_lsb;
Carry_Out <= '0';
end architecture implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_dwt.vhd | 2 | 15862 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Quicksort
-- Thread implements the quicksort algorithm
-- Passed in argument is a pointer to following struct
-- struct sortData {
-- int * startData; //pointer to start of array
-- int * endData; //pointer to end of array
-- int cacheOption // 1 operate on data where it is, 0 copy into HWTI first
-- There is not return argument, the HWT just sorts the data.
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
READ_ARGS_1,
READ_ARGS_2,
READ_ARGS_3,
WHILE_1,
WHILE_2,
WHILE_3,
WHILE_4,
WHILE_5,
WHILE_6,
WHILE_7,
WHILE_8,
FOO,
LOOP_1,
LOOP_2,
LOOP_3,
LOOP_4,
LOOP_5,
LOOP_6,
EXIT_THREAD,
EXIT_THREAD_1,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next : state_machine := FUNCTION_RESET;
signal arg, arg_next : std_logic_vector(0 to 31);
signal sig, sig_next : std_logic_vector(0 to 31);
signal len, len_next : std_logic_vector(0 to 31);
signal i, i_next : std_logic_vector(0 to 31);
signal r1, r1_next : std_logic_vector(0 to 31);
signal r2, r2_next : std_logic_vector(0 to 31);
signal r3, r3_next : std_logic_vector(0 to 31);
signal r4, r4_next : std_logic_vector(0 to 31);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
arg <= arg_next;
sig <= sig_next;
len <= len_next;
i <= i_next;
r1 <= r1_next;
r2 <= r2_next;
r3 <= r3_next;
r4 <= r4_next;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (current_state) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
next_state <= current_state;
return_state_next <= return_state;
arg_next <= arg;
sig_next <= sig;
len_next <= len;
i_next <= i;
r1_next <= r1;
r2_next <= r2;
r3_next <= r3;
r4_next <= r4;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
arg_next <= Z32;
sig_next <= Z32;
len_next <= Z32;
i_next <= Z32;
r1_next <= Z32;
r2_next <= Z32;
r3_next <= Z32;
r4_next <= Z32;
when FUNCTION_START =>
-- read the passed in argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_address <= Z32;
return_state_next <= READ_ARGS_1;
next_state <= WAIT_STATE;
-- struct Array * arrayPtr;
-- arrayPtr = (struct Array *) arg;
-- Huint * sig = arrayPtr->data;
when READ_ARGS_1 =>
arg_next <= toUser_value;
-- Read the address of the data array
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
return_state_next <= READ_ARGS_2;
next_state <= WAIT_STATE;
-- Huint len = arrayPtr->length
when READ_ARGS_2 =>
sig_next <= toUser_value;
-- Read value of length
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
return_state_next <= READ_ARGS_3;
next_state <= WAIT_STATE;
-- int i=0
-- Huint tmp[LENGTH];
when READ_ARGS_3 =>
len_next <= toUser_value;
-- initialize i
i_next <= Z32;
-- Declare len number of variables on the stack
thrd2intrfc_opcode <= OPCODE_DECLARE;
thrd2intrfc_value <= toUser_value;
return_state_next <= WHILE_1;
next_state <= WAIT_STATE;
-- while ( i < (len >> 1 ) ) {
when WHILE_1 =>
-- set r1 to len >> 1
r1_next <= '0' & len(0 to 30);
-- set r2 to i << 1
r2_next <= i(1 to 31) & '0';
next_state <= WHILE_2;
when WHILE_2 =>
if ( i < r1 ) then
next_state <= WHILE_3;
else
next_state <= FOO;
end if;
-- tmp[(i<<1)+1] = (sig[(i<<1)] + sig[(i<<1)+1]) >> 1;
when WHILE_3 =>
-- Read the value of sig[(i<<1)]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= sig + (r2(2 to 31) & "00");
return_state_next <= WHILE_4;
next_state <= WAIT_STATE;
when WHILE_4 =>
r3_next <= toUser_value;
-- Read the value of sig[(i<<1) + 1]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= sig + (r2(2 to 31) & "00") + x"00000004";
return_state_next <= WHILE_5;
next_state <= WAIT_STATE;
when WHILE_5 =>
-- Calculate the averaged value
r4_next <= ('0' & r3(0 to 30)) + ('0' & toUser_value(0 to 30));
next_state <= WHILE_6;
when WHILE_6 =>
-- write the average value to tmp array
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= r2 + x"00000001";
thrd2intrfc_value <= r4;
return_state_next <= WHILE_7;
next_state <= WAIT_STATE;
-- tmp[(i<<1)] = (sig[(i<<1)] - tmp[(i<<1) + 1];
when WHILE_7 =>
-- write the difference to tmp array
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= r2;
thrd2intrfc_value <= r3 - r4;
return_state_next <= WHILE_8;
next_state <= WAIT_STATE;
-- i++;
when WHILE_8 =>
-- increment i
i_next <= i + x"00000001";
next_state <= WHILE_1;
-- i=0;
when FOO =>
i_next <= Z32;
next_state <= LOOP_1;
-- while ( i < (len >> 1 ) ) {
when LOOP_1 =>
-- set r2 to i << 1
r2_next <= i(1 to 31) & '0';
-- Check the while condition
if ( i < r1 ) then
next_state <= LOOP_2;
else
next_state <= EXIT_THREAD;
end if;
-- sig[i] = tmp[(i<<1)+1];
when LOOP_2 =>
-- read the value of the tmp array
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= r2 + x"00000001";
return_state_next <= LOOP_3;
next_state <= WAIT_STATE;
when LOOP_3 =>
-- write the temp value back to data array
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= sig + (i(2 to 31) & "00");
thrd2intrfc_value <= toUser_value;
return_state_next <= LOOP_4;
next_state <= WAIT_STATE;
-- sig[(len>>1)+i] = tmp[(i<<1)];
when LOOP_4 =>
-- read the value of the tmp array
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= r2;
return_state_next <= LOOP_5;
next_state <= WAIT_STATE;
when LOOP_5 =>
-- write the temp value back to data array
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= sig + (r1(2 to 31) & "00") + (i(2 to 31) & "00");
thrd2intrfc_value <= toUser_value;
return_state_next <= LOOP_6;
next_state <= WAIT_STATE;
when LOOP_6 =>
-- increment i
i_next <= i + x"00000001";
next_state <= LOOP_1;
when EXIT_THREAD =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
return_state_next <= EXIT_THREAD_1;
next_state <= WAIT_STATE;
when EXIT_THREAD_1 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
next_state <= WAIT_STATE;
when WAIT_STATE =>
case toUser_goWait is
when '1' => --Here because HWTUL chose to be here for one clock cycle
next_state <= return_state;
when OTHERS => --ie '0', Here because HWTI is telling us to wait
next_state <= return_state;
end case;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause |
EnricoGiordano1992/resim-simulating-partial-reconfiguration | examples/state_migration/edk/pcores/xps_icapi_v1_01_a/hdl/vhdl/icap_virtex_wrapper.vhd | 6 | 4458 |
---------------------------------------------------------------------
--
-- ICAP_VIRTEX4_WRAPPER
--
-- Description: Instantiating ICAP_VIRTEX4
-- Simulation/Synthesis: Synthesis
-- Reference: $XILINX_HOME/vhdl/src/unisims/primitive/ICAP_VIRTEX4.vhd
--
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity ICAP_VIRTEX4_WRAPPER is
generic(
ICAP_WIDTH: string := "X8" -- "X8" or "X32"
);
port(
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0);
CE : in std_logic;
CLK : in std_logic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_logic
);
end ICAP_VIRTEX4_WRAPPER;
architecture synth of ICAP_VIRTEX4_WRAPPER is
component ICAP_VIRTEX4 is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
begin
i_ICAP_VIRTEX4 : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => ICAP_WIDTH
)
port map (
BUSY => BUSY,
O => O,
CE => CE,
CLK => CLK,
I => I,
WRITE => WRITE
);
end synth;
---------------------------------------------------------------------
--
-- ICAP_VIRTEX5_WRAPPER
--
-- Description: Instantiating ICAP_VIRTEX5
-- Simulation/Synthesis: Synthesis
-- Reference: $XILINX_HOME/vhdl/src/unisims/primitive/ICAP_VIRTEX5.vhd
--
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity ICAP_VIRTEX5_WRAPPER is
generic(
ICAP_WIDTH: string := "X8" -- "X8", "X16" or "X32"
);
port(
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0);
CE : in std_logic;
CLK : in std_logic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_logic
);
end ICAP_VIRTEX5_WRAPPER;
architecture synth of ICAP_VIRTEX5_WRAPPER is
component ICAP_VIRTEX5 is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
begin
i_ICAP_VIRTEX5 : ICAP_VIRTEX5
generic map (
ICAP_WIDTH => ICAP_WIDTH
)
port map (
BUSY => BUSY,
O => O,
CE => CE,
CLK => CLK,
I => I,
WRITE => WRITE
);
end synth;
---------------------------------------------------------------------
--
-- ICAP_VIRTEX6_WRAPPER
--
-- Description: Instantiating ICAP_VIRTEX6
-- Simulation/Synthesis: Synthesis
-- Reference: $XILINX_HOME/vhdl/src/unisims/primitive/ICAP_VIRTEX6.vhd
--
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity ICAP_VIRTEX6_WRAPPER is
generic(
DEVICE_ID : bit_vector := X"04244093";
ICAP_WIDTH : string := "X8"; -- "X8", "X16" or "X32"
SIM_CFG_FILE_NAME : string := "NONE"
);
port(
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0);
CSB : in std_logic;
CLK : in std_logic;
I : in std_logic_vector(31 downto 0);
RDWRB : in std_logic
);
end ICAP_VIRTEX6_WRAPPER;
architecture synth of ICAP_VIRTEX6_WRAPPER is
component ICAP_VIRTEX6 is
generic(
DEVICE_ID : bit_vector := X"04244093";
ICAP_WIDTH : string := "X8";
SIM_CFG_FILE_NAME : string := "NONE"
);
port(
CLK : in std_logic;
CSB : in std_logic;
RDWRB : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
begin
i_ICAP_VIRTEX6 : ICAP_VIRTEX6
generic map (
DEVICE_ID => DEVICE_ID,
ICAP_WIDTH => ICAP_WIDTH,
SIM_CFG_FILE_NAME => SIM_CFG_FILE_NAME
)
port map (
BUSY => BUSY,
O => O,
CSB => CSB,
CLK => CLK,
I => I,
RDWRB => RDWRB
);
end synth;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/ipif_steer.vhd | 2 | 18833 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer.vhd,v 1.1 2003/02/18 19:16:01 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Steer is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64
C_SMALLEST : integer := 32; -- 8, 16, 32, 64
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity IPIF_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Steer is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_thread_manager_v1_00_a/devl/bfmsim/simulation/behavioral/synch_bus_wrapper.vhd | 6 | 975 | -------------------------------------------------------------------------------
-- synch_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library bfm_synch_v1_00_a;
use bfm_synch_v1_00_a.all;
entity synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end synch_bus_wrapper;
architecture STRUCTURE of synch_bus_wrapper is
component bfm_synch is
generic (
C_NUM_SYNCH : integer
);
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to (C_NUM_SYNCH*32)-1);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
begin
synch_bus : bfm_synch
generic map (
C_NUM_SYNCH => 4
)
port map (
FROM_SYNCH_OUT => FROM_SYNCH_OUT,
TO_SYNCH_IN => TO_SYNCH_IN
);
end architecture STRUCTURE;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_scheduler_v1_00_a/devl/bfmsim/simulation/behavioral/synch_bus_wrapper.vhd | 6 | 975 | -------------------------------------------------------------------------------
-- synch_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library bfm_synch_v1_00_a;
use bfm_synch_v1_00_a.all;
entity synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end synch_bus_wrapper;
architecture STRUCTURE of synch_bus_wrapper is
component bfm_synch is
generic (
C_NUM_SYNCH : integer
);
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to (C_NUM_SYNCH*32)-1);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
begin
synch_bus : bfm_synch
generic map (
C_NUM_SYNCH => 4
)
port map (
FROM_SYNCH_OUT => FROM_SYNCH_OUT,
TO_SYNCH_IN => TO_SYNCH_IN
);
end architecture STRUCTURE;
| bsd-3-clause |
jevinskie/aes-over-pcie | source/experiment/lfsr.vhd | 1 | 1289 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lfsr is
port (
clk : in std_logic;
clr : in std_logic;
count : out unsigned(3 downto 0);
top : out std_logic
);
end lfsr;
architecture behav of lfsr is
signal cnt, next_cnt : unsigned(3 downto 0);
signal near,near2 : std_logic;
signal g, next_g : unsigned(3 downto 0);
begin
process(clk)
begin
if (rising_edge(clk)) then
cnt <= next_cnt;
g <= next_g;
end if;
end process;
process(cnt, clr, near, g)
begin
if (clr='1') then
next_cnt <= (others => '1');
next_g <= (others => '1');
else
-- next_cnt <= cnt rol 1;
--next_cnt(3) <= cnt(2) xor cnt(0) xor near;
--next_cnt(2) <= cnt(1) xor cnt(0);
next_cnt <= cnt ror 1;
next_cnt(3) <= cnt(3) xor cnt(0) xor near;
next_g(3) <= g(0);
next_g(2) <= g(0) xor g(3);
next_g(1 downto 0) <= g(2 downto 1);
end if;
end process;
near <= '1' when (cnt(3)='0' and cnt(2)='0' and cnt(1)='0') else '0';
near2 <= '1' when (g(3)='0' and g(2)='0' and g(1)='0') else '0';
count <= cnt;
top <= '1' when cnt = x"e" else '0';
end behav;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/pr_6smp/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/trylock_fsm.vhd | 11 | 6378 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/family.vhd | 3 | 21228 | -- $Header: /devl/xcs/repo/env/Databases/ip2/processor/hardware/opb_v20/opb_v20_v1_10_d/hdl/src/vhdl/Attic/family.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
--------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- END_CHANGELOG
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
package family is
-- constant declarations
constant ANY : string := "any";
constant X4K : string := "x4k";
constant X4KE : string := "x4ke";
constant X4KL : string := "x4kl";
constant X4KEX : string := "x4kex";
constant X4KXL : string := "x4kxl";
constant X4KXV : string := "x4kxv";
constant X4KXLA : string := "x4kxla";
constant SPARTAN : string := "spartan";
constant SPARTANXL : string := "spartanxl";
constant SPARTAN2 : string := "spartan2";
constant SPARTAN2E : string := "spartan2e";
constant VIRTEX : string := "virtex";
constant VIRTEXE : string := "virtexe";
constant VIRTEX2 : string := "virtex2";
constant VIRTEX2P : string := "virtex2p";
constant BYZANTIUM : string := "byzantium";
constant SPARTAN3 : string := "spartan3";
constant QRVIRTEX2 : string := "qrvirtex2";
constant QVIRTEX2 : string := "qvirtex2";
constant VIRTEX4 : string := "virtex4";
constant VIRTEX5 : string := "virtex5";
constant SPARTAN3E : string := "spartan3e";
constant SPARTAN3A : string := "spartan3a";
constant SPARTAN3AN: string := "spartan3an";
-- function declarations
-- derived - provides a means to determine if a family specified in child is
-- the same as, or is a super set of, the family specified in
-- ancestor.
--
-- Typically, child is set to the generic specifying the family type
-- the user wishes to implement the design into (C_FAMILY), and the
-- designer hard codes ancestor to the family type supported by the
-- design. If the design supports multiple family types, then each
-- of those family types would need to be tested against C_FAMILY
-- using this function. An example for the VIRTEX2P hierarchy
-- is shown below:
--
-- VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2P)
-- generate
-- -- logic specific to Virtex2P family
-- end generate VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if not derived(C_FAMILY,VIRTEX2P)
-- generate
--
-- VIRTEX2_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2)
-- generate
-- -- logic specific to Virtex2 family
-- end generate VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2_SPECIFIC_LOGIC_GEN
-- if not derived(C_FAMILY,VIRTEX2)
-- generate
--
-- VIRTEX_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX)
-- generate
-- -- logic specific to Virtex family
-- end generate VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX_SPECIFIC_LOGIC_GEN;
-- if not derived(C_FAMILY,VIRTEX)
-- generate
--
-- ANY_FAMILY_TYPE_LOGIC_GEN:
-- if derived(C_FAMILY,ANY)
-- generate
-- -- logic not specific to any family
-- end generate ANY_FAMILY_TYPE_LOGIC_GEN;
--
-- end generate NON_VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- This function will return TRUE if the family type specified in
-- child is equal to, or a super set of, the family type specified in
-- ancestor, otherwise it returns FALSE.
--
-- The current super sets are defined by the following list, where
-- all family types listed to the right of an item are contained in
-- the super set of that item, for all lines containing that item.
--
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
--
-- For exampel, all other family types are contained in the super set
-- for ANY. Stated another way, if the designer specifies ANY
-- for the family type the design supports, then the function will
-- return TRUE for any family type the user wishes to implement the
-- design into.
--
-- if derived(C_FAMILY,ANY) generate ... end generate;
--
-- If the designer specifies VIRTEX2 as the family type supported by
-- the design, then the function will only return TRUE if the user
-- intends to implement the design in VIRTEX2, VIRTEX2P, BYZANTIUM,
-- or SPARTAN3.
--
-- if derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses VIRTEX2 BRAMs
-- end generate;
--
-- if not derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses non VIRTEX2 BRAMs
-- end generate;
--
-- Note:
-- The last three lines of the list above were modified from the
-- original to remove VIRTEX from those lines because, from our point
-- of view, VIRTEX2 is different enough from VIRTEX to conclude that
-- it should be its own base family type.
--
-- **************************************************************************
-- WARNING
-- **************************************************************************
-- DO NOT RELY ON THE DERIVED FUNCTION TO PROVIDE DIFFERENTIATION BETWEEN
-- FAMILY TYPES FOR ANYTHING OTHER THAN BRAMS
--
-- Use of the derived function assumes that the designer is not using
-- RLOCs (RLOC'd FIFO's from Coregen, etc.) and that the BRAMs in the
-- derived families are similar. If the designer is using specific
-- elements of a family type, they are responsible for ensuring that
-- those same elements are available in all family types supported by
-- their design, and that the elements function exactly the same in all
-- "similar" families.
--
-- **************************************************************************
--
function derived ( child, ancestor : string ) return boolean;
-- equalIgnoreCase - Returns TRUE if case insensitive string comparison
-- determines that str1 and str2 are equal, otherwise FALSE
function equalIgnoreCase( str1, str2 : string ) return boolean;
-- toLowerCaseChar - Returns the lower case form of char if char is an upper
-- case letter. Otherwise char is returned.
function toLowerCaseChar( char : character ) return character;
end family;
package body family is
-- True if architecture "child" is derived from, or equal to,
-- the architecture "ancestor".
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
function derived ( child, ancestor : string ) return boolean is
variable is_derived : boolean := FALSE;
begin
if equalIgnoreCase( child, VIRTEX ) then -- base family type
if ( equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2 ) then
if ( equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QRVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QRVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX5 ) then
if ( equalIgnoreCase(ancestor,VIRTEX5) OR
equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX4 ) then
if ( equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2P ) then
if ( equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, BYZANTIUM ) then
if ( equalIgnoreCase(ancestor,BYZANTIUM) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEXE ) then
if ( equalIgnoreCase(ancestor,VIRTEXE) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2 ) then
if ( equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2E ) then
if ( equalIgnoreCase(ancestor,SPARTAN2E) OR
equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3 ) then
if ( equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3E ) then
if ( equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3A ) then
if ( equalIgnoreCase(ancestor,SPARTAN3A) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3AN ) then
if ( equalIgnoreCase(ancestor,SPARTAN3AN) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4K ) then -- base family type
if ( equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KEX ) then
if ( equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXL ) then
if ( equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXV ) then
if ( equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXLA ) then
if ( equalIgnoreCase(ancestor,X4KXLA) OR
equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KE ) then
if ( equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KL ) then
if ( equalIgnoreCase(ancestor,X4KL) OR
equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN ) then
if ( equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTANXL ) then
if ( equalIgnoreCase(ancestor,SPARTANXL) OR
equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, ANY ) then
if equalIgnoreCase( ancestor, any ) then is_derived := TRUE;
end if;
end if;
return is_derived;
end derived;
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalIgnoreCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoreCase;
end family;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/util_intr_split_v1_00_a/hdl/vhdl/util_intr_split.vhd | 2 | 4825 | -------------------------------------------------------------------------------
-- $Id: util_intr_split.vhd,v 1.1 2003/10/02 22:48:54 abq_ip Exp $
-------------------------------------------------------------------------------
-- util_intr_split.vhd - Entity and architecture
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: util_intr_split.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- util_intr_split.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/10/02 22:48:54 $
--
-- History:
-- goran 2003-05-19 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity util_intr_split is
generic (
C_SIZE_IN : integer := 2);
--C_LEFT_POS : integer := 0;
--C_SPLIT : integer := 1);
port (
Sig : in std_logic_vector(0 to C_SIZE_IN-1);
Out1 : out std_logic;
Out2 : out std_logic);
--Out1 : out std_logic_vector(C_LEFT_POS to C_SPLIT-1);
--Out2 : out std_logic_vector(C_SPLIT to C_SIZE_IN-1));
end entity util_intr_split;
architecture IMP of util_intr_split is
begin -- architecture IMP
Out1 <= Sig(0);
Out2 <= Sig(1);
--Out1 <= Sig(C_LEFT_POS to C_SPLIT-1);
--Out2 <= Sig(C_SPLIT to C_SIZE_IN-1);
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_scheduler_v1_00_a/devl/bfmsim/pcores/plb_scheduler_tb_v1_00_a/simhdl/vhdl/plb_scheduler_tb.vhd | 3 | 21916 | ------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
-- DO NOT CHANGE THE entity name, architecture name, generic parameter
-- declaration or port declaration of this file. You may add components,
-- instances, constants, signals, etc. as you wish.
--
-- See IBM Bus Functional Model Toolkit User's Manual for more information
-- on the BFMs.
--
------------------------------------------------------------------------------
-- plb_scheduler_tb.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_scheduler_tb.vhd
-- Version: 1.00.a
-- Description: IP testbench
-- Date: Mon Apr 6 14:20:49 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library plb_scheduler_v1_00_a;
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity plb_scheduler_tb is
------------------------------------------
-- DO NOT CHANGE THIS GENERIC DECLARATION
------------------------------------------
generic
(
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
);
------------------------------------------
-- DO NOT CHANGE THIS PORT DECLARATION
------------------------------------------
port
(
-- PLB (v4.6) bus interface, do not add or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity plb_scheduler_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of plb_scheduler_tb is
--USER testbench signal declarations added here as you wish
------------------------------------------
-- Signal to hook up master detected error and synch bus
------------------------------------------
signal sig_dev_mderr : std_logic;
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant MST_ERROR : integer := 30;
constant INTERRUPT : integer := 31;
signal my_reset : std_logic;
begin
------------------------------------------
-- Instance of IP under test.
-- Communication with the BFL is by using SYNCH_IN/SYNCH_OUT signals.
------------------------------------------
UUT : entity plb_scheduler_v1_00_a.plb_scheduler
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_SUPPORT_BURSTS => C_SPLB_SUPPORT_BURSTS,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_SPLB_CLK_PERIOD_PS => C_SPLB_CLK_PERIOD_PS,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY,
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_P2P => C_MPLB_P2P,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_MPLB_CLK_PERIOD_PS => C_MPLB_CLK_PERIOD_PS
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Soft_Reset => my_reset,
Reset_Done => open,
Soft_Stop => '0',
SWTM_DOB => (others => '0'),
SWTM_ADDRB => open,
SWTM_DIB => open,
SWTM_ENB => open,
SWTM_WEB => open,
TM2SCH_current_cpu_tid => (others => '0'),
TM2SCH_opcode => (others => '0'),
TM2SCH_data => (others => '0'),
TM2SCH_request => '0',
SCH2TM_busy => open,
SCH2TM_data => open,
SCH2TM_next_cpu_tid => open,
SCH2TM_next_tid_valid => open,
Preemption_Interrupt => open,
-- MAP USER PORTS ABOVE THIS LINE ------------------
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => sig_dev_mderr,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm
);
------------------------------------------
-- Hook up UUT MD_error to synch_out bit for Master Detected Error status monitor
------------------------------------------
SYNCH_OUT(MST_ERROR) <= sig_dev_mderr;
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
my_reset <= '1';
-- wait for end of reset
wait until (SPLB_Rst'EVENT and SPLB_Rst = '0');
my_reset <= '0';
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
-- wait for reset to be completed
wait for 200 ns;
------------------------------------------
-- Test User Logic Slave Register
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic Slave Register Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic Slave Register Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User Logic IP Master
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic IP Master Read Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master read ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master read transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue User Logic IP Master Write Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master write ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master write transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue the rest of User Logic IP Master Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic IP Master Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User I/Os and other features
------------------------------------------
--USER code added here to stimulate any user I/Os
wait;
end process TEST_PROCESS;
end architecture testbench;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp1/design/pcores/plb_scheduler_v1_00_a/hdl/vhdl/parallel.vhd | 11 | 9985 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity parallel is
generic
(
-- The number of input bits into the priority encoder
INPUT_BITS : integer := 128;
-- The number of output bits from the priority encoder.
-- For correct operation the number of output bits should be
-- any number greater than or equal to log2( INPUT_BITS ).
OUTPUT_BITS : integer := 7;
-- The number of bits to consider at a time.
-- This number should be less that INPUT_BITS and should divide
-- INPUT_BITS evenly.
CHUNK_BITS : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(0 to INPUT_BITS - 1);
enable : in std_logic;
output : out std_logic_vector(0 to OUTPUT_BITS - 1)
);
end entity parallel;
-------------------------------------------------------------------------------
-- architecture
-------------------------------------------------------------------------------
architecture imp of parallel is
type find_state is ( narrow_search, prior_encode, prior_read );
-- Find the log base 2 of a natural number.
-- This function works for both synthesis and simulation
function log2( N : in natural ) return positive is
begin
if N <= 2 then
return 1;
else
return 1 + log2(N/2);
end if;
end;
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
-- Return the array slice that is used for a given chunk index
function bit_range( data : in std_logic_vector; index : in integer ) return std_logic_vector is
begin
return data( (index * CHUNK_BITS) to ((index + 1) * CHUNK_BITS) - 1 );
end function;
-- Given the number of INPUT_BITS and the number of CHUNK_BITS we
-- can determine the number of chunks we will need to look at.
constant CHUNK_NUM : integer := INPUT_BITS / CHUNK_BITS;
-- Given the number of CHUNK_BITS we can determine the number of output
-- bits that the priority encoder is going to return.
constant CHUNK_OUT : integer := log2( CHUNK_BITS );
-- The number of EXTRA bits is the number of extra bits that we number add
-- to the output of the priority encoder to get the real output.
constant EXTRA_BITS : integer := OUTPUT_BITS - CHUNK_OUT;
-- These two signals control the state transitions in the FSM which
-- produces the output for this entity.
signal find_current : find_state;
signal find_next : find_state;
-- These signals are the input signals into the priority encoder.
signal pri_in : std_logic_vector(0 to CHUNK_BITS - 1);
signal pri_in_next : std_logic_vector(0 to CHUNK_BITS - 1);
-- This signal is the output from the priority encoder.
signal pri_out : std_logic_vector(0 to CHUNK_OUT - 1 );
-- This is the overall output from the design. It could be removed
-- by just assigning to output instead, however, that would mean that
-- output would need to be an inout signal instead of just an out.
signal best : std_logic_vector(0 to OUTPUT_BITS - 1);
signal best_next : std_logic_vector(0 to OUTPUT_BITS - 1);
-- These signals are used to narrow our search for the highest priority.
signal narrow : std_logic_vector(0 to CHUNK_NUM - 1);
signal narrow_next : std_logic_vector(0 to CHUNK_NUM - 1);
-- This forces the synthesizer to recognize the pri_out signal as the
-- output from a priority encoder. XST documentation says that the
-- synthesizer will recognize a priority encoder by setting this to
-- "yes" but will not actually generate a priority encoder unless this
-- is set to "force".
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of pri_out: signal is "force";
begin
-- Output the best priority
output <= best;
-- This process is the priority encoder. It will determine the highest bits
-- set in the array pri_in and will return its index on the signal pri_out.
--
-- Notice that this process is NOT sensitive to the clock. This process
-- would not be recognized as a priority encoder if it were sensitive to
-- the clock.
priority_encoder : process ( pri_in ) is
begin
-- The default output. It no bits are set in the array (or if only
-- bit 0 is set) then this is the value returned.
pri_out <= (others => '0');
-- This statement loops over the entire array and finds the index of the
-- highest bit set. The index of the highest bit set is then converted
-- into a std_logic_vector and output onto pri_out.
--
-- Notice that the loop starts at the highest index and proceeds to the
-- lowest index. This is because in our system the lower the bit index
-- the higher the priority.
for i in pri_in'high downto 0 loop
if( pri_in(i) = '1' ) then
pri_out <= std_logic_vector( to_unsigned(i, pri_out'length) );
end if;
end loop;
end process priority_encoder;
-- This process controls the state transition from the current state
-- to the next state (and also handles reset). It also takes care of
-- transitioning FSM inputs to there next values.
find_best_next : process ( clk, rst, find_next ) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
find_current <= narrow_search;
best <= (others => '0');
pri_in <= (others => '0');
narrow <= (others => '0');
else
find_current <= find_next;
best <= best_next;
pri_in <= pri_in_next;
narrow <= narrow_next;
end if;
end if;
end process find_best_next;
-- This process implements the FSM logic. It is broken into three states.
-- NARROW_SEARCH:
-- This state narrows the priority search by taking each chunk of the input and
-- or'ing all of the chunks bits together. This provides an indication of which
-- chunk of the input contains the highest priority.
--
-- This allows use to use a smaller priority encoder as the expense of a 2 clock
-- cycle delay. However, the smaller priority encoder provides significant savings
-- in terms of slice utilization.
--
-- PRIOR_ENCODE:
-- This state determines which of the chunks contains the highest priority input and
-- then places that chunk's input bits onto the priority encoders input lines. If no
-- bits in the input array are set then the priority encoders input lines are NOT
-- changed.
--
-- PRIOR_READ:
-- This state reads the data off of the priority encoder and then adds the extra bits
-- needed to produce the full priority value. This is done because the priority encoder
-- returns the index of the highest bit of the selected chunk but we want the index
-- of the highest bit set in the input not in the chunk.
--
-- Luckily, the translation from chunk index to input index it straight forward because
-- chunks are just non-overlapping slices of the input array.
find_best_logic : process( find_current, input, best, pri_in, narrow, pri_out, enable ) is
begin
find_next <= find_current;
best_next <= best;
pri_in_next <= pri_in;
narrow_next <= narrow;
case find_current is
when narrow_search =>
if( enable = '1' ) then
for i in narrow'high downto 0 loop
narrow_next(i) <= bit_set( bit_range( input, i ) );
end loop;
find_next <= prior_encode;
end if;
when prior_encode =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
pri_in_next <= bit_range( input, i );
--exit;
end if;
end loop;
find_next <= prior_read;
when prior_read =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
best_next <= std_logic_vector(to_unsigned(i,EXTRA_BITS)) & pri_out;
end if;
end loop;
find_next <= narrow_search;
end case;
end process find_best_logic;
end architecture imp;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_scheduler_smp_v1_00_a/hdl/vhdl/parallel.vhd | 11 | 9985 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity parallel is
generic
(
-- The number of input bits into the priority encoder
INPUT_BITS : integer := 128;
-- The number of output bits from the priority encoder.
-- For correct operation the number of output bits should be
-- any number greater than or equal to log2( INPUT_BITS ).
OUTPUT_BITS : integer := 7;
-- The number of bits to consider at a time.
-- This number should be less that INPUT_BITS and should divide
-- INPUT_BITS evenly.
CHUNK_BITS : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(0 to INPUT_BITS - 1);
enable : in std_logic;
output : out std_logic_vector(0 to OUTPUT_BITS - 1)
);
end entity parallel;
-------------------------------------------------------------------------------
-- architecture
-------------------------------------------------------------------------------
architecture imp of parallel is
type find_state is ( narrow_search, prior_encode, prior_read );
-- Find the log base 2 of a natural number.
-- This function works for both synthesis and simulation
function log2( N : in natural ) return positive is
begin
if N <= 2 then
return 1;
else
return 1 + log2(N/2);
end if;
end;
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
-- Return the array slice that is used for a given chunk index
function bit_range( data : in std_logic_vector; index : in integer ) return std_logic_vector is
begin
return data( (index * CHUNK_BITS) to ((index + 1) * CHUNK_BITS) - 1 );
end function;
-- Given the number of INPUT_BITS and the number of CHUNK_BITS we
-- can determine the number of chunks we will need to look at.
constant CHUNK_NUM : integer := INPUT_BITS / CHUNK_BITS;
-- Given the number of CHUNK_BITS we can determine the number of output
-- bits that the priority encoder is going to return.
constant CHUNK_OUT : integer := log2( CHUNK_BITS );
-- The number of EXTRA bits is the number of extra bits that we number add
-- to the output of the priority encoder to get the real output.
constant EXTRA_BITS : integer := OUTPUT_BITS - CHUNK_OUT;
-- These two signals control the state transitions in the FSM which
-- produces the output for this entity.
signal find_current : find_state;
signal find_next : find_state;
-- These signals are the input signals into the priority encoder.
signal pri_in : std_logic_vector(0 to CHUNK_BITS - 1);
signal pri_in_next : std_logic_vector(0 to CHUNK_BITS - 1);
-- This signal is the output from the priority encoder.
signal pri_out : std_logic_vector(0 to CHUNK_OUT - 1 );
-- This is the overall output from the design. It could be removed
-- by just assigning to output instead, however, that would mean that
-- output would need to be an inout signal instead of just an out.
signal best : std_logic_vector(0 to OUTPUT_BITS - 1);
signal best_next : std_logic_vector(0 to OUTPUT_BITS - 1);
-- These signals are used to narrow our search for the highest priority.
signal narrow : std_logic_vector(0 to CHUNK_NUM - 1);
signal narrow_next : std_logic_vector(0 to CHUNK_NUM - 1);
-- This forces the synthesizer to recognize the pri_out signal as the
-- output from a priority encoder. XST documentation says that the
-- synthesizer will recognize a priority encoder by setting this to
-- "yes" but will not actually generate a priority encoder unless this
-- is set to "force".
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of pri_out: signal is "force";
begin
-- Output the best priority
output <= best;
-- This process is the priority encoder. It will determine the highest bits
-- set in the array pri_in and will return its index on the signal pri_out.
--
-- Notice that this process is NOT sensitive to the clock. This process
-- would not be recognized as a priority encoder if it were sensitive to
-- the clock.
priority_encoder : process ( pri_in ) is
begin
-- The default output. It no bits are set in the array (or if only
-- bit 0 is set) then this is the value returned.
pri_out <= (others => '0');
-- This statement loops over the entire array and finds the index of the
-- highest bit set. The index of the highest bit set is then converted
-- into a std_logic_vector and output onto pri_out.
--
-- Notice that the loop starts at the highest index and proceeds to the
-- lowest index. This is because in our system the lower the bit index
-- the higher the priority.
for i in pri_in'high downto 0 loop
if( pri_in(i) = '1' ) then
pri_out <= std_logic_vector( to_unsigned(i, pri_out'length) );
end if;
end loop;
end process priority_encoder;
-- This process controls the state transition from the current state
-- to the next state (and also handles reset). It also takes care of
-- transitioning FSM inputs to there next values.
find_best_next : process ( clk, rst, find_next ) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
find_current <= narrow_search;
best <= (others => '0');
pri_in <= (others => '0');
narrow <= (others => '0');
else
find_current <= find_next;
best <= best_next;
pri_in <= pri_in_next;
narrow <= narrow_next;
end if;
end if;
end process find_best_next;
-- This process implements the FSM logic. It is broken into three states.
-- NARROW_SEARCH:
-- This state narrows the priority search by taking each chunk of the input and
-- or'ing all of the chunks bits together. This provides an indication of which
-- chunk of the input contains the highest priority.
--
-- This allows use to use a smaller priority encoder as the expense of a 2 clock
-- cycle delay. However, the smaller priority encoder provides significant savings
-- in terms of slice utilization.
--
-- PRIOR_ENCODE:
-- This state determines which of the chunks contains the highest priority input and
-- then places that chunk's input bits onto the priority encoders input lines. If no
-- bits in the input array are set then the priority encoders input lines are NOT
-- changed.
--
-- PRIOR_READ:
-- This state reads the data off of the priority encoder and then adds the extra bits
-- needed to produce the full priority value. This is done because the priority encoder
-- returns the index of the highest bit of the selected chunk but we want the index
-- of the highest bit set in the input not in the chunk.
--
-- Luckily, the translation from chunk index to input index it straight forward because
-- chunks are just non-overlapping slices of the input array.
find_best_logic : process( find_current, input, best, pri_in, narrow, pri_out, enable ) is
begin
find_next <= find_current;
best_next <= best;
pri_in_next <= pri_in;
narrow_next <= narrow;
case find_current is
when narrow_search =>
if( enable = '1' ) then
for i in narrow'high downto 0 loop
narrow_next(i) <= bit_set( bit_range( input, i ) );
end loop;
find_next <= prior_encode;
end if;
when prior_encode =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
pri_in_next <= bit_range( input, i );
--exit;
end if;
end loop;
find_next <= prior_read;
when prior_read =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
best_next <= std_logic_vector(to_unsigned(i,EXTRA_BITS)) & pri_out;
end if;
end loop;
find_next <= narrow_search;
end case;
end process find_best_logic;
end architecture imp;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/numa3_hwti/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/common.vhd | 11 | 19809 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package common is
-- Synch Manager Operations
constant SYNCH_LOCK : std_logic_vector(0 to 2) := "000";
constant SYNCH_UNLOCK : std_logic_vector(0 to 2) := "001";
constant SYNCH_TRY : std_logic_vector(0 to 2) := "010";
constant SYNCH_OWNER : std_logic_vector(0 to 2) := "011";
constant SYNCH_KIND : std_logic_vector(0 to 2) := "100";
constant SYNCH_COUNT : std_logic_vector(0 to 2) := "101";
constant SYNCH_RESULT : std_logic_vector(0 to 2) := "110";
-- Synch Manager Lock Types
constant SYNCH_FAST : std_logic_vector(0 to 1) := "00";
constant SYNCH_RECURS : std_logic_vector(0 to 1) := "01";
constant SYNCH_ERROR : std_logic_vector(0 to 1) := "10";
-- Constants for the status codes which are returned
constant SYNCH_LOCKSTA_CONTINUE : std_logic_vector(0 to 0) := "0";
constant SYNCH_LOCKSTA_BLOCK : std_logic_vector(0 to 0) := "1";
constant SYNCH_UNLOCKSTA_SUCCESS : std_logic_vector(0 to 0) := "0";
constant SYNCH_UNLOCKSTA_ERROR : std_logic_vector(0 to 0) := "1";
constant SYNCH_TRYLOCKSTA_SUCCESS : std_logic_vector(0 to 0) := "0";
constant SYNCH_TRYLOCKSTA_ERROR : std_logic_vector(0 to 0) := "1";
-- Constants used by this package
constant CMBITS : natural := 3;
constant KNBITS : natural := 2;
-- Calculate the number one for any given bit width
function one( n : in natural ) return std_logic_vector;
-- Calculate the number zero for any given bit width
function zero( n : in natural ) return std_logic_vector;
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive;
-- Calculate the 2 to the power n. This function can be used to determine
-- the maximum natural number which is representable by a given number
-- of bits.
function pow2( n : in natural ) return positive;
-- Determine if a number is exactly a power of two. This can be used
-- to check that generics are input as power of two (if that is what
-- is wanted).
function is_pow2( n : in natural ) return boolean;
-- Calculate the address used to add a thread to the thread scheduler.
function add_thread( base : in std_logic_vector;
tid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address used to store the result value from an add thread.
function add_result( base : in std_logic_vector ) return std_logic_vector;
-- Calculate a synchronization manager command
function synch_cmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector;
cmd : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_lockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_unlockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_trylockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_kindcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_countcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_ownercmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_locksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_unlocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_trylocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_kindsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_countsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_ownersta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
end package common;
package body common is
-- Calculate a synchronization manager command
function synch_cmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector;
cmd : in std_logic_vector ) return std_logic_vector is
variable addr : std_logic_vector(0 to DWID-1);
begin
addr := BASE;
addr(DWID-MBITS-2 to DWID-3) := mid;
addr(DWID-MBITS-TBITS-2 to DWID-MBITS-3) := tid;
addr(DWID-MBITS-TBITS-CMBITS-2 to DWID-MBITS-TBITS-3) := cmd;
return addr;
end function synch_cmd;
-- Calculate the address for a lock command
function synch_lockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_LOCK);
end function synch_lockcmd;
-- Extract status information for the lock operation
function synch_locksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
variable tmp : std_logic_vector(0 to 0);
begin
tmp(0) := sta(0) or sta(1);
return tmp;
end function synch_locksta;
-- Calculate the address for a lock command
function synch_unlockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_UNLOCK);
end function synch_unlockcmd;
-- Extract status information for the unlock operation
function synch_unlocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(0 to 0);
end function synch_unlocksta;
-- Calculate the address for a lock command
function synch_trylockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_TRY);
end function synch_trylockcmd;
-- Extract status information for the unlock operation
function synch_trylocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(1 to 1);
end function synch_trylocksta;
-- Calculate the address for a lock command
function synch_kindcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_KIND);
end function synch_kindcmd;
-- Extract status information for the unlock operation
function synch_kindsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(DWID-2 to DWID-1);
end function synch_kindsta;
-- Calculate the address for a lock command
function synch_ownercmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_OWNER);
end function synch_ownercmd;
-- Extract status information for the unlock operation
function synch_ownersta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(DWID-TBITS to DWID-1);
end function synch_ownersta;
-- Calculate the address for a lock command
function synch_countcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_COUNT);
end function synch_countcmd;
-- Extract status information for the unlock operation
function synch_countsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(DWID-CBITS to DWID-1);
end function synch_countsta;
-- Calculate the number one for any given bit width
function one( n : in natural ) return std_logic_vector is
variable o : std_logic_vector(0 to n-1);
begin
o(0 to n-2) := (others => '0');
o(n-1) := '1';
return o;
end function one;
-- Calculate the number zero for any given bit width
function zero( n : in natural ) return std_logic_vector is
variable z : std_logic_vector(0 to n-1);
begin
z(0 to n-1) := (others => '0');
return z;
end function zero;
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive is
begin
if n <= 2 then
return 1;
else
return 1 + log2(n/2);
end if;
end function log2;
-- Calculate the 2 to the power n. This function can be used to determine
-- the maximum natural number which is representable by a given number
-- of bits.
function pow2( n : in natural ) return positive is
begin
if n = 0 then
return 1;
else
return 2 * pow2( n - 1 );
end if;
end function pow2;
-- Determine if a number is exactly a power of two. This can be used
-- to check that generics are input as power of two (if that is what
-- is wanted).
function is_pow2( n : in natural ) return boolean is
variable l : positive;
variable p : positive;
begin
if( n = 1 ) then
return true;
end if;
if( (n mod 2) = 1 or n = 0) then
return false;
end if;
return is_pow2( n / 2 );
end function is_pow2;
-- Calculate the address used to add a thread to the thread scheduler.
function add_thread( base : in std_logic_vector; tid : in std_logic_vector ) return std_logic_vector is
begin
return base(0 to base'high - tid'length - 7) &
"00100" &
tid &
base(base'high-1 to base'high);
end function add_thread;
-- Calculate the address used to store the result value from an add thread.
function add_result( base : in std_logic_vector ) return std_logic_vector is
begin
return base(0 to base'high-2) & "11";
end function add_result;
end package body common;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_sync_manager_v1_00_a/hdl/vhdl/common.vhd | 11 | 19809 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package common is
-- Synch Manager Operations
constant SYNCH_LOCK : std_logic_vector(0 to 2) := "000";
constant SYNCH_UNLOCK : std_logic_vector(0 to 2) := "001";
constant SYNCH_TRY : std_logic_vector(0 to 2) := "010";
constant SYNCH_OWNER : std_logic_vector(0 to 2) := "011";
constant SYNCH_KIND : std_logic_vector(0 to 2) := "100";
constant SYNCH_COUNT : std_logic_vector(0 to 2) := "101";
constant SYNCH_RESULT : std_logic_vector(0 to 2) := "110";
-- Synch Manager Lock Types
constant SYNCH_FAST : std_logic_vector(0 to 1) := "00";
constant SYNCH_RECURS : std_logic_vector(0 to 1) := "01";
constant SYNCH_ERROR : std_logic_vector(0 to 1) := "10";
-- Constants for the status codes which are returned
constant SYNCH_LOCKSTA_CONTINUE : std_logic_vector(0 to 0) := "0";
constant SYNCH_LOCKSTA_BLOCK : std_logic_vector(0 to 0) := "1";
constant SYNCH_UNLOCKSTA_SUCCESS : std_logic_vector(0 to 0) := "0";
constant SYNCH_UNLOCKSTA_ERROR : std_logic_vector(0 to 0) := "1";
constant SYNCH_TRYLOCKSTA_SUCCESS : std_logic_vector(0 to 0) := "0";
constant SYNCH_TRYLOCKSTA_ERROR : std_logic_vector(0 to 0) := "1";
-- Constants used by this package
constant CMBITS : natural := 3;
constant KNBITS : natural := 2;
-- Calculate the number one for any given bit width
function one( n : in natural ) return std_logic_vector;
-- Calculate the number zero for any given bit width
function zero( n : in natural ) return std_logic_vector;
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive;
-- Calculate the 2 to the power n. This function can be used to determine
-- the maximum natural number which is representable by a given number
-- of bits.
function pow2( n : in natural ) return positive;
-- Determine if a number is exactly a power of two. This can be used
-- to check that generics are input as power of two (if that is what
-- is wanted).
function is_pow2( n : in natural ) return boolean;
-- Calculate the address used to add a thread to the thread scheduler.
function add_thread( base : in std_logic_vector;
tid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address used to store the result value from an add thread.
function add_result( base : in std_logic_vector ) return std_logic_vector;
-- Calculate a synchronization manager command
function synch_cmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector;
cmd : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_lockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_unlockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_trylockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_kindcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_countcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_ownercmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_locksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_unlocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_trylocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_kindsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_countsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_ownersta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
end package common;
package body common is
-- Calculate a synchronization manager command
function synch_cmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector;
cmd : in std_logic_vector ) return std_logic_vector is
variable addr : std_logic_vector(0 to DWID-1);
begin
addr := BASE;
addr(DWID-MBITS-2 to DWID-3) := mid;
addr(DWID-MBITS-TBITS-2 to DWID-MBITS-3) := tid;
addr(DWID-MBITS-TBITS-CMBITS-2 to DWID-MBITS-TBITS-3) := cmd;
return addr;
end function synch_cmd;
-- Calculate the address for a lock command
function synch_lockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_LOCK);
end function synch_lockcmd;
-- Extract status information for the lock operation
function synch_locksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
variable tmp : std_logic_vector(0 to 0);
begin
tmp(0) := sta(0) or sta(1);
return tmp;
end function synch_locksta;
-- Calculate the address for a lock command
function synch_unlockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_UNLOCK);
end function synch_unlockcmd;
-- Extract status information for the unlock operation
function synch_unlocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(0 to 0);
end function synch_unlocksta;
-- Calculate the address for a lock command
function synch_trylockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_TRY);
end function synch_trylockcmd;
-- Extract status information for the unlock operation
function synch_trylocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(1 to 1);
end function synch_trylocksta;
-- Calculate the address for a lock command
function synch_kindcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_KIND);
end function synch_kindcmd;
-- Extract status information for the unlock operation
function synch_kindsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(DWID-2 to DWID-1);
end function synch_kindsta;
-- Calculate the address for a lock command
function synch_ownercmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_OWNER);
end function synch_ownercmd;
-- Extract status information for the unlock operation
function synch_ownersta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(DWID-TBITS to DWID-1);
end function synch_ownersta;
-- Calculate the address for a lock command
function synch_countcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_COUNT);
end function synch_countcmd;
-- Extract status information for the unlock operation
function synch_countsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(DWID-CBITS to DWID-1);
end function synch_countsta;
-- Calculate the number one for any given bit width
function one( n : in natural ) return std_logic_vector is
variable o : std_logic_vector(0 to n-1);
begin
o(0 to n-2) := (others => '0');
o(n-1) := '1';
return o;
end function one;
-- Calculate the number zero for any given bit width
function zero( n : in natural ) return std_logic_vector is
variable z : std_logic_vector(0 to n-1);
begin
z(0 to n-1) := (others => '0');
return z;
end function zero;
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive is
begin
if n <= 2 then
return 1;
else
return 1 + log2(n/2);
end if;
end function log2;
-- Calculate the 2 to the power n. This function can be used to determine
-- the maximum natural number which is representable by a given number
-- of bits.
function pow2( n : in natural ) return positive is
begin
if n = 0 then
return 1;
else
return 2 * pow2( n - 1 );
end if;
end function pow2;
-- Determine if a number is exactly a power of two. This can be used
-- to check that generics are input as power of two (if that is what
-- is wanted).
function is_pow2( n : in natural ) return boolean is
variable l : positive;
variable p : positive;
begin
if( n = 1 ) then
return true;
end if;
if( (n mod 2) = 1 or n = 0) then
return false;
end if;
return is_pow2( n / 2 );
end function is_pow2;
-- Calculate the address used to add a thread to the thread scheduler.
function add_thread( base : in std_logic_vector; tid : in std_logic_vector ) return std_logic_vector is
begin
return base(0 to base'high - tid'length - 7) &
"00100" &
tid &
base(base'high-1 to base'high);
end function add_thread;
-- Calculate the address used to store the result value from an add thread.
function add_result( base : in std_logic_vector ) return std_logic_vector is
begin
return base(0 to base'high-2) & "11";
end function add_result;
end package body common;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/condvar_tb.vhd | 9 | 5092 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:46:38 06/16/2009
-- Design Name:
-- Module Name: /home/jagron/ise_projects/cond_var/proj/condvar_tb.vhd
-- Project Name: proj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: condvar
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
ENTITY condvar_tb IS
END condvar_tb;
ARCHITECTURE behavior OF condvar_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT condvar
PORT(
msg_chan_channelDataIn : OUT std_logic_vector(0 to 7);
msg_chan_channelDataOut : IN std_logic_vector(0 to 7);
msg_chan_exists : IN std_logic;
msg_chan_full : IN std_logic;
msg_chan_channelRead : OUT std_logic;
msg_chan_channelWrite : OUT std_logic;
cmd : IN std_logic;
opcode : IN std_logic_vector(0 to 1);
cvar : IN std_logic_vector(0 to 7);
tid : IN std_logic_vector(0 to 7);
ack : OUT std_logic;
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
--Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to 1) := (others => '0');
signal cvar : std_logic_vector(0 to 7) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal clock_sig : std_logic := '0';
signal reset_sig : std_logic := '0';
--Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
-- Clock period definitions
constant clock_sig_period : time := 10 ns;
constant C_ENQ : std_logic_vector(0 to 2-1) := conv_std_logic_vector(0, 2); -- Opcode for "wait" enqueue
constant C_DEQ : std_logic_vector(0 to 2-1) := conv_std_logic_vector(1, 2); -- Opcode for "signal" dequeue
constant C_DEQALL : std_logic_vector(0 to 2-1) := conv_std_logic_vector(2, 2); -- Opcode for "broadcast" dequeue
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: condvar PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
cmd => cmd,
opcode => opcode,
cvar => cvar,
tid => tid,
ack => ack,
clock_sig => clock_sig,
reset_sig => reset_sig
);
-- Clock process definitions
clock_sig_process :process
begin
clock_sig <= '0';
wait for clock_sig_period/2;
clock_sig <= '1';
wait for clock_sig_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure operation(aopcode : in std_logic_vector(0 to 1); acvar: in integer; atid : in integer) is
begin
-- Send a packet
wait until clock_sig = '0' and ack = '0';
cvar <= conv_std_logic_vector(acvar,8);
tid <= conv_std_logic_vector(atid,8);
cmd <= '1';
opcode <= aopcode;
wait until ack = '1';
cvar <= conv_std_logic_vector(0, 8);
tid <= conv_std_logic_vector(0, 8);
cmd <= '0';
opcode <= "00";
wait until clock_sig = '0';
wait for 4*clock_sig_period;
end procedure operation;
begin
wait for clock_sig_period*10;
-- Reset the core
reset_sig <= '1';
wait for clock_sig_period;
reset_sig <= '0';
wait for clock_sig_period;
-- Delay
wait for clock_sig_period*2048;
-- ENQ
operation(C_ENQ,0,9);
-- ENQ
operation(C_ENQ,0,7);
-- ENQ
operation(C_ENQ,0,5);
-- ENQ
operation(C_ENQ,0,3);
-- ENQ
operation(C_ENQ,1,10);
-- ENQ
operation(C_ENQ,1,8);
-- ENQ
operation(C_ENQ,1,6);
-- ENQ
operation(C_ENQ,1,4);
-- DEQ
operation(C_DEQ,0,0);
operation(C_DEQ,0,0);
operation(C_DEQ,0,0);
-- DEQ-ALL
operation(C_DEQALL,1,0);
-- DEQ-ALL
operation(C_DEQALL,0,0);
wait;
end process;
END;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/ipif_control_rd.vhd | 3 | 35921 | -------------------------------------------------------------------------------
-- $Id: ipif_control_rd.vhd,v 1.1 2003/03/15 01:05:25 ostlerf Exp $
-------------------------------------------------------------------------------
--ipif_control_rd.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_control_rd.vhd
--
-- Description: This VHDL design file is for the Point Design of the Mauna
-- Loa Read Packet FIFO IPIF Local Bus Interface control
-- block.
--
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs. Separate lines with blank lines if necessary to
-- improve readability.
--
-- ipif_control_rd.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe March 19,2001 -- V1.00a
--
-- Doug Thorpe June 08-12,2001 -- V1.00b
-- - Corrected an error condition where the FIFO2Bus_Error was getting set
-- at the end of a legitimate burst read operation. If the RdFIFO goes
-- empty after the initiation of the read (at least one FIFO2Bus_RdAck
-- has been issued), an 'Empty' condition causes only an inhibit of the
-- FIFO2Bus_RdAck signal.
-- - Fixed the implimentation of the MIR inclusion/occlusion through the
-- use of if--generate clauses.
--
-- DET June 25, 2001 V1.00c
-- - Removed redundant logic assignments flagged by
-- Synplicity
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
--
-- DET Aug 20, 2001 Version v1.01a
-- - Platform Generator Compliancy modifications
--
-- DET Sept 17, 2001
-- - Size optimization changes
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
entity ipif_control_rd is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for disable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_INTFC_TYPE : integer range 0 to 31 := 1;
-- IPIF block protocol Type
C_VERSION_MAJOR : integer range 0 to 9 := 1;
-- Major versioning of top level design
C_VERSION_MINOR : integer range 0 to 99 := 2;
-- Minor Version of top level design
C_VERSION_REV : integer range 0 to 26 := 0;
-- Revision letter of top level design
C_FIFO_WIDTH : Integer := 32;
-- Width of FIFO data in bits
C_DP_ADDRESS_WIDTH : Integer := 9;
-- Indicates address width of RdFIFO memory
-- (= log2(fifo_depth)
C_SUPPORT_BURST : Boolean := true;
-- Indicates read burst support for the IPIF bus
C_IPIF_DBUS_WIDTH : Integer := 32
-- Width of the IPIF data bus in bits
);
port (
-- Inputs From the IPIF Bus
Bus_rst : In std_logic; -- Master Reset from the IPIF
Bus_Clk : In std_logic; -- Master timing clock from the IPIF
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(C_IPIF_DBUS_WIDTH-4 to
C_IPIF_DBUS_WIDTH-1);
-- Inputs from the FIFO Interface Logic
Fifo_rd_data : In std_logic_vector(0 to C_FIFO_WIDTH-1);
BRAMFifo_RdAck : In std_logic;
SRLFifo_RdAck : In std_logic;
Occupancy : In std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
AlmostEmpty : In std_logic;
Empty : In std_logic;
Deadlock : In std_logic;
-- Outputs to the FIFO
Fifo_rst : Out std_logic;
BRAMFifo_RdReq : Out std_logic;
SRLFifo_RdReq : Out std_logic;
Fifo_burst_rd_xfer : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock : Out std_logic;
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end ipif_control_rd ;
-------------------------------------------------------------------------------
architecture implementation of ipif_control_rd is
-- COMPONENTS
-- No components
--TYPES
-- no types
-- CONSTANTS
-- Module Software Reset screen value for write data
Constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- This requires a Hex 'A' to be written
-- to ativate the S/W reset port
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
--INTERNAL SIGNALS
signal bus_data_out : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal sw_reset_error : std_logic;
signal reg_occupancy : std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Signal reg_almostempty : std_logic;
Signal reg_empty : std_logic;
Signal reg_deadlock : std_logic;
Signal reg_rdce2 : std_logic;
Signal reg_wrce1 : std_logic;
Signal reg_rdreq : std_logic;
Signal read_ack : std_logic;
Signal reg_read_ack : std_logic;
Signal write_ack : std_logic;
Signal rd_access_error : std_logic;
Signal wr_access_error : std_logic;
Signal burst_rd_xfer : std_logic;
Signal read_req : std_logic;
Signal reg_read_req : std_logic;
Signal write_req : std_logic;
Signal fifo_rd_req : std_logic;
Signal fifo_errack_inhibit : std_logic;
Signal rd_vect : std_logic_vector(0 to 3);
Signal sig_srl_rdack : std_logic;
Signal sig_bram_rdack : std_logic;
Signal sig_rst_match : std_logic;
Signal sig_rst_vect : std_logic_vector(0 to 1);
Signal sig_fifo_rd_data : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-------------------------------------------------------------------------------
---------- start architecture logic -------------------------------------------
begin
-- General access detection (used to terminate reply signal to the Bus)
read_req <= (Bus2FIFO_RdCE1 or Bus2FIFO_RdCE2 or Bus2FIFO_RdCE3);
write_req <= (Bus2FIFO_WrCE1 or Bus2FIFO_WrCE2 or Bus2FIFO_WrCE3);
-- I/O assignments
FIFO2Bus_DBus <= bus_data_out;
FIFO2Bus_ToutSup <= LOGIC_LOW; -- output signal not currently used so
-- drive low .
FIFO2Bus_Retry <= LOGIC_LOW; -- output signal not currently used so
-- drive low.
FIFO2Bus_WrAck <= write_ack and write_req; -- connect the write
-- acknowledge (drive only
-- if a request is present)
FIFO2Bus_RdAck <= read_ack and read_req; -- connect the read
-- acknowledge (drive only if
-- a request is present)
FIFO2Bus_Error <= (sw_reset_error or
rd_access_error or
wr_access_error) and
(read_req or write_req);
FIFO2IRPT_DeadLock <= Deadlock;
BRAMFifo_RdReq <= Bus_RdReq and Bus2FIFO_RdCE3; -- Read Request to BRAM
-- based FIFO.
SRLFifo_RdReq <= reg_rdreq and Bus2FIFO_RdCE3; -- Read Request to SRL
-- based FIFO
Fifo_burst_rd_xfer <= burst_rd_xfer; -- Burst detect signal to FIFO read
-- controller
sig_srl_rdack <= SRLFifo_RdAck;
sig_bram_rdack <= BRAMFifo_RdAck;
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- The FIFO data bus width is smaller than the IPIF data bus width so connect
-- the smaller FIFO data to LSB position of data bus to IPIF interface and
-- set the remaining data bus bits to zeroes.
-------------------------------------------------------------------------------
BUS_BIGGER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH > C_FIFO_WIDTH) generate
CONNECT_DBUS : process (fifo_rd_data)
Begin
sig_fifo_rd_data <= (others => '0'); --default bus state
for j in 0 to C_FIFO_WIDTH-1 loop
sig_fifo_rd_data(C_IPIF_DBUS_WIDTH-C_FIFO_WIDTH+j)
<= fifo_rd_data(j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_BIGGER_THAN_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is equal to the IPIF data bus width so connect
-- the FIFO data to IPIF data interface.
-------------------------------------------------------------------------------
BUS_EQUAL_TO_FIFO : if (C_IPIF_DBUS_WIDTH = C_FIFO_WIDTH) generate
sig_fifo_rd_data <= fifo_rd_data;
end generate BUS_EQUAL_TO_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is bigger than the IPIF data bus width !!BAD!!!
-- Connect the LSBits of the FIFO data to the IPIF data bus interface,
-- Don't use (truncate) the MSBits of the FIFO data spilling over the IPIF
-- data bus width.
-------------------------------------------------------------------------------
BUS_SMALLER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH < C_FIFO_WIDTH) generate
CONNECT_DBUS : process (fifo_rd_data)
Begin
for j in C_IPIF_DBUS_WIDTH-1 downto 0 loop
sig_fifo_rd_data(j) <= fifo_rd_data(C_FIFO_WIDTH-
C_IPIF_DBUS_WIDTH+j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_SMALLER_THAN_FIFO;
------------------------------------------------------------------------------
-- Register the input chip enables
------------------------------------------------------------------------------
REGISTER_CHIP_ENABLES : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_rdce2 <= '0';
reg_wrce1 <= '0';
reg_rdreq <= '0';
reg_read_req <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
reg_rdce2 <= Bus2FIFO_RdCE2;
reg_wrce1 <= Bus2FIFO_WrCE1;
reg_rdreq <= Bus_RdReq;
reg_read_req <= read_req;
Else
null;
End if;
End process; -- REGISTER_CHIP_ENABLES
INCLUDE_BURST : if (C_SUPPORT_BURST = true) generate
--burst_rd_xfer <= reg_rdreq and Bus_RdReq;
-------------------------------------------------------------------------
-- This process detects the completion of at least one valid FIFO data
-- read cycle during a burst read.
-------------------------------------------------------------------------
GEN_ERRACK_INHIB : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
fifo_errack_inhibit <= '0';
burst_rd_xfer <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1' ) Then
burst_rd_xfer <= reg_rdreq and Bus_RdReq;
If (Bus2FIFO_RdCE3 = '1' and sig_bram_rdack = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_RdCE3 = '1' and sig_srl_rdack = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_RdCE3 = '0') Then
fifo_errack_inhibit <= '0';
else
null;
End if;
else
null;
End if;
End process; -- GEN_ERRACK_INHIB
end generate INCLUDE_BURST;
OMIT_BURST : if (C_SUPPORT_BURST = false) generate
burst_rd_xfer <= '0';
fifo_errack_inhibit <= '0';
end generate OMIT_BURST;
-------------------------------------------------------------------------------
-- Assemble and latch the FIFO status register fields
-------------------------------------------------------------------------------
GET_STATUS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_occupancy <= (others => '0');
reg_deadlock <= '0';
reg_almostempty <= '0';
reg_empty <= '1';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
If (reg_rdce2 = '1') Then -- hold last value registered during
-- read operation.
null;
else -- register new status every clock
reg_occupancy <= Occupancy ;
reg_deadlock <= Deadlock ;
reg_almostempty <= AlmostEmpty ;
reg_empty <= Empty ;
End if;
else
null; -- do nothing
End if;
End process; -- GET_STATUS
sig_rst_match <= Bus_DBus(C_IPIF_DBUS_WIDTH-4)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-3))
and Bus_DBus(C_IPIF_DBUS_WIDTH-2)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-1));
sig_rst_vect <= sig_rst_match & Bus2FIFO_WrCE1;
------------------------------------------------------------------------------
-- Generate the S/W reset as a result of an IPIF Bus write to register
-- port 1 and data on the DBus inputs matching the Reset match value.
------------------------------------------------------------------------------
GENERATE_SOFTWARE_RESET : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
Fifo_rst <= '1';
sw_reset_error <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
Case sig_rst_vect Is
When "11" =>
Fifo_rst <= '1';
sw_reset_error <= '0';
When "01" =>
Fifo_rst <= '0';
sw_reset_error <= '1';
When others =>
Fifo_rst <= '0';
sw_reset_error <= '0';
End case;
Else
null;
End if;
End process; -- GENERATE_SOFTWARE_RESET
-- Synthesis for MIR inclusion ------------------------------------------------
Include_MIR :if (C_MIR_ENABLE = True) generate
signal mir_value : std_logic_vector(0 to 31);
Signal mir_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics and Constants
-- Conversion to std_logic_vector is required
----------------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MAJOR, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MINOR, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_VERSION_REV, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_BLOCK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_INTFC_TYPE, 8);
BUS_LEQ_32 : if (C_IPIF_DBUS_WIDTH <= 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
for j in 0 to C_IPIF_DBUS_WIDTH-1 loop
mir_bus(j) <= mir_value((32-C_IPIF_DBUS_WIDTH)+j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_LEQ_32;
BUS_GT_32 : if (C_IPIF_DBUS_WIDTH > 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
mir_bus <= (others => '0'); -- default bus values
for j in 0 to 31 loop
mir_bus((C_IPIF_DBUS_WIDTH-32)+j) <= mir_value(j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_GT_32;
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0';
-- Occupancy is not scaled in this case.
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostempty ;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the occupancy value down.
-- Note status_bus bit 3 is not set, signaling a complete occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '0' ; -- occupancy is not scaled
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the occupancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '1'; -- occupancy is scaled to fit
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, mir_bus, status_bus,
sig_fifo_rd_data, rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1001" => -- Read MIR port
bus_data_out <= mir_bus;
When "1010" => -- Read Status port
bus_data_out <= status_bus;
When "1100" => -- Read FIFO data port
bus_data_out <= sig_fifo_rd_data;
When others => -- default to zeroes
bus_data_out <= (others => '0');
End case;
End process; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE3 = '1' and Empty = '1' and
fifo_errack_inhibit = '0') Then -- attempting to read the
-- rdfifo with an empty
rd_access_error <= '1'; -- condition is an error,
-- but only on the
-- initiation of the read
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Include_MIR;
-------------------------------------------------------------------------------
-- Synthesis for MIR occlusion
-------------------------------------------------------------------------------
Occlude_MIR : if (C_MIR_ENABLE = False) generate
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
-- occupancy is not scaled in this case.
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostempty ;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the occupancy value down.
-- Note status_bus bit 3 is not set, signaling a complete occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '0' ; -- occupancy is not scaled
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the occupancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus(4 to C_IPIF_DBUS_WIDTH-1) <= (others => '0');
-- set default bus values
status_bus(3) <= '1' ;
-- Indicate occupancy is scaled to fit
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, sig_fifo_rd_data,
status_bus, rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1010" =>
bus_data_out <= status_bus;
When "1100" =>
bus_data_out <= sig_fifo_rd_data;
When others =>
bus_data_out <= (others => '0');
End case;
End process ; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE1 = '1') Then -- attempting to read MIR but it
-- is not included
rd_access_error <= '1';
Elsif (Bus2FIFO_RdCE3 = '1' and Empty = '1' and
fifo_errack_inhibit = '0') Then -- attempting to read the
-- rdfifo with an empty
rd_access_error <= '1'; -- condition is an error,
-- but only on the
-- initiation of the read
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Occlude_MIR;
-------------------------------------------------------------------------------
-- Generate the Read Acknowledge to the Bus
-------------------------------------------------------------------------------
GEN_READ_ACK : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_read_ack <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (Bus2FIFO_RdCE1 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE2 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE3 = '1') Then
reg_read_ack <= sig_bram_rdack;
else
reg_read_ack <= '0';
End if;
Else
null;
End if;
End process; -- GEN_READ_ACK
read_ack <= reg_read_ack
or rd_access_error
or sig_srl_rdack;
write_ack <= reg_wrce1 or wr_access_error;
-------------------------------------------------------------------------------
-- Generate the Write Error Acknowledge Reply to the Bus when
-- an attempted write access by the IPIF Local Bus is invalid
-------------------------------------------------------------------------------
--GEN_WR_ERROR : process (Bus2FIFO_WrCE2, Bus2FIFO_WrCE3)
GEN_WR_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
wr_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_WrCE2 = '1') Then -- attempting to write to the status
-- register.
wr_access_error <= '1';
ElsIf (Bus2FIFO_WrCE3 = '1') Then -- attempting a write to the FIFO
-- Read data port.
wr_access_error <= '1';
Else
wr_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_WR_ERROR
end implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/xps_bram_if_cntlr_v1_00_b/hdl/vhdl/xbic_be_reset_gen.vhd | 2 | 10315 | -------------------------------------------------------------------------------
-- $Id: xbic_be_reset_gen.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_be_reset_gen - entity / architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_be_reset_gen.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
-------------------------------------------------------------------------------
-- Author: GAB
--
-- History:
--
-- DET Feb-5-07
-- ~~~~~~
-- -- Special version for the XPS BRAM IF Cntlr that is adapted
-- from plbv46_slave_burst_V1_00_a library
-- ^^^^^^
--
-- DET 3/6/2007 Reduced latency revision
-- ~~~~~~
-- - Added missing 64-bit case for when C_SMALLEST = 32 and C_NATIVE_DWIDTH=128.
-- this cause bus2ip_be to be driven incorrectly for address offets 0x4,
-- 0x5, 0x6,and 0x7.
-- ^^^^^^
--
-- DET 5/24/2007 Jm
-- ~~~~~~
-- - Changed the design to output active low BE reset mask.
-- - Modifed output Mask width to be the full width of the BE bus.
-- ^^^^^^
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity xbic_be_reset_gen is
generic (
C_NATIVE_DWIDTH : integer := 32;
C_SMALLEST : integer := 32
);
port(
Addr : in std_logic_vector(0 to 1);
MSize : in std_logic_vector(0 to 1);
BE_Sngl_Mask : out std_logic_vector(0 to (C_NATIVE_DWIDTH/8) - 1)
);
end entity xbic_be_reset_gen;
architecture implementation of xbic_be_reset_gen is
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal reset_be_extended : std_logic_vector(0 to (C_NATIVE_DWIDTH/8) - 1);
------------------------------------------------------------------------------
-- Architecture BEGIN
------------------------------------------------------------------------------
begin
BE_Sngl_Mask <= not(reset_be_extended);
GEN_FOR_SAME : if C_NATIVE_DWIDTH <= C_SMALLEST generate
reset_be_extended <= (others => '0');
end generate GEN_FOR_SAME;
---------------------
-- 64 Bit Support --
---------------------
GEN_BE_64_32: if C_NATIVE_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,MSize)
begin
addr_bits <= Addr(1); --a29
reset_be_extended <= (others => '0');
case addr_bits is
when '0' =>
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "00001111";
when others => null;
end case;
when '1' =>
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "11110000";
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_BE_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_BE_128_32: if C_NATIVE_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,MSize)
begin
addr_bits <= Addr; -- 24 25 26 27 | 28 29 30 31
reset_be_extended <= (others => '0');
case addr_bits is
when "00" => --0
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "0000111111111111";
when "01" => -- 64-Bit Master
reset_be_extended <= "0000000011111111";
when others => null;
end case;
when "01" => --4
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "1111000011111111";
when "01" => -- 64-Bit Master -- GAB 12/22/06
reset_be_extended <= "0000000011111111";
when others => null;
end case;
when "10" => --8
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "1111111100001111";
when "01" => -- 64-Bit Master
reset_be_extended <= "1111111100000000";
when others => null;
end case;
when "11" => --C
case MSize is
when "00" => --32-Bit Master
reset_be_extended <= "1111111111110000";
when "01" => --64-Bit Master
reset_be_extended <= "1111111100000000";
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_BE_128_32;
GEN_BE_128_64: if C_NATIVE_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,MSize)
begin
addr_bits <= Addr(0);
reset_be_extended <= (others => '0');
case addr_bits is
when '0' =>
case MSize is
when "01" => -- 64-Bit Master
reset_be_extended <= "0000000011111111";
when others => null;
end case;
when '1' => --8
case MSize is
when "01" => -- 64-Bit Master
reset_be_extended <= "1111111100000000";
when others => null;
end case;
when others =>
null;
end case;
end process CONNECT_PROC;
end generate GEN_BE_128_64;
end implementation; -- (architecture)
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_hwti_v1_00_a/hdl/vhdl/plb_hwti.vhd | 2 | 40730 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_e;
use ipif_common_v1_00_e.ipif_pkg.all;
library plb_ipif_v2_01_a;
use plb_ipif_v2_01_a.all;
library plb_hwti_v1_00_a;
use plb_hwti_v1_00_a.all;
library fsl_v20_v2_10_a;
use fsl_v20_v2_10_a.all;
entity plb_hwti is
generic
(
C_MANAG_BASE : std_logic_vector := x"60000000";
C_SCHED_BASE : std_logic_vector := x"61000000";
C_MUTEX_BASE : std_logic_vector := x"75000000";
C_CONDV_BASE : std_logic_vector := x"74000000";
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_PLB_NUM_MASTERS : integer := 8;
C_PLB_MID_WIDTH : integer := 3;
C_FAMILY : string := "virtex2p"
);
port
(
U2HLOW_M_WRITE : in std_logic;
U2HLOW_M_DATA : in std_logic_vector(0 to 31);
U2HLOW_M_CONTROL : in std_logic;
U2HLOW_M_FULL : out std_logic;
U2HHIGH_M_WRITE : in std_logic;
U2HHIGH_M_DATA : in std_logic_vector(0 to 31);
U2HHIGH_M_CONTROL : in std_logic;
U2HHIGH_M_FULL : out std_logic;
H2ULOW_S_READ : in std_logic;
H2ULOW_S_DATA : out std_logic_vector(0 to 31);
H2ULOW_S_CONTROL : out std_logic;
H2ULOW_S_EXISTS : out std_logic;
H2UHIGH_S_READ : in std_logic;
H2UHIGH_S_DATA : out std_logic_vector(0 to 31);
H2UHIGH_S_CONTROL : out std_logic;
H2UHIGH_S_EXISTS : out std_logic;
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_MErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_PLB_AWIDTH-1);
PLB_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1)
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity plb_hwti;
architecture IMP of plb_hwti is
signal USER2HWTIL_S_READ : std_logic;
signal USER2HWTIL_S_DATA : std_logic_vector(0 to 31);
signal USER2HWTIL_S_CONTROL : std_logic;
signal USER2HWTIL_S_EXISTS : std_logic;
signal USER2HWTIL_M_WRITE : std_logic;
signal USER2HWTIL_M_DATA : std_logic_vector(0 to 31);
signal USER2HWTIL_M_CONTROL : std_logic;
signal USER2HWTIL_M_FULL : std_logic;
signal USER2HWTIH_S_READ : std_logic;
signal USER2HWTIH_S_DATA : std_logic_vector(0 to 31);
signal USER2HWTIH_S_CONTROL : std_logic;
signal USER2HWTIH_S_EXISTS : std_logic;
signal USER2HWTIH_M_WRITE : std_logic;
signal USER2HWTIH_M_DATA : std_logic_vector(0 to 31);
signal USER2HWTIH_M_CONTROL : std_logic;
signal USER2HWTIH_M_FULL : std_logic;
signal USER2HWTI_S_READ : std_logic;
signal USER2HWTI_S_DATA : std_logic_vector(0 to 63);
signal USER2HWTI_S_CONTROL : std_logic;
signal USER2HWTI_S_EXISTS : std_logic;
signal USER2HWTI_M_WRITE : std_logic;
signal USER2HWTI_M_DATA : std_logic_vector(0 to 63);
signal USER2HWTI_M_CONTROL : std_logic;
signal USER2HWTI_M_FULL : std_logic;
signal HWTI2USERL_S_READ : std_logic;
signal HWTI2USERL_S_DATA : std_logic_vector(0 to 31);
signal HWTI2USERL_S_CONTROL : std_logic;
signal HWTI2USERL_S_EXISTS : std_logic;
signal HWTI2USERL_M_WRITE : std_logic;
signal HWTI2USERL_M_DATA : std_logic_vector(0 to 31);
signal HWTI2USERL_M_CONTROL : std_logic;
signal HWTI2USERL_M_FULL : std_logic;
signal HWTI2USERH_S_READ : std_logic;
signal HWTI2USERH_S_DATA : std_logic_vector(0 to 31);
signal HWTI2USERH_S_CONTROL : std_logic;
signal HWTI2USERH_S_EXISTS : std_logic;
signal HWTI2USERH_M_WRITE : std_logic;
signal HWTI2USERH_M_DATA : std_logic_vector(0 to 31);
signal HWTI2USERH_M_CONTROL : std_logic;
signal HWTI2USERH_M_FULL : std_logic;
signal HWTI2USER_S_READ : std_logic;
signal HWTI2USER_S_DATA : std_logic_vector(0 to 63);
signal HWTI2USER_S_CONTROL : std_logic;
signal HWTI2USER_S_EXISTS : std_logic;
signal HWTI2USER_M_WRITE : std_logic;
signal HWTI2USER_M_DATA : std_logic_vector(0 to 63);
signal HWTI2USER_M_CONTROL : std_logic;
signal HWTI2USER_M_FULL : std_logic;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant USER_SLAVE : integer := USER_00;
constant USER_MASTER : integer := USER_10;
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_SLAVE, -- user logic slave space (s/w addressable constrol/status registers)
1 => USER_MASTER -- user logic master space (ip master model registers)
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant SLAVE_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant SLAVE_HIGHADDR : std_logic_vector := C_BASEADDR or X"0000001F";
constant MASTER_BASEADDR : std_logic_vector := C_BASEADDR or X"00000020";
constant MASTER_HIGHADDR : std_logic_vector := C_BASEADDR or X"0000002F";
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & SLAVE_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & SLAVE_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & MASTER_BASEADDR, -- user logic master space base address
ZERO_ADDR_PAD & MASTER_HIGHADDR -- user logic master space high address
);
-- specify data width for each target address range.
constant USER_DWIDTH : integer := 64;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 32, -- user logic slave space data width
1 => 32 -- user logic master space data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant USER_NUM_SLAVE_CE : integer := 8;
constant USER_NUM_MASTER_CE : integer := 8;
constant USER_NUM_CE : integer := USER_NUM_SLAVE_CE+USER_NUM_MASTER_CE;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_SLAVE_CE), -- number of chip enableds for user logic slave space (one per register)
1 => pad_power2(USER_NUM_MASTER_CE) -- number of chip enables for user logic master space (one per register)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0), -- user logic slave space dependent properties (none defined)
1 => (others => 0) -- user logic master space dependent properties (none defined)
);
-- specify determinate timing parameters to be used during read
-- accesses for each address range, these values are used to optimize
-- data beat timing response for burst reads from addresses sources such
-- as ddr and sdram memory, each address space requires three integer
-- entries for mode [0-2], latency [0-31] and wait states [0-31].
constant ARD_DTIME_READ_ARRAY : INTEGER_ARRAY_TYPE :=
(
0, 0, 0, -- user logic slave space determinate read parameters
0, 0, 0 -- user logic master space determinate read parameters
);
-- specify determinate timing parameters to be used during write
-- accesses for each address range, they not used currently, so
-- all entries should be set to zeros.
constant ARD_DTIME_WRITE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0, 0, 0, -- user logic slave space determinate write parameters
0, 0, 0 -- user logic master space determinate write parameters
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the plb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- plb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 1;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 128.
constant DEV_MAX_BURST_SIZE : integer := 128;
-- specify size of the largest target burstable memory space (in
-- bytes and a power of 2), this is to optimize the size of the
-- internal burst address counters.
constant DEV_BURST_PAGE_SIZE : integer := 1024;
-- specify number of plb clock cycles are allowed before a
-- data phase transfer timeout, this feature is useful during
-- system integration and debug.
constant DEV_DPHASE_TIMEOUT : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a plb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of plb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify allowing dma busrt mode transactions or not.
constant DMA_ALLOW_BURST : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma, apply to software
-- design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000;
-- specify period of the plb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant PLB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the plb data bus width.
constant IPIF_DWIDTH : integer := C_PLB_DWIDTH;
-- specify ipif address bus size, used for future ipif optimization,
-- should be set equal to the plb address bus width.
constant IPIF_AWIDTH : integer := C_PLB_AWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_PLB_AWIDTH;
-- specify index for user logic slave/master spaces chip enable.
constant USER_SLAVE_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, get_id_index(ARD_ID_ARRAY, USER_SLAVE));
constant USER_MASTER_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, get_id_index(ARD_ID_ARRAY, USER_MASTER));
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_Data : std_logic_vector(0 to C_PLB_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iBus2IP_Data : std_logic_vector(0 to C_PLB_DWIDTH - 1);
signal iBus2IP_BE : std_logic_vector(0 to (C_PLB_DWIDTH/8) - 1);
signal iBus2IP_Burst : std_logic;
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Addr : std_logic_vector(0 to IPIF_AWIDTH - 1) := (others => '0');
signal iIP2Bus_MstBE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1) := (others => '0');
signal iIP2IP_Addr : std_logic_vector(0 to IPIF_AWIDTH - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iIP2Bus_MstNum : std_logic_vector(0 to log2(DEV_MAX_BURST_SIZE/(C_PLB_DWIDTH/8))) := (others => '0');
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to find_id_dwidth(ARD_ID_ARRAY, ARD_DWIDTH_ARRAY, IPIF_RDFIFO_DATA, 32)-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
begin
------------------------------------------
-- instantiate the PLB IPIF
------------------------------------------
PLB_IPIF_I : entity plb_ipif_v2_01_a.plb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_ARD_DTIME_READ_ARRAY => ARD_DTIME_READ_ARRAY,
C_ARD_DTIME_WRITE_ARRAY => ARD_DTIME_WRITE_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_DEV_BURST_PAGE_SIZE => DEV_BURST_PAGE_SIZE,
C_DEV_DPHASE_TIMEOUT => DEV_DPHASE_TIMEOUT,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_ALLOW_BURST => DMA_ALLOW_BURST,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_PLB_MID_WIDTH => C_PLB_MID_WIDTH,
C_PLB_NUM_MASTERS => C_PLB_NUM_MASTERS,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_PLB_CLK_PERIOD_PS => PLB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_IPIF_AWIDTH => IPIF_AWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
PLB_clk => PLB_Clk,
Reset => PLB_Rst,
Freeze => '0',
IP2INTC_Irpt => open,
PLB_ABus => PLB_ABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_ordered => PLB_ordered,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_pendReq => PLB_pendReq,
PLB_pendPri => PLB_pendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_compress => M_compress,
M_guarded => M_guarded,
M_ordered => M_ordered,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
IP2Bus_Clk => '0',
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Freeze => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '0',
Bus2IP_Addr => open,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_Burst => iBus2IP_Burst,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2IP_Addr => iIP2IP_Addr,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstNum => iIP2Bus_MstNum,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_IPMstTrans => open,
IP2RFIFO_WrReq => '0',
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_WrAck => open,
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_Data => open,
WFIFO2IP_RdAck => open,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
IP2Bus_DMA_Req => '0',
Bus2IP_DMA_Ack => open
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : entity plb_hwti_v1_00_a.user_logic
generic map
(
--C_MANAG_BASEADDR : std_logic_vector := x"00000000";
--C_SCHED_BASEADDR : std_logic_vector := x"00000000";
--C_MUTEX_BASEADDR : std_logic_vector := x"00000000";
--C_CONDV_BASEADDR : std_logic_vector := x"00000000";
USR_BASE => C_BASEADDR,
MTX_BASE => C_MUTEX_BASE,
CDV_BASE => C_CONDV_BASE,
SCH_BASE => C_SCHED_BASE,
MNG_BASE => C_MANAG_BASE,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE
)
port map
(
FSL_S_READ => USER2HWTI_S_READ,
FSL_S_DATA => USER2HWTI_S_DATA,
FSL_S_CONTROL => USER2HWTI_S_CONTROL,
FSL_S_EXISTS => USER2HWTI_S_EXISTS,
FSL_M_WRITE => HWTI2USER_M_WRITE,
FSL_M_DATA => HWTI2USER_M_DATA,
FSL_M_CONTROL => HWTI2USER_M_CONTROL,
FSL_M_FULL => HWTI2USER_M_FULL,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_Burst => iBus2IP_Burst,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstNum => iIP2Bus_MstNum,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr
);
user2hwti_low : entity fsl_v20_v2_10_a.fsl_v20
generic map
(
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 0,
C_USE_CONTROL => 1,
C_FSL_DWIDTH => 32,
C_FSL_DEPTH => 16
)
port map
(
FSL_Clk => PLB_Clk,
SYS_Rst => PLB_Rst,
FSL_Rst => open,
FSL_M_Clk => '0',
FSL_M_Data => USER2HWTIL_M_Data,
FSL_M_Control => USER2HWTIL_M_Control,
FSL_M_Write => USER2HWTIL_M_Write,
FSL_M_Full => USER2HWTIL_M_Full,
FSL_S_Clk => '0',
FSL_S_Data => USER2HWTIL_S_Data,
FSL_S_Control => USER2HWTIL_S_Control,
FSL_S_Read => USER2HWTIL_S_Read,
FSL_S_Exists => USER2HWTIL_S_Exists,
FSL_Full => open,
FSL_Has_Data => open,
FSL_Control_IRQ => open
);
user2hwti_high : entity fsl_v20_v2_10_a.fsl_v20
generic map
(
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 0,
C_USE_CONTROL => 1,
C_FSL_DWIDTH => 32,
C_FSL_DEPTH => 16
)
port map
(
FSL_Clk => PLB_Clk,
SYS_Rst => PLB_Rst,
FSL_Rst => open,
FSL_M_Clk => '0',
FSL_M_Data => USER2HWTIH_M_DATA,
FSL_M_Control => USER2HWTIH_M_CONTROL,
FSL_M_Write => USER2HWTIH_M_WRITE,
FSL_M_Full => USER2HWTIH_M_FULL,
FSL_S_Clk => '0',
FSL_S_Data => USER2HWTIH_S_DATA,
FSL_S_Control => USER2HWTIH_S_CONTROL,
FSL_S_Read => USER2HWTIH_S_READ,
FSL_S_Exists => USER2HWTIH_S_EXISTS,
FSL_Full => open,
FSL_Has_Data => open,
FSL_Control_IRQ => open
);
hwti2user_low : entity fsl_v20_v2_10_a.fsl_v20
generic map
(
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 0,
C_USE_CONTROL => 1,
C_FSL_DWIDTH => 32,
C_FSL_DEPTH => 16
)
port map
(
FSL_Clk => PLB_Clk,
SYS_Rst => PLB_Rst,
FSL_Rst => open,
FSL_M_Clk => '0',
FSL_M_Data => HWTI2USERL_M_DATA,
FSL_M_Control => HWTI2USERL_M_CONTROL,
FSL_M_Write => HWTI2USERL_M_WRITE,
FSL_M_Full => HWTI2USERL_M_FULL,
FSL_S_Clk => '0',
FSL_S_Data => HWTI2USERL_S_DATA,
FSL_S_Control => HWTI2USERL_S_CONTROL,
FSL_S_Read => HWTI2USERL_S_READ,
FSL_S_Exists => HWTI2USERL_S_EXISTS,
FSL_Full => open,
FSL_Has_Data => open,
FSL_Control_IRQ => open
);
hwti2user_high : entity fsl_v20_v2_10_a.fsl_v20
generic map
(
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 0,
C_USE_CONTROL => 1,
C_FSL_DWIDTH => 32,
C_FSL_DEPTH => 16
)
port map
(
FSL_Clk => PLB_Clk,
SYS_Rst => PLB_Rst,
FSL_Rst => open,
FSL_M_Clk => '0',
FSL_M_Data => HWTI2USERH_M_DATA,
FSL_M_Control => HWTI2USERH_M_CONTROL,
FSL_M_Write => HWTI2USERH_M_WRITE,
FSL_M_Full => HWTI2USERH_M_FULL,
FSL_S_Clk => '0',
FSL_S_Data => HWTI2USERH_S_DATA,
FSL_S_Control => HWTI2USERH_S_CONTROL,
FSL_S_Read => HWTI2USERH_S_READ,
FSL_S_Exists => HWTI2USERH_S_EXISTS,
FSL_Full => open,
FSL_Has_Data => open,
FSL_Control_IRQ => open
);
HWTI2USERL_M_DATA <= HWTI2USER_M_DATA(32 to 63);
HWTI2USERH_M_DATA <= HWTI2USER_M_DATA(0 to 31);
HWTI2USERL_M_CONTROL <= HWTI2USER_M_CONTROL;
HWTI2USERH_M_CONTROL <= HWTI2USER_M_CONTROL;
HWTI2USERL_M_WRITE <= HWTI2USER_M_WRITE;
HWTI2USERH_M_WRITE <= HWTI2USER_M_WRITE;
HWTI2USER_M_FULL <= HWTI2USERL_M_FULL or HWTI2USERH_M_FULL;
H2ULOW_S_DATA <= HWTI2USERL_S_DATA;
H2UHIGH_S_DATA <= HWTI2USERH_S_DATA;
H2ULOW_S_CONTROL <= HWTI2USERL_S_CONTROL;
H2UHIGH_S_CONTROL <= HWTI2USERH_S_CONTROL;
H2ULOW_S_EXISTS <= HWTI2USERL_S_EXISTS;
H2UHIGH_S_EXISTS <= HWTI2USERH_S_EXISTS;
HWTI2USERL_S_READ <= H2ULOW_S_READ or H2UHIGH_S_READ;
HWTI2USERH_S_READ <= H2ULOW_S_READ or H2UHIGH_S_READ;
USER2HWTIL_M_DATA <= U2HLOW_M_DATA;
USER2HWTIH_M_DATA <= U2HHIGH_M_DATA;
USER2HWTIL_M_CONTROL <= U2HLOW_M_CONTROL;
USER2HWTIH_M_CONTROL <= U2HHIGH_M_CONTROL;
USER2HWTIL_M_WRITE <= U2HLOW_M_WRITE;
USER2HWTIH_M_WRITE <= U2HHIGH_M_WRITE;
U2HLOW_M_FULL <= USER2HWTIL_M_FULL or USER2HWTIH_M_FULL;
U2HHIGH_M_FULL <= USER2HWTIL_M_FULL or USER2HWTIH_M_FULL;
USER2HWTI_S_DATA <= USER2HWTIH_S_DATA & USER2HWTIL_S_DATA;
USER2HWTI_S_CONTROL <= USER2HWTIL_S_CONTROL or USER2HWTIH_S_CONTROL;
USER2HWTI_S_EXISTS <= USER2HWTIL_S_EXISTS and USER2HWTIH_S_EXISTS;
USER2HWTIL_S_READ <= USER2HWTI_S_READ;
USER2HWTIH_S_READ <= USER2HWTI_S_READ;
--USER2HWTI_M_WRITE <= U2HLOW_M_WRITE and U2HHIGH_M_WRITE;
--USER2HWTI_M_DATA <= U2HLOW_M_DATA & U2HHIGH_M_DATA;
--USER2HWTI_M_CONTROL <= U2HLOW_M_CONTROL or U2HHIGH_M_CONTROL;
--USER2HWTI_M_FULL <= USER2HWTIH_M_FULL or USER2HWTIL_M_FULL;
--U2HLOW_M_FULL <= USER2HWTIL_M_FULL;
--U2HHIGH_M_FULL <= USER2HWTIH_M_FULL;
--HWTI2USER_S_READ <= H2ULOW_S_READ or H2UHIGH_S_READ;
--H2ULOW_S_DATA <= HWTI2USERL_S_DATA;
--H2ULOW_S_CONTROL <= HWTI2USERL_S_CONTROL;
--H2ULOW_S_EXISTS <= HWTI2USERL_S_EXISTS;
--H2UHIGH_S_DATA <= HWTI2USERH_S_DATA;
--H2UHIGH_S_CONTROL <= HWTI2USERH_S_CONTROL;
--H2UHIGH_S_EXISTS <= HWTI2USERH_S_EXISTS;
--USER2HWTIL_S_READ <= USER2HWTI_S_READ;
--USER2HWTIH_S_READ <= USER2HWTI_S_READ;
--USER2HWTI_S_DATA <= USER2HWTIH_S_DATA & USER2HWTIL_S_DATA;
--USER2HWTI_S_CONTROL <= USER2HWTIH_S_CONTROL or USER2HWTIL_S_CONTROL;
--USER2HWTI_S_EXISTS <= USER2HWTIH_S_EXISTS and USER2HWTIL_S_EXISTS;
--HWTI2USERH_M_WRITE <= HWTI2USER_M_WRITE;
--HWTI2USERL_M_WRITE <= HWTI2USER_M_WRITE;
--HWTI2USERH_M_DATA <= HWTI2USER_M_DATA(0 to 31);
--HWTI2USERL_M_DATA <= HWTI2USER_M_DATA(32 to 63);
--HWTI2USERH_M_CONTROL <= HWTI2USER_M_CONTROL;
--HWTI2USERL_M_CONTROL <= HWTI2USER_M_CONTROL;
--HWTI2USER_M_FULL <= HWTI2USERH_M_FULL or HWTI2USERL_M_FULL;
--HWTI2USER_S_READ <= FSL_S_READ;
--FSL_S_DATA <= HWTI2USER_S_DATA;
--FSL_S_CONTROL <= HWTI2USER_S_CONTROL;
--FSL_S_EXISTS <= HWTI2USER_S_EXISTS;
--USER2HWTI_M_WRITE <= FSL_M_WRITE;
--USER2HWTI_M_DATA <= FSL_M_DATA;
--USER2HWTI_M_CONTROL <= FSL_M_CONTROL;
--FSL_M_FULL <= USER2HWTI_M_FULL;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_SLAVE_CE-1) <= iBus2IP_RdCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_SLAVE_CE-1);
uBus2IP_RdCE(USER_NUM_SLAVE_CE to USER_NUM_CE-1) <= iBus2IP_RdCE(USER_MASTER_CE_INDEX to USER_MASTER_CE_INDEX+USER_NUM_MASTER_CE-1);
uBus2IP_WrCE(0 to USER_NUM_SLAVE_CE-1) <= iBus2IP_WrCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_SLAVE_CE-1);
uBus2IP_WrCE(USER_NUM_SLAVE_CE to USER_NUM_CE-1) <= iBus2IP_WrCE(USER_MASTER_CE_INDEX to USER_MASTER_CE_INDEX+USER_NUM_MASTER_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
| bsd-3-clause |
jevinskie/aes-over-pcie | source/state_filter_out_p.vhd | 1 | 1761 | -- File name: state_filter_out_p.vhd
-- Created: 2009-04-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: parallel state_filter_out
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity state_filter_out_p is
port (
current_state : in state_type;
sub_bytes_out : in state_type;
shift_rows_out : in state_type;
mix_columns_out : in state_type;
add_round_key_out : in state_type;
load_out : in byte;
subblock : in subblock_type;
i : in g_index;
next_state : out state_type
);
end entity state_filter_out_p;
architecture mux of state_filter_out_p is
begin
process(current_state, sub_bytes_out, shift_rows_out,
mix_columns_out, add_round_key_out, load_out, subblock, i)
begin
next_state <= current_state;
case subblock is
when identity =>
-- already selected
when sub_bytes =>
next_state <= sub_bytes_out;
when shift_rows =>
next_state <= shift_rows_out;
when mix_columns =>
next_state <= mix_columns_out;
when add_round_key =>
next_state <= add_round_key_out;
when load_pt =>
for x in index loop
for y in index loop
if (x + y * 4 = i) then
next_state(x, y) <= load_out;
end if;
end loop;
end loop;
when store_ct =>
-- already selected
when others =>
-- already selected
end case;
end process;
end architecture mux;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_scheduler_v1_00_a/devl/bfmsim/simulation/behavioral/bfm_memory_wrapper.vhd | 4 | 6409 | -------------------------------------------------------------------------------
-- bfm_memory_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_slave_bfm_v1_00_a;
use plbv46_slave_bfm_v1_00_a.all;
entity bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1)
);
end bfm_memory_wrapper;
architecture STRUCTURE of bfm_memory_wrapper is
component plbv46_slave_bfm is
generic (
PLB_SLAVE_SIZE : std_logic_vector(0 to 1);
PLB_SLAVE_NUM : std_logic_vector(0 to 3);
PLB_SLAVE_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_1 : std_logic_vector(0 to 31);
C_SPLB_DWIDTH : integer;
C_SPLB_NUM_MASTERS : integer;
C_SPLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1))
);
end component;
begin
bfm_memory : plbv46_slave_bfm
generic map (
PLB_SLAVE_SIZE => B"10",
PLB_SLAVE_NUM => B"0000",
PLB_SLAVE_ADDR_LO_0 => X"10000000",
PLB_SLAVE_ADDR_HI_0 => X"1000ffff",
PLB_SLAVE_ADDR_LO_1 => X"20000000",
PLB_SLAVE_ADDR_HI_1 => X"2000ffff",
C_SPLB_DWIDTH => 128,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_ssize => Sl_ssize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ
);
end architecture STRUCTURE;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/join_4.vhd | 2 | 17135 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: join_4.c
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- hthread_create( &data->thread, NULL, data->function, NULL );
when STATE_3 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, NULL );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
--retVal = _read_thread_status( data->thread );
when STATE_12 =>
--Prepare cmd to send to Thread Manager
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= x"60000A00" and ( reg7(2 to 31) & "00" );
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
--retVal = retVal & 0x00000010;
when STATE_13 =>
retVal_next <= intrfc2thrd_value and x"00000010";
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_acc_idea_v1_00_a/hdl/vhdl/Vector_3_par_user_logic_hwtul.vhd | 2 | 17358 | --accm
-- ************************************
-- Automatically Generated FSM
-- vector_chan
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity vector_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32;
OPCODE_BITS : integer := 6;
FUNC_BITS : integer := 6
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity vector_chan;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of vector_chan is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
fetch,
get_instr,
read_size,
read_index,
decode,
defunc,
halt,
addv_for_loop,
extra1,
addv_ALU,
addv_write_back,
mulv_for_loop,
extra2,
mulv_ALU,
mulv_write_back,
redv_for_loop,
extra3,
redv_ALU,
redv_write_back
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal in_Vector_A_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_B_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_C_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal swapped, swapped_next : std_logic;
signal i, i_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal n, n_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal n_new, n_new_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal instruction, instruction_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal index, index_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal ret, ret_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataA1, dataA1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataA2, dataA2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB1, dataB1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB2, dataB2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC1, dataC1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC2, dataC2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataMUL, dataMUL_next : std_logic_vector(0 to G_DATA_WIDTH + G_DATA_WIDTH - 1);
signal op, op_next : std_logic_vector(0 to 5);
signal rs, rs_next : std_logic_vector(0 to 4);
signal rt, rt_next : std_logic_vector(0 to 4);
signal rd, rd_next : std_logic_vector(0 to 4);
signal sh, sh_next : std_logic_vector(0 to 4);
signal fn, fn_next : std_logic_vector(0 to 5);
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OP_R : std_logic_vector(0 to OPCODE_BITS-1) := "000000";
constant FN_NOP : std_logic_vector(0 to FUNC_BITS-1) := "000000"; -- 0/00H
constant FN_ADDV : std_logic_vector(0 to FUNC_BITS-1) := "110000"; -- 0/30H
constant FN_MULV : std_logic_vector(0 to FUNC_BITS-1) := "110001"; -- 0/31
constant FN_REDV : std_logic_vector(0 to FUNC_BITS-1) := "110010"; -- 0/32
--constant OP_NOP : std_logic_vector(0 to OPCODE_BITS-1) := x"0";
--constant OP_ADD : std_logic_vector(0 to OPCODE_BITS-1) := x"1";
--constant OP_SUB : std_logic_vector(0 to OPCODE_BITS-1) := x"2";
--constant OP_ADDi : std_logic_vector(0 to OPCODE_BITS-1) := x"3";
--constant OP_SUBi : std_logic_vector(0 to OPCODE_BITS-1) := x"4";
--constant OP_ADDV : std_logic_vector(0 to OPCODE_BITS-1) := x"5";
--constant OP_SUBV : std_logic_vector(0 to OPCODE_BITS-1) := x"6";
--constant OP_ADDVS : std_logic_vector(0 to OPCODE_BITS-1) := x"7";
--constant OP_SUBVS : std_logic_vector(0 to OPCODE_BITS-1) := x"8";
--constant OP_SNEV : std_logic_vector(0 to OPCODE_BITS-1) := x"9";
--constant OP_SNEVS : std_logic_vector(0 to OPCODE_BITS-1) := x"A";
--constant OP_SLTV : std_logic_vector(0 to OPCODE_BITS-1) := x"B";
--constant OP_SLTVS : std_logic_vector(0 to OPCODE_BITS-1) := x"C";
--constant OP_CVM : std_logic_vector(0 to OPCODE_BITS-1) := x"D";
--constant OP_SVLR : std_logic_vector(0 to OPCODE_BITS-1) := x"E";
--constant OP_SVMR : std_logic_vector(0 to OPCODE_BITS-1) := x"F";
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
Vector_A_addr0 <= in_Vector_A_addr0(2 to 31) & "00";
Vector_B_addr0 <= in_Vector_B_addr0(2 to 31) & "00";
Vector_C_addr0 <= in_Vector_C_addr0(2 to 31) & "00";
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
swapped_next,
i_next,
n_next,
n_new_next,
instruction_next,
index_next,
ret_next,
dataA1_next,
dataA2_next,
dataB1_next,
dataB2_next,
dataC1_next,
dataC2_next,
dataMUL_next,
op_next,
rs_next,
rt_next,
rd_next,
sh_next,
fn_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
swapped <= '0';
i <= (others => '0');
n <= (others => '0');
n_new <= (others => '0');
instruction <= (others => '0');
index <= (others => '0');
ret <= (others => '0');
dataA1 <= (others => '0');
dataA2 <= (others => '0');
dataB1 <= (others => '0');
dataB2 <= (others => '0');
dataC1 <= (others => '0');
dataC2 <= (others => '0');
dataMUL <= (others => '0');
op <= (others => '0');
rs <= (others => '0');
rt <= (others => '0');
rd <= (others => '0');
sh <= (others => '0');
fn <= (others => '0');
current_state <= reset;
else
-- Transition to next state
swapped <= swapped_next;
i <= i_next;
n <= n_next;
n_new <= n_new_next;
instruction <= instruction_next;
index <= index_next;
ret <= ret_next;
dataA1 <= dataA1_next;
dataA2 <= dataA2_next;
dataB1 <= dataB1_next;
dataB2 <= dataB2_next;
dataC1 <= dataC1_next;
dataC2 <= dataC2_next;
dataMUL <= dataMUL_next;
op <= op_next;
rs <= rs_next;
rt <= rt_next;
rd <= rd_next;
sh <= sh_next;
fn <= fn_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
Vector_A_dOUT0,
Vector_B_dOUT0,
Vector_C_dOUT0,
chan1_channelDataOut, chan1_full, chan1_exists,
swapped,
i,
n,
n_new,
instruction,
index,
ret,
dataA1,
dataA2,
dataB1,
dataB2,
dataC1,
dataC2,
dataMUL,
op,
rs,
rt,
rd,
sh,
fn,
current_state) is
begin
-- Default signal assignments
swapped_next <= swapped;
i_next <= i;
n_next <= n;
n_new_next <= n_new;
instruction_next <= instruction;
index_next <= index;
ret_next <= ret;
dataA1_next <= dataA1;
dataA2_next <= dataA2;
dataB1_next <= dataB1;
dataB2_next <= dataB2;
dataC1_next <= dataC1;
dataC2_next <= dataC2;
dataMUL_next <= dataMUL;
op_next <= op;
rs_next <= rs;
rt_next <= rt;
rd_next <= rd;
sh_next <= sh;
fn_next <= fn;
in_Vector_A_addr0 <= (others => '0');
Vector_A_dIN0 <= (others => '0');
Vector_A_rENA0 <= '0';
Vector_A_wENA0 <= (others => '0');
in_Vector_B_addr0 <= (others => '0');
Vector_B_dIN0 <= (others => '0');
Vector_B_rENA0 <= '0';
Vector_B_wENA0 <= (others => '0');
in_Vector_C_addr0 <= (others => '0');
Vector_C_dIN0 <= (others => '0');
Vector_C_rENA0 <= '0';
Vector_C_wENA0 <= (others => '0');
chan1_channelDataIn <= (others => '0');
chan1_channelRead <= '0';
chan1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when addv_ALU =>
dataC1_next <= dataA1 + dataB1;
next_state <= addv_write_back;
when addv_for_loop =>
if ( i >= n ) then
next_state <= halt;
elsif ( i < n ) then
in_Vector_A_addr0 <= i;
Vector_A_rENA0 <= '1';
in_Vector_B_addr0 <= i;
Vector_B_rENA0 <= '1';
next_state <= extra1;
end if;
when addv_write_back =>
i_next <= i + 1;
in_Vector_C_addr0 <= i;
Vector_C_dIN0 <= dataC1;
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
next_state <= addv_for_loop;
when decode =>
if ( op = OP_R ) then
next_state <= defunc;
end if;
when defunc =>
if ( fn = FN_NOP ) then
next_state <= halt;
elsif ( fn = FN_ADDV ) then
i_next <= index;
next_state <= addv_for_loop;
elsif ( fn = FN_MULV ) then
i_next <= index;
next_state <= mulv_for_loop;
elsif ( fn = FN_REDV ) then
i_next <= index;
next_state <= redv_for_loop;
end if;
when extra1 =>
dataB1_next <= Vector_B_dOUT0;
dataA1_next <= Vector_A_dOUT0;
next_state <= addv_ALU;
when extra2 =>
dataB1_next <= Vector_B_dOUT0;
dataA1_next <= Vector_A_dOUT0;
next_state <= mulv_ALU;
when extra3 =>
dataB1_next <= Vector_B_dOUT0;
dataA1_next <= Vector_A_dOUT0;
next_state <= redv_ALU;
when fetch =>
if chan1_exists = '0' then
next_state <= fetch;
elsif chan1_exists /= '0' then
instruction_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= get_instr;
end if;
when get_instr =>
ret_next <= (others => '0');
fn_next <= instruction(26 to 31);
sh_next <= instruction(21 to 25);
rt_next <= instruction(16 to 20);
rs_next <= instruction(11 to 15);
rd_next <= instruction(6 to 10);
op_next <= instruction(0 to 5);
next_state <= read_size;
when halt =>
if chan1_full /= '0' then
next_state <= halt;
elsif chan1_full = '0' then
chan1_channelDataIn <= ret;
chan1_channelWrite <= '1';
next_state <= fetch;
end if;
when mulv_ALU =>
dataMUL_next <= dataA1 * dataB1;
next_state <= mulv_write_back;
when mulv_for_loop =>
if ( i >= n ) then
next_state <= halt;
elsif ( i < n ) then
in_Vector_A_addr0 <= i;
Vector_A_rENA0 <= '1';
in_Vector_B_addr0 <= i;
Vector_B_rENA0 <= '1';
next_state <= extra2;
end if;
when mulv_write_back =>
i_next <= i + 1;
in_Vector_C_addr0 <= i;
Vector_C_dIN0 <= dataMUL(32 to 63);
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
next_state <= mulv_for_loop;
when read_index =>
if chan1_exists = '0' then
next_state <= read_index;
elsif chan1_exists /= '0' then
index_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= decode;
end if;
when read_size =>
if chan1_exists = '0' then
next_state <= read_size;
elsif chan1_exists /= '0' then
n_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= read_index;
end if;
when redv_ALU =>
dataMUL_next <= dataA1 * dataB1;
next_state <= redv_write_back;
when redv_for_loop =>
if ( i >= n ) then
next_state <= halt;
elsif ( i < n ) then
in_Vector_A_addr0 <= i;
Vector_A_rENA0 <= '1';
in_Vector_B_addr0 <= i;
Vector_B_rENA0 <= '1';
next_state <= extra3;
end if;
when redv_write_back =>
i_next <= i + 1;
ret_next <= ret + dataMUL(32 to 63);
next_state <= redv_for_loop;
when reset =>
next_state <= fetch;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_acc_crc_v1_00_a/hdl/vhdl/user_logic_hwtul.vhd | 3 | 6536 | -- ************************************
-- Automatically Generated FSM
-- crc
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity crc is
generic(
G_INPUT_WIDTH : integer := 32;
G_ADDR_WIDTH : integer := 32;
G_DIVISOR_WIDTH : integer := 4;
divisor : std_logic_vector(0 to 3) := "1011"
);
port
(
array_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
array_dIN0 : out std_logic_vector(0 to (G_INPUT_WIDTH - 1));
array_dOUT0 : in std_logic_vector(0 to (G_INPUT_WIDTH - 1));
array_rENA0 : out std_logic;
array_wENA0 : out std_logic_vector(0 to (G_INPUT_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (G_INPUT_WIDTH - 1));
chan1_channelDataOut : in std_logic_vector(0 to (G_INPUT_WIDTH - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity crc;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of crc is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
idle,
read_data,
extra1,
do_crc
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal i, i_next : std_logic_vector(0 to 7);
signal j, j_next : std_logic_vector(0 to 31);
signal result, result_next : std_logic_vector(0 to G_INPUT_WIDTH - 1);
signal size, size_next : std_logic_vector(0 to G_INPUT_WIDTH - 1);
signal in_array_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
array_addr0 <= in_array_addr0(2 to 31) & "00"; --The external memory is organized in this way.
-- ************************
-- Permanent Connections
-- ************************
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
i_next,
j_next,
result_next,
size_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
i <= (others => '0');
j <= (others => '0');
result <= (others => '0');
size <= (others => '0');
current_state <= reset;
else
-- Transition to next state
i <= i_next;
j <= j_next;
result <= result_next;
size <= size_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
array_dOUT0,
chan1_channelDataOut, chan1_full, chan1_exists,
i,
j,
result,
size,
current_state) is
begin
-- Default signal assignments
i_next <= i;
j_next <= j;
result_next <= result;
size_next <= size;
in_array_addr0 <= (others => '0');
array_dIN0 <= (others => '0');
array_rENA0 <= '0';
array_wENA0 <= (others => '0');
chan1_channelDataIn <= (others => '0');
chan1_channelRead <= '0';
chan1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when do_crc =>
if ( i < G_INPUT_WIDTH - G_DIVISOR_WIDTH + 1 ) and ( result(conv_integer(i)) = '0' ) then
i_next <= i + 1;
next_state <= do_crc;
elsif ( i < G_INPUT_WIDTH - G_DIVISOR_WIDTH + 1 ) then
result_next(conv_integer(i) to conv_integer(i) + ( G_DIVISOR_WIDTH - 1 )) <= result(conv_integer(i) to conv_integer(i) + ( G_DIVISOR_WIDTH - 1 )) xor divisor;
i_next <= i + 1;
next_state <= do_crc;
else
in_array_addr0 <= j;
array_dIN0 <= result;
array_wENA0 <= (others => '1');
array_rENA0 <= '1';
next_state <= read_data;
j_next <= j + 1;
end if;
when extra1 =>
i_next <= conv_std_logic_vector(0,8);
result_next <= array_dOUT0;
next_state <= do_crc;
when idle =>
if chan1_exists = '0' then
next_state <= idle;
elsif chan1_exists /= '0' then
j_next <= "00000000000000000" & chan1_channelDataOut(17 to 31);
size_next <= "00000000000000000" & chan1_channelDataOut(2 to 16);
chan1_channelRead <= '1';
next_state <= read_data;
end if;
when read_data =>
if ( j < size ) then
in_array_addr0 <= j;
array_rENA0 <= '1';
next_state <= extra1;
elsif chan1_full /= '0' then
next_state <= read_data;
elsif chan1_full = '0' then
chan1_channelDataIn <= (others => '0');
chan1_channelWrite <= '1';
next_state <= idle;
end if;
when reset =>
next_state <= idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_two_v1_00_a/hdl/vhdl/hw_acc_two.vhd | 2 | 7966 | ------------------------------------------------------------------------------
-- add_sub_core - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: add_sub_core
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Thu Aug 9 10:06:10 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_two is
port
(
Tintrfc2thrd_value : out std_logic_vector(0 to 31);
Tintrfc2thrd_function : out std_logic_vector(0 to 15);
Tintrfc2thrd_goWait : out std_logic;
Tthrd2intrfc_address : out std_logic_vector(0 to 31);
Tthrd2intrfc_value : out std_logic_vector(0 to 31);
Tthrd2intrfc_function : out std_logic_vector(0 to 15);
Tthrd2intrfc_opcode : out std_logic_vector(0 to 5);
Ttimer : out std_logic_vector( 0 to 31);
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
FSL1_M_Write : out std_logic;
FSL1_M_Data : out std_logic_vector(0 to 31);
FSL1_M_Full : in std_logic;
FSL2_M_Write : out std_logic;
FSL2_M_Data : out std_logic_vector(0 to 31);
FSL2_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
end hw_acc_two;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_two is
component user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic ;
full : in std_logic ;
Ttimer : out std_logic_vector( 0 to 31)
);
end component user_logic_hwtul;
signal intrfc2thrd : std_logic_vector(0 to 63);
signal thrd2intrfc : std_logic_vector( 0 to 95);
signal rd : std_logic;
signal wr : std_logic;
signal exist : std_logic;
signal full : std_logic;
signal timer : std_logic_vector( 0 to 31) ;
-- Architecture Section
begin
Tintrfc2thrd_value <= intrfc2thrd(0 to 31) ;
Tintrfc2thrd_function <= intrfc2thrd (32 to 47);
Tintrfc2thrd_goWait <= exist ;
Tthrd2intrfc_address <= thrd2intrfc (32 to 63);
Tthrd2intrfc_value <= thrd2intrfc (0 to 31) ;
Tthrd2intrfc_function <= thrd2intrfc (64 to 79);
Tthrd2intrfc_opcode <= thrd2intrfc (80 to 85);
Ttimer <= timer;
intrfc2thrd <= FSL0_S_Data & FSL1_S_Data;
FSL0_M_Data <= thrd2intrfc(0 to 31);
FSL1_M_Data <= thrd2intrfc(32 to 63);
FSL2_M_Data <= thrd2intrfc(64 to 95);
--=======================================================
full <= FSL0_M_Full or FSL1_M_Full or FSL2_M_Full;
exist <= FSL0_S_Exists and FSL1_S_Exists ;
--=======================================================
FSL0_S_Read <= rd;
FSL1_S_Read <= rd;
FSL0_M_Write <= wr;
FSL1_M_Write <= wr;
FSL2_M_Write <= wr;
USER_LOGIC_HWTUL_I : user_logic_hwtul
port map
(
clock => FSL_Clk,
intrfc2thrd => intrfc2thrd,
thrd2intrfc => thrd2intrfc,
rd => rd,
wr => wr,
exist => exist,
full => full,
Ttimer => timer
);
end architecture implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_huffmanEncode.vhd | 2 | 21738 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Quicksort
-- Thread implements the quicksort algorithm
-- Passed in argument is a pointer to following struct
-- struct sortData {
-- int * startData; //pointer to start of array
-- int * endData; //pointer to end of array
-- int cacheOption // 1 operate on data where it is, 0 copy into HWTI first
-- There is not return argument, the HWT just sorts the data.
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
READ_ARGS_1,
READ_ARGS_2,
READ_ARGS_3,
READ_ARGS_4,
READ_ARGS_5,
FORLOOP_1,
FORLOOP_2,
FORLOOP_3,
FORLOOP_4,
WHILE_A_1,
WHILE_A_2,
WHILE_A_3,
WHILE_B_1,
WHILE_B_2,
WHILE_B_3,
WHILE_B_4,
WHILE_B_5,
WHILE_B_6,
FLUSH_1,
FLUSH_2,
EXIT_THREAD,
EXIT_THREAD_1,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant MAX_SIZE : std_logic_vector(0 to 31) := x"00000400";
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next : state_machine := FUNCTION_RESET;
signal arg, arg_next : std_logic_vector(0 to 31);
signal bufer, buffer_next : std_logic_vector(0 to 31);
signal bufLen, bufLen_next : std_logic_vector(0 to 31);
signal outputIndex, outputIndex_next : std_logic_vector(0 to 31);
signal index, index_next : std_logic_vector(0 to 31);
signal len, len_next : std_logic_vector(0 to 31);
signal pos, pos_next : std_logic_vector(0 to 31);
signal inputData, inputData_next : std_logic_vector(0 to 31);
signal outputData, outputData_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
arg <= arg_next;
bufer <= buffer_next;
bufLen <= bufLen_next;
outputIndex <= outputIndex_next;
index <= index_next;
len <= len_next;
pos <= pos_next;
inputData <= inputData_next;
outputData <= outputData_next;
count <= count_next;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (current_state) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
next_state <= current_state;
return_state_next <= return_state;
arg_next <= arg;
buffer_next <= bufer;
bufLen_next <= bufLen;
outputIndex_next <= outputIndex;
index_next <= index;
len_next <= len;
pos_next <= pos;
inputData_next <= inputData;
outputData_next <= outputData;
count_next <= count;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
arg_next <= Z32;
buffer_next <= Z32;
bufLen_next <= Z32;
outputIndex_next <= Z32;
index_next <= Z32;
len_next <= Z32;
pos_next <= Z32;
inputData_next <= Z32;
outputData_next <= Z32;
count_next <= Z32;
when FUNCTION_START =>
-- read the passed in argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_address <= Z32;
return_state_next <= READ_ARGS_1;
next_state <= WAIT_STATE;
-- int Code[MAX_SIZE]
when READ_ARGS_1 =>
arg_next <= toUser_value;
-- Declare an array of MAX_SIZE on the stack
thrd2intrfc_opcode <= OPCODE_DECLARE;
thrd2intrfc_value <= MAX_SIZE;
return_state_next <= READ_ARGS_2;
next_state <= WAIT_STATE;
-- struct HuffmanStructure * huffman = (struct HuffmanStructure *)arg;
when READ_ARGS_2 =>
-- Read value of inputData pointer
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
return_state_next <= READ_ARGS_3;
next_state <= WAIT_STATE;
when READ_ARGS_3 =>
inputData_next <= toUser_value;
-- Read value of outputData pointer
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
return_state_next <= READ_ARGS_4;
next_state <= WAIT_STATE;
when READ_ARGS_4 =>
outputData_next <= toUser_value;
-- Read value of count
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
return_state_next <= READ_ARGS_5;
next_state <= WAIT_STATE;
when READ_ARGS_5 =>
count_next <= toUser_value;
next_state <= FORLOOP_1;
-- for ( index = 0; index < huffman->count; index++ );
when FORLOOP_1 =>
-- index was initialized in the start state
-- check to see if index is less than count
if ( index < count ) then
next_state <= FORLOOP_2;
else
next_state <= FLUSH_1;
end if;
-- Len = 0;
-- Pos = huffman->inputData[Index];
when FORLOOP_2 =>
-- len was initialized in the start state
-- read the character to encode
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= inputData + (index(2 to 31) & "00");
return_state_next <= FORLOOP_3;
next_state <= WAIT_STATE;
when FORLOOP_3 =>
pos_next <= toUser_value;
next_state <= WHILE_A_1;
-- while ((pos < MAX_SIZE) && (huffman->code.Parent[Pos] >= 0 ))
when WHILE_A_1 =>
-- check to see if pos < MAX_SIZE
if ( pos < MAX_SIZE ) then
-- read the value of huffman->code.Parent[pos]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000100C" + (pos(2 to 31) & "00");
return_state_next <= WHILE_A_2;
next_state <= WAIT_STATE;
else
next_state <= WHILE_B_1;
end if;
-- code[len++] = huffman->code.bit[pos]
-- pos = huffman->code.parent[pos]
when WHILE_A_2 =>
-- check to see of huffman->code.Parent[pos] >= 0
-- can check this by inspecting the bit 0
case toUser_value(0) is
when '0' =>
-- this is a positive number or zero
pos_next <= toUser_value;
-- read the value of huffman->code.bit[pos]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000400C" + (pos(2 to 31) & "00");
return_state_next <= WHILE_A_3;
next_state <= WAIT_STATE;
when others =>
-- this is a negative number
next_state <= WHILE_B_1;
end case;
when WHILE_A_3 =>
-- set code[len] to the value of huffman->code.bit[pos]
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_value <= toUser_value;
thrd2intrfc_address <= len;
-- increment len
len_next <= len + x"00000001";
return_state_next <= WHILE_A_1;
next_state <= WAIT_STATE;
-- end of while loop
-- while( len > 0 )
when WHILE_B_1 =>
case len is
when x"00000000" =>
-- len is = 0
next_state <= FORLOOP_4;
when others =>
-- len is > 0
-- decrement len in preparation for next step
len_next <= len - x"00000001";
next_state <= WHILE_B_2;
end case;
-- Buffer = (Buffer << 1) | Code[--Len];
when WHILE_B_2 =>
-- read the value of code[len]
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_value <= toUser_value;
thrd2intrfc_address <= len;
return_state_next <= WHILE_B_3;
next_state <= WAIT_STATE;
-- BufLen++;
when WHILE_B_3 =>
-- set the value of buffer
--buffer_next <= (bufer(1 to 31) & '0') | toUser_value;
buffer_next <= bufer(1 to 31) & toUser_value(31);
-- increment buflen
buflen_next <= bufLen + x"00000001";
next_state <= WHILE_B_4;
-- if ( BufLen == 32 )
-- huffman->outputData[outputIndex] = Buffer
when WHILE_B_4 =>
-- check to see if BufLen == 32, do this by checking bit 26
case bufLen(26) is
when '0' =>
-- bufLen is less than 32
next_state <= WHILE_B_1;
when others =>
-- bufLen is 32
-- store the value of outputData[outputIndex]
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_value <= bufer;
thrd2intrfc_address <= outputData + (outputIndex(2 to 31) & "00");
return_state_next <= WHILE_B_5;
next_state <= WAIT_STATE;
end case;
-- outputIndex++;
-- Buffer = 0;
-- BufLen = 0;
when WHILE_B_5 =>
outputIndex_next <= outputIndex + x"00000001";
buffer_next <= Z32;
bufLen_next <= Z32;
next_state <= WHILE_B_1;
-- end if statement
-- end while loop
when FORLOOP_4 =>
-- increment index
index_next <= index + x"00000001";
next_state <= FORLOOP_1;
-- end for loop
-- if ( bufLen != 0 )
-- Buffer = Buffer << (32 - BufLen)
when FLUSH_1 =>
-- check to see if bufLen is equal to 0, only have to check last 6 bits
-- if it is not 0, check the value to know how much to shift buffer
case bufLen(26 to 31) is
when "000000" =>
next_state <= EXIT_THREAD;
when "000001" =>
buffer_next <= bufer(31) & Z32(0 to 30);
next_state <= FLUSH_2;
when "000010" =>
buffer_next <= bufer(30 to 31) & Z32(0 to 29);
next_state <= FLUSH_2;
when "000011" =>
buffer_next <= bufer(29 to 31) & Z32(0 to 28);
next_state <= FLUSH_2;
when "000100" =>
buffer_next <= bufer(28 to 31) & Z32(0 to 27);
next_state <= FLUSH_2;
when "000101" =>
buffer_next <= bufer(27 to 31) & Z32(0 to 26);
next_state <= FLUSH_2;
when "000110" =>
buffer_next <= bufer(26 to 31) & Z32(0 to 25);
next_state <= FLUSH_2;
when "000111" =>
buffer_next <= bufer(25 to 31) & Z32(0 to 24);
next_state <= FLUSH_2;
when "001000" =>
buffer_next <= bufer(24 to 31) & Z32(0 to 23);
next_state <= FLUSH_2;
when "001001" =>
buffer_next <= bufer(23 to 31) & Z32(0 to 22);
next_state <= FLUSH_2;
when "001010" =>
buffer_next <= bufer(22 to 31) & Z32(0 to 21);
next_state <= FLUSH_2;
when "001011" =>
buffer_next <= bufer(21 to 31) & Z32(0 to 20);
next_state <= FLUSH_2;
when "001100" =>
buffer_next <= bufer(20 to 31) & Z32(0 to 19);
next_state <= FLUSH_2;
when "001101" =>
buffer_next <= bufer(19 to 31) & Z32(0 to 18);
next_state <= FLUSH_2;
when "001110" =>
buffer_next <= bufer(18 to 31) & Z32(0 to 17);
next_state <= FLUSH_2;
when "001111" =>
buffer_next <= bufer(17 to 31) & Z32(0 to 16);
next_state <= FLUSH_2;
when "010000" =>
buffer_next <= bufer(16 to 31) & Z32(0 to 15);
next_state <= FLUSH_2;
when "010001" =>
buffer_next <= bufer(15 to 31) & Z32(0 to 14);
next_state <= FLUSH_2;
when "010010" =>
buffer_next <= bufer(14 to 31) & Z32(0 to 13);
next_state <= FLUSH_2;
when "010011" =>
buffer_next <= bufer(13 to 31) & Z32(0 to 12);
next_state <= FLUSH_2;
when "010100" =>
buffer_next <= bufer(12 to 31) & Z32(0 to 11);
next_state <= FLUSH_2;
when "010101" =>
buffer_next <= bufer(11 to 31) & Z32(0 to 10);
next_state <= FLUSH_2;
when "010110" =>
buffer_next <= bufer(10 to 31) & Z32(0 to 9);
next_state <= FLUSH_2;
when "010111" =>
buffer_next <= bufer(9 to 31) & Z32(0 to 8);
next_state <= FLUSH_2;
when "011000" =>
buffer_next <= bufer(8 to 31) & Z32(0 to 7);
next_state <= FLUSH_2;
when "011001" =>
buffer_next <= bufer(7 to 31) & Z32(0 to 6);
next_state <= FLUSH_2;
when "011010" =>
buffer_next <= bufer(6 to 31) & Z32(0 to 5);
next_state <= FLUSH_2;
when "011011" =>
buffer_next <= bufer(5 to 31) & Z32(0 to 4);
next_state <= FLUSH_2;
when "011100" =>
buffer_next <= bufer(4 to 31) & Z32(0 to 3);
next_state <= FLUSH_2;
when "011101" =>
buffer_next <= bufer(3 to 31) & Z32(0 to 2);
next_state <= FLUSH_2;
when "011110" =>
buffer_next <= bufer(2 to 31) & Z32(0 to 1);
next_state <= FLUSH_2;
when "011111" =>
buffer_next <= bufer(1 to 31) & Z32(0);
next_state <= FLUSH_2;
when others =>
-- should never get to this state
next_state <= EXIT_THREAD;
end case;
-- huffman->outputData[outputIndex] = Buffer
when FLUSH_2 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_value <= bufer;
thrd2intrfc_address <= outputData + (outputIndex(2 to 31) & "00");
return_state_next <= EXIT_THREAD;
next_state <= WAIT_STATE;
-- end if statement
when EXIT_THREAD =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
return_state_next <= EXIT_THREAD_1;
next_state <= WAIT_STATE;
when EXIT_THREAD_1 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
next_state <= WAIT_STATE;
when WAIT_STATE =>
case toUser_goWait is
when '1' => --Here because HWTUL chose to be here for one clock cycle
next_state <= return_state;
when OTHERS => --ie '0', Here because HWTI is telling us to wait
next_state <= return_state;
end case;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/mux_onehot.vhd | 2 | 14599 | -------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/mutex_store.vhd | 11 | 7532 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity mutex_store is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
miaddr : in std_logic_vector(0 to C_MWIDTH-1);
miena : in std_logic;
miwea : in std_logic;
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
mikind : in std_logic_vector(0 to 1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
sysrst : in std_logic;
rstdone : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mokind : out std_logic_vector(0 to 1);
mocount : out std_logic_vector(0 to C_CWIDTH-1)
);
end mutex_store;
architecture behavioral of mutex_store is
-- Calculate the number of mutexes to use
constant MUTEXES : integer := pow2( C_MWIDTH );
-- Constant for the last position to be reset
constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1');
-- Calculate the beginning and ending bit positions for data
constant OWN_SRT : integer := 0;
constant OWN_END : integer := OWN_SRT + C_TWIDTH-1;
constant NXT_SRT : integer := OWN_END+1;
constant NXT_END : integer := NXT_SRT + C_TWIDTH-1;
constant LST_SRT : integer := NXT_END+1;
constant LST_END : integer := LST_SRT + C_TWIDTH-1;
constant KND_SRT : integer := LST_END+1;
constant KND_END : integer := KND_SRT + 1;
constant CNT_SRT : integer := KND_END + 1;
constant CNT_END : integer := CNT_SRT + C_CWIDTH-1;
-- Declare a storage area for the mutex data
type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1);
-- Declare signals for the mutex storage area
signal store : mstore;
signal mena : std_logic;
signal mwea : std_logic;
signal maddr : std_logic_vector(0 to C_MWIDTH-1);
signal minput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1);
signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1);
-- Type for the reset state machine
type rststate is
(
IDLE,
RESET
);
-- Declare signals for the reset
signal rena : std_logic;
signal rwea : std_logic;
signal rst_cs : rststate;
signal raddr : std_logic_vector(0 to C_MWIDTH-1);
signal raddrn : std_logic_vector(0 to C_MWIDTH-1);
signal rowner : std_logic_vector(0 to C_TWIDTH-1);
signal rnext : std_logic_vector(0 to C_TWIDTH-1);
signal rlast : std_logic_vector(0 to C_TWIDTH-1);
signal rkind : std_logic_vector(0 to 1);
signal rcount : std_logic_vector(0 to C_CWIDTH-1);
begin
moowner <= moutput(OWN_SRT to OWN_END);
monext <= moutput(NXT_SRT to NXT_END);
molast <= moutput(LST_SRT to LST_END);
mokind <= moutput(KND_SRT to KND_END);
mocount <= moutput(CNT_SRT to CNT_END);
mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount,
miena,miwea,miaddr,miowner,milast,mikind,micount) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
mena <= rena;
mwea <= rwea;
maddr <= raddr;
minput <= rowner & rnext & rlast & rkind & rcount;
else
mena <= miena;
mwea <= miwea;
maddr <= miaddr;
minput <= miowner & minext & milast & mikind & micount;
end if;
end if;
end process mutex_mux;
mutex_reset_controller : process(clk,rst) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
rst_cs <= RESET;
raddr <= raddrn;
else
rst_cs <= IDLE;
end if;
end if;
end process mutex_reset_controller;
mutex_reset_logic : process(rst_cs,raddr) is
begin
rena <= '1';
rwea <= '1';
rstdone <= '1';
rowner <= (others => '0');
rnext <= (others => '0');
rlast <= (others => '0');
rkind <= (others => '0');
rcount <= (others => '0');
case rst_cs is
when IDLE =>
raddrn <= (others => '0');
when RESET =>
if( raddr = RST_END ) then
raddrn <= raddr;
else
rstdone <= '0';
raddrn <= raddr + 1;
end if;
end case;
end process mutex_reset_logic;
mutex_store_controller : process (clk) is
begin
if( rising_edge(clk) ) then
if( mena = '1' ) then
if( mwea = '1' ) then
store( conv_integer(maddr) ) <= minput;
end if;
moutput <= store( conv_integer(maddr) );
end if;
end if;
end process mutex_store_controller;
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/hwti_mblaze_6smp/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/master.vhd | 10 | 10243 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity master is
generic
(
C_BASEADDR : std_logic_vector := x"00000000";
C_HIGHADDR : std_logic_vector := x"FFFFFFFF";
C_SCHED_BASEADDR : std_logic_vector := x"00000000";
C_RESULT_BASEADDR : std_logic_vector := x"00000000";
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 6;
C_NUM_CE : integer := 4
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
-- Bus2IP_MstLastAck : in std_logic;
-- IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
-- IP2Bus_MstBE : out std_logic_vector(0 to C_DWIDTH/8-1);
-- IP2Bus_MstBurst : out std_logic;
-- IP2Bus_MstBusLock : out std_logic;
-- IP2Bus_MstRdReq : out std_logic;
-- IP2Bus_MstWrReq : out std_logic;
-- IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : in std_logic;
send_id : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : out std_logic;
saddr : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sena : out std_logic;
swea : out std_logic;
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end master;
architecture behavioral of master is
constant THR_BIT : integer := log2( C_NUM_THREADS );
type send_state is
(
IDLE,
SENDING,
FINISH
);
type queue_state is
(
IDLE,
DONE,
GETWAIT,
GETDONE
);
signal mst_cmplt : std_logic;
signal send_cs : send_state;
signal send_ns : send_state;
signal queue_cs : queue_state;
signal queue_ns : queue_state;
signal send_rdy : std_logic;
signal send_valid : std_logic;
signal send_validn : std_logic;
signal send_cur : std_logic_vector(0 to THR_BIT-1);
signal send_curn : std_logic_vector(0 to THR_BIT-1);
signal send_first : std_logic_vector(0 to THR_BIT-1);
signal send_firstn : std_logic_vector(0 to THR_BIT-1);
signal send_last : std_logic_vector(0 to THR_BIT-1);
signal send_lastn : std_logic_vector(0 to THR_BIT-1);
signal send_count : std_logic_vector(0 to THR_BIT-1);
signal send_countn : std_logic_vector(0 to THR_BIT-1);
begin
-- System reset only takes one clock cycle so were always "done"
system_resetdone <= '1';
queue_update : process(Bus2IP_Clk) is
begin
if( rising_edge(Bus2IP_Clk) ) then
if( Bus2IP_Reset = '1' or system_reset = '1' ) then
queue_cs <= IDLE;
send_count <= (others => '0');
send_first <= (others => '0');
send_last <= (others => '0');
send_cur <= (others => '0');
send_valid <= '0';
else
queue_cs <= queue_ns;
send_count <= send_countn;
send_first <= send_firstn;
send_last <= send_lastn;
send_cur <= send_curn;
send_valid <= send_validn;
end if;
end if;
end process queue_update;
queue_controller : process(Bus2IP_Clk,queue_cs, send_cur, send_last, send_first, send_count, send_ena, send_id, send_rdy, sinext) is
begin
sena <= '0';
swea <= '0';
saddr <= (others => '0');
sonext <= (others => '0');
queue_ns <= queue_cs;
send_curn <= send_cur;
send_lastn <= send_last;
send_firstn <= send_first;
send_countn <= send_count;
send_validn <= '0';
case queue_cs is
when IDLE =>
if( send_ena = '1' ) then
if( send_count = zero(THR_BIT) ) then
send_firstn <= send_id;
else
sena <= '1';
swea <= '1';
saddr <= send_last;
sonext <= send_id;
end if;
send_lastn <= send_id;
send_countn <= send_count+1;
send_ack <= '1';
queue_ns <= DONE;
elsif( send_rdy = '1' and send_count /= zero(THR_BIT) ) then
send_curn <= send_first;
send_validn <= '1';
sena <= '1';
saddr <= send_first;
queue_ns <= GETWAIT;
end if;
when DONE =>
send_ack <= '1';
if( send_ena = '0' ) then
queue_ns <= IDLE;
end if;
when GETWAIT => null;
queue_ns <= GETDONE;
when GETDONE =>
send_firstn <= sinext;
send_countn <= send_count-1;
queue_ns <= IDLE;
end case;
end process queue_controller;
send_update : process (Bus2IP_Clk,send_ns) is
begin
if( rising_edge(Bus2IP_Clk) ) then
if( Bus2IP_Reset = '1' or system_reset = '1' ) then
send_cs <= IDLE;
else
send_cs <= send_ns;
end if;
end if;
end process send_update;
send_controller : process (Bus2IP_Mst_CmdAck, Bus2IP_MstRd_src_rdy_n, send_cs,send_valid,send_cur) is
begin
send_ns <= send_cs;
send_rdy <= '0';
IP2Bus_Mst_Addr <= (others => '0');
IP2Bus_Mst_BE <= (others => '0');
IP2Bus_MstRd_Req <= '0';
case send_cs is
when IDLE =>
send_rdy <= '1';
if( send_valid = '1' ) then
send_ns <= SENDING;
end if;
when SENDING =>
-- Capture the Bus2IP_Mst_Cmplt value for later.
if (mst_cmplt = '0') then
mst_cmplt <= Bus2IP_Mst_Cmplt;
end if;
if (Bus2IP_Mst_CmdAck = '1') then
send_ns <= FINISH;
else
IP2Bus_Mst_Addr <= add_thread(C_SCHED_BASEADDR,send_cur);
IP2Bus_MstRd_Req <= '1';
IP2Bus_Mst_BE <= "1111";
send_ns <= SENDING;
end if;
when FINISH =>
if ((mst_cmplt = '1') or (Bus2IP_Mst_Cmplt = '1')) then
send_ns <= IDLE;
else
send_ns <= FINISH;
end if;
end case;
end process send_controller;
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/pr_6smp/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/master.vhd | 10 | 10243 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity master is
generic
(
C_BASEADDR : std_logic_vector := x"00000000";
C_HIGHADDR : std_logic_vector := x"FFFFFFFF";
C_SCHED_BASEADDR : std_logic_vector := x"00000000";
C_RESULT_BASEADDR : std_logic_vector := x"00000000";
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 6;
C_NUM_CE : integer := 4
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
-- Bus2IP_MstLastAck : in std_logic;
-- IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
-- IP2Bus_MstBE : out std_logic_vector(0 to C_DWIDTH/8-1);
-- IP2Bus_MstBurst : out std_logic;
-- IP2Bus_MstBusLock : out std_logic;
-- IP2Bus_MstRdReq : out std_logic;
-- IP2Bus_MstWrReq : out std_logic;
-- IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : in std_logic;
send_id : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : out std_logic;
saddr : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sena : out std_logic;
swea : out std_logic;
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end master;
architecture behavioral of master is
constant THR_BIT : integer := log2( C_NUM_THREADS );
type send_state is
(
IDLE,
SENDING,
FINISH
);
type queue_state is
(
IDLE,
DONE,
GETWAIT,
GETDONE
);
signal mst_cmplt : std_logic;
signal send_cs : send_state;
signal send_ns : send_state;
signal queue_cs : queue_state;
signal queue_ns : queue_state;
signal send_rdy : std_logic;
signal send_valid : std_logic;
signal send_validn : std_logic;
signal send_cur : std_logic_vector(0 to THR_BIT-1);
signal send_curn : std_logic_vector(0 to THR_BIT-1);
signal send_first : std_logic_vector(0 to THR_BIT-1);
signal send_firstn : std_logic_vector(0 to THR_BIT-1);
signal send_last : std_logic_vector(0 to THR_BIT-1);
signal send_lastn : std_logic_vector(0 to THR_BIT-1);
signal send_count : std_logic_vector(0 to THR_BIT-1);
signal send_countn : std_logic_vector(0 to THR_BIT-1);
begin
-- System reset only takes one clock cycle so were always "done"
system_resetdone <= '1';
queue_update : process(Bus2IP_Clk) is
begin
if( rising_edge(Bus2IP_Clk) ) then
if( Bus2IP_Reset = '1' or system_reset = '1' ) then
queue_cs <= IDLE;
send_count <= (others => '0');
send_first <= (others => '0');
send_last <= (others => '0');
send_cur <= (others => '0');
send_valid <= '0';
else
queue_cs <= queue_ns;
send_count <= send_countn;
send_first <= send_firstn;
send_last <= send_lastn;
send_cur <= send_curn;
send_valid <= send_validn;
end if;
end if;
end process queue_update;
queue_controller : process(Bus2IP_Clk,queue_cs, send_cur, send_last, send_first, send_count, send_ena, send_id, send_rdy, sinext) is
begin
sena <= '0';
swea <= '0';
saddr <= (others => '0');
sonext <= (others => '0');
queue_ns <= queue_cs;
send_curn <= send_cur;
send_lastn <= send_last;
send_firstn <= send_first;
send_countn <= send_count;
send_validn <= '0';
case queue_cs is
when IDLE =>
if( send_ena = '1' ) then
if( send_count = zero(THR_BIT) ) then
send_firstn <= send_id;
else
sena <= '1';
swea <= '1';
saddr <= send_last;
sonext <= send_id;
end if;
send_lastn <= send_id;
send_countn <= send_count+1;
send_ack <= '1';
queue_ns <= DONE;
elsif( send_rdy = '1' and send_count /= zero(THR_BIT) ) then
send_curn <= send_first;
send_validn <= '1';
sena <= '1';
saddr <= send_first;
queue_ns <= GETWAIT;
end if;
when DONE =>
send_ack <= '1';
if( send_ena = '0' ) then
queue_ns <= IDLE;
end if;
when GETWAIT => null;
queue_ns <= GETDONE;
when GETDONE =>
send_firstn <= sinext;
send_countn <= send_count-1;
queue_ns <= IDLE;
end case;
end process queue_controller;
send_update : process (Bus2IP_Clk,send_ns) is
begin
if( rising_edge(Bus2IP_Clk) ) then
if( Bus2IP_Reset = '1' or system_reset = '1' ) then
send_cs <= IDLE;
else
send_cs <= send_ns;
end if;
end if;
end process send_update;
send_controller : process (Bus2IP_Mst_CmdAck, Bus2IP_MstRd_src_rdy_n, send_cs,send_valid,send_cur) is
begin
send_ns <= send_cs;
send_rdy <= '0';
IP2Bus_Mst_Addr <= (others => '0');
IP2Bus_Mst_BE <= (others => '0');
IP2Bus_MstRd_Req <= '0';
case send_cs is
when IDLE =>
send_rdy <= '1';
if( send_valid = '1' ) then
send_ns <= SENDING;
end if;
when SENDING =>
-- Capture the Bus2IP_Mst_Cmplt value for later.
if (mst_cmplt = '0') then
mst_cmplt <= Bus2IP_Mst_Cmplt;
end if;
if (Bus2IP_Mst_CmdAck = '1') then
send_ns <= FINISH;
else
IP2Bus_Mst_Addr <= add_thread(C_SCHED_BASEADDR,send_cur);
IP2Bus_MstRd_Req <= '1';
IP2Bus_Mst_BE <= "1111";
send_ns <= SENDING;
end if;
when FINISH =>
if ((mst_cmplt = '1') or (Bus2IP_Mst_Cmplt = '1')) then
send_ns <= IDLE;
else
send_ns <= FINISH;
end if;
end case;
end process send_controller;
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_init_3.vhd | 2 | 15641 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_init_3.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_mutex_init( mutex, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = _mutex_owner( mutex->num );
when STATE_4 =>
-- Load the value of mutex->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg1_next <= intrfc2thrd_value;
-- Call the Synch Manager to find out the owner
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= x"75030000"; -- and yes I"m cheating with the calculated address
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp1/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/result_fsm.vhd | 11 | 3686 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity result_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
sysrst : in std_logic;
rstdone : out std_logic;
rnw : in std_logic;
datain : in std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1)
);
end result_fsm;
architecture behavioral of result_fsm is
-- Declare signals for the results register
signal results : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
result_controller : process (clk,rst,sysrst,start,results,datain,rnw) is
begin
if( rising_edge(clk) ) then
data <= (others => '0');
finish <= '0';
if( rst = '1' or sysrst = '1' ) then
results <= (others => '0');
else
results <= results;
if( start = '1' ) then
if( rnw = '1' ) then
results <= datain;
else
data <= results;
end if;
finish <= '1';
end if;
end if;
end if;
end process result_controller;
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/result_fsm.vhd | 11 | 3686 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity result_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
sysrst : in std_logic;
rstdone : out std_logic;
rnw : in std_logic;
datain : in std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1)
);
end result_fsm;
architecture behavioral of result_fsm is
-- Declare signals for the results register
signal results : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
result_controller : process (clk,rst,sysrst,start,results,datain,rnw) is
begin
if( rising_edge(clk) ) then
data <= (others => '0');
finish <= '0';
if( rst = '1' or sysrst = '1' ) then
results <= (others => '0');
else
results <= results;
if( start = '1' ) then
if( rnw = '1' ) then
results <= datain;
else
data <= results;
end if;
finish <= '1';
end if;
end if;
end if;
end process result_controller;
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/address_decoder.vhd | 3 | 24702 | -------------------------------------------------------------------------------
-- $Id: address_decoder.vhd,v 1.3 2003/05/19 05:19:19 ostlerf Exp $
-------------------------------------------------------------------------------
-- address_decoder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
--
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification, target data bus size, and ce number.
--
-------------------------------------------------------------------------------
--
-- -- address_decoder.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
-- DET 02-12-2002 -- First version
--
--
-- FLO 03-11-2002 -- Modified for use with OPB IPIF
--
-- ToDo List
-- (1) Disable CE, CS if the byte-enable pattern doesn't match the size, or
-- alternatively, generate an error.
--
--
-- FLO 05/16/2003
-- ^^^^^^
-- Fixed pselect component declaration with generic C_BAR as a constrained
-- array. The pselect instance was being tied to the pselect entity with
-- C_BAR declared as an unconstrained array. ModelSim 7.2b detected
-- this error but earlier ModelSims, Synplify and XST allow it.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_unsigned.CONV_INTEGER; --Used in byte count compare 2 MA2SA_Num
--use ieee.std_logic_arith.conv_std_logic_vector;
library Unisim;
use Unisim.vcomponents.all;
--use Unisim.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
use proc_common_v1_00_b.pselect;
--use proc_common_v1_00_b.or_gate;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : Integer := 32;
C_USE_REG_OUTPUTS : Boolean := true;
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
-- := (
-- X"1000_0000", -- IP user0 base address
-- X"1000_01FF", -- IP user0 high address
-- X"1000_0200", -- IP user1 base address
-- X"1000_02FF", -- IP user1 high address
-- X"1000_2000", -- IP user2 base address
-- X"1000_20FF", -- IP user2 high address
-- X"1000_2100", -- IPIF Interrupt base address
-- X"1000_21ff", -- IPIF Interrupt high address
-- X"1000_2200", -- IPIF Reset base address
-- X"1000_22FF", -- IPIF Reset high address
-- X"1000_2300", -- IPIF WrFIFO Registers base address
-- X"1000_23FF", -- IPIF WrFIFO Registers high address
-- X"7000_0000", -- IPIF WrFIFO Data base address
-- X"7000_00FF", -- IPIF WrFIFO Data high address
-- X"8000_0000", -- IPIF RdFIFO Registers base address
-- X"8FFF_FFFF", -- IPIF RdFIFO Registers high address
-- X"9000_0000", -- IPIF RdFIFO Data base address
-- X"9FFF_FFFF" -- IPIF RdFIFO Data high address
-- )
;
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE
-- := (
-- 64 , -- User0 data width
-- 64 , -- User1 data width
-- 64 , -- User2 data width
-- 32 , -- IPIF Interrupt data width
-- 32 , -- IPIF Reset data width
-- 32 , -- IPIF WrFIFO Registers data width
-- 64 , -- IPIF WrFIFO Data data width
-- 32 , -- IPIF RdFIFO Registers data width
-- 64 -- IPIF RdFIFO Data width
-- )
;
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
-- := (
-- 8, -- User0 CE Number
-- 1, -- User1 CE Number
-- 1, -- User2 CE Number
-- 16, -- IPIF Interrupt CE Number
-- 1, -- IPIF Reset CE Number
-- 2, -- IPIF WrFIFO Registers CE Number
-- 1, -- IPIF WrFIFO Data data CE Number
-- 2, -- IPIF RdFIFO Registers CE Number
-- 1 -- IPIF RdFIFO Data CE Number
-- )
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
Address_In : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid : In std_logic;
Bus_RNW : In std_logic;
IP2Bus_RdAck_mx : In std_logic;
IP2Bus_WrAck_mx : In std_logic;
Bus2IP_Burst : In std_logic;
Addr_Match : Out std_logic;
CS_Out : Out std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
CS_Size : Out std_logic_vector(0 to 2);
CE_Out : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
RdCE_Out : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Devicesel_inh_opb : in std_logic;
Devicesel_inh_mstr : in std_logic
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of integer;
type size_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
std_logic_vector(0 to 2);
-- functions ------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then return i;
end if;
end loop;
return(C_BUS_AWIDTH);
end function Addr_Bits;
function Get_Addr_Bits (baseaddrs : SLV64_ARRAY_TYPE)
return decode_bit_array_type is
Variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits(
baseaddrs(i*2)( baseaddrs(0)'length-C_BUS_AWIDTH
to baseaddrs(0)'length-1
),
baseaddrs(i*2+1)( baseaddrs(0)'length-C_BUS_AWIDTH
to baseaddrs(0)'length-1
)
);
end loop;
return(num_bits);
end function Get_Addr_Bits;
function encode_size (size : integer) return std_logic_vector is
Variable enc_size : Std_logic_vector(0 to 2);
begin
Case size Is
When 8 =>
enc_size := "001";
When 16 =>
enc_size := "010";
When 32 =>
enc_size := "011";
When 64 =>
enc_size := "100";
When 128 =>
enc_size := "101";
When others =>
enc_size := "000";
End case;
return(enc_size);
end function encode_size;
--ToDo, remove
-- function bool2int(b: boolean) return integer is
-- type tab_type is array (false to true) of integer;
-- constant tab : tab_type := (false => 0, true => 1);
-- begin
-- return tab(b);
-- end bool2int;
--
--
-------------------------------------------------------------------------------
---- Function calc_start_ce_index
----
---- This function is used to process the array specifying the number of Chip
---- Enables required for a Base Address specification. The CE Size array is
---- input to the function and an integer index representing the index of the
---- target module in the ce_num_array. An integer is returned reflecting the
---- starting index of the assigned Chip Enables within the CE, RdCE, and
---- WrCE Buses.
-------------------------------------------------------------------------------
-- function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
-- index : integer) return integer is
-- Variable ce_num_sum : integer := 0;
-- begin
-- for i in 0 to index-1 loop
-- ce_num_sum := ce_num_sum + ce_num_array(i)
-- + bool2int(ce_num_array(i)=0);
-- End loop;
-- return(ce_num_sum);
-- end function calc_start_ce_index;
--
--
-------------------------------------------------------------------------------
---- Function calc_num_ce
----
---- This function is used to process the array specifying the number of Chip
---- Enables required for a Base Address specification. The array is input to
---- the function and an integer is returned reflecting the total number of
---- Chip Enables required for the CE, RdCE, and WrCE Buses
-------------------------------------------------------------------------------
-- function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
-- Variable ce_num_sum : integer := 0;
-- begin
-- for i in 0 to (ce_num_array'length)-1 loop
-- ce_num_sum := ce_num_sum + ce_num_array(i)
-- + bool2int(ce_num_array(i)=0);
-- End loop;
-- return(ce_num_sum);
-- end function calc_num_ce;
-- Components------------------------------------------------------------------
component pselect is
generic (
C_AB : integer;
C_AW : integer;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end component pselect;
component or_gate is
generic (
C_OR_WIDTH : natural;
C_BUS_WIDTH : natural;
C_USE_LUT_OR : boolean
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end component or_gate;
-- constants
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
Constant DECODE_BITS : decode_bit_array_type := Get_Addr_Bits(C_ARD_ADDR_RANGE_ARRAY);
Constant NUM_SIZES : integer := C_ARD_DWIDTH_ARRAY'length;
Constant NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
-- Signals
signal CS_Out_i : std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal CE_Out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal CS_Size_i : std_logic_vector(0 to 2);
signal CS_Size_array : size_array_type;
Signal size_or_bus : std_logic_vector(0 to (3*NUM_SIZES)-1);
Signal decode_hit : std_logic_vector(0 to 0);
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Universal Address Decode Block
-----------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
begin
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: pselect
generic map (
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => C_ARD_ADDR_RANGE_ARRAY(bar_index*2)
( C_ARD_ADDR_RANGE_ARRAY(0)'length-C_BUS_AWIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length-1
)
)
port map (
A => Address_In, -- [in]
AValid => Address_Valid, -- [in]
CS => CS_Out_i(bar_index) -- [out]
);
-- Generate the size outputs
Assign_size : process (CS_Out_i(bar_index))
Begin
If (CS_Out_i(bar_index) = '1') Then
CS_Size_array(bar_index) <= encode_size(C_ARD_DWIDTH_ARRAY(bar_index));
else
CS_Size_array(bar_index) <= (others => '0');
End if;
End process; -- assign_size
-------------------------------------------------------------------------
-- Now expand the individual chip enables for each base address.
-------------------------------------------------------------------------
DECODE_REGBITS: for ce_index in
0 to C_ARD_NUM_CE_ARRAY(bar_index)
- 1
generate
Constant NEXT_CE_INDEX_START : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_DECODE_ADDR_SIZE : Integer range 0 to 15 := log2(C_ARD_NUM_CE_ARRAY(bar_index));
begin
---------------------------------------------------------------------
-- There is only one CE required so just use the output of the
-- pselect as the CE.
---------------------------------------------------------------------
CE_IS_CS : if (CE_DECODE_ADDR_SIZE = 0) generate
Constant ARRAY_INDEX : integer := ce_index;
Constant BASEADDR_INDEX : integer := bar_index;
begin
CE_Out_i(NEXT_CE_INDEX_START+ARRAY_INDEX) <= CS_Out_i(BASEADDR_INDEX);
end generate CE_IS_CS;
---------------------------------------------------------------------
-- Multiple CEs are required so expand and decode as needed by the
-- specified number of CEs.
---------------------------------------------------------------------
CE_EXPAND : if (CE_DECODE_ADDR_SIZE > 0) generate
Constant ARRAY_INDEX : integer := ce_index;
Constant BASEADDR_INDEX : integer := bar_index;
constant CE_DECODE_SKIP_BITS : Integer range 0 to 8 := log2(C_ARD_DWIDTH_ARRAY(BASEADDR_INDEX)/8);
constant CE_ADDR_WIDTH : Integer range 0 to 31 := CE_DECODE_ADDR_SIZE + CE_DECODE_SKIP_BITS;
constant ADDR_START_INDEX : integer range 0 to 31 := C_BUS_AWIDTH-CE_ADDR_WIDTH;
constant ADDR_END_INDEX : integer range 0 to 31 := C_BUS_AWIDTH-CE_DECODE_SKIP_BITS-1;
Signal compare_address : std_logic_vector(0 to CE_DECODE_ADDR_SIZE-1);
begin
INDIVIDUAL_CE_GEN : process (Address_In, CS_Out_i(BASEADDR_INDEX), compare_address)
Begin
compare_address <= Address_In(ADDR_START_INDEX to ADDR_END_INDEX);
if compare_address = ARRAY_INDEX then
CE_Out_i(NEXT_CE_INDEX_START+ARRAY_INDEX) <= CS_Out_i(BASEADDR_INDEX);
else
CE_Out_i(NEXT_CE_INDEX_START+ARRAY_INDEX) <= '0';
end if;
End process INDIVIDUAL_CE_GEN;
end generate CE_EXPAND;
end generate DECODE_REGBITS;
end generate MEM_DECODE_GEN;
OR_CS_Size : process (CS_Size_array)
Begin
for i in 0 to NUM_SIZES-1 loop
size_or_bus(3*i to 3*i+2) <= CS_Size_array(i);
End loop;
End process; -- OR_CS_SIZE
I_OR_SIZES : or_gate
generic map(
C_OR_WIDTH => NUM_SIZES,
C_BUS_WIDTH => 3,
C_USE_LUT_OR => TRUE
)
port map(
A => size_or_bus,
Y => CS_Size_i
);
I_OR_CS : or_gate
generic map(
C_OR_WIDTH => NUM_BASE_ADDRS,
C_BUS_WIDTH => 1,
C_USE_LUT_OR => TRUE
)
port map(
A => CS_Out_i,
Y => decode_hit
);
-------------------------------------------------------------------------------
-- end of decoder block
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Non-Registered Outputs Selection
-------------------------------------------------------------------------------
NOREG_OUTPUTS : if (C_USE_REG_OUTPUTS = False) generate
-- Assign output signals to combinational signals
Addr_Match <= decode_hit(0) ;
CS_Out <= CS_Out_i ;
CS_Size <= CS_Size_i ;
CE_Out <= CE_Out_i ;
SET_NOREG_RW_CE : process (CE_Out_i, Bus_RNW)
Begin
for i in 0 to NUM_CE_SIGNALS-1 loop
RdCE_Out(i) <= CE_Out_i(i) and Bus_RNW;
WrCE_Out(i) <= CE_Out_i(i) and not(Bus_RNW);
End loop;
End process; -- SET_NOREG_RW_CE
end generate NOREG_OUTPUTS;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- PLB REQUIRED REGISTERING
-------------------------------------------------------------------------------
-- The following logic is required by the PLB. It latches and holds the
-- signals necesary for the completion of the data phase of a PLB access.
-- It also generates the correct RdCE and WrCE timing for interfacing to
-- legacy OPB modules
-------------------------------------------------------------------------------
REGISTER_OUTPUTS : if (C_USE_REG_OUTPUTS = True) generate
signal CS_Out_i_reg : std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal CE_Out_i_reg : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal RdCE_Out_i_reg : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal WrCE_Out_i_reg : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal CS_Size_i_reg : std_logic_vector(0 to 2);
Signal decode_hit_reg : std_logic;
signal ff_reset : std_logic;
signal rdce_reset : std_logic;
signal wrce_reset : std_logic;
begin
ff_reset <= '1' when (Bus2IP_Burst = '0' and ( IP2Bus_WrAck_mx = '1'
or IP2Bus_RdAck_mx = '1'
)
)
or Bus_rst = '1' or
(Devicesel_inh_opb or Devicesel_inh_mstr) = '1'
else '0' ;
rdce_reset <= '1' when (Bus2IP_Burst = '0' and IP2Bus_RdAck_mx = '1')
or Bus_rst = '1'
or Bus_RNW = '0' or
(Devicesel_inh_opb or Devicesel_inh_mstr) = '1' else '0';
wrce_reset <= '1' when (Bus2IP_Burst = '0' and IP2Bus_WrAck_mx = '1')
or Bus_rst = '1'
or Bus_RNW = '1' or
(Devicesel_inh_opb or Devicesel_inh_mstr) = '1'
else '0';
REGCS_GEN: for i in 0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 generate
REGCS_FF_I: FDR
port map (
Q => CS_Out_i_reg(i),
C => Bus_clk,
D => CS_Out_i(i),
R => ff_reset
);
end generate REGCS_GEN;
REGCS_SIZE_GEN: for i in 0 to 2 generate
REGCS_SIZE_FF_I: FDR
port map (
D => CS_Size_i(i),
C => Bus_clk,
Q => CS_Size_i_reg(i),
R => ff_reset
);
end generate REGCS_SIZE_GEN;
REGCE_GEN: for i in 0 to NUM_CE_SIGNALS-1 generate
REGCE_FF_I: FDR
port map (
D => CE_Out_i(i),
C => Bus_clk,
Q => CE_Out_i_reg(i),
R => ff_reset
);
REGRDCE_FF_I: FDR
port map (
D => CE_Out_i(i),
C => Bus_clk,
Q => RdCE_Out_i_reg(i),
R => rdce_reset
);
REGWRCE_FF_I: FDR
port map (
D => CE_Out_i(i),
C => Bus_clk,
Q => WrCE_Out_i_reg(i),
R => wrce_reset
);
end generate REGCE_GEN;
-- -- Register the CS and CE signals
-- REGCS_PROCESS: process(Bus_clk)
-- begin
--
-- if (Bus_clk'event and Bus_clk='1') then
-- if (Bus2IP_Burst = '0' and ( IP2Bus_WrAck_mx = '1'
-- or IP2Bus_RdAck_mx = '1'
-- )
-- )
-- or Bus_rst = '1'
-- then
-- CS_Out_i_reg <= (others => '0');
-- CS_Size_i_reg <= (others => '0');
-- CE_Out_i_reg <= (others => '0');
-- else
-- CS_Out_i_reg <= CS_Out_i;
-- CS_Size_i_reg <= CS_Size_i;
-- CE_Out_i_reg <= CE_Out_i;
-- end if;
-- end if;
--
-- if (Bus_clk'event and Bus_clk='1') then
-- if (Bus2IP_Burst = '0' and IP2Bus_RdAck_mx = '1')
-- or Bus_rst = '1'
-- or Bus_RNW = '0'
-- then
-- RdCE_Out_i_reg <= (others => '0');
-- else
-- RdCE_Out_i_reg <= CE_Out_i;
-- end if;
-- end if;
--
-- if (Bus_clk'event and Bus_clk='1') then
-- if (Bus2IP_Burst = '0' and IP2Bus_WrAck_mx = '1')
-- or Bus_rst = '1'
-- or Bus_RNW = '1'
-- then
-- WrCE_Out_i_reg <= (others => '0');
-- else
-- WrCE_Out_i_reg <= CE_Out_i;
-- end if;
-- end if;
--
-- end process;
-- Register the Decode hit signal
REG_DECODE_HIT : process (Bus_clk)
Begin
if (Bus_clk'event and Bus_clk='1') then
if Bus_rst = '1' then
decode_hit_reg <= '0';
else
decode_hit_reg <= decode_hit(0);
end if;
end if;
End process; -- REG_DECODE_HIT
-- Assign output signals to registered signals
Addr_Match <= decode_hit_reg ;
CS_Out <= CS_Out_i_reg ;
CS_Size <= CS_Size_i_reg ;
CE_Out <= CE_Out_i_reg ;
RdCE_Out <= RdCE_Out_i_reg ;
WrCE_Out <= WrCE_Out_i_reg ;
end generate REGISTER_OUTPUTS;
-------------------------------------------------------------------------------
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp1/design/pcores/plb_hthreads_timer_v1_00_a/hdl/vhdl/user_logic.vhd | 9 | 9363 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_counter_reg : std_logic_vector(0 to 2*C_SLV_DWIDTH-1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s) and counter
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_counter_reg <= (others => '0');
else
slv_counter_reg <= slv_counter_reg + 1;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_counter_reg ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_counter_reg(0 to C_SLV_DWIDTH-1); -- Upper bits
when "01" => slv_ip2bus_data <= slv_counter_reg(C_SLV_DWIDTH to 2*C_SLV_DWIDTH-1); -- Lower bits
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/plb_hthreads_timer_v1_00_a/hdl/vhdl/user_logic.vhd | 9 | 9363 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_counter_reg : std_logic_vector(0 to 2*C_SLV_DWIDTH-1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s) and counter
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_counter_reg <= (others => '0');
else
slv_counter_reg <= slv_counter_reg + 1;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_counter_reg ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_counter_reg(0 to C_SLV_DWIDTH-1); -- Upper bits
when "01" => slv_ip2bus_data <= slv_counter_reg(C_SLV_DWIDTH to 2*C_SLV_DWIDTH-1); -- Lower bits
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| bsd-3-clause |
jevinskie/aes-over-pcie | source/experiment/bus_test.vhd | 1 | 1243 | -- File name: bus_test.vhd
-- Created: 2009-02-25
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: block for testing bus stuff
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bus_test is
port (
clk : in std_logic;
nrst : in std_logic;
b : out unsigned(7 downto 0)
);
end bus_test;
architecture behavioral of bus_test is
signal n : unsigned(2 downto 0);
begin
process(clk, nrst)
begin
if (nrst='0') then
n <= (others => '0');
elsif (rising_edge(clk)) then
n <= n + 1;
end if;
end process;
process(n)
begin
case n is
when "001" => b <= to_unsigned(2, 8);
when others => b <= (others => 'Z');
end case;
end process;
process(n)
begin
case n is
when "011" => b <= to_unsigned(4, 8);
when others => b <= (others => 'Z');
end case;
end process;
process(n)
begin
case n is
when "001" => b <= (others => 'Z');
when "011" => b <= (others => 'Z');
when others => b <= to_unsigned(7, 8);
end case;
end process;
end behavioral;
| bsd-3-clause |
EnricoGiordano1992/resim-simulating-partial-reconfiguration | examples/state_migration/edk/pcores/ipif_v1_00_a/hdl/vhdl/plbv46_master_burst_wrapper_128.vhd | 3 | 19674 | ------------------------------------------------------------------------------
-- plbv46_master_burst_wrapper.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_master_burst_v1_01_a;
use plbv46_master_burst_v1_01_a.plbv46_master_burst;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plbv46_master_burst_wrapper is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 128;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_INHIBIT_CC_BLE_INCLUSION : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- ADD USER GENERICS BELOW THIS LINE ---------------
-- ADD USER GENERICS ABOVE THIS LINE ---------------
);
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
MPLB_Clk : in std_logic ;
MPLB_Rst : in std_logic ;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8) - 1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_abort : out std_logic;
M_lockErr : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_UABus : out std_logic_vector(0 to 31);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to C_MPLB_DWIDTH-1);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- ADD USER PORTS BELOW THIS LINE ------------------
Bus2IP_Mst_Clk : out std_logic;
Bus2IP_Mst_Reset : out std_logic;
IP2Bus_MstRd_Req : in std_logic;
IP2Bus_MstWr_Req : in std_logic;
IP2Bus_Mst_Addr : in std_logic_vector(0 to C_MPLB_AWIDTH-1);
IP2Bus_Mst_Length : in std_logic_vector(0 to 11);
IP2Bus_Mst_BE : in std_logic_vector(0 to 128/8 -1);
IP2Bus_Mst_Type : in std_logic;
IP2Bus_Mst_Lock : in std_logic;
IP2Bus_Mst_Reset : in std_logic;
Bus2IP_Mst_CmdAck : out std_logic;
Bus2IP_Mst_Cmplt : out std_logic;
Bus2IP_Mst_Error : out std_logic;
Bus2IP_Mst_Rearbitrate : out std_logic;
Bus2IP_Mst_Cmd_Timeout : out std_logic;
Bus2IP_MstRd_d : out std_logic_vector(0 to 128-1);
Bus2IP_MstRd_rem : out std_logic_vector(0 to 128/8-1);
Bus2IP_MstRd_sof_n : out std_logic;
Bus2IP_MstRd_eof_n : out std_logic;
Bus2IP_MstRd_src_rdy_n : out std_logic;
Bus2IP_MstRd_src_dsc_n : out std_logic;
IP2Bus_MstRd_dst_rdy_n : in std_logic;
IP2Bus_MstRd_dst_dsc_n : in std_logic;
IP2Bus_MstWr_d : in std_logic_vector(0 to 128-1);
IP2Bus_MstWr_rem : in std_logic_vector(0 to 128/8-1);
IP2Bus_MstWr_sof_n : in std_logic;
IP2Bus_MstWr_eof_n : in std_logic;
IP2Bus_MstWr_src_rdy_n : in std_logic;
IP2Bus_MstWr_src_dsc_n : in std_logic;
Bus2IP_MstWr_dst_rdy_n : out std_logic;
Bus2IP_MstWr_dst_dsc_n : out std_logic
-- ADD USER PORTS ABOVE THIS LINE ------------------
);
end entity plbv46_master_burst_wrapper;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plbv46_master_burst_wrapper is
constant PADDING_ZEROS : std_logic_vector(0 to 127) := (others => '0');
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
-- NOT USED: signal ipif_IP2Bus_MstRd_Req : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_Req : std_logic;
-- NOT USED: signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
-- NOT USED: signal ipif_IP2Bus_Mst_Length : std_logic_vector(0 to 11);
-- NOT USED: signal ipif_IP2Bus_Mst_Type : std_logic;
-- NOT USED: signal ipif_IP2Bus_Mst_Lock : std_logic;
-- NOT USED: signal ipif_IP2Bus_Mst_Reset : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_CmdAck : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Cmplt : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Error : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_sof_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_eof_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_src_dsc_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstRd_dst_rdy_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstRd_dst_dsc_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_sof_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_eof_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_src_rdy_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_src_dsc_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstWr_dst_dsc_n : std_logic;
--
-- BITWIDTH ADAPTION:
--
-- Bitwidth of plbv46_master_burst is variable depending on the C_SPLB_DWIDTH/C_SPLB_NATIVE_DWIDTH
-- Bitwidth of plbv46_master_burst_wrapper_128 is tuned for 128bit systemc modules
--
-- The following signals may have different bitwidth between
-- plbv46_master_burst and plbv46_master_burst_wrapper_128. And MSBs of them may not be connected
--
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_IP2Bus_MstWr_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
begin
------------------------------------------
-- instantiate plbv46_master_burst
------------------------------------------
PLBV46_MASTER_BURST_I : entity plbv46_master_burst_v1_01_a.plbv46_master_burst
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_INHIBIT_CC_BLE_INCLUSION => C_INHIBIT_CC_BLE_INCLUSION,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr,
IP2Bus_Mst_Length => IP2Bus_Mst_Length,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE, ---- FOR BITWIDTH ADAPTION
IP2Bus_Mst_Type => IP2Bus_Mst_Type,
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d, ---- FOR BITWIDTH ADAPTION
Bus2IP_MstRd_rem => ipif_Bus2IP_MstRd_rem, ---- FOR BITWIDTH ADAPTION
Bus2IP_MstRd_sof_n => Bus2IP_MstRd_sof_n,
Bus2IP_MstRd_eof_n => Bus2IP_MstRd_eof_n,
Bus2IP_MstRd_src_rdy_n => Bus2IP_MstRd_src_rdy_n,
Bus2IP_MstRd_src_dsc_n => Bus2IP_MstRd_src_dsc_n,
IP2Bus_MstRd_dst_rdy_n => IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => IP2Bus_MstRd_dst_dsc_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d, ---- FOR BITWIDTH ADAPTION
IP2Bus_MstWr_rem => ipif_IP2Bus_MstWr_rem, ---- FOR BITWIDTH ADAPTION
IP2Bus_MstWr_sof_n => IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => IP2Bus_MstWr_src_dsc_n,
Bus2IP_MstWr_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n,
Bus2IP_MstWr_dst_dsc_n => Bus2IP_MstWr_dst_dsc_n
);
ipif_IP2Bus_Mst_BE <= IP2Bus_Mst_BE(128/8-C_MPLB_NATIVE_DWIDTH/8 to 128/8-1);
ipif_IP2Bus_MstWr_d <= IP2Bus_MstWr_d(128-C_MPLB_NATIVE_DWIDTH to 128-1);
ipif_IP2Bus_MstWr_rem <= IP2Bus_MstWr_rem(128/8-C_MPLB_NATIVE_DWIDTH/8 to 128/8-1);
Bus2IP_MstRd_d <= PADDING_ZEROS(C_MPLB_NATIVE_DWIDTH to 128-1) & ipif_Bus2IP_MstRd_d;
Bus2IP_MstRd_rem <= PADDING_ZEROS(C_MPLB_NATIVE_DWIDTH/8 to 16-1) & ipif_Bus2IP_MstRd_rem;
Bus2IP_Mst_Clk <= MPLB_Clk;
Bus2IP_Mst_Reset <= MPLB_Rst;
end IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_hthread_reset_core_v1_00_a/hdl/vhdl/plb_hthread_reset_core.vhd | 9 | 24727 | ------------------------------------------------------------------------------
-- plb_hthread_reset_core.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_hthread_reset_core.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plb_hthread_reset_core_v1_00_a;
use plb_hthread_reset_core_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity plb_hthread_reset_core is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity plb_hthread_reset_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_hthread_reset_core is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant RST_NUM_CE : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => RST_NUM_CE -- number of ce for soft reset space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 4;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant RST_CS_INDEX : integer := 1;
constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_hthread_reset_core_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
reset_port0 => reset_port0,
reset_response_port0 => reset_response_port0,
reset_port1 => reset_port1,
reset_response_port1 => reset_response_port1,
reset_port2 => reset_port2,
reset_response_port2 => reset_response_port2,
reset_port3 => reset_port3,
reset_response_port3 => reset_response_port3,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "01" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/testbench.vhd | 11 | 11805 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.common.all;
entity testbench is
end testbench;
architecture behavior of testbench is
-- Synch Manager Configuration Constants
constant SCHED_BADDR : std_logic_vector(0 to 31) := x"60000000";
constant SCHED_HADDR : std_logic_vector(0 to 31) := x"6FFFFFFF";
constant MUTEX_BADDR : std_logic_vector(0 to 31) := x"70000000";
constant MUTEX_HADDR : std_logic_vector(0 to 31) := x"7FFFFFFF";
constant SYNCH_THREADS : integer := 256;
constant SYNCH_MUTEXES : integer := 64;
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(SYNCH_MUTEXES);
constant THREAD_BITS : integer := log2(SYNCH_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
constant DATA_BITS : integer := 32;
--Inputs
signal OPB_Clk : std_logic := '0';
signal OPB_Rst : std_logic := '0';
signal OPB_RNW : std_logic := '0';
signal OPB_select : std_logic := '0';
signal OPB_seqAddr : std_logic := '0';
signal OPB_errAck : std_logic := '0';
signal OPB_MGrant : std_logic := '0';
signal OPB_retry : std_logic := '0';
signal OPB_timeout : std_logic := '0';
signal OPB_xferAck : std_logic := '0';
signal OPB_ABus : std_logic_vector(0 to 31) := (others=>'0');
signal OPB_BE : std_logic_vector(0 to 3) := (others=>'0');
signal OPB_DBus : std_logic_vector(0 to 31) := (others=>'0');
--Outputs
signal Sl_DBus : std_logic_vector(0 to 31);
signal Sl_errAck : std_logic;
signal Sl_retry : std_logic;
signal Sl_toutSup : std_logic;
signal Sl_xferAck : std_logic;
signal M_ABus : std_logic_vector(0 to 31);
signal M_BE : std_logic_vector(0 to 3);
signal M_busLock : std_logic;
signal M_request : std_logic;
signal M_RNW : std_logic;
signal M_select : std_logic;
signal M_seqAddr : std_logic;
-- Reset signals
signal system_reset : std_logic;
signal system_resetdone : std_logic;
begin
-- Instantiate the Unit Under Test (UUT)
synch : entity work.opb_synchmanager
generic map
(
C_NUM_THREADS => SYNCH_THREADS,
C_NUM_MUTEXES => SYNCH_MUTEXES,
C_SCHED_BADDR => SCHED_BADDR,
C_SCHED_HADDR => SCHED_HADDR,
C_BASEADDR => MUTEX_BADDR,
C_HIGHADDR => MUTEX_HADDR
)
port map
(
OPB_Clk => OPB_Clk,
OPB_Rst => OPB_Rst,
Sl_DBus => Sl_DBus,
Sl_errAck => Sl_errAck,
Sl_retry => Sl_retry,
Sl_toutSup => Sl_toutSup,
Sl_xferAck => Sl_xferAck,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus => OPB_DBus,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_request => M_request,
M_RNW => M_RNW,
M_select => M_select,
M_seqAddr => M_seqAddr,
OPB_errAck => OPB_errAck,
OPB_MGrant => OPB_MGrant,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
OPB_xferAck => OPB_xferAck,
system_reset => system_reset,
system_resetdone => system_resetdone
);
tb : process
procedure bus_trans( rnw : in std_logic;
abus : in std_logic_vector(0 to 31);
dbus : in std_logic_vector(0 to 31) ) is
begin
wait until OPB_Clk = '1';
OPB_ABus <= abus;
OPB_DBus <= dbus;
OPB_RNW <= rnw;
OPB_select <= '1';
OPB_BE <= (others => '1');
wait until Sl_xferAck = '1' and OPB_Clk = '1';
OPB_ABus <= (others => '0');
OPB_DBus <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
OPB_BE <= (others => '0');
wait until OPB_Clk = '1';
end procedure bus_trans;
procedure bus_reset is
begin
wait until OPB_Clk = '1';
OPB_Rst <= '1';
OPB_select <= '0';
OPB_seqAddr <= '0';
OPB_RNW <= '0';
OPB_BE <= (others => '0');
OPB_ABus <= (others => '0');
OPB_DBus <= (others => '0');
wait until OPB_Clk = '1';
OPB_Rst <= '0';
end procedure bus_reset;
procedure sys_reset is
begin
-- Issue a bus reset first
bus_reset;
-- Assert the system reset signal
system_reset <= '1';
-- Wait until the core is finished resetting
wait until system_resetdone = '1';
-- Deassert the system reset signal
system_reset <= '0';
end procedure sys_reset;
function synch_cmd( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1);
cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to 31);
begin
addr := MUTEX_BADDR;
addr(30-MUTEX_BITS to 29) := mid;
addr(30-MUTEX_BITS-THREAD_BITS to 29-MUTEX_BITS) := tid;
addr(30-MUTEX_BITS-THREAD_BITS-COMMAND_BITS to 29-MUTEX_BITS-THREAD_BITS) := cmd;
return addr;
end function synch_cmd;
procedure synchm_lock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_LOCK),x"FFFFFFFF");
end procedure synchm_lock;
procedure synchm_unlock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_UNLOCK),x"FFFFFFFF");
end procedure synchm_unlock;
procedure synchm_trylock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_TRY),x"FFFFFFFF");
end procedure synchm_trylock;
procedure synchm_kind( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_KIND),x"FFFFFFFF");
end procedure synchm_kind;
procedure synchm_count( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_COUNT),x"FFFFFFFF");
end procedure synchm_count;
procedure synchm_owner( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_OWNER),x"FFFFFFFF");
end procedure synchm_owner;
procedure synchm_setkind( mid : in std_logic_vector(0 to MUTEX_BITS-1);
kind : in std_logic_vector(0 to KIND_BITS-1)) is
variable data : std_logic_vector(0 to DATA_BITS-1);
begin
data := (others => '0');
data(DATA_BITS-KIND_BITS to DATA_BITS-1) := kind;
bus_trans('0',synch_cmd(x"00",mid,SYNCH_KIND),data);
end procedure synchm_setkind;
begin
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Send a bus reset command
sys_reset;
-- Setup the mutex kinds
synchm_setkind( "000000", SYNCH_FAST );
synchm_setkind( "000001", SYNCH_FAST );
synchm_setkind( "000010", SYNCH_ERROR );
synchm_setkind( "000011", SYNCH_RECURS );
-- Test standard locking and unlocking
synchm_lock( x"01", "000000" );
synchm_lock( x"02", "000000" );
synchm_trylock( x"03", "000000" );
synchm_lock( x"04", "000000" );
synchm_unlock( x"01", "000000" );
synchm_unlock( x"02", "000000" );
synchm_unlock( x"04", "000000" );
-- Test that fast mutex locking method works properly
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
-- Test that error checking mutex locking method works properly
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
-- Test that recursive mutex locking method works properly
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
-- Test that getting the owner works properly
synchm_owner( "000001" );
synchm_owner( "000010" );
synchm_owner( "000011" );
-- Test that getting the count works properly
synchm_count( "000011" );
-- Test that getting the kind works properly
synchm_kind( "000000" );
synchm_kind( "000001" );
synchm_kind( "000010" );
synchm_kind( "000011" );
-- Test that recursive mutex unlocking works
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
wait; -- will wait forever
end process;
clk : process
begin
OPB_Clk <= '0';
wait for 10 ns;
loop
OPB_Clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
end process;
end;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/hwti_mblaze_6smp/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/testbench.vhd | 11 | 11805 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.common.all;
entity testbench is
end testbench;
architecture behavior of testbench is
-- Synch Manager Configuration Constants
constant SCHED_BADDR : std_logic_vector(0 to 31) := x"60000000";
constant SCHED_HADDR : std_logic_vector(0 to 31) := x"6FFFFFFF";
constant MUTEX_BADDR : std_logic_vector(0 to 31) := x"70000000";
constant MUTEX_HADDR : std_logic_vector(0 to 31) := x"7FFFFFFF";
constant SYNCH_THREADS : integer := 256;
constant SYNCH_MUTEXES : integer := 64;
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(SYNCH_MUTEXES);
constant THREAD_BITS : integer := log2(SYNCH_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
constant DATA_BITS : integer := 32;
--Inputs
signal OPB_Clk : std_logic := '0';
signal OPB_Rst : std_logic := '0';
signal OPB_RNW : std_logic := '0';
signal OPB_select : std_logic := '0';
signal OPB_seqAddr : std_logic := '0';
signal OPB_errAck : std_logic := '0';
signal OPB_MGrant : std_logic := '0';
signal OPB_retry : std_logic := '0';
signal OPB_timeout : std_logic := '0';
signal OPB_xferAck : std_logic := '0';
signal OPB_ABus : std_logic_vector(0 to 31) := (others=>'0');
signal OPB_BE : std_logic_vector(0 to 3) := (others=>'0');
signal OPB_DBus : std_logic_vector(0 to 31) := (others=>'0');
--Outputs
signal Sl_DBus : std_logic_vector(0 to 31);
signal Sl_errAck : std_logic;
signal Sl_retry : std_logic;
signal Sl_toutSup : std_logic;
signal Sl_xferAck : std_logic;
signal M_ABus : std_logic_vector(0 to 31);
signal M_BE : std_logic_vector(0 to 3);
signal M_busLock : std_logic;
signal M_request : std_logic;
signal M_RNW : std_logic;
signal M_select : std_logic;
signal M_seqAddr : std_logic;
-- Reset signals
signal system_reset : std_logic;
signal system_resetdone : std_logic;
begin
-- Instantiate the Unit Under Test (UUT)
synch : entity work.opb_synchmanager
generic map
(
C_NUM_THREADS => SYNCH_THREADS,
C_NUM_MUTEXES => SYNCH_MUTEXES,
C_SCHED_BADDR => SCHED_BADDR,
C_SCHED_HADDR => SCHED_HADDR,
C_BASEADDR => MUTEX_BADDR,
C_HIGHADDR => MUTEX_HADDR
)
port map
(
OPB_Clk => OPB_Clk,
OPB_Rst => OPB_Rst,
Sl_DBus => Sl_DBus,
Sl_errAck => Sl_errAck,
Sl_retry => Sl_retry,
Sl_toutSup => Sl_toutSup,
Sl_xferAck => Sl_xferAck,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus => OPB_DBus,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_request => M_request,
M_RNW => M_RNW,
M_select => M_select,
M_seqAddr => M_seqAddr,
OPB_errAck => OPB_errAck,
OPB_MGrant => OPB_MGrant,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
OPB_xferAck => OPB_xferAck,
system_reset => system_reset,
system_resetdone => system_resetdone
);
tb : process
procedure bus_trans( rnw : in std_logic;
abus : in std_logic_vector(0 to 31);
dbus : in std_logic_vector(0 to 31) ) is
begin
wait until OPB_Clk = '1';
OPB_ABus <= abus;
OPB_DBus <= dbus;
OPB_RNW <= rnw;
OPB_select <= '1';
OPB_BE <= (others => '1');
wait until Sl_xferAck = '1' and OPB_Clk = '1';
OPB_ABus <= (others => '0');
OPB_DBus <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
OPB_BE <= (others => '0');
wait until OPB_Clk = '1';
end procedure bus_trans;
procedure bus_reset is
begin
wait until OPB_Clk = '1';
OPB_Rst <= '1';
OPB_select <= '0';
OPB_seqAddr <= '0';
OPB_RNW <= '0';
OPB_BE <= (others => '0');
OPB_ABus <= (others => '0');
OPB_DBus <= (others => '0');
wait until OPB_Clk = '1';
OPB_Rst <= '0';
end procedure bus_reset;
procedure sys_reset is
begin
-- Issue a bus reset first
bus_reset;
-- Assert the system reset signal
system_reset <= '1';
-- Wait until the core is finished resetting
wait until system_resetdone = '1';
-- Deassert the system reset signal
system_reset <= '0';
end procedure sys_reset;
function synch_cmd( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1);
cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to 31);
begin
addr := MUTEX_BADDR;
addr(30-MUTEX_BITS to 29) := mid;
addr(30-MUTEX_BITS-THREAD_BITS to 29-MUTEX_BITS) := tid;
addr(30-MUTEX_BITS-THREAD_BITS-COMMAND_BITS to 29-MUTEX_BITS-THREAD_BITS) := cmd;
return addr;
end function synch_cmd;
procedure synchm_lock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_LOCK),x"FFFFFFFF");
end procedure synchm_lock;
procedure synchm_unlock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_UNLOCK),x"FFFFFFFF");
end procedure synchm_unlock;
procedure synchm_trylock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_TRY),x"FFFFFFFF");
end procedure synchm_trylock;
procedure synchm_kind( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_KIND),x"FFFFFFFF");
end procedure synchm_kind;
procedure synchm_count( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_COUNT),x"FFFFFFFF");
end procedure synchm_count;
procedure synchm_owner( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_OWNER),x"FFFFFFFF");
end procedure synchm_owner;
procedure synchm_setkind( mid : in std_logic_vector(0 to MUTEX_BITS-1);
kind : in std_logic_vector(0 to KIND_BITS-1)) is
variable data : std_logic_vector(0 to DATA_BITS-1);
begin
data := (others => '0');
data(DATA_BITS-KIND_BITS to DATA_BITS-1) := kind;
bus_trans('0',synch_cmd(x"00",mid,SYNCH_KIND),data);
end procedure synchm_setkind;
begin
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Send a bus reset command
sys_reset;
-- Setup the mutex kinds
synchm_setkind( "000000", SYNCH_FAST );
synchm_setkind( "000001", SYNCH_FAST );
synchm_setkind( "000010", SYNCH_ERROR );
synchm_setkind( "000011", SYNCH_RECURS );
-- Test standard locking and unlocking
synchm_lock( x"01", "000000" );
synchm_lock( x"02", "000000" );
synchm_trylock( x"03", "000000" );
synchm_lock( x"04", "000000" );
synchm_unlock( x"01", "000000" );
synchm_unlock( x"02", "000000" );
synchm_unlock( x"04", "000000" );
-- Test that fast mutex locking method works properly
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
-- Test that error checking mutex locking method works properly
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
-- Test that recursive mutex locking method works properly
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
-- Test that getting the owner works properly
synchm_owner( "000001" );
synchm_owner( "000010" );
synchm_owner( "000011" );
-- Test that getting the count works properly
synchm_count( "000011" );
-- Test that getting the kind works properly
synchm_kind( "000000" );
synchm_kind( "000001" );
synchm_kind( "000010" );
synchm_kind( "000011" );
-- Test that recursive mutex unlocking works
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
wait; -- will wait forever
end process;
clk : process
begin
OPB_Clk <= '0';
wait for 10 ns;
loop
OPB_Clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
end process;
end;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_v20_v1_10_d/hdl/vhdl/ipif_control_wr.vhd | 3 | 38141 | -------------------------------------------------------------------------------
-- $Id: ipif_control_wr.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
--ipif_control_wr.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_control_wr.vhd
--
-- Description: This VHDL design file is for the Point Design of the Mauna
-- Loa Write Packet FIFO IPIF Local Bus Interface control
-- block.
--
-------------------------------------------------------------------------------
-- Structure:
--
--
--
-- ipif_control_wr.vhd
--
--
--
--
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe April 5, 2001 -- V1.00a
--
-- DET June 25, 2001 V1.00b
-- - eliminated redundant logic warnings during synthesis
--
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
--
-- DET Sept. 4, 2001
-- - Optimization changes and clean up
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
entity ipif_control_wr is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for disable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_INTFC_TYPE : integer range 0 to 31 := 1;
-- IPIF block protocol Type
C_VERSION_MAJOR : integer range 0 to 9 := 9;
-- Major versioning of top level design
C_VERSION_MINOR : integer range 0 to 99 := 99;
-- Minor Version of top level design
C_VERSION_REV : integer range 0 to 25 := 0;
-- Revision letter of top level design
C_FIFO_WIDTH : Integer := 32;
-- Width of FIFO data in bits
C_DP_ADDRESS_WIDTH : Integer := 9;
-- Indicates address width of RdFIFO memory
-- (= log2(fifo_depth)
C_SUPPORT_BURST : Boolean := true;
-- Indicates write burst support for the IPIF bus
C_IPIF_DBUS_WIDTH : Integer := 32
-- Width of the IPIF data bus in bits
);
port (
-- Inputs From the IPIF Bus
Bus_rst : In std_logic; -- Master Reset from the IPIF
Bus_clk : In std_logic; -- Master timing clock from the IPIF
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-- Inputs from the FIFO Interface Logic
Fifo_WrAck : In std_logic;
Vacancy : In std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
AlmostFull : In std_logic;
Full : In std_logic;
Deadlock : In std_logic;
-- Outputs to the FIFO
Fifo_wr_data : Out std_logic_vector(0 to C_FIFO_WIDTH-1);
Fifo_Reset : Out std_logic;
Fifo_WrReq : Out std_logic;
Fifo_burst_wr_xfer : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock : Out std_logic;
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end ipif_control_wr ;
-------------------------------------------------------------------------------
architecture implementation of ipif_control_wr is
--FUNCTIONS
-----------------------------------------------------------------------------
-- Function set_fwidth
--
-- This function is used to set the value of FIFO width status
-- field based on the setting of the width parameter.
-----------------------------------------------------------------------------
function set_fwidth (fifo_width : integer) return integer is
constant byte_lane_num : Integer := (fifo_width+7)/8;
Variable enc_size : Integer := 0;
begin
case byte_lane_num is
when 0|1 =>
enc_size := 1;
when 2 =>
enc_size := 2;
when 3 | 4 =>
enc_size := 3;
when 5|6|7|8 =>
enc_size := 4;
When 9|10|11|12|13|14|15|16 =>
enc_size := 5;
when others =>
enc_size := 6;
end case;
return(enc_size);
end function set_fwidth;
--TYPES
-- no types
-- CONSTANTS
-- Module Software Reset key value for write data
Constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- This requires a Hex 'A' to be written
-- to activate the S/W reset port
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- Bus Width Matching constant
Constant ENC_FIFO_WIDTH : integer := set_fwidth(C_FIFO_WIDTH);
--INTERNAL SIGNALS
signal bus_data_out : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
--signal mir_value : std_logic_vector(0 to 31);
Signal sw_reset_error : std_logic;
signal reg_vacancy : std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Signal reg_almostfull : std_logic;
Signal reg_full : std_logic;
Signal reg_deadlock : std_logic;
Signal reg_rdce1 : std_logic;
Signal reg_rdce2 : std_logic;
Signal reg_rdce3 : std_logic;
Signal reg_wrce1 : std_logic;
Signal reg_wrce2 : std_logic;
Signal reg_wrce3 : std_logic;
Signal reg_wrreq : std_logic;
Signal reg_rdreq : std_logic;
Signal read_ack : std_logic;
Signal reg_read_ack : std_logic;
Signal write_ack : std_logic;
Signal rd_access_error : std_logic;
Signal wr_access_error : std_logic;
Signal burst_wr_xfer : std_logic;
Signal read_req : std_logic;
Signal reg_read_req : std_logic;
Signal write_req : std_logic;
Signal reg_write_req : std_logic;
Signal fifo_errack_inhibit : std_logic;
Signal rd_vect : std_logic_vector(0 to 3);
Signal sig_rst_match : std_logic;
Signal sig_rst_vect : std_logic_vector(0 to 1);
Signal sig_fifo_wr_data : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-------------------------------------------------------------------------------
--------------------- start architecture logic --------------------------------
begin
-- General access detection (used to terminate reply signal to the Bus)
read_req <= (Bus2FIFO_RdCE1 or Bus2FIFO_RdCE2 or Bus2FIFO_RdCE3);
write_req <= (Bus2FIFO_WrCE1 or Bus2FIFO_WrCE2 or Bus2FIFO_WrCE3);
-- I/O assignments
FIFO2Bus_DBus <= bus_data_out;
FIFO2Bus_ToutSup <= LOGIC_LOW;
-- This output signal not currently used so
-- drive it low.
FIFO2Bus_Retry <= LOGIC_LOW;
-- This output signal not currently used so
-- drive it low.
FIFO2Bus_WrAck <= write_ack and write_req;
-- Connect the write acknowledge (drive only if a
-- request is present)
FIFO2Bus_RdAck <= read_ack and read_req;
-- Connect the read acknowledge (drive only if
-- a request is present)
FIFO2Bus_Error <= (sw_reset_error or
rd_access_error or
wr_access_error) and
(read_req or write_req);
FIFO2IRPT_DeadLock <= Deadlock;
Fifo_WrReq <= Bus2FIFO_WrCE3 and Bus_WrReq;
-- Write Request to FIFO read controller
Fifo_burst_wr_xfer <= burst_wr_xfer;
-- Burst detect signal to FIFO read controller
sig_fifo_wr_data <= Bus_DBus;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- The FIFO data bus width is smaller than the IPIF data bus width so connect
-- the smaller FIFO data to LSB position of data bus to IPIF interface and
-- set the remaining data bus bits to zeroes.
-------------------------------------------------------------------------------
BUS_BIGGER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH > C_FIFO_WIDTH) generate
CONNECT_DBUS : process (sig_fifo_wr_data)
Begin
for j in 0 to C_FIFO_WIDTH-1 loop
fifo_wr_data(j) <= sig_fifo_wr_data(C_IPIF_DBUS_WIDTH-
C_FIFO_WIDTH+j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_BIGGER_THAN_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is equal to the IPIF data bus width so connect
-- the FIFO data to IPIF data interface.
-------------------------------------------------------------------------------
BUS_EQUAL_TO_FIFO : if (C_IPIF_DBUS_WIDTH = C_FIFO_WIDTH) generate
fifo_wr_data <= sig_fifo_wr_data;
end generate BUS_EQUAL_TO_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is bigger than the IPIF data bus width !!BAD!!!
-- Connect the LSBits of the FIFO data to the IPIF data bus interface,
-- Don't use (truncate) the MSBits of the FIFO data spilling over the IPIF
-- data bus width.
-------------------------------------------------------------------------------
BUS_SMALLER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH < C_FIFO_WIDTH) generate
CONNECT_DBUS : process (sig_fifo_wr_data)
Begin
fifo_wr_data <= (others => '0'); --default bus state
for j in C_IPIF_DBUS_WIDTH-1 downto 0 loop
fifo_wr_data(C_FIFO_WIDTH-C_IPIF_DBUS_WIDTH+j)
<= sig_fifo_wr_data(j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_SMALLER_THAN_FIFO;
------------------------------------------------------------------------------
-- Register the input chip enables
------------------------------------------------------------------------------
REGISTER_CHIP_ENABLES : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
reg_rdce1 <= '0';
reg_rdce2 <= '0';
reg_rdce3 <= '0';
reg_wrce1 <= '0';
reg_wrce2 <= '0';
reg_wrce3 <= '0';
reg_rdreq <= '0';
reg_wrreq <= '0';
reg_read_req <= '0';
reg_write_req <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
reg_rdce1 <= Bus2FIFO_RdCE1;
reg_rdce2 <= Bus2FIFO_RdCE2;
reg_rdce3 <= Bus2FIFO_RdCE3;
reg_wrce1 <= Bus2FIFO_WrCE1;
reg_wrce2 <= Bus2FIFO_WrCE2;
reg_wrce3 <= Bus2FIFO_WrCE3;
reg_rdreq <= Bus_RdReq;
reg_read_req <= read_req;
reg_wrreq <= Bus_WrReq;
reg_write_req <= write_req;
Else
null;
End if;
End process; -- REGISTER_CHIP_ENABLES
-------------------------------------------------------------------------------
-- Detect a Burst Write Condition (used for reading the FIFO Data)
-------------------------------------------------------------------------------
BURST_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
burst_wr_xfer <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (reg_wrreq = '1' and Bus_WrReq = '1') Then
burst_wr_xfer <= '1';
Elsif (burst_wr_xfer = '1' and Bus_WrReq = '0') Then
burst_wr_xfer <= '0';
else
burst_wr_xfer <= '0';
End if;
else
null;
End if;
End process; -- BURST_DETECT
-------------------------------------------------------------------------------
-- Assemble and latch the FIFO status register fields
-------------------------------------------------------------------------------
GET_STATUS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
reg_vacancy <= (others => '0');
reg_deadlock <= '0';
reg_almostfull <= '0';
reg_full <= '1';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (reg_rdce2 = '1') Then -- hold last value registered during read
-- operation.
null;
else -- register new status every clock
reg_vacancy <= Vacancy ;
reg_deadlock <= Deadlock ;
reg_almostfull <= AlmostFull ;
reg_full <= Full ;
End if;
else
null; -- do nothing
End if;
End process; -- GET_STATUS
sig_rst_match <= Bus_DBus(C_IPIF_DBUS_WIDTH-4)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-3))
and Bus_DBus(C_IPIF_DBUS_WIDTH-2)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-1));
sig_rst_vect <= sig_rst_match & Bus2FIFO_WrCE1;
------------------------------------------------------------------------------
-- Generate the S/W reset as a result of an IPIF Bus write to register
-- port 1 and data on the DBus inputs matching the Reset match value.
------------------------------------------------------------------------------
GENERATE_SOFTWARE_RESET : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
FIFO_Reset <= '1';
sw_reset_error <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
Case sig_rst_vect Is
When "11" =>
FIFO_Reset <= '1';
sw_reset_error <= '0';
When "01" =>
FIFO_Reset <= '0';
sw_reset_error <= '1';
When others =>
FIFO_Reset <= '0';
sw_reset_error <= '0';
End case;
Else
null;
End if;
End process; -- GENERATE_SOFTWARE_RESET
-- Synthesis for MIR inclusion ------------------------------------------------
Include_MIR :if (C_MIR_ENABLE = True) generate
signal mir_value : std_logic_vector(0 to 31);
Signal mir_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
-------------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics and Constants
-- conversion to std_logic_vector required
-------------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MAJOR, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MINOR, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_VERSION_REV, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_BLOCK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_INTFC_TYPE, 8);
-------------------------------------------------------------------------
-- If the IPIF read data bus width is less than or equal to the MIR value
-- size (32bits), then populate the LS MIR bits that will fit. Truncate
-- those that will not fit.
-------------------------------------------------------------------------
BUS_LEQ_32 : if (C_IPIF_DBUS_WIDTH <= 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
for j in 0 to (C_IPIF_DBUS_WIDTH-1) loop
mir_bus(j) <= mir_value((32-C_IPIF_DBUS_WIDTH)+j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_LEQ_32;
-------------------------------------------------------------------------
-- If the IPIF read data bus width is greater than the MIR value size
-- (32bits), then populate the MIR bits into the LSBits of the bus
-- and zero the remaining MSBits
-------------------------------------------------------------------------
BUS_GT_32 : if (C_IPIF_DBUS_WIDTH > 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
mir_bus <= (others => '0'); -- default bus values
for j in 0 to 31 loop
mir_bus((C_IPIF_DBUS_WIDTH-32)+j) <= mir_value(j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_GT_32;
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(C_IPIF_DBUS_WIDTH-28 to C_IPIF_DBUS_WIDTH-26)
-- <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- occupancy is not scaled
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostfull;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(4 to 6) <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- Set Vacancy is not scaled in this case.
status_bus(3) <= '0';
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull ;
status_bus(0) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the vacancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(4 to 6) <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- Set Vacancy is scaled in this case.
status_bus(3) <= '1';
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull;
status_bus(0) <= reg_full ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, mir_bus, status_bus,
rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1001" => -- Read MIR port
bus_data_out <= mir_bus;
When "1010" => -- Read Status port
bus_data_out <= status_bus;
When others => -- default to zeroes
bus_data_out <= (others => '0');
End case;
End process; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (Bus2FIFO_RdCE3 = '1') Then -- attempting a read of the FIFO
-- data through the data write
rd_access_error <= '1'; -- port. This is always an error.
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Include_MIR;
-- Synthesis for MIR occlusion ------------------------------------------------
Occlude_MIR : if (C_MIR_ENABLE = False) generate
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- If the IPIF DBUS is larger than 32 bits in width, place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
-- occupancy is not scaled
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostfull ;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- If the IPIF DBUS is less than or equal to 32 bits wide and is of sufficient
-- width to contain the complete status informatio, then.....
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '0' ; -- occupancy is not scaled
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull ;
status_bus(0) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the vacancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '1' ;
-- occupancy is scaled to fit
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull;
status_bus(0) <= reg_full ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the two read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, status_bus,
rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1010" =>
bus_data_out <= status_bus;
When others =>
bus_data_out <= (others => '0');
End case;
End process; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE1 = '1') Then -- attempting to read the MIR but it
-- is not included
rd_access_error <= '1';
Elsif (Bus2FIFO_RdCE3 = '1') Then -- attempting a read of the FIFO
rd_access_error <= '1'; -- data through the data write
-- port. This is always an error.
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Occlude_MIR;
-------------------------------------------------------------------------------
-- Generate the Read Acknowledge to the Bus
-------------------------------------------------------------------------------
GEN_READ_ACK : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
reg_read_ack <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (Bus2FIFO_RdCE1 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE2 = '1' ) Then
reg_read_ack <= '1';
else
reg_read_ack <= '0';
End if;
Else
null;
End if;
End process; -- GEN_READ_ACK
read_ack <= reg_read_ack or rd_access_error;
write_ack <= reg_wrce1 or -- used for reset port write
wr_access_error or -- used for error ack on invalid
-- write ops
Fifo_WrAck ; -- The FIFO accepted the write data
-------------------------------------------------------------------------------
-- This process detects the completion of at least one valid FIFO data write
-- cycle during a burst write. An error ack is generated only if a data
-- write is initiated at the same time as the FIFO is FUll.
-------------------------------------------------------------------------------
GEN_ERRACK_INHIB : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
fifo_errack_inhibit <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1' ) Then
If (Bus2FIFO_WrCE3 = '1' and Fifo_WrAck = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_WrCE3 = '0') Then
fifo_errack_inhibit <= '0';
else
null;
End if;
else
null;
End if;
End process; -- GEN_ERRACK_INHIB
-------------------------------------------------------------------------------
-- Generate the Error Acknowledge Reply to the Bus when
-- an attempted access by the IPIF Local Bus is invalid
-------------------------------------------------------------------------------
GEN_WR_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
wr_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_WrCE3 = '1' and
Full = '1' and
fifo_errack_inhibit = '0') Then -- Initiating a fifo write during a
wr_access_error <= '1'; -- full condition, this is an error.
Elsif (Bus2FIFO_WrCE2 = '1') Then -- Attempting to write to the staus
-- register
wr_access_error <= '1';
Else
wr_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_WR_ERROR
end implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/dma_sg_cmp.vhd | 3 | 22459 | -------------------------------------------------------------------------------
-- $Id: dma_sg_cmp.vhd,v 1.6 2003/09/03 18:07:53 ostlerf Exp $
-------------------------------------------------------------------------------
-- Package with component declarations to support the DMA Scatter/Gather entity
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg_cmp.vhd
--
-- Description: Components instantiated within dma_sg are declared here.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- dma_sg_cmp.vhds
-- dma_sg_pkg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
--
-- FLO 01/30/03
-- ^^^^^^
-- Changed the dma_sg component to correspond to a changes made to the entity
-- when fixed DMASG as a 32-bit device.
-- ~~~~~~
--
-- FLO 03/02/03
-- ^^^^^^
-- Added signal DMA2Bus_MstLoc2Loc.
-- ~~~~~~
--
-- FLO 05/15/2003
-- ^^^^^^
-- Added generics C_DMA_SHORT_BURST_REMAINDER and C_DMA_BURST_SIZE
-- to the dma_sg component.
-- ~~~~~~
-- FLO 09/03/2003
-- ^^^^^^
-- Added the ld_arith_reg2 component.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.INTEGER_ARRAY_TYPE;
package dma_sg_cmp is
component dma_sg is
-- Four channel, 0123, simple sg tx rx coalesc.
generic (
C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
C_IPIF_ABUS_WIDTH : natural :=15;
C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
-- The time unit, in nanoseconds, that applies to
-- the Packet Wait Bound register. The specified value of this
-- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- simulations.
C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
: INTEGER_ARRAY_TYPE
:= ( 0, 1, 2, 3 );
-- The leftmost defined bit of the LENGTH field, assuming
-- big endian bit numbering and a LSB at bit 31.
-- If the channel is a packet channel, it is assumed that
-- the number bits defined in the LENGTH register is also
-- enough bits to hold the length of a maximum sized packet.
-- ToDo, current impl requires all channels to be the same length.
C_DMA_LENGTH_WIDTH
: INTEGER_ARRAY_TYPE
:= ( 11, 11, 11, 11 );
C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 3)
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3800",
X"0000_0000_0000_4800" );
C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 3)
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3804",
X"0000_0000_0000_4804" );
C_INTR_COALESCE
: INTEGER_ARRAY_TYPE
:= ( 0, 0, 1, 1 );
C_DEV_BLK_ID : integer := 0;
C_DMA_BASEADDR : std_logic_vector
:= X"0000_0000_0000_0000";
C_DMA_BURST_SIZE : positive := 16; -- Must be a power of 2
C_DMA_SHORT_BURST_REMAINDER : integer := 0;
C_MA2SA_NUM_WIDTH : INTEGER := 8;
C_WFIFO_VACANCY_WIDTH : integer := 10
);
-- Two channel, 23, tx rx coalesc.
-- generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 10000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 2, 3 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1800",
-- X"0000_0000_0000_2800" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1804",
-- X"0000_0000_0000_2804" );
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 1, 1 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_BURST_SIZE : positive := 16; -- Must be a power of 2
--
-- C_USE_SHORT_BURST_FOR_REMAINDER: boolean := false;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
-- Two channel, 00, simple DMA only
--generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_BURST_SIZE : positive := 16; -- Must be a power of 2
--
-- C_USE_SHORT_BURST_FOR_REMAINDER: boolean := false;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
-- Three channel, 000, simple DMA only
--generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0, 0 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0, 0 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_BURST_SIZE : positive := 16; -- Must be a power of 2
--
-- C_USE_SHORT_BURST_FOR_REMAINDER: boolean := false;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
-- One channel version. (under construction)
--generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 2, 3 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1800", X"0000_0000_0000_2800" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1804", X"0000_0000_0000_2804" );
--
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 1, 1 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_BURST_SIZE : positive := 16; -- Must be a power of 2
--
-- C_USE_SHORT_BURST_FOR_REMAINDER: boolean := false;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
port (
DMA2Bus_Data : out std_logic_vector(0 to 31);
DMA2Bus_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1 );
DMA2Bus_MstBE : out std_logic_vector(0 to C_OPB_DWIDTH/8 - 1);
DMA2Bus_MstWrReq : out std_logic;
DMA2Bus_MstRdReq : out std_logic;
DMA2Bus_MstNum : out std_logic_vector(
0 to C_MA2SA_NUM_WIDTH-1);
DMA2Bus_MstBurst : out std_logic;
DMA2Bus_MstBusLock : out std_logic;
DMA2Bus_MstLoc2Loc : out std_logic;
DMA2IP_Addr : out std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
DMA2Bus_WrAck : out std_logic;
DMA2Bus_RdAck : out std_logic;
DMA2Bus_Retry : out std_logic;
DMA2Bus_Error : out std_logic;
DMA2Bus_ToutSup : out std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Mstr_sel_ma : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to 3);
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Freeze : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_Burst : in std_logic;
WFIFO2DMA_Vacancy : in std_logic_vector(0 to C_WFIFO_VACANCY_WIDTH-1);
Bus2IP_MstLastAck : in std_logic;
DMA_RdCE : in std_logic;
DMA_WrCE : in std_logic;
IP2DMA_RxStatus_Empty : in std_logic;
IP2DMA_RxLength_Empty : in std_logic;
IP2DMA_TxStatus_Empty : in std_logic;
IP2DMA_TxLength_Full : in std_logic;
IP2Bus_DMA_Req : in std_logic;
Bus2IP_DMA_Ack : out std_logic;
DMA2Intr_Intr : out std_logic_vector(0 to 1)
);
end component;
component ctrl_reg_0_to_6
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector(0 to 6);
q : out std_logic_vector(0 to 6)
);
end component;
component ctrl_reg_0_to_0
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
-- XGR_E33 d : in std_logic_vector(0 to 0);
-- XGR_E33 q : out std_logic_vector(0 to 0)
d : in std_logic;
q : out std_logic
);
end component;
component SRL_FIFO
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end component;
component ld_arith_reg
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset to left (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset to left of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end component;
component ld_arith_reg2
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end component;
component burst_size_calc is
generic (
C_LENGTH_WIDTH : positive := 11;
C_MSTNUM_WIDTH : positive := 5;
C_DMA_BURST_SIZE : positive := 16;
C_BYTES_PER_SINGLE_TRANSFER : positive := 4;
C_DMA_SHORT_BURST_REMAINDER : integer := 0
);
port (
Bus2IP_Clk : in std_logic;
LENGTH_cco : in std_logic_vector(0 to C_LENGTH_WIDTH-1);
PLENGTH_cco : in std_logic_vector(0 to C_LENGTH_WIDTH-1);
Rx_cco : in std_logic;
MstNum : out std_logic_vector(0 to C_MSTNUM_WIDTH-1)
);
end component burst_size_calc;
end package;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_dpram_select.vhd | 3 | 115123 | -------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1 2003/03/15 01:05:27 ostlerf Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/03/15 01:05:27 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/ipif_common_v1_00_d/hdl/vhdl/interrupt_control.vhd | 3 | 37168 | -------------------------------------------------------------------------------
-- $Id: interrupt_control.vhd,v 1.2 2003/05/07 22:45:11 ostlerf Exp $
-------------------------------------------------------------------------------
--interrupt_control.vhd version v1.00b
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- need 'conv_std_logic_vector' conversion function
library proc_common_v1_00_b;
Use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
use ipif_common_v1_00_d.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_INTERRUPT_REG_NUM : INTEGER := 16;
-- Number of IPIF Interrupt sources (not including IP or the
-- two latched IPIF ISR inputs)
C_NUM_IPIF_IRPT_SRC : INTEGER := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2, -- pass through (inverting)
3, -- registered level (non-inverting)
4, -- registered level (inverting)
5, -- positive edge detect
6 -- negative edge detect
);
C_INCLUDE_DEV_PENCODER : BOOLEAN := true;-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : Boolean := true; -- Specifies device ISC hierarchy
--Exclusion of Device ISC requires exclusion of Priority encoder
C_IRPT_DBUS_WIDTH : INTEGER := 32
);
port(
-- Inputs From the IPIF Bus
Bus2IP_Clk_i : In std_logic; -- Master timing clock from the IPIF
Bus2IP_Data_sa : In std_logic_vector(0 to C_IRPT_DBUS_WIDTH-1);
Bus2IP_RdReq_sa : In std_logic;
Bus2IP_Reset_i : In std_logic; -- Master Reset from the IPIF reset block
Bus2IP_WrReq_sa : In std_logic;
Interrupt_RdCE : In std_logic_vector(0 to C_INTERRUPT_REG_NUM-1);
Interrupt_WrCE : In std_logic_vector(0 to C_INTERRUPT_REG_NUM-1);
IPIF_Reg_Interrupts : In std_logic_vector(0 to 1);
-- Interrupt inputs from the IPIF sources that will get registered in this design
IPIF_Lvl_Interrupts : In std_logic_vector(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Level Interrupt inputs from the IPIF sources
-- Inputs from the IP Interface
IP2Bus_IntrEvent : In std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Interrupt inputs from the IP
-- Final Device Interrupt Output
Intr2Bus_DevIntr : Out std_logic;
-- Device interrupt output to the Master Interrupt Controller
-- Status Reply Outputs to the Bus
Intr2Bus_DBus : Out std_logic_vector(0 to C_IRPT_DBUS_WIDTH-1);
Intr2Bus_WrAck : Out std_logic;
Intr2Bus_RdAck : Out std_logic;
Intr2Bus_Error : Out std_logic;
Intr2Bus_Retry : Out std_logic;
Intr2Bus_ToutSup : Out std_logic
);
end interrupt_control ;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
--TYPES
-- no Types
-- CONSTANTS
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer range 0 to 15 := 0;
Constant DEVICE_IPR : integer range 0 to 15 := 1;
Constant DEVICE_IER : integer range 0 to 15 := 2;
Constant DEVICE_IAR : integer range 0 to 15 := 3;
Constant DEVICE_SIE : integer range 0 to 15 := 4;
Constant DEVICE_CIE : integer range 0 to 15 := 5;
Constant DEVICE_IIR : integer range 0 to 15 := 6;
Constant DEVICE_GIE : integer range 0 to 15 := 7;
Constant IP_ISR : integer range 0 to 15 := 8;
Constant IP_IPR : integer range 0 to 15 := 9;
Constant IP_IER : integer range 0 to 15 := 10;
Constant IP_IAR : integer range 0 to 15 := 11;
Constant IP_SIE : integer range 0 to 15 := 12;
Constant IP_CIE : integer range 0 to 15 := 13;
Constant IP_IIR : integer range 0 to 15 := 14;
Constant IP_GIE : integer range 0 to 15 := 15;
-- Generic to constant mapping
Constant IRPT_DBUS_WIDTH : Integer := C_IRPT_DBUS_WIDTH - 1;
Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
--INTERNAL SIGNALS
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector(IRPT_DBUS_WIDTH downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector(PRIORITY_ENC_WIDTH-1 downto 0);
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start architecture logic -------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_RdAck <= irpt_rdack;
Intr2Bus_WrAck <= irpt_wrack;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to IRPT_DBUS_WIDTH loop
Intr2Bus_DBus(IRPT_DBUS_WIDTH-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk_i)
begin
If (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk_i)
begin
If (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1') Then -- toggle selected ISR bits from the DBus inputs
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data_sa(IRPT_DBUS_WIDTH-irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1') Then -- load input data from the DBus inputs
ip_irpt_enable_reg <= Bus2IP_Data_sa(IRPT_DBUS_WIDTH-IP_IRPT_HIGH_INDEX
to IRPT_DBUS_WIDTH);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1') Then -- load input data from the DBus inputs
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= (Bus2IP_Data_sa(IRPT_DBUS_WIDTH-i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1') Then -- load input data from the DBus inputs
ipif_irpt_enable_reg <= Bus2IP_Data_sa(IRPT_DBUS_WIDTH-IPIF_IRPT_HIGH_INDEX to IRPT_DBUS_WIDTH);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1') Then -- load input data from the DBus inputs
ipif_glbl_irpt_enable_reg <= Bus2IP_Data_sa(0);
-- Enable bit is loaded from the DBus MSB
--Placed at bit-0 MSB by Glenn Baxter
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= conv_std_logic_vector(irpt_position, PRIORITY_ENC_WIDTH);
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= conv_std_logic_vector(NO_INTR_VALUE, PRIORITY_ENC_WIDTH);
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE)
Begin
irpt_wrack <= Interrupt_WrCE(DEVICE_ISR) or
Interrupt_WrCE(DEVICE_IER) or
Interrupt_WrCE(DEVICE_GIE) or
Interrupt_WrCE(IP_ISR) or
Interrupt_WrCE(IP_IER);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE)
Begin
irpt_wrack <= Interrupt_WrCE(DEVICE_GIE) or
Interrupt_WrCE(IP_ISR) or
Interrupt_WrCE(IP_IER);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1') Then
irpt_read_data(PRIORITY_ENC_WIDTH-1 downto 0) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_rdack <= ipif_pri_encode_present; -- set the acknowledge handshake depending on
-- priority encoder presence
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1') Then
irpt_read_data(IRPT_DBUS_WIDTH) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1') Then
irpt_read_data(IRPT_DBUS_WIDTH) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/plb_thread_manager_v1_00_a/hdl/vhdl/plb_thread_manager.vhd | 9 | 24206 | ------------------------------------------------------------------------------
-- plb_thread_manager.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_thread_manager.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Apr 14 15:01:53 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plb_thread_manager_v1_00_a;
use plb_thread_manager_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity plb_thread_manager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_RESET_TIMEOUT : natural := 4096
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- DO NOT EDIT ABOVE THIS LINE ---------------------
Access_Intr : out std_logic;
Scheduler_Reset : out std_logic;
Scheduler_Reset_Done : in std_logic;
Semaphore_Reset : out std_logic;
Semaphore_Reset_Done : in std_logic;
SpinLock_Reset : out std_logic;
SpinLock_Reset_Done : in std_logic;
User_IP_Reset : out std_logic;
User_IP_Reset_Done : in std_logic;
Soft_Stop : out std_logic;
tm2sch_cpu_thread_id : out std_logic_vector(0 to 7);
tm2sch_opcode : out std_logic_vector(0 to 5);
tm2sch_data : out std_logic_vector(0 to 7);
tm2sch_request : out std_logic;
tm2sch_DOB : out std_logic_vector(0 to 31);
sch2tm_ADDRB : in std_logic_vector(0 to 8);
sch2tm_DIB : in std_logic_vector(0 to 31);
sch2tm_ENB : in std_logic;
sch2tm_WEB : in std_logic;
sch2tm_busy : in std_logic;
sch2tm_data : in std_logic_vector(0 to 7);
sch2tm_next_id : in std_logic_vector(0 to 7);
sch2tm_next_id_valid : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity plb_thread_manager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_thread_manager is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_thread_manager_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_RESET_TIMEOUT => C_RESET_TIMEOUT
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
Access_Intr => Access_Intr,
Scheduler_Reset => Scheduler_Reset,
Scheduler_Reset_Done => Scheduler_Reset_Done,
Semaphore_Reset => Semaphore_Reset,
Semaphore_Reset_Done => Semaphore_Reset_Done,
SpinLock_Reset => SpinLock_Reset,
SpinLock_Reset_Done => SpinLock_Reset_Done,
User_IP_Reset => User_IP_Reset,
User_IP_Reset_Done => User_IP_Reset_Done,
Soft_Stop => Soft_Stop,
tm2sch_cpu_thread_id => tm2sch_cpu_thread_id,
tm2sch_opcode => tm2sch_opcode,
tm2sch_data => tm2sch_data,
tm2sch_request => tm2sch_request,
tm2sch_DOB => tm2sch_DOB,
sch2tm_ADDRB => sch2tm_ADDRB,
sch2tm_DIB => sch2tm_DIB,
sch2tm_ENB => sch2tm_ENB,
sch2tm_WEB => sch2tm_WEB,
sch2tm_busy => sch2tm_busy,
sch2tm_data => sch2tm_data,
sch2tm_next_id => sch2tm_next_id,
sch2tm_next_id_valid => sch2tm_next_id_valid
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/XilinxProcessorIP/pcores/opb_ac97_v1_00_a/hdl/vhdl/opb_ac97.vhd | 4 | 10259 | -------------------------------------------------------------------------------
-- $Id: opb_ac97.vhd,v 1.1 2005/02/17 20:29:35 crh Exp $
-------------------------------------------------------------------------------
-- opb_ac97.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: opb_ac97
--
-- Description: Provides an OPB interface to the ac97 fifo controller
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_fifo
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity opb_ac97 is
generic (
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_8000";
C_HIGHADDR : std_logic_vector := X"FFFF_80FF";
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
-- C_GPOUT_DWIDTH : integer := 1;
-- value of 0,1,2,3,4
-- 0 = No Interrupt
-- 1 = empty
-- 2 = halfempty
-- 3 = halffull
-- 4 = full
C_INTR_LEVEL : integer := 1;
C_USE_BRAM : integer := 1
);
port (
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_Clk : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_Rst : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Sln_xferAck : out std_logic;
-- GPIO signals (Beep, reset, etc.)
-- AC97_GPOUT : out std_logic_vector(0 to C_GPOUT_DWIDTH-1);
-- Interrupt signals
Interrupt : out std_logic;
-- CODEC signals
Bit_Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic;
AC97Reset_n : out std_logic
);
attribute MIN_SIZE : string;
attribute MIN_SIZE of C_BASEADDR : constant is "0x100";
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_ac97;
-- library proc_common_v1_00_b;
-- use proc_common_v1_00_b.proc_common_pkg.all;
-- library ipif_common_v1_00_c;
-- use ipif_common_v1_00_c.ipif_pkg.all;
-- library opb_ipif_v3_00_a;
-- use opb_ipif_v3_00_a.all;
library Common_v1_00_a;
use Common_v1_00_a.pselect;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
library unisim;
use unisim.all;
architecture IMP of opb_ac97 is
component ac97_fifo is
generic (
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLAYBACK : integer := 1;
C_RECORD : integer := 0;
C_INTR_LEVEL : integer := 1;
C_USE_BRAM : integer := 1
);
port (
-- IP Interface
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
Interrupt: out std_logic;
-- CODEC signals
Bit_Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic;
AC97Reset_n : out std_logic
);
end component ac97_fifo;
component FDR is
port (Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component pselect is
generic (
C_AB : integer;
C_AW : integer;
C_BAR : std_logic_vector);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
ps : out std_logic);
end component pselect;
function Addr_Bits (x, y : std_logic_vector(0 to C_OPB_AWIDTH-1)) return integer is
variable addr_nor : std_logic_vector(0 to C_OPB_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_OPB_AWIDTH-1 loop
if addr_nor(i) = '1' then return i;
end if;
end loop;
return(C_OPB_AWIDTH);
end function Addr_Bits;
constant C_AB : integer := Addr_Bits(C_HIGHADDR, C_BASEADDR);
signal ac97_CS : std_logic;
signal ac97_CS_1 : std_logic; -- Active as long as AC97_CS is active
signal ac97_CS_2 : std_logic; -- Active only 1 clock cycle during an
signal ac97_CS_3 : std_logic; -- Active only 1 clock cycle during an
signal xfer_Ack : std_logic;
signal opb_RNW_1 : std_logic;
signal opb_rdce : std_logic;
signal opb_wrce : std_logic;
signal iSln_DBus : std_logic_vector(0 to 31);
signal interrupt_i : std_logic;
begin
Interrupt <= interrupt_i;
-- Do the OPB address decoding
pselect_I : pselect
generic map (
C_AB => C_AB, -- [integer]
C_AW => C_OPB_AWIDTH, -- [integer]
C_BAR => C_BASEADDR) -- [std_logic_vector]
port map (
A => OPB_ABus, -- [in std_logic_vector(0 to C_AW-1)]
AValid => OPB_select, -- [in std_logic]
ps => ac97_CS); -- [out std_logic]
ac97_CS_1_DFF : FDR
port map (
Q => ac97_CS_1, -- [out std_logic]
C => OPB_Clk, -- [in std_logic]
D => ac97_CS, -- [in std_logic]
R => xfer_Ack); -- [in std_logic]
ac97_CS_2_DFF: process (OPB_Clk, OPB_Rst) is
begin -- process uart_CS_2_DFF
if OPB_Rst = '1' then -- asynchronous reset (active high)
ac97_CS_2 <= '0';
ac97_CS_3 <= '0';
opb_RNW_1 <= '0';
elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge
ac97_CS_2 <= ac97_CS_1 and not ac97_CS_2 and not ac97_CS_3;
ac97_CS_3 <= ac97_CS_2;
opb_RNW_1 <= OPB_RNW;
end if;
end process ac97_CS_2_DFF;
opb_rdce <= ac97_CS_2 and OPB_RNW_1;
opb_wrce <= ac97_CS_2 and (not OPB_RNW_1);
XFER_Control : process (OPB_Clk, OPB_Rst) is
begin -- process XFER_Control
if OPB_Rst = '1' then -- asynchronous reset (active high)
xfer_Ack <= '0';
elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge
xfer_Ack <= ac97_CS_2;
end if;
end process XFER_Control;
Sln_errAck <= '0';
Sln_retry <= '0';
Sln_toutSup <= '0';
sln_xferAck <= xfer_Ack;
OPB_rdDBus_DFF : for I in iSln_DBus'range generate
OPB_rdBus_FDRE : FDRE
port map (
Q => Sln_DBus(I), -- [out std_logic]
C => OPB_Clk, -- [in std_logic]
CE => ac97_CS_2, -- [in std_logic]
D => iSln_Dbus(I), -- [in std_logic]
R => xfer_Ack); -- [in std_logic]
end generate OPB_rdDBus_DFF;
AC97_FIFO_I : ac97_fifo
generic map (
C_PLAYBACK => C_PLAYBACK,
C_RECORD => C_RECORD,
C_INTR_LEVEL => C_INTR_LEVEL,
C_USE_BRAM => C_USE_BRAM
)
port map (
-- IP Interface
Bus2IP_Clk => OPB_Clk,
Bus2IP_Reset => OPB_Rst,
Bus2IP_Addr => OPB_ABus,
Bus2IP_Data => OPB_Dbus,
Bus2IP_BE => OPB_BE,
Bus2IP_RdCE => opb_rdce,
Bus2IP_WrCE => opb_wrce,
IP2Bus_Data => iSln_DBus,
Interrupt => interrupt_i,
-- CODEC signals
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In,
AC97Reset_n => AC97Reset_n
);
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/test/reconos/out.vhd | 2 | 82715 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
--use work.common.all;
ENTITY user_logic_hwtul IS
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
END ENTITY user_logic_hwtul;
ARCHITECTURE IMP OF user_logic_hwtul IS
-- HWTI Declarations.
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESSOF : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
-- STATE DECLARATIONS
constant START_STATE : std_logic_vector(0 to 15) := x"0004";
constant WAIT_STATE : std_logic_vector(0 to 15) := x"0005";
constant FUNCTCALL_STATE : std_logic_vector(0 to 15) := x"0006";
constant BOOTSTRAP0 : std_logic_vector(0 to 15) := x"0007";
constant BOOTSTRAP1 : std_logic_vector(0 to 15) := x"0008";
constant mailbox_write_start : std_logic_vector(0 to 15) := x"0009";
constant mailbox_write_save_0 : std_logic_vector(0 to 15) := x"000A";
constant mailbox_write_save_1 : std_logic_vector(0 to 15) := x"000B";
constant mailbox_write_save_2 : std_logic_vector(0 to 15) := x"000C";
constant mailbox_write_save_3 : std_logic_vector(0 to 15) := x"000D";
constant mailbox_write_save_4 : std_logic_vector(0 to 15) := x"000E";
constant mailbox_write_15_0_0 : std_logic_vector(0 to 15) := x"000F";
constant mailbox_write_15_0_1 : std_logic_vector(0 to 15) := x"0010";
constant mailbox_write_15_1_0 : std_logic_vector(0 to 15) := x"0011";
constant mailbox_write_15_1_1 : std_logic_vector(0 to 15) := x"0012";
constant mailbox_write_15_2_0 : std_logic_vector(0 to 15) := x"0013";
constant mailbox_write_15_3_0 : std_logic_vector(0 to 15) := x"0014";
constant mailbox_write_15_4_0 : std_logic_vector(0 to 15) := x"0015";
constant mailbox_write_15_4_1 : std_logic_vector(0 to 15) := x"0016";
constant mailbox_write_15_4_2 : std_logic_vector(0 to 15) := x"0017";
constant mailbox_write_15_5_0 : std_logic_vector(0 to 15) := x"0018";
constant mailbox_write_15_5_1 : std_logic_vector(0 to 15) := x"0019";
constant mailbox_write_15_6_0 : std_logic_vector(0 to 15) := x"001A";
constant mailbox_write_15_6_1 : std_logic_vector(0 to 15) := x"001B";
constant mailbox_write_15_7_0 : std_logic_vector(0 to 15) := x"001C";
constant mailbox_write_16_0_0 : std_logic_vector(0 to 15) := x"001D";
constant mailbox_write_17_0_0 : std_logic_vector(0 to 15) := x"001E";
constant mailbox_write_18_0_0 : std_logic_vector(0 to 15) := x"001F";
constant mailbox_write_18_1_0 : std_logic_vector(0 to 15) := x"0020";
constant mailbox_write_18_1_1 : std_logic_vector(0 to 15) := x"0021";
constant mailbox_write_18_1_2 : std_logic_vector(0 to 15) := x"0022";
constant mailbox_write_18_1_3 : std_logic_vector(0 to 15) := x"0023";
constant mailbox_write_18_2_0 : std_logic_vector(0 to 15) := x"0024";
constant mailbox_write_18_2_1 : std_logic_vector(0 to 15) := x"0025";
constant mailbox_write_18_3_0 : std_logic_vector(0 to 15) := x"0026";
constant mailbox_write_18_4_0 : std_logic_vector(0 to 15) := x"0027";
constant mailbox_write_18_4_1 : std_logic_vector(0 to 15) := x"0028";
constant mailbox_write_18_5_0 : std_logic_vector(0 to 15) := x"0029";
constant mailbox_write_19_0_0 : std_logic_vector(0 to 15) := x"002A";
constant mailbox_write_20_0_0 : std_logic_vector(0 to 15) := x"002B";
constant mailbox_write_21_0_0 : std_logic_vector(0 to 15) := x"002C";
constant mailbox_write_21_0_1 : std_logic_vector(0 to 15) := x"002D";
constant mailbox_write_21_1_0 : std_logic_vector(0 to 15) := x"002E";
constant mailbox_write_21_2_0 : std_logic_vector(0 to 15) := x"002F";
constant mailbox_write_21_2_1 : std_logic_vector(0 to 15) := x"0030";
constant mailbox_write_21_3_0 : std_logic_vector(0 to 15) := x"0031";
constant mailbox_write_21_3_1 : std_logic_vector(0 to 15) := x"0032";
constant mailbox_write_21_4_0 : std_logic_vector(0 to 15) := x"0033";
constant mailbox_write_21_5_0 : std_logic_vector(0 to 15) := x"0034";
constant mailbox_write_21_6_0 : std_logic_vector(0 to 15) := x"0035";
constant mailbox_write_21_7_0 : std_logic_vector(0 to 15) := x"0036";
constant mailbox_write_21_7_1 : std_logic_vector(0 to 15) := x"0037";
constant mailbox_write_21_8_0 : std_logic_vector(0 to 15) := x"0038";
constant mailbox_write_21_9_0 : std_logic_vector(0 to 15) := x"0039";
constant mailbox_write_21_9_1 : std_logic_vector(0 to 15) := x"003A";
constant mailbox_write_21_10_0 : std_logic_vector(0 to 15) := x"003B";
constant mailbox_write_21_10_1 : std_logic_vector(0 to 15) := x"003C";
constant mailbox_write_21_11_0 : std_logic_vector(0 to 15) := x"003D";
constant mailbox_write_21_12_0 : std_logic_vector(0 to 15) := x"003E";
constant mailbox_write_21_12_1 : std_logic_vector(0 to 15) := x"003F";
constant mailbox_write_21_13_0 : std_logic_vector(0 to 15) := x"0040";
constant mailbox_write_21_14_0 : std_logic_vector(0 to 15) := x"0041";
constant mailbox_write_21_15_0 : std_logic_vector(0 to 15) := x"0042";
constant mailbox_write_21_15_1 : std_logic_vector(0 to 15) := x"0043";
constant mailbox_write_21_15_2 : std_logic_vector(0 to 15) := x"0044";
constant mailbox_write_21_16_0 : std_logic_vector(0 to 15) := x"0045";
constant mailbox_write_21_17_0 : std_logic_vector(0 to 15) := x"0046";
constant mailbox_write_21_17_1 : std_logic_vector(0 to 15) := x"0047";
constant mailbox_write_21_17_2 : std_logic_vector(0 to 15) := x"0048";
constant mailbox_write_21_18_0 : std_logic_vector(0 to 15) := x"0049";
constant mailbox_write_restore_0 : std_logic_vector(0 to 15) := x"004A";
constant mailbox_write_restore_1 : std_logic_vector(0 to 15) := x"004B";
constant mailbox_write_restore_2 : std_logic_vector(0 to 15) := x"004C";
constant mailbox_write_restore_3 : std_logic_vector(0 to 15) := x"004D";
constant mailbox_write_restore_4 : std_logic_vector(0 to 15) := x"004E";
constant mailbox_write_end : std_logic_vector(0 to 15) := x"004F";
constant bubblesort_start : std_logic_vector(0 to 15) := x"0050";
constant bubblesort_save_0 : std_logic_vector(0 to 15) := x"0051";
constant bubblesort_save_1 : std_logic_vector(0 to 15) := x"0052";
constant bubblesort_save_2 : std_logic_vector(0 to 15) := x"0053";
constant bubblesort_save_3 : std_logic_vector(0 to 15) := x"0054";
constant bubblesort_save_4 : std_logic_vector(0 to 15) := x"0055";
constant bubblesort_save_5 : std_logic_vector(0 to 15) := x"0056";
constant bubblesort_save_6 : std_logic_vector(0 to 15) := x"0057";
constant bubblesort_save_7 : std_logic_vector(0 to 15) := x"0058";
constant bubblesort_save_8 : std_logic_vector(0 to 15) := x"0059";
constant bubblesort_0_0_0 : std_logic_vector(0 to 15) := x"005A";
constant bubblesort_0_0_1 : std_logic_vector(0 to 15) := x"005B";
constant bubblesort_0_1_0 : std_logic_vector(0 to 15) := x"005C";
constant bubblesort_0_1_1 : std_logic_vector(0 to 15) := x"005D";
constant bubblesort_0_2_0 : std_logic_vector(0 to 15) := x"005E";
constant bubblesort_0_3_0 : std_logic_vector(0 to 15) := x"005F";
constant bubblesort_0_4_0 : std_logic_vector(0 to 15) := x"0060";
constant bubblesort_0_5_0 : std_logic_vector(0 to 15) := x"0061";
constant bubblesort_0_6_0 : std_logic_vector(0 to 15) := x"0062";
constant bubblesort_1_0_0 : std_logic_vector(0 to 15) := x"0063";
constant bubblesort_1_0_1 : std_logic_vector(0 to 15) := x"0064";
constant bubblesort_1_1_0 : std_logic_vector(0 to 15) := x"0065";
constant bubblesort_1_2_0 : std_logic_vector(0 to 15) := x"0066";
constant bubblesort_1_3_0 : std_logic_vector(0 to 15) := x"0067";
constant bubblesort_1_3_1 : std_logic_vector(0 to 15) := x"0068";
constant bubblesort_1_4_0 : std_logic_vector(0 to 15) := x"0069";
constant bubblesort_1_5_0 : std_logic_vector(0 to 15) := x"006A";
constant bubblesort_1_6_0 : std_logic_vector(0 to 15) := x"006B";
constant bubblesort_1_7_0 : std_logic_vector(0 to 15) := x"006C";
constant bubblesort_1_8_0 : std_logic_vector(0 to 15) := x"006D";
constant bubblesort_1_8_1 : std_logic_vector(0 to 15) := x"006E";
constant bubblesort_1_9_0 : std_logic_vector(0 to 15) := x"006F";
constant bubblesort_2_0_0 : std_logic_vector(0 to 15) := x"0070";
constant bubblesort_3_0_0 : std_logic_vector(0 to 15) := x"0071";
constant bubblesort_4_0_0 : std_logic_vector(0 to 15) := x"0072";
constant bubblesort_4_1_0 : std_logic_vector(0 to 15) := x"0073";
constant bubblesort_4_2_0 : std_logic_vector(0 to 15) := x"0074";
constant bubblesort_4_3_0 : std_logic_vector(0 to 15) := x"0075";
constant bubblesort_4_4_0 : std_logic_vector(0 to 15) := x"0076";
constant bubblesort_5_0_0 : std_logic_vector(0 to 15) := x"0077";
constant bubblesort_6_0_0 : std_logic_vector(0 to 15) := x"0078";
constant bubblesort_7_0_0 : std_logic_vector(0 to 15) := x"0079";
constant bubblesort_8_0_0 : std_logic_vector(0 to 15) := x"007A";
constant bubblesort_9_0_0 : std_logic_vector(0 to 15) := x"007B";
constant bubblesort_10_0_0 : std_logic_vector(0 to 15) := x"007C";
constant bubblesort_11_0_0 : std_logic_vector(0 to 15) := x"007D";
constant bubblesort_12_0_0 : std_logic_vector(0 to 15) := x"007E";
constant bubblesort_12_1_0 : std_logic_vector(0 to 15) := x"007F";
constant bubblesort_12_2_0 : std_logic_vector(0 to 15) := x"0080";
constant bubblesort_12_3_0 : std_logic_vector(0 to 15) := x"0081";
constant bubblesort_13_0_0 : std_logic_vector(0 to 15) := x"0082";
constant bubblesort_restore_0 : std_logic_vector(0 to 15) := x"0083";
constant bubblesort_restore_1 : std_logic_vector(0 to 15) := x"0084";
constant bubblesort_restore_2 : std_logic_vector(0 to 15) := x"0085";
constant bubblesort_restore_3 : std_logic_vector(0 to 15) := x"0086";
constant bubblesort_restore_4 : std_logic_vector(0 to 15) := x"0087";
constant bubblesort_restore_5 : std_logic_vector(0 to 15) := x"0088";
constant bubblesort_restore_6 : std_logic_vector(0 to 15) := x"0089";
constant bubblesort_restore_7 : std_logic_vector(0 to 15) := x"008A";
constant bubblesort_restore_8 : std_logic_vector(0 to 15) := x"008B";
constant bubblesort_end : std_logic_vector(0 to 15) := x"008C";
constant mailbox_read_start : std_logic_vector(0 to 15) := x"008D";
constant mailbox_read_save_0 : std_logic_vector(0 to 15) := x"008E";
constant mailbox_read_save_1 : std_logic_vector(0 to 15) := x"008F";
constant mailbox_read_save_2 : std_logic_vector(0 to 15) := x"0090";
constant mailbox_read_save_3 : std_logic_vector(0 to 15) := x"0091";
constant mailbox_read_save_4 : std_logic_vector(0 to 15) := x"0092";
constant mailbox_read_23_0_0 : std_logic_vector(0 to 15) := x"0093";
constant mailbox_read_23_0_1 : std_logic_vector(0 to 15) := x"0094";
constant mailbox_read_23_1_0 : std_logic_vector(0 to 15) := x"0095";
constant mailbox_read_23_2_0 : std_logic_vector(0 to 15) := x"0096";
constant mailbox_read_23_3_0 : std_logic_vector(0 to 15) := x"0097";
constant mailbox_read_23_3_1 : std_logic_vector(0 to 15) := x"0098";
constant mailbox_read_23_3_2 : std_logic_vector(0 to 15) := x"0099";
constant mailbox_read_23_4_0 : std_logic_vector(0 to 15) := x"009A";
constant mailbox_read_23_4_1 : std_logic_vector(0 to 15) := x"009B";
constant mailbox_read_23_5_0 : std_logic_vector(0 to 15) := x"009C";
constant mailbox_read_24_0_0 : std_logic_vector(0 to 15) := x"009D";
constant mailbox_read_25_0_0 : std_logic_vector(0 to 15) := x"009E";
constant mailbox_read_26_0_0 : std_logic_vector(0 to 15) := x"009F";
constant mailbox_read_26_1_0 : std_logic_vector(0 to 15) := x"00A0";
constant mailbox_read_26_1_1 : std_logic_vector(0 to 15) := x"00A1";
constant mailbox_read_26_1_2 : std_logic_vector(0 to 15) := x"00A2";
constant mailbox_read_26_1_3 : std_logic_vector(0 to 15) := x"00A3";
constant mailbox_read_26_2_0 : std_logic_vector(0 to 15) := x"00A4";
constant mailbox_read_26_2_1 : std_logic_vector(0 to 15) := x"00A5";
constant mailbox_read_26_3_0 : std_logic_vector(0 to 15) := x"00A6";
constant mailbox_read_27_0_0 : std_logic_vector(0 to 15) := x"00A7";
constant mailbox_read_28_0_0 : std_logic_vector(0 to 15) := x"00A8";
constant mailbox_read_29_0_0 : std_logic_vector(0 to 15) := x"00A9";
constant mailbox_read_29_0_1 : std_logic_vector(0 to 15) := x"00AA";
constant mailbox_read_29_1_0 : std_logic_vector(0 to 15) := x"00AB";
constant mailbox_read_29_2_0 : std_logic_vector(0 to 15) := x"00AC";
constant mailbox_read_29_2_1 : std_logic_vector(0 to 15) := x"00AD";
constant mailbox_read_29_3_0 : std_logic_vector(0 to 15) := x"00AE";
constant mailbox_read_29_4_0 : std_logic_vector(0 to 15) := x"00AF";
constant mailbox_read_29_5_0 : std_logic_vector(0 to 15) := x"00B0";
constant mailbox_read_29_5_1 : std_logic_vector(0 to 15) := x"00B1";
constant mailbox_read_29_6_0 : std_logic_vector(0 to 15) := x"00B2";
constant mailbox_read_29_7_0 : std_logic_vector(0 to 15) := x"00B3";
constant mailbox_read_29_7_1 : std_logic_vector(0 to 15) := x"00B4";
constant mailbox_read_29_8_0 : std_logic_vector(0 to 15) := x"00B5";
constant mailbox_read_29_9_0 : std_logic_vector(0 to 15) := x"00B6";
constant mailbox_read_29_10_0 : std_logic_vector(0 to 15) := x"00B7";
constant mailbox_read_29_10_1 : std_logic_vector(0 to 15) := x"00B8";
constant mailbox_read_29_11_0 : std_logic_vector(0 to 15) := x"00B9";
constant mailbox_read_29_11_1 : std_logic_vector(0 to 15) := x"00BA";
constant mailbox_read_29_12_0 : std_logic_vector(0 to 15) := x"00BB";
constant mailbox_read_29_13_0 : std_logic_vector(0 to 15) := x"00BC";
constant mailbox_read_29_13_1 : std_logic_vector(0 to 15) := x"00BD";
constant mailbox_read_29_14_0 : std_logic_vector(0 to 15) := x"00BE";
constant mailbox_read_29_15_0 : std_logic_vector(0 to 15) := x"00BF";
constant mailbox_read_29_16_0 : std_logic_vector(0 to 15) := x"00C0";
constant mailbox_read_29_16_1 : std_logic_vector(0 to 15) := x"00C1";
constant mailbox_read_29_16_2 : std_logic_vector(0 to 15) := x"00C2";
constant mailbox_read_29_17_0 : std_logic_vector(0 to 15) := x"00C3";
constant mailbox_read_29_18_0 : std_logic_vector(0 to 15) := x"00C4";
constant mailbox_read_29_18_1 : std_logic_vector(0 to 15) := x"00C5";
constant mailbox_read_29_18_2 : std_logic_vector(0 to 15) := x"00C6";
constant mailbox_read_29_19_0 : std_logic_vector(0 to 15) := x"00C7";
constant mailbox_read_restore_0 : std_logic_vector(0 to 15) := x"00C8";
constant mailbox_read_restore_1 : std_logic_vector(0 to 15) := x"00C9";
constant mailbox_read_restore_2 : std_logic_vector(0 to 15) := x"00CA";
constant mailbox_read_restore_3 : std_logic_vector(0 to 15) := x"00CB";
constant mailbox_read_restore_4 : std_logic_vector(0 to 15) := x"00CC";
constant mailbox_read_end : std_logic_vector(0 to 15) := x"00CD";
constant sort8k_entry_start : std_logic_vector(0 to 15) := x"00CE";
constant sort8k_entry_save_0 : std_logic_vector(0 to 15) := x"00CF";
constant sort8k_entry_save_1 : std_logic_vector(0 to 15) := x"00D0";
constant sort8k_entry_31_0_0 : std_logic_vector(0 to 15) := x"00D1";
constant sort8k_entry_31_0_1 : std_logic_vector(0 to 15) := x"00D2";
constant sort8k_entry_31_1_0 : std_logic_vector(0 to 15) := x"00D3";
constant sort8k_entry_32_0_0 : std_logic_vector(0 to 15) := x"00D4";
constant sort8k_entry_32_1_0 : std_logic_vector(0 to 15) := x"00D5";
constant sort8k_entry_32_1_1 : std_logic_vector(0 to 15) := x"00D6";
constant sort8k_entry_32_1_2 : std_logic_vector(0 to 15) := x"00D7";
constant sort8k_entry_32_2_0 : std_logic_vector(0 to 15) := x"00D8";
constant sort8k_entry_32_2_1 : std_logic_vector(0 to 15) := x"00D9";
constant sort8k_entry_32_2_2 : std_logic_vector(0 to 15) := x"00DA";
constant sort8k_entry_32_2_3 : std_logic_vector(0 to 15) := x"00DB";
constant sort8k_entry_32_3_0 : std_logic_vector(0 to 15) := x"00DC";
constant sort8k_entry_32_4_0 : std_logic_vector(0 to 15) := x"00DD";
constant sort8k_entry_32_4_1 : std_logic_vector(0 to 15) := x"00DE";
constant sort8k_entry_32_4_2 : std_logic_vector(0 to 15) := x"00DF";
constant sort8k_entry_32_4_3 : std_logic_vector(0 to 15) := x"00E0";
constant sort8k_entry_32_5_0 : std_logic_vector(0 to 15) := x"00E1";
constant sort8k_entry_33_0_0 : std_logic_vector(0 to 15) := x"00E2";
constant sort8k_entry_restore_0 : std_logic_vector(0 to 15) := x"00E3";
constant sort8k_entry_restore_1 : std_logic_vector(0 to 15) := x"00E4";
constant sort8k_entry_end : std_logic_vector(0 to 15) := x"00E5";
constant MULT00 : std_logic_vector(0 to 15) := x"00E6";
constant MULT01 : std_logic_vector(0 to 15) := x"00E7";
constant MULT02 : std_logic_vector(0 to 15) := x"00E8";
constant DIVIDE00 : std_logic_vector(0 to 15) := x"00E9";
constant DIVIDE01 : std_logic_vector(0 to 15) := x"00EA";
constant DIVIDE02 : std_logic_vector(0 to 15) := x"00EB";
constant DIVIDE03 : std_logic_vector(0 to 15) := x"00EC";
constant DIVIDE04 : std_logic_vector(0 to 15) := x"00ED";
constant DIVIDE05 : std_logic_vector(0 to 15) := x"00EE";
-- REGISTER DECLARATIONS
-- Special purpose registers
signal curstate : std_logic_vector(0 to 15) := START_STATE;
signal returnstate : std_logic_vector(0 to 15) := WAIT_STATE;
signal returnVal : std_logic_vector(0 to 31) := x"00000000";
signal stack_mem : std_logic_vector(0 to 31) := x"00000000";
signal params_mem : std_logic_vector(0 to 31) := x"00000000";
-- Caller save registers
signal T1 : std_logic_vector(0 to 31) := x"00000000";
signal T2 : std_logic_vector(0 to 31) := x"00000000";
signal T3 : std_logic_vector(0 to 31) := x"00000000";
signal T4 : std_logic_vector(0 to 31) := x"00000000";
signal T5 : std_logic_vector(0 to 31) := x"00000000";
signal T6 : std_logic_vector(0 to 31) := x"00000000";
-- Callee save registers
signal R4 : std_logic_vector(0 to 31) := x"00000000";
signal R5 : std_logic_vector(0 to 31) := x"00000000";
signal R6 : std_logic_vector(0 to 31) := x"00000000";
signal R7 : std_logic_vector(0 to 31) := x"00000000";
signal R0 : std_logic_vector(0 to 31) := x"00000000";
signal R1 : std_logic_vector(0 to 31) := x"00000000";
signal R2 : std_logic_vector(0 to 31) := x"00000000";
signal R3 : std_logic_vector(0 to 31) := x"00000000";
signal R8 : std_logic_vector(0 to 31) := x"00000000";
BEGIN
state_mach : PROCESS
BEGIN
WAIT UNTIL rising_edge(clock);
IF (intrfc2thrd_goWait = '1') and (intrfc2thrd_function = U_FUNCTION_RESET) THEN
-- Reset event
thrd2intrfc_address <= x"00000000";
thrd2intrfc_value <= x"00000000";
thrd2intrfc_function <= x"0000";
thrd2intrfc_opcode <= "000000";
curstate <= START_STATE;
returnstate <= WAIT_STATE;
returnVal <= x"00000000";
stack_mem <= x"00000000";
params_mem <= x"00000000";
T1 <= x"00000000";
T2 <= x"00000000";
T3 <= x"00000000";
T4 <= x"00000000";
T5 <= x"00000000";
T6 <= x"00000000";
R4 <= x"00000000";
R5 <= x"00000000";
R6 <= x"00000000";
R7 <= x"00000000";
R0 <= x"00000000";
R1 <= x"00000000";
R2 <= x"00000000";
R3 <= x"00000000";
R8 <= x"00000000";
ELSE
IF (intrfc2thrd_goWait = '1') THEN
thrd2intrfc_opcode <= OPCODE_NOOP; --OPCODE IS NOOP BY DEFAULT
CASE curstate IS
-- Start loops while function code is "start"
WHEN START_STATE =>
IF intrfc2thrd_function = U_FUNCTION_START THEN
curstate <= START_STATE;
ELSE
curstate <= BOOTSTRAP0;
END IF;
WHEN BOOTSTRAP0 =>
-- Call addressof to get the stack_mem pointer value.
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_ADDRESSOF;
curstate <= WAIT_STATE;
returnstate <= BOOTSTRAP1;
WHEN BOOTSTRAP1 =>
-- Use the result of the addressof to set stack_mem and params_mem.
-- Also call the declare opcode to initialize the stack for the thread main function.
stack_mem <= intrfc2thrd_value;
params_mem <= intrfc2thrd_value - x"00000010";
thrd2intrfc_value <= x"00000002";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_31_0_0;
-- Begin of function mailbox_write (from mailbox_no_globals.c.hif)
WHEN mailbox_write_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000005";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_0;
WHEN mailbox_write_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_1;
WHEN mailbox_write_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_2;
WHEN mailbox_write_save_2 =>
-- Save register R2 on the stack.
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_3;
WHEN mailbox_write_save_3 =>
-- Save register R3 on the stack.
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_4;
WHEN mailbox_write_save_4 =>
-- Save register R4 on the stack.
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_value <= R4;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_0_0;
WHEN mailbox_write_15_0_0 =>
-- arith2: @readarg R2 0 (296)
thrd2intrfc_value <= x"00000001";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_0_1;
WHEN mailbox_write_15_0_1 =>
-- Capture result of readarg.
R2 <= intrfc2thrd_value;
curstate <= mailbox_write_15_1_0;
WHEN mailbox_write_15_1_0 =>
-- arith2: @readarg R4 1 (297)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_1_1;
WHEN mailbox_write_15_1_1 =>
-- Capture result of readarg.
R4 <= intrfc2thrd_value;
curstate <= mailbox_write_15_2_0;
WHEN mailbox_write_15_2_0 =>
-- arith3: @add R0 R2 20 (0)
R0 <= R2 + x"00000014";
curstate <= mailbox_write_15_3_0;
WHEN mailbox_write_15_3_0 =>
-- arith2: @mov R3 R0 (320)
R3 <= R0;
curstate <= mailbox_write_15_4_0;
WHEN mailbox_write_15_4_0 =>
-- call hthread_mutex_lock R3 @returnVal @none (321)
-- Push argument 0
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_4_1;
WHEN mailbox_write_15_4_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= x"0000"&mailbox_write_15_4_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_15_4_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_15_5_0;
WHEN mailbox_write_15_5_0 =>
-- read R0 R2 12 (322)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_5_1;
WHEN mailbox_write_15_5_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_15_6_0;
WHEN mailbox_write_15_6_0 =>
-- read R1 R2 0 (323)
thrd2intrfc_address <= R2 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_6_1;
WHEN mailbox_write_15_6_1 =>
-- Capture result of read.
R1 <= intrfc2thrd_value;
curstate <= mailbox_write_15_7_0;
WHEN mailbox_write_15_7_0 =>
-- if R1 S> R0 goto hif_label0(17) (324)
if (R1 > R0) then
curstate <= mailbox_write_17_0_0;
else
curstate <= mailbox_write_16_0_0;
end if;
WHEN mailbox_write_16_0_0 =>
-- goto HIFL0(18) (325)
curstate <= mailbox_write_18_0_0;
WHEN mailbox_write_17_0_0 =>
-- goto HIFL2(21) (328)
curstate <= mailbox_write_21_0_0;
WHEN mailbox_write_18_0_0 =>
-- arith3: @add R0 R2 32 (0)
R0 <= R2 + x"00000020";
curstate <= mailbox_write_18_1_0;
WHEN mailbox_write_18_1_0 =>
-- call hthread_cond_wait R0 R3 @returnVal @none (333)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_1_1;
WHEN mailbox_write_18_1_1 =>
-- Push argument 1
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_1_2;
WHEN mailbox_write_18_1_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000028";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= x"0000"&mailbox_write_18_1_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_18_1_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000028";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_18_2_0;
WHEN mailbox_write_18_2_0 =>
-- read R0 R2 12 (334)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_2_1;
WHEN mailbox_write_18_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_18_3_0;
WHEN mailbox_write_18_3_0 =>
-- arith2: @mov R1 R0 (334)
R1 <= R0;
curstate <= mailbox_write_18_4_0;
WHEN mailbox_write_18_4_0 =>
-- read R0 R2 0 (335)
thrd2intrfc_address <= R2 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_4_1;
WHEN mailbox_write_18_4_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_18_5_0;
WHEN mailbox_write_18_5_0 =>
-- if R1 S< R0 goto hif_label2(20) (336)
if (R1 < R0) then
curstate <= mailbox_write_20_0_0;
else
curstate <= mailbox_write_19_0_0;
end if;
WHEN mailbox_write_19_0_0 =>
-- goto HIFL0(18) (337)
curstate <= mailbox_write_18_0_0;
WHEN mailbox_write_20_0_0 =>
-- goto HIFL2(21) (340)
curstate <= mailbox_write_21_0_0;
WHEN mailbox_write_21_0_0 =>
-- read R0 R2 16 (344)
thrd2intrfc_address <= R2 + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_0_1;
WHEN mailbox_write_21_0_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_1_0;
WHEN mailbox_write_21_1_0 =>
-- arith2: @mov R1 R0 (344)
R1 <= R0;
curstate <= mailbox_write_21_2_0;
WHEN mailbox_write_21_2_0 =>
-- read R0 R2 8 (345)
thrd2intrfc_address <= R2 + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_2_1;
WHEN mailbox_write_21_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_3_0;
WHEN mailbox_write_21_3_0 =>
-- arith3: @mul R0 R0 4 (347)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_write_21_3_1; --return address
T2 <= R0; --operand 1
T3 <= x"00000004"; --operand 2
T4 <= T4;
curstate <= MULT00;
WHEN mailbox_write_21_3_1 =>
R0 <= returnVal;
curstate <= mailbox_write_21_4_0;
WHEN mailbox_write_21_4_0 =>
-- arith3: @add R0 R1 R0 (349)
R0 <= R1 + R0;
curstate <= mailbox_write_21_5_0;
WHEN mailbox_write_21_5_0 =>
-- arith2: @mov R1 R4 (350)
R1 <= R4;
curstate <= mailbox_write_21_6_0;
WHEN mailbox_write_21_6_0 =>
-- write R0 0 R1 (350)
thrd2intrfc_address <= R0 + x"00000000";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_7_0;
WHEN mailbox_write_21_7_0 =>
-- read R0 R2 8 (351)
thrd2intrfc_address <= R2 + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_7_1;
WHEN mailbox_write_21_7_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_8_0;
WHEN mailbox_write_21_8_0 =>
-- arith3: @add R1 R0 1 (352)
R1 <= R0 + x"00000001";
curstate <= mailbox_write_21_9_0;
WHEN mailbox_write_21_9_0 =>
-- read R0 R2 0 (353)
thrd2intrfc_address <= R2 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_9_1;
WHEN mailbox_write_21_9_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_10_0;
WHEN mailbox_write_21_10_0 =>
-- arith3: @mod R0 R1 R0 (354)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_write_21_10_1; --return address
T2 <= R1; --operand 1
T3 <= R0; --operand 2
T4 <= T4;
curstate <= DIVIDE00;
WHEN mailbox_write_21_10_1 =>
R0 <= T4;
curstate <= mailbox_write_21_11_0;
WHEN mailbox_write_21_11_0 =>
-- write R2 8 R0 (355)
thrd2intrfc_address <= R2 + x"00000008";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_12_0;
WHEN mailbox_write_21_12_0 =>
-- read R0 R2 12 (356)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_12_1;
WHEN mailbox_write_21_12_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_13_0;
WHEN mailbox_write_21_13_0 =>
-- arith3: @add R0 R0 1 (357)
R0 <= R0 + x"00000001";
curstate <= mailbox_write_21_14_0;
WHEN mailbox_write_21_14_0 =>
-- write R2 12 R0 (358)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_15_0;
WHEN mailbox_write_21_15_0 =>
-- call hthread_mutex_unlock R3 @returnVal @none (359)
-- Push argument 0
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_15_1;
WHEN mailbox_write_21_15_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= x"0000"&mailbox_write_21_15_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_21_15_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_21_16_0;
WHEN mailbox_write_21_16_0 =>
-- arith3: @add R0 R2 28 (0)
R0 <= R2 + x"0000001C";
curstate <= mailbox_write_21_17_0;
WHEN mailbox_write_21_17_0 =>
-- call hthread_cond_signal R0 @returnVal @none (361)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_17_1;
WHEN mailbox_write_21_17_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= x"0000"&mailbox_write_21_17_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_21_17_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_21_18_0;
WHEN mailbox_write_21_18_0 =>
-- return 0 (362)
T1 <= x"00000000";
curstate <= mailbox_write_restore_0;
WHEN mailbox_write_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_1;
WHEN mailbox_write_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_2;
WHEN mailbox_write_restore_2 =>
-- Restore register R2 from the stack.
R1 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_3;
WHEN mailbox_write_restore_3 =>
-- Restore register R3 from the stack.
R2 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_4;
WHEN mailbox_write_restore_4 =>
-- Restore register R4 from the stack.
R3 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_end;
WHEN mailbox_write_end =>
-- Use the return opcode to jump back to the caller.
R4 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
-- Begin of function bubblesort (from bubblesort.c.hif)
WHEN bubblesort_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000009";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_0;
WHEN bubblesort_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_1;
WHEN bubblesort_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_2;
WHEN bubblesort_save_2 =>
-- Save register R2 on the stack.
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_3;
WHEN bubblesort_save_3 =>
-- Save register R3 on the stack.
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_4;
WHEN bubblesort_save_4 =>
-- Save register R4 on the stack.
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_value <= R4;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_5;
WHEN bubblesort_save_5 =>
-- Save register R5 on the stack.
thrd2intrfc_address <= stack_mem + x"00000014";
thrd2intrfc_value <= R5;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_6;
WHEN bubblesort_save_6 =>
-- Save register R6 on the stack.
thrd2intrfc_address <= stack_mem + x"00000018";
thrd2intrfc_value <= R6;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_7;
WHEN bubblesort_save_7 =>
-- Save register R7 on the stack.
thrd2intrfc_address <= stack_mem + x"0000001C";
thrd2intrfc_value <= R7;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_8;
WHEN bubblesort_save_8 =>
-- Save register R8 on the stack.
thrd2intrfc_address <= stack_mem + x"00000020";
thrd2intrfc_value <= R8;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_0_0_0;
WHEN bubblesort_0_0_0 =>
-- arith2: @readarg R1 0 (7)
thrd2intrfc_value <= x"00000001";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= bubblesort_0_0_1;
WHEN bubblesort_0_0_1 =>
-- Capture result of readarg.
R1 <= intrfc2thrd_value;
curstate <= bubblesort_0_1_0;
WHEN bubblesort_0_1_0 =>
-- arith2: @readarg R0 1 (8)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= bubblesort_0_1_1;
WHEN bubblesort_0_1_1 =>
-- Capture result of readarg.
R0 <= intrfc2thrd_value;
curstate <= bubblesort_0_2_0;
WHEN bubblesort_0_2_0 =>
-- arith3: @sub R4 R0 1 (24)
R4 <= R0 - x"00000001";
curstate <= bubblesort_0_3_0;
WHEN bubblesort_0_3_0 =>
-- arith2: @mov R2 R4 (25)
R2 <= R4;
curstate <= bubblesort_0_4_0;
WHEN bubblesort_0_4_0 =>
-- arith2: @mov R8 0 (26)
R8 <= x"00000000";
curstate <= bubblesort_0_5_0;
WHEN bubblesort_0_5_0 =>
-- arith2: @mov R3 0 (27)
R3 <= x"00000000";
curstate <= bubblesort_0_6_0;
WHEN bubblesort_0_6_0 =>
-- goto HIFL9(6) (28)
curstate <= bubblesort_6_0_0;
WHEN bubblesort_1_0_0 =>
-- arith3: @mul R7 R3 4 (30)
--call quick function (will set returnVal)
T1 <= x"0000"&bubblesort_1_0_1; --return address
T2 <= R3; --operand 1
T3 <= x"00000004"; --operand 2
T4 <= T4;
curstate <= MULT00;
WHEN bubblesort_1_0_1 =>
R7 <= returnVal;
curstate <= bubblesort_1_1_0;
WHEN bubblesort_1_1_0 =>
-- arith2: @mov R0 R7 (31)
R0 <= R7;
curstate <= bubblesort_1_2_0;
WHEN bubblesort_1_2_0 =>
-- arith3: @add R6 R0 R1 (32)
R6 <= R0 + R1;
curstate <= bubblesort_1_3_0;
WHEN bubblesort_1_3_0 =>
-- read R0 R6 0 (33)
thrd2intrfc_address <= R6 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_1_3_1;
WHEN bubblesort_1_3_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= bubblesort_1_4_0;
WHEN bubblesort_1_4_0 =>
-- arith2: @mov R5 R0 (33)
R5 <= R0;
curstate <= bubblesort_1_5_0;
WHEN bubblesort_1_5_0 =>
-- arith2: @mov R0 R7 (34)
R0 <= R7;
curstate <= bubblesort_1_6_0;
WHEN bubblesort_1_6_0 =>
-- arith3: @add R0 R1 R0 (35)
R0 <= R1 + R0;
curstate <= bubblesort_1_7_0;
WHEN bubblesort_1_7_0 =>
-- arith3: @add R7 R0 4 (36)
R7 <= R0 + x"00000004";
curstate <= bubblesort_1_8_0;
WHEN bubblesort_1_8_0 =>
-- read R0 R7 0 (37)
thrd2intrfc_address <= R7 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_1_8_1;
WHEN bubblesort_1_8_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= bubblesort_1_9_0;
WHEN bubblesort_1_9_0 =>
-- if R5 U<= R0 goto hif_label0(3) (38)
if (R5 <= R0) then
curstate <= bubblesort_3_0_0;
else
curstate <= bubblesort_2_0_0;
end if;
WHEN bubblesort_2_0_0 =>
-- goto HIFL2(4) (39)
curstate <= bubblesort_4_0_0;
WHEN bubblesort_3_0_0 =>
-- goto HIFL3(5) (42)
curstate <= bubblesort_5_0_0;
WHEN bubblesort_4_0_0 =>
-- write R6 0 R0 (46)
thrd2intrfc_address <= R6 + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_4_1_0;
WHEN bubblesort_4_1_0 =>
-- arith2: @mov R0 R5 (47)
R0 <= R5;
curstate <= bubblesort_4_2_0;
WHEN bubblesort_4_2_0 =>
-- write R7 0 R0 (47)
thrd2intrfc_address <= R7 + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_4_3_0;
WHEN bubblesort_4_3_0 =>
-- arith2: @mov R2 R3 (48)
R2 <= R3;
curstate <= bubblesort_4_4_0;
WHEN bubblesort_4_4_0 =>
-- arith2: @mov R8 1 (49)
R8 <= x"00000001";
curstate <= bubblesort_5_0_0;
WHEN bubblesort_5_0_0 =>
-- arith3: @add R3 R3 1 (51)
R3 <= R3 + x"00000001";
curstate <= bubblesort_6_0_0;
WHEN bubblesort_6_0_0 =>
-- if R3 U>= R4 goto hif_label2(8) (53)
if (R3 >= R4) then
curstate <= bubblesort_8_0_0;
else
curstate <= bubblesort_7_0_0;
end if;
WHEN bubblesort_7_0_0 =>
-- goto HIFL1(1) (54)
curstate <= bubblesort_1_0_0;
WHEN bubblesort_8_0_0 =>
-- goto HIFL6(9) (57)
curstate <= bubblesort_9_0_0;
WHEN bubblesort_9_0_0 =>
-- if R8 S== 0 goto hif_label4(11) (61)
if (R8 = x"00000000") then
curstate <= bubblesort_11_0_0;
else
curstate <= bubblesort_10_0_0;
end if;
WHEN bubblesort_10_0_0 =>
-- goto HIFL12(12) (62)
curstate <= bubblesort_12_0_0;
WHEN bubblesort_11_0_0 =>
-- goto HIFL7(13) (65)
curstate <= bubblesort_13_0_0;
WHEN bubblesort_12_0_0 =>
-- arith2: @mov R4 R2 (69)
R4 <= R2;
curstate <= bubblesort_12_1_0;
WHEN bubblesort_12_1_0 =>
-- arith2: @mov R8 0 (70)
R8 <= x"00000000";
curstate <= bubblesort_12_2_0;
WHEN bubblesort_12_2_0 =>
-- arith2: @mov R3 0 (71)
R3 <= x"00000000";
curstate <= bubblesort_12_3_0;
WHEN bubblesort_12_3_0 =>
-- goto HIFL9(6) (72)
curstate <= bubblesort_6_0_0;
WHEN bubblesort_13_0_0 =>
-- return @none (74)
T1 <= x"00000000";
curstate <= bubblesort_restore_0;
WHEN bubblesort_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_1;
WHEN bubblesort_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_2;
WHEN bubblesort_restore_2 =>
-- Restore register R2 from the stack.
R1 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_3;
WHEN bubblesort_restore_3 =>
-- Restore register R3 from the stack.
R2 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_4;
WHEN bubblesort_restore_4 =>
-- Restore register R4 from the stack.
R3 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_5;
WHEN bubblesort_restore_5 =>
-- Restore register R5 from the stack.
R4 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000014";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_6;
WHEN bubblesort_restore_6 =>
-- Restore register R6 from the stack.
R5 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000018";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_7;
WHEN bubblesort_restore_7 =>
-- Restore register R7 from the stack.
R6 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000001C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_8;
WHEN bubblesort_restore_8 =>
-- Restore register R8 from the stack.
R7 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000020";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_end;
WHEN bubblesort_end =>
-- Use the return opcode to jump back to the caller.
R8 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
-- Begin of function mailbox_read (from mailbox_no_globals.c.hif)
WHEN mailbox_read_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000005";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_0;
WHEN mailbox_read_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_1;
WHEN mailbox_read_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_2;
WHEN mailbox_read_save_2 =>
-- Save register R2 on the stack.
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_3;
WHEN mailbox_read_save_3 =>
-- Save register R3 on the stack.
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_4;
WHEN mailbox_read_save_4 =>
-- Save register R4 on the stack.
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_value <= R4;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_0_0;
WHEN mailbox_read_23_0_0 =>
-- arith2: @readarg R1 0 (57)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_0_1;
WHEN mailbox_read_23_0_1 =>
-- Capture result of readarg.
R1 <= intrfc2thrd_value;
curstate <= mailbox_read_23_1_0;
WHEN mailbox_read_23_1_0 =>
-- arith3: @add R0 R1 20 (0)
R0 <= R1 + x"00000014";
curstate <= mailbox_read_23_2_0;
WHEN mailbox_read_23_2_0 =>
-- arith2: @mov R2 R0 (78)
R2 <= R0;
curstate <= mailbox_read_23_3_0;
WHEN mailbox_read_23_3_0 =>
-- call hthread_mutex_lock R2 @returnVal @none (79)
-- Push argument 0
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_3_1;
WHEN mailbox_read_23_3_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= x"0000"&mailbox_read_23_3_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_23_3_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_23_4_0;
WHEN mailbox_read_23_4_0 =>
-- read R0 R1 12 (80)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_4_1;
WHEN mailbox_read_23_4_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_23_5_0;
WHEN mailbox_read_23_5_0 =>
-- if R0 S> 0 goto hif_label0(25) (81)
if (R0 > x"00000000") then
curstate <= mailbox_read_25_0_0;
else
curstate <= mailbox_read_24_0_0;
end if;
WHEN mailbox_read_24_0_0 =>
-- goto HIFL0(26) (82)
curstate <= mailbox_read_26_0_0;
WHEN mailbox_read_25_0_0 =>
-- goto HIFL2(29) (85)
curstate <= mailbox_read_29_0_0;
WHEN mailbox_read_26_0_0 =>
-- arith3: @add R0 R1 28 (0)
R0 <= R1 + x"0000001C";
curstate <= mailbox_read_26_1_0;
WHEN mailbox_read_26_1_0 =>
-- call hthread_cond_wait R0 R2 @returnVal @none (90)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_26_1_1;
WHEN mailbox_read_26_1_1 =>
-- Push argument 1
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_26_1_2;
WHEN mailbox_read_26_1_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000028";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= x"0000"&mailbox_read_26_1_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_26_1_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000028";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_26_2_0;
WHEN mailbox_read_26_2_0 =>
-- read R0 R1 12 (91)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_26_2_1;
WHEN mailbox_read_26_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_26_3_0;
WHEN mailbox_read_26_3_0 =>
-- if R0 S> 0 goto hif_label2(28) (92)
if (R0 > x"00000000") then
curstate <= mailbox_read_28_0_0;
else
curstate <= mailbox_read_27_0_0;
end if;
WHEN mailbox_read_27_0_0 =>
-- goto HIFL0(26) (93)
curstate <= mailbox_read_26_0_0;
WHEN mailbox_read_28_0_0 =>
-- goto HIFL2(29) (96)
curstate <= mailbox_read_29_0_0;
WHEN mailbox_read_29_0_0 =>
-- read R0 R1 16 (100)
thrd2intrfc_address <= R1 + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_0_1;
WHEN mailbox_read_29_0_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_1_0;
WHEN mailbox_read_29_1_0 =>
-- arith2: @mov R4 R0 (100)
R4 <= R0;
curstate <= mailbox_read_29_2_0;
WHEN mailbox_read_29_2_0 =>
-- read R0 R1 4 (101)
thrd2intrfc_address <= R1 + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_2_1;
WHEN mailbox_read_29_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_3_0;
WHEN mailbox_read_29_3_0 =>
-- arith2: @mov R3 R0 (101)
R3 <= R0;
curstate <= mailbox_read_29_4_0;
WHEN mailbox_read_29_4_0 =>
-- arith2: @mov R0 R3 (102)
R0 <= R3;
curstate <= mailbox_read_29_5_0;
WHEN mailbox_read_29_5_0 =>
-- arith3: @mul R0 R0 4 (103)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_read_29_5_1; --return address
T2 <= R0; --operand 1
T3 <= x"00000004"; --operand 2
T4 <= T4;
curstate <= MULT00;
WHEN mailbox_read_29_5_1 =>
R0 <= returnVal;
curstate <= mailbox_read_29_6_0;
WHEN mailbox_read_29_6_0 =>
-- arith3: @add R0 R4 R0 (105)
R0 <= R4 + R0;
curstate <= mailbox_read_29_7_0;
WHEN mailbox_read_29_7_0 =>
-- read R0 R0 0 (106)
thrd2intrfc_address <= R0 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_7_1;
WHEN mailbox_read_29_7_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_8_0;
WHEN mailbox_read_29_8_0 =>
-- arith2: @mov R4 R0 (106)
R4 <= R0;
curstate <= mailbox_read_29_9_0;
WHEN mailbox_read_29_9_0 =>
-- arith3: @add R3 R3 1 (107)
R3 <= R3 + x"00000001";
curstate <= mailbox_read_29_10_0;
WHEN mailbox_read_29_10_0 =>
-- read R0 R1 0 (108)
thrd2intrfc_address <= R1 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_10_1;
WHEN mailbox_read_29_10_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_11_0;
WHEN mailbox_read_29_11_0 =>
-- arith3: @mod R0 R3 R0 (109)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_read_29_11_1; --return address
T2 <= R3; --operand 1
T3 <= R0; --operand 2
T4 <= T4;
curstate <= DIVIDE00;
WHEN mailbox_read_29_11_1 =>
R0 <= T4;
curstate <= mailbox_read_29_12_0;
WHEN mailbox_read_29_12_0 =>
-- write R1 4 R0 (110)
thrd2intrfc_address <= R1 + x"00000004";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_13_0;
WHEN mailbox_read_29_13_0 =>
-- read R0 R1 12 (111)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_13_1;
WHEN mailbox_read_29_13_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_14_0;
WHEN mailbox_read_29_14_0 =>
-- arith3: @sub R0 R0 1 (112)
R0 <= R0 - x"00000001";
curstate <= mailbox_read_29_15_0;
WHEN mailbox_read_29_15_0 =>
-- write R1 12 R0 (113)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_16_0;
WHEN mailbox_read_29_16_0 =>
-- call hthread_mutex_unlock R2 @returnVal @none (114)
-- Push argument 0
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_16_1;
WHEN mailbox_read_29_16_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= x"0000"&mailbox_read_29_16_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_29_16_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_29_17_0;
WHEN mailbox_read_29_17_0 =>
-- arith3: @add R0 R1 32 (0)
R0 <= R1 + x"00000020";
curstate <= mailbox_read_29_18_0;
WHEN mailbox_read_29_18_0 =>
-- call hthread_cond_signal R0 @returnVal @none (116)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_18_1;
WHEN mailbox_read_29_18_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= x"0000"&mailbox_read_29_18_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_29_18_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_29_19_0;
WHEN mailbox_read_29_19_0 =>
-- return R4 (117)
T1 <= R4;
curstate <= mailbox_read_restore_0;
WHEN mailbox_read_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_1;
WHEN mailbox_read_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_2;
WHEN mailbox_read_restore_2 =>
-- Restore register R2 from the stack.
R1 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_3;
WHEN mailbox_read_restore_3 =>
-- Restore register R3 from the stack.
R2 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_4;
WHEN mailbox_read_restore_4 =>
-- Restore register R4 from the stack.
R3 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_end;
WHEN mailbox_read_end =>
-- Use the return opcode to jump back to the caller.
R4 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
-- Begin of function sort8k_entry (from sort8k_no_globals.c.hif)
WHEN sort8k_entry_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000002";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_save_0;
WHEN sort8k_entry_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_save_1;
WHEN sort8k_entry_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_31_0_0;
WHEN sort8k_entry_31_0_0 =>
-- arith2: @readarg R0 0 (7)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_31_0_1;
WHEN sort8k_entry_31_0_1 =>
-- Capture result of readarg.
R0 <= intrfc2thrd_value;
curstate <= sort8k_entry_31_1_0;
WHEN sort8k_entry_31_1_0 =>
-- arith2: @mov R1 R0 (37)
R1 <= R0;
curstate <= sort8k_entry_32_0_0;
WHEN sort8k_entry_32_0_0 =>
-- arith2: @mov R0 R1 (0)
R0 <= R1;
curstate <= sort8k_entry_32_1_0;
WHEN sort8k_entry_32_1_0 =>
-- call mailbox_read R0 @returnVal R0 (40)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_1_1;
WHEN sort8k_entry_32_1_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000018";
params_mem <= stack_mem + x"00000008";
thrd2intrfc_function <= mailbox_read_start;
thrd2intrfc_value <= x"0000"&sort8k_entry_32_1_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN sort8k_entry_32_1_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000018";
params_mem <= stack_mem - x"00000008";
R0 <= intrfc2thrd_value;
curstate <= sort8k_entry_32_2_0;
WHEN sort8k_entry_32_2_0 =>
-- call bubblesort R0 2048 @returnVal @none (43)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_2_1;
WHEN sort8k_entry_32_2_1 =>
-- Push argument 1
thrd2intrfc_value <= x"00000800";
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_2_2;
WHEN sort8k_entry_32_2_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"0000001C";
params_mem <= stack_mem + x"00000008";
thrd2intrfc_function <= bubblesort_start;
thrd2intrfc_value <= x"0000"&sort8k_entry_32_2_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN sort8k_entry_32_2_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"0000001C";
params_mem <= stack_mem - x"00000008";
T1 <= intrfc2thrd_value;
curstate <= sort8k_entry_32_3_0;
WHEN sort8k_entry_32_3_0 =>
-- arith3: @add R0 R1 36 (0)
R0 <= R1 + x"00000024";
curstate <= sort8k_entry_32_4_0;
WHEN sort8k_entry_32_4_0 =>
-- call mailbox_write R0 23 @returnVal @none (45)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_4_1;
WHEN sort8k_entry_32_4_1 =>
-- Push argument 1
thrd2intrfc_value <= x"00000017";
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_4_2;
WHEN sort8k_entry_32_4_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"0000001C";
params_mem <= stack_mem + x"00000008";
thrd2intrfc_function <= mailbox_write_start;
thrd2intrfc_value <= x"0000"&sort8k_entry_32_4_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN sort8k_entry_32_4_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"0000001C";
params_mem <= stack_mem - x"00000008";
T1 <= intrfc2thrd_value;
curstate <= sort8k_entry_32_5_0;
WHEN sort8k_entry_32_5_0 =>
-- goto HIFL0(32) (46)
curstate <= sort8k_entry_32_0_0;
WHEN sort8k_entry_33_0_0 =>
-- return @none (0)
T1 <= x"00000000";
curstate <= sort8k_entry_restore_0;
WHEN sort8k_entry_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_restore_1;
WHEN sort8k_entry_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_end;
WHEN sort8k_entry_end =>
-- Use the return opcode to jump back to the caller.
R1 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
--multiply quick function
--implements 32 bit multiply
--assumes return address in T1, operands in T2 and T3
WHEN MULT00 =>
T4 <= std_logic_vector(conv_signed(signed(b"00"&T2(16 to 31)) * signed(b"00"&T3(16 to 31)), 32));
returnVal <= std_logic_vector(conv_signed(signed(b"00"&T2(0 to 15)) * signed(b"00"&T3(16 to 31)), 32));
curstate <= MULT01;
WHEN MULT01 =>
T4 <= std_logic_vector(conv_signed(signed(b"00"&T2(16 to 31)) * signed(b"00"&T3(0 to 15)), 32));
returnVal <= T4 + (returnVal(16 to 31)&x"0000");
curstate <= MULT02;
WHEN MULT02 =>
returnVal <= (T4(16 to 31)&x"0000") + returnVal;
curstate <= T1(16 to 31);
-- DIVIDE QUICK FUNCTION
-- inputs
-- T2 - dividend
-- T3 - divisor
-- outputs
-- returnVal - quotient
-- T4 - remainder
-- tmps
-- T5 - tmp_divisor
-- T6 - counter
WHEN DIVIDE00 =>
if (T2 < x"00000000") then -- init quotient
returnVal <= -T2;
else
returnVal <= T2;
end if;
T4 <= x"00000000"; -- init remainder
if (T3 < x"00000000") then -- init tmp_divisor
T5 <= -T3;
else
T5 <= T3;
end if;
T6 <= x"00000000"; -- init counter
curstate <= DIVIDE01;
WHEN DIVIDE01 =>
-- BEGIN LOOP
T6 <= T6 + x"00000001"; -- increment counter
T4 <= T4(1 to 31)&returnVal(0); -- remainder = remainder(1 to 31)"ient(0)
returnVal <= returnVal(1 to 31)&'0'; -- shift quotient left
curstate <= DIVIDE02;
WHEN DIVIDE02 =>
-- if the remainder is greater than tmp_divisor
if (T4 >= T5) then
returnVal(31) <= '1'; -- set lsb of quotient
T4 <= T4 - T5; -- subtract tmp_divisor from remainder
end if;
if (T6 < x"00000020") then -- check loop bound
curstate <= DIVIDE01; -- GO TO NEXT ITERATION
else
curstate <= DIVIDE03; -- LOOP IS DONE
end if;
WHEN DIVIDE03 =>
-- LOOP IS DONE
-- THE FOLLOWING STATES HANDLE THE SIGNED ASPECT
-- if dividend < 0
if (T2 < x"00000000") then
T4 <= -T4; -- remainder = -remainder
curstate <= DIVIDE04;
else
curstate <= DIVIDE05;
end if;
WHEN DIVIDE04 =>
if (T3 > x"00000000") then
returnVal <= -returnVal;
end if;
curstate <= T1(16 to 31); -- return to caller
WHEN DIVIDE05 =>
if (T3 < x"00000000") then
returnVal <= -returnVal; -- negate the quotient
end if;
curstate <= T1(16 to 31); -- return to caller
-- Other states
WHEN WAIT_STATE =>
curstate <= returnstate;
WHEN FUNCTCALL_STATE => -- give the HWTI control over the next state
curstate <= intrfc2thrd_function;
WHEN others => --this case should never be reached
curstate <= START_STATE;
END CASE;
END IF;
END IF;
END PROCESS;
END IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_acc_quicksort_v1_00_a/hdl/vhdl/hw_acc_quicksort.vhd | 2 | 4197 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_quicksort is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
Clk : in std_logic;
RST : in std_logic;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : in std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : out std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
--This is just used for reseting
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_quicksort;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_quicksort is
component quicksort is
port
(
array_addr0 : out std_logic_vector(0 to (32 - 1));
array_dIN0 : out std_logic_vector(0 to (32- 1));
array_dOUT0 : in std_logic_vector(0 to (32 - 1));
array_rENA0 : out std_logic;
array_wENA0 : out std_logic_vector(0 to (32/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal reset_sig : std_logic;
-- Architecture Section
begin
reset_sig <= rst or FSL1_S_Exists;
FSL1_S_read <= FSL1_S_Exists ;
uut : quicksort
port map (
array_addr0 => BRAM_A_addr,
array_dIN0 => BRAM_A_dout,
array_dOUT0 => BRAM_A_din,
array_rENA0 => BRAM_A_en,
array_wENA0 => BRAM_A_wen,
chan1_channelDataIn => FSL0_M_Data,
chan1_channelDataOut => FSL0_S_Data,
chan1_exists => FSL0_S_Exists,
chan1_full => FSL0_M_Full,
chan1_channelRead => FSL0_S_Read,
chan1_channelWrite => FSL0_M_Write,
clock_sig => clk,
reset_sig => reset_sig
);
end architecture implementation;
| bsd-3-clause |
jevinskie/aes-over-pcie | source/pcie_top.vhd | 1 | 2351 | -- File name: pcie_top.vhd
-- Created: 2009-04-13
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: PCIe top level
use work.pcie.all;
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pcie_top is
port (
clk : in std_logic;
nrst : in std_logic;
rx_data : in byte; --
rx_data_k : in std_logic; --
rx_status : in std_logic_vector(2 downto 0); --
rx_elec_idle : in std_logic;
phy_status : in std_logic;
rx_valid : in std_logic; --
tx_data_aes : in byte;
aes_done : in std_logic; --
tx_detect_rx : out std_logic;
tx_elec_idle : out std_logic;
tx_comp : out std_logic;
rx_pol : out std_logic;
power_down : out std_logic_vector(1 downto 0);
tx_data : out byte; --
tx_data_k : out std_logic; --
got_key : out std_logic; --
got_pt : out std_logic;--
send_ct : out std_logic--
);
end entity pcie_top;
architecture structural of pcie_top is
signal state_d, state_q : state_type;
signal subblock : subblock_type;
signal i : g_index;
signal num_shifts : index;
signal filtered : slice;
signal round_num : round_type;
signal round_key : key_type;
signal enc_key : key_type;
signal sub_bytes_out : byte;
signal shift_rows_out : row;
signal mix_columns_out : col;
signal add_round_key_out : byte;
signal load_out : byte;
signal filtered_key : byte;
signal start_key : std_logic;
signal key_done : std_logic;
signal sbox_lookup : byte;
begin
tx_elec_idle <= '0';
tx_detect_rx <= '0';
tx_comp <= '0';
rx_pol <= '0';
power_down <= "00";
bridge_b : entity work.bridge(behavioral) port map (
clk => clk, nrst => nrst, rx_data => rx_data,
tx_data_aes => tx_data_aes, rx_data_k => rx_data_k,
tx_data => tx_data, tx_data_k => tx_data_k,
got_key => got_key, got_pt => got_pt, send_ct => send_ct,
aes_done => aes_done
);
end architecture structural;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/hwti_mblaze_6smp/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/count_fsm.vhd | 11 | 5764 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity count_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end count_fsm;
architecture behavioral of count_fsm is
-- A type for the states in the count fsm
type count_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the count fsm
signal count_cs : count_state;
signal count_ns : count_state;
-- Alias the location to store the count information
alias cdata : std_logic_vector(0 to C_CWIDTH-1) is data(C_DWIDTH-C_CWIDTH to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
count_update : process(clk,rst,sysrst,count_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
count_cs <= IDLE;
else
count_cs <= count_ns;
end if;
end if;
end process count_update;
count_controller : process(count_cs,start,mutex,micount) is
begin
count_ns <= count_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case count_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
count_ns <= READ;
end if;
when READ =>
count_ns <= DONE;
when DONE =>
finish <= '1';
cdata <= micount;
count_ns <= IDLE;
end case;
end process count_controller;
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/opb_SynchManager_v1_00_c/hdl/vhdl/count_fsm.vhd | 11 | 5764 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity count_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end count_fsm;
architecture behavioral of count_fsm is
-- A type for the states in the count fsm
type count_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the count fsm
signal count_cs : count_state;
signal count_ns : count_state;
-- Alias the location to store the count information
alias cdata : std_logic_vector(0 to C_CWIDTH-1) is data(C_DWIDTH-C_CWIDTH to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
count_update : process(clk,rst,sysrst,count_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
count_cs <= IDLE;
else
count_cs <= count_ns;
end if;
end if;
end process count_update;
count_controller : process(count_cs,start,mutex,micount) is
begin
count_ns <= count_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case count_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
count_ns <= READ;
end if;
when READ =>
count_ns <= DONE;
when DONE =>
finish <= '1';
cdata <= micount;
count_ns <= IDLE;
end case;
end process count_controller;
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/inferred_lut4.vhd | 2 | 7217 | -------------------------------------------------------------------------------
-- $Id: inferred_lut4.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- inferred_lut4.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: inferred_lut4.vhd
--
-- Description: This module is used to infer a LUT4 instantiation in
-- structural VHDL. It is compatable with Synplicity and xst
-- synthesis tools.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- inferred_lut4.vhd
--
-------------------------------------------------------------------------------
-- Author: D.Thorpe
--
-- History:
-- DET 2001-10-11 LUT4 implementation to work around xst lut4 problem with
-- INIT generic. Adapted from XST France work-around
-- solution sent to Bert Tise.
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Bus_clk", "Bus_clk_div#", "Bus_clk_#x"
-- Bus_rst signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
entity inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end entity inferred_lut4;
-------------------------------------------------------------------------------
architecture implementation of inferred_lut4 is
signal b : std_logic_vector(3 downto 0);
signal tmp : integer range 0 to 15;
begin
b <= (I3, I2, I1, I0);
tmp <= conv_integer(b);
O <= To_StdUlogic(INIT(tmp));
end architecture implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/numa3_hwti/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/kind_fsm.vhd | 11 | 6373 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity kind_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
rnw : in std_logic;
datain : in std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end kind_fsm;
architecture behavioral of kind_fsm is
-- A type for the states in the kind fsm
type kind_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the kind register fsm
signal kind_cs : kind_state;
signal kind_ns : kind_state;
-- Alias the kind input and output bits
alias kidata : std_logic_vector(0 to 1) is datain(C_DWIDTH-2 to C_DWIDTH-1);
alias kodata : std_logic_vector(0 to 1) is data(C_DWIDTH-2 to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
kind_update : process (clk,rst,sysrst,kind_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
kind_cs <= IDLE;
else
kind_cs <= kind_ns;
end if;
end if;
end process kind_update;
kind_controller : process (kind_cs,start,mutex,miowner,micount,mikind,milast,minext,rnw,datain) is
begin
kind_ns <= kind_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case kind_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
mowea <= '0';
moena <= '1';
kind_ns <= READ;
end if;
when READ =>
kind_ns <= DONE;
when DONE =>
if( rnw = '0' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
mokind <= kidata;
mocount <= micount;
monext <= minext;
molast <= milast;
finish <= '1';
kind_ns <= IDLE;
else
finish <= '1';
kodata <= mikind;
kind_ns <= IDLE;
end if;
end case;
end process kind_controller;
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/hwti_mblaze_6smp/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/owner_fsm.vhd | 11 | 5733 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity owner_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end owner_fsm;
architecture behavioral of owner_fsm is
-- A type for the states in the owner fsm
type owner_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the owner fsm
signal owner_cs : owner_state;
signal owner_ns : owner_state;
-- Alias owner output
alias odata : std_logic_vector(0 to C_TWIDTH-1) is data(C_DWIDTH-C_TWIDTH to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
owner_update : process(clk,rst,sysrst,owner_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
owner_cs <= IDLE;
else
owner_cs <= owner_ns;
end if;
end if;
end process owner_update;
owner_controller : process(owner_cs,start,mutex,miowner) is
begin
owner_ns <= owner_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case owner_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
owner_ns <= READ;
end if;
when READ =>
owner_ns <= DONE;
when DONE =>
finish <= '1';
odata <= miowner;
owner_ns <= IDLE;
end case;
end process owner_controller;
end behavioral;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/create_6.vhd | 2 | 20507 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: create_6.c
-- ARGUMENT_VALUE = 31
-- reg3 = childVal1
-- reg4 = childVal2
-- reg5 = * function1
-- reg6 = * function2
-- reg7 = thread1
-- reg8 = thread2
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function1
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg5_next <= intrfc2thrd_value;
-- Read the address of function2
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_create( &data->thread1, NULL, data->function1, ARGUMENT_VALUE );
when STATE_3 =>
reg6_next <= intrfc2thrd_value;
-- push ARGUMENT_VALUE
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"0000001F";
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function1
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg5;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread1
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_create( &data->thread2, NULL, data->function2, ARGUMENT_VALUE );
when STATE_8 =>
-- push ARGUMENT_VALUE
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"0000001F";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push data->function2
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push &data->thread2
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_13;
next_state <= WAIT_STATE;
-- hthread_join( data->thread1, (void *) &data->childVal1 );
when STATE_13 =>
-- Load the value of data->thread1
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
reg7_next <= intrfc2thrd_value;
-- push &data->childVal1
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000010";
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
-- push data->thread1
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_16 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_17;
next_state <= WAIT_STATE;
-- hthread_join( data->thread2, (void *) &data->childVal2 );
when STATE_17 =>
-- Load the value of data->thread2
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
reg8_next <= intrfc2thrd_value;
-- push &data->childVal2
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000014";
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- push data->thread2
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg8;
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_21;
next_state <= WAIT_STATE;
when STATE_21 =>
-- Load the value of childVal1
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000010";
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
reg3_next <= intrfc2thrd_value;
-- Load the value of childVal2
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000014";
next_state <= WAIT_STATE;
return_state_next <= STATE_23;
when STATE_23 =>
reg4_next <= intrfc2thrd_value;
next_state <= STATE_24;
when STATE_24 =>
if ( reg3 = reg4 ) then
retVal_next <= Z32;
else
retVal_next <= x"00000001";
end if;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_v20_v1_10_d/hdl/vhdl/priority_register_logic.vhd | 3 | 24319 | -------------------------------------------------------------------------------
-- $Id: priority_register_logic.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- OPB Arbiter - Priority Register Logic
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: priority_register_logic.vhd
-- Version: v1.02e
-- Description:
-- This file contains the priority registers and the logic to
-- update the registers for a LRU algorithm if the design is
-- parameterized for dynamic priority and dynamic priority
-- has been enabled in the control register. The number of
-- priority levels is determined by the number of masters.
-- There is a priority register for each priority level
-- containing the id of the master at that priority level. The
-- master id's are right justified in each register. Each
-- register is padded with leading zeros.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- chandan 05/25/06
-- ^^^^^^
-- Modified the process MASTER_LOOP to remove the latch it was creating.
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
--
-- library unsigned is used for overloading of '=' which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
--
-- Library OPB_ARBITER contains the package OPB_ARB_PKG with contant definitions
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.all;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-- Library UNISIM contains Xilinx primitives
library unisim;
use unisim.vcomponents.all;
------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_MASTERS -- number of masters
-- C_OPBDATA_WIDTH -- width of OPB data bus
-- C_NUM_MID_BITS -- number of bits required to encode masterIDs
-- C_DYNAM_PRIORITY -- dynamic priority is supported
--
-- Definition of Ports:
--
-- -- Master Grant signals
-- input MGrant -- Active high Master grant signals
-- input MGrant_n -- Active low Master grant signals
--
-- -- IPIF interface
-- input Bus2ip_data -- Data from OPB bus
-- input Bus2Ip_Reg_WrCE -- Clock enables for priority regs
--
-- -- Control register interface
-- input Dpen -- Dynamic priority enable
-- input Prv -- Priority registers valid
--
-- -- Priority register output
-- output Priority_register -- Priority register with leading zeros
-- output Priority_IDs -- Master IDs for each priority level
--
-- input Clk -- Clock
-- input Rst -- Reset
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity priority_register_logic is
generic ( C_NUM_MASTERS : integer := 16;
C_OPBDATA_WIDTH : integer := 32;
C_NUM_MID_BITS : integer := 4;
C_DYNAM_PRIORITY : boolean := true
);
port (
MGrant : in std_logic_vector(0 to C_NUM_MASTERS-1);
MGrant_n : in std_logic_vector(0 to C_NUM_MASTERS-1);
Bus2IP_Data : in std_logic_vector(0 to C_OPBDATA_WIDTH-1 );
Bus2IP_Reg_WrCE : in std_logic_vector(0 to C_NUM_MASTERS-1);
Dpen : in std_logic;
Prv : in std_logic;
Priority_register : out std_logic_vector(0 to C_NUM_MASTERS*C_OPBDATA_WIDTH-1);
Priority_IDs : out std_logic_vector(0 to C_NUM_MASTERS*C_NUM_MID_BITS-1);
Clk : in std_logic;
Rst : in std_logic
);
end priority_register_logic;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of priority_register_logic is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- pad number of masters to nearest power of 2
constant NUM_MSTRS_PAD : integer := pad_power2(C_NUM_MASTERS);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- Internal priority register
signal priority_register_i : std_logic_vector(0 to C_NUM_MASTERS*C_OPBDATA_WIDTH-1);
-- Internal master ids at each priority level
signal priority_ids_i : std_logic_vector(0 to C_NUM_MASTERS*C_NUM_MID_BITS-1);
-- create default set of priority IDs for use when the Prv bit is negated
-- indicating that the priority registers are being updated by the processor
signal default_ids : std_logic_vector(0 to C_NUM_MASTERS*C_NUM_MID_BITS-1);
-- Register shift controls
-- Set default to zeros, if dynamic priority is not supported, this bus will
-- stay zero.
signal shift : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- ID of master granted the bus, defaults to zero if dynamic priority is not
-- supported.
signal granted_mid : std_logic_vector(0 to C_NUM_MID_BITS-1) := (others => '0');
-- Need active low grant signals to properly drive select lines of muxes
-- this bus will use NUM_MSTRS_PAD so that bus is sized to nearest power of 2.
-- Bus defaults to '0', only the bits up to C_NUM_MASTERS
-- will get assigned a real value.
signal mgrant_n_pad : std_logic_vector(0 to NUM_MSTRS_PAD-1) := (others => '0');
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Assign internal priority register to output ports
-- Use default priority IDs when the priority registers are being updated, i.e.
-- PRV=0.
-------------------------------------------------------------------------------
Priority_register <= priority_register_i;
Priority_IDs <= priority_ids_i when Prv = '1'
else default_ids;
-- Create the default master IDs for each priority level
-- The default is that LVL0 = Master 0, LVL1 = Master 1, LVLn = Mastern
DEF_IDS_GEN: for i in 0 to C_NUM_MASTERS-1 generate
-- create default set of priority IDs for use when the Prv bit is negated
-- indicating that the priority registers are being updated by the processor
begin
default_ids(i*C_NUM_MID_BITS to i*C_NUM_MID_BITS+C_NUM_MID_BITS-1) <=
conv_std_logic_vector(i, C_NUM_MID_BITS);
end generate DEF_IDS_GEN;
-- assign the padded mgrant_n bus the MGrant_n signals
mgrant_n_pad(0 to C_NUM_MASTERS-1) <= MGrant_n;
-------------------------------------------------------------------------------
-- Dynamic Priority Support
-------------------------------------------------------------------------------
-- If the design has been parameterized for each master, have to first decode
-- the grant signals with the current priority register values to determine
-- which priority level was granted the bus. This is then used to determine
-- which priority registers need to shift in the master ID from the lower
-- priority registers. If dynamic priority is not supported, the shift controls
-- are left at their default value of 0.
-------------------------------------------------------------------------------
DYNAM_PRIORITY_GEN: if C_DYNAM_PRIORITY generate
-- one-hot active-low indicator of which priority level was granted the bus
signal grant_lvl_n : std_logic_vector(0 to C_NUM_MASTERS-1);
begin
MASTER_LOOP: for i in 0 to C_NUM_MASTERS-1 generate
-- decode each master ID in the priority registers to determine
-- which priority level was granted the bus
MASTER_4 : if C_NUM_MID_BITS = 4 generate
signal priority_ids_int : std_logic_vector(0 to 3);
begin
priority_ids_int <= priority_ids_i(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(mgrant_n_pad, priority_ids_int)
begin
case priority_ids_int is
when "0000" => grant_lvl_n(i) <= mgrant_n_pad(0);
when "0001" => grant_lvl_n(i) <= mgrant_n_pad(1);
when "0010" => grant_lvl_n(i) <= mgrant_n_pad(2);
when "0011" => grant_lvl_n(i) <= mgrant_n_pad(3);
when "0100" => grant_lvl_n(i) <= mgrant_n_pad(4);
when "0101" => grant_lvl_n(i) <= mgrant_n_pad(5);
when "0110" => grant_lvl_n(i) <= mgrant_n_pad(6);
when "0111" => grant_lvl_n(i) <= mgrant_n_pad(7);
when "1000" => grant_lvl_n(i) <= mgrant_n_pad(8);
when "1001" => grant_lvl_n(i) <= mgrant_n_pad(9);
when "1010" => grant_lvl_n(i) <= mgrant_n_pad(10);
when "1011" => grant_lvl_n(i) <= mgrant_n_pad(11);
when "1100" => grant_lvl_n(i) <= mgrant_n_pad(12);
when "1101" => grant_lvl_n(i) <= mgrant_n_pad(13);
when "1110" => grant_lvl_n(i) <= mgrant_n_pad(14);
when others => grant_lvl_n(i) <= mgrant_n_pad(15);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_4;
MASTER_3 : if C_NUM_MID_BITS = 3 generate
signal priority_ids_int : std_logic_vector(0 to 2);
begin
priority_ids_int <= priority_ids_i(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(mgrant_n_pad, priority_ids_int)
begin
case priority_ids_int is
when "000" => grant_lvl_n(i) <= mgrant_n_pad(0);
when "001" => grant_lvl_n(i) <= mgrant_n_pad(1);
when "010" => grant_lvl_n(i) <= mgrant_n_pad(2);
when "011" => grant_lvl_n(i) <= mgrant_n_pad(3);
when "100" => grant_lvl_n(i) <= mgrant_n_pad(4);
when "101" => grant_lvl_n(i) <= mgrant_n_pad(5);
when "110" => grant_lvl_n(i) <= mgrant_n_pad(6);
when others => grant_lvl_n(i) <= mgrant_n_pad(7);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_3;
MASTER_2 : if C_NUM_MID_BITS = 2 generate
signal priority_ids_int : std_logic_vector(0 to 1);
begin
priority_ids_int <= priority_ids_i(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(mgrant_n_pad, priority_ids_int)
begin
case priority_ids_int is
when "00" => grant_lvl_n(i) <= mgrant_n_pad(0);
when "01" => grant_lvl_n(i) <= mgrant_n_pad(1);
when "10" => grant_lvl_n(i) <= mgrant_n_pad(2);
when others => grant_lvl_n(i) <= mgrant_n_pad(3);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_2;
MASTER_1 : if C_NUM_MID_BITS = 1 generate
signal priority_ids_int : std_logic_vector (0 to 0);
begin
priority_ids_int <= priority_ids_i(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(mgrant_n_pad, priority_ids_int)
begin
case priority_ids_int is
when "0" => grant_lvl_n(i) <= mgrant_n_pad(0);
when others => grant_lvl_n(i) <= mgrant_n_pad(1);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_1;
-- generate the OR chain which determines the shift signals for the
-- priority registers. LVL0 shifts if GRANT_LVL0 was asserted, LVL1
-- shifts if GRANT_LVL0 or GRANT_LVL1 was asserted, LVLn shifts if
-- any grants LVL0 - LVLn were asserted
MUX0_GEN: if i = 0 generate
MUX_LVL0: MUXCY
port map (
O => shift(i), --[out]
CI => '0', --[in]
DI => '1', --[in]
S => grant_lvl_n(i) --[in]
);
end generate MUX0_GEN;
OTHER_MUXES: if i /= 0 generate
MUX_LVLS: MUXCY
port map (
O => shift(i), --[out]
CI => shift(i-1), --[in]
DI => '1', --[in]
S => grant_lvl_n(i) --[in]
);
end generate OTHER_MUXES;
end generate MASTER_LOOP;
-- have to encode the grant signals to the proper Master ID for shifting
-- into the lowest priority register
GRANT_MID_ENC: entity opb_v20_v1_10_d.onehot2encoded
generic map( C_1HOT_BUS_SIZE => C_NUM_MASTERS)
port map (
Bus_1hot => MGrant,
Bus_enc => granted_mid
);
end generate DYNAM_PRIORITY_GEN;
-------------------------------------------------------------------------------
-- Priority Registers
-------------------------------------------------------------------------------
-- The following instantiations of PRIORITY_REG provide registers for each
-- priority level which hold the id of the master at that priority level. There
-- is a priority register for each master. The default reset condition is that
-- Master 0 is at level 0 priority, Master 1 is at level 1 priority, etc.
-- Note that if dynamic priority is not supported, DPEN is set to zero and the
-- SHIFT control is set to zero.
--
-- Also note that if dynamic priority is supported, the lowest level priority
-- register shifts in the granted master id. If dynamic priority is not
-- supported, this ID is set to zeros since it will be unused.
-------------------------------------------------------------------------------
PRIOR_REG_GEN: for i in 0 to C_NUM_MASTERS-1 generate
LAST_REG: if i = C_NUM_MASTERS-1 generate
LOW_PRIOR_REG: entity opb_v20_v1_10_d.priority_reg
generic map (
C_RESET_VALUE => conv_std_logic_vector(i, C_NUM_MID_BITS),
C_NUM_MID_BITS => C_NUM_MID_BITS,
C_OPBDATA_WIDTH => C_OPBDATA_WIDTH
)
port map (
Priorreg_wrce => Bus2IP_Reg_WrCE(i),
Bus2Ip_Data => Bus2IP_Data,
Dpen => Dpen,
Shift => shift(i),
Master_id_in => granted_mid,
Master_id_out => priority_ids_i(i*C_NUM_MID_BITS to
i*C_NUM_MID_BITS + C_NUM_MID_BITS-1),
Priority => priority_register_i(i*C_OPBDATA_WIDTH to
i*C_OPBDATA_WIDTH + C_OPBDATA_WIDTH-1),
Clk => Clk,
Rst => Rst
);
end generate LAST_REG;
OTHER_REGS: if i /= C_NUM_MASTERS-1 generate
PRIOR_REG: entity opb_v20_v1_10_d.priority_reg
generic map (
C_RESET_VALUE => conv_std_logic_vector(i, C_NUM_MID_BITS),
C_NUM_MID_BITS => C_NUM_MID_BITS,
C_OPBDATA_WIDTH => C_OPBDATA_WIDTH
)
port map (
Priorreg_wrce => Bus2IP_Reg_WrCE(i),
Bus2Ip_Data => Bus2IP_Data,
Dpen => Dpen,
Shift => shift(i),
Master_id_in => priority_ids_i((i+1)*C_NUM_MID_BITS to
(i+1)*C_NUM_MID_BITS + C_NUM_MID_BITS-1),
Master_id_out => priority_ids_i(i*C_NUM_MID_BITS to
i*C_NUM_MID_BITS + C_NUM_MID_BITS-1),
Priority => priority_register_i(i*C_OPBDATA_WIDTH to
i*C_OPBDATA_WIDTH + C_OPBDATA_WIDTH-1),
Clk => Clk,
Rst => Rst
);
end generate OTHER_REGS;
end generate PRIOR_REG_GEN;
end implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pselect_mask.vhd | 2 | 13366 | -------------------------------------------------------------------------------
-- $Id: pselect_mask.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_mask.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_mask.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2002-02-06 First Version
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- PS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_mask is
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := "00000000000000100000000000000000";
C_MASK : std_logic_vector(0 to 31) := "00000000000001111100000000000000"
);
port (
A : in std_logic_vector(0 to C_AW-1);
Valid : in std_logic;
CS : out std_logic
);
end entity pselect_mask;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
library unisim;
use unisim.all;
architecture imp of pselect_mask is
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic := '0';
-- I1 : in std_logic := '0';
-- I2 : in std_logic := '0';
-- I3 : in std_logic := '0');
-- end component;
-- component MUXCY is
-- port (
-- O : out std_logic;
-- CI : in std_logic;
-- DI : in std_logic;
-- S : in std_logic
-- );
-- end component MUXCY;
function Nr_Of_Ones (S : std_logic_vector) return natural is
variable tmp : natural := 0;
begin -- function Nr_Of_Ones
for I in S'range loop
if (S(I) = '1') then
tmp := tmp + 1;
end if;
end loop; -- I
return tmp;
end function Nr_Of_Ones;
function fix_AB (B : boolean; I : integer) return integer is
begin -- function fix_AB
if (not B) then
return I + 1;
else
return I;
end if;
end function fix_AB;
constant Nr : integer := Nr_Of_Ones(C_MASK);
constant Use_CIN : boolean := ((Nr mod 4) = 0);
constant AB : integer := fix_AB(Use_CIN, Nr);
attribute INIT : string;
constant NUM_LUTS : integer := (AB-1)/4+1;
-- signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
-- signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-- function to initialize LUT within pselect
type int4 is array (3 downto 0) of integer;
function pselect_init_lut(i : integer;
AB : integer;
NUM_LUTS : integer;
C_AW : integer;
C_BAR : std_logic_vector(0 to 31))
return bit_vector is
variable init_vector : bit_vector(15 downto 0) := X"0001";
variable j : integer := 0;
variable val_in : int4;
begin
for j in 0 to 3 loop
if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) then
val_in(j) := conv_integer(C_BAR(i*4+j));
else val_in(j) := 0;
end if;
end loop;
init_vector := To_bitvector(conv_std_logic_vector(2**(val_in(3)*8+
val_in(2)*4+val_in(1)*2+val_in(0)*1),16));
return init_vector;
end pselect_init_lut;
signal A_Bus : std_logic_vector(0 to AB);
signal BAR : std_logic_vector(0 to AB);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
Make_Busses : process (A,Valid) is
variable tmp : natural;
begin -- process Make_Busses
tmp := 0;
A_Bus <= (others => '0');
BAR <= (others => '0');
for I in C_MASK'range loop
if (C_MASK(I) = '1') then
A_Bus(tmp) <= A(I);
BAR(tmp) <= C_BAR(I);
tmp := tmp + 1;
end if;
end loop; -- I
if (not Use_CIN) then
BAR(tmp) <= '1';
A_Bus(tmp) <= Valid;
end if;
end process Make_Busses;
-- More_Than_3_Bits : if (AB > 3) generate
-- Using_CIn: if (Use_CIN) generate
-- carry_chain(0) <= Valid;
-- end generate Using_CIn;
-- No_CIn: if (not Use_CIN) generate
-- carry_chain(0) <= '1';
-- end generate No_CIn;
-- GEN_DECODE : for i in 0 to NUM_LUTS-1 generate
-- signal lut_in : std_logic_vector(3 downto 0);
-- begin
-- GEN_LUT_INPUTS : for j in 0 to 3 generate
-- -- Generate to assign address bits to LUT4 inputs
-- GEN_INPUT : if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) generate
-- lut_in(j) <= A_Bus(i*4+j);
-- end generate;
-- -- Generate to assign zeros to remaining LUT4 inputs
-- GEN_ZEROS : if not(i < NUM_LUTS-1 or j <= ((AB-1) mod 4)) generate
-- lut_in(j) <= '0';
-- end generate;
-- end generate;
---------------------------------------------------------------------------------
---- RTL version without LUT instantiation for XST
---------------------------------------------------------------------------------
-- lut_out(i) <= (lut_in(0) xnor BAR(i*4+0)) and
-- (lut_in(1) xnor BAR(i*4+1)) and
-- (lut_in(2) xnor BAR(i*4+2)) and
-- (lut_in(3) xnor BAR(i*4+3));
---------------------------------------------------------------------------------
---- Structural version with LUT instantiation for Synplicity (when RLOC is
---- desired for placing LUT
---------------------------------------------------------------------------------
---- LUT4_I : LUT4
---- generic map(
---- -- Function init_lut is used to generate INIT value for LUT4
---- INIT => pselect_init_lut(i,C_AB,NUM_LUTS,C_AW,C_BAR)
---- )
---- port map (
---- O => lut_out(i), -- [out]
---- I0 => lut_in(0), -- [in]
---- I1 => lut_in(1), -- [in]
---- I2 => lut_in(2), -- [in]
---- I3 => lut_in(3)); -- [in]
---------------------------------------------------------------------------------
-- MUXCY_I : MUXCY
-- port map (
-- O => carry_chain(i+1), --[out]
-- CI => carry_chain(i), --[in]
-- DI => '0', --[in]
-- S => lut_out(i) --[in]
-- );
-- end generate;
-- CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output
-- end generate More_Than_3_Bits;
-- Less_than_4_bits: if (AB < 4) generate
CS <= Valid when A_Bus=BAR else '0';
-- end generate Less_than_4_bits;
end imp;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/stress/mutex_lock_1.vhd | 2 | 17362 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
--signal reg5, reg5_next : std_logic_vector(0 to 31);
--signal reg6, reg6_next : std_logic_vector(0 to 31);
--signal reg7, reg7_next : std_logic_vector(0 to 31);
--signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
--retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
--reg5 <= reg5_next;
--reg6 <= reg6_next;
--reg7 <= reg7_next;
--reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
--retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
--reg5_next <= reg5;
--reg6_next <= reg6;
--reg7_next <= reg7;
--reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: mutex_lock_stress_1
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t*) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutex_lock( mutex );
when STATE_2 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- hthread_yield();
when STATE_4 =>
-- call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( mutex );
when STATE_5 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
when STATE_7 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/ipif_steer.vhd | 2 | 22674 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Steer is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64
C_SMALLEST : integer := 32; -- 8, 16, 32, 64
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity IPIF_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Steer is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/condattr_destroy_2.vhd | 2 | 15952 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- condattr_destroy_2.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_condattr_t * cond = (hthread_condattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_condattr_init( condattr );
when STATE_2 =>
-- Push condattr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- hthread_condattr_destroy( condattr );
when STATE_4 =>
-- Push the argument to hthread_condattr_destroy
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_condattr_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- retVal = hthread_condattr_init( condattr );
when STATE_6 =>
-- Push cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Call hthread_condattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
when STATE_8 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_sync_manager_v1_00_a/hdl/vhdl/axi_sync_manager.vhd | 2 | 38758 | ------------------------------------------------------------------------------
-- axi_sync_manager.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_sync_manager.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Jun 26 14:24:54 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_master_lite_v1_00_a;
use axi_master_lite_v1_00_a.axi_master_lite;
library axi_sync_manager_v1_00_a;
use axi_sync_manager_v1_00_a.user_logic;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_M_AXI_LITE_ADDR_WIDTH -- Master-Intf address bus width
-- C_M_AXI_LITE_DATA_WIDTH -- Master-Intf data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
-- m_axi_lite_aclk -- AXI4LITE master: Clock
-- m_axi_lite_aresetn -- AXI4LITE master: Reset
-- md_error -- AXI4LITE master: Error
-- m_axi_lite_arready -- AXI4LITE master: Read address ready
-- m_axi_lite_arvalid -- AXI4LITE master: read address valid
-- m_axi_lite_araddr -- AXI4LITE master: read address protection
-- m_axi_lite_arprot -- AXI4LITE master: Read address protection
-- m_axi_lite_rready -- AXI4LITE master: Read data ready
-- m_axi_lite_rvalid -- AXI4LITE master: Read data valid
-- m_axi_lite_rdata -- AXI4LITE master: Read data
-- m_axi_lite_rresp -- AXI4LITE master: read data response
-- m_axi_lite_awready -- AXI4LITE master: write address ready
-- m_axi_lite_awvalid -- AXI4LITE master: write address valid
-- m_axi_lite_awaddr -- AXI4LITE master: write address valid
-- m_axi_lite_awprot -- AXI4LITE master: write address protection
-- m_axi_lite_wready -- AXI4LITE master: write data ready
-- m_axi_lite_wvalid -- AXI4LITE master: write data valid
-- m_axi_lite_wdata -- AXI4LITE master: write data
-- m_axi_lite_wstrb -- AXI4LITE master: write data strobe
-- m_axi_lite_bready -- AXI4LITE master: read response ready
-- m_axi_lite_bvalid -- AXI4LITE master: read response valid
-- m_axi_lite_bresp -- AXI4LITE master: read response
------------------------------------------------------------------------------
entity axi_sync_manager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"00FFFFFF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 0;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_M_AXI_LITE_ADDR_WIDTH : integer := 32;
C_M_AXI_LITE_DATA_WIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
m_axi_lite_aclk : in std_logic;
m_axi_lite_aresetn : in std_logic;
md_error : out std_logic;
m_axi_lite_arready : in std_logic;
m_axi_lite_arvalid : out std_logic;
m_axi_lite_araddr : out std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0);
m_axi_lite_arprot : out std_logic_vector(2 downto 0);
m_axi_lite_rready : out std_logic;
m_axi_lite_rvalid : in std_logic;
m_axi_lite_rdata : in std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0);
m_axi_lite_rresp : in std_logic_vector(1 downto 0);
m_axi_lite_awready : in std_logic;
m_axi_lite_awvalid : out std_logic;
m_axi_lite_awaddr : out std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0);
m_axi_lite_awprot : out std_logic_vector(2 downto 0);
m_axi_lite_wready : in std_logic;
m_axi_lite_wvalid : out std_logic;
m_axi_lite_wdata : out std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0);
m_axi_lite_wstrb : out std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
m_axi_lite_bready : out std_logic;
m_axi_lite_bvalid : in std_logic;
m_axi_lite_bresp : in std_logic_vector(1 downto 0)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
attribute MAX_FANOUT of m_axi_lite_aclk : signal is "10000";
attribute MAX_FANOUT of m_axi_lite_aresetn : signal is "10000";
attribute SIGIS of m_axi_lite_aclk : signal is "Clk";
attribute SIGIS of m_axi_lite_aresetn : signal is "Rst";
end entity axi_sync_manager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_sync_manager is
-------------------------------------------------------------------
-- BEGIN CODE COPIED FROM OPB SYNCH MANAGER
-------------------------------------------------------------------
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_S_AXI_ADDR_WIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_S_AXI_ADDR_WIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_S_AXI_ADDR_WIDTH - MUTEX_BITS - 2 to
C_S_AXI_ADDR_WIDTH - 3) := (others => '1');
addr(C_S_AXI_ADDR_WIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_S_AXI_ADDR_WIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_S_AXI_ADDR_WIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_S_AXI_ADDR_WIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_S_AXI_ADDR_WIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := C_S_AXI_DATA_WIDTH ;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-------------------------------------------------------------------
-- END CODE COPIED FROM OPB SYNCH MANAGER
-------------------------------------------------------------------
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
-- constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
-- constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
-- constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
-- constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
--
-- constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
-- (
-- ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
-- ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
-- ZERO_ADDR_PAD & USER_MST_BASEADDR, -- user logic master space base address
-- ZERO_ADDR_PAD & USER_MST_HIGHADDR -- user logic master space high address
-- );
-- ------------------------------------------
-- -- Array of desired number of chip enables for each address range
-- ------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG+USER_MST_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
--
-- constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
-- (
-- 0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
-- 1 => pad_power2(USER_MST_NUM_REG) -- number of ce for user logic master space
-- );
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_M_AXI_LITE_ADDR_WIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_M_AXI_LITE_DATA_WIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_MST_CS_INDEX : integer := 1;
constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_ip2bus_mstrd_req : std_logic;
signal ipif_ip2bus_mstwr_req : std_logic;
signal ipif_ip2bus_mst_addr : std_logic_vector(0 to C_M_AXI_LITE_ADDR_WIDTH-1);
signal ipif_ip2bus_mst_be : std_logic_vector(0 to (C_M_AXI_LITE_DATA_WIDTH/8)-1);
signal ipif_ip2bus_mst_lock : std_logic;
signal ipif_ip2bus_mst_reset : std_logic;
signal ipif_bus2ip_mst_cmdack : std_logic;
signal ipif_bus2ip_mst_cmplt : std_logic;
signal ipif_bus2ip_mst_error : std_logic;
signal ipif_bus2ip_mst_rearbitrate : std_logic;
signal ipif_bus2ip_mst_cmd_timeout : std_logic;
signal ipif_bus2ip_mstrd_d : std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1);
signal ipif_bus2ip_mstrd_src_rdy_n : std_logic;
signal ipif_ip2bus_mstwr_d : std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1);
signal ipif_bus2ip_mstwr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate axi_master_lite
------------------------------------------
AXI_MASTER_LITE_I : entity axi_master_lite_v1_00_a.axi_master_lite
generic map
(
C_M_AXI_LITE_ADDR_WIDTH => C_M_AXI_LITE_ADDR_WIDTH,
C_M_AXI_LITE_DATA_WIDTH => C_M_AXI_LITE_DATA_WIDTH,
C_FAMILY => C_FAMILY
)
port map
(
m_axi_lite_aclk => m_axi_lite_aclk,
m_axi_lite_aresetn => m_axi_lite_aresetn,
md_error => md_error,
m_axi_lite_arready => m_axi_lite_arready,
m_axi_lite_arvalid => m_axi_lite_arvalid,
m_axi_lite_araddr => m_axi_lite_araddr,
m_axi_lite_arprot => m_axi_lite_arprot,
m_axi_lite_rready => m_axi_lite_rready,
m_axi_lite_rvalid => m_axi_lite_rvalid,
m_axi_lite_rdata => m_axi_lite_rdata,
m_axi_lite_rresp => m_axi_lite_rresp,
m_axi_lite_awready => m_axi_lite_awready,
m_axi_lite_awvalid => m_axi_lite_awvalid,
m_axi_lite_awaddr => m_axi_lite_awaddr,
m_axi_lite_awprot => m_axi_lite_awprot,
m_axi_lite_wready => m_axi_lite_wready,
m_axi_lite_wvalid => m_axi_lite_wvalid,
m_axi_lite_wdata => m_axi_lite_wdata,
m_axi_lite_wstrb => m_axi_lite_wstrb,
m_axi_lite_bready => m_axi_lite_bready,
m_axi_lite_bvalid => m_axi_lite_bvalid,
m_axi_lite_bresp => m_axi_lite_bresp,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
-- Bus2IP_Addr => iBus2IP_Addr,
-- Bus2IP_Data => uBus2IP_Data,
-- Bus2IP_BE => uBus2IP_BE,
-- Bus2IP_RNW => iBus2IP_RNW,
-- Bus2IP_RdCE => uBus2IP_RdCE,
-- Bus2IP_WrCE => uBus2IP_WrCE,
-- Bus2IP_RdReq => iBus2IP_RdReq,
-- Bus2IP_WrReq => iBus2IP_WrReq,
-- Bus2IP_MstError => iBus2IP_MstError,
-- Bus2IP_MstLastAck => iBus2IP_MstLastAck,
-- Bus2IP_MstRdAck => iBus2IP_MstRdAck,
-- Bus2IP_MstWrAck => iBus2IP_MstWrAck,
-- Bus2IP_MstRetry => iBus2IP_MstRetry,
-- Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
-- IP2Bus_Addr => iIP2Bus_Addr,
-- IP2Bus_MstBE => uIP2Bus_MstBE,
-- IP2Bus_MstBurst => iIP2Bus_MstBurst,
-- IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
-- IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
-- IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
-- IP2IP_Addr => iIP2IP_Addr,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(USER_SLV_NUM_REG-1 downto 0) <= ipif_Bus2IP_RdCE(TOTAL_IPIF_CE -USER_SLV_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_SLV_CE_INDEX -USER_SLV_NUM_REG);
user_Bus2IP_WrCE(USER_SLV_NUM_REG-1 downto 0) <= ipif_Bus2IP_WrCE(TOTAL_IPIF_CE -USER_SLV_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_SLV_CE_INDEX -USER_SLV_NUM_REG);
user_Bus2IP_RdCE(USER_NUM_REG-1 downto USER_NUM_REG-USER_MST_NUM_REG) <= ipif_Bus2IP_RdCE(TOTAL_IPIF_CE - USER_MST_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_MST_CE_INDEX -USER_MST_NUM_REG);
user_Bus2IP_WrCE(USER_NUM_REG-1 downto USER_NUM_REG- USER_MST_NUM_REG) <= ipif_Bus2IP_WrCE(TOTAL_IPIF_CE - USER_MST_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_MST_CE_INDEX -USER_MST_NUM_REG);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
end IMP;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/hw_acc_vector_v1_00_a/hdl/vhdl/hw_acc_vector.vhd | 2 | 4996 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_vector is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : out std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : in std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_vector;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_vector is
component vector_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal ap_rst : STD_LOGIC;
-- Architecture Section
begin
ap_rst <= not ap_rst_n;
uut : vector_chan
port map (
Vector_A_addr0 => BRAM_A_addr,
Vector_A_dIN0 => BRAM_A_din,
Vector_A_dOUT0 => BRAM_A_dout,
Vector_A_rENA0 => BRAM_A_en,
Vector_A_wENA0 => BRAM_A_wen,
Vector_B_addr0 => BRAM_B_addr,
Vector_B_dIN0 => BRAM_B_din,
Vector_B_dOUT0 => BRAM_B_dout,
Vector_B_rENA0 => BRAM_B_en,
Vector_B_wENA0 => BRAM_B_wen,
Vector_C_addr0 => BRAM_C_addr,
Vector_C_dIN0 => BRAM_C_din,
Vector_C_dOUT0 => BRAM_C_dout,
Vector_C_rENA0 => BRAM_C_en,
Vector_C_wENA0 => BRAM_C_wen,
chan1_channelDataIn => M_AXIS_TDATA,
chan1_channelDataOut => S_AXIS_TDATA,
chan1_exists => S_AXIS_Tvalid,
chan1_full => not M_AXIS_Tready,
chan1_channelRead => S_AXIS_Tready,
chan1_channelWrite => M_AXIS_tvalid,
clock_sig => ap_clk,
reset_sig => ap_rst
);
end architecture implementation;
| bsd-3-clause |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_hwt_exit_v1_00_a/hdl/vhdl/plb_hwt_exit.vhd | 2 | 10401 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library plb_hwti_v1_00_a;
library plb_hwt_exit_v1_00_a;
use plb_hwti_v1_00_a.all;
entity plb_hwt_exit is
generic
(
C_MANAG_BASE : std_logic_vector := x"60000000";
C_SCHED_BASE : std_logic_vector := x"61000000";
C_MUTEX_BASE : std_logic_vector := x"75000000";
C_CONDV_BASE : std_logic_vector := x"74000000";
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_PLB_NUM_MASTERS : integer := 8;
C_PLB_MID_WIDTH : integer := 3;
C_FAMILY : string := "virtex2p"
);
port
(
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_MErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_PLB_AWIDTH-1);
PLB_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1)
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity plb_hwt_exit;
architecture imp of plb_hwt_exit is
signal HWTI2USER_READ : std_logic;
signal HWTI2USER_DATA : std_logic_vector(0 to 63);
signal HWTI2USER_CONTROL : std_logic;
signal HWTI2USER_EXISTS : std_logic;
signal USER2HWTI_WRITE : std_logic;
signal USER2HWTI_DATA : std_logic_vector(0 to 63);
signal USER2HWTI_CONTROL : std_logic;
signal USER2HWTI_FULL : std_logic;
signal U2HLOW_M_WRITE : std_logic;
signal U2HLOW_M_DATA : std_logic_vector(0 to 31);
signal U2HLOW_M_CONTROL : std_logic;
signal U2HLOW_M_FULL : std_logic;
signal U2HHIGH_M_WRITE : std_logic;
signal U2HHIGH_M_DATA : std_logic_vector(0 to 31);
signal U2HHIGH_M_CONTROL : std_logic;
signal U2HHIGH_M_FULL : std_logic;
signal H2ULOW_S_READ : std_logic;
signal H2ULOW_S_DATA : std_logic_vector(0 to 31);
signal H2ULOW_S_CONTROL : std_logic;
signal H2ULOW_S_EXISTS : std_logic;
signal H2UHIGH_S_READ : std_logic;
signal H2UHIGH_S_DATA : std_logic_vector(0 to 31);
signal H2UHIGH_S_CONTROL : std_logic;
signal H2UHIGH_S_EXISTS : std_logic;
begin
ihwti : entity plb_hwti_v1_00_a.plb_hwti
generic map
(
C_MANAG_BASE => C_MANAG_BASE,
C_SCHED_BASE => C_SCHED_BASE,
C_MUTEX_BASE => C_MUTEX_BASE,
C_CONDV_BASE => C_CONDV_BASE,
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_PLB_NUM_MASTERS => C_PLB_NUM_MASTERS,
C_PLB_MID_WIDTH => C_PLB_MID_WIDTH,
C_FAMILY => C_FAMILY
)
port map
(
U2HLOW_M_WRITE => U2HLOW_M_WRITE,
U2HLOW_M_DATA => U2HLOW_M_DATA,
U2HLOW_M_CONTROL => U2HLOW_M_CONTROL,
U2HLOW_M_FULL => U2HLOW_M_FULL,
U2HHIGH_M_WRITE => U2HHIGH_M_WRITE,
U2HHIGH_M_DATA => U2HHIGH_M_DATA,
U2HHIGH_M_CONTROL => U2HHIGH_M_CONTROL,
U2HHIGH_M_FULL => U2HHIGH_M_FULL,
H2ULOW_S_READ => H2ULOW_S_READ,
H2ULOW_S_DATA => H2ULOW_S_DATA,
H2ULOW_S_CONTROL => H2ULOW_S_CONTROL,
H2ULOW_S_EXISTS => H2ULOW_S_EXISTS,
H2UHIGH_S_READ => H2UHIGH_S_READ,
H2UHIGH_S_DATA => H2UHIGH_S_DATA,
H2UHIGH_S_CONTROL => H2UHIGH_S_CONTROL,
H2UHIGH_S_EXISTS => H2UHIGH_S_EXISTS,
PLB_Clk => PLB_Clk,
PLB_Rst => PLB_Rst,
Sl_addrAck => Sl_addrAck,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
PLB_abort => PLB_abort,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_PAValid => PLB_PAValid,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_compress => M_compress,
M_guarded => M_guarded,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_ordered => M_ordered,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize
);
ihwt : entity plb_hwt_exit_v1_00_a.hwtexit
port map
(
clk => PLB_Clk,
rst => PLB_Rst,
HWTI2USER_READ => HWTI2USER_READ,
HWTI2USER_DATA => HWTI2USER_DATA,
HWTI2USER_CONTROL => HWTI2USER_CONTROL,
HWTI2USER_EXISTS => HWTI2USER_EXISTS,
USER2HWTI_WRITE => USER2HWTI_WRITE,
USER2HWTI_DATA => USER2HWTI_DATA,
USER2HWTI_CONTROL => USER2HWTI_CONTROL,
USER2HWTI_FULL => USER2HWTI_FULL
);
H2ULOW_S_READ <= HWTI2USER_READ;
H2UHIGH_S_READ <= HWTI2USER_READ;
HWTI2USER_DATA <= H2UHIGH_S_DATA & H2ULOW_S_DATA;
HWTI2USER_CONTROL <= H2UHIGH_S_CONTROL or H2ULOW_S_CONTROL;
HWTI2USER_EXISTS <= H2UHIGH_S_EXISTS and H2ULOW_S_EXISTS;
U2HLOW_M_WRITE <= USER2HWTI_WRITE;
U2HHIGH_M_WRITE <= USER2HWTI_WRITE;
U2HLOW_M_DATA <= USER2HWTI_DATA(32 to 63);
U2HHIGH_M_DATA <= USER2HWTI_DATA(0 to 31);
U2HLOW_M_CONTROL <= USER2HWTI_CONTROL;
U2HHIGH_M_CONTROL <= USER2HWTI_CONTROL;
USER2HWTI_FULL <= U2HLOW_M_FULL or U2HHIGH_M_FULL;
end imp;
| bsd-3-clause |
jevinskie/aes-over-pcie | source/add_round_key_p.vhd | 1 | 763 | -- File name: add_round_key_p.vhd
-- Created: 2009-04-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: parallel add round key stage
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_round_key_p is
port (
data_in : in state_type;
key_in : in state_type;
data_out : out state_type
);
end entity add_round_key_p;
architecture dataflow of add_round_key_p is
begin
process(data_in, key_in)
begin
for i in index loop
for j in index loop
data_out(i, j) <= data_in(i, j) xor key_in(i, j);
end loop;
end loop;
end process;
end architecture dataflow;
| bsd-3-clause |
l3dlp/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
JorisBolsens/PYNQ | Pynq-Z1/vivado/ip/dvi2rgb_v1_6/src/TMDS_Decoder.vhd | 14 | 10863 | -------------------------------------------------------------------------------
--
-- File: TMDS_Decoder.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to one TMDS data channel and decodes TMDS data
-- according to DVI specifications. It phase aligns the data channel,
-- deserializes the stream, eliminates skew between data channels and decodes
-- data in the end.
-- sDataIn_p/n -> buffer -> de-serialize -> channel de-skew -> decode -> pData
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TMDS_Decoder is
Generic (
kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection
kTimeoutMs : natural := 50; --what is the maximum time interval for a blank to be detected
kRefClkFrqMHz : natural := 200; --what is the RefClk frequency
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
RefClk : std_logic; --200 MHz reference clock
aRst : in std_logic; --asynchronous reset; must be reset when PixelClk/SerialClk is not within spec
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Decoded parallel data
pDataIn : out std_logic_vector(7 downto 0);
pC0 : out std_logic;
pC1 : out std_logic;
pVde : out std_logic;
-- Channel bonding (three data channels in total)
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pMeVld : out std_logic;
pMeRdy : out std_logic;
--Status and debug
pRst : in std_logic; -- Synchronous reset to restart lock procedure
pAlignErr : out std_logic;
pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0));
end TMDS_Decoder;
architecture Behavioral of TMDS_Decoder is
constant kBitslipDelay : natural := 3; --three-period delay after bitslip
signal pAlignRst, pLockLostRst_n : std_logic;
signal pBitslipCnt : natural range 0 to kBitslipDelay - 1 := kBitslipDelay - 1;
signal pDataIn8b : std_logic_vector(7 downto 0);
signal pDataInBnd : std_logic_vector(9 downto 0);
signal pDataInRaw : std_logic_vector(9 downto 0);
signal pMeRdy_int, pAligned, pAlignErr_int, pAlignErr_q, pBitslip : std_logic;
signal pIDLY_LD, pIDLY_CE, pIDLY_INC : std_logic;
signal pIDLY_CNT : std_logic_vector(kIDLY_TapWidth-1 downto 0);
-- Timeout Counter End
constant kTimeoutEnd : natural := kTimeoutMs * 1000 * kRefClkFrqMHz;
signal rTimeoutCnt : natural range 0 to kTimeoutEnd-1;
signal pTimeoutRst, pTimeoutOvf, rTimeoutRst, rTimeoutOvf : std_logic;
begin
-- Deserialization block
InputSERDES_X: entity work.InputSERDES
generic map (
kIDLY_TapWidth => kIDLY_TapWidth,
kParallelWidth => 10 -- TMDS uses 1:10 serialization
)
port map (
PixelClk => PixelClk,
SerialClk => SerialClk,
sDataIn_p => sDataIn_p,
sDataIn_n => sDataIn_n,
--Encoded parallel data (raw)
pDataIn => pDataInRaw,
--Control for phase alignment
pBitslip => pBitslip,
pIDLY_LD => pIDLY_LD,
pIDLY_CE => pIDLY_CE,
pIDLY_INC => pIDLY_INC,
pIDLY_CNT => pIDLY_CNT,
aRst => aRst
);
-- reset min two period (ISERDESE2 requirement)
-- de-assert synchronously with CLKDIV, min two period (ISERDESE2 requirement)
--The timeout counter runs on RefClk, because it's a fixed frequency we can measure timeout
--independently of the TMDS Clk
--The xTimeoutRst and xTimeoutOvf signals need to be synchronized back-and-forth
TimeoutCounter: process(RefClk)
begin
if Rising_Edge(RefClk) then
if (rTimeoutRst = '1') then
rTimeoutCnt <= 0;
elsif (rTimeoutOvf = '0') then
rTimeoutCnt <= rTimeoutCnt + 1;
end if;
end if;
end process TimeoutCounter;
rTimeoutOvf <= '0' when rTimeoutCnt /= kTimeoutEnd - 1 else
'1';
SyncBaseOvf: entity work.SyncBase
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst,
InClk => RefClk,
iIn => rTimeoutOvf,
OutClk => PixelClk,
oOut => pTimeoutOvf);
SyncBaseRst: entity work.SyncBase
generic map (
kResetTo => '1',
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst,
InClk => PixelClk,
iIn => pTimeoutRst,
OutClk => RefClk,
oOut => rTimeoutRst);
-- Phase alignment controller to lock onto data stream
PhaseAlignX: entity work.PhaseAlign
generic map (
kUseFastAlgorithm => false,
kCtlTknCount => kCtlTknCount,
kIDLY_TapValuePs => kIDLY_TapValuePs,
kIDLY_TapWidth => kIDLY_TapWidth
)
port map (
pRst => pAlignRst,
PixelClk => PixelClk,
pTimeoutOvf => pTimeoutOvf,
pTimeoutRst => pTimeoutRst,
pData => pDataInRaw,
pIDLY_CE => pIDLY_CE,
pIDLY_INC => pIDLY_INC,
pIDLY_CNT => pIDLY_CNT,
pIDLY_LD => pIDLY_LD,
pAligned => pAligned,
pError => pAlignErr_int,
pEyeSize => pEyeSize);
pAlignErr <= pAlignErr_int;
pMeVld <= pAligned;
-- Bitslip when phase alignment exhausted the whole tap range and still no lock
Bitslip: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAlignErr_q <= pAlignErr_int;
pBitslip <= not pAlignErr_q and pAlignErr_int; -- single pulse bitslip on failed alignment attempt
end if;
end process Bitslip;
ResetAlignment: process(PixelClk, aRst)
begin
if (aRst = '1') then
pAlignRst <= '1';
elsif Rising_Edge(PixelClk) then
if (pRst = '1' or pBitslip = '1') then
pAlignRst <= '1';
elsif (pBitslipCnt = 0) then
pAlignRst <= '0';
end if;
end if;
end process ResetAlignment;
-- Reset phase aligment module after bitslip + 3 CLKDIV cycles (ISERDESE2 requirement)
BitslipDelay: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pBitslip = '1') then
pBitslipCnt <= kBitslipDelay - 1;
elsif (pBitslipCnt /= 0) then
pBitslipCnt <= pBitslipCnt - 1;
end if;
end if;
end process BitslipDelay;
-- Channel de-skew (bonding)
ChannelBondX: entity work.ChannelBond
port map (
PixelClk => PixelClk,
pDataInRaw => pDataInRaw,
pMeVld => pAligned,
pOtherChVld => pOtherChVld,
pOtherChRdy => pOtherChRdy,
pDataInBnd => pDataInBnd,
pMeRdy => pMeRdy_int);
pMeRdy <= pMeRdy_int;
-- Below performs the 10B-8B decoding function
-- DVI Specification: Section 3.3.3, Figure 3-6, page 31.
pDataIn8b <= pDataInBnd(7 downto 0) when pDataInBnd(9) = '0' else
not pDataInBnd(7 downto 0);
TMDS_Decode: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pMeRdy_int = '1' and pOtherChRdy = "11") then
pDataIn <= x"00"; --added for VGA-compatibility (blank pixel needed during blanking)
case (pDataInBnd) is
--Control tokens decode straight to C0, C1 values
when kCtlTkn0 =>
pC0 <= '0';
pC1 <= '0';
pVde <= '0';
when kCtlTkn1 =>
pC0 <= '1';
pC1 <= '0';
pVde <= '0';
when kCtlTkn2 =>
pC0 <= '0';
pC1 <= '1';
pVde <= '0';
when kCtlTkn3 =>
pC0 <= '1';
pC1 <= '1';
pVde <= '0';
--If not control token, it's encoded data
when others =>
pVde <= '1';
pDataIn(0) <= pDataIn8b(0);
for iBit in 1 to 7 loop
if (pDataInBnd(8) = '1') then
pDataIn(iBit) <= pDataIn8b(iBit) xor pDataIn8b(iBit-1);
else
pDataIn(iBit) <= pDataIn8b(iBit) xnor pDataIn8b(iBit-1);
end if;
end loop;
end case;
else --if we are not aligned on all channels, gate outputs
pC0 <= '0';
pC1 <= '0';
pVde <= '0';
pDataIn <= x"00";
end if;
end if;
end process;
end Behavioral; | bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mult16_16/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 12 | 103154 | `protect begin_protected
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`protect end_protected
| bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 12 | 103154 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224)
`protect data_block
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`protect end_protected
| bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul16_16/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 12 | 103154 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224)
`protect data_block
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| bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/492adc01b6634d6a/mul8_8_sim_netlist.vhdl | 1 | 179563 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:57:15 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul8_8_sim_netlist.vhdl
-- Design : mul8_8
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
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`protect key_block
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 8;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 15;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "kintexu";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 8;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 8;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 3;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 15;
attribute C_OUT_LOW of i_mult : label is 0;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12_viv
port map (
A(7 downto 0) => A(7 downto 0),
B(7 downto 0) => B(7 downto 0),
CE => '0',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mul8_8,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 8;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 15;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12
port map (
A(7 downto 0) => A(7 downto 0),
B(7 downto 0) => B(7 downto 0),
CE => '1',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
| bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_8/mul8_8_sim_netlist.vhdl | 1 | 177383 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:57:16 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_8/mul8_8_sim_netlist.vhdl
-- Design : mul8_8
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul8_8_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mul8_8_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mul8_8_mult_gen_v12_0_12 : entity is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mul8_8_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mul8_8_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mul8_8_mult_gen_v12_0_12 : entity is 8;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mul8_8_mult_gen_v12_0_12 : entity is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mul8_8_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mul8_8_mult_gen_v12_0_12 : entity is 15;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mul8_8_mult_gen_v12_0_12 : entity is "kintexu";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mul8_8_mult_gen_v12_0_12 : entity is "mult_gen_v12_0_12";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul8_8_mult_gen_v12_0_12 : entity is "yes";
end mul8_8_mult_gen_v12_0_12;
architecture STRUCTURE of mul8_8_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 8;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 8;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 3;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 15;
attribute C_OUT_LOW of i_mult : label is 0;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.mul8_8_mult_gen_v12_0_12_viv
port map (
A(7 downto 0) => A(7 downto 0),
B(7 downto 0) => B(7 downto 0),
CE => '0',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul8_8 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mul8_8 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mul8_8 : entity is "mul8_8,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul8_8 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mul8_8 : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end mul8_8;
architecture STRUCTURE of mul8_8 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 8;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 15;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.mul8_8_mult_gen_v12_0_12
port map (
A(7 downto 0) => A(7 downto 0),
B(7 downto 0) => B(7 downto 0),
CE => '1',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
| bsd-3-clause |
drhodes/jade2hdl | test-data/vhdl-examples/test-gen-make-module.vhdl | 1 | 7062 | ------------------------------------------------------------------
-- VHDL PRELUDE --------------------------------------------------
-- combinational module -------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_user_And41 IS
port (A : in std_logic; B : in std_logic; C : in std_logic; D : in std_logic; vout : out std_logic);
end mod_user_And41;
architecture struct of mod_user_And41 is
-- node declarations
signal w1, wire_x0620 : std_logic;
begin
-- each submodule is wired up here.
mod_user_AND2_nagPx : entity work.mod_user_AND2 port map (in1 => A, in2 => B, out1 => w1);
mod_user_AND2_LxVDj : entity work.mod_user_AND2 port map (in1 => C, in2 => D, out1 => wire_x0620);
mod_user_AND2_7KpMR : entity work.mod_user_AND2 port map (in1 => w1, in2 => wire_x0620, out1 => vout);
end struct;
-- Combinational testbench. ---------------------------------------
library STD;
use STD.textio.all; -- basic I/O
use STD.env.all;
library IEEE;
use IEEE.std_logic_1164.all; -- basic logic types
use IEEE.std_logic_textio.all; -- I/O for logic types
use ieee.numeric_std.all;
entity /user/And41 is end entity /user/And41;
architecture behaviour of /user/And41 is
A, B, C, D, vout: std_logic;
begin
dut : entity work.mod_user_And41 port map (A => A, B => B, C => C, D => D, vout => vout);
process
begin
-------------------------------------------------------
A <= '1';
B <= '1';
C <= '1';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 1";
report "expecting: vout = '1'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 1: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '1';
C <= '1';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 2";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 2: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '1';
C <= '0';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 3";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 3: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '1';
C <= '0';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 4";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 4: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '0';
C <= '1';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 5";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 5: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '0';
C <= '1';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 6";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 6: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '0';
C <= '0';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 7";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 7: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '0';
C <= '0';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 8";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 8: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '1';
C <= '1';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 9";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 9: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '1';
C <= '1';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 10";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 10: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '1';
C <= '0';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 11";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 11: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '1';
C <= '0';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 12";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 12: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '0';
C <= '1';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 13";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 13: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '0';
C <= '1';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 14";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 14: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '0';
C <= '0';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 15";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 15: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '0';
C <= '0';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report "// This comment is included in vhdl test cases."
report "TestNum 16";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 16: PASSED" & LF);
end if;
wait for 1.0 ns;
finish(0);
end process;
end behavior;
| bsd-3-clause |
JorisBolsens/PYNQ | Pynq-Z1/vivado/ip/trace_cntrl_1_2/hdl/vhdl/trace_cntrl_mul_32s_32s_32_7.vhd | 4 | 3069 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity trace_cntrl_mul_32s_32s_32_7_MulnS_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(32 - 1 downto 0);
b: in std_logic_vector(32 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of trace_cntrl_mul_32s_32s_32_7_MulnS_0 is
signal tmp_product : std_logic_vector(32 - 1 downto 0);
signal a_i : std_logic_vector(32 - 1 downto 0);
signal b_i : std_logic_vector(32 - 1 downto 0);
signal p_tmp : std_logic_vector(32 - 1 downto 0);
signal a_reg0 : std_logic_vector(32 - 1 downto 0);
signal b_reg0 : std_logic_vector(32 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(32 - 1 downto 0);
signal buff1 : std_logic_vector(32 - 1 downto 0);
signal buff2 : std_logic_vector(32 - 1 downto 0);
signal buff3 : std_logic_vector(32 - 1 downto 0);
signal buff4 : std_logic_vector(32 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff4;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 32));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity trace_cntrl_mul_32s_32s_32_7 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of trace_cntrl_mul_32s_32s_32_7 is
component trace_cntrl_mul_32s_32s_32_7_MulnS_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
trace_cntrl_mul_32s_32s_32_7_MulnS_0_U : component trace_cntrl_mul_32s_32s_32_7_MulnS_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul16_16/mul16_16_stub.vhdl | 2 | 1351 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:58:33 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul16_16/mul16_16_stub.vhdl
-- Design : mul16_16
-- Purpose : Stub declaration of top-level module interface
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mul16_16 is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end mul16_16;
architecture stub of mul16_16 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[15:0],B[15:0],P[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_12,Vivado 2016.4";
begin
end;
| bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_gen_0/sim/mult_gen_0.vhd | 1 | 4811 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mult_gen_0 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mult_gen_0;
ARCHITECTURE mult_gen_0_arch OF mult_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 3,
C_A_WIDTH => 8,
C_A_TYPE => 1,
C_B_WIDTH => 16,
C_B_TYPE => 0,
C_OUT_HIGH => 23,
C_OUT_LOW => 8,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mult_gen_0_arch;
| bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/1a38f03650b0a66f/mult16_16_stub.vhdl | 1 | 1470 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:32:46 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult16_16_stub.vhdl
-- Design : mult16_16
-- Purpose : Stub declaration of top-level module interface
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[15:0],B[15:0],P[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_12,Vivado 2016.4";
begin
end;
| bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/d74462b9dbd19694/mult_17x16_stub.vhdl | 1 | 1474 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:43:33 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_17x16_stub.vhdl
-- Design : mult_17x16
-- Purpose : Stub declaration of top-level module interface
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 16 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 24 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[16:0],B[15:0],P[24:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_12,Vivado 2016.4";
begin
end;
| bsd-3-clause |
drhodes/jade2hdl | test-data/vhdl/AND2/AND2.vhdl | 1 | 674 | -- library IEEE;
-- use IEEE.STD_LOGIC_1164.ALL;
ENTITY AND2 IS
PORT (in1 : IN std_logic;
in2 : IN std_logic;
out1 : OUT std_logic) ;
END ENTITY AND2 ;
ARCHITECTURE Behavioral OF AND2 IS
BEGIN
PROCESS IS
BEGIN
out1 <= in1 AND in2 ;
END PROCESS ;
END ARCHITECTURE Behavioral ;
entity RAWR IS
port ( a : in std_logic;
b : in std_logic;
c : out std_logic);
end RAWR;
architecture struct of RAWR is
component AND2 PORT (in1 : IN std_logic;
in2 : IN std_logic;
out1 : OUT std_logic);
end component;
begin
unit1 : AND2 port map (in1 => a, in2 => b, out1 => c);
end struct;
| bsd-3-clause |
drhodes/jade2hdl | test-data/vhdl/pddLNXO0pWNvo.vhdl | 1 | 6653 | ------------------------------------------------------------------
-- VHDL PRELUDE --------------------------------------------------
-- combinational module -------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_user_And41 IS
port (A : in std_logic; B : in std_logic; C : in std_logic; D : in std_logic; vout : out std_logic);
end mod_user_And41;
architecture struct of mod_user_And41 is
-- node declarations
signal w1, wire_x0620 : std_logic;
begin
-- each submodule is wired up here.
mod_user_AND2_nagPx : entity work.mod_user_AND2 port map (in1 => A, in2 => B, out1 => w1);
mod_user_AND2_LxVDj : entity work.mod_user_AND2 port map (in1 => C, in2 => D, out1 => wire_x0620);
mod_user_AND2_7KpMR : entity work.mod_user_AND2 port map (in1 => w1, in2 => wire_x0620, out1 => vout);
end struct;
-- Combinational testbench. ---------------------------------------
library STD;
use STD.textio.all; -- basic I/O
use STD.env.all;
library IEEE;
use IEEE.std_logic_1164.all; -- basic logic types
use IEEE.std_logic_textio.all; -- I/O for logic types
use ieee.numeric_std.all;
entity mod_user_And41 is end entity mod_user_And41;
architecture behaviour of mod_user_And41 is
A, B, C, D, vout: std_logic;
begin
dut : entity work.mod_user_And41 port map (A => A, B => B, C => C, D => D, vout => vout);
process
begin
-------------------------------------------------------
A <= '1';
B <= '1';
C <= '1';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 1";
report "expecting: vout = '1'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 1: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '1';
C <= '1';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 2";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 2: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '1';
C <= '0';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 3";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 3: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '1';
C <= '0';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 4";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 4: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '0';
C <= '1';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 5";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 5: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '0';
C <= '1';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 6";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 6: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '0';
C <= '0';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 7";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 7: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '1';
B <= '0';
C <= '0';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 8";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 8: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '1';
C <= '1';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 9";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 9: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '1';
C <= '1';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 10";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 10: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '1';
C <= '0';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 11";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 11: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '1';
C <= '0';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 12";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 12: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '0';
C <= '1';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 13";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 13: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '0';
C <= '1';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 14";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 14: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '0';
C <= '0';
D <= '1';
wait for 99.0 ns;
if vout /= '0' then
report ""
report "TestNum 15";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 15: PASSED" & LF);
end if;
wait for 1.0 ns;
A <= '0';
B <= '0';
C <= '0';
D <= '0';
wait for 99.0 ns;
if vout /= '0' then
report "// This comment is included in vhdl test cases."
report "TestNum 16";
report "expecting: vout = '0'";
report "got : vout = " & to_string(vout);
stop(-1);
else
write(OUTPUT, "TEST 16: PASSED" & LF);
end if;
wait for 1.0 ns;
finish(0);
end process;
end behavior;
| bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/mul8_16_sim_netlist.vhdl | 1 | 287556 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:33:05 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/mul8_16_sim_netlist.vhdl
-- Design : mul8_16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul8_16_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mul8_16_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mul8_16_mult_gen_v12_0_12 : entity is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mul8_16_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mul8_16_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mul8_16_mult_gen_v12_0_12 : entity is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mul8_16_mult_gen_v12_0_12 : entity is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mul8_16_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mul8_16_mult_gen_v12_0_12 : entity is 23;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mul8_16_mult_gen_v12_0_12 : entity is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mul8_16_mult_gen_v12_0_12 : entity is "kintexu";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mul8_16_mult_gen_v12_0_12 : entity is "mult_gen_v12_0_12";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul8_16_mult_gen_v12_0_12 : entity is "yes";
end mul8_16_mult_gen_v12_0_12;
architecture STRUCTURE of mul8_16_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 8;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 16;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 3;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 23;
attribute C_OUT_LOW of i_mult : label is 8;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.mul8_16_mult_gen_v12_0_12_viv
port map (
A(7 downto 0) => A(7 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '0',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul8_16 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mul8_16 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mul8_16 : entity is "mul8_16,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul8_16 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mul8_16 : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end mul8_16;
architecture STRUCTURE of mul8_16 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 23;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.mul8_16_mult_gen_v12_0_12
port map (
A(7 downto 0) => A(7 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '1',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
| bsd-3-clause |
JorisBolsens/PYNQ | Pynq-Z1/vivado/ip/rgb2dvi_v1_2/src/ClockGen.vhd | 9 | 8885 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ClockGen is
Generic (
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive : string := "MMCM"); -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port (
PixelClkIn : in STD_LOGIC;
PixelClkOut : out STD_LOGIC;
SerialClk : out STD_LOGIC;
aRst : in STD_LOGIC;
aLocked : out STD_LOGIC);
end ClockGen;
architecture Behavioral of ClockGen is
component SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end component SyncAsync;
component ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end component ResetBridge;
signal PixelClkInX1, PixelClkInX5, FeedbackClk : std_logic;
signal aLocked_int, pLocked, pRst, pLockWasLost : std_logic;
signal pLocked_q : std_logic_vector(2 downto 0) := (others => '1');
begin
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal pRst can be used as
-- asynchronous reset for any flip-flop in the PixelClkIn domain, since it will be de-asserted
-- synchronously.
LockLostReset: ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => PixelClkIn,
oRst => pRst);
PLL_LockSyncAsync: SyncAsync
port map (
aReset => '0',
aIn => aLocked_int,
OutClk => PixelClkIn,
oOut => pLocked);
PLL_LockLostDetect: process(PixelClkIn)
begin
if (pRst = '1') then
pLocked_q <= (others => '1');
pLockWasLost <= '1';
elsif Rising_Edge(PixelClkIn) then
pLocked_q <= pLocked_q(pLocked_q'high-1 downto 0) & pLocked;
pLockWasLost <= (not pLocked_q(0) or not pLocked_q(1)) and pLocked_q(2); --two-pulse
end if;
end process;
-- The TMDS Clk channel carries a character-rate frequency reference
-- In a single Clk period a whole character (10 bits) is transmitted
-- on each data channel. For deserialization of data channel a faster,
-- serial clock needs to be generated. In 7-series architecture an
-- OSERDESE2 primitive doing a 10:1 deserialization in DDR mode needs
-- a fast 5x clock and a slow 1x clock. These two clocks are generated
-- below with an MMCME2_ADV/PLLE2_ADV.
-- Caveats:
-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate
-- a 5x fast clock.
-- While changes in the frequency of the TMDS Clk are tracked by the
-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO
-- frequency limits are not met. In other words, there is no single
-- set of MMCM multiply and divide values that can work for the whole
-- range of resolutions and pixel clock frequencies.
-- For example: MMCM_FVCOMIN = 600 MHz
-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade
-- while FVCO = FIN * MULT_F
-- The TMDS Clk for 720p resolution in 74.25 MHz
-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX
-- However, the TMDS Clk for 1080p resolution in 148.5 MHz
-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX
-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result
-- in a correct VCO frequency, while still generating 5x and 1x clocks
-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible
-- frequencies. PLLE2_ADV could work only with BUFGs, which limits
-- the maximum achievable frequency. The reason is that only the MMCM
-- has dedicated route to BUFIO.
-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to
-- generate the 1x clock.
GenMMCM: if kClkPrimitive = "MMCM" generate
DVI_ClkGenerator: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => real(kClkRange) * 5.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => kClkRange * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => real(kClkRange) * 6.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClk,
CLKFBOUTB => open,
CLKOUT0 => PixelClkInX5,
CLKOUT0B => open,
CLKOUT1 => PixelClkInX1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => FeedbackClk,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => aLocked_int,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => pLockWasLost);
end generate;
GenPLL: if kClkPrimitive /= "MMCM" generate
DVI_ClkGenerator: PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => (kClkRange + 1) * 5,
CLKFBOUT_PHASE => 0.000,
CLKIN1_PERIOD => real(kClkRange) * 6.25,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.010,
STARTUP_WAIT => "FALSE",
CLKOUT0_DIVIDE => (kClkRange + 1) * 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => (kClkRange + 1) * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClk,
CLKOUT0 => PixelClkInX5,
CLKOUT1 => PixelClkInX1,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- Input clock control
CLKFBIN => FeedbackClk,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Other control and status signals
LOCKED => aLocked_int,
PWRDWN => '0',
RST => pLockWasLost);
end generate;
--No buffering used
--These clocks will only drive the OSERDESE2 primitives
SerialClk <= PixelClkInX5;
PixelClkOut <= PixelClkInX1;
aLocked <= aLocked_int;
end Behavioral;
| bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_17x16/hdl/xbip_utils_v3_0_vh_rfs.vhd | 13 | 163693 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 119040)
`protect data_block
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`protect end_protected
| bsd-3-clause |