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mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_0_0/sim/design_1_axi_bram_ctrl_0_0.vhd | 1 | 15,621 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_0;
ARCHITECTURE design_1_axi_bram_ctrl_0_0_arch OF design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 2,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 1,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_0_arch;
| gpl-3.0 | 6c2d8e4ea5156e657c4299edc3817828 | 0.670572 | 3.09879 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/nandtree.vhd | 1 | 2,422 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: nandtree
-- File: nandtree.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Nand-tree with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity nandtree is
generic(
tech : integer := inferred;
width : integer := 2;
imp : integer := 0 );
port( i : in std_logic_vector(width-1 downto 0);
o : out std_ulogic;
en : in std_ulogic
);
end entity;
architecture rtl of nandtree is
component rh_lib18t_nand_tree
generic (npins : integer := 2);
port(
-- Input Signlas: --
TEST_MODE : in std_logic;
IN_PINS_BUS : in std_logic_vector(npins-1 downto 0);
NAND_TREE_OUT : out std_logic
);
end component;
function fnandtree(v : std_logic_vector) return std_ulogic is
variable a : std_logic_vector(v'length-1 downto 0);
variable b : std_logic_vector(v'length downto 0);
begin
a := v; b(0) := '1';
for i in 0 to v'length-1 loop
b(i+1) := a(i) nand b(i);
end loop;
return b(v'length);
end;
begin
behav : if tech /= rhlib18t generate
o <= fnandtree(i);
end generate;
rhlib : if tech = rhlib18t generate
rhnand : rh_lib18t_nand_tree generic map (width)
port map (en, i, o);
end generate;
end;
| gpl-2.0 | be4a678d408f8cdbcc0956738d05e5db | 0.598679 | 3.749226 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/inferred/memory_inferred.vhd | 1 | 10,012 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_gen_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Behavioural memory generators
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_reg is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram_reg is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of memarr : signal is "registers";
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
-- synchronous 2-port ram, common clock
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
end;
-- synchronous 2-port ram, common clock, flip-flops
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p_reg is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p_reg is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
signal wa, ra : std_logic_vector (abits -1 downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of rfd : signal is "registers";
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then ra <= rdaddress; end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then ra <= rdaddress; end if;
end process;
end generate;
q <= rfd(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_3p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_3p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
end if;
end process;
rdata1 <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2 <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_4p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40; g0addr: integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
raddr3 : in std_logic_vector((abits -1) downto 0);
re3 : in std_ulogic;
rdata3 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_4p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, ra3, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if (re3 = '1')
-- pragma translate_off
and (conv_integer(raddr3) < numregs)
-- pragma translate_on
then ra3 <= raddr3; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
if g0addr > 0 and g0addr < numregs then
memarr(g0addr) <= (others => '0');
end if;
end if;
end process;
rdata1 <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2 <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
rdata3 <= din when (wr = '1') and (wa = ra3) and (wrfst = 1)
else memarr(conv_integer(ra3));
end;
| gpl-2.0 | 23337c5e77e07a7548ce682719bba249 | 0.615761 | 3.325141 | false | false | false | false |
freecores/usb_fpga_1_11 | examples/usb-fpga-2.04/2.04b/intraffic/fpga/intraffic.vhd | 42 | 1,939 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity intraffic is
port(
RESET : in std_logic;
CONT : in std_logic;
IFCLK : in std_logic;
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic
);
end intraffic;
architecture RTL of intraffic is
----------------------------
-- test pattern generator --
----------------------------
-- 30 bit counter
signal GEN_CNT : std_logic_vector(29 downto 0);
signal INT_CNT : std_logic_vector(6 downto 0);
signal FIFO_WORD : std_logic;
begin
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1'; -- no data alignment
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
INT_CNT <= ( others => '0' );
FIFO_WORD <= '0';
SLWR <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
if CONT = '1' or FLAGB = '1'
then
if FIFO_WORD = '0'
then
FD(14 downto 0) <= GEN_CNT(14 downto 0);
else
FD(14 downto 0) <= GEN_CNT(29 downto 15);
end if;
FD(15) <= FIFO_WORD;
if FIFO_WORD = '1'
then
GEN_CNT <= GEN_CNT + '1';
if INT_CNT = conv_std_logic_vector(99,7)
then
INT_CNT <= ( others => '0' );
else
INT_CNT <= INT_CNT + '1';
end if;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' )
then
SLWR <= '1';
else
SLWR <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
| gpl-3.0 | 94eefe5945e2aefb4085c62b1177d44a | 0.488912 | 3.269815 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-kc705/sgmii_kc705.vhd | 1 | 25,153 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sgmii
-- File: sgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to SGMII interface
------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This is the top level vhdl example design for the
-- Ethernet 1000BASE-X PCS/PMA core.
--
-- This design example instantiates IOB flip-flops
-- and input/output buffers on the GMII.
--
-- A Transmitter Elastic Buffer is instantiated on the Tx
-- GMII path to perform clock compenstation between the
-- core and the external MAC driving the Tx GMII.
--
-- This design example can be synthesised.
--
--
--
-- ----------------------------------------------------------------
-- | Example Design |
-- | |
-- | ---------------------------------------------- |
-- | | Core Block (wrapper) | |
-- | | | |
-- | | -------------- -------------- | |
-- | | | Core | | tranceiver | | |
-- | | | | | | | |
-- | --------- | | | | | | |
-- | | | | | | | | | |
-- | | Tx | | | | | | | |
-- ---->|Elastic|----->| GMII |--------->| TXP |--------->
-- | |Buffer | | | Tx | | TXN | | |
-- | | | | | | | | | |
-- | --------- | | | | | | |
-- | GMII | | | | | | |
-- | IOBs | | | | | | |
-- | | | | | | | |
-- | | | GMII | | RXP | | |
-- <-------------------| Rx |<---------| RXN |<---------
-- | | | | | | | |
-- | | -------------- -------------- | |
-- | | | |
-- | ---------------------------------------------- |
-- | |
-- ----------------------------------------------------------------
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.net.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example design
--------------------------------------------------------------------------------
entity sgmii_kc705 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
autonegotiation : integer := 1
);
port(
-- Tranceiver Interface
sgmiii : in eth_sgmii_in_type;
sgmiio : out eth_sgmii_out_type;
-- GMII Interface (client MAC <=> PCS)
gmiii : out eth_in_type;
gmiio : in eth_out_type;
-- Asynchronous reset for entire core.
reset : in std_logic;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end sgmii_kc705;
architecture top_level of sgmii_kc705 is
------------------------------------------------------------------------------
-- Component Declaration for the Core Block (core wrapper).
------------------------------------------------------------------------------
component sgmii_block
port(
-- Transceiver Interface
------------------------
drpaddr_in : in std_logic_vector(8 downto 0);
drpclk_in : in std_logic;
drpdi_in : in std_logic_vector(15 downto 0);
drpdo_out : out std_logic_vector(15 downto 0);
drpen_in : in std_logic;
drprdy_out : out std_logic;
drpwe_in : in std_logic;
gtrefclk : in std_logic; -- Very high quality 125MHz clock for GT transceiver
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
txoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
mmcm_locked : in std_logic; -- Locked signal from MMCM
userclk : in std_logic; -- 62.5MHz clock.
userclk2 : in std_logic; -- 125MHz clock.
independent_clock_bufg : in std_logic;
pma_reset : in std_logic; -- transceiver PMA reset signal
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: MDIO Interface
-----------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
link_timer_value : in std_logic_vector(8 downto 0); -- Programmable Auto-Negotiation Link Timer Control
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic -- Input from PMD to indicate presence of optical input.
);
end component;
component MMCME2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
CLKFBOUT_USE_FINE_PS : boolean := FALSE;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
CLKOUT0_USE_FINE_PS : boolean := FALSE;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
CLKOUT1_USE_FINE_PS : boolean := FALSE;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
CLKOUT2_USE_FINE_PS : boolean := FALSE;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
CLKOUT3_USE_FINE_PS : boolean := FALSE;
CLKOUT4_CASCADE : boolean := FALSE;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
CLKOUT4_USE_FINE_PS : boolean := FALSE;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
CLKOUT5_USE_FINE_PS : boolean := FALSE;
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
CLKOUT6_USE_FINE_PS : boolean := FALSE;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
SS_EN : string := "FALSE";
SS_MODE : string := "CENTER_HIGH";
SS_MOD_PERIOD : integer := 10000;
STARTUP_WAIT : boolean := FALSE
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKFBOUTB : out std_ulogic := '0';
CLKFBSTOPPED : out std_ulogic := '0';
CLKINSTOPPED : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT0B : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT1B : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT2B : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT3B : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUT6 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
----- component IBUFDS_GTE2 -----
component IBUFDS_GTE2
generic (
CLKCM_CFG : boolean := TRUE;
CLKRCV_TRST : boolean := TRUE;
CLKSWING_CFG : bit_vector := "11"
);
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
------------------------------------------------------------------------------
-- internal signals used in this top level example design.
------------------------------------------------------------------------------
-- clock generation signals for tranceiver
signal gtrefclk : std_logic;
signal txoutclk : std_logic;
signal resetdone : std_logic;
signal mmcm_locked : std_logic;
signal mmcm_reset : std_logic;
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal userclk : std_logic;
signal userclk2 : std_logic;
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0);
signal pma_reset : std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic;
signal sgmii_clk_f : std_logic;
signal sgmii_clk_en : std_logic;
signal sgmii_clk : std_logic;
signal sgmii_clk_int : std_logic;
-- GMII signals
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal gmii_isolate : std_logic;
signal gmii_txd_int : std_logic_vector(7 downto 0);
signal gmii_tx_en_int : std_logic;
signal gmii_tx_er_int : std_logic;
signal gmii_rxd_int : std_logic_vector(7 downto 0);
signal gmii_rx_dv_int : std_logic;
signal gmii_rx_er_int : std_logic;
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
signal status_vector_apb : std_logic_vector(15 downto 0);
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE";
-- Configuration register
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal configuration_vector : std_logic_vector(4 downto 0);
signal an_interrupt : std_logic;
signal an_adv_config_vector : std_logic_vector(15 downto 0);
signal an_restart_config : std_logic;
signal link_timer_value : std_logic_vector(8 downto 0);
signal status_vector : std_logic_vector(15 downto 0);
signal synchronization_done : std_logic;
signal linkup : std_logic;
signal signal_detect : std_logic;
attribute clock_signal : string;
attribute clock_signal of sgmii_clk : signal is "yes";
attribute clock_signal of sgmii_clk_int : signal is "yes";
begin
-----------------------------------------------------------------------------
-- Default for KC705
-----------------------------------------------------------------------------
-- Remove AN during simulation i.e. "00000"
configuration_vector <= "10000" when (autonegotiation = 1) else "00000";
--an_adv_config_vector <= x"4001";
an_adv_config_vector <= "0000000000100001";
an_restart_config <= '0';
link_timer_value <= "000110010";
-- Core Status vector outputs
synchronization_done <= status_vector_int(1);
linkup <= status_vector_int(0);
signal_detect <= '1';
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= status_vector_apb;
gmiii.gtx_clk <= sgmii_clk;
gmiii.tx_clk <= sgmii_clk;
gmiii.rx_clk <= sgmii_clk;
gmii_txd <= gmiio.txd;
gmii_tx_en <= gmiio.tx_en;
gmii_tx_er <= gmiio.tx_er;
gmiii.rxd <= gmii_rxd;
gmiii.rx_dv <= gmii_rx_dv;
gmiii.rx_er <= gmii_rx_er;
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
gmiii.rmii_clk <= sgmii_clk;
gmiii.rx_col <= '0';
gmiii.rx_crs <= '0';
sgmiio.mdio_o <= gmiio.mdio_o;
sgmiio.mdio_oe <= gmiio.mdio_oe;
gmiii.mdio_i <= sgmiii.mdio_i;
sgmiio.mdc <= gmiio.mdc;
gmiii.mdint <= sgmiii.mdint;
sgmiio.reset <= apb_rstn;
-----------------------------------------------------------------------------
-- Transceiver Clock Management
-----------------------------------------------------------------------------
-- Clock circuitry for the GT Transceiver uses a differential input clock.
-- gtrefclk is routed to the tranceiver.
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => sgmiii.clkp,
IB => sgmiii.clkn,
CEB => '0',
O => gtrefclk,
ODIV2 => open
);
-- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is
-- routed to an MMCM module where it is used to create phase and frequency
-- related 62.5MHz and 125MHz clock sources
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
-- STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 16,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => open,
CLKOUT0 => clkout0,
CLKOUT0B => open,
CLKOUT1 => clkout1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => txoutclk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => mmcm_reset);
mmcm_reset <= reset or (not resetdone);
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_userclk: BUFG
port map (
I => clkout1,
O => userclk
);
-- This 125MHz clock is placed onto global clock routing and is then used
-- to clock all Ethernet core logic.
bufg_userclk2: BUFG
port map (
I => clkout0,
O => userclk2
);
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
-- Create a reset pulse of a decent length
process(reset, apb_clk)
begin
if (reset = '1') then
pma_reset_pipe <= "1111";
elsif apb_clk'event and apb_clk = '1' then
pma_reset_pipe <= pma_reset_pipe(2 downto 0) & reset;
end if;
end process;
pma_reset <= pma_reset_pipe(3);
------------------------------------------------------------------------------
-- Instantiate the Core Block (core wrapper).
------------------------------------------------------------------------------
speed_is_10_100 <= not gmiio.gbit;
speed_is_100 <= gmiio.speed;
core_wrapper : sgmii_block
port map (
drpaddr_in => "000000000",
drpclk_in => '0',
drpdi_in => "0000000000000000",
drpdo_out => OPEN,
drpen_in => '0',
drprdy_out => OPEN,
drpwe_in => '0',
gtrefclk => gtrefclk,
txp => sgmiio.txp,
txn => sgmiio.txn,
rxp => sgmiii.rxp,
rxn => sgmiii.rxn,
txoutclk => txoutclk,
resetdone => resetdone,
mmcm_locked => mmcm_locked,
userclk => userclk,
userclk2 => userclk2,
independent_clock_bufg => apb_clk,
pma_reset => pma_reset,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => sgmii_clk_en,
gmii_txd => gmii_txd_int,
gmii_tx_en => gmii_tx_en_int,
gmii_tx_er => gmii_tx_er_int,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
gmii_isolate => gmii_isolate,
configuration_vector => configuration_vector,
an_interrupt => an_interrupt,
an_adv_config_vector => an_adv_config_vector,
an_restart_config => an_restart_config,
link_timer_value => link_timer_value,
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
status_vector => status_vector_int,
reset => reset,
signal_detect => signal_detect
);
-----------------------------------------------------------------------------
-- GMII transmitter data logic
-----------------------------------------------------------------------------
-- Drive input GMII signals through IOB input flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_txd_int <= gmii_txd;
gmii_tx_en_int <= gmii_tx_en;
gmii_tx_er_int <= gmii_tx_er;
end if;
end process;
-----------------------------------------------------------------------------
-- SGMII clock logic
-----------------------------------------------------------------------------
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
sgmii_clk_int <= sgmii_clk_r;
end if;
end process;
sgmii_clk <= userclk2 when (gmiio.gbit = '1') else sgmii_clk_int;
-----------------------------------------------------------------------------
-- GMII receiver data logic
-----------------------------------------------------------------------------
-- Drive input GMII signals through IOB output flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_rxd <= gmii_rxd_int;
gmii_rx_dv <= gmii_rx_dv_int;
gmii_rx_er <= gmii_rx_er_int;
end if;
end process;
-----------------------------------------------------------------------------
-- Extra registers to ease IOB placement
-----------------------------------------------------------------------------
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
status_vector <= status_vector_int;
end if;
end process;
-----------------------------------------------------------------------------
-- Extra registers to ease CDC placement
-----------------------------------------------------------------------------
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb <= status_vector_int;
end if;
end process;
end top_level;
| gpl-2.0 | 2465c15a3a900e874b5598852b8b0bd0 | 0.459746 | 4.286469 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-jopdesign-ep1c12/config.vhd | 1 | 7,707 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := inferred;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 2;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 2;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 1;
constant CFG_SRCTRL_PROMWS : integer := (3);
constant CFG_SRCTRL_RAMWS : integer := (2);
constant CFG_SRCTRL_IOWS : integer := (0);
constant CFG_SRCTRL_RMW : integer := 1;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := (19);
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 765af5decb24f14d832c467827a8fb71 | 0.648242 | 3.604771 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/keyboard/ctrl_key_decoder.vhd | 1 | 3,433 | --------------------------------------------------------------------------------
--
-- Title : ctrl_key_decoder.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Keyboard data decoder
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.ctrl_types_pkg.key_data;
entity ctrl_key_decoder is
port(
-- system signals
clk : in std_logic; --! system clock
-- keyboard in:
ps2_clk : in std_logic; --! PS/2 CLK
ps2_data : in std_logic; --! PS/2 DATA
-- keyboard out:
keys_out : out key_data; --! key data
new_key : out std_logic --! detect new key
);
end ctrl_key_decoder;
architecture ctrl_key_decoder of ctrl_key_decoder is
component ps2_keyboard is
generic(
clk_freq : integer; --! System clock frequency in Hz
db_cnt_size : integer --! Set such that (2^size)/clk_freq = 5us (size = 8 for 50MHz)
);
port(
clk : in std_logic; --! System clock
ps2_clk : in std_logic; --! Clock signal from PS/2 keyboard
ps2_data : in std_logic; --! Data signal from PS/2 keyboard
ps2_code_new : out std_logic; --! New PS/2 code is available
ps2_code : out std_logic_vector(7 downto 0) --! Code received from PS/2
);
end component;
signal new_code : std_logic;
signal key_code : std_logic_vector(7 downto 0);
signal key_codez : std_logic_vector(7 downto 0);
signal arrowU, arrowD, arrowL, arrowR : std_logic;
signal arrowEn, arrowSp, arrowY, arrowN : std_logic;
signal Esc : std_logic;
begin
key_codez <= key_code after 1 ns when rising_edge(clk);
------------------------------------------------
new_key <= new_code when rising_edge(clk);
------------------------------------------------
keys_out.wsad <= arrowU & arrowD & arrowL & arrowR when rising_edge(clk);
keys_out.enter <= arrowEn when rising_edge(clk);
keys_out.space <= arrowSp when rising_edge(clk);
keys_out.kY <= arrowY when rising_edge(clk);
keys_out.kN <= arrowN when rising_edge(clk);
keys_out.Esc <= Esc when rising_edge(clk);
------------------------------------------------
arrowU <= '1' when key_codez = x"1D" and key_code = x"F0" else '0';
arrowD <= '1' when key_codez = x"1B" and key_code = x"F0" else '0';
arrowL <= '1' when key_codez = x"1C" and key_code = x"F0" else '0';
arrowR <= '1' when key_codez = x"23" and key_code = x"F0" else '0';
arrowN <= '1' when key_codez = x"31" and key_code = x"F0" else '0';
arrowY <= '1' when key_codez = x"35" and key_code = x"F0" else '0';
arrowSp <= '1' when key_codez = x"29" and key_code = x"F0" else '0';
arrowEn <= '1' when key_codez = x"5A" and key_code = x"F0" else '0';
Esc <= '1' when key_codez = x"76" and key_code = x"F0" else '0';
------------------------------------------------
x_key: ps2_keyboard
generic map(
clk_freq => 50_000_000,
db_cnt_size => 8
)
port map(
clk => clk,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
ps2_code_new => new_code,
ps2_code => key_code
);
end ctrl_key_decoder; | mit | 10caed0f04b864c77f1ba3faf90cf058 | 0.500728 | 3.149541 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-xup/config.vhd | 1 | 5,538 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000019#;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (90);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (256);
constant CFG_DDRSP_RSKEW : integer := (0);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 0bd981b391ffd38f4b1e592021b29995 | 0.641387 | 3.650626 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/blk_mem_gen_v7_3/simulation/bmg_stim_gen.vhd | 1 | 12,594 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (11 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0):= hex_to_std_logic_vector("0",12);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (57599 downto 0) of std_logic_vector(11 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"blk_mem_gen_v7_3.mif",
DEFAULT_DATA,
12,
57600);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>57600 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(15 DOWNTO 0) <= READ_ADDR(15 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 57600 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit | 83db97636207d07a1e9fbfaa821aa5c3 | 0.547959 | 3.68138 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/openchip/charlcd/apbcharlcd.vhd | 3 | 3,431 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: charlcd
-- File: apbcharlcd.vhd
-- Author: Antti Lukats, OpenChip
-- Description: Character LCD
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library openchip;
use openchip.charlcd.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity apbcharlcd is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
lcdi : in charlcd_in_type;
lcdo : out charlcd_out_type);
end;
architecture rtl of apbcharlcd is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_OPENCHIP, OPENCHIP_APBCHARLCD, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type charlcdregs is record
outreg : std_logic_vector(31 downto 0); -- Output Latch Data/Control
inreg : std_logic_vector(7 downto 0); -- Input Latch, not used
irq : std_ulogic; -- interrupt (internal), not used
end record;
signal r, rin : charlcdregs;
begin
comb : process(rst, r, apbi, lcdi )
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable v : charlcdregs;
begin
v := r;
v.inreg := lcdi.d_in;
irq := (others => '0');
--irq(pirq) := r.irq;
v.irq := '0';
rdata := (others => '0');
-- read/write registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(31 downto 0) := r.outreg; -- read Control Reg
when "01" =>
rdata(7 downto 0) := r.inreg; -- read back if bidir?
when others =>
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
v.outreg := apbi.pwdata(31 downto 0);
when others =>
end case;
end if;
-- reset operation
if rst = '0' then
v.outreg := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
lcdo.d_out <= r.outreg(7 downto 0);
lcdo.en <= r.outreg(11 downto 8);
lcdo.rs <= r.outreg(12);
lcdo.r_wn <= r.outreg(13);
lcdo.backlight_en <= r.outreg(14);
lcdo.d_out_oe <= r.outreg(15);
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbcharlcd" & tost(pindex) &
": Character LCD rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
| gpl-2.0 | 5218e4a31d941632c70056ac92fe0c13 | 0.580589 | 3.41393 | false | false | false | false |
Luisda199824/ProcesadorMonociclo | PSR_Modifier.vhd | 1 | 2,299 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-- ADDcc : 010000
-- ADDxcc : 011000
-- SUBcc: 010100
-- SUBxcc: 011100
-- ANDcc : 010001
-- ANDNcc : 010101
-- ORcc : 010010
-- ORNcc : 010110
-- XORcc : 010011
-- XNORcc : 010111
entity PSR_Modifier is
Port ( AluOp : in STD_LOGIC_VECTOR (5 downto 0);
Crs1 : in STD_LOGIC_VECTOR (31 downto 0);
Crs2 : in STD_LOGIC_VECTOR (31 downto 0);
ALU_Result : in STD_LOGIC_VECTOR (31 downto 0);
nzvc : out STD_LOGIC_VECTOR (3 downto 0);
rst: in STD_LOGIC
);
end PSR_Modifier;
architecture Behavioral of PSR_Modifier is
begin
process(AluOp, ALU_Result, Crs1, Crs2, rst)
begin
if (rst = '1') then
nzvc <= "0000";
else
-- ANDcc o ANDNcc, ORcc, ORNcc, XORcc, XNORcc
if (AluOp="001111" OR AluOp="010001" OR AluOp="001110" OR AluOp="010010" OR AluOp="010000" OR AluOp="010011") then
nzvc(3) <= ALU_result(31);--asignacion del bit mas significativo, al bit que indica si es negativo o positivo
if (conv_integer(ALU_result)=0) then--si el resultado de la alu es igual a 0
nzvc(2) <= '1';--el bit que indica que son iguales es 1
else
nzvc(2) <= '0';
end if;
nzvc(1) <= '0';--los bits de carry y overflow siguen siendo 0
nzvc(0) <= '0';
end if;
-- ADDcc o ADDxcc
if (AluOp="001000" or AluOp="001011") then
nzvc(3) <= ALU_result(31);--lo mismo se asigna el primer bit a n
if (conv_integer(ALU_result)=0) then
nzvc(2) <= '1';
else
nzvc(2) <= '0';
end if;
nzvc(1) <= (Crs1(31) and Crs2(31) and (not ALU_result(31))) or ((not Crs1(31)) and (not Crs2(31)) and ALU_result(31));
nzvc(0) <= (Crs1(31) and Crs2(31)) or ((not ALU_result(31)) and (Crs1(31) or Crs2(31)) );
end if;
--SUBcc or SUBxcc
if (AluOp="001001" or AluOp="001101") then
nzvc(3) <= ALU_result(31);
if (conv_integer(ALU_result)=0) then
nzvc(2) <= '1';
else
nzvc(2) <= '0';
end if;
nzvc(1) <= (Crs1(31) and (not Crs2(31)) and (not ALU_result(31))) or ((not Crs1(31)) and Crs2(31) and ALU_result(31));
nzvc(0) <= ((not Crs1(31)) and Crs2(31)) or (ALU_result(31) and ((not Crs1(31)) or Crs2(31)));
end if;
end if;
end process;
end Behavioral; | mit | bee27dde077c2636f8cdf6e2b0f5e4d3 | 0.602871 | 2.793439 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/side/example_design/side_exdes.vhd | 1 | 4,312 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: side_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY side_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END side_exdes;
ARCHITECTURE xilinx OF side_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT side IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : side
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | e4218c843e2f5b69017ef6f352c6e32d | 0.573284 | 4.828667 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/i2c/i2c2ahb_gen.vhd | 1 | 4,161 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_gen
-- File: i2c2ahb_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Generic wrapper for I2C-slave, see i2c2ahb.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb_gen is
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(AHBDW-1 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(AHBDW-1 downto 0);
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2c2ahb_gen;
architecture rtl of i2c2ahb_gen is
-- AHB signals
signal ahbi : ahb_mst_in_type;
signal ahbo : ahb_mst_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
ahbi.hgrant(0) <= ahbi_hgrant;
ahbi.hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi.hready <= ahbi_hready;
ahbi.hresp <= ahbi_hresp;
ahbi.hrdata <= ahbi_hrdata;
ahbo_hbusreq <= ahbo.hbusreq;
ahbo_hlock <= ahbo.hlock;
ahbo_htrans <= ahbo.htrans;
ahbo_haddr <= ahbo.haddr;
ahbo_hwrite <= ahbo.hwrite;
ahbo_hsize <= ahbo.hsize;
ahbo_hburst <= ahbo.hburst;
ahbo_hprot <= ahbo.hprot;
ahbo_hwdata <= ahbo.hwdata;
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2c2ahb
generic map (
hindex => 0,
ahbaddrh => ahbaddrh, ahbaddrl => ahbaddrl,
ahbmaskh => ahbmaskh, ahbmaskl => ahbmaskl,
i2cslvaddr => i2cslvaddr, i2ccfgaddr => i2ccfgaddr,
oepol => oepol, filter => filter)
port map (rstn, clk, ahbi, ahbo, i2ci, i2co);
end architecture rtl;
| gpl-2.0 | a9010be0b3b98d26be5a7a5244524bd6 | 0.597212 | 3.315538 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-xup/leon3mp.vhd | 1 | 23,304 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
sysace_clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
cf_mpa : out std_logic_vector(6 downto 0);
cf_mpd : inout std_logic_vector(15 downto 0);
cf_mp_ce_z : out std_ulogic;
cf_mp_oe_z : out std_ulogic;
cf_mp_we_z : out std_ulogic;
cf_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal ldsubre, lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of ddrlock : signal is true;
attribute syn_preserve of ddrlock : signal is true;
signal stati : ahbstat_in_type;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
sysace_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_clk, clkace);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
dsui.break <= not ldsubre;
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-- gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
-- grgpio0: grgpio
-- generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
-- nbits => CFG_GRGPIO_WIDTH)
-- port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
--
-- pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
-- pio_pad : iopad generic map (tech => padtech)
-- port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
-- end generate;
-- end generate;
-- ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
-- ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
-- nftslv => CFG_AHBSTATN)
-- port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
-- end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 6,
haddr => 16#003#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo.addr <= (others => '0'); aceo.cen <= '1'; aceo.do <= (others => '0');
aceo.doen <= '1'; aceo.oen <= '1'; aceo.wen <= '0';
end generate nograce;
cf_mpa_pads : outpadv generic map
(width => 7, tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpa, aceo.addr);
cf_mp_ce_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_ce_z, aceo.cen);
cf_mpd_pads : iopadv generic map
(tech => padtech, width => 16, level => cmos, voltage => x25v)
port map (cf_mpd, aceo.do, aceo.doen, acei.di);
cf_mp_oe_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_oe_z, aceo.oen);
cf_mp_we_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_we_z, aceo.wen);
cf_mpirq_pad : inpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpirq, acei.irq);
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 1633ed0a28729faefe86eed2b082fd49 | 0.556428 | 3.576427 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de0-nano/sdctrl16.vhd | 2 | 40,194 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl16
-- File: sdctrl16.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified by: Daniel Bengtsson & Richard Fång
-- Description: 16- and 32-bit SDRAM memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl16 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 16;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl16 is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant BUS16 : boolean := (sdbits = 16);
constant BUS32 : boolean := (sdbits = 32);
constant BUS64 : boolean := (sdbits = 64);
constant REVISION : integer := 1;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, act3_16, rd1, rd2, rd3, rd4, rd4_16, rd5, rd6, rd7, rd8,
wr1, wr1_16, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
lhw : std_ulogic; --Lower halfword
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector((sdbits-1)+((16/sdbits)*16) downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 2); -- memory address
bsel : std_ulogic;
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
if BUS16 then
if (r.lhw = '1') then --muxes read data to correct part of the register.
v.hrdata(sdbits-1 downto 0) := sdi.data(sdbits-1 downto 0);
else
v.hrdata((sdbits*2)-1 downto sdbits) := sdi.data(sdbits-1 downto 0);
end if;
else
v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
v.hrdata(31 downto 0) := sdi.data(31 downto 0);
end if;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
if BUS16 then
case r.size is
when "00" => --bytesize
case r.haddr(0) is
when '0' => dqm := "11111101";
when others => dqm := "11111110";
end case;
when others => dqm := "11111100"; --halfword, word
end case;
else
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
end if;
--
-- case r.size is
-- when "00" =>
-- case r.haddr(1 downto 0) is
-- when "00" => dqm := "11111101"; lhw := '0'; --lhv := r.haddr(1)
-- when "01" => dqm := "11111110"; lhw := '0';
-- when "10" => dqm := "11111101"; lhw := '1';
-- when others => dqm := "11111110"; lhw := '1';
-- end case;
-- when "01" =>
-- dqm := "11111100";
-- if r.haddr(1) = '0' then
-- lhw := '0';
-- else
-- lhw := '1';
-- end if;
-- when others => dqm := "11111100"; --remember when word: lhw first 0 then 1
-- end case;
--
if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
if BUS16 then
case r.cfg.csize is
when "00" => raddr := haddr(21 downto 9);-- case to check for bursting over row limit, since 1 row is 512 byte.
when "01" => raddr := haddr(22 downto 10);
when "10" => raddr := haddr(23 downto 11);
when others =>
if r.cfg.bsize = "110" then raddr := haddr(25 downto 13); --tänk
else raddr := haddr(24 downto 12); end if;
end case;
else
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
end if;
-- generate bank address
-- if BUS16 then --011
-- ba := genmux(r.cfg.bsize, haddr(26 downto 19)) &
-- genmux(r.cfg.bsize, haddr(25 downto 18));
-- else
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- end if;
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
-- elsif BUS32 then
-- adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
-- else
-- adec := genmux(r.cfg.bsize, haddr(27 downto 20)); v.bsel := '0';
-- end if;
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
-- if BUS16 then
-- v.address(16 downto 2) := '0' & ba & raddr(11 downto 0); --since 1 bit lower row => tot adress field 14 bits
-- else
v.address(16 downto 2) := ba & raddr; -- ba(16-15) & raddr(14-2) (2+13= 15 bits)
-- end if;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
if not BUS16 then -- needs if, otherwise it might clock in incorrect write data to state act3_16
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
if not BUS16 then
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
if BUS16 then --HW adress needed to memory
v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
-- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
v.lhw := r.haddr(1); -- 14-2 = 12 colummn bits => 13 downto 2
else
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
end if;
v.dqm := dqm; v.burst := r.hready; -- ??
if r.hwrite = '1' then
if BUS16 then --16 bit
if r.size(1) = '1' then --word
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1); --delayed this check 1 state to keep write data correct in act3_16
v.burst := ahbsi.htrans(0) and ahbsi.htrans(1);
v.sdstate := act3_16; -- goto state for second part of word transfer
-- v.lhw := '0'; --write MSB 16 bits to AMBA adress that ends with 00
else --halfword or byte
v.sdstate := act3_16; v.hready := '1';
end if;
else --32 bit or 64
v.sdstate := wr1;
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
end if;
v.sdwen := '0'; v.bdrive := '0'; --write
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
if BUS16 then v.sdstate := act3_16; else v.sdstate := wr1; end if;
v.sdwen := '1'; v.bdrive := '1'; v.casn := '1'; --skip write, remember hready high in next state
end if;
else v.sdstate := rd1; end if;
when act3_16 => --handle 16 bit and WORD write
v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 2) & '1';
-- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 2) & '1';
v.lhw := '1';
if (r.hready and r.burst) = '1' and not (WPROTEN and (r.wprothit = '1')) then
v.hready := '0'; --kolla på transfertyp nonseq om vi vill delaya nedankoll.
if( ahbsi.htrans = "11" and
not ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) and
not ((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00") ) then
v.sdstate := wr1_16;
end if;
elsif r.burst = '1' or (r.hready and not r.burst) = '1' then --terminate burst or single write
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
else -- complete single write
v.hready := '1';
v.sdstate := act3_16; --gick till wr1 förut
end if;
when wr1_16 =>
v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1);
-- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1);
v.lhw := r.haddr(1);
v.sdstate := act3_16;
v.hready := '1';
when wr1 =>
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 => --first read applied to sdram
v.casn := '1'; v.sdstate := rd7; --nop
if not BUS16 then --starting adress cannot be XXXX...111 since we have word burst in this case. and lowest bit always 0.
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1; --adds only within 1KB limit.
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd7 =>
v.casn := '1'; --nop
if BUS16 then
if r.cfg.casdel = '1' then --casdel3
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(3 downto 1) = "110" then
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else --casdel2
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if r.haddr(3 downto 1) = "110" then
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
else -- 32 bit or larger
if r.cfg.casdel = '1' then --casdel3
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else --casdel2
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if; --precharge
elsif lineburst then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if BUS16 then
if ahbsi.htrans /= "11" then
v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
--note that DQM always has 2 cycle delay before blocking data. So NP if we fetch second HW
end if;
else
if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
elsif lineburst then
if r.haddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd3 => --first read data from sdram output v.lhw := r.haddr(1);
v.casn := '1'; --if read before cas makes nop else if pre => no difference
if BUS16 then
--note if read is for halfwor or byte we dont want to read a second time but exit.
--if the read is a word we need to change LHW to one since the next read should be muxed in next cylcle.
-- if r.size(1) = '1' then --word v.hready := not r.size(1)
-- v.sdstate := rd4_16; v.hready := '0'; --hready low since just first part of a word
-- v.lhw := '1'; -- read low 16 next state
-- else --HW or byte
-- v.sdstate := rd4_16; v.hready := '1';
-- end if;
v.sdstate := rd4_16;
v.lhw := not r.lhw; --r.lhw is 0 for word, we should invert for next half of word.For HW or Byte v.lhw does not matter.
v.hready := not r.size(1); --if word transfer the r.size(1) is 1 and hready goes low.If HW or byte r.size(1)=0 => hready=1
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
elsif lineburst and ((ahbsi.htrans = "11") and (r.cfg.casdel = '1')) then --only enter if cl3
if r.haddr(3 downto 1) = "100" then
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else --32 bit or larger
v.sdstate := rd4; v.hready := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd4_16 => --enter as word (r.hready is still 0) else 1. If hready one next transfer sampled into v.
--v.hready := '1';
v.hready := not r.hready;-- if Byte or HW exit with hready low. If word flip bit, makes correct exit with hready low.
v.lhw := not r.lhw; --r.lhw is one the first time we enter (taking care of second part of word)
v.casn := '1';
--quit on: Single transfer CL 2/3 (prcharge if CL 2 and timer was not 0)
if (ahbsi.htrans /= "11" and (r.hready = '1')) or
((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00" and r.hready = '1') or --probably dont have to check hready 1 since if 0 adresses equal.
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100") and (r.hready = '1')) then --quit on: ST W/HW/BYTE OR
--v.hready := '0'; --if Byte or HW exit with hready low, if ST word exit with high.
v.dqm := (others => '1');
if r.sdcsn /= "11" then --not prechargeing
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; --precharge
else--exit
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then --NOTE: r.casn = 1 makes sure its the first halfword of a word that is checked (hready low)
if r.cfg.casdel = '0' then
if (r.haddr(3 downto 1) = "100") and (r.casn = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
else
if (r.haddr(3 downto 1) = "010") and (r.hready = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if r.cfg.renable = '1' and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
-- if writing to IO space config regs. Just mapping write data to all config values in config reg
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
if pageburst = 2 then v.cfg.pageburst := hwdata(17); end if;
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
--reads out config registers (r/w does not matter) according to manual depending on address, notice generic determines data width.
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
if BUS64 then regsd(15) := '1'; end if;
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd;
else
if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
else dout := r.hrdata(31 downto 0); end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.bsel := '0';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
-- Quick hack to get rid of undriven signal warnings. Check this for future
-- merge with main sdctrl.
drivehack : block
begin
sdo.qdrive <= '0';
sdo.nbdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.oct <= '0';
sdo.xsdcsn <= (others => '1');
sdo.data(127 downto 16) <= (others => '0');
sdo.cb <= (others => '0');
sdo.ba <= (others => '0');
sdo.sdck <= (others => '0');
sdo.cal_en <= (others => '0');
sdo.cal_inc <= (others => '0');
sdo.cal_pll <= (others => '0');
sdo.odt <= (others => '0');
sdo.conf <= (others => '0');
sdo.vcbdrive <= (others => '0');
sdo.dqs_gate <= '0';
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
end block drivehack;
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
mux16_wrdata : if BUS16 generate --mux data depending on Low/High HW
sdo.data(15 downto 0) <= r.hwdata(15 downto 0) when r.lhw = '1' else r.hwdata(31 downto 16);
end generate;
wrdata : if not BUS16 generate
drivebus: for i in 0 to sdbits/64 generate
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end generate;
end generate;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address;
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
if BUS16 then --mux data depending on Low/High HW
if (r.lhw ='1') then
sdo.data(15 downto 0) <= r.hwdata(15 downto 0);
else
sdo.data(15 downto 0) <= r.hwdata(31 downto 16);
end if;
end if;
if not BUS16 then
for i in 0 to sdbits/64 loop
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end loop;
end if;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl16" & tost(hindex) &
": PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 | e3ce0df722669965ccdba6119d4c8b07 | 0.527843 | 3.285644 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/irqmp/irqmp.vhd | 1 | 11,203 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: irqmp
-- File: irqmp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multi-processor APB interrupt controller. Implements a
-- two-level interrupt controller for 15 interrupts.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
entity irqmp is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end;
architecture rtl of irqmp is
constant REVISION : integer := 3;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_IRQMP, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type mask_type is array (0 to ncpu-1) of std_logic_vector(15 downto 1);
type mask2_type is array (0 to ncpu-1) of std_logic_vector(15 downto 0);
type irl_type is array (0 to ncpu-1) of std_logic_vector(3 downto 0);
type irl2_type is array (0 to ncpu-1) of std_logic_vector(4 downto 0);
type reg_type is record
imask : mask_type;
ilevel : std_logic_vector(15 downto 1);
ipend : std_logic_vector(15 downto 1);
iforce : mask_type;
ibroadcast : std_logic_vector(15 downto 1);
irl : irl_type;
cpurst : std_logic_vector(ncpu-1 downto 0);
end record;
type ereg_type is record
imask : mask2_type;
ipend : std_logic_vector(15 downto 0);
irl : irl2_type;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : reg_type := (
imask => (others => (others => '0')), ilevel => (others => '0'),
ipend => (others => '0'), iforce => (others => (others => '0')),
ibroadcast => (others => '0'), irl => (others => (others => '0')),
cpurst => (others => '0'));
constant ERES : ereg_type := (
imask => (others => (others => '0')), ipend => (others => '0'),
irl => (others => (others => '0')));
function prioritize(b : std_logic_vector(15 downto 0)) return std_logic_vector is
variable a : std_logic_vector(15 downto 0);
variable irl : std_logic_vector(3 downto 0);
variable level : integer range 0 to 15;
begin
irl := "0000"; level := 0; a := b;
for i in 15 downto 0 loop
level := i;
if a(i) = '1' then exit; end if;
end loop;
irl := conv_std_logic_vector(level, 4);
return(irl);
end;
signal r, rin : reg_type;
signal r2, r2in : ereg_type;
begin
comb : process(rst, r, r2, apbi, irqi)
variable v : reg_type;
variable temp : mask_type;
variable prdata : std_logic_vector(31 downto 0);
variable tmpirq : std_logic_vector(15 downto 0);
variable tmpvar : std_logic_vector(15 downto 1);
variable cpurun : std_logic_vector(ncpu-1 downto 0);
variable v2 : ereg_type;
variable irl2 : std_logic_vector(3 downto 0);
variable ipend2 : std_logic_vector(ncpu-1 downto 0);
variable temp2 : mask2_type;
variable neirq : integer;
begin
v := r; v.cpurst := (others => '0');
cpurun := (others => '0'); cpurun(0) := '1';
tmpvar := (others => '0'); ipend2 := (others => '0');
v2 := r2;
-- prioritize interrupts
if eirq /= 0 then
for i in 0 to ncpu-1 loop
temp2(i) := r2.ipend and r2.imask(i);
ipend2(i) := orv(temp2(i));
end loop;
end if;
for i in 0 to ncpu-1 loop
temp(i) := ((r.iforce(i) or r.ipend) and r.imask(i));
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and r.ilevel) & '0');
if v.irl(i) = "0000" then
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and not r.ilevel) & '0');
end if;
end loop;
-- register read
prdata := (others => '0');
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => prdata(15 downto 1) := r.ilevel;
when "001" =>
prdata(15 downto 1) := r.ipend;
if eirq /= 0 then prdata(31 downto 16) := r2.ipend; end if;
when "010" => prdata(15 downto 1) := r.iforce(0);
when "011" =>
when "100" | "101" =>
prdata(31 downto 28) := conv_std_logic_vector(ncpu-1, 4);
prdata(19 downto 16) := conv_std_logic_vector(eirq, 4);
for i in 0 to ncpu -1 loop prdata(i) := irqi(i).pwd; end loop;
if ncpu > 1 then
prdata(27) := '1';
case apbi.paddr(4 downto 2) is
when "101" =>
prdata := (others => '0');
prdata(15 downto 1) := r.ibroadcast;
when others =>
end case;
end if;
when others =>
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.imask(i);
if eirq /= 0 then prdata(31 downto 16) := r2.imask(i); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.iforce(i);
end if;
end loop;
when "11" =>
if eirq /= 0 then
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(4 downto 0) := r2.irl(i);
end if;
end loop;
end if;
when others =>
end case;
-- register write
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => v.ilevel := apbi.pwdata(15 downto 1);
when "001" => v.ipend := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := apbi.pwdata(31 downto 16); end if;
when "010" => v.iforce(0) := apbi.pwdata(15 downto 1);
when "011" => v.ipend := r.ipend and not apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := r2.ipend and not apbi.pwdata(31 downto 16); end if;
when "100" =>
for i in 0 to ncpu -1 loop v.cpurst(i) := apbi.pwdata(i); end loop;
when others =>
if ncpu > 1 then
case apbi.paddr(4 downto 2) is
when "101" =>
v.ibroadcast := apbi.pwdata(15 downto 1);
when others =>
end case;
end if;
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.imask(i) := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.imask(i) := apbi.pwdata(31 downto 16); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.iforce(i) := (r.iforce(i) or apbi.pwdata(15 downto 1)) and
not apbi.pwdata(31 downto 17);
end if;
end loop;
when others =>
end case;
end if;
-- register new interrupts
for i in 1 to 15 loop
if i > NAHBIRQ-1 then
exit;
end if;
if ncpu = 1 then
v.ipend(i) := v.ipend(i) or apbi.pirq(i);
else
v.ipend(i) := v.ipend(i) or (apbi.pirq(i) and not r.ibroadcast(i));
for j in 0 to ncpu-1 loop
tmpvar := v.iforce(j);
tmpvar(i) := tmpvar(i) or (apbi.pirq(i) and r.ibroadcast(i));
v.iforce(j) := tmpvar;
end loop;
end if;
end loop;
if eirq /= 0 then
for i in 16 to 31 loop
if i > NAHBIRQ-1 then exit; end if;
v2.ipend(i-16) := v2.ipend(i-16) or apbi.pirq(i);
end loop;
end if;
-- interrupt acknowledge
for i in 0 to ncpu-1 loop
if irqi(i).intack = '1' then
tmpirq := decode(irqi(i).irl);
temp(i) := tmpirq(15 downto 1);
v.iforce(i) := v.iforce(i) and not temp(i);
v.ipend := v.ipend and not ((not r.iforce(i)) and temp(i));
if eirq /= 0 then
if eirq = conv_integer(irqi(i).irl) then
v2.irl(i) := orv(temp2(i)) & prioritize(temp2(i));
if v2.irl(i)(4) = '1' then
v2.ipend(conv_integer(v2.irl(i)(3 downto 0))) := '0';
end if;
end if;
end if;
end if;
end loop;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.imask := RRES.imask; v.iforce := RRES.iforce; v.ipend := RRES.ipend;
if ncpu > 1 then
v.ibroadcast := RRES.ibroadcast;
end if;
v2.ipend := ERES.ipend; v2.imask := ERES.imask; v2.irl := ERES.irl;
end if;
apbo.prdata <= prdata;
for i in 0 to ncpu-1 loop
irqo(i).irl <= r.irl(i); irqo(i).rst <= r.cpurst(i);
irqo(i).run <= cpurun(i);
irqo(i).rstvec <= (others => '0'); -- Alternate reset vector
irqo(i).iact <= '0';
irqo(i).index <= conv_std_logic_vector(i, 4);
irqo(i).hrdrst <= '0';
end loop;
rin <= v; r2in <= v2;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
dor2regs : if eirq /= 0 generate
regs : process(clk)
begin
if rising_edge(clk) then
r2 <= r2in;
if RESET_ALL and (rst = '0') then r2 <= ERES; end if;
end if;
end process;
end generate;
nor2regs : if eirq = 0 generate
-- r2 <= ((others => "0000000000000000"), "0000000000000000", (others => "00000"));
r2.ipend <= (others => '0');
driveregs: for i in 0 to (ncpu-1) generate
r2.imask(i) <= (others => '0');
r2.irl(i) <= (others => '0');
end generate driveregs;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("irqmp" &
": Multi-processor Interrupt Controller rev " & tost(REVISION) &
", #cpu " & tost(NCPU) & ", eirq " & tost(eirq));
-- pragma translate_on
end;
| gpl-2.0 | 94e45cdad9b965cabef02a02606d72d9 | 0.564938 | 3.231324 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys3/testbench.vhd | 1 | 8,247 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library hynix;
use hynix.components.all;
use work.debug.all;
use work.config.all;
library hynix;
use hynix.components.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(26 downto 0):=(others =>'0');
signal data : std_logic_vector(31 downto 0);
signal RamCS : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
signal FlashCS : std_ulogic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(7 downto 0);
signal brdyn : std_ulogic;
signal sw : std_logic_vector(7 downto 0):= (others =>'0');
signal btn : std_logic_vector(4 downto 0):= (others =>'0');
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
clk => clk,
-- PROM
address => address(25 downto 0),
data => data(31 downto 16),
MemOE => oen,
MemWR => writen,
RamCS => RamCS,
--FlashRp => FlashRP
FlashCS => FlashCS,
-- AHB Uart
RsRx => dsurx,
RsTx => dsutx,
-- PHY
PhyTxClk => etx_clk,
PhyRxClk => erx_clk,
PhyRxd => erxdt(3 downto 0),
PhyRxDv => erx_dv,
PhyRxEr => erx_er,
PhyCol => erx_col,
PhyCrs => erx_crs,
PhyTxd => etxdt(3 downto 0),
PhyTxEn => etx_en,
PhyTxEr => etx_er,
PhyMdc => emdc,
PhyMdio => emdio,
-- Output signals for LEDs
led => led,
sw => sw,
btn => btn
);
btn(0) <= rst;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => 4+i, abits => romdepth, fname => promfile)--index => i
port map (address(romdepth-1 downto 0), data(31-i*8 downto 24-i*8), FlashCS,
writen, oen);
end generate;
sram0 : sram
generic map (index => 4, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(31 downto 24), RamCS, writen, oen);
sram1 : sram
generic map (index => 5, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(23 downto 16), RamCS, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
led(3) <= 'L'; -- ERROR pull-down
error <= not led(3);
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 | 4333e24693e77748f903003c21312e12 | 0.566873 | 3.512351 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0/sim/design_1_axi_uartlite_0_0.vhd | 1 | 8,182 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0;
USE axi_uartlite_v2_0.axi_uartlite;
ENTITY design_1_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END design_1_axi_uartlite_0_0;
ARCHITECTURE design_1_axi_uartlite_0_0_arch OF design_1_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT interrupt";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END design_1_axi_uartlite_0_0_arch;
| gpl-3.0 | d83f640a450778c3c80f4a004f13f727 | 0.690174 | 3.343686 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/spi/spi2ahb_apb.vhd | 1 | 6,817 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb_apb
-- File: spi2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from SPI.
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity spi2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb_apb;
architecture rtl of spi2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPI2AHB, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
spi2ahbi : spi2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal spi2ahbo : spi2ahb_out_type;
begin
bridge : spi2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter,
cpol => cpol, cpha => cpha)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
spii => spii, spio => spio, spi2ahbi => r.spi2ahbi,
spi2ahbo => spi2ahbo);
comb: process (r, rstn, apbi, spi2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := spi2ahbo.prot; v.dmax := spi2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.spi2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.spi2ahbi.haddr;
when MASK_OFF => apbout := r.spi2ahbi.hmask;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.spi2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.spi2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.spi2ahbi.hmask := apbi.pwdata;
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((spi2ahbo.dma and not r.dmax) or
(spi2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or spi2ahbo.prot; v.wr := spi2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.spi2ahbi.en := conv_std_logic(resen = 1);
v.spi2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.spi2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in spi2ahbx...
end architecture rtl;
| gpl-2.0 | b77e39af38aee91ea983fc6ec99b1643 | 0.535426 | 3.797772 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/greth/ethernet_mac.vhd | 1 | 5,107 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.net.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package ethernet_mac is
type eth_tx_in_type is record
start : std_ulogic;
valid : std_ulogic;
data : std_logic_vector(31 downto 0);
full_duplex : std_ulogic;
length : std_logic_vector(10 downto 0);
col : std_ulogic;
crs : std_ulogic;
read_ack : std_ulogic;
end record;
type eth_tx_out_type is record
status : std_logic_vector(1 downto 0);
done : std_ulogic;
restart : std_ulogic;
read : std_ulogic;
tx_er : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
end record;
type eth_rx_in_type is record
writeok : std_ulogic;
rxen : std_ulogic;
rx_dv : std_ulogic;
rx_er : std_ulogic;
rxd : std_logic_vector(3 downto 0);
done_ack : std_ulogic;
write_ack : std_ulogic;
end record;
type eth_rx_out_type is record
write : std_ulogic;
data : std_logic_vector(31 downto 0);
done : std_ulogic;
length : std_logic_vector(10 downto 0);
status : std_logic_vector(2 downto 0);
start : std_ulogic;
end record;
type eth_mdio_in_type is record
mdioi : std_ulogic;
write : std_ulogic;
read : std_ulogic;
mdiostart : std_ulogic;
regadr : std_logic_vector(4 downto 0);
phyadr : std_logic_vector(4 downto 0);
data : std_logic_vector(15 downto 0);
end record;
type eth_mdio_out_type is record
mdc : std_ulogic;
mdioo : std_ulogic;
mdioen : std_ulogic;
data : std_logic_vector(15 downto 0);
done : std_ulogic;
error : std_ulogic;
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
component eth_ahb_mst is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
end package;
| gpl-2.0 | dcd55a464445805fcb7059080f23858e | 0.55512 | 3.571329 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s06/AXI_STREAM_HLS_S06/HLS/simple_axi_stream_counter/solution1/syn/vhdl/axi_stream_counter.vhd | 3 | 7,508 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity axi_stream_counter is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
counter_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
counter_TVALID : OUT STD_LOGIC;
counter_TREADY : IN STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of axi_stream_counter is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"axi_stream_counter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.440000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=34,HLS_SYN_LUT=34}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_19 : BOOLEAN;
signal counterValue : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal counterValue_assign_fu_34_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_ioackin_counter_TREADY : STD_LOGIC;
signal ap_reg_ioackin_counter_TREADY : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_60 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_counter_TREADY assign process. --
ap_reg_ioackin_counter_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_counter_TREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
if (not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY)))) then
ap_reg_ioackin_counter_TREADY <= ap_const_logic_0;
elsif (ap_sig_bdd_60) then
ap_reg_ioackin_counter_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY))))) then
counterValue <= counterValue_assign_fu_34_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_sig_ioackin_counter_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_ioackin_counter_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_ioackin_counter_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= ap_const_lv32_0;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_19 assign process. --
ap_sig_bdd_19_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_19 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_60 assign process. --
ap_sig_bdd_60_assign_proc : process(ap_start, counter_TREADY)
begin
ap_sig_bdd_60 <= (not((ap_start = ap_const_logic_0)) and (ap_const_logic_1 = counter_TREADY));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_19)
begin
if (ap_sig_bdd_19) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_counter_TREADY assign process. --
ap_sig_ioackin_counter_TREADY_assign_proc : process(counter_TREADY, ap_reg_ioackin_counter_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_counter_TREADY)) then
ap_sig_ioackin_counter_TREADY <= counter_TREADY;
else
ap_sig_ioackin_counter_TREADY <= ap_const_logic_1;
end if;
end process;
counterValue_assign_fu_34_p2 <= std_logic_vector(unsigned(counterValue) + unsigned(ap_const_lv32_1));
counter_TDATA <= std_logic_vector(unsigned(counterValue) + unsigned(ap_const_lv32_1));
-- counter_TVALID assign process. --
counter_TVALID_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_reg_ioackin_counter_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (ap_const_logic_0 = ap_reg_ioackin_counter_TREADY))) then
counter_TVALID <= ap_const_logic_1;
else
counter_TVALID <= ap_const_logic_0;
end if;
end process;
end behav;
| gpl-3.0 | ac7b8e790d2efa30b07af523f8c23f0c | 0.587906 | 3.148008 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/car/simulation/car_tb.vhd | 1 | 4,325 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: car_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY car_tb IS
END ENTITY;
ARCHITECTURE car_tb_ARCH OF car_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
car_synth_inst:ENTITY work.car_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | 5499d2196e7c6dcf7705eedfbf1e8589 | 0.617803 | 4.650538 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/cachemem.vhd | 1 | 21,810 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity cachemem is
generic (
tech : integer range 0 to NTECH := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
mmuen : integer range 0 to 1 := 0;
testen : integer range 0 to 3 := 0
);
port (
clk : in std_ulogic;
crami : in cram_in_type;
cramo : out cram_out_type;
sclk : in std_ulogic
);
end;
architecture rtl of cachemem is
constant DSNOOPSEP : boolean := (dsnoop > 3);
constant DSNOOPFAST : boolean := (dsnoop = 2) or (dsnoop = 6);
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant ITAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + ilinesize + 1;
constant DTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + dlinesize + 1;
constant IPTAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + 1;
constant ILRR_BIT : integer := creplalg_tbl(irepl);
constant DLRR_BIT : integer := creplalg_tbl(drepl);
constant ITAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant DTAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant ICLOCK_BIT : integer := isetlock;
constant DCLOCK_BIT : integer := dsetlock;
constant ILRAM_BITS : integer := log2(ilramsize) + 10;
constant DLRAM_BITS : integer := log2(dlramsize) + 10;
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant MMUCTX_BITS : natural := 8*mmuen;
-- i/d tag layout
-- +-----+----------+---+--------+-----+-------+
-- | LRR | LOCK_BIT |PAR| MMUCTX | TAG | VALID |
-- +-----+----------+---+--------+-----+-------+
-- [opt] [ opt ] [ ] [ opt ] [ ]
constant ITWIDTH : natural := ITAG_BITS + ILRR_BIT + ICLOCK_BIT + MMUCTX_BITS
;
constant DTWIDTH : natural := DTAG_BITS + DLRR_BIT + DCLOCK_BIT + MMUCTX_BITS
;
constant IDWIDTH : natural := 32
;
constant DDWIDTH : natural := 32
;
constant DPTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + 1;
constant DTLRR_BIT_POS : natural := DTWIDTH-DLRR_BIT; -- if DTLRR_BIT=0 discard (pos DTWIDTH)
constant DTLOCK_BIT_POS : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT); -- if DTCLOCK_BIT=0 but DTLRR_BIT=1 lrr will overwrite
constant DTMMU_VEC_U : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT
)-1;
constant DTMMU_VEC_D : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT+
MMUCTX_BITS);
constant ITLRR_BIT_POS : natural := ITWIDTH-ILRR_BIT; -- if DLRR_BIT=0 discard (pos DTWIDTH)
constant ITLOCK_BIT_POS : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT); -- if DCLOCK_BIT=0 but DLRR_BIT=1 lrr will overwrite
constant ITMMU_VEC_U : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT
)-1;
constant ITMMU_VEC_D : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT+
MMUCTX_BITS);
constant DPTAG_RAM_BITS : integer := DPTAG_BITS
;
constant DTAG_RAM_BITS : integer := DTAG_BITS
;
subtype dtdatain_vector is std_logic_vector(DTWIDTH downto 0);
type dtdatain_type is array (0 to MAXSETS-1) of dtdatain_vector;
subtype itdatain_vector is std_logic_vector(ITWIDTH downto 0);
type itdatain_type is array (0 to MAXSETS-1) of itdatain_vector;
subtype dddatain_vector is std_logic_vector(DDWIDTH-1 downto 0);
type dddatain_type is array (0 to MAXSETS-1) of dddatain_vector;
subtype itdataout_vector is std_logic_vector(ITWIDTH downto 0);
type itdataout_type is array (0 to MAXSETS-1) of itdataout_vector;
subtype iddataout_vector is std_logic_vector(IDWIDTH -1 downto 0);
type iddataout_type is array (0 to MAXSETS-1) of iddataout_vector;
subtype dtdataout_vector is std_logic_vector(DTWIDTH downto 0);
type dtdataout_type is array (0 to MAXSETS-1) of dtdataout_vector;
subtype dddataout_vector is std_logic_vector(DDWIDTH -1 downto 0);
type dddataout_type is array (0 to MAXSETS-1) of dddataout_vector;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal ildaddr : std_logic_vector(ILRAM_BITS-3 downto 0);
signal itdatain : itdatain_type;
signal itdatainx : itdatain_type;
signal itdatain_cmp : itdatain_type;
signal itdataout : itdataout_type;
signal iddatain : std_logic_vector(IDWIDTH -1 downto 0);
signal iddatainx : std_logic_vector(IDWIDTH -1 downto 0);
signal iddatain_cmp : std_logic_vector(IDWIDTH -1 downto 0);
signal iddataout : iddataout_type;
signal ildataout : std_logic_vector(31 downto 0);
signal itenable : std_ulogic;
signal idenable : std_ulogic;
signal itwrite : std_logic_vector(0 to MAXSETS-1);
signal idwrite : std_logic_vector(0 to MAXSETS-1);
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr2 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr3 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal ldaddr : std_logic_vector(DLRAM_BITS-1 downto 2);
signal dtdatain : dtdatain_type;
signal dtdatainx : dtdatain_type;
signal dtdatain_cmp : dtdatain_type;
signal dtdatain2 : dtdatain_type;
signal dtdatain3 : dtdatain_type;
signal dtdatainu : dtdatain_type;
signal dtdataout : dtdataout_type;
signal dtdataout2: dtdataout_type;
signal dtdataout3: dtdataout_type;
signal dddatain : dddatain_type;
signal dddatainx : dddatain_type;
signal dddatain_cmp : dddatain_type;
signal dddataout : dddataout_type;
signal lddatain, ldataout : std_logic_vector(31 downto 0);
signal dtenable : std_logic_vector(0 to MAXSETS-1);
signal dtenable2 : std_logic_vector(0 to MAXSETS-1);
signal ddenable : std_logic_vector(0 to MAXSETS-1);
signal dtwrite : std_logic_vector(0 to MAXSETS-1);
signal dtwrite2 : std_logic_vector(0 to MAXSETS-1);
signal dtwrite3 : std_logic_vector(0 to MAXSETS-1);
signal ddwrite : std_logic_vector(0 to MAXSETS-1);
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
itaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto 0);
ildaddr <= crami.icramin.address(ILRAM_BITS-3 downto 0);
itinsel : process(clk, crami, dtdataout2, dtdataout3
)
variable viddatain : std_logic_vector(IDWIDTH -1 downto 0);
variable vdddatain : dddatain_type;
variable vitdatain : itdatain_type;
variable vdtdatain : dtdatain_type;
variable vdtdatain2 : dtdatain_type;
variable vdtdatain3 : dtdatain_type;
variable vdtdatainu : dtdatain_type;
begin
viddatain := (others => '0');
vdddatain := (others => (others => '0'));
viddatain(31 downto 0) := crami.icramin.data;
for i in 0 to DSETS-1 loop
vdtdatain(i) := (others => '0');
if mmuen = 1 then
vdtdatain(i)(DTMMU_VEC_U downto DTMMU_VEC_D) := crami.dcramin.ctx(i);
end if;
vdtdatain(i)(DTLOCK_BIT_POS) := crami.dcramin.tag(i)(CTAG_LOCKPOS);
if drepl = lrr then
vdtdatain(i)(DTLRR_BIT_POS) := crami.dcramin.tag(i)(CTAG_LRRPOS);
end if;
vdtdatain(i)(DTAG_BITS-1 downto 0) := crami.dcramin.tag(i)(TAG_HIGH downto DTAG_LOW) & crami.dcramin.tag(i)(dlinesize-1 downto 0);
if (crami.dcramin.flush = '1') then
vdtdatain(i) := (others => '0');
vdtdatain(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"FF";
vdtdatain(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
for i in 0 to DSETS-1 loop
vdtdatain2(i) := (others => '0');
vdddatain(i)(31 downto 0) := crami.dcramin.data(i);
vdtdatain2(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"FF";
vdtdatain2(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain2(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end loop;
vdtdatainu := (others => (others => '0'));
vdtdatain3 := (others => (others => '0'));
for i in 0 to DSETS-1 loop
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS) := crami.dcramin.ptag(i)(TAG_HIGH downto DTAG_LOW);
if DSNOOPSEP and (crami.dcramin.flush = '1') then
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"F3";
vdtdatain3(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain3(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
for i in 0 to ISETS-1 loop
vitdatain(i) := (others => '0');
if mmuen = 1 then
vitdatain(i)(ITMMU_VEC_U downto ITMMU_VEC_D) := crami.icramin.ctx;
end if;
vitdatain(i)(ITLOCK_BIT_POS) := crami.icramin.tag(i)(CTAG_LOCKPOS);
if irepl = lrr then
vitdatain(i)(ITLRR_BIT_POS) := crami.icramin.tag(i)(CTAG_LRRPOS);
end if;
vitdatain(i)(ITAG_BITS-1 downto 0) := crami.icramin.tag(i)(TAG_HIGH downto ITAG_LOW)
& crami.icramin.tag(i)(ilinesize-1 downto 0);
if (crami.icramin.flush = '1') then
vitdatain(i) := (others => '0');
vitdatain(i)(ITAG_BITS-1 downto ITAG_BITS-8) := X"FF";
vitdatain(i)(ITAG_BITS-9 downto ITAG_BITS-10) := conv_std_logic_vector(i,2);
vitdatain(i)(ITAG_BITS-11 downto ITAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
-- pragma translate_off
itdatainx <= vitdatain; iddatainx <= viddatain;
dtdatainx <= vdtdatain; dddatainx <= vdddatain;
-- pragma translate_on
itdatain <= vitdatain; iddatain <= viddatain;
dtdatain <= vdtdatain; dtdatain2 <= vdtdatain2; dddatain <= vdddatain;
dtdatain3 <= vdtdatain3;
end process;
itwrite <= crami.icramin.twrite;
idwrite <= crami.icramin.dwrite;
itenable <= crami.icramin.tenable;
idenable <= crami.icramin.denable;
dtaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
dtaddr2 <= crami.dcramin.saddress(DOFFSET_BITS-1 downto 0);
dtaddr3 <= crami.dcramin.faddress(DOFFSET_BITS-1 downto 0);
ddaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto 0);
ldaddr <= crami.dcramin.ldramin.address(DLRAM_BITS-1 downto 2);
dtwrite <= crami.dcramin.twrite;
dtwrite2 <= crami.dcramin.swrite;
dtwrite3 <= crami.dcramin.tpwrite;
ddwrite <= crami.dcramin.dwrite;
dtenable <= crami.dcramin.tenable;
dtenable2 <= crami.dcramin.senable;
ddenable <= crami.dcramin.denable;
ime : if icen = 1 generate
im0 : for i in 0 to ISETS-1 generate
itags0 : syncram generic map (tech, IOFFSET_BITS, ITWIDTH, testen)
port map ( clk, itaddr, itdatain(i)(ITWIDTH-1 downto 0), itdataout(i)(ITWIDTH-1 downto 0), itenable, itwrite(i), crami.dcramin.tdiag);
idata0 : syncram generic map (tech, IOFFSET_BITS+ILINE_BITS, IDWIDTH, testen)
port map (clk, idaddr, iddatain, iddataout(i), idenable, idwrite(i), crami.dcramin.ddiag);
itdataout(i)(ITWIDTH) <= '0';
end generate;
end generate;
imd : if icen = 0 generate
ind0 : for i in 0 to ISETS-1 generate
itdataout(i) <= (others => '0');
iddataout(i) <= (others => '0');
end generate;
end generate;
ild0 : if ilram = 1 generate
ildata0 : syncram
generic map (tech, ILRAM_BITS-2, 32, testen)
port map (clk, ildaddr, iddatain, ildataout,
crami.icramin.ldramin.enable, crami.icramin.ldramin.write, crami.dcramin.ddiag);
end generate;
dme : if dcen = 1 generate
dtags0 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram
generic map (tech, DOFFSET_BITS, DTWIDTH, testen)
port map (clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i), crami.dcramin.tdiag);
end generate;
end generate;
dtags1 : if DSNOOP /= 0 generate
dt1 : if not DSNOOPSEP generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto 0),
dtdataout2(i)(DTWIDTH-1 downto 0), dtenable2(i), dtwrite2(i), crami.dcramin.tdiag);
end generate;
end generate;
-- virtual address snoop case
mdt1 : if DSNOOPSEP generate
slow : if not DSNOOPFAST generate
mdt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH-dlinesize+1) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto dlinesize-1),
dtdataout(i)(DTWIDTH-1 downto dlinesize-1), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto dlinesize-1),
dtdataout2(i)(DTWIDTH-1 downto dlinesize-1), dtenable2(i), dtwrite2(i), crami.dcramin.tdiag);
dtags1 : syncram_dp
generic map (tech, DOFFSET_BITS, DPTAG_RAM_BITS) port map (
clk, dtaddr, dtdatain3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
open, dtwrite3(i), dtwrite3(i),
sclk, dtaddr2, dtdatainu(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
dtdataout3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS), dtenable2(i), dtwrite2(i), crami.dcramin.sdiag);
end generate;
end generate;
fast : if DSNOOPFAST generate
mdt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_2p
generic map (tech, DOFFSET_BITS, DTWIDTH-dlinesize+1, 0, 1, testen) port map (
clk, dtenable(i), dtaddr, dtdataout(i)(DTWIDTH-1 downto dlinesize-1),
sclk, dtwrite2(i), dtaddr3, dtdatain(i)(DTWIDTH-1 downto dlinesize-1), crami.dcramin.tdiag);
dtags1 : syncram_2p
generic map (tech, DOFFSET_BITS, DPTAG_RAM_BITS, 0, 1, testen) port map (
sclk, dtenable2(i), dtaddr2, dtdataout3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
clk, dtwrite3(i), dtaddr, dtdatain3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS), crami.dcramin.sdiag);
end generate;
end generate;
end generate;
end generate;
nodtags1 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtdataout2(i)(DTWIDTH-1 downto 0) <= zero64(DTWIDTH-1 downto 0);
end generate;
end generate;
dd0 : for i in 0 to DSETS-1 generate
ddata0 : syncram
generic map (tech, DOFFSET_BITS+DLINE_BITS, DDWIDTH, testen)
port map (clk, ddaddr, dddatain(i), dddataout(i), ddenable(i), ddwrite(i), crami.dcramin.ddiag);
dtdataout(i)(DTWIDTH) <= '0';
end generate;
end generate;
dmd : if dcen = 0 generate
dnd0 : for i in 0 to DSETS-1 generate
dtdataout(i) <= (others => '0');
dtdataout2(i) <= (others => '0');
dddataout(i) <= (others => '0');
end generate;
end generate;
ldxs0 : if not ((dlram = 1) and (DSETS > 1)) generate
lddatain <= dddatain(0)(31 downto 0);
end generate;
ldxs1 : if (dlram = 1) and (DSETS > 1) generate
lddatain <= dddatain(1)(31 downto 0);
end generate;
ld0 : if dlram = 1 generate
ldata0 : syncram
generic map (tech, DLRAM_BITS-2, 32, testen)
port map (clk, ldaddr, lddatain, ldataout, crami.dcramin.ldramin.enable,
crami.dcramin.ldramin.write, crami.dcramin.ddiag);
end generate;
itx : for i in 0 to ISETS-1 generate
cramo.icramo.tag(i)(TAG_HIGH downto ITAG_LOW) <= itdataout(i)(ITAG_BITS-1 downto (ITAG_BITS-1) - (TAG_HIGH - ITAG_LOW));
--(ITWIDTH-1-(ILRR_BIT+ICLOCK_BIT) downto ITWIDTH-(TAG_HIGH-ITAG_LOW)-(ILRR_BIT+ICLOCK_BIT)-1);
cramo.icramo.tag(i)(ilinesize-1 downto 0) <= itdataout(i)(ilinesize-1 downto 0);
cramo.icramo.tag(i)(CTAG_LRRPOS) <= itdataout(i)(ITLRR_BIT_POS);
cramo.icramo.tag(i)(CTAG_LOCKPOS) <= itdataout(i)(ITLOCK_BIT_POS);
ictx : if mmuen = 1 generate
cramo.icramo.ctx(i) <= itdataout(i)(ITMMU_VEC_U downto ITMMU_VEC_D);
end generate;
noictx : if mmuen = 0 generate
cramo.icramo.ctx(i) <= (others => '0');
end generate;
cramo.icramo.data(i) <= ildataout when (ilram = 1) and ((ISETS = 1) or (i = 1)) and (crami.icramin.ldramin.read = '1') else iddataout(i)(31 downto 0);
itv : if ilinesize = 4 generate
cramo.icramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
ite : for j in 10 to ITAG_LOW-1 generate
cramo.icramo.tag(i)(j) <= '0';
end generate;
end generate;
itx2 : for i in ISETS to MAXSETS-1 generate
cramo.icramo.tag(i) <= (others => '0');
cramo.icramo.data(i) <= (others => '0');
cramo.icramo.ctx(i) <= (others => '0');
end generate;
itd : for i in 0 to DSETS-1 generate
cramo.dcramo.tag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
-- cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= dtdataout(i)(dlinesize-1 downto 0);
cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= (others => dtdataout(i)(dlinesize-1));
cramo.dcramo.tag(i)(CTAG_LRRPOS) <= dtdataout(i)(DTLRR_BIT_POS);
cramo.dcramo.tag(i)(CTAG_LOCKPOS) <= dtdataout(i)(DTLOCK_BIT_POS);
dctx : if mmuen /= 0 generate
cramo.dcramo.ctx(i) <= dtdataout(i)(DTMMU_VEC_U downto DTMMU_VEC_D);
end generate;
nodctx : if mmuen = 0 generate
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
stagv : if DSNOOPSEP generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout3(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
cramo.dcramo.stag(i)(DTAG_LOW-1 downto 0) <= (others =>'0');
end generate;
stagp : if not DSNOOPSEP generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout2(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
cramo.dcramo.stag(i)(DTAG_LOW-1 downto 0) <= (others =>'0');
end generate;
cramo.dcramo.data(i) <= ldataout when (dlram = 1) and ((DSETS = 1) or (i = 1)) and (crami.dcramin.ldramin.read = '1')
else dddataout(i)(31 downto 0);
dtv : if dlinesize = 4 generate
cramo.dcramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
dte : for j in 10 to DTAG_LOW-1 generate
cramo.dcramo.tag(i)(j) <= '0';
end generate;
end generate;
itd2 : for i in DSETS to MAXSETS-1 generate
cramo.dcramo.tag(i) <= (others => '0');
cramo.dcramo.stag(i) <= (others => '0');
cramo.dcramo.data(i) <= (others => '0');
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
end ;
| gpl-2.0 | 03cbfd28c0b6a460a7a322a2b49bfea8 | 0.618111 | 3.526273 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/FIFO_image_filter_img_0_rows_V_channel.vhd | 4 | 4,628 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_rows_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_0_rows_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_img_0_rows_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_rows_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_0_rows_V_channel is
component FIFO_image_filter_img_0_rows_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_0_rows_V_channel_shiftReg : FIFO_image_filter_img_0_rows_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | c0104d5c7f9064ceb5a43e9f598b3234 | 0.539326 | 3.490196 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd | 1 | 9,109 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY design_1_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END design_1_axi_gpio_0_0;
ARCHITECTURE design_1_axi_gpio_0_0_arch OF design_1_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_gpio_0_0_arch;
| gpl-3.0 | 75c8f1991ab72daabdd12616746f3c1b | 0.678999 | 3.219866 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/gencomp/netcomp.vhd | 1 | 70,046 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: netcomp
-- File: netcomp.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler
-- Description: Declaration of netlists components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use work.gencomp.all;
package netcomp is
---------------------------------------------------------------------------
-- netlists ---------------------------------------------------------------
---------------------------------------------------------------------------
component grusbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debug_abits : integer := 12);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- grusb_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
suspendm : out std_ulogic;
dbus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
txenablen : out std_ulogic;
txdat : out std_ulogic;
txse0 : out std_ulogic;
-- grusb_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
urstdrive : in std_logic_vector((nports-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic;
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
-- debug signals
debug_raddr : out std_logic_vector(15 downto 0);
debug_waddr : out std_logic_vector(15 downto 0);
debug_wdata : out std_logic_vector(31 downto 0);
debug_we : out std_ulogic;
debug_rdata : in std_logic_vector(31 downto 0));
end component;
component grspwc_net
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc2_net is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_logic;
tickinraw : in std_logic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_logic;
tickout : out std_logic;
tickoutraw : out std_logic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic;
testrst : in std_logic;
testen : in std_logic;
rxdav : out std_logic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_logic
);
end component;
component grlfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component leon3ft_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic
);
end component;
component ftmctrl_net
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
wsshift : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
memi_data: in Std_Logic_Vector(31 downto 0);
memi_brdyn: in Std_Logic;
memi_bexcn: in Std_Logic;
memi_writen: in Std_Logic;
memi_wrn: in Std_Logic_Vector(3 downto 0);
memi_bwidth: in Std_Logic_Vector(1 downto 0);
memi_sd: in Std_Logic_Vector(63 downto 0);
memi_cb: in Std_Logic_Vector(15 downto 0);
memi_scb: in Std_Logic_Vector(15 downto 0);
memi_edac: in Std_Logic;
memo_address: out Std_Logic_Vector(31 downto 0);
memo_data: out Std_Logic_Vector(31 downto 0);
memo_sddata: out Std_Logic_Vector(63 downto 0);
memo_ramsn: out Std_Logic_Vector(7 downto 0);
memo_ramoen: out Std_Logic_Vector(7 downto 0);
memo_ramn: out Std_ULogic;
memo_romn: out Std_ULogic;
memo_mben: out Std_Logic_Vector(3 downto 0);
memo_iosn: out Std_Logic;
memo_romsn: out Std_Logic_Vector(7 downto 0);
memo_oen: out Std_Logic;
memo_writen: out Std_Logic;
memo_wrn: out Std_Logic_Vector(3 downto 0);
memo_bdrive: out Std_Logic_Vector(3 downto 0);
memo_vbdrive: out Std_Logic_Vector(31 downto 0);
memo_svbdrive: out Std_Logic_Vector(63 downto 0);
memo_read: out Std_Logic;
memo_sa: out Std_Logic_Vector(14 downto 0);
memo_cb: out Std_Logic_Vector(15 downto 0);
memo_scb: out Std_Logic_Vector(15 downto 0);
memo_vcdrive: out Std_Logic_Vector(15 downto 0);
memo_svcdrive: out Std_Logic_Vector(15 downto 0);
memo_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0);
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0);
sdo_sdwen: out Std_ULogic;
sdo_rasn: out Std_ULogic;
sdo_casn: out Std_ULogic;
sdo_dqm: out Std_Logic_Vector( 7 downto 0);
wpo_wprothit: in Std_ULogic);
end component;
component ssrctrl_net
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
component ftsrctrl_net
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri_data: in Std_Logic_Vector(31 downto 0); -- Data bus address
sri_brdyn: in Std_Logic;
sri_bexcn: in Std_Logic;
sri_writen: in Std_Logic;
sri_wrn: in Std_Logic_Vector(3 downto 0);
sri_bwidth: in Std_Logic_Vector(1 downto 0);
sri_sd: in Std_Logic_Vector(63 downto 0);
sri_cb: in Std_Logic_Vector(15 downto 0);
sri_scb: in Std_Logic_Vector(15 downto 0);
sri_edac: in Std_Logic;
sro_address: out Std_Logic_Vector(31 downto 0);
sro_data: out Std_Logic_Vector(31 downto 0);
sro_sddata: out Std_Logic_Vector(63 downto 0);
sro_ramsn: out Std_Logic_Vector(7 downto 0);
sro_ramoen: out Std_Logic_Vector(7 downto 0);
sro_ramn: out Std_ULogic;
sro_romn: out Std_ULogic;
sro_mben: out Std_Logic_Vector(3 downto 0);
sro_iosn: out Std_Logic;
sro_romsn: out Std_Logic_Vector(7 downto 0);
sro_oen: out Std_Logic;
sro_writen: out Std_Logic;
sro_wrn: out Std_Logic_Vector(3 downto 0);
sro_bdrive: out Std_Logic_Vector(3 downto 0);
sro_vbdrive: out Std_Logic_Vector(31 downto 0); --vector bus drive
sro_svbdrive: out Std_Logic_Vector(63 downto 0); --vector bus drive sdram
sro_read: out Std_Logic;
sro_sa: out Std_Logic_Vector(14 downto 0);
sro_cb: out Std_Logic_Vector(15 downto 0);
sro_scb: out Std_Logic_Vector(15 downto 0);
sro_vcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb
sro_svcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb sdram
sro_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0); -- clk en
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0); -- chip sel
sdo_sdwen: out Std_ULogic; -- write en
sdo_rasn: out Std_ULogic; -- row addr stb
sdo_casn: out Std_ULogic; -- col addr stb
sdo_dqm: out Std_Logic_Vector(15 downto 0); -- data i/o mask
sdo_bdrive: out Std_ULogic; -- bus drive
sdo_qdrive: out Std_ULogic; -- bus drive
sdo_vbdrive: out Std_Logic_Vector(31 downto 0); -- vector bus drive
sdo_address: out Std_Logic_Vector(16 downto 2); -- address out
sdo_data: out Std_Logic_Vector(127 downto 0); -- data out
sdo_cb: out Std_Logic_Vector(15 downto 0);
sdo_ce: out Std_ULogic;
sdo_ba: out Std_Logic_Vector(2 downto 0)); -- bank address
end component;
component grlfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0;
wrt : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component spictrl_net
generic (
tech : integer range 0 to NTECH := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
component leon4_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
hclken : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic);
end component;
component grpci2_phy_net is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0
);
port(
pciclk : in std_logic;
pcii_rst : in std_ulogic;
pcii_gnt : in std_ulogic;
pcii_idsel : in std_ulogic;
pcii_ad : in std_logic_vector(31 downto 0);
pcii_cbe : in std_logic_vector(3 downto 0);
pcii_frame : in std_ulogic;
pcii_irdy : in std_ulogic;
pcii_trdy : in std_ulogic;
pcii_devsel : in std_ulogic;
pcii_stop : in std_ulogic;
pcii_lock : in std_ulogic;
pcii_perr : in std_ulogic;
pcii_serr : in std_ulogic;
pcii_par : in std_ulogic;
pcii_host : in std_ulogic;
pcii_pci66 : in std_ulogic;
pcii_pme_status : in std_ulogic;
pcii_int : in std_logic_vector(3 downto 0);
phyi_pcirstout : in std_logic;
phyi_pciasyncrst : in std_logic;
phyi_pcisoftrst : in std_logic_vector(2 downto 0);
phyi_pciinten : in std_logic_vector(3 downto 0);
phyi_m_request : in std_logic;
phyi_m_mabort : in std_logic;
phyi_pr_m_fstate : in std_logic_vector(1 downto 0);
phyi_pr_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_0_last : in std_logic;
phyi_pr_m_cfifo_0_stlast : in std_logic;
phyi_pr_m_cfifo_0_hold : in std_logic;
phyi_pr_m_cfifo_0_valid : in std_logic;
phyi_pr_m_cfifo_0_err : in std_logic;
phyi_pr_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_1_last : in std_logic;
phyi_pr_m_cfifo_1_stlast : in std_logic;
phyi_pr_m_cfifo_1_hold : in std_logic;
phyi_pr_m_cfifo_1_valid : in std_logic;
phyi_pr_m_cfifo_1_err : in std_logic;
phyi_pr_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_2_last : in std_logic;
phyi_pr_m_cfifo_2_stlast : in std_logic;
phyi_pr_m_cfifo_2_hold : in std_logic;
phyi_pr_m_cfifo_2_valid : in std_logic;
phyi_pr_m_cfifo_2_err : in std_logic;
phyi_pv_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_0_last : in std_logic;
phyi_pv_m_cfifo_0_stlast : in std_logic;
phyi_pv_m_cfifo_0_hold : in std_logic;
phyi_pv_m_cfifo_0_valid : in std_logic;
phyi_pv_m_cfifo_0_err : in std_logic;
phyi_pv_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_1_last : in std_logic;
phyi_pv_m_cfifo_1_stlast : in std_logic;
phyi_pv_m_cfifo_1_hold : in std_logic;
phyi_pv_m_cfifo_1_valid : in std_logic;
phyi_pv_m_cfifo_1_err : in std_logic;
phyi_pv_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_2_last : in std_logic;
phyi_pv_m_cfifo_2_stlast : in std_logic;
phyi_pv_m_cfifo_2_hold : in std_logic;
phyi_pv_m_cfifo_2_valid : in std_logic;
phyi_pv_m_cfifo_2_err : in std_logic;
phyi_pr_m_addr : in std_logic_vector(31 downto 0);
phyi_pr_m_cbe_data : in std_logic_vector(3 downto 0);
phyi_pr_m_cbe_cmd : in std_logic_vector(3 downto 0);
phyi_pr_m_first : in std_logic_vector(1 downto 0);
phyi_pv_m_term : in std_logic_vector(1 downto 0);
phyi_pr_m_ltimer : in std_logic_vector(7 downto 0);
phyi_pr_m_burst : in std_logic;
phyi_pr_m_abort : in std_logic_vector(0 downto 0);
phyi_pr_m_perren : in std_logic_vector(0 downto 0);
phyi_pr_m_done_fifo : in std_logic;
phyi_t_abort : in std_logic;
phyi_t_ready : in std_logic;
phyi_t_retry : in std_logic;
phyi_pr_t_state : in std_logic_vector(2 downto 0);
phyi_pv_t_state : in std_logic_vector(2 downto 0);
phyi_pr_t_fstate : in std_logic_vector(1 downto 0);
phyi_pr_t_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_0_last : in std_logic;
phyi_pr_t_cfifo_0_stlast : in std_logic;
phyi_pr_t_cfifo_0_hold : in std_logic;
phyi_pr_t_cfifo_0_valid : in std_logic;
phyi_pr_t_cfifo_0_err : in std_logic;
phyi_pr_t_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_1_last : in std_logic;
phyi_pr_t_cfifo_1_stlast : in std_logic;
phyi_pr_t_cfifo_1_hold : in std_logic;
phyi_pr_t_cfifo_1_valid : in std_logic;
phyi_pr_t_cfifo_1_err : in std_logic;
phyi_pr_t_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_2_last : in std_logic;
phyi_pr_t_cfifo_2_stlast : in std_logic;
phyi_pr_t_cfifo_2_hold : in std_logic;
phyi_pr_t_cfifo_2_valid : in std_logic;
phyi_pr_t_cfifo_2_err : in std_logic;
phyi_pv_t_diswithout : in std_logic;
phyi_pr_t_stoped : in std_logic;
phyi_pr_t_lcount : in std_logic_vector(2 downto 0);
phyi_pr_t_first_word : in std_logic;
phyi_pr_t_cur_acc_0_read : in std_logic;
phyi_pv_t_hold_write : in std_logic;
phyi_pv_t_hold_reset : in std_logic;
phyi_pr_conf_comm_perren : in std_logic;
phyi_pr_conf_comm_serren : in std_logic;
pcio_aden : out std_ulogic;
pcio_vaden : out std_logic_vector(31 downto 0);
pcio_cbeen : out std_logic_vector(3 downto 0);
pcio_frameen : out std_ulogic;
pcio_irdyen : out std_ulogic;
pcio_trdyen : out std_ulogic;
pcio_devselen : out std_ulogic;
pcio_stopen : out std_ulogic;
pcio_ctrlen : out std_ulogic;
pcio_perren : out std_ulogic;
pcio_paren : out std_ulogic;
pcio_reqen : out std_ulogic;
pcio_locken : out std_ulogic;
pcio_serren : out std_ulogic;
pcio_inten : out std_ulogic;
pcio_vinten : out std_logic_vector(3 downto 0);
pcio_req : out std_ulogic;
pcio_ad : out std_logic_vector(31 downto 0);
pcio_cbe : out std_logic_vector(3 downto 0);
pcio_frame : out std_ulogic;
pcio_irdy : out std_ulogic;
pcio_trdy : out std_ulogic;
pcio_devsel : out std_ulogic;
pcio_stop : out std_ulogic;
pcio_perr : out std_ulogic;
pcio_serr : out std_ulogic;
pcio_par : out std_ulogic;
pcio_lock : out std_ulogic;
pcio_power_state : out std_logic_vector(1 downto 0);
pcio_pme_enable : out std_ulogic;
pcio_pme_clear : out std_ulogic;
pcio_int : out std_ulogic;
pcio_rst : out std_ulogic;
phyo_pciv_rst : out std_ulogic;
phyo_pciv_gnt : out std_ulogic;
phyo_pciv_idsel : out std_ulogic;
phyo_pciv_ad : out std_logic_vector(31 downto 0);
phyo_pciv_cbe : out std_logic_vector(3 downto 0);
phyo_pciv_frame : out std_ulogic;
phyo_pciv_irdy : out std_ulogic;
phyo_pciv_trdy : out std_ulogic;
phyo_pciv_devsel : out std_ulogic;
phyo_pciv_stop : out std_ulogic;
phyo_pciv_lock : out std_ulogic;
phyo_pciv_perr : out std_ulogic;
phyo_pciv_serr : out std_ulogic;
phyo_pciv_par : out std_ulogic;
phyo_pciv_host : out std_ulogic;
phyo_pciv_pci66 : out std_ulogic;
phyo_pciv_pme_status : out std_ulogic;
phyo_pciv_int : out std_logic_vector(3 downto 0);
phyo_pr_m_state : out std_logic_vector(2 downto 0);
phyo_pr_m_last : out std_logic_vector(1 downto 0);
phyo_pr_m_hold : out std_logic_vector(1 downto 0);
phyo_pr_m_term : out std_logic_vector(1 downto 0);
phyo_pr_t_hold : out std_logic_vector(0 downto 0);
phyo_pr_t_stop : out std_logic;
phyo_pr_t_abort : out std_logic;
phyo_pr_t_diswithout : out std_logic;
phyo_pr_t_addr_perr : out std_logic;
phyo_pcirsto : out std_logic_vector(0 downto 0);
phyo_pr_po_ad : out std_logic_vector(31 downto 0);
phyo_pr_po_aden : out std_logic_vector(31 downto 0);
phyo_pr_po_cbe : out std_logic_vector(3 downto 0);
phyo_pr_po_cbeen : out std_logic_vector(3 downto 0);
phyo_pr_po_frame : out std_logic;
phyo_pr_po_frameen : out std_logic;
phyo_pr_po_irdy : out std_logic;
phyo_pr_po_irdyen : out std_logic;
phyo_pr_po_trdy : out std_logic;
phyo_pr_po_trdyen : out std_logic;
phyo_pr_po_stop : out std_logic;
phyo_pr_po_stopen : out std_logic;
phyo_pr_po_devsel : out std_logic;
phyo_pr_po_devselen : out std_logic;
phyo_pr_po_par : out std_logic;
phyo_pr_po_paren : out std_logic;
phyo_pr_po_perr : out std_logic;
phyo_pr_po_perren : out std_logic;
phyo_pr_po_lock : out std_logic;
phyo_pr_po_locken : out std_logic;
phyo_pr_po_req : out std_logic;
phyo_pr_po_reqen : out std_logic;
phyo_pr_po_serren : out std_logic;
phyo_pr_po_inten : out std_logic;
phyo_pr_po_vinten : out std_logic_vector(3 downto 0);
phyo_pio_rst : out std_ulogic;
phyo_pio_gnt : out std_ulogic;
phyo_pio_idsel : out std_ulogic;
phyo_pio_ad : out std_logic_vector(31 downto 0);
phyo_pio_cbe : out std_logic_vector(3 downto 0);
phyo_pio_frame : out std_ulogic;
phyo_pio_irdy : out std_ulogic;
phyo_pio_trdy : out std_ulogic;
phyo_pio_devsel : out std_ulogic;
phyo_pio_stop : out std_ulogic;
phyo_pio_lock : out std_ulogic;
phyo_pio_perr : out std_ulogic;
phyo_pio_serr : out std_ulogic;
phyo_pio_par : out std_ulogic;
phyo_pio_host : out std_ulogic;
phyo_pio_pci66 : out std_ulogic;
phyo_pio_pme_status : out std_ulogic;
phyo_pio_int : out std_logic_vector(3 downto 0);
phyo_poo_ad : out std_logic_vector(31 downto 0);
phyo_poo_aden : out std_logic_vector(31 downto 0);
phyo_poo_cbe : out std_logic_vector(3 downto 0);
phyo_poo_cbeen : out std_logic_vector(3 downto 0);
phyo_poo_frame : out std_logic;
phyo_poo_frameen : out std_logic;
phyo_poo_irdy : out std_logic;
phyo_poo_irdyen : out std_logic;
phyo_poo_trdy : out std_logic;
phyo_poo_trdyen : out std_logic;
phyo_poo_stop : out std_logic;
phyo_poo_stopen : out std_logic;
phyo_poo_devsel : out std_logic;
phyo_poo_devselen : out std_logic;
phyo_poo_par : out std_logic;
phyo_poo_paren : out std_logic;
phyo_poo_perr : out std_logic;
phyo_poo_perren : out std_logic;
phyo_poo_lock : out std_logic;
phyo_poo_locken : out std_logic;
phyo_poo_req : out std_logic;
phyo_poo_reqen : out std_logic;
phyo_poo_serren : out std_logic;
phyo_poo_inten : out std_logic;
phyo_poo_vinten : out std_logic_vector(3 downto 0)
);
end component;
end;
| gpl-2.0 | fdcdcfc742cebf1f14d818894afbad7a | 0.534577 | 3.355658 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-ztex-ufm-115/ahb2mig_ztex.vhd | 1 | 15,799 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_ztex
-- File: ahb2mig_ztex.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus.
-------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_ztex is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
MEMCLK_PERIOD : integer := 5000
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem : in std_logic
);
end ;
architecture rtl of ahb2mig_ztex is
component mig_37
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
signal r, rin : reg_type;
signal i : mcb_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
MCB_inst : entity work.mig_37 generic map(
C3_RST_ACT_LOW => 1,
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_MEMCLK_PERIOD => MEMCLK_PERIOD
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_sys_clk => clk_mem,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error
);
end;
| gpl-2.0 | 5015dc1f6b651d2bb333b8aa439b73b7 | 0.506298 | 3.051767 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/hynix/ddr2/components.vhd | 1 | 2,022 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2007 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declaration of Hynix RAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.HY5PS121621F_PACK.all;
package components is
component HY5PS121621F
generic (
TimingCheckFlag : boolean := TRUE;
PUSCheckFlag : boolean := FALSE;
Part_Number : PART_NUM_TYPE := B400;
bbits : natural := 64;
index : integer := 0;
fname : string := "ram.srec";
fdelay : integer := 0);
Port ( DQ : inout std_logic_vector(15 downto 0) := (others => 'Z');
LDQS : inout std_logic := 'Z';
LDQSB : inout std_logic := 'Z';
UDQS : inout std_logic := 'Z';
UDQSB : inout std_logic := 'Z';
LDM : in std_logic;
WEB : in std_logic;
CASB : in std_logic;
RASB : in std_logic;
CSB : in std_logic;
BA : in std_logic_vector(1 downto 0);
ADDR : in std_logic_vector(12 downto 0);
CKE : in std_logic;
CLK : in std_logic;
CLKB : in std_logic;
UDM : in std_logic );
End component;
end;
-- pragma translate_on
| gpl-2.0 | c66001c290752e92e45d31d282db1d97 | 0.498022 | 3.895954 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-vc707/leon3mp.vhd | 1 | 40,851 | -----------------------------------------------------------------------------
-- LEON3 Xilinx VC707 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.grusb.all;
use gaisler.can.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false;
autonegotiation : integer := 1
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(4 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
usb_refclk_opt : in std_logic;
usb_clkout : in std_logic;
usb_d : inout std_logic_vector(7 downto 0);
usb_nxt : in std_logic;
usb_stp : out std_logic;
usb_dir : in std_logic;
usb_resetn : out std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
txp : out std_logic;
txn : out std_logic;
rxp : in std_logic;
rxn : in std_logic;
emdio : inout std_logic;
emdc : out std_ulogic;
eint : in std_ulogic;
erst : out std_ulogic;
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
spi_data_out : in std_logic;
spi_data_in : out std_ulogic;
spi_data_cs_b : out std_ulogic;
spi_clk : out std_ulogic
);
end;
architecture rtl of leon3mp is
component sgmii_vc707
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
autonegotiation : integer := 1
);
port(
sgmiii : in eth_sgmii_in_type;
sgmiio : out eth_sgmii_out_type;
gmiii : out eth_in_type;
gmiio : in eth_out_type;
reset : in std_logic; -- Asynchronous reset for entire core.
button : in std_logic;
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component ahb2mig_series7
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ddr_dummy
port (
ddr_dq : inout std_logic_vector(63 downto 0);
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dqs_n : inout std_logic_vector(7 downto 0);
ddr_addr : out std_logic_vector(13 downto 0);
ddr_ba : out std_logic_vector(2 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_cke : out std_logic_vector(0 downto 0);
ddr_cs_n : out std_logic_vector(0 downto 0);
ddr_dm : out std_logic_vector(7 downto 0);
ddr_odt : out std_logic_vector(0 downto 0)
);
end component ;
--constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRUSBHC+CFG_GRUSBDC+CFG_GRUSB_DCL;
constant maxahbm : integer := 16;
--constant maxahbs : integer := 1+CFG_DSU+CFG_MCTRL_LEON2+CFG_AHBROMEN+CFG_AHBRAMEN+2+CFG_GRUSBDC;
constant maxahbs : integer := 16;
constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT+CFG_AHBSTAT+CFG_GRUSBHC+CFG_GRUSBDC;
signal vcc, gnd : std_logic_vector(31 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal ui_clk : std_ulogic;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgiu : clkgen_in_type;
signal cgo, cgo2, cgou : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal sgmiii : eth_sgmii_in_type;
signal sgmiio : eth_sgmii_out_type;
signal sgmiirst : std_logic;
signal buttonsgmi : std_logic;
signal ethernet_phy_int : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal egtx_clk :std_ulogic;
signal negtx_clk :std_ulogic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, uclk ,ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
constant BOARD_FREQ : integer := 200000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal dsurx_int : std_logic;
signal dsutx_int : std_logic;
signal dsuctsn_int : std_logic;
signal dsurtsn_int : std_logic;
signal dsu_sel : std_logic;
signal usbi : grusb_in_vector(0 downto 0);
signal usbo : grusb_out_vector(0 downto 0);
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal clkref : std_logic;
signal migrstn : std_logic;
attribute keep : boolean;
attribute syn_keep : string;
attribute keep of clkm : signal is true;
attribute keep of uclk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_gen : if (CFG_MIG_SERIES7 = 0) generate
clk_pad_ds : clkpad_ds generic map (tech => padtech, level => sstl, voltage => x15v) port map (clk200p, clk200n, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, open, open);
end generate;
reset_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1, syncin => 0)
port map (rst, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_SERIES7 = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, '1', migrstn, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui_break_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech) port map (button(3), dsui.break);
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.extclk <= '0';
end generate;
nouah : if CFG_AHB_UART = 0 generate
apbo(7) <= apb_none;
duo.txd <= '0';
duo.rtsn <= '0';
dui.extclk <= '0';
end generate;
sw4_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (switch(4), '0', '1', dsu_sel);
dsutx_int <= duo.txd when dsu_sel = '1' else u1o.txd;
dui.rxd <= dsurx_int when dsu_sel = '1' else '1';
u1i.rxd <= dsurx_int when dsu_sel = '0' else '1';
dsurtsn_int <= duo.rtsn when dsu_sel = '1' else u1o.rtsn;
dui.ctsn <= dsuctsn_int when dsu_sel = '1' else '1';
u1i.ctsn <= dsuctsn_int when dsu_sel = '0' else '1';
dsurx_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech) port map (dsurx, dsurx_int);
dsutx_pad : outpad generic map (level => cmos, voltage => x18v, tech => padtech) port map (dsutx, dsutx_int);
dsuctsn_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech) port map (dsuctsn, dsuctsn_int);
dsurtsn_pad : outpad generic map (level => cmos, voltage => x18v, tech => padtech) port map (dsurtsn, dsurtsn_int);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+1)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+1),
open, open, open, open, open, open, open, gnd(0));
end generate;
nojtag : if CFG_AHB_JTAG = 0 generate apbo(CFG_NCPU+1) <= apb_none; end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 26, tech => padtech, level => cmos, voltage => x18v)
port map (address(25 downto 0), memo.address(26 downto 1));
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (oen, memo.oen);
adv_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (adv, '0');
wri_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16, level => cmos, voltage => x18v)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (romsn, vcc(0)); --ahbso(0) <= ahbso_none;
end generate;
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_SERIES7 = 1) generate
ddrc : ahb2mig_series7 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#C00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => rstraw,
clk_amba => clkm,
sys_clk_p => clk200p,
sys_clk_n => clk200n,
clk_ref_i => clkref,
ui_clk => clkm,
ui_clk_sync_rst => open
);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
end generate;
no_mig_gen : if (CFG_MIG_SERIES7 = 0) generate
ahbram0 : ahbram
generic map (hindex => 4, haddr => 16#400#, tech => CFG_MEMTECH, kbytes => 128)
port map ( rstn, clkm, ahbsi, ahbso(4));
ddrdummy0 : ddr_dummy
port map (
ddr_dq => ddr3_dq,
ddr_dqs => ddr3_dqs_p,
ddr_dqs_n => ddr3_dqs_n,
ddr_addr => ddr3_addr,
ddr_ba => ddr3_ba,
ddr_ras_n => ddr3_ras_n,
ddr_cas_n => ddr3_cas_n,
ddr_we_n => ddr3_we_n,
ddr_reset_n => ddr3_reset_n,
ddr_ck_p => ddr3_ck_p,
ddr_ck_n => ddr3_ck_n,
ddr_cke => ddr3_cke,
ddr_cs_n => ddr3_cs_n,
ddr_dm => ddr3_dm,
ddr_odt => ddr3_odt
);
calib_done <= '1';
end generate;
led2_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (led(2), calib_done);
led3_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (led(3), lock);
led4_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (led(4), ahbso(4).hready);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => gmiii, etho => gmiio);
sgmiirst <= not rstraw;
sgmii0 : sgmii_vc707
generic map(
pindex => 11,
paddr => 11,
pmask => 16#fff#,
autonegotiation => autonegotiation
)
port map(
sgmiii => sgmiii,
sgmiio => sgmiio,
gmiii => gmiii,
gmiio => gmiio,
reset => sgmiirst,
button => buttonsgmi,
apb_clk => clkm,
apb_rstn => rstn,
apbi => apbi,
apbo => apbo(11)
);
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v) port map (button(2), buttonsgmi);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (emdio, sgmiio.mdio_o, sgmiio.mdio_oe, sgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (emdc, sgmiio.mdc);
eint_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (eint, sgmiii.mdint);
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (erst, sgmiio.reset);
sgmiii.clkp <= gtrefclk_p;
sgmiii.clkn <= gtrefclk_n;
txp <= sgmiio.txp;
txn <= sgmiio.txn;
sgmiii.rxp <= rxp;
sgmiii.rxn <= rxn;
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc
generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-------------------------------------------------------------------------------
-- USB ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that more than one USB component can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
-- Incoming 60 MHz clock from transceiver, arch 3 = through BUFGDLL or
-- arch 2 = through BUFG or similiar.
--usb_clkout_pad : clkpad
--generic map (tech => padtech, arch => 3)
--port map (usb_clkout, uclk, cgo.clklock, ulock);
usb_clkout_pad : clkpad generic map (tech => padtech, arch => 2) port map (usb_clkout,uclk);
usb_d_pad: iopadv
generic map(tech => padtech, width => 8)
port map (usb_d, usbo(0).dataout(7 downto 0), usbo(0).oen,
usbi(0).datain(7 downto 0));
usb_nxt_pad : inpad generic map (tech => padtech)
port map (usb_nxt, usbi(0).nxt);
usb_dir_pad : inpad generic map (tech => padtech)
port map (usb_dir, usbi(0).dir);
usb_resetn_pad : outpad generic map (tech => padtech)
port map (usb_resetn, usbo(0).reset);
usb_stp_pad : outpad generic map (tech => padtech)
port map (usb_stp, usbo(0).stp);
end generate usbpads;
nousb: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
--ulock <= '1';
usb_resetn_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_resetn, '0');
usb_stp_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_stp, '0');
end generate nousb;
-----------------------------------------------------------------------------
-- USB 2.0 Host Controller
-----------------------------------------------------------------------------
usbhc0: if CFG_GRUSBHC = 1 generate
usbhc0 : grusbhc
generic map (
ehchindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
ehcpindex => 13, ehcpaddr => 13, ehcpirq => 13, ehcpmask => 16#fff#,
uhchindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1,
uhchsindex => 8, uhchaddr => 16#A00#, uhchmask => 16#fff#, uhchirq => 9, tech => fabtech,
memtech => memtech, ehcgen => CFG_GRUSBHC_EHC, uhcgen => CFG_GRUSBHC_UHC,
endian_conv => CFG_GRUSBHC_ENDIAN, be_regs => CFG_GRUSBHC_BEREGS,
be_desc => CFG_GRUSBHC_BEDESC, uhcblo => CFG_GRUSBHC_BLO,
bwrd => CFG_GRUSBHC_BWRD, vbusconf => CFG_GRUSBHC_VBUSCONF)
port map (
clkm,uclk,rstn,apbi,apbo(13),ahbmi,ahbsi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1
downto
CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1),
ahbso(8 downto 8),
usbo,usbi);
end generate usbhc0;
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 8, hirq => 6, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
aiface => CFG_GRUSBDC_AIFACE, uiface => 1,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech, keepclk => 1)
port map(
uclk => uclk,
usbi => usbi(0),
usbo => usbo(0),
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
memtech => memtech, keepclk => 1, uiface => 1)
port map (
uclk, usbi(0), usbo(0), clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH));
end generate usb_dcl0;
----------------------------------------------------------------------
--- I2C Controller --------------------------------------------------
----------------------------------------------------------------------
--i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 11, filter => 9)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
--end generate i2cm;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 3 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 4 to 5 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (button(i-4), gpioi.din(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
serrx_pad : outpad generic map (level => cmos, voltage => x18v, tech => padtech)
port map (led(5), rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x18v, tech => padtech)
port map (led(6), txd1);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(12), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_in, spio.mosi);
sck_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_cs_b, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_in, vcc(0));
sck_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_clk, gnd(0));
slvsel_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_cs_b, vcc(0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 3, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
-- pragma translate_on
test1_gen : if (testahb = false) generate
ahbram0 : ahbram generic map (hindex => 3, haddr => 16#200#,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(3));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRUSBDC+CFG_GRUSBHC*2+CFG_GRUSB_DCL) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx VC707 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | d35398fca9bc3192d9ec231abbbaaa11 | 0.535066 | 3.535659 | false | false | false | false |
Luisda199824/ProcesadorMonociclo | Alu.vhd | 1 | 1,772 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Alu is
Port ( AluOp : in STD_LOGIC_VECTOR (5 downto 0);
rs1 : in STD_LOGIC_VECTOR (31 downto 0);
rs2 : in STD_LOGIC_VECTOR (31 downto 0);
c : in STD_LOGIC;
AluResult : out STD_LOGIC_VECTOR (31 downto 0));
end Alu;
architecture Behavioral of Alu is
begin
process(AluOp, rs1, rs2, c)
begin
case (AluOp) is
when "000000" => -- Add
AluResult <= rs1 - rs2;
when "000001" => -- Sub
AluResult <= rs1 - rs2;
when "000010" => -- Or
AluResult <= rs1 or rs2;
when "000011" => -- And
AluResult <= rs1 and rs2;
when "000100" => -- Xor
AluResult <= rs1 xor rs2;
when "000101" => -- Or n
AluResult <= rs1 or not rs2;
when "000110" => -- And n
AluResult <= rs1 and not rs2;
when "000111" => -- Xnor
AluResult <= rs1 xnor rs2;
when "001000" => -- Addcc
AluResult <= rs1 + rs2;
when "001001" => -- Subcc
AluResult <= rs1 - rs2;
when "001010" => -- Addx
AluResult <= rs1 + rs2 + c;
when "001011" => -- Addxcc
AluResult <= rs1 + rs2 + c;
when "001100" => -- Subx
AluResult <= rs1 - rs2 - c;
when "001101" => -- Subxcc
AluResult <= rs1 - rs2 - c;
when "001110" => -- Orcc
AluResult <= rs1 or rs2;
when "001111" => -- Andcc
AluResult <= rs1 and rs2;
when "010000" => -- Xorcc
AluResult <= rs1 xor rs2;
when "010001" => -- Andncc
AluResult <= rs1 and not rs2;
when "010010" => -- Orncc
AluResult <= rs1 or not rs2;
when "010011" => -- Xnorncc
AluResult <= rs1 xnor rs2;
when others =>
AluResult <= (others => '0');
end case;
end process;
end Behavioral; | mit | 11d9101a50244948754e50bccdf6c10b | 0.573363 | 2.943522 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-sp605/testbench.vhd | 1 | 16,732 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library hynix;
use hynix.components.all;
library micron;
use work.config.all; -- configuration
entity testbench is
generic (
pcie_target_simulation : integer := 0; -- set to 1 to test pci express, only if pcie_target is enabled
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := 40;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_mii_int_n : std_ulogic;
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr3_tdqs_n : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_reset_n: std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(7 downto 0);
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
constant lresp : boolean := false;
-----------------------------------------------------FOR PCIE---------------
function REF_CLK_HALF_CYCLE(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 5000; -- 100 MHz / 5000 ps half-cycle
when 1 => return 4000; -- 125 MHz / 4000 ps half-cycle
when others => return 1; -- invalid case
end case;
end REF_CLK_HALF_CYCLE;
component xilinx_pcie_2_0_rport_v6 is
generic
(
REF_CLK_FREQ : integer := 0;
ALLOW_X8_GEN2 : boolean := FALSE;
PL_FAST_TRAIN : boolean := FALSE;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
DEVICE_ID : bit_vector := X"0007";
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
LTSSM_MAX_LINK_WIDTH : bit_vector := X"08";
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
USER_CLK_FREQ : integer := 3;
VC0_TX_LASTPACKET : integer := 31;
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
VC0_TOTAL_CREDITS_CD : integer := 154;
VC0_TOTAL_CREDITS_PD : integer := 154
);
port (
sys_clk : in std_logic;
sys_reset_n : in std_logic;
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0)
);
end component xilinx_pcie_2_0_rport_v6;
component sys_clk_gen is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk : out std_logic
);
end component sys_clk_gen;
component sys_clk_gen_ds is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk_p : out std_logic;
sys_clk_n : out std_logic
);
end component sys_clk_gen_ds;
--
-- System reset
--
signal sys_reset_n : std_logic;
--
-- System clocks
--
signal rp_sys_clk : std_logic;
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
--
-- PCI-Express Serial Interconnect
--
signal ep_pci_exp_txn : std_logic_vector(0 downto 0);
signal ep_pci_exp_txp : std_logic_vector(0 downto 0);
signal rp_pci_exp_txn : std_logic_vector(0 downto 0);
signal rp_pci_exp_txp : std_logic_vector(0 downto 0);
--
-- Misc. signals
--
signal led_0 : std_logic;
signal led_1 : std_logic;
signal led_2 : std_logic;
-----------------------------------------------pcie end--------------
begin
-- clock and reset
clk27 <= not clk27 after ct * 1 ns;
clk33 <= not clk33 after 15 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch <= "0000";
---------------------pcie----------------------------------------------
pcie_sim: if pcie_target_simulation = 1 generate
RP : xilinx_pcie_2_0_rport_v6
generic map (
REF_CLK_FREQ => 1,
PL_FAST_TRAIN => TRUE,
ALLOW_X8_GEN2 => FALSE,
LINK_CAP_MAX_LINK_SPEED => X"1",
DEVICE_ID => X"0007",
LINK_CAP_MAX_LINK_WIDTH => X"01",
LTSSM_MAX_LINK_WIDTH => X"01",
LINK_CAP_MAX_LINK_WIDTH_int => 1,
LINK_CTRL2_TARGET_LINK_SPEED => X"1",
DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
USER_CLK_FREQ => 3,
VC0_TX_LASTPACKET => 31,
VC0_RX_RAM_LIMIT => X"03FF",
VC0_TOTAL_CREDITS_CD => 154,
VC0_TOTAL_CREDITS_PD => 154
)
port map (
-- SYS Inteface
sys_clk => rp_sys_clk,
sys_reset_n => sys_reset_n,
-- PCI-Express Interface
pci_exp_txn => rp_pci_exp_txn,
pci_exp_txp => rp_pci_exp_txp,
pci_exp_rxn => ep_pci_exp_txn,
pci_exp_rxp => ep_pci_exp_txp
);
--
-- Generate system clocks and reset
--
CLK_GEN_RP : sys_clk_gen
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk => rp_sys_clk
);
CLK_GEN_EP : sys_clk_gen_ds
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk_p => ep_sys_clk_p,
sys_clk_n => ep_sys_clk_n
);
BOARD_INIT : process
begin
report("[" & time'image(now) & "] : System Reset Asserted...");
sys_reset_n <= '0';
for n in 0 to 499 loop
wait until rising_edge(ep_sys_clk_p);
end loop;
report("[" & time'image(now) & "] : System Reset De-asserted...");
sys_reset_n <= '1';
wait until falling_edge(sys_reset_n); -- forever
end process BOARD_INIT;
end generate;
--------------------------------------pcie---------------------------
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk27, clk200p, clk200n, clk33, address(24 downto 1),
data, oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_reset_n, ddr_we, ddr_ras, ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, button,
switch, led,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data,
phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_mii_int_n,
iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spi_sel_n, spi_clk, spi_mosi, ep_pci_exp_txn(0), ep_pci_exp_txp(0), rp_pci_exp_txn(0),
rp_pci_exp_txp(0), ep_sys_clk_p, ep_sys_clk_n, sys_reset_n,
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_d
);
-- prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
-- port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
-- writen, oen);
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
address(0) <= '0';
u1 : entity micron.ddr3
port map ( rst_n => ddr_reset_n, dq => ddr_dq,
tdqs_n => ddr3_tdqs_n,
dqs => ddr_dqs, dqs_n => ddr_dqsn,
dm_tdqs => ddr_dm, we_n => ddr_we, cas_n => ddr_cas,
ras_n => ddr_ras, cs_n => ddr_csb, ba => ddr_ba,
addr => ddr_ad(12 downto 0), cke => ddr_cke,
ck => ddr_clk, ck_n => ddr_clkb, odt => ddr_odt) ;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(phy_rst_n, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
end generate;
sysace_mpirq <= '0';
sysace_d <= (others => 'Z');
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
| gpl-2.0 | 6fe4906910816adbbc20bfe282863e07 | 0.557076 | 3.051058 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-c5ekit/pllsim.vhd | 1 | 1,440 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
entity syspll1 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end;
architecture sim of syspll1 is
begin
p: process
variable vclk: std_logic := '0';
begin
outclk_0 <= vclk;
wait for 5.555 ns;
vclk := not vclk;
end process;
locked <= '0', '1' after 1 us;
end;
| gpl-2.0 | 2714d172e7cda03d54e101d200a7f356 | 0.63125 | 3.870968 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/mmu_acache.vhd | 1 | 14,409 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_acache
-- File: mmu_acache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Interface module between (MMU,I/D cache controllers) and Amba AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_acache is
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
mcmmi : in memory_mm_in_type;
mcmmo : out memory_mm_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_acache is
type reg_type is record -- cache control register type
bg : std_logic; -- bus grant
bo : std_logic_vector(1 downto 0); -- bus owner
ba : std_logic; -- bus active
lb : std_ulogic; -- last burst cycle
retry : std_logic; -- retry/split pending
retry2 : std_ulogic; -- retry/split pending
werr : std_logic; -- write error
hlocken : std_ulogic; -- ready to perform locked transaction
hcache : std_logic; -- cacheable access
nba : std_ulogic;
nbo : std_logic_vector(1 downto 0); -- bus owner
end record;
type reg2_type is record
reqmsk : std_logic_vector(2 downto 0);
hclken2 : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : reg_type := (
bg => '0',
bo => (others => '0'),
ba => '0',
lb => '0',
retry => '0',
retry2 => '0',
werr => '0',
hlocken => '0',
hcache => '0',
nba => '0',
nbo => (others => '0')
);
constant R2RES : reg2_type := (
reqmsk => (others => '0'), hclken2 => '0'
);
constant L3DI :integer := GAISLER_LEON3
;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, L3DI, 0, LEON3_VERSION, 0),
others => zero32);
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
function dec_fixed(haddr : std_logic_vector(3 downto 0);
cached : integer)
return std_ulogic is
begin
if (cached /= 0) then return ctbl(conv_integer(haddr(3 downto 0)));
else return('1'); end if;
end;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
begin
comb : process(ahbi, r, rst, mcii, mcdi, mcmmi, ahbso, hclken, r2)
variable v : reg_type;
variable v2 : reg2_type;
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_logic; -- read/write
variable hlock : std_logic; -- bus lock
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_logic; -- bus request
variable iready, dready, mmready : std_logic;
variable igrant, dgrant, mmgrant : std_logic;
variable iretry, dretry, mmretry : std_logic;
variable ihcache, dhcache, mmhcache, dec_hcache : std_logic;
variable imexc, dmexc, mmmexc : std_logic;
variable dreq : std_logic;
variable nbo : std_logic_vector(1 downto 0);
variable su, nb, bo_icache : std_ulogic;
variable scanen : std_ulogic;
variable vreqmsk: std_ulogic;
variable burst : std_ulogic;
begin
-- initialisation
htrans := HTRANS_IDLE;
v := r; v.werr := '0'; v2 := r2;
iready := '0'; dready := '0'; mmready := '0';
igrant := '0'; dgrant := '0'; mmgrant := '0';
imexc := '0'; dmexc := '0'; mmmexc := '0'; hlock := '0';
iretry := '0'; dretry := '0'; mmretry := '0';
ihcache := '0'; dhcache := '0'; mmhcache := '0'; su := '0';
if (r.bo = "00") then bo_icache := '1'; else bo_icache := '0'; end if;
haddr := (others => '0');
hwrite := '0';
hsize := (others => '0');
hlock := '0';
hburst := (others => '0');
if ahbi.hready = '1' then v.lb := '0'; end if;
if scantest = 1 then scanen := ahbi.scanen; else scanen := '0'; end if;
v.retry2 := (r.retry or r.retry2) and not (r.ba and not r.retry);
vreqmsk := orv(r2.reqmsk);
-- generate AHB signals
dreq := mcdi.req;
hwdata := mcdi.data;
hbusreq := '0';
if (mcii.req = '1') and ((clk2x = 0) or (r2.reqmsk(2) = '1')) and (r.hlocken = '0') and
not (( ((r.ba and dreq) = '1') and (r.bo = "01")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "00";
hbusreq := '1'; burst := mcii.burst;
htrans := HTRANS_NONSEQ;
elsif (dreq = '1') and ((clk2x = 0) or (r2.reqmsk(1) = '1')) and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "01";
hbusreq := '1'; burst := mcdi.burst;
if (not mcdi.lock or r.hlocken) = '1' then htrans := HTRANS_NONSEQ; end if;
elsif (mcmmi.req = '1') and ((clk2x = 0) or (r2.reqmsk(0) = '1')) and (r.hlocken = '0') and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and dreq) = '1') and (r.bo = "01"))) then
nbo := "10";
hbusreq := '1'; burst := '0';
htrans := HTRANS_NONSEQ;
else
nbo := "11"; burst := '0';
end if;
-- dont change bus master if we have started driving htrans
if r.nba = '1' then
nbo := r.nbo; hbusreq := '1'; htrans := HTRANS_NONSEQ;
end if;
-- dont change bus master on retry
if (r.retry2 and not r.ba) = '1' then
nbo := r.bo; hbusreq := '1'; htrans := HTRANS_NONSEQ;
end if;
dec_hcache := ahb_slv_dec_cache(mcdi.address, ahbso, cached);
if nbo = "10" then
haddr := mcmmi.address; hwrite := not mcmmi.read; hsize := '0' & mcmmi.size;
hlock := mcmmi.lock;
htrans := HTRANS_NONSEQ; hburst := HBURST_SINGLE;
if (mcmmi.req and r.bg and ahbi.hready and not r.retry) = '1'
then mmgrant := '1'; v.hcache := dec_fixed(haddr(31 downto 28), cached); end if;
elsif nbo = "00" then
haddr := mcii.address; hwrite := '0'; hsize := HSIZE_WORD; hlock := '0';
su := mcii.su;
if ((mcii.req and r.ba) = '1') and (r.bo = "00") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
if (((ilinesize = 4) and haddr(3 downto 2) = "10")
or ((ilinesize = 8) and haddr(4 downto 2) = "110")) and (ahbi.hready = '1')
then v.lb := '1'; end if;
end if;
if mcii.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (mcii.req and r.bg and ahbi.hready and not r.retry) = '1'
then igrant := '1'; v.hcache := dec_fixed(haddr(31 downto 28), cached); end if;
elsif nbo = "01" then
haddr := mcdi.address; hwrite := not mcdi.read; hsize := '0' & mcdi.size;
hlock := mcdi.lock;
if mcdi.asi /= "1010" then su := '1'; else su := '0'; end if; --ASI_UDATA
if mcdi.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if ((dreq and r.ba) = '1') and (r.bo = "01") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
hburst := HBURST_INCR;
end if;
if (dreq and r.bg and ahbi.hready and not r.retry) = '1'
then dgrant := (not mcdi.lock or r.hlocken) or r.retry2; v.hcache := dec_hcache; end if;
end if;
if (hclken = '1') or (clk2x = 0) then
if (r.ba = '1') and ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT))
then v.retry := not ahbi.hready; else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if r.bo = "10" then
hwdata := mcmmi.data;
if r.ba = '1' then
mmhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => mmready := '1';
when HRESP_RETRY | HRESP_SPLIT=> mmretry := '1';
when others => mmready := '1'; mmmexc := '1'; v.werr := not mcmmi.read;
end case;
end if;
end if;
elsif r.bo = "00" then
if r.ba = '1' then
ihcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => iready := '1';
when HRESP_RETRY | HRESP_SPLIT=> iretry := '1';
when others => iready := '1'; imexc := '1';
end case;
end if;
end if;
elsif r.bo = "01" then
if r.ba = '1' then
dhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => dready := '1';
when HRESP_RETRY | HRESP_SPLIT=> dretry := '1';
when others => dready := '1'; dmexc := '1'; v.werr := not mcdi.read;
end case;
end if;
end if;
hlock := mcdi.lock or ((r.retry or (r.retry2 and not r.ba)) and r.hlocken);
end if;
if nbo = "01" and ((hsize = "011") or ((mcdi.read and mcdi.cache) = '1')) then
hsize := "010";
end if;
if (r.bo = "01") and (hlock = '1') then nbo := "01"; end if;
if ahbi.hready = '1' then
if r.retry = '0' then v.bo := nbo; end if;
v.bg := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else v.ba := '0'; end if;
v.hlocken := hlock and ahbi.hgrant(hindex);
if (clk2x /= 0) then
igrant := igrant and vreqmsk;
dgrant := dgrant and vreqmsk;
mmgrant := mmgrant and vreqmsk;
if (r.bo = nbo) then v.ba := v.ba and vreqmsk; end if;
end if;
end if;
if hburst = HBURST_SINGLE then nb := '1'; else nb := '0'; end if;
v.nbo := nbo; v.nba := orv(htrans) and not v.ba;
-- parity generation
if (clk2x /= 0) then
v2.hclken2 := hclken;
if hclken = '1' then
v2.reqmsk := mcii.req & mcdi.req & mcmmi.req;
if (clk2x > 8) and (r2.hclken2 = '1') then v2.reqmsk := "111"; end if;
end if;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.bg := '0'; v.bo := "00"; v.ba := '0'; v.retry := '0'; v.werr := '0'; v.lb := '0';
v.hcache := '0'; v.hlocken := '0'; v.nba := '0'; v.nbo := "00";
v.retry2 := '0';
end if;
-- drive ports
ahbo.haddr <= haddr ;
ahbo.htrans <= htrans;
-- ahbo.hbusreq <= hbusreq and not r.lb and not ((((not bo_icache) and r.ba) or nb) and r.bg);
-- ahbo.hbusreq <= hbusreq and not r.lb and not((not burst) and r.bg);
ahbo.hbusreq <= hbusreq and (not r.lb or orv(nbo)) and (burst or not r.bg);
ahbo.hwdata <= ahbdrivedata(hwdata);
ahbo.hlock <= hlock;
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hindex <= hindex;
if nbo = "00" then ahbo.hprot <= "11" & su & '0';
else ahbo.hprot <= "11" & su & '1'; end if;
mcio.grant <= igrant;
mcio.ready <= iready;
mcio.mexc <= imexc;
mcio.retry <= iretry;
mcio.cache <= ihcache;
mcdo.grant <= dgrant;
mcdo.ready <= dready;
mcdo.mexc <= dmexc;
mcdo.retry <= dretry;
mcdo.werr <= r.werr;
mcdo.cache <= dhcache;
mcdo.ba <= r.ba;
mcdo.bg <= r.bg and not v.bo(1);
mcmmo.grant <= mmgrant;
mcmmo.ready <= mmready;
mcmmo.mexc <= mmmexc;
mcmmo.retry <= mmretry;
mcmmo.werr <= r.werr;
mcmmo.cache <= mmhcache;
mcio.scanen <= scanen;
mcdo.scanen <= scanen;
mcdo.testen <= ahbi.testen;
rin <= v; r2in <= v2;
end process;
mcio.data <= ahbreadword(ahbi.hrdata);
mcdo.data <= ahbreadword(ahbi.hrdata);
mcmmo.data <= ahbreadword(ahbi.hrdata);
ahbo.hirq <= (others => '0');
ahbo.hconfig <= hconfig;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
reg2gen : if (clk2x /= 0) generate
reg2 : process(clk)
begin
if rising_edge(clk) then
r2 <= r2in;
if RESET_ALL and (rst = '0') then r2 <= R2RES; end if;
end if;
end process;
end generate;
noreg2gen : if (clk2x = 0) generate
r2.reqmsk <= "000";
end generate;
end;
| gpl-2.0 | ede123acfb978ee58dfb6edc45a1dcdf | 0.536678 | 3.321577 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/jtag/jtagcom2.vhd | 1 | 9,301 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: JTAG Debug Interface with AHB master interface
-- Redesigned to work for TCK both slower and faster than AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom2 is
generic (
gatetech: integer := 0;
isel : integer range 0 to 1 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tckp : in std_ulogic;
tckn : in std_ulogic;
trst : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of jtagcom2 is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type tckpreg_type is record
addr : std_logic_vector(34 downto 0);
datashft : std_logic_vector(32 downto 0);
done_sync : std_ulogic;
prun : std_ulogic;
inshift : std_ulogic;
holdn : std_ulogic;
end record;
type tcknreg_type is record
run: std_ulogic;
done_sync1: std_ulogic;
qual_rdata: std_ulogic;
addrlo : std_logic_vector(ADDBITS-1 downto 2);
data : std_logic_vector(32 downto 0);
end record;
type ahbreg_type is record
run_sync: std_logic_vector(1 downto 0);
qual_dreg: std_ulogic;
qual_areg: std_ulogic;
areg: std_logic_vector(34 downto 0);
dreg: std_logic_vector(31 downto 0);
done: std_ulogic;
dmastart: std_ulogic;
wdone: std_ulogic;
end record;
signal ar, arin : ahbreg_type;
signal tpr, tprin: tckpreg_type;
signal tnr, tnrin: tcknreg_type;
signal qual_rdata, rdataq: std_logic_vector(31 downto 0);
signal qual_dreg, dregq: std_logic_vector(31 downto 0);
signal qual_areg, aregqin, aregq: std_logic_vector(34 downto 0);
attribute syn_keep: boolean;
attribute syn_keep of rdataq : signal is true;
attribute syn_keep of dregq : signal is true;
attribute syn_keep of aregq : signal is true;
begin
rdqgen: for x in 31 downto 0 generate
rdq: grnand2 generic map (tech => gatetech) port map (ar.dreg(x), qual_rdata(x), rdataq(x));
end generate;
dqgen: for x in 31 downto 0 generate
dq: grnand2 generic map (tech => gatetech) port map (tnr.data(x), qual_dreg(x), dregq(x));
end generate;
aregqin <= tpr.addr(34 downto ADDBITS) &
tnr.addrlo(ADDBITS-1 downto 2) &
tpr.addr(1 downto 0);
aqgen: for x in 34 downto 0 generate
aq: grnand2 generic map (tech => gatetech) port map (aregqin(x), qual_areg(x), aregq(x));
end generate;
comb : process (rst, ar, tapo, dmao, tpr, tnr, aregq, dregq, rdataq)
variable av : ahbreg_type;
variable tpv : tckpreg_type;
variable tnv : tcknreg_type;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
begin
av := ar; tpv := tpr; tnv := tnr;
---------------------------------------------------------------------------
-- TCK side logic
---------------------------------------------------------------------------
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
vtapi.en := asel or dsel;
vtapi.tdo:=tpr.addr(0);
if dsel='1' then
vtapi.tdo:=tpr.datashft(0) and tpr.holdn;
end if;
write := tpr.addr(34); seq := tpr.datashft(32);
-- Sync regs using alternating phases
tnv.done_sync1 := ar.done;
tpv.done_sync := tnr.done_sync1;
-- Data CDC
qual_rdata <= (others => tnr.qual_rdata);
if tnr.qual_rdata='1' then tpv.datashft(32 downto 0) := '1' & (not rdataq); end if;
if tapo.capt='1' then tpv.addr(ADDBITS-1 downto 2) := tnr.addrlo; end if;
-- Track whether we're in the middle of shifting
if tapo.shift='1' then tpv.inshift:='1'; end if;
if tapo.upd='1' then tpv.inshift:='0'; end if;
if tapo.shift='1' then
if asel = '1' and tpr.prun='0' then tpv.addr(34 downto 0) := tapo.tdi & tpr.addr(34 downto 1); end if;
if dsel = '1' and tpr.holdn='1' then tpv.datashft(32 downto 0) := tapo.tdi & tpr.datashft(32 downto 1); end if;
end if;
if tnr.run='0' then tpv.holdn:='1'; end if;
tpv.prun := tnr.run;
if tpr.prun='0' then
tnv.qual_rdata := '0';
if tapo.shift='0' and tapo.upd = '1' then
if asel='1' then tnv.addrlo := tpr.addr(ADDBITS-1 downto 2); end if;
if dsel='1' then tnv.data := tpr.datashft; end if;
if (asel and not write) = '1' then tpv.holdn := '0'; tnv.run := '1'; end if;
if (dsel and (write or (not write and seq))) = '1' then
tnv.run := '1';
if (seq and not write) = '1' then
tnv.addrlo := tnr.addrlo + 1;
tpv.holdn := '0';
end if;
end if;
end if;
else
if tpr.done_sync='1' and (tpv.inshift='0' or write='1') then
tnv.run := '0';
if write='0' then
tnv.qual_rdata := '1';
end if;
if (write and tnr.data(32)) = '1' then
tnv.addrlo := tnr.addrlo + 1;
end if;
end if;
end if;
if tapo.reset='1' then
tpv.inshift := '0';
tnv.run := '0';
end if;
---------------------------------------------------------------------------
-- AHB side logic
---------------------------------------------------------------------------
-- Sync regs and CDC transfer
av.run_sync := tnr.run & ar.run_sync(1);
qual_dreg <= (others => ar.qual_dreg);
if ar.qual_dreg='1' then av.dreg:=not dregq; end if;
qual_areg <= (others => ar.qual_areg);
if ar.qual_areg='1' then av.areg:=not aregq; end if;
vdmai.address := ar.areg(31 downto 0);
vdmai.wdata := ahbdrivedata(ar.dreg(31 downto 0));
vdmai.start := '0'; vdmai.burst := '0';
vdmai.write := ar.areg(34);
vdmai.busy := '0'; vdmai.irq := '0';
vdmai.size := '0' & ar.areg(33 downto 32);
av.qual_dreg := '0';
av.qual_areg := '0';
vdmai.start := '0';
if ar.dmastart='1' then
if dmao.active='1' then
if dmao.ready='1' then
av.dreg := ahbreadword(dmao.rdata);
if ar.areg(34)='0' then
av.done := '1';
end if;
av.dmastart := '0';
end if;
else
vdmai.start := '1';
if ar.areg(34)='1' and ar.wdone='0' then
av.done := '1';
av.wdone := '1';
end if;
end if;
end if;
if ar.qual_areg='1' then
av.dmastart := '1';
av.wdone := '0';
end if;
if ar.run_sync(0)='1' and ar.qual_areg='0' and ar.dmastart='0' and ar.done='0' then
av.qual_dreg := '1';
av.qual_areg := '1';
end if;
if ar.run_sync(0)='0' and ar.done='1' then
av.done := '0';
end if;
if (rst = '0') then
av.qual_dreg := '0';
av.qual_areg := '0';
av.done := '0';
av.areg := (others => '0');
av.dreg := (others => '0');
av.dmastart := '0';
end if;
tprin <= tpv; tnrin <= tnv; arin <= av; dmai <= vdmai; tapi <= vtapi;
end process;
ahbreg : process(clk)
begin
if rising_edge(clk) then ar <= arin; end if;
end process;
tckpreg: process(tckp,trst)
begin
if rising_edge(tckp) then
tpr <= tprin;
end if;
if trst='0' then
tpr.done_sync <= '0';
tpr.prun <= '0';
tpr.inshift <= '0';
tpr.holdn <= '1';
end if;
end process;
tcknreg: process(tckn,trst)
begin
if rising_edge(tckn) then
tnr <= tnrin;
end if;
if trst='0' then
tnr.run <= '0';
tnr.done_sync1 <= '0';
tnr.qual_rdata <= '0';
end if;
end process;
end;
| gpl-2.0 | f39f856336cf336c3ab85ad118c961c1 | 0.555639 | 3.380952 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/unisim/ddr_phy_unisim.vhd | 1 | 103,327 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: ddr_phy_unisim.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Virtex-2 and Virtex-4
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex4 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex4_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0)
);
end;
architecture rtl of virtex4_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute keep of rclk90b : signal is true;
attribute syn_keep : boolean;
attribute syn_keep of rclk90b : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of rclk90b : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR : component is true;
attribute syn_noprune of ODDR : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddrclkfbl);
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dllfb <= clk_0r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR port map ( Q => ddr_clk_fb_outr, C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclkdiffio : if phyiconf = 0 generate
ddrclocks0 : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad_ds generic map (tech => virtex4, level => sstl2_ii)
port map (ddr_clk(i), ddr_clkb(i), ddr_clkl(i), '1');
end generate;
end generate;
ddrclknodiffio : if phyiconf = 1 generate
ddrclocks1 : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk1_pad : outpad generic map (tech => virtex4, level => sstl2_ii)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR port map ( Q => ddr_clkbl(i), C => clk90r, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
ddrclk1b_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk0r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk0r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk0r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk0r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk0r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clk0r, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk0r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk0r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), -- 1-bit output for negative edge of clock
C => rclk90b, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clk0r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.FDDRRSE;
use unisim.IFDDRRSE;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrv2;
------------------------------------------------------------------
-- Virtex2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex2_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex2_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component oddrv2
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of FDDRRSE : component is true;
attribute syn_noprune of IFDDRRSE : component is true;
attribute syn_noprune of oddrv2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : FDDRRSE port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : FDDRRSE port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : FDDRRSE port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2 port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IFDDRRSE
port map ( Q0 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q1 => dqin(i), -- 1-bit output for negative edge of clock
C0 => rclk90b, -- clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
C1 => rclk270b, -- clk90r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dq(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
-- dinq1 : FD port map ( Q => dqin(i+dbits), C => clk90r, D => dqinl(i));
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrv2
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => open); -- o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR2;
use unisim.IDDR2;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrc3e;
------------------------------------------------------------------
-- Spartan3E DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity spartan3e_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of spartan3e_ddr_phy is
component oddrc3e
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
attribute syn_noprune of oddrc3e : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r;
-- clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR2 port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2 port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2 port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
clkread <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map ( Q0 => dqinl(i), Q1 => dqin(i), C0 => rclk90b, C1 => rclk270b,
CE => vcc, D => ddr_dqin(i), R => gnd, S => gnd );
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrc3e
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDELAY;
use unisim.ISERDES;
use unisim.BUFIO;
use unisim.IDELAYCTRL;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex5 DDR2 PHY ----------------------------------------------
------------------------------------------------------------------
entity virtex5_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0; ddelayb8 : integer := 0;
ddelayb9 : integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := virtex5; odten : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0; abits: integer := 14; nclk: integer := 3;
ncs: integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0)
);
end;
architecture rtl of virtex5_ddr2_phy_wo_pads is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
component OBUFDS
generic (
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT";
SLEW : string := "SLOW"
);
port (
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal cbdqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_rasnr2, ddr_casnr2, ddr_wenr2 : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(nclk-1 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(ncs-1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin, ddr_dqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_cbdqin, ddr_cbdqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_cbdqout : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_cbdqoen : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_adr : std_logic_vector (abits-1 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1+eightbanks downto 0); -- ddr address
signal ddr_adr2 : std_logic_vector (abits-1 downto 0); -- ddr address
signal ddr_bar2 : std_logic_vector (1+eightbanks downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr data mask
signal ddr_cbdmr : std_logic_vector (dbits/8-1 downto 0); -- ddr checkbit mask
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen_reg: std_logic_vector (dbits/8-1 downto 0); -- ddr dqs reg
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsoen_reg: std_logic_vector (dbits/8-1 downto 0); -- ddr dqs reg
signal ddr_cbdqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk, dqsclkn : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
signal clk200, clk200_0, clk200fb, clk200fx, lock200 : std_logic;
signal odtl : std_logic_vector(ncs-1 downto 0);
signal refclk_rdy : std_logic_vector(numidelctrl-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
type ddelay_type is array (0 to 11) of integer;
constant ddelay : ddelay_type := (ddelayb0, ddelayb1, ddelayb2,
ddelayb3, ddelayb4, ddelayb5,
ddelayb6, ddelayb7, ddelayb8,
ddelayb9, ddelayb10, ddelayb11);
attribute syn_noprune : boolean;
attribute syn_noprune of IDELAYCTRL : component is true;
attribute syn_keep : boolean;
attribute syn_keep of dqsclk : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of dqsclk : signal is true;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR : component is true;
attribute syn_noprune of ODDR : component is true;
attribute keep : boolean;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
begin
-- Generate 200 MHz ref clock if not supplied
refclkx : if norefclk = 0 generate
buf_clk200 : BUFG port map( I => clkref200, O => clk200);
lock200 <= '1';
end generate;
norefclkx : if norefclk /= 0 generate
bufg0 : BUFG port map (I => clk200fx, O => clk200);
HMODE_dll200 : if (tech = virtex4 and MHz >= 210) or (tech = virtex5) generate
dll200 : DCM
generic map (
CLKFX_MULTIPLY => 400/MHz, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH",
CLK_FEEDBACK => "NONE")
port map (
CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0),
LOCKED => lock200, CLKFX => clk200fx);
end generate;
LMODE_dll200 : if not ((tech = virtex4 and MHz >= 210) or (tech = virtex5)) generate
dll200 : DCM
generic map (
CLKFX_MULTIPLY => 400/MHz, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",
CLK_FEEDBACK => "NONE")
port map (
CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0),
LOCKED => lock200, CLKFX => clk200fx);
end generate;
end generate;
-- Delay control
idelctrl : for i in 0 to numidelctrl-1 generate
u : IDELAYCTRL port map (rst => dllrst(0), refclk => clk200, rdy => refclk_rdy(i));
end generate;
oe <= not oen;
vcc <= '1';
gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
dll0rst <= dllrst;
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
HMODE_dllm : if (tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div > 140) or (MHz > 120))) generate
dllm : DCM
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
port map (
CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
LMODE_dllm : if not ((tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div > 140) or (MHz > 120)))) generate
dllm : DCM
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map (
CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
end generate;
-- DDR clock generation
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
clk180r <= not mclk;
clkout <= mclk;
dllfb <= clk90r;
HMODE_dll : if (tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120)) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
LMODE_dll : if not ((tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120))) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
rstdel : process (mclk, rst, mlock, lock200)
begin
if rst = '0' or mlock = '0' or lock200 = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
--rcnt : process (clk_0r)
rcnt : process (clkoutret)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
--if rising_edge(clk_0r) then
if rising_edge(clkoutret) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked and orv(refclk_rdy);
-- Generate external DDR clock
ddrclocks : for i in 0 to nclk-1 generate
dclk0r : ODDR port map ( Q => ddr_clk(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddr_clkb(i) <= '0'; -- unused
end generate;
-- ODT
odtgen : for i in 0 to ncs-1 generate
odtl(i) <= locked and orv(refclk_rdy) and odt(i);
ddr_odt(i) <= odtl(i);
end generate;
ddrbanks : for i in 0 to ncs-1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk180r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
ddr_csb(i) <= ddr_csnr(i);
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk180r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
ddr_cke(i) <= ddr_ckenr(i);
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk180r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
ddr_rasb <= ddr_rasnr;
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk180r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
ddr_casb <= ddr_casnr;
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk180r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
ddr_web <= ddr_wenr;
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clkoutret, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
end generate;
ddr_dm <= ddr_dmr;
bagen : for i in 0 to 1+eightbanks generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk180r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
end generate;
ddr_ba <= ddr_bar;
dagen : for i in 0 to abits-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk180r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
end generate;
ddr_ad <= ddr_adr;
-- DQS generation
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
--D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
D1 => dqsn(i), D2 => gnd, R => gnd, S => gnd);
doen_reg : FD port map ( Q => ddr_dqsoen_reg(i), C => clk180r, D => dqsoen);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk90r, D => ddr_dqsoen_reg(i));
end generate;
ddr_dqs_out <= ddr_dqsin;
ddr_dqs_oen <= ddr_dqsoen;
ddr_dqsoutl <= ddr_dqs_in;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
del_dq0 : IDELAY generic map(IOBDELAY_TYPE => "VARIABLE", IOBDELAY_VALUE => ddelay(i/8))
port map(O => ddr_dqin(i), I => ddr_dqin_nodel(i), C => clkoutret, CE => cal_en(i/8),
INC => cal_inc(i/8), RST => cal_rst);
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), --dqin(i), -- 1-bit output for negative edge of clock
C => clk180r, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => clkoutret, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clkoutret, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD
generic map (INIT => '1')
port map ( Q => ddr_dqoen(i), C => clkoutret, D => oen);
end generate;
ddr_dq_out <= ddr_dqout;
ddr_dq_oen <= ddr_dqoen;
ddr_dqin_nodel <= ddr_dq_in;
end;
------------------------------------------------------------------
-- Spartan 3A DDR2 PHY -------------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.IDDR2;
use unisim.ODDR2;
use unisim.FD;
use unisim.BUFIO;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity spartan3a_ddr2_phy is
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan3;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0);
port ( rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- row address
ba : in std_logic_vector ( 2 downto 0); -- bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
odt : in std_logic_vector(1 downto 0));
end;
architecture rtl of spartan3a_ddr2_phy is
component DCM
generic (CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false);
port ( CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG
port (O : out std_logic;
I : in std_logic);
end component;
component ODDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT : bit := '0'; -- Sets initial state of the Q0
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q : out std_ulogic; -- 1-bit DDR output data
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D0 : in std_ulogic; -- 1-bit data input (associated with C1)
D1 : in std_ulogic; -- 1-bit data input (associated with C1)
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component FD
generic (INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT_Q0 : bit := '0'; -- Sets initial state of the Q0
INIT_Q1 : bit := '0'; -- Sets initial state of the Q1
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q0 : out std_ulogic; -- 1-bit output captured with C0 clock
Q1 : out std_ulogic; -- 1-bit output captured with C1 clock
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D : in std_ulogic; -- 1-bit DDR data input
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal ddr_clk_fbl, ddr_clk_fb_outl : std_ulogic;
signal clk_90ro : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal rclk0b, rclk90b, rclk180b, rclk270b : std_ulogic;
signal rclk0, rclk90, rclk180, rclk270 : std_ulogic;
signal rclk0b_high, rclk90b_high, rclk270b_high : std_ulogic;
signal rclk0_high, rclk90_high, rclk270_high : std_ulogic;
signal locked, vlockl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr row address
signal ddr_bar : std_logic_vector (1+eightbanks downto 0); -- ddr bank address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr mask
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqinl : std_logic_vector (dbits*2-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_ulogic;
signal dll1rst : std_ulogic;
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal odtl : std_logic_vector(1 downto 0);
--signals needed for alignment with DQS
signal dm_delay : std_logic_vector (dbits/8-1 downto 0);
signal dqout_delay : std_logic_vector (dbits-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= '1';
elsif rising_edge(clk) then
dll0rst <= '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map (CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation (90 degrees phase-shifted DLL)
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
dllfb <= clk90r;
dll : DCM
generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 64)
port map (CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk0r <= mclk;
clk180r <= not mclk;
clk270r <= not clk90r;
clkout <= mclk;
rstdel : process (mclk, rst, mlock)
begin
if rst = '0' or mlock = '0' then
dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16);
vlock := '0';
elsif vlock = '0' then
cnt := cnt -1;
vlock := cnt(15) and not co;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2
port map (Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2
port map (Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
-- Generate the DDR clock to be fed back for DQ synchronization
dclkfb0r : ODDR2
port map (Q => ddr_clk_fb_outl, C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclkfb_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outl);
-- The above clock fed back for DQ synchronization
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddr_clk_fbl);
-- ODT pads
odtgen : for i in 0 to 1 generate
odtl(i) <= locked and odt(i);
ddr_odt_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_odt(i), odtl(i));
end generate;
-- DDR single-edge control signals
ddrbanks : for i in 0 to 1 generate
csn0gen : FD
port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD
port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : FD
port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD
port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_casb, ddr_casnr);
wengen : FD
port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_web, ddr_wenr);
bagen : for i in 0 to 1+eightbanks generate
ba0 : FD
port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
addrgen : for i in 0 to 13 generate
addr0 : FD
port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- Data mask (DM) generation
dmgen : for i in 0 to dbits/8-1 generate
dq_delay : FD
port map ( Q => dm_delay(i), C => clk0r, D => dm(i));
dm0 : ODDR2
generic map (DDR_ALIGNMENT => "NONE")
port map (Q => ddr_dmr(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dm(i+dbits/8), D1 => dm_delay(i), R => gnd, S => gnd);
ddr_bm_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
-- Data strobe (DQS) generation
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR2
port map ( Q => ddr_dqsin(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsn(i), D1 => gnd, R => gnd, S => gnd);
doen : FD
port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad_ds
generic map (tech => virtex5, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i), i => ddr_dqsin(i),
en => ddr_dqsoen(i), o => ddr_dqsoutl(i));
end generate;
-- Phase shift the feedback clock and use it to latch DQ
rstphase : process (ddr_clk_fbl, rst, lockl)
begin
if rst = '0' or lockl = '0' then
dll1rst <= '1';
elsif rising_edge(ddr_clk_fbl) then
dll1rst <= '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg8 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
bufg9 : BUFG port map (I => rclk180, O => rclk180b);
read_dll : DCM
generic map (clkin_period => 8.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "VARIABLE", PHASE_SHIFT => rskew)
port map ( CLKIN => ddr_clk_fbl, CLKFB => rclk90b, DSSEN => gnd, PSCLK => mclk,
PSEN => cal_pll(0), PSINCDEC => cal_pll(1), RST => dll1rst, CLK0 => rclk90,
CLK90 => rclk180); --, CLK180 => rclk270);
-- Data bus
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map (Q0 => dqinl(i+dbits), -- 1-bit output for positive edge of C0
Q1 => dqinl(i), -- 1-bit output for negative edge of C1
C0 => rclk90b, -- 1-bit clock input
C1 => rclk270b, -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd); -- 1-bit set
dinq0 : FD
port map ( Q => dqin(i+dbits), C => rclk180b, D => dqinl(i));
dinq1 : FD
port map ( Q => dqin(i), C => rclk180b, D => dqinl(i+dbits));
dq_delay : FD
port map ( Q => dqout_delay(i), C => clk0r, D => dqout(i));
dout : ODDR2
generic map (DDR_ALIGNMENT => "NONE")
port map (Q => ddr_dqout(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dqout(i+dbits), D1 => dqout_delay(i), R => gnd, S => gnd);
doen : FD
port map (Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad
generic map (tech => virtex4, level => sstl18_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
------------------------------------------------------------------
-- Spartan 6 DDR2 PHY -------------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM_SP;
use unisim.IDDR2;
use unisim.ODDR2;
use unisim.FD;
use unisim.IODELAY2;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity spartan6_ddr2_phy_wo_pads is
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan6;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3; ncs : integer := 2 );
port ( rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0);
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- row address
ba : in std_logic_vector ( 2 downto 0); -- bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0));
end;
architecture rtl of spartan6_ddr2_phy_wo_pads is
component DCM_SP is
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false );
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK2X180 : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
CLKFX : out std_ulogic;
CLKFX180 : out std_ulogic;
LOCKED : out std_ulogic;
PSDONE : out std_ulogic;
STATUS : out std_logic_vector(7 downto 0);
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
DSSEN : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
RST : in std_ulogic );
end component;
component BUFG
port (O : out std_logic;
I : in std_logic);
end component;
component ODDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT : bit := '0'; -- Sets initial state of the Q0
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q : out std_ulogic; -- 1-bit DDR output data
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D0 : in std_ulogic; -- 1-bit data input (associated with C1)
D1 : in std_ulogic; -- 1-bit data input (associated with C1)
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component FD
generic (INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT_Q0 : bit := '0'; -- Sets initial state of the Q0
INIT_Q1 : bit := '0'; -- Sets initial state of the Q1
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q0 : out std_ulogic; -- 1-bit output captured with C0 clock
Q1 : out std_ulogic; -- 1-bit output captured with C1 clock
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D : in std_ulogic; -- 1-bit DDR data input
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component IODELAY2 is
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75 );
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic );
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal dqsoen_reg : std_logic_vector(dbits/8-1 downto 0);
signal ddr_dq_indel : std_logic_vector(dbits-1 downto 0);
signal ckel : std_logic_vector(ncs-1 downto 0);
signal clk_90ro : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, dllfb : std_ulogic;
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal delay_cal : std_ulogic;
signal dcal_started : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mlock <= '1';
mclk <= clk;
-- mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
-- Extend DCM reset signal.
dll0rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & "0";
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM_SP
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "1X", CLKIN_PERIOD => 1000.0/real(MHz) )
port map (CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation (90 degrees phase-shifted DLL)
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
dllfb <= clk90r;
dll : DCM_SP
generic map ( CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 64 )
port map (CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk0r <= mclk;
clk180r <= not mclk;
clk270r <= not clk90r;
clkout <= mclk;
-- Extend DCM reset signal.
dllrstdel : process (mclk, rst, mlock)
begin
if rst = '0' or mlock = '0' then
dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & "0";
end if;
end process;
-- Delay lock signal.
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16);
vlock := '0';
elsif vlock = '0' then
cnt := cnt -1;
vlock := cnt(15) and not co;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
ddrclocks : for i in 0 to nclk-1 generate
dclk0r : ODDR2
port map ( Q => ddr_clk(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd );
end generate;
-- DDR single-edge control signals
ddrbanks : for i in 0 to ncs-1 generate
ddr_odt(i) <= locked and odt(i);
csn0gen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_csb(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => csn(i), D1 => csn(i), R => gnd, S => gnd );
ckel(i) <= cke(i) and locked;
ckegen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_cke(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => ckel(i), D1 => ckel(i), R => gnd, S => gnd );
end generate;
rasgen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_rasb, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => rasn, D1 => rasn, R => gnd, S => gnd );
casgen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_casb, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => casn, D1 => casn, R => gnd, S => gnd );
wengen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_web, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => wen, D1 => wen, R => gnd, S => gnd );
bagen : for i in 0 to 1+eightbanks generate
ba0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_ba(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => ba(i), D1 => ba(i), R => gnd, S => gnd );
end generate;
addrgen : for i in 0 to abits-1 generate
addr0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_ad(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => addr(i), D1 => addr(i), R => gnd, S => gnd );
end generate;
-- Data mask (DM) generation
dmgen : for i in 0 to dbits/8-1 generate
dmgen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dm(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dm(i+dbits/8), D1 => dm(i), R => gnd, S => gnd );
end generate;
-- Data strobe (DQS) generation
dqsgen : for i in 0 to dbits/8-1 generate
dqsreg : FD
port map ( Q => dqsn(i), C => clk180r, D => oe );
dqsgen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dqs_out(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsn(i), D1 => gnd, R => gnd, S => gnd );
doenreg : FD
port map ( Q => dqsoen_reg(i), C => clk180r, D => dqsoen );
doen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dqs_oen(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsoen_reg(i), D1 => dqsoen_reg(i), R => gnd, S => gnd );
end generate;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
dqdelay : IODELAY2
generic map ( DATA_RATE => "DDR", DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "VARIABLE_FROM_ZERO" )
port map ( BUSY => open, CAL => delay_cal, CE => cal_en(i/8), CLK => clk0r,
DATAOUT => ddr_dq_indel(i), DATAOUT2 => open, DOUT => open,
IDATAIN => ddr_dq_in(i), INC => cal_inc(i/8),
IOCLK0 => clk0r, IOCLK1 => clk180r,
ODATAIN => gnd, RST => cal_rst, T => vcc, TOUT => open );
din : IDDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( D => ddr_dq_indel(i), C0 => clk0r, C1 => clk180r, CE => vcc,
R => gnd, S => gnd, Q0 => dqin(i), Q1 => dqin(i+dbits) );
dout : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dq_out(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dqout(i+dbits), D1 => dqout(i), R => gnd, S => gnd );
doen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dq_oen(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => oen, D1 => oen, R => gnd, S => gnd );
end generate;
-- Generate IODELAY calibration command after core reset.
calcmd : process (mclk, rst)
begin
if rst = '0' then
dcal_started <= '0';
delay_cal <= '0';
elsif rising_edge(mclk) then
if mlock = '1' then
dcal_started <= '1';
delay_cal <= not dcal_started;
end if;
end if;
end process;
end architecture;
| gpl-2.0 | 4699435c498c901909e0503ddd091899 | 0.547069 | 3.327762 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-clock-gate/clkgate.vhd | 1 | 2,475 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity clkgate is
generic (tech : integer := 0; ncpu : integer := 1; dsuen : integer := 1);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
clkahb : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0)
);
end;
architecture rtl of clkgate is
signal npwd, xpwd, ypwd : std_logic_vector(ncpu-1 downto 0);
signal vrst, wrst : std_logic_vector(ncpu-1 downto 0);
signal clken: std_logic_vector(ncpu-1 downto 0);
signal xrst, vcc : std_ulogic;
begin
vcc <= '1';
cand : for i in 0 to ncpu-1 generate
clken(i) <= not npwd(i);
clkand0 : clkand generic map (tech) port map (clkin, clken(i), clkcpu(i));
end generate;
cand0 : clkand generic map (tech) port map (clkin, vcc, clkahb);
vrst <= (others => rst);
r1 : if dsuen = 1 generate
nreg : process(clkin)
begin
if falling_edge(clkin) then
npwd <= pwd and vrst;
end if;
end process;
end generate;
r2 : if dsuen = 0 generate
reg : process(clkin)
begin
if rising_edge(clkin) then
xrst <= rst;
xpwd <= pwd and wrst;
end if;
end process;
wrst <= (others => xrst);
nreg : process(clkin)
begin
if falling_edge(clkin) then
npwd <= xpwd;
end if;
end process;
end generate;
end;
| gpl-2.0 | c0edeafc7ba9791f50c3cc45ea19bc8a | 0.613737 | 3.72741 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/bftLib/round_2.vhdl | 1 | 3,817 | --/////////////////////////////////////////////////////////////////////////
--// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
--//
--// XILINX CONFIDENTIAL PROPERTY
--// This document contains proprietary information which is
--// protected by copyright. All rights are reserved. This notice
--// refers to original work by Xilinx, Inc. which may be derivitive
--// of other work distributed under license of the authors. In the
--// case of derivitive work, nothing in this notice overrides the
--// original author's license agreeement. Where applicable, the
--// original license agreement is included in it's original
--// unmodified form immediately below this header.
--//
--// Xilinx, Inc.
--// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
--// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
--// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
--// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
--// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
--// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
--// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
--// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
--// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
--// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
--// AND FITNESS FOR A PARTICULAR PURPOSE.
--//
--/////////////////////////////////////////////////////////////////////////
-- This is round_2 of the FFT calculation
-- Step size is 1 so X and X +2 are mixed together
-- X0 with X2, X1 with X3 and etc
-- U is a constant with a bogus value - you will want to change it
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
library bftLib;
use bftLib.bftPackage.all;
entity round_2 is
port (
clk : in std_logic;
x : in xType;
xOut : out xType
);
end entity round_2;
architecture aR2 of round_2 is
constant u : uType :=
( X"F0F0",
X"F0F0",
X"F0F0",
X"F0F0",
X"F0F0",
X"F0F0",
X"F0F0",
X"F0F0");
begin
--This really should be rolled into two generate loops
ct0: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(0), xStep=>x(2), u=>u(0), xOut=>xOut(0), xOutStep =>xOut(2));
ct1: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(1), xStep=>x(3), u=>u(1), xOut=>xOut(1), xOutStep =>xOut(3));
ct2: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(4), xStep=>x(6), u=>u(2), xOut=>xOut(4), xOutStep =>xOut(6));
ct3: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(5), xStep=>x(7), u=>u(3), xOut=>xOut(5), xOutStep =>xOut(7));
ct4: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(8), xStep=>x(10), u=>u(4), xOut=>xOut(8), xOutStep =>xOut(10));
ct5: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(9), xStep=>x(11), u=>u(5), xOut=>xOut(9), xOutStep =>xOut(11));
ct6: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(12), xStep=>x(14), u=>u(6), xOut=>xOut(12), xOutStep =>xOut(14));
ct7: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(13), xStep=>x(15), u=>u(7), xOut=>xOut(13), xOutStep =>xOut(15));
end architecture aR2;
| gpl-2.0 | 69125a22c92eeb93eddc2b23bf50527f | 0.62274 | 3.324913 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/CrcPkg.vhd | 1 | 113,437 | -------------------------------------------------------------------------------
-- Title : CRC Package
-------------------------------------------------------------------------------
-- File : CrcPkg.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description: This package defines a few functions that are useful for
-- computing CRC values.
--
-- crc32Parallel<N>Byte defines parallel implementations of the
-- CRC32 algorithm with the "standard" CRC32 polynomial: 0x04C11DB7
-- Byte widths of 1-8 are currently supported.
--
-- To see how the parallel statements are generated, see here:
-- http://www.slac.stanford.edu/~kurtisn/Crc32/Crc32.cpp
-- This is an implementation of the ideas found here:
-- http://outputlogic.com/my-stuff/circuit-cellar-january-2010-crc.pdf
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.UtilityPkg.all;
package CrcPkg is
function crcByteLookup (inByte : slv; constant poly : slv) return slv;
function crcLfsrShift (lfsr : slv; constant poly : slv; input : sl) return slv;
--Specific CRC32 parallel implementations with the standard polynomial: 0x04C11DB7
function crc32Parallel1Byte (crcCur : slv(31 downto 0); data : slv(7 downto 0)) return slv;
function crc32Parallel2Byte (crcCur : slv(31 downto 0); data : slv(15 downto 0)) return slv;
function crc32Parallel3Byte (crcCur : slv(31 downto 0); data : slv(23 downto 0)) return slv;
function crc32Parallel4Byte (crcCur : slv(31 downto 0); data : slv(31 downto 0)) return slv;
function crc32Parallel5Byte (crcCur : slv(31 downto 0); data : slv(39 downto 0)) return slv;
function crc32Parallel6Byte (crcCur : slv(31 downto 0); data : slv(47 downto 0)) return slv;
function crc32Parallel7Byte (crcCur : slv(31 downto 0); data : slv(55 downto 0)) return slv;
function crc32Parallel8Byte (crcCur : slv(31 downto 0); data : slv(63 downto 0)) return slv;
end CrcPkg;
package body CrcPkg is
-------------------------------------------------------------------------------------------------
-- Implements an N tap linear feedback shift operation suitable for CRC implementations
-- This uses a Galois LFSR and inherently assumes the highest polynomial term is 1
-- (e.g., in CRC32 the x^32 term is implicit, so the standard polynomial 0x04C11DB7 is
-- good enough).
--
-- Size of LFSR is variable and determined by length of lfsr parameter, but size of the
-- lfsr and polynomial should match.
--
-- The shift is in the direction of increasing index (left shift for decending, right for ascending)
-- New data bits are shifted in from the lsb-end.
--
-- As written, this can be called N-times to implement CRC calculations, but requires an
-- a message augmented with zeroes to match standard CRC calculations. This makes it a
-- "nondirect" implementation.
-------------------------------------------------------------------------------------------------
function crcLfsrShift (lfsr : slv; constant poly : slv; input : sl) return slv is
variable retVar : slv(lfsr'range) := (others => '0');
begin
if (lfsr'ascending) then
for i in lfsr'range loop
if poly(i) = '1' then
if (i = 0) then
retVar(i) := lfsr(lfsr'right) xor input;
else
retVar(i) := lfsr(lfsr'right) xor lfsr(i-1);
end if;
else
if (i = 0) then
retVar(i) := input;
else
retVar(i) := lfsr(i-1);
end if;
end if;
end loop;
else
for i in lfsr'range loop
if poly(i) = '1' then
if (i = 0) then
retVar(i) := lfsr(lfsr'left) xor input;
else
retVar(i) := lfsr(lfsr'left) xor lfsr(i-1);
end if;
else
if (i = 0) then
retVar(i) := input;
else
retVar(i) := lfsr(i-1);
end if;
end if;
end loop;
end if;
return retVar;
end function;
-------------------------------------------------------------------------------------------------
-- Implements an lookup of CRC values for a given data byte. This is used in many
-- "table driven" implementations of CRC.
-- Supports both ascending or descending bit orders.
-------------------------------------------------------------------------------------------------
function crcByteLookup (inByte : slv; constant poly : slv) return slv is
variable retVar : slv(poly'range) := (others => '0');
begin
assert (inByte'high-inByte'low = 7) report "crcByteLookup() - input must be byte-sized" severity failure;
if (inByte'ascending) then
retVar(retVar'right-7 to retVar'right) := inByte;
retVar(0 to retVar'right-8) := (others => '0');
for b in 7 downto 0 loop
if (retVar(retVar'right) = '1') then
retVar := ('0' & retVar(0 to retVar'right-1)) xor poly;
else
retVar := ('0' & retVar(0 to retVar'right-1));
end if;
end loop;
else
retVar(retVar'left downto retVar'left-7) := inByte;
retVar(retVar'left-8 downto 0) := (others => '0');
for b in 7 downto 0 loop
if (retVar(retVar'left) = '1') then
retVar := (retVar(retVar'left-1 downto 0) & '0') xor poly;
else
retVar := (retVar(retVar'left-1 downto 0) & '0');
end if;
end loop;
end if;
return retVar;
end function;
---------------------------------------------------------
-- Parallel CRC implementations for various byte widths
---------------------------------------------------------
function crc32Parallel1Byte (crcCur : slv(31 downto 0); data : slv(7 downto 0)) return slv is
variable retVar : slv(31 downto 0) := (others => '0');
begin
retVar(0) := data(0) xor data(6) xor crcCur(24) xor crcCur(30);
retVar(1) := data(0) xor data(1) xor data(6) xor data(7) xor crcCur(24) xor crcCur(25) xor crcCur(30) xor crcCur(31);
retVar(2) := data(0) xor data(1) xor data(2) xor data(6) xor data(7) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(30) xor crcCur(31);
retVar(3) := data(1) xor data(2) xor data(3) xor data(7) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(31);
retVar(4) := data(0) xor data(2) xor data(3) xor data(4) xor data(6) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(30);
retVar(5) := data(0) xor data(1) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(6) := data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(7) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(7) := data(0) xor data(2) xor data(3) xor data(5) xor data(7) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(31);
retVar(8) := data(0) xor data(1) xor data(3) xor data(4) xor crcCur(0) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(28);
retVar(9) := data(1) xor data(2) xor data(4) xor data(5) xor crcCur(1) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(29);
retVar(10) := data(0) xor data(2) xor data(3) xor data(5) xor crcCur(2) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(29);
retVar(11) := data(0) xor data(1) xor data(3) xor data(4) xor crcCur(3) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(28);
retVar(12) := data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor crcCur(4) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(29) xor crcCur(30);
retVar(13) := data(1) xor data(2) xor data(3) xor data(5) xor data(6) xor data(7) xor crcCur(5) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(14) := data(2) xor data(3) xor data(4) xor data(6) xor data(7) xor crcCur(6) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(15) := data(3) xor data(4) xor data(5) xor data(7) xor crcCur(7) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(16) := data(0) xor data(4) xor data(5) xor crcCur(8) xor crcCur(24) xor crcCur(28) xor crcCur(29);
retVar(17) := data(1) xor data(5) xor data(6) xor crcCur(9) xor crcCur(25) xor crcCur(29) xor crcCur(30);
retVar(18) := data(2) xor data(6) xor data(7) xor crcCur(10) xor crcCur(26) xor crcCur(30) xor crcCur(31);
retVar(19) := data(3) xor data(7) xor crcCur(11) xor crcCur(27) xor crcCur(31);
retVar(20) := data(4) xor crcCur(12) xor crcCur(28);
retVar(21) := data(5) xor crcCur(13) xor crcCur(29);
retVar(22) := data(0) xor crcCur(14) xor crcCur(24);
retVar(23) := data(0) xor data(1) xor data(6) xor crcCur(15) xor crcCur(24) xor crcCur(25) xor crcCur(30);
retVar(24) := data(1) xor data(2) xor data(7) xor crcCur(16) xor crcCur(25) xor crcCur(26) xor crcCur(31);
retVar(25) := data(2) xor data(3) xor crcCur(17) xor crcCur(26) xor crcCur(27);
retVar(26) := data(0) xor data(3) xor data(4) xor data(6) xor crcCur(18) xor crcCur(24) xor crcCur(27) xor crcCur(28) xor crcCur(30);
retVar(27) := data(1) xor data(4) xor data(5) xor data(7) xor crcCur(19) xor crcCur(25) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(28) := data(2) xor data(5) xor data(6) xor crcCur(20) xor crcCur(26) xor crcCur(29) xor crcCur(30);
retVar(29) := data(3) xor data(6) xor data(7) xor crcCur(21) xor crcCur(27) xor crcCur(30) xor crcCur(31);
retVar(30) := data(4) xor data(7) xor crcCur(22) xor crcCur(28) xor crcCur(31);
retVar(31) := data(5) xor crcCur(23) xor crcCur(29);
return retVar;
end function;
function crc32Parallel2Byte (crcCur : slv(31 downto 0); data : slv(15 downto 0)) return slv is
variable retVar : slv(31 downto 0) := (others => '0');
begin
retVar(0) := data(0) xor data(6) xor data(9) xor data(10) xor data(12) xor crcCur(16) xor crcCur(22) xor crcCur(25) xor crcCur(26) xor crcCur(28);
retVar(1) := data(0) xor data(1) xor data(6) xor data(7) xor data(9) xor data(11) xor data(12) xor data(13) xor crcCur(16) xor crcCur(17) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(29);
retVar(2) := data(0) xor data(1) xor data(2) xor data(6) xor data(7) xor data(8) xor data(9) xor data(13) xor data(14) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(29) xor crcCur(30);
retVar(3) := data(1) xor data(2) xor data(3) xor data(7) xor data(8) xor data(9) xor data(10) xor data(14) xor data(15) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(30) xor crcCur(31);
retVar(4) := data(0) xor data(2) xor data(3) xor data(4) xor data(6) xor data(8) xor data(11) xor data(12) xor data(15) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(24) xor crcCur(27) xor crcCur(28) xor crcCur(31);
retVar(5) := data(0) xor data(1) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(26) xor crcCur(29);
retVar(6) := data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(27) xor crcCur(30);
retVar(7) := data(0) xor data(2) xor data(3) xor data(5) xor data(7) xor data(8) xor data(10) xor data(15) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(31);
retVar(8) := data(0) xor data(1) xor data(3) xor data(4) xor data(8) xor data(10) xor data(11) xor data(12) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(28);
retVar(9) := data(1) xor data(2) xor data(4) xor data(5) xor data(9) xor data(11) xor data(12) xor data(13) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(21) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(29);
retVar(10) := data(0) xor data(2) xor data(3) xor data(5) xor data(9) xor data(13) xor data(14) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(25) xor crcCur(29) xor crcCur(30);
retVar(11) := data(0) xor data(1) xor data(3) xor data(4) xor data(9) xor data(12) xor data(14) xor data(15) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(25) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(12) := data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(9) xor data(12) xor data(13) xor data(15) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(25) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(13) := data(1) xor data(2) xor data(3) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(14) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(26) xor crcCur(29) xor crcCur(30);
retVar(14) := data(2) xor data(3) xor data(4) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(15) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(27) xor crcCur(30) xor crcCur(31);
retVar(15) := data(3) xor data(4) xor data(5) xor data(7) xor data(8) xor data(9) xor data(12) xor data(15) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(28) xor crcCur(31);
retVar(16) := data(0) xor data(4) xor data(5) xor data(8) xor data(12) xor data(13) xor crcCur(0) xor crcCur(16) xor crcCur(20) xor crcCur(21) xor crcCur(24) xor crcCur(28) xor crcCur(29);
retVar(17) := data(1) xor data(5) xor data(6) xor data(9) xor data(13) xor data(14) xor crcCur(1) xor crcCur(17) xor crcCur(21) xor crcCur(22) xor crcCur(25) xor crcCur(29) xor crcCur(30);
retVar(18) := data(2) xor data(6) xor data(7) xor data(10) xor data(14) xor data(15) xor crcCur(2) xor crcCur(18) xor crcCur(22) xor crcCur(23) xor crcCur(26) xor crcCur(30) xor crcCur(31);
retVar(19) := data(3) xor data(7) xor data(8) xor data(11) xor data(15) xor crcCur(3) xor crcCur(19) xor crcCur(23) xor crcCur(24) xor crcCur(27) xor crcCur(31);
retVar(20) := data(4) xor data(8) xor data(9) xor data(12) xor crcCur(4) xor crcCur(20) xor crcCur(24) xor crcCur(25) xor crcCur(28);
retVar(21) := data(5) xor data(9) xor data(10) xor data(13) xor crcCur(5) xor crcCur(21) xor crcCur(25) xor crcCur(26) xor crcCur(29);
retVar(22) := data(0) xor data(9) xor data(11) xor data(12) xor data(14) xor crcCur(6) xor crcCur(16) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(30);
retVar(23) := data(0) xor data(1) xor data(6) xor data(9) xor data(13) xor data(15) xor crcCur(7) xor crcCur(16) xor crcCur(17) xor crcCur(22) xor crcCur(25) xor crcCur(29) xor crcCur(31);
retVar(24) := data(1) xor data(2) xor data(7) xor data(10) xor data(14) xor crcCur(8) xor crcCur(17) xor crcCur(18) xor crcCur(23) xor crcCur(26) xor crcCur(30);
retVar(25) := data(2) xor data(3) xor data(8) xor data(11) xor data(15) xor crcCur(9) xor crcCur(18) xor crcCur(19) xor crcCur(24) xor crcCur(27) xor crcCur(31);
retVar(26) := data(0) xor data(3) xor data(4) xor data(6) xor data(10) xor crcCur(10) xor crcCur(16) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(26);
retVar(27) := data(1) xor data(4) xor data(5) xor data(7) xor data(11) xor crcCur(11) xor crcCur(17) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(27);
retVar(28) := data(2) xor data(5) xor data(6) xor data(8) xor data(12) xor crcCur(12) xor crcCur(18) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(28);
retVar(29) := data(3) xor data(6) xor data(7) xor data(9) xor data(13) xor crcCur(13) xor crcCur(19) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(29);
retVar(30) := data(4) xor data(7) xor data(8) xor data(10) xor data(14) xor crcCur(14) xor crcCur(20) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(30);
retVar(31) := data(5) xor data(8) xor data(9) xor data(11) xor data(15) xor crcCur(15) xor crcCur(21) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(31);
return retVar;
end function;
function crc32Parallel3Byte (crcCur : slv(31 downto 0); data : slv(23 downto 0)) return slv is
variable retVar : slv(31 downto 0) := (others => '0');
begin
retVar(0) := data(0) xor data(6) xor data(9) xor data(10) xor data(12) xor data(16) xor crcCur(8) xor crcCur(14) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(24);
retVar(1) := data(0) xor data(1) xor data(6) xor data(7) xor data(9) xor data(11) xor data(12) xor data(13) xor data(16) xor data(17) xor crcCur(8) xor crcCur(9) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(24) xor crcCur(25);
retVar(2) := data(0) xor data(1) xor data(2) xor data(6) xor data(7) xor data(8) xor data(9) xor data(13) xor data(14) xor data(16) xor data(17) xor data(18) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(25) xor crcCur(26);
retVar(3) := data(1) xor data(2) xor data(3) xor data(7) xor data(8) xor data(9) xor data(10) xor data(14) xor data(15) xor data(17) xor data(18) xor data(19) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(27);
retVar(4) := data(0) xor data(2) xor data(3) xor data(4) xor data(6) xor data(8) xor data(11) xor data(12) xor data(15) xor data(18) xor data(19) xor data(20) xor crcCur(8) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(16) xor crcCur(19) xor crcCur(20) xor crcCur(23) xor crcCur(26) xor crcCur(27) xor crcCur(28);
retVar(5) := data(0) xor data(1) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(19) xor data(20) xor data(21) xor crcCur(8) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(18) xor crcCur(21) xor crcCur(27) xor crcCur(28) xor crcCur(29);
retVar(6) := data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(20) xor data(21) xor data(22) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(19) xor crcCur(22) xor crcCur(28) xor crcCur(29) xor crcCur(30);
retVar(7) := data(0) xor data(2) xor data(3) xor data(5) xor data(7) xor data(8) xor data(10) xor data(15) xor data(16) xor data(21) xor data(22) xor data(23) xor crcCur(8) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(23) xor crcCur(24) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(8) := data(0) xor data(1) xor data(3) xor data(4) xor data(8) xor data(10) xor data(11) xor data(12) xor data(17) xor data(22) xor data(23) xor crcCur(8) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(25) xor crcCur(30) xor crcCur(31);
retVar(9) := data(1) xor data(2) xor data(4) xor data(5) xor data(9) xor data(11) xor data(12) xor data(13) xor data(18) xor data(23) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(13) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(26) xor crcCur(31);
retVar(10) := data(0) xor data(2) xor data(3) xor data(5) xor data(9) xor data(13) xor data(14) xor data(16) xor data(19) xor crcCur(8) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(17) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(27);
retVar(11) := data(0) xor data(1) xor data(3) xor data(4) xor data(9) xor data(12) xor data(14) xor data(15) xor data(16) xor data(17) xor data(20) xor crcCur(8) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(17) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(28);
retVar(12) := data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(9) xor data(12) xor data(13) xor data(15) xor data(17) xor data(18) xor data(21) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(17) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(29);
retVar(13) := data(1) xor data(2) xor data(3) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(14) xor data(16) xor data(18) xor data(19) xor data(22) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(18) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(30);
retVar(14) := data(2) xor data(3) xor data(4) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(15) xor data(17) xor data(19) xor data(20) xor data(23) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(19) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(31);
retVar(15) := data(3) xor data(4) xor data(5) xor data(7) xor data(8) xor data(9) xor data(12) xor data(15) xor data(16) xor data(18) xor data(20) xor data(21) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(20) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(28) xor crcCur(29);
retVar(16) := data(0) xor data(4) xor data(5) xor data(8) xor data(12) xor data(13) xor data(17) xor data(19) xor data(21) xor data(22) xor crcCur(8) xor crcCur(12) xor crcCur(13) xor crcCur(16) xor crcCur(20) xor crcCur(21) xor crcCur(25) xor crcCur(27) xor crcCur(29) xor crcCur(30);
retVar(17) := data(1) xor data(5) xor data(6) xor data(9) xor data(13) xor data(14) xor data(18) xor data(20) xor data(22) xor data(23) xor crcCur(9) xor crcCur(13) xor crcCur(14) xor crcCur(17) xor crcCur(21) xor crcCur(22) xor crcCur(26) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(18) := data(2) xor data(6) xor data(7) xor data(10) xor data(14) xor data(15) xor data(19) xor data(21) xor data(23) xor crcCur(10) xor crcCur(14) xor crcCur(15) xor crcCur(18) xor crcCur(22) xor crcCur(23) xor crcCur(27) xor crcCur(29) xor crcCur(31);
retVar(19) := data(3) xor data(7) xor data(8) xor data(11) xor data(15) xor data(16) xor data(20) xor data(22) xor crcCur(11) xor crcCur(15) xor crcCur(16) xor crcCur(19) xor crcCur(23) xor crcCur(24) xor crcCur(28) xor crcCur(30);
retVar(20) := data(4) xor data(8) xor data(9) xor data(12) xor data(16) xor data(17) xor data(21) xor data(23) xor crcCur(12) xor crcCur(16) xor crcCur(17) xor crcCur(20) xor crcCur(24) xor crcCur(25) xor crcCur(29) xor crcCur(31);
retVar(21) := data(5) xor data(9) xor data(10) xor data(13) xor data(17) xor data(18) xor data(22) xor crcCur(13) xor crcCur(17) xor crcCur(18) xor crcCur(21) xor crcCur(25) xor crcCur(26) xor crcCur(30);
retVar(22) := data(0) xor data(9) xor data(11) xor data(12) xor data(14) xor data(16) xor data(18) xor data(19) xor data(23) xor crcCur(8) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(31);
retVar(23) := data(0) xor data(1) xor data(6) xor data(9) xor data(13) xor data(15) xor data(16) xor data(17) xor data(19) xor data(20) xor crcCur(8) xor crcCur(9) xor crcCur(14) xor crcCur(17) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(28);
retVar(24) := data(1) xor data(2) xor data(7) xor data(10) xor data(14) xor data(16) xor data(17) xor data(18) xor data(20) xor data(21) xor crcCur(0) xor crcCur(9) xor crcCur(10) xor crcCur(15) xor crcCur(18) xor crcCur(22) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(29);
retVar(25) := data(2) xor data(3) xor data(8) xor data(11) xor data(15) xor data(17) xor data(18) xor data(19) xor data(21) xor data(22) xor crcCur(1) xor crcCur(10) xor crcCur(11) xor crcCur(16) xor crcCur(19) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(30);
retVar(26) := data(0) xor data(3) xor data(4) xor data(6) xor data(10) xor data(18) xor data(19) xor data(20) xor data(22) xor data(23) xor crcCur(2) xor crcCur(8) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(18) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(27) := data(1) xor data(4) xor data(5) xor data(7) xor data(11) xor data(19) xor data(20) xor data(21) xor data(23) xor crcCur(3) xor crcCur(9) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(19) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(28) := data(2) xor data(5) xor data(6) xor data(8) xor data(12) xor data(20) xor data(21) xor data(22) xor crcCur(4) xor crcCur(10) xor crcCur(13) xor crcCur(14) xor crcCur(16) xor crcCur(20) xor crcCur(28) xor crcCur(29) xor crcCur(30);
retVar(29) := data(3) xor data(6) xor data(7) xor data(9) xor data(13) xor data(21) xor data(22) xor data(23) xor crcCur(5) xor crcCur(11) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(21) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(30) := data(4) xor data(7) xor data(8) xor data(10) xor data(14) xor data(22) xor data(23) xor crcCur(6) xor crcCur(12) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(22) xor crcCur(30) xor crcCur(31);
retVar(31) := data(5) xor data(8) xor data(9) xor data(11) xor data(15) xor data(23) xor crcCur(7) xor crcCur(13) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(23) xor crcCur(31);
return retVar;
end function;
function crc32Parallel4Byte (crcCur : slv(31 downto 0); data : slv(31 downto 0)) return slv is
variable retVar : slv(31 downto 0) := (others => '0');
begin
retVar(0) := data(0) xor data(6) xor data(9) xor data(10) xor data(12) xor data(16) xor data(24) xor data(25) xor data(26) xor data(28) xor data(29) xor data(30) xor data(31) xor crcCur(0) xor crcCur(6) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(16) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(1) := data(0) xor data(1) xor data(6) xor data(7) xor data(9) xor data(11) xor data(12) xor data(13) xor data(16) xor data(17) xor data(24) xor data(27) xor data(28) xor crcCur(0) xor crcCur(1) xor crcCur(6) xor crcCur(7) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(16) xor crcCur(17) xor crcCur(24) xor crcCur(27) xor crcCur(28);
retVar(2) := data(0) xor data(1) xor data(2) xor data(6) xor data(7) xor data(8) xor data(9) xor data(13) xor data(14) xor data(16) xor data(17) xor data(18) xor data(24) xor data(26) xor data(30) xor data(31) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(6) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(13) xor crcCur(14) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(24) xor crcCur(26) xor crcCur(30) xor crcCur(31);
retVar(3) := data(1) xor data(2) xor data(3) xor data(7) xor data(8) xor data(9) xor data(10) xor data(14) xor data(15) xor data(17) xor data(18) xor data(19) xor data(25) xor data(27) xor data(31) xor crcCur(1) xor crcCur(2) xor crcCur(3) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(25) xor crcCur(27) xor crcCur(31);
retVar(4) := data(0) xor data(2) xor data(3) xor data(4) xor data(6) xor data(8) xor data(11) xor data(12) xor data(15) xor data(18) xor data(19) xor data(20) xor data(24) xor data(25) xor data(29) xor data(30) xor data(31) xor crcCur(0) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(6) xor crcCur(8) xor crcCur(11) xor crcCur(12) xor crcCur(15) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(24) xor crcCur(25) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(5) := data(0) xor data(1) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(19) xor data(20) xor data(21) xor data(24) xor data(28) xor data(29) xor crcCur(0) xor crcCur(1) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(7) xor crcCur(10) xor crcCur(13) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(24) xor crcCur(28) xor crcCur(29);
retVar(6) := data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(20) xor data(21) xor data(22) xor data(25) xor data(29) xor data(30) xor crcCur(1) xor crcCur(2) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(7) xor crcCur(8) xor crcCur(11) xor crcCur(14) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(25) xor crcCur(29) xor crcCur(30);
retVar(7) := data(0) xor data(2) xor data(3) xor data(5) xor data(7) xor data(8) xor data(10) xor data(15) xor data(16) xor data(21) xor data(22) xor data(23) xor data(24) xor data(25) xor data(28) xor data(29) xor crcCur(0) xor crcCur(2) xor crcCur(3) xor crcCur(5) xor crcCur(7) xor crcCur(8) xor crcCur(10) xor crcCur(15) xor crcCur(16) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(28) xor crcCur(29);
retVar(8) := data(0) xor data(1) xor data(3) xor data(4) xor data(8) xor data(10) xor data(11) xor data(12) xor data(17) xor data(22) xor data(23) xor data(28) xor data(31) xor crcCur(0) xor crcCur(1) xor crcCur(3) xor crcCur(4) xor crcCur(8) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(17) xor crcCur(22) xor crcCur(23) xor crcCur(28) xor crcCur(31);
retVar(9) := data(1) xor data(2) xor data(4) xor data(5) xor data(9) xor data(11) xor data(12) xor data(13) xor data(18) xor data(23) xor data(24) xor data(29) xor crcCur(1) xor crcCur(2) xor crcCur(4) xor crcCur(5) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(18) xor crcCur(23) xor crcCur(24) xor crcCur(29);
retVar(10) := data(0) xor data(2) xor data(3) xor data(5) xor data(9) xor data(13) xor data(14) xor data(16) xor data(19) xor data(26) xor data(28) xor data(29) xor data(31) xor crcCur(0) xor crcCur(2) xor crcCur(3) xor crcCur(5) xor crcCur(9) xor crcCur(13) xor crcCur(14) xor crcCur(16) xor crcCur(19) xor crcCur(26) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(11) := data(0) xor data(1) xor data(3) xor data(4) xor data(9) xor data(12) xor data(14) xor data(15) xor data(16) xor data(17) xor data(20) xor data(24) xor data(25) xor data(26) xor data(27) xor data(28) xor data(31) xor crcCur(0) xor crcCur(1) xor crcCur(3) xor crcCur(4) xor crcCur(9) xor crcCur(12) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(20) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(31);
retVar(12) := data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(9) xor data(12) xor data(13) xor data(15) xor data(17) xor data(18) xor data(21) xor data(24) xor data(27) xor data(30) xor data(31) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(9) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(17) xor crcCur(18) xor crcCur(21) xor crcCur(24) xor crcCur(27) xor crcCur(30) xor crcCur(31);
retVar(13) := data(1) xor data(2) xor data(3) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(14) xor data(16) xor data(18) xor data(19) xor data(22) xor data(25) xor data(28) xor data(31) xor crcCur(1) xor crcCur(2) xor crcCur(3) xor crcCur(5) xor crcCur(6) xor crcCur(7) xor crcCur(10) xor crcCur(13) xor crcCur(14) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(22) xor crcCur(25) xor crcCur(28) xor crcCur(31);
retVar(14) := data(2) xor data(3) xor data(4) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(15) xor data(17) xor data(19) xor data(20) xor data(23) xor data(26) xor data(29) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(6) xor crcCur(7) xor crcCur(8) xor crcCur(11) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(23) xor crcCur(26) xor crcCur(29);
retVar(15) := data(3) xor data(4) xor data(5) xor data(7) xor data(8) xor data(9) xor data(12) xor data(15) xor data(16) xor data(18) xor data(20) xor data(21) xor data(24) xor data(27) xor data(30) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(12) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(20) xor crcCur(21) xor crcCur(24) xor crcCur(27) xor crcCur(30);
retVar(16) := data(0) xor data(4) xor data(5) xor data(8) xor data(12) xor data(13) xor data(17) xor data(19) xor data(21) xor data(22) xor data(24) xor data(26) xor data(29) xor data(30) xor crcCur(0) xor crcCur(4) xor crcCur(5) xor crcCur(8) xor crcCur(12) xor crcCur(13) xor crcCur(17) xor crcCur(19) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(26) xor crcCur(29) xor crcCur(30);
retVar(17) := data(1) xor data(5) xor data(6) xor data(9) xor data(13) xor data(14) xor data(18) xor data(20) xor data(22) xor data(23) xor data(25) xor data(27) xor data(30) xor data(31) xor crcCur(1) xor crcCur(5) xor crcCur(6) xor crcCur(9) xor crcCur(13) xor crcCur(14) xor crcCur(18) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(27) xor crcCur(30) xor crcCur(31);
retVar(18) := data(2) xor data(6) xor data(7) xor data(10) xor data(14) xor data(15) xor data(19) xor data(21) xor data(23) xor data(24) xor data(26) xor data(28) xor data(31) xor crcCur(2) xor crcCur(6) xor crcCur(7) xor crcCur(10) xor crcCur(14) xor crcCur(15) xor crcCur(19) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(28) xor crcCur(31);
retVar(19) := data(3) xor data(7) xor data(8) xor data(11) xor data(15) xor data(16) xor data(20) xor data(22) xor data(24) xor data(25) xor data(27) xor data(29) xor crcCur(3) xor crcCur(7) xor crcCur(8) xor crcCur(11) xor crcCur(15) xor crcCur(16) xor crcCur(20) xor crcCur(22) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(29);
retVar(20) := data(4) xor data(8) xor data(9) xor data(12) xor data(16) xor data(17) xor data(21) xor data(23) xor data(25) xor data(26) xor data(28) xor data(30) xor crcCur(4) xor crcCur(8) xor crcCur(9) xor crcCur(12) xor crcCur(16) xor crcCur(17) xor crcCur(21) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(30);
retVar(21) := data(5) xor data(9) xor data(10) xor data(13) xor data(17) xor data(18) xor data(22) xor data(24) xor data(26) xor data(27) xor data(29) xor data(31) xor crcCur(5) xor crcCur(9) xor crcCur(10) xor crcCur(13) xor crcCur(17) xor crcCur(18) xor crcCur(22) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(31);
retVar(22) := data(0) xor data(9) xor data(11) xor data(12) xor data(14) xor data(16) xor data(18) xor data(19) xor data(23) xor data(24) xor data(26) xor data(27) xor data(29) xor data(31) xor crcCur(0) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(31);
retVar(23) := data(0) xor data(1) xor data(6) xor data(9) xor data(13) xor data(15) xor data(16) xor data(17) xor data(19) xor data(20) xor data(26) xor data(27) xor data(29) xor data(31) xor crcCur(0) xor crcCur(1) xor crcCur(6) xor crcCur(9) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(31);
retVar(24) := data(1) xor data(2) xor data(7) xor data(10) xor data(14) xor data(16) xor data(17) xor data(18) xor data(20) xor data(21) xor data(27) xor data(28) xor data(30) xor crcCur(1) xor crcCur(2) xor crcCur(7) xor crcCur(10) xor crcCur(14) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(21) xor crcCur(27) xor crcCur(28) xor crcCur(30);
retVar(25) := data(2) xor data(3) xor data(8) xor data(11) xor data(15) xor data(17) xor data(18) xor data(19) xor data(21) xor data(22) xor data(28) xor data(29) xor data(31) xor crcCur(2) xor crcCur(3) xor crcCur(8) xor crcCur(11) xor crcCur(15) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(22) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(26) := data(0) xor data(3) xor data(4) xor data(6) xor data(10) xor data(18) xor data(19) xor data(20) xor data(22) xor data(23) xor data(24) xor data(25) xor data(26) xor data(28) xor data(31) xor crcCur(0) xor crcCur(3) xor crcCur(4) xor crcCur(6) xor crcCur(10) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(31);
retVar(27) := data(1) xor data(4) xor data(5) xor data(7) xor data(11) xor data(19) xor data(20) xor data(21) xor data(23) xor data(24) xor data(25) xor data(26) xor data(27) xor data(29) xor crcCur(1) xor crcCur(4) xor crcCur(5) xor crcCur(7) xor crcCur(11) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(29);
retVar(28) := data(2) xor data(5) xor data(6) xor data(8) xor data(12) xor data(20) xor data(21) xor data(22) xor data(24) xor data(25) xor data(26) xor data(27) xor data(28) xor data(30) xor crcCur(2) xor crcCur(5) xor crcCur(6) xor crcCur(8) xor crcCur(12) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(30);
retVar(29) := data(3) xor data(6) xor data(7) xor data(9) xor data(13) xor data(21) xor data(22) xor data(23) xor data(25) xor data(26) xor data(27) xor data(28) xor data(29) xor data(31) xor crcCur(3) xor crcCur(6) xor crcCur(7) xor crcCur(9) xor crcCur(13) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(30) := data(4) xor data(7) xor data(8) xor data(10) xor data(14) xor data(22) xor data(23) xor data(24) xor data(26) xor data(27) xor data(28) xor data(29) xor data(30) xor crcCur(4) xor crcCur(7) xor crcCur(8) xor crcCur(10) xor crcCur(14) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(30);
retVar(31) := data(5) xor data(8) xor data(9) xor data(11) xor data(15) xor data(23) xor data(24) xor data(25) xor data(27) xor data(28) xor data(29) xor data(30) xor data(31) xor crcCur(5) xor crcCur(8) xor crcCur(9) xor crcCur(11) xor crcCur(15) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(30) xor crcCur(31);
return retVar;
end function;
function crc32Parallel5Byte (crcCur : slv(31 downto 0); data : slv(39 downto 0)) return slv is
variable retVar : slv(31 downto 0) := (others => '0');
begin
retVar(0) := data(0) xor data(6) xor data(9) xor data(10) xor data(12) xor data(16) xor data(24) xor data(25) xor data(26) xor data(28) xor data(29) xor data(30) xor data(31) xor data(32) xor data(34) xor data(37) xor crcCur(1) xor crcCur(2) xor crcCur(4) xor crcCur(8) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(29);
retVar(1) := data(0) xor data(1) xor data(6) xor data(7) xor data(9) xor data(11) xor data(12) xor data(13) xor data(16) xor data(17) xor data(24) xor data(27) xor data(28) xor data(33) xor data(34) xor data(35) xor data(37) xor data(38) xor crcCur(1) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(8) xor crcCur(9) xor crcCur(16) xor crcCur(19) xor crcCur(20) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(30);
retVar(2) := data(0) xor data(1) xor data(2) xor data(6) xor data(7) xor data(8) xor data(9) xor data(13) xor data(14) xor data(16) xor data(17) xor data(18) xor data(24) xor data(26) xor data(30) xor data(31) xor data(32) xor data(35) xor data(36) xor data(37) xor data(38) xor data(39) xor crcCur(0) xor crcCur(1) xor crcCur(5) xor crcCur(6) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(16) xor crcCur(18) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(3) := data(1) xor data(2) xor data(3) xor data(7) xor data(8) xor data(9) xor data(10) xor data(14) xor data(15) xor data(17) xor data(18) xor data(19) xor data(25) xor data(27) xor data(31) xor data(32) xor data(33) xor data(36) xor data(37) xor data(38) xor data(39) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(6) xor crcCur(7) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(17) xor crcCur(19) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(28) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(4) := data(0) xor data(2) xor data(3) xor data(4) xor data(6) xor data(8) xor data(11) xor data(12) xor data(15) xor data(18) xor data(19) xor data(20) xor data(24) xor data(25) xor data(29) xor data(30) xor data(31) xor data(33) xor data(38) xor data(39) xor crcCur(0) xor crcCur(3) xor crcCur(4) xor crcCur(7) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(16) xor crcCur(17) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(30) xor crcCur(31);
retVar(5) := data(0) xor data(1) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(19) xor data(20) xor data(21) xor data(24) xor data(28) xor data(29) xor data(37) xor data(39) xor crcCur(2) xor crcCur(5) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(16) xor crcCur(20) xor crcCur(21) xor crcCur(29) xor crcCur(31);
retVar(6) := data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(20) xor data(21) xor data(22) xor data(25) xor data(29) xor data(30) xor data(38) xor crcCur(0) xor crcCur(3) xor crcCur(6) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(17) xor crcCur(21) xor crcCur(22) xor crcCur(30);
retVar(7) := data(0) xor data(2) xor data(3) xor data(5) xor data(7) xor data(8) xor data(10) xor data(15) xor data(16) xor data(21) xor data(22) xor data(23) xor data(24) xor data(25) xor data(28) xor data(29) xor data(32) xor data(34) xor data(37) xor data(39) xor crcCur(0) xor crcCur(2) xor crcCur(7) xor crcCur(8) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(20) xor crcCur(21) xor crcCur(24) xor crcCur(26) xor crcCur(29) xor crcCur(31);
retVar(8) := data(0) xor data(1) xor data(3) xor data(4) xor data(8) xor data(10) xor data(11) xor data(12) xor data(17) xor data(22) xor data(23) xor data(28) xor data(31) xor data(32) xor data(33) xor data(34) xor data(35) xor data(37) xor data(38) xor crcCur(0) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(9) xor crcCur(14) xor crcCur(15) xor crcCur(20) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(30);
retVar(9) := data(1) xor data(2) xor data(4) xor data(5) xor data(9) xor data(11) xor data(12) xor data(13) xor data(18) xor data(23) xor data(24) xor data(29) xor data(32) xor data(33) xor data(34) xor data(35) xor data(36) xor data(38) xor data(39) xor crcCur(1) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(10) xor crcCur(15) xor crcCur(16) xor crcCur(21) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(10) := data(0) xor data(2) xor data(3) xor data(5) xor data(9) xor data(13) xor data(14) xor data(16) xor data(19) xor data(26) xor data(28) xor data(29) xor data(31) xor data(32) xor data(33) xor data(35) xor data(36) xor data(39) xor crcCur(1) xor crcCur(5) xor crcCur(6) xor crcCur(8) xor crcCur(11) xor crcCur(18) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(31);
retVar(11) := data(0) xor data(1) xor data(3) xor data(4) xor data(9) xor data(12) xor data(14) xor data(15) xor data(16) xor data(17) xor data(20) xor data(24) xor data(25) xor data(26) xor data(27) xor data(28) xor data(31) xor data(33) xor data(36) xor crcCur(1) xor crcCur(4) xor crcCur(6) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(12) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(23) xor crcCur(25) xor crcCur(28);
retVar(12) := data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(9) xor data(12) xor data(13) xor data(15) xor data(17) xor data(18) xor data(21) xor data(24) xor data(27) xor data(30) xor data(31) xor crcCur(1) xor crcCur(4) xor crcCur(5) xor crcCur(7) xor crcCur(9) xor crcCur(10) xor crcCur(13) xor crcCur(16) xor crcCur(19) xor crcCur(22) xor crcCur(23);
retVar(13) := data(1) xor data(2) xor data(3) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(14) xor data(16) xor data(18) xor data(19) xor data(22) xor data(25) xor data(28) xor data(31) xor data(32) xor crcCur(2) xor crcCur(5) xor crcCur(6) xor crcCur(8) xor crcCur(10) xor crcCur(11) xor crcCur(14) xor crcCur(17) xor crcCur(20) xor crcCur(23) xor crcCur(24);
retVar(14) := data(2) xor data(3) xor data(4) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(15) xor data(17) xor data(19) xor data(20) xor data(23) xor data(26) xor data(29) xor data(32) xor data(33) xor crcCur(0) xor crcCur(3) xor crcCur(6) xor crcCur(7) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(15) xor crcCur(18) xor crcCur(21) xor crcCur(24) xor crcCur(25);
retVar(15) := data(3) xor data(4) xor data(5) xor data(7) xor data(8) xor data(9) xor data(12) xor data(15) xor data(16) xor data(18) xor data(20) xor data(21) xor data(24) xor data(27) xor data(30) xor data(33) xor data(34) xor crcCur(0) xor crcCur(1) xor crcCur(4) xor crcCur(7) xor crcCur(8) xor crcCur(10) xor crcCur(12) xor crcCur(13) xor crcCur(16) xor crcCur(19) xor crcCur(22) xor crcCur(25) xor crcCur(26);
retVar(16) := data(0) xor data(4) xor data(5) xor data(8) xor data(12) xor data(13) xor data(17) xor data(19) xor data(21) xor data(22) xor data(24) xor data(26) xor data(29) xor data(30) xor data(32) xor data(35) xor data(37) xor crcCur(0) xor crcCur(4) xor crcCur(5) xor crcCur(9) xor crcCur(11) xor crcCur(13) xor crcCur(14) xor crcCur(16) xor crcCur(18) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(27) xor crcCur(29);
retVar(17) := data(1) xor data(5) xor data(6) xor data(9) xor data(13) xor data(14) xor data(18) xor data(20) xor data(22) xor data(23) xor data(25) xor data(27) xor data(30) xor data(31) xor data(33) xor data(36) xor data(38) xor crcCur(1) xor crcCur(5) xor crcCur(6) xor crcCur(10) xor crcCur(12) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(19) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(28) xor crcCur(30);
retVar(18) := data(2) xor data(6) xor data(7) xor data(10) xor data(14) xor data(15) xor data(19) xor data(21) xor data(23) xor data(24) xor data(26) xor data(28) xor data(31) xor data(32) xor data(34) xor data(37) xor data(39) xor crcCur(2) xor crcCur(6) xor crcCur(7) xor crcCur(11) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(20) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(29) xor crcCur(31);
retVar(19) := data(3) xor data(7) xor data(8) xor data(11) xor data(15) xor data(16) xor data(20) xor data(22) xor data(24) xor data(25) xor data(27) xor data(29) xor data(32) xor data(33) xor data(35) xor data(38) xor crcCur(0) xor crcCur(3) xor crcCur(7) xor crcCur(8) xor crcCur(12) xor crcCur(14) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(21) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(30);
retVar(20) := data(4) xor data(8) xor data(9) xor data(12) xor data(16) xor data(17) xor data(21) xor data(23) xor data(25) xor data(26) xor data(28) xor data(30) xor data(33) xor data(34) xor data(36) xor data(39) xor crcCur(0) xor crcCur(1) xor crcCur(4) xor crcCur(8) xor crcCur(9) xor crcCur(13) xor crcCur(15) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(22) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(31);
retVar(21) := data(5) xor data(9) xor data(10) xor data(13) xor data(17) xor data(18) xor data(22) xor data(24) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(37) xor crcCur(1) xor crcCur(2) xor crcCur(5) xor crcCur(9) xor crcCur(10) xor crcCur(14) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(23) xor crcCur(26) xor crcCur(27) xor crcCur(29);
retVar(22) := data(0) xor data(9) xor data(11) xor data(12) xor data(14) xor data(16) xor data(18) xor data(19) xor data(23) xor data(24) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(36) xor data(37) xor data(38) xor crcCur(1) xor crcCur(3) xor crcCur(4) xor crcCur(6) xor crcCur(8) xor crcCur(10) xor crcCur(11) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(23) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(30);
retVar(23) := data(0) xor data(1) xor data(6) xor data(9) xor data(13) xor data(15) xor data(16) xor data(17) xor data(19) xor data(20) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(36) xor data(38) xor data(39) xor crcCur(1) xor crcCur(5) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(23) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(24) := data(1) xor data(2) xor data(7) xor data(10) xor data(14) xor data(16) xor data(17) xor data(18) xor data(20) xor data(21) xor data(27) xor data(28) xor data(30) xor data(32) xor data(35) xor data(36) xor data(37) xor data(39) xor crcCur(2) xor crcCur(6) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(13) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(24) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(25) := data(2) xor data(3) xor data(8) xor data(11) xor data(15) xor data(17) xor data(18) xor data(19) xor data(21) xor data(22) xor data(28) xor data(29) xor data(31) xor data(33) xor data(36) xor data(37) xor data(38) xor crcCur(0) xor crcCur(3) xor crcCur(7) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(14) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(25) xor crcCur(28) xor crcCur(29) xor crcCur(30);
retVar(26) := data(0) xor data(3) xor data(4) xor data(6) xor data(10) xor data(18) xor data(19) xor data(20) xor data(22) xor data(23) xor data(24) xor data(25) xor data(26) xor data(28) xor data(31) xor data(38) xor data(39) xor crcCur(2) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(23) xor crcCur(30) xor crcCur(31);
retVar(27) := data(1) xor data(4) xor data(5) xor data(7) xor data(11) xor data(19) xor data(20) xor data(21) xor data(23) xor data(24) xor data(25) xor data(26) xor data(27) xor data(29) xor data(32) xor data(39) xor crcCur(3) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(24) xor crcCur(31);
retVar(28) := data(2) xor data(5) xor data(6) xor data(8) xor data(12) xor data(20) xor data(21) xor data(22) xor data(24) xor data(25) xor data(26) xor data(27) xor data(28) xor data(30) xor data(33) xor crcCur(0) xor crcCur(4) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(25);
retVar(29) := data(3) xor data(6) xor data(7) xor data(9) xor data(13) xor data(21) xor data(22) xor data(23) xor data(25) xor data(26) xor data(27) xor data(28) xor data(29) xor data(31) xor data(34) xor crcCur(1) xor crcCur(5) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(26);
retVar(30) := data(4) xor data(7) xor data(8) xor data(10) xor data(14) xor data(22) xor data(23) xor data(24) xor data(26) xor data(27) xor data(28) xor data(29) xor data(30) xor data(32) xor data(35) xor crcCur(0) xor crcCur(2) xor crcCur(6) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(27);
retVar(31) := data(5) xor data(8) xor data(9) xor data(11) xor data(15) xor data(23) xor data(24) xor data(25) xor data(27) xor data(28) xor data(29) xor data(30) xor data(31) xor data(33) xor data(36) xor crcCur(0) xor crcCur(1) xor crcCur(3) xor crcCur(7) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(28);
return retVar;
end function;
function crc32Parallel6Byte (crcCur : slv(31 downto 0); data : slv(47 downto 0)) return slv is
variable retVar : slv(31 downto 0) := (others => '0');
begin
retVar(0) := data(0) xor data(6) xor data(9) xor data(10) xor data(12) xor data(16) xor data(24) xor data(25) xor data(26) xor data(28) xor data(29) xor data(30) xor data(31) xor data(32) xor data(34) xor data(37) xor data(44) xor data(45) xor data(47) xor crcCur(0) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(21) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(1) := data(0) xor data(1) xor data(6) xor data(7) xor data(9) xor data(11) xor data(12) xor data(13) xor data(16) xor data(17) xor data(24) xor data(27) xor data(28) xor data(33) xor data(34) xor data(35) xor data(37) xor data(38) xor data(44) xor data(46) xor data(47) xor crcCur(0) xor crcCur(1) xor crcCur(8) xor crcCur(11) xor crcCur(12) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(22) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(2) := data(0) xor data(1) xor data(2) xor data(6) xor data(7) xor data(8) xor data(9) xor data(13) xor data(14) xor data(16) xor data(17) xor data(18) xor data(24) xor data(26) xor data(30) xor data(31) xor data(32) xor data(35) xor data(36) xor data(37) xor data(38) xor data(39) xor data(44) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(8) xor crcCur(10) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(28);
retVar(3) := data(1) xor data(2) xor data(3) xor data(7) xor data(8) xor data(9) xor data(10) xor data(14) xor data(15) xor data(17) xor data(18) xor data(19) xor data(25) xor data(27) xor data(31) xor data(32) xor data(33) xor data(36) xor data(37) xor data(38) xor data(39) xor data(40) xor data(45) xor crcCur(1) xor crcCur(2) xor crcCur(3) xor crcCur(9) xor crcCur(11) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(29);
retVar(4) := data(0) xor data(2) xor data(3) xor data(4) xor data(6) xor data(8) xor data(11) xor data(12) xor data(15) xor data(18) xor data(19) xor data(20) xor data(24) xor data(25) xor data(29) xor data(30) xor data(31) xor data(33) xor data(38) xor data(39) xor data(40) xor data(41) xor data(44) xor data(45) xor data(46) xor data(47) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(8) xor crcCur(9) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(28) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(5) := data(0) xor data(1) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(19) xor data(20) xor data(21) xor data(24) xor data(28) xor data(29) xor data(37) xor data(39) xor data(40) xor data(41) xor data(42) xor data(44) xor data(46) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(8) xor crcCur(12) xor crcCur(13) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(30);
retVar(6) := data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(20) xor data(21) xor data(22) xor data(25) xor data(29) xor data(30) xor data(38) xor data(40) xor data(41) xor data(42) xor data(43) xor data(45) xor data(47) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(9) xor crcCur(13) xor crcCur(14) xor crcCur(22) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(31);
retVar(7) := data(0) xor data(2) xor data(3) xor data(5) xor data(7) xor data(8) xor data(10) xor data(15) xor data(16) xor data(21) xor data(22) xor data(23) xor data(24) xor data(25) xor data(28) xor data(29) xor data(32) xor data(34) xor data(37) xor data(39) xor data(41) xor data(42) xor data(43) xor data(45) xor data(46) xor data(47) xor crcCur(0) xor crcCur(5) xor crcCur(6) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(12) xor crcCur(13) xor crcCur(16) xor crcCur(18) xor crcCur(21) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(8) := data(0) xor data(1) xor data(3) xor data(4) xor data(8) xor data(10) xor data(11) xor data(12) xor data(17) xor data(22) xor data(23) xor data(28) xor data(31) xor data(32) xor data(33) xor data(34) xor data(35) xor data(37) xor data(38) xor data(40) xor data(42) xor data(43) xor data(45) xor data(46) xor crcCur(1) xor crcCur(6) xor crcCur(7) xor crcCur(12) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(30);
retVar(9) := data(1) xor data(2) xor data(4) xor data(5) xor data(9) xor data(11) xor data(12) xor data(13) xor data(18) xor data(23) xor data(24) xor data(29) xor data(32) xor data(33) xor data(34) xor data(35) xor data(36) xor data(38) xor data(39) xor data(41) xor data(43) xor data(44) xor data(46) xor data(47) xor crcCur(2) xor crcCur(7) xor crcCur(8) xor crcCur(13) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(10) := data(0) xor data(2) xor data(3) xor data(5) xor data(9) xor data(13) xor data(14) xor data(16) xor data(19) xor data(26) xor data(28) xor data(29) xor data(31) xor data(32) xor data(33) xor data(35) xor data(36) xor data(39) xor data(40) xor data(42) xor crcCur(0) xor crcCur(3) xor crcCur(10) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(23) xor crcCur(24) xor crcCur(26);
retVar(11) := data(0) xor data(1) xor data(3) xor data(4) xor data(9) xor data(12) xor data(14) xor data(15) xor data(16) xor data(17) xor data(20) xor data(24) xor data(25) xor data(26) xor data(27) xor data(28) xor data(31) xor data(33) xor data(36) xor data(40) xor data(41) xor data(43) xor data(44) xor data(45) xor data(47) xor crcCur(0) xor crcCur(1) xor crcCur(4) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(15) xor crcCur(17) xor crcCur(20) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(12) := data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(9) xor data(12) xor data(13) xor data(15) xor data(17) xor data(18) xor data(21) xor data(24) xor data(27) xor data(30) xor data(31) xor data(41) xor data(42) xor data(46) xor data(47) xor crcCur(1) xor crcCur(2) xor crcCur(5) xor crcCur(8) xor crcCur(11) xor crcCur(14) xor crcCur(15) xor crcCur(25) xor crcCur(26) xor crcCur(30) xor crcCur(31);
retVar(13) := data(1) xor data(2) xor data(3) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(14) xor data(16) xor data(18) xor data(19) xor data(22) xor data(25) xor data(28) xor data(31) xor data(32) xor data(42) xor data(43) xor data(47) xor crcCur(0) xor crcCur(2) xor crcCur(3) xor crcCur(6) xor crcCur(9) xor crcCur(12) xor crcCur(15) xor crcCur(16) xor crcCur(26) xor crcCur(27) xor crcCur(31);
retVar(14) := data(2) xor data(3) xor data(4) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(15) xor data(17) xor data(19) xor data(20) xor data(23) xor data(26) xor data(29) xor data(32) xor data(33) xor data(43) xor data(44) xor crcCur(1) xor crcCur(3) xor crcCur(4) xor crcCur(7) xor crcCur(10) xor crcCur(13) xor crcCur(16) xor crcCur(17) xor crcCur(27) xor crcCur(28);
retVar(15) := data(3) xor data(4) xor data(5) xor data(7) xor data(8) xor data(9) xor data(12) xor data(15) xor data(16) xor data(18) xor data(20) xor data(21) xor data(24) xor data(27) xor data(30) xor data(33) xor data(34) xor data(44) xor data(45) xor crcCur(0) xor crcCur(2) xor crcCur(4) xor crcCur(5) xor crcCur(8) xor crcCur(11) xor crcCur(14) xor crcCur(17) xor crcCur(18) xor crcCur(28) xor crcCur(29);
retVar(16) := data(0) xor data(4) xor data(5) xor data(8) xor data(12) xor data(13) xor data(17) xor data(19) xor data(21) xor data(22) xor data(24) xor data(26) xor data(29) xor data(30) xor data(32) xor data(35) xor data(37) xor data(44) xor data(46) xor data(47) xor crcCur(1) xor crcCur(3) xor crcCur(5) xor crcCur(6) xor crcCur(8) xor crcCur(10) xor crcCur(13) xor crcCur(14) xor crcCur(16) xor crcCur(19) xor crcCur(21) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(17) := data(1) xor data(5) xor data(6) xor data(9) xor data(13) xor data(14) xor data(18) xor data(20) xor data(22) xor data(23) xor data(25) xor data(27) xor data(30) xor data(31) xor data(33) xor data(36) xor data(38) xor data(45) xor data(47) xor crcCur(2) xor crcCur(4) xor crcCur(6) xor crcCur(7) xor crcCur(9) xor crcCur(11) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(20) xor crcCur(22) xor crcCur(29) xor crcCur(31);
retVar(18) := data(2) xor data(6) xor data(7) xor data(10) xor data(14) xor data(15) xor data(19) xor data(21) xor data(23) xor data(24) xor data(26) xor data(28) xor data(31) xor data(32) xor data(34) xor data(37) xor data(39) xor data(46) xor crcCur(3) xor crcCur(5) xor crcCur(7) xor crcCur(8) xor crcCur(10) xor crcCur(12) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(21) xor crcCur(23) xor crcCur(30);
retVar(19) := data(3) xor data(7) xor data(8) xor data(11) xor data(15) xor data(16) xor data(20) xor data(22) xor data(24) xor data(25) xor data(27) xor data(29) xor data(32) xor data(33) xor data(35) xor data(38) xor data(40) xor data(47) xor crcCur(0) xor crcCur(4) xor crcCur(6) xor crcCur(8) xor crcCur(9) xor crcCur(11) xor crcCur(13) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(22) xor crcCur(24) xor crcCur(31);
retVar(20) := data(4) xor data(8) xor data(9) xor data(12) xor data(16) xor data(17) xor data(21) xor data(23) xor data(25) xor data(26) xor data(28) xor data(30) xor data(33) xor data(34) xor data(36) xor data(39) xor data(41) xor crcCur(0) xor crcCur(1) xor crcCur(5) xor crcCur(7) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(14) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(23) xor crcCur(25);
retVar(21) := data(5) xor data(9) xor data(10) xor data(13) xor data(17) xor data(18) xor data(22) xor data(24) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(37) xor data(40) xor data(42) xor crcCur(1) xor crcCur(2) xor crcCur(6) xor crcCur(8) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(15) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(24) xor crcCur(26);
retVar(22) := data(0) xor data(9) xor data(11) xor data(12) xor data(14) xor data(16) xor data(18) xor data(19) xor data(23) xor data(24) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(36) xor data(37) xor data(38) xor data(41) xor data(43) xor data(44) xor data(45) xor data(47) xor crcCur(0) xor crcCur(2) xor crcCur(3) xor crcCur(7) xor crcCur(8) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(15) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(23) := data(0) xor data(1) xor data(6) xor data(9) xor data(13) xor data(15) xor data(16) xor data(17) xor data(19) xor data(20) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(36) xor data(38) xor data(39) xor data(42) xor data(46) xor data(47) xor crcCur(0) xor crcCur(1) xor crcCur(3) xor crcCur(4) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(15) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(26) xor crcCur(30) xor crcCur(31);
retVar(24) := data(1) xor data(2) xor data(7) xor data(10) xor data(14) xor data(16) xor data(17) xor data(18) xor data(20) xor data(21) xor data(27) xor data(28) xor data(30) xor data(32) xor data(35) xor data(36) xor data(37) xor data(39) xor data(40) xor data(43) xor data(47) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(4) xor crcCur(5) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(16) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(27) xor crcCur(31);
retVar(25) := data(2) xor data(3) xor data(8) xor data(11) xor data(15) xor data(17) xor data(18) xor data(19) xor data(21) xor data(22) xor data(28) xor data(29) xor data(31) xor data(33) xor data(36) xor data(37) xor data(38) xor data(40) xor data(41) xor data(44) xor crcCur(1) xor crcCur(2) xor crcCur(3) xor crcCur(5) xor crcCur(6) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(17) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(25) xor crcCur(28);
retVar(26) := data(0) xor data(3) xor data(4) xor data(6) xor data(10) xor data(18) xor data(19) xor data(20) xor data(22) xor data(23) xor data(24) xor data(25) xor data(26) xor data(28) xor data(31) xor data(38) xor data(39) xor data(41) xor data(42) xor data(44) xor data(47) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(6) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(15) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(31);
retVar(27) := data(1) xor data(4) xor data(5) xor data(7) xor data(11) xor data(19) xor data(20) xor data(21) xor data(23) xor data(24) xor data(25) xor data(26) xor data(27) xor data(29) xor data(32) xor data(39) xor data(40) xor data(42) xor data(43) xor data(45) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(16) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(29);
retVar(28) := data(2) xor data(5) xor data(6) xor data(8) xor data(12) xor data(20) xor data(21) xor data(22) xor data(24) xor data(25) xor data(26) xor data(27) xor data(28) xor data(30) xor data(33) xor data(40) xor data(41) xor data(43) xor data(44) xor data(46) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(17) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(30);
retVar(29) := data(3) xor data(6) xor data(7) xor data(9) xor data(13) xor data(21) xor data(22) xor data(23) xor data(25) xor data(26) xor data(27) xor data(28) xor data(29) xor data(31) xor data(34) xor data(41) xor data(42) xor data(44) xor data(45) xor data(47) xor crcCur(5) xor crcCur(6) xor crcCur(7) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(18) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(30) := data(4) xor data(7) xor data(8) xor data(10) xor data(14) xor data(22) xor data(23) xor data(24) xor data(26) xor data(27) xor data(28) xor data(29) xor data(30) xor data(32) xor data(35) xor data(42) xor data(43) xor data(45) xor data(46) xor crcCur(6) xor crcCur(7) xor crcCur(8) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(16) xor crcCur(19) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(30);
retVar(31) := data(5) xor data(8) xor data(9) xor data(11) xor data(15) xor data(23) xor data(24) xor data(25) xor data(27) xor data(28) xor data(29) xor data(30) xor data(31) xor data(33) xor data(36) xor data(43) xor data(44) xor data(46) xor data(47) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(20) xor crcCur(27) xor crcCur(28) xor crcCur(30) xor crcCur(31);
return retVar;
end function;
function crc32Parallel7Byte (crcCur : slv(31 downto 0); data : slv(55 downto 0)) return slv is
variable retVar : slv(31 downto 0) := (others => '0');
begin
retVar(0) := data(0) xor data(6) xor data(9) xor data(10) xor data(12) xor data(16) xor data(24) xor data(25) xor data(26) xor data(28) xor data(29) xor data(30) xor data(31) xor data(32) xor data(34) xor data(37) xor data(44) xor data(45) xor data(47) xor data(48) xor data(50) xor data(53) xor data(54) xor data(55) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(7) xor crcCur(8) xor crcCur(10) xor crcCur(13) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(1) := data(0) xor data(1) xor data(6) xor data(7) xor data(9) xor data(11) xor data(12) xor data(13) xor data(16) xor data(17) xor data(24) xor data(27) xor data(28) xor data(33) xor data(34) xor data(35) xor data(37) xor data(38) xor data(44) xor data(46) xor data(47) xor data(49) xor data(50) xor data(51) xor data(53) xor crcCur(0) xor crcCur(3) xor crcCur(4) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(14) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(29);
retVar(2) := data(0) xor data(1) xor data(2) xor data(6) xor data(7) xor data(8) xor data(9) xor data(13) xor data(14) xor data(16) xor data(17) xor data(18) xor data(24) xor data(26) xor data(30) xor data(31) xor data(32) xor data(35) xor data(36) xor data(37) xor data(38) xor data(39) xor data(44) xor data(51) xor data(52) xor data(53) xor data(55) xor crcCur(0) xor crcCur(2) xor crcCur(6) xor crcCur(7) xor crcCur(8) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(20) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(3) := data(1) xor data(2) xor data(3) xor data(7) xor data(8) xor data(9) xor data(10) xor data(14) xor data(15) xor data(17) xor data(18) xor data(19) xor data(25) xor data(27) xor data(31) xor data(32) xor data(33) xor data(36) xor data(37) xor data(38) xor data(39) xor data(40) xor data(45) xor data(52) xor data(53) xor data(54) xor crcCur(1) xor crcCur(3) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(21) xor crcCur(28) xor crcCur(29) xor crcCur(30);
retVar(4) := data(0) xor data(2) xor data(3) xor data(4) xor data(6) xor data(8) xor data(11) xor data(12) xor data(15) xor data(18) xor data(19) xor data(20) xor data(24) xor data(25) xor data(29) xor data(30) xor data(31) xor data(33) xor data(38) xor data(39) xor data(40) xor data(41) xor data(44) xor data(45) xor data(46) xor data(47) xor data(48) xor data(50) xor crcCur(0) xor crcCur(1) xor crcCur(5) xor crcCur(6) xor crcCur(7) xor crcCur(9) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(26);
retVar(5) := data(0) xor data(1) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(19) xor data(20) xor data(21) xor data(24) xor data(28) xor data(29) xor data(37) xor data(39) xor data(40) xor data(41) xor data(42) xor data(44) xor data(46) xor data(49) xor data(50) xor data(51) xor data(53) xor data(54) xor data(55) xor crcCur(0) xor crcCur(4) xor crcCur(5) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(22) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(6) := data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(20) xor data(21) xor data(22) xor data(25) xor data(29) xor data(30) xor data(38) xor data(40) xor data(41) xor data(42) xor data(43) xor data(45) xor data(47) xor data(50) xor data(51) xor data(52) xor data(54) xor data(55) xor crcCur(1) xor crcCur(5) xor crcCur(6) xor crcCur(14) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(23) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(7) := data(0) xor data(2) xor data(3) xor data(5) xor data(7) xor data(8) xor data(10) xor data(15) xor data(16) xor data(21) xor data(22) xor data(23) xor data(24) xor data(25) xor data(28) xor data(29) xor data(32) xor data(34) xor data(37) xor data(39) xor data(41) xor data(42) xor data(43) xor data(45) xor data(46) xor data(47) xor data(50) xor data(51) xor data(52) xor data(54) xor crcCur(0) xor crcCur(1) xor crcCur(4) xor crcCur(5) xor crcCur(8) xor crcCur(10) xor crcCur(13) xor crcCur(15) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(30);
retVar(8) := data(0) xor data(1) xor data(3) xor data(4) xor data(8) xor data(10) xor data(11) xor data(12) xor data(17) xor data(22) xor data(23) xor data(28) xor data(31) xor data(32) xor data(33) xor data(34) xor data(35) xor data(37) xor data(38) xor data(40) xor data(42) xor data(43) xor data(45) xor data(46) xor data(50) xor data(51) xor data(52) xor data(54) xor crcCur(4) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(14) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(22) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(30);
retVar(9) := data(1) xor data(2) xor data(4) xor data(5) xor data(9) xor data(11) xor data(12) xor data(13) xor data(18) xor data(23) xor data(24) xor data(29) xor data(32) xor data(33) xor data(34) xor data(35) xor data(36) xor data(38) xor data(39) xor data(41) xor data(43) xor data(44) xor data(46) xor data(47) xor data(51) xor data(52) xor data(53) xor data(55) xor crcCur(0) xor crcCur(5) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(10) := data(0) xor data(2) xor data(3) xor data(5) xor data(9) xor data(13) xor data(14) xor data(16) xor data(19) xor data(26) xor data(28) xor data(29) xor data(31) xor data(32) xor data(33) xor data(35) xor data(36) xor data(39) xor data(40) xor data(42) xor data(50) xor data(52) xor data(55) xor crcCur(2) xor crcCur(4) xor crcCur(5) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(26) xor crcCur(28) xor crcCur(31);
retVar(11) := data(0) xor data(1) xor data(3) xor data(4) xor data(9) xor data(12) xor data(14) xor data(15) xor data(16) xor data(17) xor data(20) xor data(24) xor data(25) xor data(26) xor data(27) xor data(28) xor data(31) xor data(33) xor data(36) xor data(40) xor data(41) xor data(43) xor data(44) xor data(45) xor data(47) xor data(48) xor data(50) xor data(51) xor data(54) xor data(55) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(7) xor crcCur(9) xor crcCur(12) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(30) xor crcCur(31);
retVar(12) := data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(9) xor data(12) xor data(13) xor data(15) xor data(17) xor data(18) xor data(21) xor data(24) xor data(27) xor data(30) xor data(31) xor data(41) xor data(42) xor data(46) xor data(47) xor data(49) xor data(50) xor data(51) xor data(52) xor data(53) xor data(54) xor crcCur(0) xor crcCur(3) xor crcCur(6) xor crcCur(7) xor crcCur(17) xor crcCur(18) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(30);
retVar(13) := data(1) xor data(2) xor data(3) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(14) xor data(16) xor data(18) xor data(19) xor data(22) xor data(25) xor data(28) xor data(31) xor data(32) xor data(42) xor data(43) xor data(47) xor data(48) xor data(50) xor data(51) xor data(52) xor data(53) xor data(54) xor data(55) xor crcCur(1) xor crcCur(4) xor crcCur(7) xor crcCur(8) xor crcCur(18) xor crcCur(19) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(14) := data(2) xor data(3) xor data(4) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(15) xor data(17) xor data(19) xor data(20) xor data(23) xor data(26) xor data(29) xor data(32) xor data(33) xor data(43) xor data(44) xor data(48) xor data(49) xor data(51) xor data(52) xor data(53) xor data(54) xor data(55) xor crcCur(2) xor crcCur(5) xor crcCur(8) xor crcCur(9) xor crcCur(19) xor crcCur(20) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(15) := data(3) xor data(4) xor data(5) xor data(7) xor data(8) xor data(9) xor data(12) xor data(15) xor data(16) xor data(18) xor data(20) xor data(21) xor data(24) xor data(27) xor data(30) xor data(33) xor data(34) xor data(44) xor data(45) xor data(49) xor data(50) xor data(52) xor data(53) xor data(54) xor data(55) xor crcCur(0) xor crcCur(3) xor crcCur(6) xor crcCur(9) xor crcCur(10) xor crcCur(20) xor crcCur(21) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(16) := data(0) xor data(4) xor data(5) xor data(8) xor data(12) xor data(13) xor data(17) xor data(19) xor data(21) xor data(22) xor data(24) xor data(26) xor data(29) xor data(30) xor data(32) xor data(35) xor data(37) xor data(44) xor data(46) xor data(47) xor data(48) xor data(51) xor crcCur(0) xor crcCur(2) xor crcCur(5) xor crcCur(6) xor crcCur(8) xor crcCur(11) xor crcCur(13) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(27);
retVar(17) := data(1) xor data(5) xor data(6) xor data(9) xor data(13) xor data(14) xor data(18) xor data(20) xor data(22) xor data(23) xor data(25) xor data(27) xor data(30) xor data(31) xor data(33) xor data(36) xor data(38) xor data(45) xor data(47) xor data(48) xor data(49) xor data(52) xor crcCur(1) xor crcCur(3) xor crcCur(6) xor crcCur(7) xor crcCur(9) xor crcCur(12) xor crcCur(14) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(28);
retVar(18) := data(2) xor data(6) xor data(7) xor data(10) xor data(14) xor data(15) xor data(19) xor data(21) xor data(23) xor data(24) xor data(26) xor data(28) xor data(31) xor data(32) xor data(34) xor data(37) xor data(39) xor data(46) xor data(48) xor data(49) xor data(50) xor data(53) xor crcCur(0) xor crcCur(2) xor crcCur(4) xor crcCur(7) xor crcCur(8) xor crcCur(10) xor crcCur(13) xor crcCur(15) xor crcCur(22) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(29);
retVar(19) := data(3) xor data(7) xor data(8) xor data(11) xor data(15) xor data(16) xor data(20) xor data(22) xor data(24) xor data(25) xor data(27) xor data(29) xor data(32) xor data(33) xor data(35) xor data(38) xor data(40) xor data(47) xor data(49) xor data(50) xor data(51) xor data(54) xor crcCur(0) xor crcCur(1) xor crcCur(3) xor crcCur(5) xor crcCur(8) xor crcCur(9) xor crcCur(11) xor crcCur(14) xor crcCur(16) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(30);
retVar(20) := data(4) xor data(8) xor data(9) xor data(12) xor data(16) xor data(17) xor data(21) xor data(23) xor data(25) xor data(26) xor data(28) xor data(30) xor data(33) xor data(34) xor data(36) xor data(39) xor data(41) xor data(48) xor data(50) xor data(51) xor data(52) xor data(55) xor crcCur(1) xor crcCur(2) xor crcCur(4) xor crcCur(6) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(15) xor crcCur(17) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(31);
retVar(21) := data(5) xor data(9) xor data(10) xor data(13) xor data(17) xor data(18) xor data(22) xor data(24) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(37) xor data(40) xor data(42) xor data(49) xor data(51) xor data(52) xor data(53) xor crcCur(0) xor crcCur(2) xor crcCur(3) xor crcCur(5) xor crcCur(7) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(16) xor crcCur(18) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(29);
retVar(22) := data(0) xor data(9) xor data(11) xor data(12) xor data(14) xor data(16) xor data(18) xor data(19) xor data(23) xor data(24) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(36) xor data(37) xor data(38) xor data(41) xor data(43) xor data(44) xor data(45) xor data(47) xor data(48) xor data(52) xor data(55) xor crcCur(0) xor crcCur(2) xor crcCur(3) xor crcCur(5) xor crcCur(7) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(28) xor crcCur(31);
retVar(23) := data(0) xor data(1) xor data(6) xor data(9) xor data(13) xor data(15) xor data(16) xor data(17) xor data(19) xor data(20) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(36) xor data(38) xor data(39) xor data(42) xor data(46) xor data(47) xor data(49) xor data(50) xor data(54) xor data(55) xor crcCur(2) xor crcCur(3) xor crcCur(5) xor crcCur(7) xor crcCur(10) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(15) xor crcCur(18) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(30) xor crcCur(31);
retVar(24) := data(1) xor data(2) xor data(7) xor data(10) xor data(14) xor data(16) xor data(17) xor data(18) xor data(20) xor data(21) xor data(27) xor data(28) xor data(30) xor data(32) xor data(35) xor data(36) xor data(37) xor data(39) xor data(40) xor data(43) xor data(47) xor data(48) xor data(50) xor data(51) xor data(55) xor crcCur(3) xor crcCur(4) xor crcCur(6) xor crcCur(8) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(19) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(31);
retVar(25) := data(2) xor data(3) xor data(8) xor data(11) xor data(15) xor data(17) xor data(18) xor data(19) xor data(21) xor data(22) xor data(28) xor data(29) xor data(31) xor data(33) xor data(36) xor data(37) xor data(38) xor data(40) xor data(41) xor data(44) xor data(48) xor data(49) xor data(51) xor data(52) xor crcCur(4) xor crcCur(5) xor crcCur(7) xor crcCur(9) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(16) xor crcCur(17) xor crcCur(20) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(28);
retVar(26) := data(0) xor data(3) xor data(4) xor data(6) xor data(10) xor data(18) xor data(19) xor data(20) xor data(22) xor data(23) xor data(24) xor data(25) xor data(26) xor data(28) xor data(31) xor data(38) xor data(39) xor data(41) xor data(42) xor data(44) xor data(47) xor data(48) xor data(49) xor data(52) xor data(54) xor data(55) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(4) xor crcCur(7) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(27) := data(1) xor data(4) xor data(5) xor data(7) xor data(11) xor data(19) xor data(20) xor data(21) xor data(23) xor data(24) xor data(25) xor data(26) xor data(27) xor data(29) xor data(32) xor data(39) xor data(40) xor data(42) xor data(43) xor data(45) xor data(48) xor data(49) xor data(50) xor data(53) xor data(55) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(3) xor crcCur(5) xor crcCur(8) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(29) xor crcCur(31);
retVar(28) := data(2) xor data(5) xor data(6) xor data(8) xor data(12) xor data(20) xor data(21) xor data(22) xor data(24) xor data(25) xor data(26) xor data(27) xor data(28) xor data(30) xor data(33) xor data(40) xor data(41) xor data(43) xor data(44) xor data(46) xor data(49) xor data(50) xor data(51) xor data(54) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(6) xor crcCur(9) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(30);
retVar(29) := data(3) xor data(6) xor data(7) xor data(9) xor data(13) xor data(21) xor data(22) xor data(23) xor data(25) xor data(26) xor data(27) xor data(28) xor data(29) xor data(31) xor data(34) xor data(41) xor data(42) xor data(44) xor data(45) xor data(47) xor data(50) xor data(51) xor data(52) xor data(55) xor crcCur(1) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(7) xor crcCur(10) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(31);
retVar(30) := data(4) xor data(7) xor data(8) xor data(10) xor data(14) xor data(22) xor data(23) xor data(24) xor data(26) xor data(27) xor data(28) xor data(29) xor data(30) xor data(32) xor data(35) xor data(42) xor data(43) xor data(45) xor data(46) xor data(48) xor data(51) xor data(52) xor data(53) xor crcCur(0) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(8) xor crcCur(11) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(27) xor crcCur(28) xor crcCur(29);
retVar(31) := data(5) xor data(8) xor data(9) xor data(11) xor data(15) xor data(23) xor data(24) xor data(25) xor data(27) xor data(28) xor data(29) xor data(30) xor data(31) xor data(33) xor data(36) xor data(43) xor data(44) xor data(46) xor data(47) xor data(49) xor data(52) xor data(53) xor data(54) xor crcCur(0) xor crcCur(1) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(7) xor crcCur(9) xor crcCur(12) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(28) xor crcCur(29) xor crcCur(30);
return retVar;
end function;
function crc32Parallel8Byte (crcCur : slv(31 downto 0); data : slv(63 downto 0)) return slv is
variable retVar : slv(31 downto 0) := (others => '0');
begin
retVar(0) := data(0) xor data(6) xor data(9) xor data(10) xor data(12) xor data(16) xor data(24) xor data(25) xor data(26) xor data(28) xor data(29) xor data(30) xor data(31) xor data(32) xor data(34) xor data(37) xor data(44) xor data(45) xor data(47) xor data(48) xor data(50) xor data(53) xor data(54) xor data(55) xor data(58) xor data(60) xor data(61) xor data(63) xor crcCur(0) xor crcCur(2) xor crcCur(5) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(26) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(1) := data(0) xor data(1) xor data(6) xor data(7) xor data(9) xor data(11) xor data(12) xor data(13) xor data(16) xor data(17) xor data(24) xor data(27) xor data(28) xor data(33) xor data(34) xor data(35) xor data(37) xor data(38) xor data(44) xor data(46) xor data(47) xor data(49) xor data(50) xor data(51) xor data(53) xor data(56) xor data(58) xor data(59) xor data(60) xor data(62) xor data(63) xor crcCur(1) xor crcCur(2) xor crcCur(3) xor crcCur(5) xor crcCur(6) xor crcCur(12) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(2) := data(0) xor data(1) xor data(2) xor data(6) xor data(7) xor data(8) xor data(9) xor data(13) xor data(14) xor data(16) xor data(17) xor data(18) xor data(24) xor data(26) xor data(30) xor data(31) xor data(32) xor data(35) xor data(36) xor data(37) xor data(38) xor data(39) xor data(44) xor data(51) xor data(52) xor data(53) xor data(55) xor data(57) xor data(58) xor data(59) xor crcCur(0) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(7) xor crcCur(12) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(27);
retVar(3) := data(1) xor data(2) xor data(3) xor data(7) xor data(8) xor data(9) xor data(10) xor data(14) xor data(15) xor data(17) xor data(18) xor data(19) xor data(25) xor data(27) xor data(31) xor data(32) xor data(33) xor data(36) xor data(37) xor data(38) xor data(39) xor data(40) xor data(45) xor data(52) xor data(53) xor data(54) xor data(56) xor data(58) xor data(59) xor data(60) xor crcCur(0) xor crcCur(1) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(7) xor crcCur(8) xor crcCur(13) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(28);
retVar(4) := data(0) xor data(2) xor data(3) xor data(4) xor data(6) xor data(8) xor data(11) xor data(12) xor data(15) xor data(18) xor data(19) xor data(20) xor data(24) xor data(25) xor data(29) xor data(30) xor data(31) xor data(33) xor data(38) xor data(39) xor data(40) xor data(41) xor data(44) xor data(45) xor data(46) xor data(47) xor data(48) xor data(50) xor data(57) xor data(58) xor data(59) xor data(63) xor crcCur(1) xor crcCur(6) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(12) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(25) xor crcCur(26) xor crcCur(27) xor crcCur(31);
retVar(5) := data(0) xor data(1) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(19) xor data(20) xor data(21) xor data(24) xor data(28) xor data(29) xor data(37) xor data(39) xor data(40) xor data(41) xor data(42) xor data(44) xor data(46) xor data(49) xor data(50) xor data(51) xor data(53) xor data(54) xor data(55) xor data(59) xor data(61) xor data(63) xor crcCur(5) xor crcCur(7) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(14) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(27) xor crcCur(29) xor crcCur(31);
retVar(6) := data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(20) xor data(21) xor data(22) xor data(25) xor data(29) xor data(30) xor data(38) xor data(40) xor data(41) xor data(42) xor data(43) xor data(45) xor data(47) xor data(50) xor data(51) xor data(52) xor data(54) xor data(55) xor data(56) xor data(60) xor data(62) xor crcCur(6) xor crcCur(8) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(15) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(28) xor crcCur(30);
retVar(7) := data(0) xor data(2) xor data(3) xor data(5) xor data(7) xor data(8) xor data(10) xor data(15) xor data(16) xor data(21) xor data(22) xor data(23) xor data(24) xor data(25) xor data(28) xor data(29) xor data(32) xor data(34) xor data(37) xor data(39) xor data(41) xor data(42) xor data(43) xor data(45) xor data(46) xor data(47) xor data(50) xor data(51) xor data(52) xor data(54) xor data(56) xor data(57) xor data(58) xor data(60) xor crcCur(0) xor crcCur(2) xor crcCur(5) xor crcCur(7) xor crcCur(9) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(14) xor crcCur(15) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(28);
retVar(8) := data(0) xor data(1) xor data(3) xor data(4) xor data(8) xor data(10) xor data(11) xor data(12) xor data(17) xor data(22) xor data(23) xor data(28) xor data(31) xor data(32) xor data(33) xor data(34) xor data(35) xor data(37) xor data(38) xor data(40) xor data(42) xor data(43) xor data(45) xor data(46) xor data(50) xor data(51) xor data(52) xor data(54) xor data(57) xor data(59) xor data(60) xor data(63) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(3) xor crcCur(5) xor crcCur(6) xor crcCur(8) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(14) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(22) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(31);
retVar(9) := data(1) xor data(2) xor data(4) xor data(5) xor data(9) xor data(11) xor data(12) xor data(13) xor data(18) xor data(23) xor data(24) xor data(29) xor data(32) xor data(33) xor data(34) xor data(35) xor data(36) xor data(38) xor data(39) xor data(41) xor data(43) xor data(44) xor data(46) xor data(47) xor data(51) xor data(52) xor data(53) xor data(55) xor data(58) xor data(60) xor data(61) xor crcCur(0) xor crcCur(1) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(6) xor crcCur(7) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(15) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(23) xor crcCur(26) xor crcCur(28) xor crcCur(29);
retVar(10) := data(0) xor data(2) xor data(3) xor data(5) xor data(9) xor data(13) xor data(14) xor data(16) xor data(19) xor data(26) xor data(28) xor data(29) xor data(31) xor data(32) xor data(33) xor data(35) xor data(36) xor data(39) xor data(40) xor data(42) xor data(50) xor data(52) xor data(55) xor data(56) xor data(58) xor data(59) xor data(60) xor data(62) xor data(63) xor crcCur(0) xor crcCur(1) xor crcCur(3) xor crcCur(4) xor crcCur(7) xor crcCur(8) xor crcCur(10) xor crcCur(18) xor crcCur(20) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(11) := data(0) xor data(1) xor data(3) xor data(4) xor data(9) xor data(12) xor data(14) xor data(15) xor data(16) xor data(17) xor data(20) xor data(24) xor data(25) xor data(26) xor data(27) xor data(28) xor data(31) xor data(33) xor data(36) xor data(40) xor data(41) xor data(43) xor data(44) xor data(45) xor data(47) xor data(48) xor data(50) xor data(51) xor data(54) xor data(55) xor data(56) xor data(57) xor data(58) xor data(59) xor crcCur(1) xor crcCur(4) xor crcCur(8) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(27);
retVar(12) := data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(6) xor data(9) xor data(12) xor data(13) xor data(15) xor data(17) xor data(18) xor data(21) xor data(24) xor data(27) xor data(30) xor data(31) xor data(41) xor data(42) xor data(46) xor data(47) xor data(49) xor data(50) xor data(51) xor data(52) xor data(53) xor data(54) xor data(56) xor data(57) xor data(59) xor data(61) xor data(63) xor crcCur(9) xor crcCur(10) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(29) xor crcCur(31);
retVar(13) := data(1) xor data(2) xor data(3) xor data(5) xor data(6) xor data(7) xor data(10) xor data(13) xor data(14) xor data(16) xor data(18) xor data(19) xor data(22) xor data(25) xor data(28) xor data(31) xor data(32) xor data(42) xor data(43) xor data(47) xor data(48) xor data(50) xor data(51) xor data(52) xor data(53) xor data(54) xor data(55) xor data(57) xor data(58) xor data(60) xor data(62) xor crcCur(0) xor crcCur(10) xor crcCur(11) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(30);
retVar(14) := data(2) xor data(3) xor data(4) xor data(6) xor data(7) xor data(8) xor data(11) xor data(14) xor data(15) xor data(17) xor data(19) xor data(20) xor data(23) xor data(26) xor data(29) xor data(32) xor data(33) xor data(43) xor data(44) xor data(48) xor data(49) xor data(51) xor data(52) xor data(53) xor data(54) xor data(55) xor data(56) xor data(58) xor data(59) xor data(61) xor data(63) xor crcCur(0) xor crcCur(1) xor crcCur(11) xor crcCur(12) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(31);
retVar(15) := data(3) xor data(4) xor data(5) xor data(7) xor data(8) xor data(9) xor data(12) xor data(15) xor data(16) xor data(18) xor data(20) xor data(21) xor data(24) xor data(27) xor data(30) xor data(33) xor data(34) xor data(44) xor data(45) xor data(49) xor data(50) xor data(52) xor data(53) xor data(54) xor data(55) xor data(56) xor data(57) xor data(59) xor data(60) xor data(62) xor crcCur(1) xor crcCur(2) xor crcCur(12) xor crcCur(13) xor crcCur(17) xor crcCur(18) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(30);
retVar(16) := data(0) xor data(4) xor data(5) xor data(8) xor data(12) xor data(13) xor data(17) xor data(19) xor data(21) xor data(22) xor data(24) xor data(26) xor data(29) xor data(30) xor data(32) xor data(35) xor data(37) xor data(44) xor data(46) xor data(47) xor data(48) xor data(51) xor data(56) xor data(57) xor crcCur(0) xor crcCur(3) xor crcCur(5) xor crcCur(12) xor crcCur(14) xor crcCur(15) xor crcCur(16) xor crcCur(19) xor crcCur(24) xor crcCur(25);
retVar(17) := data(1) xor data(5) xor data(6) xor data(9) xor data(13) xor data(14) xor data(18) xor data(20) xor data(22) xor data(23) xor data(25) xor data(27) xor data(30) xor data(31) xor data(33) xor data(36) xor data(38) xor data(45) xor data(47) xor data(48) xor data(49) xor data(52) xor data(57) xor data(58) xor crcCur(1) xor crcCur(4) xor crcCur(6) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(20) xor crcCur(25) xor crcCur(26);
retVar(18) := data(2) xor data(6) xor data(7) xor data(10) xor data(14) xor data(15) xor data(19) xor data(21) xor data(23) xor data(24) xor data(26) xor data(28) xor data(31) xor data(32) xor data(34) xor data(37) xor data(39) xor data(46) xor data(48) xor data(49) xor data(50) xor data(53) xor data(58) xor data(59) xor crcCur(0) xor crcCur(2) xor crcCur(5) xor crcCur(7) xor crcCur(14) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(21) xor crcCur(26) xor crcCur(27);
retVar(19) := data(3) xor data(7) xor data(8) xor data(11) xor data(15) xor data(16) xor data(20) xor data(22) xor data(24) xor data(25) xor data(27) xor data(29) xor data(32) xor data(33) xor data(35) xor data(38) xor data(40) xor data(47) xor data(49) xor data(50) xor data(51) xor data(54) xor data(59) xor data(60) xor crcCur(0) xor crcCur(1) xor crcCur(3) xor crcCur(6) xor crcCur(8) xor crcCur(15) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(22) xor crcCur(27) xor crcCur(28);
retVar(20) := data(4) xor data(8) xor data(9) xor data(12) xor data(16) xor data(17) xor data(21) xor data(23) xor data(25) xor data(26) xor data(28) xor data(30) xor data(33) xor data(34) xor data(36) xor data(39) xor data(41) xor data(48) xor data(50) xor data(51) xor data(52) xor data(55) xor data(60) xor data(61) xor crcCur(1) xor crcCur(2) xor crcCur(4) xor crcCur(7) xor crcCur(9) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(23) xor crcCur(28) xor crcCur(29);
retVar(21) := data(5) xor data(9) xor data(10) xor data(13) xor data(17) xor data(18) xor data(22) xor data(24) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(37) xor data(40) xor data(42) xor data(49) xor data(51) xor data(52) xor data(53) xor data(56) xor data(61) xor data(62) xor crcCur(2) xor crcCur(3) xor crcCur(5) xor crcCur(8) xor crcCur(10) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(24) xor crcCur(29) xor crcCur(30);
retVar(22) := data(0) xor data(9) xor data(11) xor data(12) xor data(14) xor data(16) xor data(18) xor data(19) xor data(23) xor data(24) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(36) xor data(37) xor data(38) xor data(41) xor data(43) xor data(44) xor data(45) xor data(47) xor data(48) xor data(52) xor data(55) xor data(57) xor data(58) xor data(60) xor data(61) xor data(62) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(16) xor crcCur(20) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(29) xor crcCur(30);
retVar(23) := data(0) xor data(1) xor data(6) xor data(9) xor data(13) xor data(15) xor data(16) xor data(17) xor data(19) xor data(20) xor data(26) xor data(27) xor data(29) xor data(31) xor data(34) xor data(35) xor data(36) xor data(38) xor data(39) xor data(42) xor data(46) xor data(47) xor data(49) xor data(50) xor data(54) xor data(55) xor data(56) xor data(59) xor data(60) xor data(62) xor crcCur(2) xor crcCur(3) xor crcCur(4) xor crcCur(6) xor crcCur(7) xor crcCur(10) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(18) xor crcCur(22) xor crcCur(23) xor crcCur(24) xor crcCur(27) xor crcCur(28) xor crcCur(30);
retVar(24) := data(1) xor data(2) xor data(7) xor data(10) xor data(14) xor data(16) xor data(17) xor data(18) xor data(20) xor data(21) xor data(27) xor data(28) xor data(30) xor data(32) xor data(35) xor data(36) xor data(37) xor data(39) xor data(40) xor data(43) xor data(47) xor data(48) xor data(50) xor data(51) xor data(55) xor data(56) xor data(57) xor data(60) xor data(61) xor data(63) xor crcCur(0) xor crcCur(3) xor crcCur(4) xor crcCur(5) xor crcCur(7) xor crcCur(8) xor crcCur(11) xor crcCur(15) xor crcCur(16) xor crcCur(18) xor crcCur(19) xor crcCur(23) xor crcCur(24) xor crcCur(25) xor crcCur(28) xor crcCur(29) xor crcCur(31);
retVar(25) := data(2) xor data(3) xor data(8) xor data(11) xor data(15) xor data(17) xor data(18) xor data(19) xor data(21) xor data(22) xor data(28) xor data(29) xor data(31) xor data(33) xor data(36) xor data(37) xor data(38) xor data(40) xor data(41) xor data(44) xor data(48) xor data(49) xor data(51) xor data(52) xor data(56) xor data(57) xor data(58) xor data(61) xor data(62) xor crcCur(1) xor crcCur(4) xor crcCur(5) xor crcCur(6) xor crcCur(8) xor crcCur(9) xor crcCur(12) xor crcCur(16) xor crcCur(17) xor crcCur(19) xor crcCur(20) xor crcCur(24) xor crcCur(25) xor crcCur(26) xor crcCur(29) xor crcCur(30);
retVar(26) := data(0) xor data(3) xor data(4) xor data(6) xor data(10) xor data(18) xor data(19) xor data(20) xor data(22) xor data(23) xor data(24) xor data(25) xor data(26) xor data(28) xor data(31) xor data(38) xor data(39) xor data(41) xor data(42) xor data(44) xor data(47) xor data(48) xor data(49) xor data(52) xor data(54) xor data(55) xor data(57) xor data(59) xor data(60) xor data(61) xor data(62) xor crcCur(6) xor crcCur(7) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(15) xor crcCur(16) xor crcCur(17) xor crcCur(20) xor crcCur(22) xor crcCur(23) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(29) xor crcCur(30);
retVar(27) := data(1) xor data(4) xor data(5) xor data(7) xor data(11) xor data(19) xor data(20) xor data(21) xor data(23) xor data(24) xor data(25) xor data(26) xor data(27) xor data(29) xor data(32) xor data(39) xor data(40) xor data(42) xor data(43) xor data(45) xor data(48) xor data(49) xor data(50) xor data(53) xor data(55) xor data(56) xor data(58) xor data(60) xor data(61) xor data(62) xor data(63) xor crcCur(0) xor crcCur(7) xor crcCur(8) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(16) xor crcCur(17) xor crcCur(18) xor crcCur(21) xor crcCur(23) xor crcCur(24) xor crcCur(26) xor crcCur(28) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(28) := data(2) xor data(5) xor data(6) xor data(8) xor data(12) xor data(20) xor data(21) xor data(22) xor data(24) xor data(25) xor data(26) xor data(27) xor data(28) xor data(30) xor data(33) xor data(40) xor data(41) xor data(43) xor data(44) xor data(46) xor data(49) xor data(50) xor data(51) xor data(54) xor data(56) xor data(57) xor data(59) xor data(61) xor data(62) xor data(63) xor crcCur(1) xor crcCur(8) xor crcCur(9) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(17) xor crcCur(18) xor crcCur(19) xor crcCur(22) xor crcCur(24) xor crcCur(25) xor crcCur(27) xor crcCur(29) xor crcCur(30) xor crcCur(31);
retVar(29) := data(3) xor data(6) xor data(7) xor data(9) xor data(13) xor data(21) xor data(22) xor data(23) xor data(25) xor data(26) xor data(27) xor data(28) xor data(29) xor data(31) xor data(34) xor data(41) xor data(42) xor data(44) xor data(45) xor data(47) xor data(50) xor data(51) xor data(52) xor data(55) xor data(57) xor data(58) xor data(60) xor data(62) xor data(63) xor crcCur(2) xor crcCur(9) xor crcCur(10) xor crcCur(12) xor crcCur(13) xor crcCur(15) xor crcCur(18) xor crcCur(19) xor crcCur(20) xor crcCur(23) xor crcCur(25) xor crcCur(26) xor crcCur(28) xor crcCur(30) xor crcCur(31);
retVar(30) := data(4) xor data(7) xor data(8) xor data(10) xor data(14) xor data(22) xor data(23) xor data(24) xor data(26) xor data(27) xor data(28) xor data(29) xor data(30) xor data(32) xor data(35) xor data(42) xor data(43) xor data(45) xor data(46) xor data(48) xor data(51) xor data(52) xor data(53) xor data(56) xor data(58) xor data(59) xor data(61) xor data(63) xor crcCur(0) xor crcCur(3) xor crcCur(10) xor crcCur(11) xor crcCur(13) xor crcCur(14) xor crcCur(16) xor crcCur(19) xor crcCur(20) xor crcCur(21) xor crcCur(24) xor crcCur(26) xor crcCur(27) xor crcCur(29) xor crcCur(31);
retVar(31) := data(5) xor data(8) xor data(9) xor data(11) xor data(15) xor data(23) xor data(24) xor data(25) xor data(27) xor data(28) xor data(29) xor data(30) xor data(31) xor data(33) xor data(36) xor data(43) xor data(44) xor data(46) xor data(47) xor data(49) xor data(52) xor data(53) xor data(54) xor data(57) xor data(59) xor data(60) xor data(62) xor crcCur(1) xor crcCur(4) xor crcCur(11) xor crcCur(12) xor crcCur(14) xor crcCur(15) xor crcCur(17) xor crcCur(20) xor crcCur(21) xor crcCur(22) xor crcCur(25) xor crcCur(27) xor crcCur(28) xor crcCur(30);
return retVar;
end function;
end package body CrcPkg;
----------------------------------
-- 32-bit CRC Implementation --
-- Arbitrary number of bytes in --
----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.CrcPkg.all;
entity Crc32 is
generic (
BYTE_WIDTH_G : integer := 4; -- Maximum byte width (1-8 supported)
CRC_INIT_G : slv(31 downto 0) := x"FFFFFFFF";
GATE_DELAY_G : time := 0.5 ns
);
port (
crcOut : out slv(31 downto 0); -- CRC output
crcClk : in sl; -- system clock
crcDataValid : in sl; -- indicate that new data arrived and CRC can be computed
crcDataWidth : in slv(2 downto 0); -- indicate width in bytes minus 1, 0 - 1 byte, 1 - 2 bytes ... , 7 - 8 bytes
crcIn : in slv((BYTE_WIDTH_G*8-1) downto 0); -- input data for CRC calculation
crcReset : in sl -- initializes CRC logic to CRC_INIT_G
);
end Crc32;
architecture rtl of Crc32 is
type RegType is record
crc : slv(31 downto 0);
data : slv((BYTE_WIDTH_G*8-1) downto 0);
valid : sl;
byteWidth : slv(2 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
crc => CRC_INIT_G,
data => (others => '0'),
valid => '0',
byteWidth => (others => '0')
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
begin
assert (BYTE_WIDTH_G > 0 and BYTE_WIDTH_G <= 8) report "BYTE_WIDTH_G must be in the range [1,8]" severity failure;
comb : process(crcIn,crcDataWidth,crcReset,crcDataValid,r)
variable v : RegType;
variable prevCrc : slv(31 downto 0);
begin
v := r;
v.byteWidth := crcDataWidth;
v.valid := crcDataValid;
-- Transpose the input data
for byte in (BYTE_WIDTH_G-1) downto 0 loop
if (crcDataWidth >= BYTE_WIDTH_G-byte-1) then
for b in 0 to 7 loop
v.data((byte+1)*8-1-b) := crcIn(byte*8+b);
end loop;
else
v.data((byte+1)*8-1 downto byte*8) := (others => '0');
end if;
end loop;
if (crcReset = '0') then
prevCrc := r.crc;
else
prevCrc := CRC_INIT_G;
end if;
-- Calculate CRC in parallel - implementation used depends on the
-- byte width in use.
if (r.valid = '1') then
case(r.byteWidth) is
when "000" =>
v.crc := crc32Parallel1Byte(prevCrc, r.data(BYTE_WIDTH_G*8-1 downto (BYTE_WIDTH_G-1)*8));
when "001" =>
if (BYTE_WIDTH_G >= 2) then
v.crc := crc32Parallel2Byte(prevCrc, r.data(BYTE_WIDTH_G*8-1 downto (BYTE_WIDTH_G-2)*8));
end if;
when "010" =>
if (BYTE_WIDTH_G >= 3) then
v.crc := crc32Parallel3Byte(prevCrc, r.data(BYTE_WIDTH_G*8-1 downto (BYTE_WIDTH_G-3)*8));
end if;
when "011" =>
if (BYTE_WIDTH_G >= 4) then
v.crc := crc32Parallel4Byte(prevCrc, r.data(BYTE_WIDTH_G*8-1 downto (BYTE_WIDTH_G-4)*8));
end if;
when "100" =>
if (BYTE_WIDTH_G >= 5) then
v.crc := crc32Parallel5Byte(prevCrc, r.data(BYTE_WIDTH_G*8-1 downto (BYTE_WIDTH_G-5)*8));
end if;
when "101" =>
if (BYTE_WIDTH_G >= 6) then
v.crc := crc32Parallel6Byte(prevCrc, r.data(BYTE_WIDTH_G*8-1 downto (BYTE_WIDTH_G-6)*8));
end if;
when "110" =>
if (BYTE_WIDTH_G >= 7) then
v.crc := crc32Parallel7Byte(prevCrc, r.data(BYTE_WIDTH_G*8-1 downto (BYTE_WIDTH_G-7)*8));
end if;
when "111" =>
if (BYTE_WIDTH_G = 8) then
v.crc := crc32Parallel8Byte(prevCrc, r.data(BYTE_WIDTH_G*8-1 downto (BYTE_WIDTH_G-8)*8));
end if;
when others => v.crc := (others => '0');
end case;
else
v.crc := prevCrc;
end if;
rin <= v;
-- Transpose each byte in the data out and invert
-- This inversion is equivalent to an XOR of the CRC register with xFFFFFFFF
for byte in 0 to 3 loop
for b in 0 to 7 loop
crcOut(byte*8+b) <= not(r.crc((byte+1)*8-1-b));
end loop;
end loop;
end process;
seq : process (crcClk) is
begin
if (rising_edge(crcClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 800cd0f50095be0db11cda19485ab0f7 | 0.667604 | 2.644157 | false | false | false | false |
takeshineshiro/utrasound_fpga_modelsim | fpga_sim/src/tb_matchfilter.vhd | 1 | 8,688 | -- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- ================================================================================
--
-- Generated by: FIR Compiler 9.0
-- Generated on: 2014-8-27 12:08:48
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity tb_matchfilter is
--START MEGAWIZARD INSERT CONSTANTS
constant FIR_INPUT_FILE_c : string := "matchfilter_input.txt";
constant FIR_OUTPUT_FILE_c : string := "matchfilter_output.txt";
constant NUM_OF_CHANNELS_c : natural := 1;
constant DATA_WIDTH_c : natural := 15;
constant CHANNEL_OUT_WIDTH_c : natural := 0;
constant OUT_WIDTH_c : natural := 30;
constant COEF_SET_ADDRESS_WIDTH_c : natural := 0;
constant COEF_RELOAD_BIT_WIDTH_c : natural := 11;
--END MEGAWIZARD INSERT CONSTANTS
end entity tb_matchfilter;
--library work;
--library auk_dspip_lib;
-------------------------------------------------------------------------------
architecture rtl of tb_matchfilter is
signal ast_sink_data : std_logic_vector (DATA_WIDTH_c-1 downto 0) := (others => '0');
signal ast_source_data : std_logic_vector (OUT_WIDTH_c-1 downto 0);
signal ast_sink_error : std_logic_vector (1 downto 0) := (others => '0');
signal ast_source_error : std_logic_vector (1 downto 0);
signal ast_sink_valid : std_logic := '0';
signal ast_source_valid : std_logic;
signal ast_source_ready : std_logic := '0';
signal clk : std_logic := '0';
signal reset_testbench : std_logic := '0';
signal reset_design : std_logic;
signal eof : std_logic;
signal ast_sink_ready : std_logic;
signal start : std_logic;
signal cnt : natural range 0 to NUM_OF_CHANNELS_c;
constant tclk : time := 10 ns;
constant time_lapse_max : time := 60 us;
signal time_lapse : time;
begin
DUT : entity work.matchfilter
port map (
clk => clk,
reset_n => reset_design,
ast_sink_ready => ast_sink_ready,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_source_valid => ast_source_valid,
ast_source_ready => ast_source_ready,
ast_sink_error => ast_sink_error,
ast_source_error => ast_source_error);
-- for example purposes, the ready signal is always asserted.
ast_source_ready <= '1';
-- no input error
ast_sink_error <= (others => '0');
-- start valid for first cycle to indicate that the file reading should start.
start_p : process (clk, reset_testbench)
begin
if reset_testbench = '0' then
start <= '1';
elsif rising_edge(clk) then
if ast_sink_valid = '1' and ast_sink_ready = '1' then
start <= '0';
end if;
end if;
end process start_p;
-----------------------------------------------------------------------------------------------
-- Read input data from file
-----------------------------------------------------------------------------------------------
source_model : process(clk) is
file in_file : text open read_mode is FIR_INPUT_FILE_c;
variable data_in : integer;
variable indata : line;
begin
if rising_edge(clk) then
if(reset_testbench = '0') then
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
ast_sink_valid <= '0' after tclk/4;
eof <= '0';
else
if not endfile(in_file) and (eof = '0') then
eof <= '0';
if((ast_sink_valid = '1' and ast_sink_ready = '1') or
(start = '1'and not (ast_sink_valid = '1' and ast_sink_ready = '0'))) then
readline(in_file, indata);
read(indata, data_in);
ast_sink_valid <= '1' after tclk/4;
ast_sink_data <= std_logic_vector(to_signed(data_in, DATA_WIDTH_c)) after tclk/4;
else
ast_sink_valid <= '1' after tclk/4;
ast_sink_data <= ast_sink_data after tclk/4;
end if;
else
eof <= '1';
ast_sink_valid <= '0' after tclk/4;
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
end if;
end if;
end if;
end process source_model;
---------------------------------------------------------------------------------------------
-- Write FIR output to file
---------------------------------------------------------------------------------------------
sink_model : process(clk) is
file ro_file : text open write_mode is FIR_OUTPUT_FILE_c;
variable rdata : line;
variable data_r : integer;
begin
if rising_edge(clk) then
if(ast_source_valid = '1' and ast_source_ready = '1') then
data_r := to_integer(signed(ast_source_data));
write(rdata, data_r);
writeline(ro_file, rdata);
end if;
end if;
end process sink_model;
-------------------------------------------------------------------------------
-- clock generator
-------------------------------------------------------------------------------
clkgen : process
begin -- process clkgen
if eof = '1' then
clk <= '0';
assert FALSE
report "NOTE: Stimuli ended" severity note;
wait;
elsif time_lapse >= time_lapse_max then
clk <= '0';
assert FALSE
report "ERROR: Reached time_lapse_max without activity, probably simulation is stuck!" severity Error;
wait;
else
clk <= '0';
wait for tclk/2;
clk <= '1';
wait for tclk/2;
end if;
end process clkgen;
monitor_toggling_activity : process(clk, reset_testbench,
ast_source_data, ast_source_valid)
begin
if reset_testbench = '0' then
time_lapse <= 0 ns;
elsif ast_source_data'event or ast_source_valid'event then
time_lapse <= 0 ns;
elsif rising_edge(clk) then
if time_lapse < time_lapse_max then
time_lapse <= time_lapse + tclk;
end if;
end if;
end process monitor_toggling_activity;
-------------------------------------------------------------------------------
-- reset generator
-------------------------------------------------------------------------------
reset_testbench_gen : process
begin -- process resetgen
reset_testbench <= '1';
wait for tclk/4;
reset_testbench <= '0';
wait for tclk*2;
reset_testbench <= '1';
wait;
end process reset_testbench_gen;
reset_design_gen : process
begin -- process resetgen
reset_design <= '1';
wait for tclk/4;
reset_design <= '0';
wait for tclk*2;
reset_design <= '1';
wait for tclk*80;
reset_design <= '1';
wait for tclk*81*2;
reset_design <= '1';
wait;
end process reset_design_gen;
-------------------------------------------------------------------------------
-- control signals
-------------------------------------------------------------------------------
end architecture rtl;
| apache-2.0 | a552008616e1c3bbd8f4cb6a9aff1da9 | 0.536142 | 4.203193 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/src/frequency_divider_tb.vhd | 3 | 3,247 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity frequencyDividerTb is
end frequencyDividerTb;
architecture rtl of frequencyDividerTb is
----------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------
constant cSystemClock : natural := 50E6;
constant cDivider1 : natural := 4;
constant cDivider2 : natural := 6;
signal clock : std_ulogic := '0';
signal reset : std_ulogic := '0';
signal dutOutput1 : std_ulogic;
signal dutOutput2 : std_ulogic;
begin
clock <= not clock after 1E9 ns / (2 * cSystemClock);
reset <= '1' after 200 ns;
-- DUT
DUT1: entity work.frequencyDivider(rtl)
generic map
(
divideBy => cDivider1
)
port map
(
clock => clock,
nResetAsync => reset,
output => dutOutput1
);
DUT2: entity work.frequencyDivider(rtl)
generic map
(
divideBy => cDivider2
)
port map
(
clock => clock,
nResetAsync => reset,
output => dutOutput2
);
end architecture rtl;
| gpl-2.0 | b7579e80773334a66320151d768d6fa8 | 0.378811 | 5.279675 | false | false | false | false |
32bitmicro/Malinki | fabric/rio/bench/vhdl/TestRioPacketBuffer.vhd | 3 | 97,030 | -------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Contains automatic simulation test code to verify a RioPacketBufferWindow
-- implementation.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestRioPacketBuffer.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for TestRioPacketBuffer.
-------------------------------------------------------------------------------
entity TestRioPacketBuffer is
end entity;
-------------------------------------------------------------------------------
-- Architecture for TestRioPacketBuffer.
-------------------------------------------------------------------------------
architecture TestRioPacketBufferImpl of TestRioPacketBuffer is
component RioPacketBufferWindow is
port(
clk : in std_logic;
areset_n : in std_logic;
inboundWriteFrameFull_o : out std_logic;
inboundWriteFrame_i : in std_logic;
inboundWriteFrameAbort_i : in std_logic;
inboundWriteContent_i : in std_logic;
inboundWriteContentData_i : in std_logic_vector(31 downto 0);
inboundReadFrameEmpty_o : out std_logic;
inboundReadFrame_i : in std_logic;
inboundReadFrameRestart_i : in std_logic;
inboundReadFrameAborted_o : out std_logic;
inboundReadContentEmpty_o : out std_logic;
inboundReadContent_i : in std_logic;
inboundReadContentEnd_o : out std_logic;
inboundReadContentData_o : out std_logic_vector(31 downto 0);
outboundWriteFrameFull_o : out std_logic;
outboundWriteFrame_i : in std_logic;
outboundWriteFrameAbort_i : in std_logic;
outboundWriteContent_i : in std_logic;
outboundWriteContentData_i : in std_logic_vector(31 downto 0);
outboundReadFrameEmpty_o : out std_logic;
outboundReadFrame_i : in std_logic;
outboundReadFrameRestart_i : in std_logic;
outboundReadFrameAborted_o : out std_logic;
outboundReadWindowEmpty_o : out std_logic;
outboundReadWindowReset_i : in std_logic;
outboundReadWindowNext_i : in std_logic;
outboundReadContentEmpty_o : out std_logic;
outboundReadContent_i : in std_logic;
outboundReadContentEnd_o : out std_logic;
outboundReadContentData_o : out std_logic_vector(31 downto 0));
end component;
signal clk : std_logic;
signal areset_n : std_logic;
signal inboundWriteFrameFull : std_logic;
signal inboundWriteFrame : std_logic;
signal inboundWriteFrameAbort : std_logic;
signal inboundWriteContent : std_logic;
signal inboundWriteContentData : std_logic_vector(31 downto 0);
signal inboundReadFrameEmpty : std_logic;
signal inboundReadFrame : std_logic;
signal inboundReadFrameRestart : std_logic;
signal inboundReadFrameAborted : std_logic;
signal inboundReadContentEmpty : std_logic;
signal inboundReadContent : std_logic;
signal inboundReadContentEnd : std_logic;
signal inboundReadContentData : std_logic_vector(31 downto 0);
signal outboundWriteFrameFull : std_logic;
signal outboundWriteFrame : std_logic;
signal outboundWriteFrameAbort : std_logic;
signal outboundWriteContent : std_logic;
signal outboundWriteContentData : std_logic_vector(31 downto 0);
signal outboundReadFrameEmpty : std_logic;
signal outboundReadFrame : std_logic;
signal outboundReadFrameRestart : std_logic;
signal outboundReadFrameAborted : std_logic;
signal outboundReadWindowEmpty : std_logic;
signal outboundReadWindowReset : std_logic;
signal outboundReadWindowNext : std_logic;
signal outboundReadContentEmpty : std_logic;
signal outboundReadContent : std_logic;
signal outboundReadContentEnd : std_logic;
signal outboundReadContentData : std_logic_vector(31 downto 0);
begin
-----------------------------------------------------------------------------
-- Clock generation.
-----------------------------------------------------------------------------
ClockGenerator: process
begin
clk <= '0';
wait for 20 ns;
clk <= '1';
wait for 20 ns;
end process;
-----------------------------------------------------------------------------
-- Test case driver.
-----------------------------------------------------------------------------
TestDriver: process
---------------------------------------------------------------------------
-- Inbound procedures.
---------------------------------------------------------------------------
procedure SetInboundWriteContent(
constant content : in std_logic_vector(31 downto 0)) is
begin
assert inboundWriteFrameFull = '0'
report "Inbound frame cannot be accepted." severity error;
inboundWriteContent <= '1';
inboundWriteContentData <= content;
wait until clk'event and clk = '1';
wait for 1 ns;
inboundWriteContent <= '0';
inboundWriteContentData <= (others=>'U');
end procedure;
procedure SetInboundWriteFrame is
begin
inboundWriteFrame <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
inboundWriteFrame <= '0';
end procedure;
procedure SetInboundWriteFrameAbort is
begin
inboundWriteFrameAbort <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
inboundWriteFrameAbort <= '0';
end procedure;
procedure SetInboundReadContent(
constant content : in std_logic_vector(31 downto 0)) is
begin
inboundReadContent <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
assert (inboundReadContentData = content)
report "Unexpected content read." severity error;
assert (inboundReadContentEnd = '0')
report "Unexpected content end." severity error;
inboundReadContent <= '0';
end procedure;
procedure SetInboundReadContentEnd is
begin
inboundReadContent <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
assert (inboundReadContentEnd = '1')
report "Unexpected content end." severity error;
inboundReadContent <= '0';
end procedure;
procedure SetInboundReadFrame is
begin
assert inboundReadFrameEmpty = '0'
report "No pending inbound frame to be read." severity error;
inboundReadFrame <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
inboundReadFrame <= '0';
end procedure;
procedure SetInboundReadFrameRestart is
begin
inboundReadFrameRestart <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
inboundReadFrameRestart <= '0';
end procedure;
---------------------------------------------------------------------------
-- Outbound procedures.
---------------------------------------------------------------------------
procedure SetOutboundWriteContent(
constant content : in std_logic_vector(31 downto 0)) is
begin
assert outboundWriteFrameFull = '0'
report "Outbound frame cannot be accepted." severity error;
outboundWriteContent <= '1';
outboundWriteContentData <= content;
wait until clk'event and clk = '1';
wait for 1 ns;
outboundWriteContent <= '0';
outboundWriteContentData <= (others=>'U');
end procedure;
procedure SetOutboundWriteFrame is
begin
assert outboundWriteFrameFull = '0'
report "Outbound frame cannot be accepted." severity error;
outboundWriteFrame <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
outboundWriteFrame <= '0';
end procedure;
procedure SetOutboundWriteFrameAbort is
begin
outboundWriteFrameAbort <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
outboundWriteFrameAbort <= '0';
end procedure;
procedure SetOutboundReadContent(
constant content : in std_logic_vector(31 downto 0)) is
begin
outboundReadContent <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
assert (outboundReadContentData = content)
report "Unexpected content read." severity error;
assert (outboundReadContentEnd = '0')
report "Unexpected content end." severity error;
outboundReadContent <= '0';
end procedure;
procedure SetOutboundReadContentEnd is
begin
outboundReadContent <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
assert (outboundReadContentEnd = '1')
report "Unexpected content end." severity error;
outboundReadContent <= '0';
end procedure;
procedure SetOutboundReadFrame is
begin
assert outboundReadFrameEmpty = '0'
report "No pending outbound frame to be read." severity error;
outboundReadFrame <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
outboundReadFrame <= '0';
end procedure;
procedure SetOutboundReadFrameRestart is
begin
outboundReadFrameRestart <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
outboundReadFrameRestart <= '0';
end procedure;
procedure SetOutboundReadWindowReset is
begin
outboundReadWindowReset <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
outboundReadWindowReset <= '0';
end procedure;
procedure SetOutboundReadWindowNext is
begin
assert outboundReadWindowEmpty = '0'
report "No pending outbound window frame to be read." severity error;
outboundReadWindowNext <= '1';
wait until clk'event and clk = '1';
wait for 1 ns;
outboundReadWindowNext <= '0';
end procedure;
begin
inboundWriteFrame <= '0';
inboundWriteFrameAbort <= '0';
inboundWriteContent <= '0';
inboundWriteContentData <= (others=>'U');
inboundReadFrame <= '0';
inboundReadFrameRestart <= '0';
inboundReadContent <= '0';
outboundWriteFrame <= '0';
outboundWriteFrameAbort <= '0';
outboundWriteContent <= '0';
outboundWriteContentData <= (others=>'U');
outboundReadFrame <= '0';
outboundReadFrameRestart <= '0';
outboundReadWindowReset <= '0';
outboundReadWindowNext <= '0';
outboundReadContent <= '0';
areset_n <= '0';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
areset_n <= '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPacketBuffer");
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPacketBuffer-TC1");
PrintS("Description: Test normal operation without using the window. Only");
PrintS(" full frames are tested.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Complete a small frame and read it.");
PrintS("Result: The read frame should be equal to the one written.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC1-Step1");
---------------------------------------------------------------------------
-- REMARK: Update testcases for inbound and outbound...
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
SetInboundWriteContent(x"deadbeef");
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
SetInboundWriteFrame;
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
SetInboundReadContent(x"deadbeef");
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
SetInboundReadContentEnd;
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
SetInboundReadFrame;
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 2:");
PrintS("Action: Write a rio maximum size frame and read it.");
PrintS("Result: The read frame should be equal to the one written.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC1-Step2");
---------------------------------------------------------------------------
for i in 0 to 68 loop
SetInboundWriteContent(std_logic_vector(to_unsigned(i, 32)));
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
end loop;
SetInboundWriteFrame;
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
for i in 0 to 68 loop
SetInboundReadContent(std_logic_vector(to_unsigned(i, 32)));
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
end loop;
SetInboundReadContentEnd;
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
SetInboundReadFrame;
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 3:");
PrintS("Action: Fill the maximum number of small frames without filling ");
PrintS(" the memory.");
PrintS("Result: The frame buffer should accept 63 frames.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC1-Step3");
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Write maximum number of frames.
---------------------------------------------------------------------------
for i in 0 to 2 loop
SetInboundWriteContent(std_logic_vector(to_unsigned(i, 32)));
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
end loop;
for j in 1 to 62 loop
SetInboundWriteFrame;
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
for i in 0 to 2 loop
SetInboundWriteContent(std_logic_vector(to_unsigned(j+i, 32)));
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
end loop;
end loop;
SetInboundWriteFrame;
assert (inboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
---------------------------------------------------------------------------
-- Read the frames written in the above steps.
---------------------------------------------------------------------------
for i in 0 to 2 loop
SetInboundReadContent(std_logic_vector(to_unsigned(i, 32)));
assert (inboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
end loop;
SetInboundReadContentEnd;
assert (inboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
for j in 1 to 62 loop
SetInboundReadFrame;
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
for i in 0 to 2 loop
SetInboundReadContent(std_logic_vector(to_unsigned(j+i, 32)));
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
end loop;
SetInboundReadContentEnd;
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
end loop;
SetInboundReadFrame;
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 4:");
PrintS("Action: Fill the memory to its limit.");
PrintS("Result: The frame buffer should accept 255-69 words.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC1-Step4");
---------------------------------------------------------------------------
for i in 0 to 186 loop
SetInboundWriteContent(std_logic_vector(to_unsigned(i, 32)));
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
end loop;
SetInboundWriteFrame;
assert (inboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
---------------------------------------------------------------------------
for i in 0 to 186 loop
SetInboundReadContent(std_logic_vector(to_unsigned(i, 32)));
assert (inboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
end loop;
SetInboundReadContentEnd;
assert (inboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
SetInboundReadFrame;
assert (inboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (inboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPacketBuffer-TC2");
PrintS("Description: Test operation when using the window.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Add one frame and update the window.");
PrintS("Result: The window empty flag and the read frame empty flag should");
PrintS(" be updated and it should be possible to read the frame again.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC2-Step1");
---------------------------------------------------------------------------
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 2 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
for i in 0 to 2 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowReset;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 2 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 2:");
PrintS("Action: Add two frames and test the window accesses.");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC2-Step2");
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Write two frames.
---------------------------------------------------------------------------
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 2 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(1+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 2 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(2+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Read the frames using the window mechanism.
---------------------------------------------------------------------------
for i in 0 to 2 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(1+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 2 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(2+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Reset the window and read the frames again.
---------------------------------------------------------------------------
SetOutboundReadWindowReset;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 2 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(1+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 2 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(2+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Remove one frame and access the remaining frame.
---------------------------------------------------------------------------
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowReset;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 2 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(2+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Remove the remaining frame.
---------------------------------------------------------------------------
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowReset;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 3:");
PrintS("Action: Add maximum number of frames and test the window accesses.");
PrintS("Result: The buffer should be full and not accept more frames.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC2-Step3");
---------------------------------------------------------------------------
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Write 3*63 frames => maximum number of frames.
---------------------------------------------------------------------------
for i in 0 to 2 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
end loop;
for j in 1 to 62 loop
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 2 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(j+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Read the whole window until it is empty.
---------------------------------------------------------------------------
for j in 0 to 61 loop
for i in 0 to 2 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(j+i, 32)));
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
for i in 0 to 2 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(62+i, 32)));
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Reset the window and remove all frames.
---------------------------------------------------------------------------
SetOutboundReadWindowReset;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for j in 0 to 61 loop
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadWindowReset;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 2 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(62+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 4:");
PrintS("Action: Add maximum number of words and test the window accesses.");
PrintS("Result: The content memory should be full.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC2-Step4");
---------------------------------------------------------------------------
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Write 6*31+69=255 words and 7 frames => full content.
---------------------------------------------------------------------------
for i in 0 to 30 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
end loop;
for j in 1 to 5 loop
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 30 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(j+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 68 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(1024+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Read the whole window until it is empty.
---------------------------------------------------------------------------
for j in 0 to 5 loop
for i in 0 to 30 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(j+i, 32)));
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
for i in 0 to 68 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(1024+i, 32)));
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Reset the window and remove all frames.
---------------------------------------------------------------------------
SetOutboundReadWindowReset;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for j in 0 to 1 loop
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
for j in 2 to 5 loop
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadWindowReset;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 68 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(1024+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 5:");
PrintS("Action: Add maximum number of words -1 and test the window accesses.");
PrintS("Result: The content memory should not accept more frames.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC2-Step5");
---------------------------------------------------------------------------
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Write 11*17=187 (one full frame will not fit).
---------------------------------------------------------------------------
for i in 0 to 16 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
end loop;
for j in 1 to 10 loop
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 16 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(j+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
-- Reset the window and remove all frames.
---------------------------------------------------------------------------
SetOutboundReadWindowReset;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '1')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for j in 1 to 9 loop
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 6:");
PrintS("Action: Add two frames and start reading the second, then remove");
PrintS(" the first.");
PrintS("Result: The readContentEnd flag should not be changed when frames");
PrintS(" are removed.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC2-Step6");
---------------------------------------------------------------------------
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
for i in 0 to 3 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 3 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(i+1, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
for i in 0 to 3 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadContent(std_logic_vector(to_unsigned(1, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadContent(std_logic_vector(to_unsigned(2, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadContent(std_logic_vector(to_unsigned(3, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadContent(std_logic_vector(to_unsigned(4, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPacketBuffer");
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPacketBuffer-TC3");
PrintS("Description: Test operation when restarting and aborting frames.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Write one frame and abort it.");
PrintS("Result: The aborted frame should be discarded.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC3-Step1");
---------------------------------------------------------------------------
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 3 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundWriteFrameAbort;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 2:");
PrintS("Action: Write one full frame then one more that is aborted.");
PrintS("Result: The first frame should remain and the aborted should be ");
PrintS(" discarded.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC3-Step2");
---------------------------------------------------------------------------
for i in 0 to 3 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(1+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 3 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(2+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundWriteFrameAbort;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 3 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(3+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 3 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(1+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 3 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(3+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 3:");
PrintS("Action: Write one full frame then read one that is restarted.");
PrintS("Result: The content of the first frame should be read twice. ");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC3-Step3");
---------------------------------------------------------------------------
for i in 0 to 3 loop
SetOutboundWriteContent(std_logic_vector(to_unsigned(1+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 3 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(1+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrameRestart;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
for i in 0 to 3 loop
SetOutboundReadContent(std_logic_vector(to_unsigned(1+i, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
end loop;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPacketBuffer");
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPacketBuffer-TC4");
PrintS("Description: Test operation when partial frames are read.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Write a one word frame and read it before it is completed.");
PrintS("Result: Empty signals should reflect the status of the frame.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC4-Step1");
---------------------------------------------------------------------------
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
SetOutboundWriteContent(std_logic_vector(to_unsigned(1, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
SetOutboundReadContent(std_logic_vector(to_unsigned(1, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 2:");
PrintS("Action: Write content to a frame and read it, then abort the frame.");
PrintS("Result: The reader should be notified about the aborted frame. The");
PrintS(" notification should be reset when the frame has been ");
PrintS(" restarted.");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC4-Step2");
---------------------------------------------------------------------------
SetOutboundWriteContent(std_logic_vector(to_unsigned(1, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundReadContent(std_logic_vector(to_unsigned(1, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundWriteFrameAbort;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '1')
report "Unexpected readFrameAborted." severity error;
SetOutboundWriteContent(std_logic_vector(to_unsigned(2, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '1')
report "Unexpected readFrameAborted." severity error;
SetOutboundReadFrameRestart;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundReadContent(std_logic_vector(to_unsigned(2, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 3:");
PrintS("Action: Write one complete frame then abort a second.");
PrintS("Result: The reader should not notice the aborted frame. ");
---------------------------------------------------------------------------
PrintR("TG_RioPacketBuffer-TC4-Step3");
---------------------------------------------------------------------------
SetOutboundWriteContent(std_logic_vector(to_unsigned(1, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundReadContent(std_logic_vector(to_unsigned(1, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundWriteFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundWriteContent(std_logic_vector(to_unsigned(2, 32)));
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundWriteFrameAbort;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundReadContentEnd;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '0')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '0')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundReadWindowNext;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '0')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
SetOutboundReadFrame;
assert (outboundWriteFrameFull = '0')
report "Unexpected writeFrameFull." severity error;
assert (outboundReadFrameEmpty = '1')
report "Unexpected readFrameEmpty." severity error;
assert (outboundReadWindowEmpty = '1')
report "Unexpected readWindowEmpty." severity error;
assert (outboundReadContentEmpty = '1')
report "Unexpected readContentEmpty." severity error;
assert (outboundReadFrameAborted = '0')
report "Unexpected readFrameAborted." severity error;
---------------------------------------------------------------------------
-- Test completed.
---------------------------------------------------------------------------
TestEnd;
end process;
-----------------------------------------------------------------------------
-- Instantiate the testobject.
-----------------------------------------------------------------------------
TestPacketBuffer: RioPacketBufferWindow
port map(
clk=>clk, areset_n=>areset_n,
inboundWriteFrameFull_o=>inboundWriteFrameFull,
inboundWriteFrame_i=>inboundWriteFrame,
inboundWriteFrameAbort_i=>inboundWriteFrameAbort,
inboundWriteContent_i=>inboundWriteContent,
inboundWriteContentData_i=>inboundWriteContentData,
inboundReadFrameEmpty_o=>inboundReadFrameEmpty,
inboundReadFrame_i=>inboundReadFrame,
inboundReadFrameRestart_i=>inboundReadFrameRestart,
inboundReadFrameAborted_o=>inboundReadFrameAborted,
inboundReadContentEmpty_o=>inboundReadContentEmpty,
inboundReadContent_i=>inboundReadContent,
inboundReadContentEnd_o=>inboundReadContentEnd,
inboundReadContentData_o=>inboundReadContentData,
outboundWriteFrameFull_o=>outboundWriteFrameFull,
outboundWriteFrame_i=>outboundWriteFrame,
outboundWriteFrameAbort_i=>outboundWriteFrameAbort,
outboundWriteContent_i=>outboundWriteContent,
outboundWriteContentData_i=>outboundWriteContentData,
outboundReadFrameEmpty_o=>outboundReadFrameEmpty,
outboundReadFrame_i=>outboundReadFrame,
outboundReadFrameRestart_i=>outboundReadFrameRestart,
outboundReadFrameAborted_o=>outboundReadFrameAborted,
outboundReadWindowEmpty_o=>outboundReadWindowEmpty,
outboundReadWindowReset_i=>outboundReadWindowReset,
outboundReadWindowNext_i=>outboundReadWindowNext,
outboundReadContentEmpty_o=>outboundReadContentEmpty,
outboundReadContent_i=>outboundReadContent,
outboundReadContentEnd_o=>outboundReadContentEnd,
outboundReadContentData_o=>outboundReadContentData);
end architecture;
| bsd-3-clause | c8337e471b9ef0c262d9e98ff933f753 | 0.61079 | 5.617438 | false | false | false | false |
pkerling/ethernet_mac | mii_gmii.vhd | 1 | 6,129 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Adaption layer for data transfer with MII and GMII
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.framing_common.all;
use work.ethernet_types.all;
entity mii_gmii is
port(
tx_reset_i : in std_ulogic;
tx_clock_i : in std_ulogic;
rx_reset_i : in std_ulogic;
rx_clock_i : in std_ulogic;
-- MII (Media-independent interface)
mii_tx_en_o : out std_ulogic;
mii_txd_o : out std_ulogic_vector(7 downto 0);
mii_rx_er_i : in std_ulogic;
mii_rx_dv_i : in std_ulogic;
mii_rxd_i : in std_ulogic_vector(7 downto 0);
-- RGMII (Reduced pin count gigabit media-independent interface)
-- Leave open if RGMII is not used
rgmii_tx_ctl_o : out std_ulogic;
rgmii_rx_ctl_i : in std_ulogic;
-- Other pins:
-- mii_gtx_clk_o is TXC
-- mii_txd_o[3:0] is TD[3:0]
-- mii_rx_clk_i is RXC
-- mii_rxd_i[3:0] is RD[3:0]
-- Interface control signals
-- Must stay stable after tx_reset_i or rx_reset_i is deasserted
speed_select_i : in t_ethernet_speed;
-- TX/RX control
-- TX signals synchronous to tx_clock
tx_enable_i : in std_ulogic;
-- When asserted together with tx_enable_i, tx_byte_sent_o works as normal, but no data is actually
-- put onto the media-independent interface (for IPG transmission)
tx_gap_i : in std_ulogic;
tx_data_i : in t_ethernet_data;
-- Put next data byte on tx_data_i when asserted
tx_byte_sent_o : out std_ulogic;
-- RX signals synchronous to rx_clock
-- Asserted as long as one continuous frame is being received
rx_frame_o : out std_ulogic;
-- Valid when rx_byte_received_o is asserted
rx_data_o : out t_ethernet_data;
rx_byte_received_o : out std_ulogic;
rx_error_o : out std_ulogic
);
end entity;
architecture rtl of mii_gmii is
-- Transmission
type t_mii_gmii_tx_state is (
TX_INIT,
TX_GMII,
TX_MII_LO_QUAD,
TX_MII_HI_QUAD
);
signal tx_state : t_mii_gmii_tx_state := TX_INIT;
-- Reception
type t_mii_gmii_rx_state is (
RX_INIT,
RX_GMII,
RX_MII_LO_QUAD,
RX_MII_HI_QUAD
);
signal rx_state : t_mii_gmii_rx_state := RX_INIT;
begin
-- TX FSM is split into this synchronous process and the output process for tx_byte_sent_o
-- A strictly one-process FSM is impractical for MII transmission: Wait states would be needed
-- to correctly generate tx_byte_sent_o for GMII.
mii_gmii_tx_sync : process(tx_reset_i, tx_clock_i)
begin
-- Use asynchronous reset, clock_tx is not guaranteed to be running during system initialization
if tx_reset_i = '1' then
tx_state <= TX_INIT;
mii_tx_en_o <= '0';
elsif rising_edge(tx_clock_i) then
mii_tx_en_o <= '0';
mii_txd_o <= (others => '0');
case tx_state is
when TX_INIT =>
case speed_select_i is
when SPEED_1000MBPS =>
tx_state <= TX_GMII;
when others =>
tx_state <= TX_MII_LO_QUAD;
end case;
when TX_GMII =>
-- GMII is very simple: Pass data through when
-- tx_enable_i is asserted
mii_tx_en_o <= tx_enable_i and not tx_gap_i;
mii_txd_o <= tx_data_i;
when TX_MII_LO_QUAD =>
mii_tx_en_o <= tx_enable_i and not tx_gap_i;
mii_txd_o <= "0000" & tx_data_i(3 downto 0);
if tx_enable_i = '1' then
-- Advance to high quad only when data was actually sent
tx_state <= TX_MII_HI_QUAD;
end if;
when TX_MII_HI_QUAD =>
-- tx_enable_i is not considered, a full byte always has to be sent
mii_tx_en_o <= not tx_gap_i;
mii_txd_o <= "0000" & tx_data_i(7 downto 4);
tx_state <= TX_MII_LO_QUAD;
end case;
end if;
end process;
-- TX output process
-- Generates only the tx_byte_sent_o output
mii_gmii_tx_output : process(tx_state, tx_enable_i, speed_select_i)
begin
-- Default output value
tx_byte_sent_o <= '0';
case tx_state is
when TX_INIT =>
-- Look ahead to have tx_byte_sent already set in the TX_GMII clock cycle
if tx_enable_i = '1' and speed_select_i = SPEED_1000MBPS then
tx_byte_sent_o <= '1';
end if;
when TX_GMII =>
-- Look ahead again
if tx_enable_i = '0' then
tx_byte_sent_o <= '0';
else
tx_byte_sent_o <= '1';
end if;
when TX_MII_LO_QUAD =>
null;
when TX_MII_HI_QUAD =>
-- MII is simpler, no look-ahead needed
tx_byte_sent_o <= '1';
end case;
end process;
-- MII/GMII packet reception
mii_gmii_rx_fsm : process(rx_clock_i, rx_reset_i)
begin
if rx_reset_i = '1' then
rx_state <= RX_INIT;
rx_byte_received_o <= '0';
elsif rising_edge(rx_clock_i) then
-- Default output values
rx_frame_o <= '0';
rx_byte_received_o <= '0';
rx_error_o <= '0';
if rx_state /= RX_INIT then
-- Hand indicators through
rx_error_o <= mii_rx_er_i;
rx_frame_o <= mii_rx_dv_i;
end if;
case rx_state is
when RX_INIT =>
-- Wait for a pause in reception
if mii_rx_dv_i = '0' then
case speed_select_i is
when SPEED_1000MBPS =>
rx_state <= RX_GMII;
when others =>
rx_state <= RX_MII_LO_QUAD;
end case;
end if;
when RX_GMII =>
-- Just pass the data through
rx_data_o <= mii_rxd_i;
rx_byte_received_o <= mii_rx_dv_i;
when RX_MII_LO_QUAD =>
-- Wait until start of reception
if mii_rx_dv_i = '1' then
rx_state <= RX_MII_HI_QUAD;
end if;
-- Capture low quad
rx_data_o(3 downto 0) <= mii_rxd_i(3 downto 0);
when RX_MII_HI_QUAD =>
-- Capture high quad and mark it valid
rx_data_o(7 downto 4) <= mii_rxd_i(3 downto 0);
rx_byte_received_o <= '1';
rx_frame_o <= '1';
if mii_rx_dv_i = '0' then
-- Frame ended prematurely on a half-byte
rx_error_o <= '1';
end if;
rx_state <= RX_MII_LO_QUAD;
end case;
end if;
end process;
end architecture;
| bsd-3-clause | aa17c004e7750ba55d2600b1404c085c | 0.604666 | 2.789713 | false | false | false | false |
josemonsalve2/cpeg324_calculator | vivado/hdl/blk_mem_gen_0/blk_mem_gen_v8_3_1/simulation/blk_mem_gen_v8_3.vhd | 13 | 222,214 | -------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
| gpl-3.0 | 88c51b9ddc6722b5209da97e233f58cb | 0.5113 | 3.528102 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/niosii/synthesis/submodules/altera_asmi_parallel.vhd | 1 | 6,641 | -- altera_asmi_parallel.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity altera_asmi_parallel is
port (
clkin : in std_logic := '0'; -- clkin.clk
fast_read : in std_logic := '0'; -- fast_read.fast_read
rden : in std_logic := '0'; -- rden.rden
addr : in std_logic_vector(23 downto 0) := (others => '0'); -- addr.addr
read_sid : in std_logic := '0'; -- read_sid.read_sid
read_status : in std_logic := '0'; -- read_status.read_status
write : in std_logic := '0'; -- write.write
datain : in std_logic_vector(7 downto 0) := (others => '0'); -- datain.datain
shift_bytes : in std_logic := '0'; -- shift_bytes.shift_bytes
sector_protect : in std_logic := '0'; -- sector_protect.sector_protect
sector_erase : in std_logic := '0'; -- sector_erase.sector_erase
bulk_erase : in std_logic := '0'; -- bulk_erase.bulk_erase
wren : in std_logic := '0'; -- wren.wren
read_rdid : in std_logic := '0'; -- read_rdid.read_rdid
reset : in std_logic := '0'; -- reset.reset
read_dummyclk : in std_logic := '0'; -- read_dummyclk.read_dummyclk
dataout : out std_logic_vector(7 downto 0); -- dataout.dataout
busy : out std_logic; -- busy.busy
data_valid : out std_logic; -- data_valid.data_valid
epcs_id : out std_logic_vector(7 downto 0); -- epcs_id.epcs_id
status_out : out std_logic_vector(7 downto 0); -- status_out.status_out
illegal_write : out std_logic; -- illegal_write.illegal_write
illegal_erase : out std_logic; -- illegal_erase.illegal_erase
rdid_out : out std_logic_vector(7 downto 0) -- rdid_out.rdid_out
);
end entity altera_asmi_parallel;
architecture rtl of altera_asmi_parallel is
component niosii_epcq_controller_0_altera_asmi_parallel_altera_asmi_parallel is
port (
clkin : in std_logic := 'X'; -- clk
fast_read : in std_logic := 'X'; -- fast_read
rden : in std_logic := 'X'; -- rden
addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- addr
read_sid : in std_logic := 'X'; -- read_sid
read_status : in std_logic := 'X'; -- read_status
write : in std_logic := 'X'; -- write
datain : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain
shift_bytes : in std_logic := 'X'; -- shift_bytes
sector_protect : in std_logic := 'X'; -- sector_protect
sector_erase : in std_logic := 'X'; -- sector_erase
bulk_erase : in std_logic := 'X'; -- bulk_erase
wren : in std_logic := 'X'; -- wren
read_rdid : in std_logic := 'X'; -- read_rdid
reset : in std_logic := 'X'; -- reset
read_dummyclk : in std_logic := 'X'; -- read_dummyclk
dataout : out std_logic_vector(7 downto 0); -- dataout
busy : out std_logic; -- busy
data_valid : out std_logic; -- data_valid
epcs_id : out std_logic_vector(7 downto 0); -- epcs_id
status_out : out std_logic_vector(7 downto 0); -- status_out
illegal_write : out std_logic; -- illegal_write
illegal_erase : out std_logic; -- illegal_erase
rdid_out : out std_logic_vector(7 downto 0) -- rdid_out
);
end component niosii_epcq_controller_0_altera_asmi_parallel_altera_asmi_parallel;
begin
altera_asmi_parallel : component niosii_epcq_controller_0_altera_asmi_parallel_altera_asmi_parallel
port map (
clkin => clkin, -- clkin.clk
fast_read => fast_read, -- fast_read.fast_read
rden => rden, -- rden.rden
addr => addr, -- addr.addr
read_sid => read_sid, -- read_sid.read_sid
read_status => read_status, -- read_status.read_status
write => write, -- write.write
datain => datain, -- datain.datain
shift_bytes => shift_bytes, -- shift_bytes.shift_bytes
sector_protect => sector_protect, -- sector_protect.sector_protect
sector_erase => sector_erase, -- sector_erase.sector_erase
bulk_erase => bulk_erase, -- bulk_erase.bulk_erase
wren => wren, -- wren.wren
read_rdid => read_rdid, -- read_rdid.read_rdid
reset => reset, -- reset.reset
read_dummyclk => read_dummyclk, -- read_dummyclk.read_dummyclk
dataout => dataout, -- dataout.dataout
busy => busy, -- busy.busy
data_valid => data_valid, -- data_valid.data_valid
epcs_id => epcs_id, -- epcs_id.epcs_id
status_out => status_out, -- status_out.status_out
illegal_write => illegal_write, -- illegal_write.illegal_write
illegal_erase => illegal_erase, -- illegal_erase.illegal_erase
rdid_out => rdid_out -- rdid_out.rdid_out
);
end architecture rtl; -- of altera_asmi_parallel
| mit | 43a224ec55d9cf2984a19e80f5987cac | 0.432616 | 3.867793 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_timer/niosii/synthesis/niosii_rst_controller.vhd | 6 | 9,023 | -- niosii_rst_controller.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity niosii_rst_controller;
architecture rtl of niosii_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of niosii_rst_controller
| mit | 91414d0e7cd12e086e3362426b217f8f | 0.547379 | 2.725982 | false | false | false | false |
jotego/jt12 | doc/other/common.vhd | 2 | 1,930 | --------======== common.vhd ========--------
-- Common entities for use with YM2203/YM2612 implementation
-- Copyright (C) 2015 Sauraen
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- circular_buffer
-- A simple circular buffer, used for most of the YM2612's registers.
library ieee;
use ieee.std_logic_1164.all;
entity circular_buffer is
generic (
DATA_WIDTH: positive := 8; --arbitrary default value
BUFFER_DEPTH: positive := 3; --arbitrary default value
CLEAR_ON_RESET: boolean := false
);
port (
clk, rst_bar: in std_logic;
din: in std_logic_vector(DATA_WIDTH-1 downto 0);
dout: out std_logic_vector(DATA_WIDTH-1 downto 0);
load: in std_logic
);
end entity;
architecture arch of circular_buffer is
type memtype is array(BUFFER_DEPTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal mem : memtype;
begin
process(clk, rst_bar) is begin
if rst_bar = '0' and CLEAR_ON_RESET then
for i in BUFFER_DEPTH-1 downto 0 loop
mem(i) <= (others => '0');
end loop;
elsif rising_edge(clk) then
if load = '1' then
mem(BUFFER_DEPTH-1) <= din;
else
mem(BUFFER_DEPTH-1) <= mem(0);
end if;
for i in buffer_depth-2 downto 0 loop
mem(i) <= mem(i+1);
end loop;
dout <= mem(0);
end if;
end process;
end architecture; | gpl-3.0 | 0f19da046f582439e399a261c8aab93e | 0.675648 | 3.40388 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/src/altremote_pulsed_tb.vhd | 3 | 3,046 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity altremotePulsedTb is
end altremotePulsedTb;
architecture rtl of altremotePulsedTb is
----------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------
constant cSystemClock : natural := 50E6;
constant cDivider1 : natural := 4;
constant cDivider2 : natural := 6;
signal clock : std_ulogic := '0';
signal reset : std_ulogic := '0';
signal reconf : std_ulogic := '0';
begin
clock <= not clock after 1E9 ns / (2 * cSystemClock);
reset <= '1' after 200 ns;
reconf <= '1' after 20 ns,
'0' after 1 us;
-- DUT
DUT: entity work.altremotePulsed(rtl)
port map
(
clock => clock,
nResetAsync => reset,
reconf => reconf
);
end architecture rtl;
| gpl-2.0 | f62baed3f5a42be3a93e7ab859094191 | 0.35522 | 5.651206 | false | false | false | false |
FrankBuss/YaGraphCon | spartan3e/src/GraphicsAccelerator.vhd | 1 | 5,929 | -- Copyright (c) 2009 Frank Buss ([email protected])
-- See license.txt for license
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
use work.YaGraphConPackage.all;
entity GraphicsAccelerator is
generic(
ADDRESS_WIDTH: natural;
BIT_DEPTH: natural;
PITCH_WIDTH: natural
);
port(
clock: in std_logic;
reset:in std_logic;
-- register interface
srcStart: in unsigned(ADDRESS_WIDTH-1 downto 0);
srcPitch: in unsigned(PITCH_WIDTH-1 downto 0);
dstStart: in unsigned(ADDRESS_WIDTH-1 downto 0);
dstPitch: in unsigned(PITCH_WIDTH-1 downto 0);
color: in unsigned(BIT_DEPTH-1 downto 0);
srcX0: in unsigned(15 downto 0);
srcY0: in unsigned(15 downto 0);
srcX1: in unsigned(15 downto 0);
dstX0: in unsigned(15 downto 0);
dstY0: in unsigned(15 downto 0);
dstX1: in unsigned(15 downto 0);
dstY1: in unsigned(15 downto 0);
blitTransparent: in std_logic;
command: in unsigned(7 downto 0);
-- operation interface
start: in std_logic;
busy: out std_logic;
-- framebuffer interface
readAddress: out unsigned(ADDRESS_WIDTH-1 downto 0);
writeAddress: out unsigned(ADDRESS_WIDTH-1 downto 0);
data: out unsigned(BIT_DEPTH-1 downto 0);
q: in unsigned(BIT_DEPTH-1 downto 0);
writeEnable: out std_logic
);
end entity GraphicsAccelerator;
architecture rtl of GraphicsAccelerator is
-- statemachine
type stateType is (
WAIT_FOR_START,
PIXEL,
LINE_INIT,
HORIZONTAL_LINE,
VERTICAL_LINE,
RECT,
BLIT_DELAY1,
BLIT_DELAY2,
BLIT
);
signal state: stateType := WAIT_FOR_START;
signal x: unsigned(15 downto 0);
signal y: unsigned(15 downto 0);
signal x2: unsigned(15 downto 0);
signal y2: unsigned(15 downto 0);
signal dx: unsigned(15 downto 0);
signal dy: unsigned(15 downto 0);
signal incx: std_logic;
signal incy: std_logic;
signal balance: signed(15 downto 0);
begin
process(clock)
variable dx2: unsigned(dx'high downto 0);
variable dy2: unsigned(dy'high downto 0);
procedure setPixel(x: unsigned(15 downto 0); y: unsigned(15 downto 0); clr: unsigned(BIT_DEPTH-1 downto 0)) is
begin
writeAddress <= adjustLength(dstStart + dstPitch * y + x, writeAddress'length);
writeEnable <= '1';
data <= clr;
end;
procedure nextBlitRead is
begin
readAddress <= adjustLength(srcStart + srcPitch * y2 + x2, readAddress'length);
if x2 < srcX1 then
x2 <= x2 + 1;
else
x2 <= srcX0;
y2 <= y2 + 1;
end if;
end;
procedure doIncx is
begin
if incx = '1' then
x <= x + 1;
else
x <= x - 1;
end if;
end;
procedure doIncy is
begin
if incy = '1' then
y <= y + 1;
else
y <= y - 1;
end if;
end;
begin
if rising_edge(clock) then
if reset = '1' then
state <= WAIT_FOR_START;
busy <= '0';
else
writeEnable <= '0';
case state is
when WAIT_FOR_START =>
busy <= '0';
if start = '1' then
busy <= '1';
case command is
when SET_PIXEL =>
x <= dstX0;
y <= dstY0;
state <= PIXEL;
when LINE_TO =>
if dstX1 >= dstX0 then
dx <= dstX1 - dstX0;
incx <= '1';
else
dx <= dstX0 - dstX1;
incx <= '0';
end if;
if dstY1 >= dstY0 then
dy <= dstY1 - dstY0;
incy <= '1';
else
dy <= dstY0 - dstY1;
incy <= '0';
end if;
x <= dstX0;
y <= dstY0;
x2 <= dstX1;
y2 <= dstY1;
state <= LINE_INIT;
when FILL_RECT =>
x <= dstX0;
y <= dstY0;
state <= RECT;
when BLIT_COMMAND | BLIT_TRANSPARENT =>
x <= dstX0;
y <= dstY0;
x2 <= srcX0;
y2 <= srcY0;
state <= BLIT_DELAY1;
when others => null;
end case;
end if;
when PIXEL =>
setPixel(x, y, color);
state <= WAIT_FOR_START;
when LINE_INIT =>
dx2 := dx(dx'high - 1 downto 0) & "0";
dy2 := dy(dy'high - 1 downto 0) & "0";
if dx >= dy then
balance <= to_signed(to_integer(dy2) - to_integer(dx), balance'length);
state <= HORIZONTAL_LINE;
else
balance <= to_signed(to_integer(dx2) - to_integer(dy), balance'length);
state <= VERTICAL_LINE;
end if;
dx <= dx2;
dy <= dy2;
when HORIZONTAL_LINE =>
if x /= x2 then
setPixel(x, y, color);
if balance >= 0 then
doIncy;
balance <= balance - to_integer(dx) + to_integer(dy);
else
balance <= balance + to_integer(dy);
end if;
doIncx;
else
setPixel(x, y, color);
state <= WAIT_FOR_START;
end if;
when VERTICAL_LINE =>
if y /= y2 then
setPixel(x, y, color);
if balance >= 0 then
doIncx;
balance <= balance - to_integer(dy) + to_integer(dx);
else
balance <= balance + to_integer(dx);
end if;
doIncy;
else
setPixel(x, y, color);
state <= WAIT_FOR_START;
end if;
when RECT =>
setPixel(x, y, color);
if x < dstX1 then
x <= x + 1;
else
x <= dstX0;
if y < dstY1 then
y <= y + 1;
else
state <= WAIT_FOR_START;
end if;
end if;
when BLIT_DELAY1 =>
nextBlitRead;
state <= BLIT_DELAY2;
when BLIT_DELAY2 =>
nextBlitRead;
state <= BLIT;
when BLIT =>
if blitTransparent = '1' then
if q /= color then
setPixel(x, y, q);
end if;
else
setPixel(x, y, q);
end if;
if x < dstX1 then
x <= x + 1;
else
x <= dstX0;
if y < dstY1 then
y <= y + 1;
else
state <= WAIT_FOR_START;
end if;
end if;
nextBlitRead;
when others =>
state <= WAIT_FOR_START;
end case;
end if;
end if;
end process;
end architecture rtl;
| mit | 0a322bf4ab8b7067568bb61f736f5db2 | 0.556755 | 2.92357 | false | false | false | false |
insop/hyos | hyos_plb_v1_00_e/hdl/vhdl/hyos_plb.vhd | 1 | 25,609 | ------------------------------------------------------------------------------
-- hyos_plb.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: hyos_plb.vhd
-- Version: 1.00.e
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Mar 22 15:43:09 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library hyos_plb_v1_00_e;
use hyos_plb_v1_00_e.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity hyos_plb is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex6"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity hyos_plb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of hyos_plb is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 8;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant RST_NUM_CE : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => RST_NUM_CE -- number of ce for soft reset space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 4;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant RST_CS_INDEX : integer := 1;
constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 8
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "01" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| gpl-3.0 | ac6eee068801d92424e241c4f11e0467 | 0.449451 | 4.432156 | false | false | false | false |
PsiStarPsi/firmware-general | Transceivers/S6/GtpS6.vhd | 1 | 17,384 | library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
use work.UtilityPkg.all;
entity GtpS6 is
generic (
-- Reference clock selection --
-- 000: CLK00/CLK01 selected
-- 001: GCLK00/GCLK01 selected
-- 010: PLLCLK00/PLLCLK01 selected
-- 011: CLKINEAST0/CLKINEAST0 selected
-- 100: CLK10/CLK11 selected
-- 101: GCLK10/GCLK11 selected
-- 110: PLLCLK10/PLLCLK11 selected
-- 111: CLKINWEST0/CLKINWEST1 selected
REF_SEL_PLL0_G : slv(2 downto 0) := "001";
REF_SEL_PLL1_G : slv(2 downto 0) := "001"
);
port (
-- Clocking & reset
gtpClkIn : in std_logic;
gtpReset0 : in std_logic;
gtpReset1 : in std_logic;
txReset0 : in std_logic;
txReset1 : in std_logic;
rxReset0 : in std_logic;
rxReset1 : in std_logic;
rxBufReset0 : in std_logic;
rxBufReset1 : in std_logic;
-- User clock out
usrClkOut : out std_logic;
usrClkX2Out : out std_logic;
-- DCM clocking
dcmClkValid : out std_logic;
dcmSpLocked : out std_logic;
usrClkValid : out std_logic;
usrClkLocked : out std_logic;
-- General status outputs
pllLock0 : out std_logic;
pllLock1 : out std_logic;
gtpResetDone0 : out std_logic;
gtpResetDone1 : out std_logic;
-- Input signals (raw)
gtpRxP0 : in std_logic;
gtpRxN0 : in std_logic;
gtpTxP0 : out std_logic;
gtpTxN0 : out std_logic;
gtpRxP1 : in std_logic;
gtpRxN1 : in std_logic;
gtpTxP1 : out std_logic;
gtpTxN1 : out std_logic;
-- Data interfaces
rxDataOut0 : out std_logic_vector(15 downto 0);
rxDataOut1 : out std_logic_vector(15 downto 0);
txDataIn0 : in std_logic_vector(15 downto 0);
txDataIn1 : in std_logic_vector(15 downto 0);
-- RX status
rxCharIsComma0 : out std_logic_vector(1 downto 0);
rxCharIsComma1 : out std_logic_vector(1 downto 0);
rxCharIsK0 : out std_logic_vector(1 downto 0);
rxCharIsK1 : out std_logic_vector(1 downto 0);
rxDispErr0 : out std_logic_vector(1 downto 0);
rxDispErr1 : out std_logic_vector(1 downto 0);
rxNotInTable0 : out std_logic_vector(1 downto 0);
rxNotInTable1 : out std_logic_vector(1 downto 0);
rxRunDisp0 : out std_logic_vector(1 downto 0);
rxRunDisp1 : out std_logic_vector(1 downto 0);
rxClkCor0 : out std_logic_vector(2 downto 0);
rxClkCor1 : out std_logic_vector(2 downto 0);
rxByteAligned0 : out std_logic;
rxByteAligned1 : out std_logic;
rxEnMCommaAlign0 : in std_logic;
rxEnMCommaAlign1 : in std_logic;
rxEnPCommaAlign0 : in std_logic;
rxEnPCommaAlign1 : in std_logic;
rxBufStatus0 : out std_logic_vector(2 downto 0);
rxBufStatus1 : out std_logic_vector(2 downto 0);
-- TX status
txCharDispMode0 : in std_logic_vector(1 downto 0) := "00";
txCharDispMode1 : in std_logic_vector(1 downto 0) := "00";
txCharDispVal0 : in std_logic_vector(1 downto 0) := "00";
txCharDispVal1 : in std_logic_vector(1 downto 0) := "00";
txCharIsK0 : in std_logic_vector(1 downto 0);
txCharIsK1 : in std_logic_vector(1 downto 0);
txRunDisp0 : out std_logic_vector(1 downto 0);
txRunDisp1 : out std_logic_vector(1 downto 0);
txBufStatus0 : out std_logic_vector(1 downto 0);
txBufStatus1 : out std_logic_vector(1 downto 0);
-- Loopback settings
loopbackIn0 : in std_logic_vector(2 downto 0) := "000";
loopbackIn1 : in std_logic_vector(2 downto 0) := "000"
);
end GtpS6;
architecture rtl of GtpS6 is
constant slZero : std_logic := '0';
-- Reference clock selection --
-- 000: CLK00/CLK01 selected
-- 001: GCLK00/GCLK01 selected
-- 010: PLLCLK00/PLLCLK01 selected
-- 011: CLKINEAST0/CLKINEAST0 selected
-- 100: CLK10/CLK11 selected
-- 101: GCLK10/GCLK11 selected
-- 110: PLLCLK10/PLLCLK11 selected
-- 111: CLKINWEST0/CLKINWEST1 selected
-- constant refSelDyPll0 : std_logic_vector(2 downto 0) := "001";
-- constant refSelDyPll1 : std_logic_vector(2 downto 0) := "001";
-- DCM signals
signal clk0 : std_logic;
signal clkOut1 : std_logic;
signal clkDv : std_logic;
signal dcmInputClockStopped : std_logic;
signal clkIn1 : std_logic;
signal clkFbIn : std_logic;
signal gclkDcm : std_logic;
signal dcmSpStatus : std_logic_vector(7 downto 0);
signal dcmSpLockedInternal : std_logic;
signal usrClkStatus : std_logic_vector(7 downto 0);
signal usrClkLockedInternal : std_logic;
signal pllLock0Internal : std_logic;
signal pllLock1Internal : std_logic;
signal rxClkCorr0 : std_logic_vector(2 downto 0);
signal rxClkCorr1 : std_logic_vector(2 downto 0);
-- User clocking
signal gtpClkOut0 : std_logic_vector(1 downto 0);
signal gtpClkOut1 : std_logic_vector(1 downto 0);
signal txOutClk0 : std_logic;
signal txOutClk1 : std_logic;
signal usrClkSource : std_logic;
signal usrClkSourceBufG : std_logic;
signal txRxUsrClkRaw : std_logic;
signal txRxUsrClk2Raw : std_logic;
signal txRxUsrClk : std_logic;
signal txRxUsrClk2 : std_logic;
signal usrClkX2Raw : std_logic;
begin
-- Set up input clocking here
U_S6_DCM : DCM_SP
generic map (
CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 4.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => false
)
port map (
-- CLKIN => clkIn1,
CLKIN => gtpClkIn,
CLKFB => clkFbIn,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => clkDv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Control & status
LOCKED => dcmSpLockedInternal,
STATUS => dcmSpStatus,
RST => '0',
-- Unused, tie low
DSSEN => '0'
);
dcmInputClockStopped <= dcmSpStatus(1);
dcmSpLocked <= dcmSpLockedInternal;
dcmClkValid <= dcmSpLockedInternal and (not dcmSpStatus(1));
-- U_DcmClkIn_BufG : BUFG port map ( I => gtpClkIn, O => clkIn1 );
U_DcmFb_BufG : BUFG port map ( I => clk0, O => clkFbIn );
U_DcmClkOut_BufG : BUFG port map ( I => clkDv, O => gClkDcm );
-- Set up USR clocks (see UG386 p. 74 for TX)
-- (see UG386 p. 159 for RX)
U_USRCLK_DCM : DCM_SP
generic map (
CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 8.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => false
)
port map (
CLKIN => usrClkSource,
CLKFB => txRxUsrClk,
-- Output clocks
CLK0 => txRxUsrClkRaw,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => txRxUsrClk2Raw,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Control & status
LOCKED => usrClkLockedInternal,
STATUS => usrClkStatus,
RST => not(pllLock0Internal),
-- Unused, tie low
DSSEN => '0'
);
pllLock0 <= pllLock0Internal;
-- usrInputClockStopped <= usrClkStatus(1);
usrClkLocked <= usrClkLockedInternal;
usrClkValid <= usrClkLockedInternal and (not usrClkStatus(1));
U_BufIo2 : BUFIO2 port map ( I => gtpClkOut0(0), DIVCLK => usrClkSource );
-- U_usrClk_BufG : BUFG port map ( I => usrClkSource, O => usrClkSourceBufG );
U_UsrClkOut_BufG : BUFG port map ( I => txRxUsrClkRaw, O => txRxUsrClk );
U_UsrClk2Out_BufG : BUFG port map ( I => txRxUsrClk2Raw, O => txRxUsrClk2 );
usrClkX2Out <= txRxUsrClk;
-- U_UsrClkX2_BufG : BUFG port map ( I => usrClkX2Raw, O => usrClkX2Out );
-- Clock out to the rest of the system
usrClkOut <= txRxUsrClk2;
--------------------------
-- Instantiate the tile --
--------------------------
U_GtpS6Tile : entity work.GtpS6Tile
generic map (
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP => 0, -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 => 5,
TILE_CLK25_DIVIDER_1 => 5,
TILE_PLL_DIVSEL_FB_0 => 2,
TILE_PLL_DIVSEL_FB_1 => 2,
TILE_PLL_DIVSEL_REF_0 => 1,
TILE_PLL_DIVSEL_REF_1 => 1,
TILE_SIM_REFCLK0_SOURCE => "000",
TILE_SIM_REFCLK1_SOURCE => "000",
--
TILE_PLL_SOURCE_0 => "PLL0",
TILE_PLL_SOURCE_1 => "PLL0"
)
port map (
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN => loopbackIn0, -- in std_logic_vector(2 downto 0);
LOOPBACK1_IN => loopbackIn1, -- in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN => slZero, -- in std_logic;
CLK01_IN => slZero, -- in std_logic;
CLK10_IN => slZero, -- in std_logic;
CLK11_IN => slZero, -- in std_logic;
GCLK00_IN => gClkDcm, -- in std_logic;
GCLK01_IN => slZero, -- in std_logic;
GCLK10_IN => slZero, -- in std_logic;
GCLK11_IN => slZero, -- in std_logic;
CLKINEAST0_IN => slZero, -- in std_logic;
CLKINEAST1_IN => slZero, -- in std_logic;
CLKINWEST0_IN => slZero, -- in std_logic;
CLKINWEST1_IN => slZero, -- in std_logic;
GTPRESET0_IN => gtpReset0, -- in std_logic;
GTPRESET1_IN => gtpReset1, -- in std_logic;
TXRESET0_IN => txReset0, -- in std_logic;
TXRESET1_IN => txReset1, -- in std_logic;
RXRESET0_IN => rxReset0, -- in std_logic;
RXRESET1_IN => rxReset1, -- in std_logic;
PLLLKDET0_OUT => pllLock0Internal, -- out std_logic;
PLLLKDET1_OUT => pllLock1Internal, -- out std_logic;
REFSELDYPLL0_IN => REF_SEL_PLL0_G, -- in std_logic_vector(2 downto 0);
REFSELDYPLL1_IN => REF_SEL_PLL1_G, -- in std_logic_vector(2 downto 0);
RESETDONE0_OUT => gtpResetDone0, -- out std_logic;
RESETDONE1_OUT => gtpResetDone1, -- out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0_OUT => rxCharIsComma0, -- out std_logic_vector(1 downto 0);
RXCHARISCOMMA1_OUT => rxCharIsComma1, -- out std_logic_vector(1 downto 0);
RXCHARISK0_OUT => rxCharIsK0, -- out std_logic_vector(1 downto 0);
RXCHARISK1_OUT => rxCharIsK1, -- out std_logic_vector(1 downto 0);
RXDISPERR0_OUT => rxDispErr0, -- out std_logic_vector(1 downto 0);
RXDISPERR1_OUT => rxDispErr1, -- out std_logic_vector(1 downto 0);
RXNOTINTABLE0_OUT => rxNotInTable0, -- out std_logic_vector(1 downto 0);
RXNOTINTABLE1_OUT => rxNotInTable1, -- out std_logic_vector(1 downto 0);
RXRUNDISP0_OUT => rxRunDisp0, -- out std_logic_vector(1 downto 0);
RXRUNDISP1_OUT => rxRunDisp1, -- out std_logic_vector(1 downto 0);
--------------- Receive Ports - RX Buffer and Phase Alignment --------------
RXBUFRESET0_IN => rxBufReset0, -- in std_logic;
RXBUFRESET1_IN => rxBufReset1, -- in std_logic;
RXBUFSTATUS0_OUT => rxBufStatus0, -- out std_logic_vector(2 downto 0);
RXBUFSTATUS1_OUT => rxBufStatus1, -- out std_logic_vector(2 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0_OUT => rxClkCorr0, -- out std_logic_vector(2 downto 0);
RXCLKCORCNT1_OUT => rxClkCorr1, -- out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT => rxByteAligned0, -- out std_logic;
RXBYTEISALIGNED1_OUT => rxByteAligned1, -- out std_logic;
RXENMCOMMAALIGN0_IN => rxEnMCommaAlign0, -- in std_logic;
RXENMCOMMAALIGN1_IN => rxEnMCommaAlign1, -- in std_logic;
RXENPCOMMAALIGN0_IN => rxEnPCommaAlign0, -- in std_logic;
RXENPCOMMAALIGN1_IN => rxEnPCommaAlign1, -- in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT => rxDataOut0, -- out std_logic_vector(15 downto 0);
RXDATA1_OUT => rxDataOut1, -- out std_logic_vector(15 downto 0);
RXUSRCLK0_IN => txRxUsrClk, -- in std_logic;
RXUSRCLK1_IN => txRxUsrClk, -- in std_logic;
RXUSRCLK20_IN => txRxUsrClk2, -- in std_logic;
RXUSRCLK21_IN => txRxUsrClk2, -- in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXN0_IN => gtpRxN0, -- in std_logic;
RXN1_IN => gtpRxN1, -- in std_logic;
RXP0_IN => gtpRxP0, -- in std_logic;
RXP1_IN => gtpRxP1, -- in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT => gtpClkOut0, -- out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT => gtpClkOut1, -- out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARDISPMODE0_IN => txCharDispMode0, -- in std_logic_vector(1 downto 0);
TXCHARDISPMODE1_IN => txCharDispMode1, -- in std_logic_vector(1 downto 0);
TXCHARDISPVAL0_IN => txCharDispVal0, -- in std_logic_vector(1 downto 0);
TXCHARDISPVAL1_IN => txCharDispVal1, -- in std_logic_vector(1 downto 0);
TXCHARISK0_IN => txCharIsK0, -- in std_logic_vector(1 downto 0);
TXCHARISK1_IN => txCharIsK1, -- in std_logic_vector(1 downto 0);
TXRUNDISP0_OUT => txRunDisp0, -- out std_logic_vector(1 downto 0);
TXRUNDISP1_OUT => txRunDisp1, -- out std_logic_vector(1 downto 0);
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0_OUT => txBufStatus0, -- out std_logic_vector(1 downto 0);
TXBUFSTATUS1_OUT => txBufStatus1, -- out std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN => txDataIn0, -- in std_logic_vector(15 downto 0);
TXDATA1_IN => txDataIn1, -- in std_logic_vector(15 downto 0);
TXOUTCLK0_OUT => txOutClk0, -- out std_logic;
TXOUTCLK1_OUT => txOutClk1, -- out std_logic;
TXUSRCLK0_IN => txRxUsrClk, -- in std_logic;
TXUSRCLK1_IN => txRxUsrClk, -- in std_logic;
TXUSRCLK20_IN => txRxUsrClk2, -- in std_logic;
TXUSRCLK21_IN => txRxUsrClk2, -- in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT => gtpTxN0, -- out std_logic;
TXN1_OUT => gtpTxN1, -- out std_logic;
TXP0_OUT => gtpTxP0, -- out std_logic;
TXP1_OUT => gtpTxP1 -- out std_logic
);
end rtl;
| lgpl-2.1 | 520f03dd46aab2fdf04b4df7dd168291 | 0.519501 | 3.59545 | false | false | false | false |
pkerling/ethernet_mac | crc32.vhd | 1 | 1,732 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Utility functions for CRC32/Ethernet frame check sequence calculation
library ieee;
use ieee.std_logic_1164.all;
use work.crc.all;
package crc32 is
-- As defined in IEEE 802.3 clause 3.2.9
-- x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
constant CRC32_POLYNOMIAL : std_ulogic_vector(32 downto 0) := (
32 | 26 | 23 | 22 | 16 | 12 | 11 | 10 | 8 | 7 | 5 | 4 | 2 | 1 | 0 => '1',
others => '0'
);
-- CRC32 value type
subtype t_crc32 is std_ulogic_vector(31 downto 0);
-- Value that remains as CRC value when incoming data including the original FCS is piped through update_crc32
-- and the FCS is correct.
-- Usually this would be zero, but the inversion of the FCS in clause 3.2.9 e changes it to this magic value.
constant CRC32_POSTINVERT_MAGIC : t_crc32 := X"C704DD7B";
-- Update CRC32 old_crc by one bit (input)
function update_crc32(old_crc : t_crc32; input : std_ulogic) return t_crc32;
-- Update CRC32 old_crc by an arbitrary number of bits (input)
function update_crc32(old_crc : t_crc32; input : std_ulogic_vector) return t_crc32;
constant CRC32_BYTES : positive := (t_crc32'length / 8);
end package;
package body crc32 is
function update_crc32(old_crc : t_crc32; input : std_ulogic) return t_crc32 is
begin
return update_crc(old_crc, input, CRC32_POLYNOMIAL);
end function;
function update_crc32(old_crc : t_crc32; input : std_ulogic_vector) return t_crc32 is
begin
return update_crc(old_crc, input, CRC32_POLYNOMIAL);
end function;
end package body;
| bsd-3-clause | 5c47ea12599e4c2581bf9a7c90acc1aa | 0.69515 | 2.991364 | false | false | false | false |
pkerling/ethernet_mac | framing.vhd | 1 | 13,660 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- MAC sublayer functionality (en-/decapsulation, FCS, IPG)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
use work.framing_common.all;
use work.crc32.all;
use work.utility.all;
entity framing is
port(
tx_reset_i : in std_ulogic;
tx_clock_i : in std_ulogic;
rx_reset_i : in std_ulogic;
rx_clock_i : in std_ulogic;
-- MAC address of this station
-- Must not change after either reset is deasserted
-- Used for
-- * dropping received packets when the destination address differs from both this one and the broadcast address
-- * inserting as source address in transmitted packets when the first byte of the source address in the data stream is all-ones
mac_address_i : in t_mac_address;
-- For details on the signals, see the port list of mii_gmii
-- TX from client logic
-- The length/type field is considered part of the data!
-- It is not interpreted by the framing layer at all.
tx_enable_i : in std_ulogic;
tx_data_i : in t_ethernet_data;
tx_byte_sent_o : out std_ulogic;
-- Do not start new frames while asserted
-- (continuing the previous one is alright)
tx_busy_o : out std_ulogic;
-- RX to client logic
rx_frame_o : out std_ulogic;
rx_data_o : out t_ethernet_data;
rx_byte_received_o : out std_ulogic;
rx_error_o : out std_ulogic;
-- TX to MII
mii_tx_enable_o : out std_ulogic;
mii_tx_data_o : out t_ethernet_data;
mii_tx_byte_sent_i : in std_ulogic;
mii_tx_gap_o : out std_ulogic;
-- RX from MII
mii_rx_frame_i : in std_ulogic;
mii_rx_data_i : in t_ethernet_data;
mii_rx_byte_received_i : in std_ulogic;
mii_rx_error_i : in std_ulogic
);
end entity;
architecture rtl of framing is
-- Transmission
type t_tx_state is (
TX_IDLE,
-- TX_PREMABLE1 is not needed: first preamble byte is transmitted directly in TX_IDLE when start of transmission
-- is detected.
TX_PREAMBLE2,
TX_PREAMBLE3,
TX_PREAMBLE4,
TX_PREAMBLE5,
TX_PREAMBLE6,
TX_PREAMBLE7,
TX_START_FRAME_DELIMITER,
TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS,
TX_SOURCE_ADDRESS,
TX_CLIENT_DATA,
TX_PAD,
TX_FRAME_CHECK_SEQUENCE2,
TX_FRAME_CHECK_SEQUENCE3,
TX_FRAME_CHECK_SEQUENCE4,
TX_INTERPACKET_GAP
);
signal tx_state : t_tx_state := TX_IDLE;
signal tx_frame_check_sequence : t_crc32;
signal tx_padding_required : natural range 0 to MIN_FRAME_DATA_BYTES + 4 + 1 := 0;
signal tx_interpacket_gap_counter : integer range 0 to INTERPACKET_GAP_BYTES;
signal tx_mac_address_byte : integer range 0 to MAC_ADDRESS_BYTES;
-- Reception
type t_rx_state is (
RX_WAIT_START_FRAME_DELIMITER,
RX_DATA,
RX_ERROR,
RX_SKIP_FRAME
);
signal rx_state : t_rx_state := RX_WAIT_START_FRAME_DELIMITER;
signal rx_frame_check_sequence : t_crc32;
subtype t_rx_frame_size is natural range 0 to MAX_FRAME_DATA_BYTES + CRC32_BYTES + 1;
signal rx_frame_size : t_rx_frame_size;
signal rx_is_group_address : std_ulogic;
signal rx_mac_address_byte : integer range 0 to MAC_ADDRESS_BYTES;
begin
-- Pass mii_tx_byte_sent_i through directly as long as data is being transmitted
-- to avoid having to prefetch data in the synchronous process
tx_byte_sent_o <= '1' when ((tx_state = TX_CLIENT_DATA or tx_state = TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS or tx_state = TX_SOURCE_ADDRESS) and mii_tx_byte_sent_i = '1') else '0';
-- Transmission state machine
tx_fsm_sync : process(tx_reset_i, tx_clock_i)
variable update_fcs : boolean;
variable data_out : t_ethernet_data;
begin
if tx_reset_i = '1' then
tx_state <= TX_IDLE;
mii_tx_enable_o <= '0';
tx_busy_o <= '1';
elsif rising_edge(tx_clock_i) then
mii_tx_enable_o <= '0';
tx_busy_o <= '0';
if tx_state = TX_IDLE then
if tx_enable_i = '1' then
-- Jump straight into preamble to save a clock cycle of latency
tx_state <= TX_PREAMBLE2;
mii_tx_data_o <= PREAMBLE_DATA;
mii_tx_enable_o <= '1';
mii_tx_gap_o <= '0';
tx_busy_o <= '1';
end if;
else
-- Keep TX enable and busy asserted at all times
mii_tx_enable_o <= '1';
tx_busy_o <= '1';
-- Use mii_tx_byte_sent_i as clock enable
if mii_tx_byte_sent_i = '1' then
mii_tx_gap_o <= '0';
data_out := (others => '0');
update_fcs := FALSE;
case tx_state is
when TX_IDLE =>
-- Handled above, cannot happen here
null;
when TX_PREAMBLE2 | TX_PREAMBLE3 | TX_PREAMBLE4 | TX_PREAMBLE5 | TX_PREAMBLE6 =>
tx_state <= t_tx_state'succ(tx_state);
data_out := PREAMBLE_DATA;
when TX_PREAMBLE7 =>
tx_state <= TX_START_FRAME_DELIMITER;
data_out := PREAMBLE_DATA;
when TX_START_FRAME_DELIMITER =>
tx_state <= TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS;
data_out := START_FRAME_DELIMITER_DATA;
-- Load padding register
tx_padding_required <= MIN_FRAME_DATA_BYTES;
-- Load FCS
-- Initial value is 0xFFFFFFFF which is equivalent to inverting the first 32 bits of the frame
-- as required in clause 3.2.9 a
tx_frame_check_sequence <= (others => '1');
-- Load MAC address counter
tx_mac_address_byte <= 0;
when TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS =>
data_out := tx_data_i;
update_fcs := TRUE;
-- Skip destination address
if tx_mac_address_byte < MAC_ADDRESS_BYTES then
tx_mac_address_byte <= tx_mac_address_byte + 1;
else
-- All-ones means that we should insert the source address here
if tx_data_i = x"FF" then
tx_state <= TX_SOURCE_ADDRESS;
-- Override client data with first source address byte
data_out := extract_byte(mac_address_i, 0);
-- Second byte is to be sent in next cycle
tx_mac_address_byte <= 1;
else
-- Transmit as usual, skip TX_SOURCE_ADDRESS
tx_state <= TX_CLIENT_DATA;
end if;
end if;
-- Bail out from here if transmission was aborted
-- Note that this should not happen under normal circumstances as the
-- Ethernet frame would be far too short.
if tx_enable_i = '0' then
tx_state <= TX_PAD;
data_out := PADDING_DATA;
end if;
when TX_SOURCE_ADDRESS =>
data_out := extract_byte(mac_address_i, tx_mac_address_byte);
update_fcs := TRUE;
if tx_mac_address_byte < MAC_ADDRESS_BYTES - 1 then
tx_mac_address_byte <= tx_mac_address_byte + 1;
else
-- Address completely sent when tx_mac_address_byte reaches 5
-- Pass on client data again in next cycle
tx_state <= TX_CLIENT_DATA;
end if;
when TX_CLIENT_DATA =>
data_out := tx_data_i;
update_fcs := TRUE;
if tx_enable_i = '0' then
-- No more user data was available, next value has to be sent
-- in this clock cycle already
if tx_padding_required = 0 then
-- Send FCS byte 1 now, byte 2 in next cycle
tx_state <= TX_FRAME_CHECK_SEQUENCE2;
data_out := fcs_output_byte(tx_frame_check_sequence, 0);
update_fcs := FALSE;
else
tx_state <= TX_PAD;
data_out := PADDING_DATA;
end if;
end if;
when TX_PAD =>
data_out := PADDING_DATA;
update_fcs := TRUE;
if tx_padding_required = 0 then
-- When required=0, previous one was the last one -> send FCS
tx_state <= TX_FRAME_CHECK_SEQUENCE2;
data_out := fcs_output_byte(tx_frame_check_sequence, 0);
update_fcs := FALSE;
end if;
when TX_FRAME_CHECK_SEQUENCE2 =>
tx_state <= t_tx_state'succ(tx_state);
data_out := fcs_output_byte(tx_frame_check_sequence, 1);
when TX_FRAME_CHECK_SEQUENCE3 =>
tx_state <= t_tx_state'succ(tx_state);
data_out := fcs_output_byte(tx_frame_check_sequence, 2);
when TX_FRAME_CHECK_SEQUENCE4 =>
tx_state <= TX_INTERPACKET_GAP;
data_out := fcs_output_byte(tx_frame_check_sequence, 3);
-- Load IPG counter with initial value
tx_interpacket_gap_counter <= 0;
when TX_INTERPACKET_GAP =>
-- Only state where the MAC is still busy but no data is actually sent
mii_tx_gap_o <= '1';
if tx_interpacket_gap_counter = INTERPACKET_GAP_BYTES - 1 then
-- Last IPG byte is transmitted in this cycle
tx_state <= TX_IDLE;
else
tx_interpacket_gap_counter <= tx_interpacket_gap_counter + 1;
end if;
end case;
mii_tx_data_o <= data_out;
if update_fcs then
tx_frame_check_sequence <= update_crc32(tx_frame_check_sequence, data_out);
end if;
if tx_state = TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS or tx_state = TX_SOURCE_ADDRESS or tx_state = TX_CLIENT_DATA or tx_state = TX_PAD then
-- Decrement required padding
if tx_padding_required > 0 then
tx_padding_required <= tx_padding_required - 1;
end if;
end if;
end if;
end if;
end if;
end process;
-- Reception state machine
rx_fsm_sync : process(rx_reset_i, rx_clock_i)
begin
if rx_reset_i = '1' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
elsif rising_edge(rx_clock_i) then
rx_error_o <= '0';
rx_data_o <= mii_rx_data_i;
rx_byte_received_o <= '0';
rx_frame_o <= '0';
case rx_state is
when RX_WAIT_START_FRAME_DELIMITER =>
-- Reset MAC address detection
rx_mac_address_byte <= 0;
rx_is_group_address <= '1';
-- Reset frame size and FCS
rx_frame_size <= 0;
-- Initial value is 0xFFFFFFFF which is equivalent to inverting the first 32 bits of the frame
-- as required in clause 3.2.9 a
rx_frame_check_sequence <= (others => '1');
if mii_rx_frame_i = '1' then
if mii_rx_byte_received_i = '1' then
case mii_rx_data_i is
when START_FRAME_DELIMITER_DATA =>
rx_state <= RX_DATA;
when PREAMBLE_DATA =>
-- Do nothing, wait for end of preamble
null;
when others =>
-- The frame needs to be thrown away, but there is no need to
-- inform the higher layer since nothing of value was actually "received" anyway.
rx_state <= RX_SKIP_FRAME;
end case;
end if;
if mii_rx_error_i = '1' then
-- Same here
rx_state <= RX_SKIP_FRAME;
end if;
end if;
when RX_DATA =>
rx_frame_o <= '1';
rx_byte_received_o <= mii_rx_byte_received_i;
if mii_rx_frame_i = '0' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
-- Remaining FCS after parsing whole packet + FCS needs to be a specific value
if mii_rx_error_i = '1' or rx_frame_check_sequence /= CRC32_POSTINVERT_MAGIC or rx_frame_size < MIN_FRAME_DATA_BYTES + CRC32_BYTES or rx_frame_size > MAX_FRAME_DATA_BYTES + CRC32_BYTES then
rx_error_o <= '1';
end if;
else
if mii_rx_byte_received_i = '1' then
-- Update FCS check
rx_frame_check_sequence <= update_crc32(rx_frame_check_sequence, mii_rx_data_i);
-- Increase frame size
if rx_frame_size < t_rx_frame_size'high then
rx_frame_size <= rx_frame_size + 1;
end if;
-- Check destination MAC address (first 6 bytes of packet)
if rx_mac_address_byte < MAC_ADDRESS_BYTES then
-- First byte determines whether the address is an individual or group address
if rx_mac_address_byte = 0 then
if mii_rx_data_i(0) = '0' then
-- LSB of the address is zero: packet is destined for an individual entity
rx_is_group_address <= '0';
-- Check first address byte
if mii_rx_data_i /= extract_byte(mac_address_i, rx_mac_address_byte) then
-- Packet is not destined for us -> drop it
rx_state <= RX_ERROR;
end if;
end if;
-- If not: It is a group address packet -> do not drop it and do not check the address further
elsif rx_is_group_address = '0' then
-- Check other MAC address bytes only if we know it doesn't have a group destination address
if mii_rx_data_i /= extract_byte(mac_address_i, rx_mac_address_byte) then
-- Packet is not destined for us -> drop it
rx_state <= RX_ERROR;
end if;
end if;
rx_mac_address_byte <= rx_mac_address_byte + 1;
end if;
end if;
if mii_rx_error_i = '1' then
-- Skip the rest of the frame and tell the higher layer
rx_state <= RX_ERROR;
end if;
end if;
when RX_SKIP_FRAME =>
-- Skip the currently receiving frame without signaling the higher layer
if mii_rx_frame_i = '0' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
end if;
when RX_ERROR =>
-- Skip the currently receiving frame and signal the higher layer
rx_frame_o <= '1';
rx_error_o <= '1';
if mii_rx_frame_i = '0' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
end if;
end case;
end if;
end process;
end architecture;
| bsd-3-clause | 5c0680efe47bd602abf433b51fa1eaef | 0.600439 | 3.215631 | false | false | false | false |
32bitmicro/Malinki | fabric/rio/rtl/vhdl/RioCommon.vhd | 2 | 45,114 | -------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Contains commonly used types, functions, procedures and entities used in
-- the RapidIO IP library project.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RioCommon library.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- RioCommon package description.
-------------------------------------------------------------------------------
package rio_common is
-----------------------------------------------------------------------------
-- Commonly used types.
-----------------------------------------------------------------------------
type Array1 is array (natural range <>) of
std_logic;
type Array2 is array (natural range <>) of
std_logic_vector(1 downto 0);
type Array3 is array (natural range <>) of
std_logic_vector(2 downto 0);
type Array4 is array (natural range <>) of
std_logic_vector(3 downto 0);
type Array5 is array (natural range <>) of
std_logic_vector(4 downto 0);
type Array8 is array (natural range <>) of
std_logic_vector(7 downto 0);
type Array9 is array (natural range <>) of
std_logic_vector(8 downto 0);
type Array10 is array (natural range <>) of
std_logic_vector(9 downto 0);
type Array16 is array (natural range <>) of
std_logic_vector(15 downto 0);
type Array32 is array (natural range <>) of
std_logic_vector(31 downto 0);
type Array34 is array (natural range <>) of
std_logic_vector(33 downto 0);
-----------------------------------------------------------------------------
-- Commonly used constants.
-----------------------------------------------------------------------------
-- Symbol types between the serial and the PCS layer.
constant SYMBOL_IDLE : std_logic_vector(1 downto 0) := "00";
constant SYMBOL_CONTROL : std_logic_vector(1 downto 0) := "01";
constant SYMBOL_ERROR : std_logic_vector(1 downto 0) := "10";
constant SYMBOL_DATA : std_logic_vector(1 downto 0) := "11";
-- STYPE0 constants.
constant STYPE0_PACKET_ACCEPTED : std_logic_vector(2 downto 0) := "000";
constant STYPE0_PACKET_RETRY : std_logic_vector(2 downto 0) := "001";
constant STYPE0_PACKET_NOT_ACCEPTED : std_logic_vector(2 downto 0) := "010";
constant STYPE0_RESERVED : std_logic_vector(2 downto 0) := "011";
constant STYPE0_STATUS : std_logic_vector(2 downto 0) := "100";
constant STYPE0_VC_STATUS : std_logic_vector(2 downto 0) := "101";
constant STYPE0_LINK_RESPONSE : std_logic_vector(2 downto 0) := "110";
constant STYPE0_IMPLEMENTATION_DEFINED : std_logic_vector(2 downto 0) := "111";
-- STYPE1 constants.
constant STYPE1_START_OF_PACKET : std_logic_vector(2 downto 0) := "000";
constant STYPE1_STOMP : std_logic_vector(2 downto 0) := "001";
constant STYPE1_END_OF_PACKET : std_logic_vector(2 downto 0) := "010";
constant STYPE1_RESTART_FROM_RETRY : std_logic_vector(2 downto 0) := "011";
constant STYPE1_LINK_REQUEST : std_logic_vector(2 downto 0) := "100";
constant STYPE1_MULTICAST_EVENT : std_logic_vector(2 downto 0) := "101";
constant STYPE1_RESERVED : std_logic_vector(2 downto 0) := "110";
constant STYPE1_NOP : std_logic_vector(2 downto 0) := "111";
-- FTYPE constants.
constant FTYPE_REQUEST_CLASS : std_logic_vector(3 downto 0) := "0010";
constant FTYPE_WRITE_CLASS : std_logic_vector(3 downto 0) := "0101";
constant FTYPE_STREAMING_WRITE_CLASS : std_logic_vector(3 downto 0) := "0110";
constant FTYPE_MAINTENANCE_CLASS : std_logic_vector(3 downto 0) := "1000";
constant FTYPE_RESPONSE_CLASS : std_logic_vector(3 downto 0) := "1101";
constant FTYPE_DOORBELL_CLASS : std_logic_vector(3 downto 0) := "1010";
constant FTYPE_MESSAGE_CLASS : std_logic_vector(3 downto 0) := "0010";
-- TTYPE Constants
constant TTYPE_MAINTENANCE_READ_REQUEST : std_logic_vector(3 downto 0) := "0000";
constant TTYPE_MAINTENANCE_WRITE_REQUEST : std_logic_vector(3 downto 0) := "0001";
constant TTYPE_MAINTENANCE_READ_RESPONSE : std_logic_vector(3 downto 0) := "0010";
constant TTYPE_MAINTENANCE_WRITE_RESPONSE : std_logic_vector(3 downto 0) := "0011";
constant TTYPE_NREAD_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
constant TTYPE_NWRITE_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
constant LINK_REQUEST_CMD_RESET_DEVICE : std_logic_vector(2 downto 0) := "011";
constant LINK_REQUEST_CMD_INPUT_STATUS : std_logic_vector(2 downto 0) := "100";
constant PACKET_NOT_ACCEPTED_CAUSE_UNEXPECTED_ACKID : std_logic_vector(4 downto 0) := "00001";
constant PACKET_NOT_ACCEPTED_CAUSE_CONTROL_CRC : std_logic_vector(4 downto 0) := "00010";
constant PACKET_NOT_ACCEPTED_CAUSE_NON_MAINTENANCE_STOPPED : std_logic_vector(4 downto 0) := "00011";
constant PACKET_NOT_ACCEPTED_CAUSE_PACKET_CRC : std_logic_vector(4 downto 0) := "00100";
constant PACKET_NOT_ACCEPTED_CAUSE_INVALID_CHARACTER : std_logic_vector(4 downto 0) := "00101";
constant PACKET_NOT_ACCEPTED_CAUSE_NO_RESOURCES : std_logic_vector(4 downto 0) := "00110";
constant PACKET_NOT_ACCEPTED_CAUSE_LOSS_DESCRAMBLER : std_logic_vector(4 downto 0) := "00111";
constant PACKET_NOT_ACCEPTED_CAUSE_GENERAL_ERROR : std_logic_vector(4 downto 0) := "11111";
-----------------------------------------------------------------------------
-- Types used in simulations.
-----------------------------------------------------------------------------
type ByteArray is array (natural range <>) of
std_logic_vector(7 downto 0);
type HalfwordArray is array (natural range <>) of
std_logic_vector(15 downto 0);
type WordArray is array (natural range <>) of
std_logic_vector(31 downto 0);
type DoublewordArray is array (natural range <>) of
std_logic_vector(63 downto 0);
-- Type defining a RapidIO frame.
type RioFrame is record
length : natural range 0 to 69;
payload : WordArray(0 to 68);
end record;
type RioFrameArray is array (natural range <>) of RioFrame;
-- Type defining a RapidIO payload.
type RioPayload is record
length : natural range 0 to 133;
data : HalfwordArray(0 to 132);
end record;
-----------------------------------------------------------------------------
-- Crc5 calculation function.
-- ITU, polynom=0x15.
-----------------------------------------------------------------------------
function Crc5(constant data : in std_logic_vector(18 downto 0);
constant crc : in std_logic_vector(4 downto 0))
return std_logic_vector;
---------------------------------------------------------------------------
-- Create a RapidIO physical layer control symbol.
---------------------------------------------------------------------------
function RioControlSymbolCreate(
constant stype0 : in std_logic_vector(2 downto 0);
constant parameter0 : in std_logic_vector(4 downto 0);
constant parameter1 : in std_logic_vector(4 downto 0);
constant stype1 : in std_logic_vector(2 downto 0);
constant cmd : in std_logic_vector(2 downto 0))
return std_logic_vector;
-----------------------------------------------------------------------------
-- Crc16 calculation function.
-- CITT, polynom=0x1021.
-----------------------------------------------------------------------------
function Crc16(constant data : in std_logic_vector(15 downto 0);
constant crc : in std_logic_vector(15 downto 0))
return std_logic_vector;
---------------------------------------------------------------------------
-- Create a randomly initialized data array.
---------------------------------------------------------------------------
procedure CreateRandomPayload(
variable payload : out HalfwordArray(0 to 132);
variable seed1 : inout positive;
variable seed2 : inout positive);
procedure CreateRandomPayload(
variable payload : out DoublewordArray(0 to 31);
variable seed1 : inout positive;
variable seed2 : inout positive);
---------------------------------------------------------------------------
-- Create a generic RapidIO frame.
---------------------------------------------------------------------------
function RioFrameCreate(
constant ackId : in std_logic_vector(4 downto 0);
constant vc : in std_logic;
constant crf : in std_logic;
constant prio : in std_logic_vector(1 downto 0);
constant tt : in std_logic_vector(1 downto 0);
constant ftype : in std_logic_vector(3 downto 0);
constant sourceId : in std_logic_vector(15 downto 0);
constant destId : in std_logic_vector(15 downto 0);
constant payload : in RioPayload)
return RioFrame;
---------------------------------------------------------------------------
-- Create a NWRITE RapidIO frame.
---------------------------------------------------------------------------
function RioNwrite(
constant wrsize : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant address : in std_logic_vector(28 downto 0);
constant wdptr : in std_logic;
constant xamsbs : in std_logic_vector(1 downto 0);
constant dataLength : in natural range 1 to 32;
constant data : in DoublewordArray(0 to 31))
return RioPayload;
---------------------------------------------------------------------------
-- Create a NREAD RapidIO frame.
---------------------------------------------------------------------------
function RioNread(
constant rdsize : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant address : in std_logic_vector(28 downto 0);
constant wdptr : in std_logic;
constant xamsbs : in std_logic_vector(1 downto 0))
return RioPayload;
---------------------------------------------------------------------------
-- Create a RESPONSE RapidIO frame.
---------------------------------------------------------------------------
function RioResponse(
constant status : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant dataLength : in natural range 0 to 32;
constant data : in DoublewordArray(0 to 31))
return RioPayload;
---------------------------------------------------------------------------
-- Create a Maintenance RapidIO frame.
---------------------------------------------------------------------------
function RioMaintenance(
constant transaction : in std_logic_vector(3 downto 0);
constant size : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant hopCount : in std_logic_vector(7 downto 0);
constant configOffset : in std_logic_vector(20 downto 0);
constant wdptr : in std_logic;
constant dataLength : in natural range 0 to 8;
constant data : in DoublewordArray(0 to 7))
return RioPayload;
-----------------------------------------------------------------------------
-- Function to convert a std_logic_vector to a string.
-----------------------------------------------------------------------------
function byteToString(constant byte : std_logic_vector(7 downto 0))
return string;
---------------------------------------------------------------------------
-- Procedure to print to report file and output
---------------------------------------------------------------------------
procedure PrintR( constant str : string );
---------------------------------------------------------------------------
-- Procedure to print to spec file
---------------------------------------------------------------------------
procedure PrintS( constant str : string );
---------------------------------------------------------------------------
-- Procedure to Assert Expression
---------------------------------------------------------------------------
procedure AssertE( constant exp: boolean; constant str : string );
---------------------------------------------------------------------------
-- Procedure to Print Error
---------------------------------------------------------------------------
procedure PrintE( constant str : string );
---------------------------------------------------------------------------
-- Procedure to end a test.
---------------------------------------------------------------------------
procedure TestEnd;
end package;
-------------------------------------------------------------------------------
-- RioCommon package body description.
-------------------------------------------------------------------------------
package body rio_common is
-----------------------------------------------------------------------------
-- Crc5 calculation function.
-- ITU, polynom=0x15.
-----------------------------------------------------------------------------
function Crc5(constant data : in std_logic_vector(18 downto 0);
constant crc : in std_logic_vector(4 downto 0))
return std_logic_vector is
type crcTableType is array (0 to 31) of std_logic_vector(7 downto 0);
constant crcTable : crcTableType := (
x"00", x"15", x"1f", x"0a", x"0b", x"1e", x"14", x"01",
x"16", x"03", x"09", x"1c", x"1d", x"08", x"02", x"17",
x"19", x"0c", x"06", x"13", x"12", x"07", x"0d", x"18",
x"0f", x"1a", x"10", x"05", x"04", x"11", x"1b", x"0e" );
variable index : natural range 0 to 31;
variable result : std_logic_vector(4 downto 0);
begin
result := crc;
index := to_integer(unsigned(data(18 downto 14) xor result));
result := crcTable(index)(4 downto 0);
index := to_integer(unsigned(data(13 downto 9) xor result));
result := crcTable(index)(4 downto 0);
index := to_integer(unsigned(data(8 downto 4) xor result));
result := crcTable(index)(4 downto 0);
index := to_integer(unsigned((data(3 downto 0) & '0') xor result));
return crcTable(index)(4 downto 0);
end Crc5;
---------------------------------------------------------------------------
-- Create a RapidIO physical layer control symbol.
---------------------------------------------------------------------------
function RioControlSymbolCreate(
constant stype0 : in std_logic_vector(2 downto 0);
constant parameter0 : in std_logic_vector(4 downto 0);
constant parameter1 : in std_logic_vector(4 downto 0);
constant stype1 : in std_logic_vector(2 downto 0);
constant cmd : in std_logic_vector(2 downto 0))
return std_logic_vector is
variable returnValue : std_logic_vector(31 downto 0);
variable symbolData : std_logic_vector(18 downto 0);
begin
symbolData(18 downto 16) := stype0;
symbolData(15 downto 11) := parameter0;
symbolData(10 downto 6) := parameter1;
symbolData(5 downto 3) := stype1;
symbolData(2 downto 0) := cmd;
returnValue(31 downto 13) := symbolData;
returnValue(12 downto 8) := Crc5(symbolData, "11111");
returnValue(7 downto 0) := x"00";
return returnValue;
end function;
-----------------------------------------------------------------------------
-- Crc16 calculation function.
-- CITT, polynom=0x1021.
-----------------------------------------------------------------------------
function Crc16(constant data : in std_logic_vector(15 downto 0);
constant crc : in std_logic_vector(15 downto 0))
return std_logic_vector is
type crcTableType is array (0 to 255) of std_logic_vector(15 downto 0);
constant crcTable : crcTableType := (
x"0000", x"1021", x"2042", x"3063", x"4084", x"50a5", x"60c6", x"70e7",
x"8108", x"9129", x"a14a", x"b16b", x"c18c", x"d1ad", x"e1ce", x"f1ef",
x"1231", x"0210", x"3273", x"2252", x"52b5", x"4294", x"72f7", x"62d6",
x"9339", x"8318", x"b37b", x"a35a", x"d3bd", x"c39c", x"f3ff", x"e3de",
x"2462", x"3443", x"0420", x"1401", x"64e6", x"74c7", x"44a4", x"5485",
x"a56a", x"b54b", x"8528", x"9509", x"e5ee", x"f5cf", x"c5ac", x"d58d",
x"3653", x"2672", x"1611", x"0630", x"76d7", x"66f6", x"5695", x"46b4",
x"b75b", x"a77a", x"9719", x"8738", x"f7df", x"e7fe", x"d79d", x"c7bc",
x"48c4", x"58e5", x"6886", x"78a7", x"0840", x"1861", x"2802", x"3823",
x"c9cc", x"d9ed", x"e98e", x"f9af", x"8948", x"9969", x"a90a", x"b92b",
x"5af5", x"4ad4", x"7ab7", x"6a96", x"1a71", x"0a50", x"3a33", x"2a12",
x"dbfd", x"cbdc", x"fbbf", x"eb9e", x"9b79", x"8b58", x"bb3b", x"ab1a",
x"6ca6", x"7c87", x"4ce4", x"5cc5", x"2c22", x"3c03", x"0c60", x"1c41",
x"edae", x"fd8f", x"cdec", x"ddcd", x"ad2a", x"bd0b", x"8d68", x"9d49",
x"7e97", x"6eb6", x"5ed5", x"4ef4", x"3e13", x"2e32", x"1e51", x"0e70",
x"ff9f", x"efbe", x"dfdd", x"cffc", x"bf1b", x"af3a", x"9f59", x"8f78",
x"9188", x"81a9", x"b1ca", x"a1eb", x"d10c", x"c12d", x"f14e", x"e16f",
x"1080", x"00a1", x"30c2", x"20e3", x"5004", x"4025", x"7046", x"6067",
x"83b9", x"9398", x"a3fb", x"b3da", x"c33d", x"d31c", x"e37f", x"f35e",
x"02b1", x"1290", x"22f3", x"32d2", x"4235", x"5214", x"6277", x"7256",
x"b5ea", x"a5cb", x"95a8", x"8589", x"f56e", x"e54f", x"d52c", x"c50d",
x"34e2", x"24c3", x"14a0", x"0481", x"7466", x"6447", x"5424", x"4405",
x"a7db", x"b7fa", x"8799", x"97b8", x"e75f", x"f77e", x"c71d", x"d73c",
x"26d3", x"36f2", x"0691", x"16b0", x"6657", x"7676", x"4615", x"5634",
x"d94c", x"c96d", x"f90e", x"e92f", x"99c8", x"89e9", x"b98a", x"a9ab",
x"5844", x"4865", x"7806", x"6827", x"18c0", x"08e1", x"3882", x"28a3",
x"cb7d", x"db5c", x"eb3f", x"fb1e", x"8bf9", x"9bd8", x"abbb", x"bb9a",
x"4a75", x"5a54", x"6a37", x"7a16", x"0af1", x"1ad0", x"2ab3", x"3a92",
x"fd2e", x"ed0f", x"dd6c", x"cd4d", x"bdaa", x"ad8b", x"9de8", x"8dc9",
x"7c26", x"6c07", x"5c64", x"4c45", x"3ca2", x"2c83", x"1ce0", x"0cc1",
x"ef1f", x"ff3e", x"cf5d", x"df7c", x"af9b", x"bfba", x"8fd9", x"9ff8",
x"6e17", x"7e36", x"4e55", x"5e74", x"2e93", x"3eb2", x"0ed1", x"1ef0" );
variable index : natural range 0 to 255;
variable result : std_logic_vector(15 downto 0);
begin
result := crc;
index := to_integer(unsigned(data(15 downto 8) xor result(15 downto 8)));
result := crcTable(index) xor (result(7 downto 0) & x"00");
index := to_integer(unsigned(data(7 downto 0) xor result(15 downto 8)));
result := crcTable(index) xor (result(7 downto 0) & x"00");
return result;
end Crc16;
---------------------------------------------------------------------------
-- Create a randomly initialized data array.
---------------------------------------------------------------------------
procedure CreateRandomPayload(
variable payload : out HalfwordArray(0 to 132);
variable seed1 : inout positive;
variable seed2 : inout positive) is
variable rand: real;
variable int_rand: integer;
variable stim: std_logic_vector(7 downto 0);
begin
for i in payload'range loop
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
end loop;
end procedure;
procedure CreateRandomPayload(
variable payload : out DoublewordArray(0 to 31);
variable seed1 : inout positive;
variable seed2 : inout positive) is
variable rand: real;
variable int_rand: integer;
variable stim: std_logic_vector(7 downto 0);
begin
for i in payload'range loop
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(23 downto 16) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(31 downto 24) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(39 downto 32) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(47 downto 40) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(55 downto 48) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(63 downto 56) := std_logic_vector(to_unsigned(int_rand, 8));
end loop;
end procedure;
---------------------------------------------------------------------------
-- Create a generic RapidIO frame.
---------------------------------------------------------------------------
function RioFrameCreate(
constant ackId : in std_logic_vector(4 downto 0);
constant vc : in std_logic;
constant crf : in std_logic;
constant prio : in std_logic_vector(1 downto 0);
constant tt : in std_logic_vector(1 downto 0);
constant ftype : in std_logic_vector(3 downto 0);
constant sourceId : in std_logic_vector(15 downto 0);
constant destId : in std_logic_vector(15 downto 0);
constant payload : in RioPayload) return RioFrame is
variable frame : RioFrame;
variable result : HalfwordArray(0 to 137);
variable crc : std_logic_vector(15 downto 0) := x"ffff";
begin
-- Add the header and addresses.
result(0) := ackId & "0" & vc & crf & prio & tt & ftype;
result(1) := destId;
result(2) := sourceId;
-- Update the calculated CRC with the header contents.
crc := Crc16("00000" & result(0)(10 downto 0), crc);
crc := Crc16(result(1), crc);
crc := Crc16(result(2), crc);
-- Check if a single CRC should be added or two.
if (payload.length <= 37) then
-- Single CRC.
for i in 0 to payload.length-1 loop
result(i+3) := payload.data(i);
crc := Crc16(payload.data(i), crc);
end loop;
result(payload.length+3) := crc;
-- Check if paddning is needed to make the payload even 32-bit.
if ((payload.length mod 2) = 1) then
result(payload.length+4) := x"0000";
frame.length := (payload.length+5) / 2;
else
frame.length := (payload.length+4) / 2;
end if;
else
-- Double CRC.
for i in 0 to 36 loop
result(i+3) := payload.data(i);
crc := Crc16(payload.data(i), crc);
end loop;
-- Add in-the-middle crc.
result(40) := crc;
crc := Crc16(crc, crc);
for i in 37 to payload.length-1 loop
result(i+4) := payload.data(i);
crc := Crc16(payload.data(i), crc);
end loop;
result(payload.length+4) := crc;
-- Check if paddning is needed to make the payload even 32-bit.
if ((payload.length mod 2) = 0) then
result(payload.length+5) := x"0000";
frame.length := (payload.length+6) / 2;
else
frame.length := (payload.length+5) / 2;
end if;
end if;
-- Update the result length.
for i in 0 to frame.length-1 loop
frame.payload(i) := result(2*i) & result(2*i+1);
end loop;
return frame;
end function;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
function RioNwrite(
constant wrsize : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant address : in std_logic_vector(28 downto 0);
constant wdptr : in std_logic;
constant xamsbs : in std_logic_vector(1 downto 0);
constant dataLength : in natural range 1 to 32;
constant data : in DoublewordArray(0 to 31))
return RioPayload is
variable payload : RioPayload;
begin
payload.data(0)(15 downto 12) := "0100";
payload.data(0)(11 downto 8) := wrsize;
payload.data(0)(7 downto 0) := tid;
payload.data(1) := address(28 downto 13);
payload.data(2)(15 downto 3) := address(12 downto 0);
payload.data(2)(2) := wdptr;
payload.data(2)(1 downto 0) := xamsbs;
for i in 0 to dataLength-1 loop
payload.data(3+4*i) := data(i)(63 downto 48);
payload.data(4+4*i) := data(i)(47 downto 32);
payload.data(5+4*i) := data(i)(31 downto 16);
payload.data(6+4*i) := data(i)(15 downto 0);
end loop;
payload.length := 3 + 4*dataLength;
return payload;
end function;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
function RioNread(
constant rdsize : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant address : in std_logic_vector(28 downto 0);
constant wdptr : in std_logic;
constant xamsbs : in std_logic_vector(1 downto 0))
return RioPayload is
variable payload : RioPayload;
begin
payload.data(0)(15 downto 12) := "0100";
payload.data(0)(11 downto 8) := rdsize;
payload.data(0)(7 downto 0) := tid;
payload.data(1) := address(28 downto 13);
payload.data(2)(15 downto 3) := address(12 downto 0);
payload.data(2)(2) := wdptr;
payload.data(2)(1 downto 0) := xamsbs;
payload.length := 3;
return payload;
end function;
---------------------------------------------------------------------------
-- Create a RESPONSE RapidIO frame.
---------------------------------------------------------------------------
function RioResponse(
constant status : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant dataLength : in natural range 0 to 32;
constant data : in DoublewordArray(0 to 31))
return RioPayload is
variable payload : RioPayload;
begin
payload.data(0)(11 downto 8) := status;
payload.data(0)(7 downto 0) := tid;
if (dataLength = 0) then
payload.data(0)(15 downto 12) := "0000";
payload.length := 1;
else
payload.data(0)(15 downto 12) := "1000";
for i in 0 to dataLength-1 loop
payload.data(1+4*i) := data(i)(63 downto 48);
payload.data(2+4*i) := data(i)(47 downto 32);
payload.data(3+4*i) := data(i)(31 downto 16);
payload.data(4+4*i) := data(i)(15 downto 0);
end loop;
payload.length := 1 + 4*dataLength;
end if;
return payload;
end function;
---------------------------------------------------------------------------
-- Create a Maintenance RapidIO frame.
---------------------------------------------------------------------------
function RioMaintenance(
constant transaction : in std_logic_vector(3 downto 0);
constant size : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant hopCount : in std_logic_vector(7 downto 0);
constant configOffset : in std_logic_vector(20 downto 0);
constant wdptr : in std_logic;
constant dataLength : in natural range 0 to 8;
constant data : in DoublewordArray(0 to 7))
return RioPayload is
variable payload : RioPayload;
begin
payload.data(0)(15 downto 12) := transaction;
payload.data(0)(11 downto 8) := size;
payload.data(0)(7 downto 0) := tid;
payload.data(1)(15 downto 8) := hopCount;
payload.data(1)(7 downto 0) := configOffset(20 downto 13);
payload.data(2)(15 downto 3) := configOffset(12 downto 0);
payload.data(2)(2) := wdptr;
payload.data(2)(1 downto 0) := "00";
if (dataLength = 0) then
payload.length := 3;
else
for i in 0 to dataLength-1 loop
payload.data(3+4*i) := data(i)(63 downto 48);
payload.data(4+4*i) := data(i)(47 downto 32);
payload.data(5+4*i) := data(i)(31 downto 16);
payload.data(6+4*i) := data(i)(15 downto 0);
end loop;
payload.length := 3 + 4*dataLength;
end if;
return payload;
end function;
-----------------------------------------------------------------------------
-- Function to convert a std_logic_vector to a string.
-----------------------------------------------------------------------------
function byteToString(constant byte : std_logic_vector(7 downto 0))
return string is
constant table : string(1 to 16) := "0123456789abcdef";
variable returnValue : string(1 to 2);
begin
returnValue(1) := table(to_integer(unsigned(byte(7 downto 4))) + 1);
returnValue(2) := table(to_integer(unsigned(byte(3 downto 0))) + 1);
return returnValue;
end function;
---------------------------------------------------------------------------
-- Procedure to print test report
---------------------------------------------------------------------------
procedure PrintR( constant str : string ) is
file reportFile : text;
variable reportLine, outputLine : line;
variable fStatus: FILE_OPEN_STATUS;
begin
--Write report note to wave/transcript window
report str severity NOTE;
end PrintR;
---------------------------------------------------------------------------
-- Procedure to print test spec
---------------------------------------------------------------------------
procedure PrintS( constant str : string ) is
file specFile : text;
variable specLine, outputLine : line;
variable fStatus: FILE_OPEN_STATUS;
begin
--Write to spec file
file_open(fStatus, specFile, "testspec.txt", append_mode);
write(specLine, string'(str));
writeline (specFile, specLine);
file_close(specFile);
end PrintS;
---------------------------------------------------------------------------
-- Procedure to Assert Expression
---------------------------------------------------------------------------
procedure AssertE( constant exp: boolean; constant str : string ) is
file reportFile : text;
variable reportLine, outputLine : line;
variable fStatus: FILE_OPEN_STATUS;
begin
if (not exp) then
--Write to STD_OUTPUT
report(str) severity error;
else
PrintR("Status: Passed");
PrintS("Status: Passed");
end if;
end AssertE;
---------------------------------------------------------------------------
-- Procedure to Print Error
---------------------------------------------------------------------------
procedure PrintE( constant str : string ) is
file reportFile : text;
variable reportLine, outputLine : line;
variable fStatus: FILE_OPEN_STATUS;
begin
--Write to STD_OUTPUT
report str severity error;
end PrintE;
---------------------------------------------------------------------------
-- Procedure to end a test.
---------------------------------------------------------------------------
procedure TestEnd is
begin
assert false report "Test complete." severity failure;
wait;
end TestEnd;
end rio_common;
-------------------------------------------------------------------------------
-- Crc16CITT
-- A CRC-16 calculator following the implementation proposed in the 2.2
-- standard.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Entity for Crc16CITT.
-------------------------------------------------------------------------------
entity Crc16CITT is
port(
d_i : in std_logic_vector(15 downto 0);
crc_i : in std_logic_vector(15 downto 0);
crc_o : out std_logic_vector(15 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for Crc16CITT.
-------------------------------------------------------------------------------
architecture Crc16Impl of Crc16CITT is
signal d : std_logic_vector(0 to 15);
signal c : std_logic_vector(0 to 15);
signal e : std_logic_vector(0 to 15);
signal cc : std_logic_vector(0 to 15);
begin
-- Reverse the bit vector indexes to make them the same as in the standard.
d(15) <= d_i(0); d(14) <= d_i(1); d(13) <= d_i(2); d(12) <= d_i(3);
d(11) <= d_i(4); d(10) <= d_i(5); d(9) <= d_i(6); d(8) <= d_i(7);
d(7) <= d_i(8); d(6) <= d_i(9); d(5) <= d_i(10); d(4) <= d_i(11);
d(3) <= d_i(12); d(2) <= d_i(13); d(1) <= d_i(14); d(0) <= d_i(15);
-- Reverse the bit vector indexes to make them the same as in the standard.
c(15) <= crc_i(0); c(14) <= crc_i(1); c(13) <= crc_i(2); c(12) <= crc_i(3);
c(11) <= crc_i(4); c(10) <= crc_i(5); c(9) <= crc_i(6); c(8) <= crc_i(7);
c(7) <= crc_i(8); c(6) <= crc_i(9); c(5) <= crc_i(10); c(4) <= crc_i(11);
c(3) <= crc_i(12); c(2) <= crc_i(13); c(1) <= crc_i(14); c(0) <= crc_i(15);
-- Calculate the resulting crc.
e <= c xor d;
cc(0) <= e(4) xor e(5) xor e(8) xor e(12);
cc(1) <= e(5) xor e(6) xor e(9) xor e(13);
cc(2) <= e(6) xor e(7) xor e(10) xor e(14);
cc(3) <= e(0) xor e(7) xor e(8) xor e(11) xor e(15);
cc(4) <= e(0) xor e(1) xor e(4) xor e(5) xor e(9);
cc(5) <= e(1) xor e(2) xor e(5) xor e(6) xor e(10);
cc(6) <= e(0) xor e(2) xor e(3) xor e(6) xor e(7) xor e(11);
cc(7) <= e(0) xor e(1) xor e(3) xor e(4) xor e(7) xor e(8) xor e(12);
cc(8) <= e(0) xor e(1) xor e(2) xor e(4) xor e(5) xor e(8) xor e(9) xor e(13);
cc(9) <= e(1) xor e(2) xor e(3) xor e(5) xor e(6) xor e(9) xor e(10) xor e(14);
cc(10) <= e(2) xor e(3) xor e(4) xor e(6) xor e(7) xor e(10) xor e(11) xor e(15);
cc(11) <= e(0) xor e(3) xor e(7) xor e(11);
cc(12) <= e(0) xor e(1) xor e(4) xor e(8) xor e(12);
cc(13) <= e(1) xor e(2) xor e(5) xor e(9) xor e(13);
cc(14) <= e(2) xor e(3) xor e(6) xor e(10) xor e(14);
cc(15) <= e(3) xor e(4) xor e(7) xor e(11) xor e(15);
-- Reverse the bit vector indexes to make them the same as in the standard.
crc_o(15) <= cc(0); crc_o(14) <= cc(1); crc_o(13) <= cc(2); crc_o(12) <= cc(3);
crc_o(11) <= cc(4); crc_o(10) <= cc(5); crc_o(9) <= cc(6); crc_o(8) <= cc(7);
crc_o(7) <= cc(8); crc_o(6) <= cc(9); crc_o(5) <= cc(10); crc_o(4) <= cc(11);
crc_o(3) <= cc(12); crc_o(2) <= cc(13); crc_o(1) <= cc(14); crc_o(0) <= cc(15);
end architecture;
-------------------------------------------------------------------------------
-- MemoryDualPort
-- Generic synchronous memory with one read/write port and one read port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for MemoryDualPort.
-------------------------------------------------------------------------------
entity MemoryDualPort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
writeEnableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
clkB_i : in std_logic;
enableB_i : in std_logic;
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for MemoryDualPort.
-------------------------------------------------------------------------------
architecture MemoryDualPortImpl of MemoryDualPort is
type MemoryType is array (natural range <>) of
std_logic_vector(DATA_WIDTH-1 downto 0);
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
begin
process(clkA_i)
begin
if (clkA_i'event and clkA_i = '1') then
if (enableA_i = '1') then
if (writeEnableA_i = '1') then
memory(to_integer(unsigned(addressA_i))) <= dataA_i;
end if;
dataA_o <= memory(to_integer(unsigned(addressA_i)));
end if;
end if;
end process;
process(clkB_i)
begin
if (clkB_i'event and clkB_i = '1') then
if (enableB_i = '1') then
dataB_o <= memory(to_integer(unsigned(addressB_i)));
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
-- MemorySimpleDualPort
-- Generic synchronous memory with one write port and one read port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for MemorySimpleDualPort.
-------------------------------------------------------------------------------
entity MemorySimpleDualPort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
clkB_i : in std_logic;
enableB_i : in std_logic;
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for MemorySimpleDualPort.
-------------------------------------------------------------------------------
architecture MemorySimpleDualPortImpl of MemorySimpleDualPort is
type MemoryType is array (natural range <>) of
std_logic_vector(DATA_WIDTH-1 downto 0);
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
begin
process(clkA_i)
begin
if (clkA_i'event and clkA_i = '1') then
if (enableA_i = '1') then
memory(to_integer(unsigned(addressA_i))) <= dataA_i;
end if;
end if;
end process;
process(clkB_i)
begin
if (clkB_i'event and clkB_i = '1') then
if (enableB_i = '1') then
dataB_o <= memory(to_integer(unsigned(addressB_i)));
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
-- MemorySinglePort
-- Generic synchronous memory with one read/write port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for MemorySinglePort.
-------------------------------------------------------------------------------
entity MemorySinglePort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clk_i : in std_logic;
enable_i : in std_logic;
writeEnable_i : in std_logic;
address_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for MemorySinglePort.
-------------------------------------------------------------------------------
architecture MemorySinglePortImpl of MemorySinglePort is
type MemoryType is array (natural range <>) of
std_logic_vector(DATA_WIDTH-1 downto 0);
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (enable_i = '1') then
if (writeEnable_i = '1') then
memory(to_integer(unsigned(address_i))) <= data_i;
end if;
data_o <= memory(to_integer(unsigned(address_i)));
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
-- MemorySimpleDualPortAsync
-- Generic memory with one synchronous write port and one asynchronous read port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for MemorySimpleDualPortAsync.
-------------------------------------------------------------------------------
entity MemorySimpleDualPortAsync is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1;
INIT_VALUE : std_logic := 'U');
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for MemorySimpleDualPortAsync.
-------------------------------------------------------------------------------
architecture MemorySimpleDualPortAsyncImpl of MemorySimpleDualPortAsync is
type MemoryType is array (natural range <>) of
std_logic_vector(DATA_WIDTH-1 downto 0);
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1) := (others=>(others=>INIT_VALUE));
begin
process(clkA_i)
begin
if (clkA_i'event and clkA_i = '1') then
if (enableA_i = '1') then
memory(to_integer(unsigned(addressA_i))) <= dataA_i;
end if;
end if;
end process;
dataB_o <= memory(to_integer(unsigned(addressB_i)));
end architecture;
-------------------------------------------------------------------------------
-- RioFifo1
-- Simple fifo which is one entry deep.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Entity for RioFifo1.
-------------------------------------------------------------------------------
entity RioFifo1 is
generic(
WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
empty_o : out std_logic;
read_i : in std_logic;
data_o : out std_logic_vector(WIDTH-1 downto 0);
full_o : out std_logic;
write_i : in std_logic;
data_i : in std_logic_vector(WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for RioFifo1.
-------------------------------------------------------------------------------
architecture RioFifo1Impl of RioFifo1 is
signal empty : std_logic;
signal full : std_logic;
begin
empty_o <= empty;
full_o <= full;
process(areset_n, clk)
begin
if (areset_n = '0') then
empty <= '1';
full <= '0';
data_o <= (others => '0');
elsif (clk'event and clk = '1') then
if (empty = '1') then
if (write_i = '1') then
empty <= '0';
full <= '1';
data_o <= data_i;
end if;
else
if (read_i = '1') then
empty <= '1';
full <= '0';
end if;
end if;
end if;
end process;
end architecture;
| bsd-3-clause | 4577668e583ea612dc9be1645f515cd1 | 0.513699 | 3.861508 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/K7SerialInterfaceIn.vhd | 1 | 6,587 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
library UNISIM;
use UNISIM.VComponents.all;
entity K7SerialInterfaceIn is
Generic (
GATE_DELAY_G : time := 1 ns;
BITSLIP_WAIT_G : integer := 25*8
);
Port (
-- Parallel clock and reset
sstClk : in sl;
sstRst : in sl := '0';
-- Aligned indicator
aligned : in sl;
-- Parallel data out
dataOut : out slv(9 downto 0);
-- Serial clock in
sstX5Clk : in sl;
sstX5Rst : in sl := '0';
-- Serial data in
dataIn : in sl
);
end K7SerialInterfaceIn;
architecture Behavioral of K7SerialInterfaceIn is
type StateType is (RESET_S, READ_WORD_S, BITSLIP_S);
type RegType is record
state : StateType;
dataWord : slv(9 downto 0);
dataWrite : sl;
bitCount : slv(3 downto 0);
slipCount : slv(15 downto 0);
flip : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => RESET_S,
dataWord => (others => '0'),
dataWrite => '0',
bitCount => (others => '0'),
slipCount => (others => '0'),
flip => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal serialDataInRising : sl;
signal serialDataInFalling : sl;
signal risingWord : slv(4 downto 0);
signal fallingWord : slv(4 downto 0);
signal dataWord : slv(9 downto 0);
signal dataWordFlipped : slv(9 downto 0);
signal fifoEmpty : sl;
signal fifoFull : sl;
begin
-- IDDR to grab the serial data
-- Template here: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf
-- Documentation here: http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
IDDR_inst : IDDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED", -- "OPPOSITE_EDGE",
-- "SAME_EDGE"
-- or "SAME_EDGE_PIPELINED"
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
SRTYPE => "SYNC" -- Set/Reset type: "SYNC" or "ASYNC"
)
port map (
Q1 => serialDataInRising, -- 1-bit output for positive edge of clock
Q2 => serialDataInFalling, -- 1-bit output for negative edge of clock
C => sstX5Clk, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D => dataIn, -- 1-bit DDR data input
R => '0', -- 1-bit reset
S => '0' -- 1-bit set
);
-- Shift register for the rising and falling words
process(sstX5Clk) begin
if rising_edge(sstX5Clk) then
if sstX5Rst = '1' then
risingWord <= (others => '0');
fallingWord <= (others => '0');
else
risingWord(0) <= serialDataInRising;
fallingWord(0) <= serialDataInFalling;
for i in 1 to risingWord'left loop
risingWord(i) <= risingWord(i-1);
fallingWord(i) <= fallingWord(i-1);
end loop;
end if;
end if;
end process;
-- Create data word and flipped data word
process(sstX5Clk) begin
if rising_edge(sstX5Clk) then
for i in 0 to risingWord'left loop
dataWord(i*2) <= risingWord(i);
dataWord(i*2+1) <= fallingWord(i);
dataWordFlipped(i*2) <= fallingWord(i);
dataWordFlipped(i*2+1) <= risingWord(i);
end loop;
end if;
end process;
-- State machine to grab 10 bits and write them into a FIFO
-- Master state machine (combinatorial)
comb : process(r, serialDataInRising, serialDataInFalling,
aligned, dataWord,dataWordFlipped, sstX5Rst) is
variable v : RegType;
begin
v := r;
-- Resets for pulsed outputs
v.dataWrite := '0';
-- State machine
case(r.state) is
when RESET_S =>
v.bitCount := (others => '0');
v.flip := '0';
v.state := READ_WORD_S;
when READ_WORD_S =>
v.bitCount := r.bitCount + 2;
-- if r.flip = '0' then
-- v.dataWord(conv_integer(r.bitCount)) := serialDataInRising;
-- v.dataWord(conv_integer(r.bitCount+1)) := serialDataInFalling;
-- else
-- v.dataWord(conv_integer(r.bitCount+1)) := serialDataInRising;
-- v.dataWord(conv_integer(r.bitCount)) := serialDataInFalling;
-- end if;
if r.bitCount = 8 then
v.bitCount := (others => '0');
v.dataWrite := '1';
if r.flip = '0' then
v.dataWord := dataWord;
else
v.dataWord := dataWordFlipped;
end if;
if aligned = '0' then
if r.slipCount < BITSLIP_WAIT_G then
v.slipCount := r.slipCount + 1;
else
v.slipCount := (others => '0');
if r.flip = '0' then
v.flip := '1';
else
v.flip := '0';
v.state := BITSLIP_S;
end if;
end if;
end if;
end if;
when BITSLIP_S =>
v.bitCount := (others => '0');
v.state := READ_WORD_S;
when others =>
v.state := RESET_S;
end case;
-- Reset logic
if (sstX5Rst = '1') then
v := REG_INIT_C;
end if;
-- Assignment of combinatorial variable to signal
rin <= v;
end process;
-- Master state machine (sequential)
seq : process (sstX5Clk) is
begin
if (rising_edge(sstX5Clk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
-- Read FIFO out to the top level
U_SerializationFifo : entity work.SerializationFifo
PORT MAP (
rst => sstRst,
wr_clk => sstX5Clk,
rd_clk => sstClk,
din => r.dataWord,
wr_en => r.dataWrite,
rd_en => not(fifoEmpty),
dout => dataOut,
full => fifoFull,
empty => fifoEmpty,
valid => open
);
end Behavioral;
| lgpl-2.1 | 8de21990ddc23bc970d612f69096d9e1 | 0.503264 | 3.818551 | false | false | false | false |
Dragonturtle/SHERPA | HDL/FPGALink/fx2_interface.vhdl | 1 | 9,922 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fx2_interface is
port(
clk_in : in std_logic; -- 48MHz clock from FX2LP
reset_in : in std_logic; -- synchronous active-high reset input
reset_out : out std_logic; -- synchronous active-high reset output
-- FX2LP interface ---------------------------------------------------------------------------
fx2FifoSel_out : out std_logic; -- select FIFO: '0' for EP2OUT, '1' for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Channel read/write interface --------------------------------------------------------------
chanAddr_out : out std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
h2fData_out : out std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
h2fValid_out : out std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData_out"
h2fReady_in : in std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
f2hData_in : in std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
f2hValid_in : in std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
f2hReady_out : out std_logic -- '1' means "on the next clock rising edge, put your next byte of data on f2hData_in"
);
end entity;
architecture rtl of fx2_interface is
-- The read/write nomenclature here refers to the FPGA reading and writing the FX2LP FIFOs, and is therefore
-- of the opposite sense to the host's read and write. So host reads are fulfilled in the S_WRITE state, and
-- vice-versa. Apologies for the confusion.
type StateType is (
S_RESET, -- wait for gotData_in to go low when FX2LP enables FIFO mode
S_IDLE, -- wait for requst from host & register chanAddr & isWrite
S_GET_COUNT0, -- register most significant byte of message length
S_GET_COUNT1, -- register least significant byte of message length
S_BEGIN_WRITE, -- switch direction of FX2LP data bus
S_WRITE, -- write data to FX2LP EP6IN FIFO, one byte at a time
S_END_WRITE_ALIGNED, -- end an aligned write (do not assert fx2PktEnd_out)
S_END_WRITE_NONALIGNED, -- end a nonaligned write (assert fx2PktEnd_out)
S_READ -- read data from FX2LP EP2OUT FIFO, one byte at a time
);
constant FIFO_READ : std_logic_vector(1 downto 0) := "10"; -- assert fx2Read_out (active-low)
constant FIFO_WRITE : std_logic_vector(1 downto 0) := "01"; -- assert fx2Write_out (active-low)
constant FIFO_NOP : std_logic_vector(1 downto 0) := "11"; -- assert nothing
constant OUT_FIFO : std_logic := '0'; -- EP2OUT
constant IN_FIFO : std_logic := '1'; -- EP6IN
signal state, state_next : StateType := S_RESET;
signal fifoOp : std_logic_vector(1 downto 0) := "ZZ";
signal count, count_next : unsigned(16 downto 0) := (others => '0'); -- read/write count
signal chanAddr, chanAddr_next : std_logic_vector(6 downto 0) := (others => '0'); -- channel being accessed (0-127)
signal isWrite, isWrite_next : std_logic := '0'; -- is this FX2LP FIFO access a write or a read?
signal isAligned, isAligned_next : std_logic := '0'; -- is this FX2LP FIFO write block-aligned?
signal dataOut : std_logic_vector(7 downto 0); -- data to be driven on fx2Data_io
signal driveBus : std_logic := '0'; -- whether or not to drive fx2Data_io
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_RESET;
count <= (others => '0');
chanAddr <= (others => '0');
isWrite <= '0';
isAligned <= '0';
else
state <= state_next;
count <= count_next;
chanAddr <= chanAddr_next;
isWrite <= isWrite_next;
isAligned <= isAligned_next;
end if;
end if;
end process;
-- Next state logic
process(
state, fx2Data_io, fx2GotData_in, fx2GotRoom_in, count, isAligned, isWrite, chanAddr,
f2hData_in, f2hValid_in, h2fReady_in)
begin
state_next <= state;
count_next <= count;
chanAddr_next <= chanAddr;
isWrite_next <= isWrite; -- is the FPGA writing to the FX2LP?
isAligned_next <= isAligned; -- does this FIFO write end on a block (512-byte) boundary?
dataOut <= (others => '0');
driveBus <= '0'; -- don't drive fx2Data_io by default
fifoOp <= FIFO_READ; -- read the FX2LP FIFO by default
fx2PktEnd_out <= '1'; -- inactive: FPGA does not commit a short packet.
f2hReady_out <= '0';
h2fValid_out <= '0';
reset_out <= '0';
case state is
when S_GET_COUNT0 =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' ) then
-- The count high word high byte will be available on the next clock edge.
count_next(15 downto 8) <= unsigned(fx2Data_io);
state_next <= S_GET_COUNT1;
end if;
when S_GET_COUNT1 =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' ) then
-- The count high word low byte will be available on the next clock edge.
count_next(7 downto 0) <= unsigned(fx2Data_io);
if ( count(15 downto 8) = x"00" and fx2Data_io = x"00" ) then
count_next(16) <= '1';
else
count_next(16) <= '0';
end if;
if ( isWrite = '1' ) then
state_next <= S_BEGIN_WRITE;
else
state_next <= S_READ;
end if;
end if;
when S_BEGIN_WRITE =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
if ( count(8 downto 0) = "000000000" ) then
isAligned_next <= '1';
else
isAligned_next <= '0';
end if;
state_next <= S_WRITE;
when S_WRITE =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
if ( fx2GotRoom_in = '1' ) then
f2hReady_out <= '1';
end if;
if ( fx2GotRoom_in = '1' and f2hValid_in = '1' ) then
fifoOp <= FIFO_WRITE;
dataOut <= f2hData_in;
driveBus <= '1';
count_next <= count - 1;
if ( count = 1 ) then
if ( isAligned = '1' ) then
state_next <= S_END_WRITE_ALIGNED; -- don't assert fx2PktEnd
else
state_next <= S_END_WRITE_NONALIGNED; -- assert fx2PktEnd to commit small packet
end if;
end if;
else
fifoOp <= FIFO_NOP;
end if;
when S_END_WRITE_ALIGNED =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
state_next <= S_IDLE;
when S_END_WRITE_NONALIGNED =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
fx2PktEnd_out <= '0'; -- Active: FPGA commits the packet early.
state_next <= S_IDLE;
when S_READ =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' and h2fReady_in = '1') then
-- A data byte will be available on the next clock edge
h2fValid_out <= '1';
count_next <= count - 1;
if ( count = 1 ) then
state_next <= S_IDLE;
end if;
else
fifoOp <= FIFO_NOP;
end if;
-- S_RESET - tri-state everything
when S_RESET =>
reset_out <= '1';
driveBus <= '0';
fifoOp <= "ZZ";
fx2FifoSel_out <= 'Z';
fx2PktEnd_out <= 'Z';
if ( fx2GotData_in = '0' ) then
state_next <= S_IDLE;
end if;
-- S_IDLE and others
when others =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' ) then
-- The read/write flag and a seven-bit channel address will be available on the
-- next clock edge.
chanAddr_next <= fx2Data_io(6 downto 0);
isWrite_next <= fx2Data_io(7);
state_next <= S_GET_COUNT0;
end if;
end case;
end process;
-- Drive stateless signals
fx2Read_out <= fifoOp(0);
fx2Write_out <= fifoOp(1);
chanAddr_out <= chanAddr;
h2fData_out <= fx2Data_io;
fx2Data_io <= dataOut when driveBus = '1' else (others => 'Z');
end architecture;
| gpl-3.0 | 2166b15027f28f98a670e924dd255a94 | 0.583552 | 3.339616 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | 3e17d0bfd74c2b991f2d9c58fb64015f | 0.940168 | 1.860951 | false | false | false | false |
pkerling/ethernet_mac | xilinx/fixed_input_delay.vhd | 1 | 2,594 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Apply a fixed delay to an input pin using IODELAY2
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity fixed_input_delay is
generic(
IDELAY_VALUE : natural range 0 to 255 := 0
);
port(
pad_i : in std_ulogic;
delayed_o : out std_ulogic
);
end entity;
architecture spartan_6 of fixed_input_delay is
begin
mii_rx_dv_IODELAY2_inst : IODELAY2
generic map(
COUNTER_WRAPAROUND => "WRAPAROUND", -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
IDELAY_MODE => "NORMAL", -- "NORMAL" or "PCI"
IDELAY_TYPE => "FIXED", -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
-- or "DIFF_PHASE_DETECTOR"
IDELAY_VALUE => IDELAY_VALUE, -- Amount of taps for fixed input delay (0-255)
ODELAY_VALUE => 0, -- Amount of taps fixed output delay (0-255)
SERDES_MODE => "NONE", -- "NONE", "MASTER" or "SLAVE"
SIM_TAPDELAY_VALUE => 75 -- Per tap delay used for simulation in ps
)
port map(
BUSY => open, -- 1-bit output: Busy output after CAL
DATAOUT => delayed_o, -- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => open, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => open, -- 1-bit output: Delayed data output
TOUT => open, -- 1-bit output: Delayed 3-state output
CAL => '0', -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => '0', -- 1-bit input: Clock input
IDATAIN => pad_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
INC => '0', -- 1-bit input: Increment / decrement input
IOCLK0 => '0', -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
RST => '0', -- 1-bit input: Reset to zero or 1/2 of total delay period
T => '1' -- 1-bit input: 3-state input signal
);
end architecture;
| bsd-3-clause | 19d1ce452cc11b2dab741e2b273c5b18 | 0.587895 | 3.435762 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pwm/niosii/niosii_inst.vhd | 1 | 1,550 | component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_rxd : in std_logic := 'X'; -- rxd
uart_0_txd : out std_logic; -- txd
ip_pwm_dir : out std_logic_vector(1 downto 0); -- dir
ip_pwm_out : out std_logic_vector(1 downto 0) -- out
);
end component niosii;
u0 : component niosii
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export, -- pio_0_external_connection.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
uart_0_rxd => CONNECTED_TO_uart_0_rxd, -- uart_0.rxd
uart_0_txd => CONNECTED_TO_uart_0_txd, -- .txd
ip_pwm_dir => CONNECTED_TO_ip_pwm_dir, -- ip_pwm.dir
ip_pwm_out => CONNECTED_TO_ip_pwm_out -- .out
);
| mit | e647d2d44c02c4de2f1389853c02cab8 | 0.376774 | 4.155496 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/SyncBit.vhd | 1 | 4,587 | ---------------------------------------------------------------------------------
-- Title : 1-bit synchronizer
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : SyncBit.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Simple one-bit synchronizer.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
library unisim;
use unisim.vcomponents.all;
entity SyncBit is
generic (
SYNC_STAGES_G : integer := 2;
CLK_POL_G : sl := '1';
RST_POL_G : sl := '1';
INIT_STATE_G : sl := '0';
GATE_DELAY_G : time := 1 ns
);
port (
-- Clock and reset
clk : in sl;
rst : in sl := '0';
-- Incoming bit, asynchronous
asyncBit : in sl;
-- Outgoing bit, synced to clk
syncBit : out sl
);
end SyncBit;
-- Define architecture
architecture structural of SyncBit is
-- Internal Signals
signal data_sync1 : std_logic;
signal syncBitPipe : std_logic_vector(SYNC_STAGES_G-2 downto 0);
-- These attributes will stop Vivado translating the desired flip-flops into an
-- SRL based shift register.
attribute ASYNC_REG : string;
-- attribute ASYNC_REG of "G_RisingEdgeClock.cdc_reg1" : label is "TRUE";
-- attribute ASYNC_REG of "G_RisingEdgeClock.cdc_reg2" : label is "TRUE";
-- attribute ASYNC_REG of "G_FallingEdgeClock.cdc_reg1" : label is "TRUE";
-- attribute ASYNC_REG of "G_FallingEdgeClock.cdc_reg2" : label is "TRUE";
-- These attributes will stop timing errors being reported on the target flip-flop during back annotated SDF simulation.
-- Unfortunately this does not seem to fix timing errors in implementation.
-- To do this, modify the UCF to add something like:
--
attribute MSGON : string;
-- attribute MSGON of "G_RisingEdgeClock.cdc_reg1" : label is "FALSE";
-- attribute MSGON of "G_RisingEdgeClock.cdc_reg2" : label is "FALSE";
-- attribute MSGON of "G_FallingEdgeClock.cdc_reg1" : label is "FALSE";
-- attribute MSGON of "G_FallingEdgeClock.cdc_reg2" : label is "FALSE";
-- These attributes will stop XST translating the desired flip-flops into an
-- SRL based shift register.
attribute shreg_extract : string;
-- attribute shreg_extract of "G_RisingEdgeClock.cdc_reg1" : label is "no";
-- attribute shreg_extract of "G_RisingEdgeClock.cdc_reg2" : label is "no";
-- attribute shreg_extract of "G_FallingEdgeClock.cdc_reg1" : label is "no";
-- attribute shreg_extract of "G_FallingEdgeClock.cdc_reg2" : label is "no";
begin
G_RisingEdgeClock : if CLK_POL_G = '1' generate
cdc_reg1 : FDRE
generic map (
INIT => to_bit(INIT_STATE_G)
)
port map (
C => clk,
CE => '1',
R => rst,
D => asyncBit,
Q => data_sync1
);
cdc_reg2 : FDRE
generic map (
INIT => to_bit(INIT_STATE_G)
)
port map (
C => clk,
CE => '1',
R => rst,
D => data_sync1,
Q => syncBitPipe(0)
);
end generate;
G_FallingEdgeClock : if CLK_POL_G = '0' generate
cdc_reg1 : FDCE_1
generic map (
INIT => to_bit(INIT_STATE_G)
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => asyncBit,
Q => data_sync1
);
cdc_reg2 : FDCE_1
generic map (
INIT => to_bit(INIT_STATE_G)
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => data_sync1,
Q => syncBitPipe(0)
);
end generate;
G_SyncPipe : if SYNC_STAGES_G > 2 generate
process(clk) begin
if rising_edge(clk) then
if rst = '1' then
syncBitPipe(syncBitPipe'left downto 1) <= (others => INIT_STATE_G);
else
for i in syncBitPipe'left downto 1 loop
syncBitPipe(i) <= syncBitPipe(i-1);
end loop;
end if;
end if;
end process;
end generate;
syncBit <= syncBitPipe(syncBitPipe'left);
end structural;
| lgpl-2.1 | b3e226c7a292c15a1f0a3d4af6037d28 | 0.514716 | 3.923867 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/niosii/synthesis/submodules/altera_epcq_controller_core.vhd | 1 | 18,709 | -- altera_epcq_controller_core.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity altera_epcq_controller_core is
generic (
DEVICE_FAMILY : string := "Cyclone IV E";
ADDR_WIDTH : integer := 19;
ASMI_ADDR_WIDTH : integer := 24;
ASI_WIDTH : integer := 1;
CS_WIDTH : integer := 1;
CHIP_SELS : integer := 1;
ENABLE_4BYTE_ADDR : integer := 0
);
port (
clk : in std_logic := '0'; -- clock_sink.clk
reset_n : in std_logic := '0'; -- reset.reset_n
avl_csr_read : in std_logic := '0'; -- avl_csr.read
avl_csr_waitrequest : out std_logic; -- .waitrequest
avl_csr_write : in std_logic := '0'; -- .write
avl_csr_addr : in std_logic_vector(2 downto 0) := (others => '0'); -- .address
avl_csr_wrdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avl_csr_rddata : out std_logic_vector(31 downto 0); -- .readdata
avl_csr_rddata_valid : out std_logic; -- .readdatavalid
avl_mem_write : in std_logic := '0'; -- avl_mem.write
avl_mem_burstcount : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
avl_mem_waitrequest : out std_logic; -- .waitrequest
avl_mem_read : in std_logic := '0'; -- .read
avl_mem_addr : in std_logic_vector(18 downto 0) := (others => '0'); -- .address
avl_mem_wrdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avl_mem_rddata : out std_logic_vector(31 downto 0); -- .readdata
avl_mem_rddata_valid : out std_logic; -- .readdatavalid
avl_mem_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
asmi_status_out : in std_logic_vector(7 downto 0) := (others => '0'); -- asmi_status_out.conduit_status_out
asmi_epcs_id : in std_logic_vector(7 downto 0) := (others => '0'); -- asmi_epcs_id.conduit_epcs_id
asmi_illegal_erase : in std_logic := '0'; -- asmi_illegal_erase.conduit_illegal_erase
asmi_illegal_write : in std_logic := '0'; -- asmi_illegal_write.conduit_illegal_write
ddasi_dataoe : in std_logic_vector(0 downto 0) := (others => '0'); -- ddasi_dataoe.conduit_ddasi_dataoe
ddasi_dclk : in std_logic := '0'; -- ddasi_dclk.conduit_ddasi_dclk
ddasi_scein : in std_logic_vector(0 downto 0) := (others => '0'); -- ddasi_scein.conduit_ddasi_scein
ddasi_sdoin : in std_logic_vector(0 downto 0) := (others => '0'); -- ddasi_sdoin.conduit_ddasi_sdoin
asmi_busy : in std_logic := '0'; -- asmi_busy.conduit_busy
asmi_data_valid : in std_logic := '0'; -- asmi_data_valid.conduit_data_valid
asmi_dataout : in std_logic_vector(7 downto 0) := (others => '0'); -- asmi_dataout.conduit_dataout
epcq_dataout : in std_logic_vector(0 downto 0) := (others => '0'); -- epcq_dataout.conduit_epcq_dataout
ddasi_dataout : out std_logic_vector(0 downto 0); -- ddasi_dataout.conduit_ddasi_dataout
asmi_read_rdid : out std_logic; -- asmi_read_rdid.conduit_read_rdid
asmi_read_status : out std_logic; -- asmi_read_status.conduit_read_status
asmi_read_sid : out std_logic; -- asmi_read_sid.conduit_read_sid
asmi_bulk_erase : out std_logic; -- asmi_bulk_erase.conduit_bulk_erase
asmi_sector_erase : out std_logic; -- asmi_sector_erase.conduit_sector_erase
asmi_sector_protect : out std_logic; -- asmi_sector_protect.conduit_sector_protect
epcq_dclk : out std_logic; -- epcq_dclk.conduit_epcq_dclk
epcq_scein : out std_logic_vector(0 downto 0); -- epcq_scein.conduit_epcq_scein
epcq_sdoin : out std_logic_vector(0 downto 0); -- epcq_sdoin.conduit_epcq_sdoin
epcq_dataoe : out std_logic_vector(0 downto 0); -- epcq_dataoe.conduit_epcq_dataoe
asmi_clkin : out std_logic; -- asmi_clkin.conduit_clkin
asmi_reset : out std_logic; -- asmi_reset.conduit_reset
asmi_sce : out std_logic_vector(0 downto 0); -- asmi_sce.conduit_asmi_sce
asmi_addr : out std_logic_vector(23 downto 0); -- asmi_addr.conduit_addr
asmi_datain : out std_logic_vector(7 downto 0); -- asmi_datain.conduit_datain
asmi_fast_read : out std_logic; -- asmi_fast_read.conduit_fast_read
asmi_rden : out std_logic; -- asmi_rden.conduit_rden
asmi_shift_bytes : out std_logic; -- asmi_shift_bytes.conduit_shift_bytes
asmi_wren : out std_logic; -- asmi_wren.conduit_wren
asmi_write : out std_logic; -- asmi_write.conduit_write
asmi_rdid_out : in std_logic_vector(7 downto 0) := (others => '0'); -- asmi_rdid_out.conduit_rdid_out
asmi_en4b_addr : out std_logic; -- asmi_en4b_addr.conduit_en4b_addr
irq : out std_logic -- interrupt_sender.irq
);
end entity altera_epcq_controller_core;
architecture rtl of altera_epcq_controller_core is
component altera_epcq_controller_arb is
generic (
DEVICE_FAMILY : string := "";
ADDR_WIDTH : integer := 19;
ASMI_ADDR_WIDTH : integer := 24;
ASI_WIDTH : integer := 1;
CS_WIDTH : integer := 1;
CHIP_SELS : integer := 1;
ENABLE_4BYTE_ADDR : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
avl_csr_read : in std_logic := 'X'; -- read
avl_csr_waitrequest : out std_logic; -- waitrequest
avl_csr_write : in std_logic := 'X'; -- write
avl_csr_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
avl_csr_wrdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avl_csr_rddata : out std_logic_vector(31 downto 0); -- readdata
avl_csr_rddata_valid : out std_logic; -- readdatavalid
avl_mem_write : in std_logic := 'X'; -- write
avl_mem_burstcount : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
avl_mem_waitrequest : out std_logic; -- waitrequest
avl_mem_read : in std_logic := 'X'; -- read
avl_mem_addr : in std_logic_vector(18 downto 0) := (others => 'X'); -- address
avl_mem_wrdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avl_mem_rddata : out std_logic_vector(31 downto 0); -- readdata
avl_mem_rddata_valid : out std_logic; -- readdatavalid
avl_mem_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
asmi_status_out : in std_logic_vector(7 downto 0) := (others => 'X'); -- conduit_status_out
asmi_epcs_id : in std_logic_vector(7 downto 0) := (others => 'X'); -- conduit_epcs_id
asmi_illegal_erase : in std_logic := 'X'; -- conduit_illegal_erase
asmi_illegal_write : in std_logic := 'X'; -- conduit_illegal_write
ddasi_dataoe : in std_logic_vector(0 downto 0) := (others => 'X'); -- conduit_ddasi_dataoe
ddasi_dclk : in std_logic := 'X'; -- conduit_ddasi_dclk
ddasi_scein : in std_logic_vector(0 downto 0) := (others => 'X'); -- conduit_ddasi_scein
ddasi_sdoin : in std_logic_vector(0 downto 0) := (others => 'X'); -- conduit_ddasi_sdoin
asmi_busy : in std_logic := 'X'; -- conduit_busy
asmi_data_valid : in std_logic := 'X'; -- conduit_data_valid
asmi_dataout : in std_logic_vector(7 downto 0) := (others => 'X'); -- conduit_dataout
epcq_dataout : in std_logic_vector(0 downto 0) := (others => 'X'); -- conduit_epcq_dataout
ddasi_dataout : out std_logic_vector(0 downto 0); -- conduit_ddasi_dataout
asmi_read_rdid : out std_logic; -- conduit_read_rdid
asmi_read_status : out std_logic; -- conduit_read_status
asmi_read_sid : out std_logic; -- conduit_read_sid
asmi_bulk_erase : out std_logic; -- conduit_bulk_erase
asmi_sector_erase : out std_logic; -- conduit_sector_erase
asmi_sector_protect : out std_logic; -- conduit_sector_protect
epcq_dclk : out std_logic; -- conduit_epcq_dclk
epcq_scein : out std_logic_vector(0 downto 0); -- conduit_epcq_scein
epcq_sdoin : out std_logic_vector(0 downto 0); -- conduit_epcq_sdoin
epcq_dataoe : out std_logic_vector(0 downto 0); -- conduit_epcq_dataoe
asmi_clkin : out std_logic; -- conduit_clkin
asmi_reset : out std_logic; -- conduit_reset
asmi_sce : out std_logic_vector(0 downto 0); -- conduit_asmi_sce
asmi_addr : out std_logic_vector(23 downto 0); -- conduit_addr
asmi_datain : out std_logic_vector(7 downto 0); -- conduit_datain
asmi_fast_read : out std_logic; -- conduit_fast_read
asmi_rden : out std_logic; -- conduit_rden
asmi_shift_bytes : out std_logic; -- conduit_shift_bytes
asmi_wren : out std_logic; -- conduit_wren
asmi_write : out std_logic; -- conduit_write
asmi_rdid_out : in std_logic_vector(7 downto 0) := (others => 'X'); -- conduit_rdid_out
asmi_en4b_addr : out std_logic; -- conduit_en4b_addr
irq : out std_logic -- irq
);
end component altera_epcq_controller_arb;
begin
device_family_check : if DEVICE_FAMILY /= "Cyclone IV E" generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
addr_width_check : if ADDR_WIDTH /= 19 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
asmi_addr_width_check : if ASMI_ADDR_WIDTH /= 24 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
asi_width_check : if ASI_WIDTH /= 1 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
cs_width_check : if CS_WIDTH /= 1 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
chip_sels_check : if CHIP_SELS /= 1 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
enable_4byte_addr_check : if ENABLE_4BYTE_ADDR /= 0 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
altera_epcq_controller_core : component altera_epcq_controller_arb
generic map (
DEVICE_FAMILY => "Cyclone IV E",
ADDR_WIDTH => 19,
ASMI_ADDR_WIDTH => 24,
ASI_WIDTH => 1,
CS_WIDTH => 1,
CHIP_SELS => 1,
ENABLE_4BYTE_ADDR => 0
)
port map (
clk => clk, -- clock_sink.clk
reset_n => reset_n, -- reset.reset_n
avl_csr_read => avl_csr_read, -- avl_csr.read
avl_csr_waitrequest => avl_csr_waitrequest, -- .waitrequest
avl_csr_write => avl_csr_write, -- .write
avl_csr_addr => avl_csr_addr, -- .address
avl_csr_wrdata => avl_csr_wrdata, -- .writedata
avl_csr_rddata => avl_csr_rddata, -- .readdata
avl_csr_rddata_valid => avl_csr_rddata_valid, -- .readdatavalid
avl_mem_write => avl_mem_write, -- avl_mem.write
avl_mem_burstcount => avl_mem_burstcount, -- .burstcount
avl_mem_waitrequest => avl_mem_waitrequest, -- .waitrequest
avl_mem_read => avl_mem_read, -- .read
avl_mem_addr => avl_mem_addr, -- .address
avl_mem_wrdata => avl_mem_wrdata, -- .writedata
avl_mem_rddata => avl_mem_rddata, -- .readdata
avl_mem_rddata_valid => avl_mem_rddata_valid, -- .readdatavalid
avl_mem_byteenable => avl_mem_byteenable, -- .byteenable
asmi_status_out => asmi_status_out, -- asmi_status_out.conduit_status_out
asmi_epcs_id => asmi_epcs_id, -- asmi_epcs_id.conduit_epcs_id
asmi_illegal_erase => asmi_illegal_erase, -- asmi_illegal_erase.conduit_illegal_erase
asmi_illegal_write => asmi_illegal_write, -- asmi_illegal_write.conduit_illegal_write
ddasi_dataoe => ddasi_dataoe, -- ddasi_dataoe.conduit_ddasi_dataoe
ddasi_dclk => ddasi_dclk, -- ddasi_dclk.conduit_ddasi_dclk
ddasi_scein => ddasi_scein, -- ddasi_scein.conduit_ddasi_scein
ddasi_sdoin => ddasi_sdoin, -- ddasi_sdoin.conduit_ddasi_sdoin
asmi_busy => asmi_busy, -- asmi_busy.conduit_busy
asmi_data_valid => asmi_data_valid, -- asmi_data_valid.conduit_data_valid
asmi_dataout => asmi_dataout, -- asmi_dataout.conduit_dataout
epcq_dataout => epcq_dataout, -- epcq_dataout.conduit_epcq_dataout
ddasi_dataout => ddasi_dataout, -- ddasi_dataout.conduit_ddasi_dataout
asmi_read_rdid => asmi_read_rdid, -- asmi_read_rdid.conduit_read_rdid
asmi_read_status => asmi_read_status, -- asmi_read_status.conduit_read_status
asmi_read_sid => asmi_read_sid, -- asmi_read_sid.conduit_read_sid
asmi_bulk_erase => asmi_bulk_erase, -- asmi_bulk_erase.conduit_bulk_erase
asmi_sector_erase => asmi_sector_erase, -- asmi_sector_erase.conduit_sector_erase
asmi_sector_protect => asmi_sector_protect, -- asmi_sector_protect.conduit_sector_protect
epcq_dclk => epcq_dclk, -- epcq_dclk.conduit_epcq_dclk
epcq_scein => epcq_scein, -- epcq_scein.conduit_epcq_scein
epcq_sdoin => epcq_sdoin, -- epcq_sdoin.conduit_epcq_sdoin
epcq_dataoe => epcq_dataoe, -- epcq_dataoe.conduit_epcq_dataoe
asmi_clkin => asmi_clkin, -- asmi_clkin.conduit_clkin
asmi_reset => asmi_reset, -- asmi_reset.conduit_reset
asmi_sce => asmi_sce, -- asmi_sce.conduit_asmi_sce
asmi_addr => asmi_addr, -- asmi_addr.conduit_addr
asmi_datain => asmi_datain, -- asmi_datain.conduit_datain
asmi_fast_read => asmi_fast_read, -- asmi_fast_read.conduit_fast_read
asmi_rden => asmi_rden, -- asmi_rden.conduit_rden
asmi_shift_bytes => asmi_shift_bytes, -- asmi_shift_bytes.conduit_shift_bytes
asmi_wren => asmi_wren, -- asmi_wren.conduit_wren
asmi_write => asmi_write, -- asmi_write.conduit_write
asmi_rdid_out => asmi_rdid_out, -- asmi_rdid_out.conduit_rdid_out
asmi_en4b_addr => asmi_en4b_addr, -- asmi_en4b_addr.conduit_en4b_addr
irq => irq -- interrupt_sender.irq
);
end architecture rtl; -- of altera_epcq_controller_core
| mit | f37758915140b960831ca7f60aeeaa40 | 0.48009 | 3.774259 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_sdram/niosii_top.vhd | 3 | 2,662 | ----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
----------------------------------------------------------------------------------
--The MIT License (MIT)
--
--Copyright (c) 2015
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
----------------------------------------------------------------------------------
-- Library Define
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity niosii_top is
Port (
p_clk_50Mhz : in std_logic;
p_button : in std_logic_vector( 1 downto 0 );
p_led_out : out std_logic_vector( 7 downto 0 )
);
end niosii_top;
architecture Behavioral of niosii_top is
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component niosii;
signal s_reset_n : std_logic;
begin
s_reset_n <= p_button(0);
u0 : component niosii
port map (
clk_clk => p_clk_50Mhz,
pio_0_external_connection_export => p_led_out,
reset_reset_n => s_reset_n
);
end Behavioral;
| mit | cfc27ee4eed11b19e843ea33e1d46ef1 | 0.574756 | 4.159375 | false | false | false | false |
josemonsalve2/cpeg324_calculator | vivado/hdl/blk_mem_gen_0/sim/blk_mem_gen_0.vhd | 1 | 12,421 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 256,
C_READ_DEPTH_A => 256,
C_ADDRA_WIDTH => 8,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 256,
C_READ_DEPTH_B => 256,
C_ADDRB_WIDTH => 8,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.54005 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| gpl-3.0 | df4dd8a6f7d4c6ab0171c4cfe95bb316 | 0.606312 | 3.192238 | false | false | false | false |
pkerling/ethernet_mac | xilinx/mii_gmii_io_spartan6.vhd | 1 | 6,802 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- IO structure for MII/GMII on Xilinx Spartan-6 devices
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
architecture spartan_6 of mii_gmii_io is
signal gmii_active : std_ulogic := '0';
signal clock_tx : std_ulogic := '0';
signal clock_tx_inv : std_ulogic := '1';
signal clock_mii_rx_io : std_ulogic := '0';
signal clock_mii_rx_div : std_ulogic;
-- IDELAY_VALUE applied to the inputs using IODELAY2
-- This will need fine-tuning depending on the exact device and the location of the IO pins
-- The constraints file can be used to override this default value in the fixed_input_delay
-- instances if needed
constant MII_RX_INPUT_DELAY : natural := 10;
signal clock_mii_rx_ibufg : std_ulogic;
begin
clock_tx_o <= clock_tx;
-- Inverter is absorbed into the IOB FF clock inputs
clock_tx_inv <= not clock_tx;
-- speed_select_i must be registered so no hazards can reach the BUFGMUX
with speed_select_i select gmii_active <=
'1' when SPEED_1000MBPS,
'0' when others;
-- Switch between 125 Mhz reference clock and MII_TX_CLK for TX process and register clocking
-- depending on mode of operation
-- Asynchronous clock switch-over is required: the MII TX_CLK might not be running any more when
-- switching to GMII. This means that glitches can occur on the clock and the complete MAC has to
-- be reset after a speed change.
clock_tx_BUFGMUX_inst : BUFGMUX
generic map(
CLK_SEL_TYPE => "ASYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map(
O => clock_tx, -- 1-bit output: Clock buffer output
I0 => mii_tx_clk_i, -- 1-bit input: Clock buffer input (S=0)
I1 => clock_125_i, -- 1-bit input: Clock buffer input (S=1)
S => gmii_active -- 1-bit input: Clock buffer select
);
-- Output clock only when running GMII to reduce switching noise
-- and avoid outputting a useless 25 MHz clock in MII mode.
-- Invert clock so that the output values toggle at the falling edge (as seen from the PHY)
-- and are valid when the clock rises.
-- The inverse clock is generated by simple inversion. This is not a problem since inverters
-- are integrated into the ODDR2 clock inputs (no LUT necessary).
-- Clock enable is not synchronous to clock_tx here, but that shouldn't matter as it
-- switches only very seldomly. If the setup/hold time is violated, only one or two clock cyles
-- should be missed.
ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map(
Q => gmii_gtx_clk_o, -- 1-bit output data
C0 => clock_tx_inv, -- 1-bit clock input
C1 => clock_tx, -- 1-bit clock input
CE => gmii_active, -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Use FDRE in IOB for output pins to guarantee delay characteristics are identical to the GTX_CLK output.
-- The registers need to be clocked by clock_tx and not clock_125. Metastability would
-- ensure otherwise since the TX state machine is clocked by clock_tx and clock_tx/clock_125
-- have no defined phase relationship.
mii_tx_en_buffer_inst : entity work.output_buffer
port map(
pad_o => mii_tx_en_o,
buffer_i => int_mii_tx_en_i,
clock_i => clock_tx
);
mii_txd_buffer_generate : for i in mii_txd_o'range generate
mii_txd_buffer_inst : entity work.output_buffer
port map(
pad_o => mii_txd_o(i),
buffer_i => int_mii_txd_i(i),
clock_i => clock_tx
);
end generate;
-- Inserting a delay into the clock path should theoretically allow fine-tuning
-- of the clock/data offset, but the timing analyzer doesn't like it as very big
-- IDELAY_VALUE values are necessary that exhibit strong variations. Maybe it works anyway. Try if
-- the current method fails.
-- mii_rx_clk_delay_inst : entity work.fixed_input_delay
-- generic map (
-- IDELAY_VALUE => 0
-- )
-- port map (
-- pin_i => mii_rx_clk_i,
-- delayed_o => mii_rx_clk_delayed
-- );
IBUFG_inst : IBUFG
generic map(
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVCMOS33")
port map(
O => clock_mii_rx_ibufg, -- Clock buffer output
I => mii_rx_clk_i -- Clock buffer input (connect directly to top-level port)
);
-- Use of a PLL or DCM for RX_CLK is not possible! The clock frequency in 10 Mbps mode (2.5 MHz)
-- is below the minimum input frequency of both the PLL and DCM block.
mii_rx_clk_BUFIO2_inst : BUFIO2
generic map(
DIVIDE => 1, -- DIVCLK divider (1,3-8)
DIVIDE_BYPASS => TRUE, -- Bypass the divider circuitry (TRUE/FALSE)
I_INVERT => FALSE, -- Invert clock (TRUE/FALSE)
USE_DOUBLER => FALSE -- Use doubler circuitry (TRUE/FALSE)
)
port map(
DIVCLK => clock_mii_rx_div, -- 1-bit output: Divided clock output
IOCLK => clock_mii_rx_io, -- 1-bit output: I/O output clock
SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
I => clock_mii_rx_ibufg -- 1-bit input: Clock input (connect to IBUFG)
);
mii_rx_clk_BUFG_inst : BUFG
port map(
O => clock_rx_o, -- 1-bit output: Clock buffer output
I => clock_mii_rx_div -- 1-bit input: Clock buffer input
);
mii_rx_dv_buffer_inst : entity work.input_buffer
generic map(
HAS_DELAY => TRUE,
IDELAY_VALUE => MII_RX_INPUT_DELAY
)
port map(
pad_i => mii_rx_dv_i,
buffer_o => int_mii_rx_dv_o,
clock_i => clock_mii_rx_io
);
mii_rx_er_buffer_inst : entity work.input_buffer
generic map(
HAS_DELAY => TRUE,
IDELAY_VALUE => MII_RX_INPUT_DELAY
)
port map(
pad_i => mii_rx_er_i,
buffer_o => int_mii_rx_er_o,
clock_i => clock_mii_rx_io
);
mii_rxd_buffer_generate : for i in mii_rxd_i'range generate
mii_rxd_buffer_inst : entity work.input_buffer
generic map(
HAS_DELAY => TRUE,
IDELAY_VALUE => MII_RX_INPUT_DELAY
)
port map(
pad_i => mii_rxd_i(i),
buffer_o => int_mii_rxd_o(i),
clock_i => clock_mii_rx_io
);
end generate;
end architecture;
| bsd-3-clause | c53f0084fa730ee1c340c200d63ffef8 | 0.643487 | 3.196429 | false | false | false | false |
josemonsalve2/cpeg324_calculator | vivado/hdl/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 1 | 14,440 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.54005 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 256,
C_READ_DEPTH_A => 256,
C_ADDRA_WIDTH => 8,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 256,
C_READ_DEPTH_B => 256,
C_ADDRB_WIDTH => 8,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.54005 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| gpl-3.0 | 7e798efccc12131bab7b6f369eb9bfbe | 0.625208 | 2.992746 | false | false | false | false |
josemonsalve2/cpeg324_calculator | vivado/hdl/InstructionsMemory/src/Sim/new/InstructionMemory_tb.vhd | 1 | 3,746 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/09/2016 11:44:29 PM
-- Design Name:
-- Module Name: InstructionMemory_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstructionMemory_tb is
-- Port ( );
end InstructionMemory_tb;
architecture Behavioral of InstructionMemory_tb is
constant clk_period : time := 8 ns;
component InstructionsMemory
Port ( clk : in STD_LOGIC;
PC : in STD_LOGIC_VECTOR (7 downto 0);
Instruction : out STD_LOGIC_VECTOR (7 downto 0);
Address : in STD_LOGIC_VECTOR (7 downto 0);
data_write : in STD_LOGIC_VECTOR (7 downto 0);
data_read : out STD_LOGIC_VECTOR (7 downto 0);
write_enable : in STD_LOGIC;
reset: in STD_LOGIC;
num_instructions: out STD_LOGIC_VECTOR (7 downto 0):=(others => '0')
);
end component;
SIGNAL clk : STD_LOGIC:='0';
SIGNAL PC : STD_LOGIC_VECTOR (7 downto 0):=(others => '0');
SIGNAL Instruction : STD_LOGIC_VECTOR (7 downto 0):=(others => '0');
SIGNAL Address : STD_LOGIC_VECTOR (7 downto 0):=(others => '0');
SIGNAL data_write : STD_LOGIC_VECTOR (7 downto 0):=(others => '0');
SIGNAL data_read : STD_LOGIC_VECTOR (7 downto 0):=(others => '0');
SIGNAL write_enable : STD_LOGIC:='0';
SIGNAL reset: STD_LOGIC:='0';
SIGNAL num_instructions: STD_LOGIC_VECTOR (7 downto 0):=(others => '0');
signal counter : STD_LOGIC_VECTOR (31 downto 0):=(others => '0');
begin
instMem_0: InstructionsMemory
PORT MAP (
clk => clk,
PC => PC,
Instruction => Instruction,
Address => Address,
data_write => data_write,
data_read => data_read,
write_enable => write_enable,
reset => reset,
num_instructions => num_instructions
);
clk_proc_0: process is
begin
clk <= '0';
wait for clk_period/2; --for 0.5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;
inst_mem_proc: process (clk)
begin
counter <= counter +1;
if counter = x"0000" & x"0000" then
reset <= '1';
elsif counter = x"0000" & x"000A" then
reset <= '0';
elsif counter = x"0000" & x"001C" then
Address <= "00000001";
data_write <= "10101010";
write_enable <= '1';
elsif counter = x"0000" & x"0020" then
write_enable <= '0';
elsif counter = x"0000" & x"0035" then
PC<= PC + 1;
elsif counter = x"0000" & x"000A" then
elsif counter = x"0000" & x"000A" then
end if;
end process;
end Behavioral;
| gpl-3.0 | bae0483c08bce9321f9d1b96dab44bbe | 0.503203 | 4.176143 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_test/niosii/niosii_inst.vhd | 1 | 2,985 | component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_addr : out std_logic_vector(12 downto 0); -- addr
sdram_ba : out std_logic_vector(1 downto 0); -- ba
sdram_cas_n : out std_logic; -- cas_n
sdram_cke : out std_logic; -- cke
sdram_cs_n : out std_logic; -- cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_ras_n : out std_logic; -- ras_n
sdram_we_n : out std_logic; -- we_n
sdram_clk_clk : out std_logic -- clk
);
end component niosii;
u0 : component niosii
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export, -- pio_0_external_connection.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_addr => CONNECTED_TO_sdram_addr, -- sdram.addr
sdram_ba => CONNECTED_TO_sdram_ba, -- .ba
sdram_cas_n => CONNECTED_TO_sdram_cas_n, -- .cas_n
sdram_cke => CONNECTED_TO_sdram_cke, -- .cke
sdram_cs_n => CONNECTED_TO_sdram_cs_n, -- .cs_n
sdram_dq => CONNECTED_TO_sdram_dq, -- .dq
sdram_dqm => CONNECTED_TO_sdram_dqm, -- .dqm
sdram_ras_n => CONNECTED_TO_sdram_ras_n, -- .ras_n
sdram_we_n => CONNECTED_TO_sdram_we_n, -- .we_n
sdram_clk_clk => CONNECTED_TO_sdram_clk_clk -- sdram_clk.clk
);
| mit | 1c5b66f3a8fb1b8e93127d52b5e3600a | 0.318928 | 4.753185 | false | false | false | false |
PsiStarPsi/firmware-general | General/sim/CommandInterpreterTest.vhd | 1 | 8,191 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:38:54 09/09/2015
-- Design Name:
-- Module Name: C:/Users/Kurtis/Google Drive/mTC/svn/src/General/sim/CommandInterpreterTest.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CommandInterpreter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY CommandInterpreterTest IS
END CommandInterpreterTest;
ARCHITECTURE behavior OF CommandInterpreterTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CommandInterpreter
PORT(
usrClk : IN std_logic;
usrRst : IN std_logic;
rxData : IN std_logic_vector(31 downto 0);
rxDataValid : IN std_logic;
rxDataLast : IN std_logic;
rxDataReady : OUT std_logic;
txData : OUT std_logic_vector(31 downto 0);
txDataValid : OUT std_logic;
txDataLast : OUT std_logic;
txDataReady : IN std_logic;
myId : IN std_logic_vector(15 downto 0);
regAddr : OUT std_logic_vector(15 downto 0);
regWrData : OUT std_logic_vector(15 downto 0);
regRdData : IN std_logic_vector(15 downto 0);
regReq : OUT std_logic;
regOp : OUT std_logic;
regAck : IN std_logic
);
END COMPONENT;
--Inputs
signal usrClk : std_logic := '0';
signal usrRst : std_logic := '0';
signal rxData : std_logic_vector(31 downto 0) := (others => '0');
signal rxDataValid : std_logic := '0';
signal rxDataLast : std_logic := '0';
signal txDataReady : std_logic := '0';
signal myId : std_logic_vector(15 downto 0) := (others => '0');
signal regRdData : std_logic_vector(15 downto 0) := (others => '0');
signal regAck : std_logic := '0';
--Outputs
signal rxDataReady : std_logic;
signal txData : std_logic_vector(31 downto 0);
signal txDataValid : std_logic;
signal txDataLast : std_logic;
signal regAddr : std_logic_vector(15 downto 0);
signal regWrData : std_logic_vector(15 downto 0);
signal regReq : std_logic;
signal regOp : std_logic;
signal packetCount : std_logic_vector(15 downto 0) := (others => '0');
signal targetAddr : std_logic_vector(15 downto 0) := x"00A5";
signal targetData : std_logic_vector(15 downto 0) := x"0120";
signal thisCommand : std_logic_vector(31 downto 0);
signal thisCommandId : std_logic_vector(23 downto 0);
signal thisCommandNoResponse : std_logic;
signal thisCommandIdWord : std_logic_vector(31 downto 0);
signal thisCommandDataWord : std_logic_vector(31 downto 0);
signal commandChecksum : std_logic_vector(31 downto 0);
signal packetChecksum : std_logic_vector(31 downto 0);
signal scrodRev : std_logic_vector(7 downto 0);
signal scrodId : std_logic_Vector(15 downto 0);
signal scrodIdWord : std_logic_vector(31 downto 0);
signal packetLength : std_logic_vector(31 downto 0);
signal myReg : std_logic_vector(15 downto 0);
constant MY_REG_ADDR_C : std_logic_Vector(15 downto 0) := x"00A5";
constant WORD_HEADER_C : std_logic_vector(31 downto 0) := x"00BE11E2";
constant WORD_COMMAND_C : std_logic_vector(31 downto 0) := x"646F6974";
constant WORD_PING_C : std_logic_vector(31 downto 0) := x"70696E67";
constant WORD_READ_C : std_logic_vector(31 downto 0) := x"72656164";
constant WORD_WRITE_C : std_logic_vector(31 downto 0) := x"72697465";
constant WORD_ACK_C : std_logic_vector(31 downto 0) := x"6F6B6179";
constant WORD_ERR_C : std_logic_vector(31 downto 0) := x"7768613f";
-- Clock period definitions
constant usrClk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CommandInterpreter PORT MAP (
usrClk => usrClk,
usrRst => usrRst,
rxData => rxData,
rxDataValid => rxDataValid,
rxDataLast => rxDataLast,
rxDataReady => rxDataReady,
txData => txData,
txDataValid => txDataValid,
txDataLast => txDataLast,
txDataReady => txDataReady,
myId => myId,
regAddr => regAddr,
regWrData => regWrData,
regRdData => regRdData,
regReq => regReq,
regOp => regOp,
regAck => regAck
);
-- Clock process definitions
usrClk_process :process
begin
usrClk <= '0';
wait for usrClk_period/2;
usrClk <= '1';
wait for usrClk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
usrRst <= '1';
wait for 100 ns;
usrRst <= '0';
wait for usrClk_period*10;
-- insert stimulus here
wait;
end process;
scrodRev <= x"00";
scrodId <= x"0000";
thisCommand <= WORD_READ_C;
thisCommandId <= x"009900";
thisCommandNoResponse <= '0';
targetAddr <= x"00A6";
targetData <= x"0120";
thisCommandIdWord <= thisCommandNoResponse & "0000000" & thisCommandId;
thisCommandDataWord <= targetData & targetAddr;
scrodIdWord <= x"00" & scrodRev & scrodId;
packetLength <= x"00000007" when thisCommand /= WORD_PING_C else x"00000006";
commandChecksum <= thisCommandIdWord + thisCommand + thisCommandDataWord;
packetChecksum <= WORD_HEADER_C + packetLength + WORD_COMMAND_C +
scrodIdWord + thisCommandIdWord + thisCommand +
thisCommandDataWord + commandChecksum;
process(usrClk) begin
if rising_edge(usrClk) then
if usrRst = '1' then
rxDataValid <= '0';
rxDataLast <= '0';
rxData <= (others => '0');
else
if rxDataReady = '1' then
packetCount <= packetCount + 1;
end if;
rxDataValid <= '1';
rxDataLast <= '0';
case conv_integer(packetCount) is
when 0 => rxData <= WORD_HEADER_C;
when 1 => rxData <= packetLength;
when 2 => rxData <= WORD_COMMAND_C;
when 3 => rxData <= scrodIdWord;
when 4 => rxData <= thisCommandIdWord;
when 5 => rxData <= thisCommand;
when 6 => rxData <= thisCommandDataWord;
when 7 => rxData <= commandChecksum;
when 8 => rxData <= packetChecksum;
rxDataLast <= '1';
when others => rxDataValid <= '0';
end case;
end if;
end if;
end process;
process(usrClk) begin
if rising_edge(usrClk) then
if usrRst = '1' then
myReg <= x"AAAA";
elsif regReq = '1' then
regAck <= regReq;
case regAddr is
when MY_REG_ADDR_C =>
regRdData <= myReg;
if regOp = '1' then
myReg <= regWrData;
end if;
when others =>
regRdData <= (others => '0');
end case;
else
regAck <= '0';
end if;
end if;
end process;
txDataReady <= '1';
END;
| lgpl-2.1 | 163f78e1b513a6e82de55992b7451f21 | 0.571359 | 3.937981 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pwm/niosii/synthesis/niosii.vhd | 1 | 89,734 | -- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
ip_pwm_dir : out std_logic_vector(1 downto 0); -- ip_pwm.dir
ip_pwm_out : out std_logic_vector(1 downto 0); -- .out
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- pio_0_external_connection.export
reset_reset_n : in std_logic := '0'; -- reset.reset_n
uart_0_rxd : in std_logic := '0'; -- uart_0.rxd
uart_0_txd : out std_logic -- .txd
);
end entity niosii;
architecture rtl of niosii is
component niosii_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
c2 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component niosii_altpll_0;
component ip_pwm_top is
port (
avs_s0_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
avs_s0_read : in std_logic := 'X'; -- read
avs_s0_readdata : out std_logic_vector(31 downto 0); -- readdata
avs_s0_write : in std_logic := 'X'; -- write
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avs_s0_waitrequest : out std_logic; -- waitrequest
clock_clk : in std_logic := 'X'; -- clk
reset_reset : in std_logic := 'X'; -- reset
pwm_dir : out std_logic_vector(1 downto 0); -- dir
pwm_out : out std_logic_vector(1 downto 0) -- out
);
end component ip_pwm_top;
component niosii_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosii_jtag_uart_0;
component niosii_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(17 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(17 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component niosii_nios2_gen2_0;
component niosii_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosii_onchip_memory2_0;
component niosii_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosii_pio_0;
component niosii_timer_ms is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosii_timer_ms;
component niosii_timer_us is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosii_timer_us;
component niosii_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
chipselect : in std_logic := 'X'; -- chipselect
read_n : in std_logic := 'X'; -- read_n
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
dataavailable : out std_logic; -- dataavailable
readyfordata : out std_logic; -- readyfordata
rxd : in std_logic := 'X'; -- export
txd : out std_logic; -- export
irq : out std_logic -- irq
);
end component niosii_uart_0;
component niosii_mm_interconnect_0 is
port (
altpll_0_c0_clk : in std_logic := 'X'; -- clk
altpll_0_c1_clk : in std_logic := 'X'; -- clk
altpll_0_c2_clk : in std_logic := 'X'; -- clk
clk_0_clk_clk : in std_logic := 'X'; -- clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
ip_pwm_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
timer_us_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address
altpll_0_pll_slave_write : out std_logic; -- write
altpll_0_pll_slave_read : out std_logic; -- read
altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
ip_pwm_0_avs_s0_address : out std_logic_vector(7 downto 0); -- address
ip_pwm_0_avs_s0_write : out std_logic; -- write
ip_pwm_0_avs_s0_read : out std_logic; -- read
ip_pwm_0_avs_s0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
ip_pwm_0_avs_s0_writedata : out std_logic_vector(31 downto 0); -- writedata
ip_pwm_0_avs_s0_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_address : out std_logic_vector(0 downto 0); -- address
jtag_uart_0_avalon_jtag_slave_write : out std_logic; -- write
jtag_uart_0_avalon_jtag_slave_read : out std_logic; -- read
jtag_uart_0_avalon_jtag_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_uart_0_avalon_jtag_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(13 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
timer_ms_s1_address : out std_logic_vector(2 downto 0); -- address
timer_ms_s1_write : out std_logic; -- write
timer_ms_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
timer_ms_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
timer_ms_s1_chipselect : out std_logic; -- chipselect
timer_us_s1_address : out std_logic_vector(2 downto 0); -- address
timer_us_s1_write : out std_logic; -- write
timer_us_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
timer_us_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
timer_us_s1_chipselect : out std_logic; -- chipselect
uart_0_s1_address : out std_logic_vector(2 downto 0); -- address
uart_0_s1_write : out std_logic; -- write
uart_0_s1_read : out std_logic; -- read
uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
uart_0_s1_begintransfer : out std_logic; -- begintransfer
uart_0_s1_chipselect : out std_logic -- chipselect
);
end component niosii_mm_interconnect_0;
component niosii_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
receiver2_irq : in std_logic := 'X'; -- irq
receiver3_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosii_irq_mapper;
component altera_irq_clock_crosser is
generic (
IRQ_WIDTH : integer := 1
);
port (
receiver_clk : in std_logic := 'X'; -- clk
sender_clk : in std_logic := 'X'; -- clk
receiver_reset : in std_logic := 'X'; -- reset
sender_reset : in std_logic := 'X'; -- reset
receiver_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
sender_irq : out std_logic_vector(0 downto 0) -- irq
);
end component altera_irq_clock_crosser;
component niosii_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller;
component niosii_rst_controller_002 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller_002;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [irq_mapper:clk, irq_synchronizer:sender_clk, irq_synchronizer_001:sender_clk, irq_synchronizer_002:sender_clk, jtag_uart_0:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_memory2_0:clk, rst_controller_002:clk]
signal altpll_0_c1_clk : std_logic; -- altpll_0:c1 -> [ip_pwm_0:clock_clk, irq_synchronizer:receiver_clk, mm_interconnect_0:altpll_0_c1_clk, pio_0:clk, rst_controller_001:clk, uart_0:clk]
signal altpll_0_c2_clk : std_logic; -- altpll_0:c2 -> [irq_synchronizer_001:receiver_clk, irq_synchronizer_002:receiver_clk, mm_interconnect_0:altpll_0_c2_clk, rst_controller_003:clk, timer_ms:clk, timer_us:clk]
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
signal mm_interconnect_0_ip_pwm_0_avs_s0_readdata : std_logic_vector(31 downto 0); -- ip_pwm_0:avs_s0_readdata -> mm_interconnect_0:ip_pwm_0_avs_s0_readdata
signal mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest : std_logic; -- ip_pwm_0:avs_s0_waitrequest -> mm_interconnect_0:ip_pwm_0_avs_s0_waitrequest
signal mm_interconnect_0_ip_pwm_0_avs_s0_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:ip_pwm_0_avs_s0_address -> ip_pwm_0:avs_s0_address
signal mm_interconnect_0_ip_pwm_0_avs_s0_read : std_logic; -- mm_interconnect_0:ip_pwm_0_avs_s0_read -> ip_pwm_0:avs_s0_read
signal mm_interconnect_0_ip_pwm_0_avs_s0_write : std_logic; -- mm_interconnect_0:ip_pwm_0_avs_s0_write -> ip_pwm_0:avs_s0_write
signal mm_interconnect_0_ip_pwm_0_avs_s0_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:ip_pwm_0_avs_s0_writedata -> ip_pwm_0:avs_s0_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata
signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address
signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read
signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write
signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(13 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address
signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in
signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in
signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
signal mm_interconnect_0_timer_us_s1_chipselect : std_logic; -- mm_interconnect_0:timer_us_s1_chipselect -> timer_us:chipselect
signal mm_interconnect_0_timer_us_s1_readdata : std_logic_vector(15 downto 0); -- timer_us:readdata -> mm_interconnect_0:timer_us_s1_readdata
signal mm_interconnect_0_timer_us_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:timer_us_s1_address -> timer_us:address
signal mm_interconnect_0_timer_us_s1_write : std_logic; -- mm_interconnect_0:timer_us_s1_write -> mm_interconnect_0_timer_us_s1_write:in
signal mm_interconnect_0_timer_us_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:timer_us_s1_writedata -> timer_us:writedata
signal mm_interconnect_0_timer_ms_s1_chipselect : std_logic; -- mm_interconnect_0:timer_ms_s1_chipselect -> timer_ms:chipselect
signal mm_interconnect_0_timer_ms_s1_readdata : std_logic_vector(15 downto 0); -- timer_ms:readdata -> mm_interconnect_0:timer_ms_s1_readdata
signal mm_interconnect_0_timer_ms_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:timer_ms_s1_address -> timer_ms:address
signal mm_interconnect_0_timer_ms_s1_write : std_logic; -- mm_interconnect_0:timer_ms_s1_write -> mm_interconnect_0_timer_ms_s1_write:in
signal mm_interconnect_0_timer_ms_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:timer_ms_s1_writedata -> timer_ms:writedata
signal irq_mapper_receiver0_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal irq_mapper_receiver1_irq : std_logic; -- irq_synchronizer:sender_irq -> irq_mapper:receiver1_irq
signal irq_synchronizer_receiver_irq : std_logic_vector(0 downto 0); -- uart_0:irq -> irq_synchronizer:receiver_irq
signal irq_mapper_receiver2_irq : std_logic; -- irq_synchronizer_001:sender_irq -> irq_mapper:receiver2_irq
signal irq_synchronizer_001_receiver_irq : std_logic_vector(0 downto 0); -- timer_us:irq -> irq_synchronizer_001:receiver_irq
signal irq_mapper_receiver3_irq : std_logic; -- irq_synchronizer_002:sender_irq -> irq_mapper:receiver3_irq
signal irq_synchronizer_002_receiver_irq : std_logic_vector(0 downto 0); -- timer_ms:irq -> irq_synchronizer_002:receiver_irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [ip_pwm_0:reset_reset, irq_synchronizer:receiver_reset, mm_interconnect_0:ip_pwm_0_reset_reset_bridge_in_reset_reset, rst_controller_001_reset_out_reset:in]
signal rst_controller_002_reset_out_reset : std_logic; -- rst_controller_002:reset_out -> [irq_mapper:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, irq_synchronizer_002:sender_reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_002_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_002_reset_out_reset_req : std_logic; -- rst_controller_002:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal rst_controller_003_reset_out_reset : std_logic; -- rst_controller_003:reset_out -> [irq_synchronizer_001:receiver_reset, irq_synchronizer_002:receiver_reset, mm_interconnect_0:timer_us_reset_reset_bridge_in_reset_reset, rst_controller_003_reset_out_reset:in]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0, rst_controller_003:reset_in0]
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:inv -> jtag_uart_0:av_read_n
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:inv -> jtag_uart_0:av_write_n
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n
signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n
signal mm_interconnect_0_timer_us_s1_write_ports_inv : std_logic; -- mm_interconnect_0_timer_us_s1_write:inv -> timer_us:write_n
signal mm_interconnect_0_timer_ms_s1_write_ports_inv : std_logic; -- mm_interconnect_0_timer_ms_s1_write:inv -> timer_ms:write_n
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [pio_0:reset_n, uart_0:reset_n]
signal rst_controller_002_reset_out_reset_ports_inv : std_logic; -- rst_controller_002_reset_out_reset:inv -> [jtag_uart_0:rst_n, nios2_gen2_0:reset_n]
signal rst_controller_003_reset_out_reset_ports_inv : std_logic; -- rst_controller_003_reset_out_reset:inv -> [timer_ms:reset_n, timer_us:reset_n]
begin
altpll_0 : component niosii_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset
read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read
write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address
readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => altpll_0_c1_clk, -- c1.clk
c2 => altpll_0_c2_clk, -- c2.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
ip_pwm_0 : component ip_pwm_top
port map (
avs_s0_address => mm_interconnect_0_ip_pwm_0_avs_s0_address, -- avs_s0.address
avs_s0_read => mm_interconnect_0_ip_pwm_0_avs_s0_read, -- .read
avs_s0_readdata => mm_interconnect_0_ip_pwm_0_avs_s0_readdata, -- .readdata
avs_s0_write => mm_interconnect_0_ip_pwm_0_avs_s0_write, -- .write
avs_s0_writedata => mm_interconnect_0_ip_pwm_0_avs_s0_writedata, -- .writedata
avs_s0_waitrequest => mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest, -- .waitrequest
clock_clk => altpll_0_c1_clk, -- clock.clk
reset_reset => rst_controller_001_reset_out_reset, -- reset.reset
pwm_dir => ip_pwm_dir, -- pwm.dir
pwm_out => ip_pwm_out -- .out
);
jtag_uart_0 : component niosii_jtag_uart_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
rst_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- avalon_jtag_slave.chipselect
av_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address(0), -- .address
av_read_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv, -- .read_n
av_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
av_write_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv, -- .write_n
av_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
av_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
av_irq => irq_mapper_receiver0_irq -- irq.irq
);
nios2_gen2_0 : component niosii_nios2_gen2_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_002_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosii_onchip_memory2_0
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_002_reset_out_reset, -- reset1.reset
reset_req => rst_controller_002_reset_out_reset_req -- .reset_req
);
pio_0 : component niosii_pio_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
out_port => pio_0_external_connection_export -- external_connection.export
);
timer_ms : component niosii_timer_ms
port map (
clk => altpll_0_c2_clk, -- clk.clk
reset_n => rst_controller_003_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_timer_ms_s1_address, -- s1.address
writedata => mm_interconnect_0_timer_ms_s1_writedata, -- .writedata
readdata => mm_interconnect_0_timer_ms_s1_readdata, -- .readdata
chipselect => mm_interconnect_0_timer_ms_s1_chipselect, -- .chipselect
write_n => mm_interconnect_0_timer_ms_s1_write_ports_inv, -- .write_n
irq => irq_synchronizer_002_receiver_irq(0) -- irq.irq
);
timer_us : component niosii_timer_us
port map (
clk => altpll_0_c2_clk, -- clk.clk
reset_n => rst_controller_003_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_timer_us_s1_address, -- s1.address
writedata => mm_interconnect_0_timer_us_s1_writedata, -- .writedata
readdata => mm_interconnect_0_timer_us_s1_readdata, -- .readdata
chipselect => mm_interconnect_0_timer_us_s1_chipselect, -- .chipselect
write_n => mm_interconnect_0_timer_us_s1_write_ports_inv, -- .write_n
irq => irq_synchronizer_001_receiver_irq(0) -- irq.irq
);
uart_0 : component niosii_uart_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_uart_0_s1_address, -- s1.address
begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect
read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n
write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
dataavailable => open, -- .dataavailable
readyfordata => open, -- .readyfordata
rxd => uart_0_rxd, -- external_connection.export
txd => uart_0_txd, -- .export
irq => irq_synchronizer_receiver_irq(0) -- irq.irq
);
mm_interconnect_0 : component niosii_mm_interconnect_0
port map (
altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk
altpll_0_c1_clk => altpll_0_c1_clk, -- altpll_0_c1.clk
altpll_0_c2_clk => altpll_0_c2_clk, -- altpll_0_c2.clk
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
ip_pwm_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- ip_pwm_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_002_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
timer_us_reset_reset_bridge_in_reset_reset => rst_controller_003_reset_out_reset, -- timer_us_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address
altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read
altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
ip_pwm_0_avs_s0_address => mm_interconnect_0_ip_pwm_0_avs_s0_address, -- ip_pwm_0_avs_s0.address
ip_pwm_0_avs_s0_write => mm_interconnect_0_ip_pwm_0_avs_s0_write, -- .write
ip_pwm_0_avs_s0_read => mm_interconnect_0_ip_pwm_0_avs_s0_read, -- .read
ip_pwm_0_avs_s0_readdata => mm_interconnect_0_ip_pwm_0_avs_s0_readdata, -- .readdata
ip_pwm_0_avs_s0_writedata => mm_interconnect_0_ip_pwm_0_avs_s0_writedata, -- .writedata
ip_pwm_0_avs_s0_waitrequest => mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address, -- jtag_uart_0_avalon_jtag_slave.address
jtag_uart_0_avalon_jtag_slave_write => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write, -- .write
jtag_uart_0_avalon_jtag_slave_read => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read, -- .read
jtag_uart_0_avalon_jtag_slave_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
timer_ms_s1_address => mm_interconnect_0_timer_ms_s1_address, -- timer_ms_s1.address
timer_ms_s1_write => mm_interconnect_0_timer_ms_s1_write, -- .write
timer_ms_s1_readdata => mm_interconnect_0_timer_ms_s1_readdata, -- .readdata
timer_ms_s1_writedata => mm_interconnect_0_timer_ms_s1_writedata, -- .writedata
timer_ms_s1_chipselect => mm_interconnect_0_timer_ms_s1_chipselect, -- .chipselect
timer_us_s1_address => mm_interconnect_0_timer_us_s1_address, -- timer_us_s1.address
timer_us_s1_write => mm_interconnect_0_timer_us_s1_write, -- .write
timer_us_s1_readdata => mm_interconnect_0_timer_us_s1_readdata, -- .readdata
timer_us_s1_writedata => mm_interconnect_0_timer_us_s1_writedata, -- .writedata
timer_us_s1_chipselect => mm_interconnect_0_timer_us_s1_chipselect, -- .chipselect
uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address
uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write
uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read
uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect
);
irq_mapper : component niosii_irq_mapper
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_002_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq
receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
irq_synchronizer : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c1_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_001_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_002_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver1_irq -- sender.irq
);
irq_synchronizer_001 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c2_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_003_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_002_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_001_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver2_irq -- sender.irq
);
irq_synchronizer_002 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c2_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_003_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_002_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_002_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver3_irq -- sender.irq
);
rst_controller : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c1_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_002 : component niosii_rst_controller_002
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_002_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_002_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_003 : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c2_clk, -- clk.clk
reset_out => rst_controller_003_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read;
mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write;
mm_interconnect_0_timer_us_s1_write_ports_inv <= not mm_interconnect_0_timer_us_s1_write;
mm_interconnect_0_timer_ms_s1_write_ports_inv <= not mm_interconnect_0_timer_ms_s1_write;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
rst_controller_002_reset_out_reset_ports_inv <= not rst_controller_002_reset_out_reset;
rst_controller_003_reset_out_reset_ports_inv <= not rst_controller_003_reset_out_reset;
end architecture rtl; -- of niosii
| mit | 54050192702ff11279f025d6e59e411c | 0.45977 | 3.746722 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/src/gpio-ext.vhd | 1 | 6,472 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DSP-Crowd project --
-- https://www.dsp-crowd.com --
-- --
-- Author(s): --
-- - Johannes Natter, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2017 Authors and www.dsp-crowd.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gpio_ext is
generic
(
my_id : natural := 0
);
port
(
clock : in std_ulogic;
n_reset_async : in std_ulogic;
spi_cs : in std_ulogic;
data : in std_ulogic_vector(7 downto 0);
data_is_id : in std_ulogic;
data_valid : in std_ulogic;
input_state : out std_ulogic;
input_state_valid : out std_ulogic;
cmd_done : out std_ulogic;
gpio_in : in std_ulogic;
gpio_out : out std_ulogic;
gpio_en : out std_ulogic
);
begin
assert (my_id >= 0)
report "gpio_ext: id must be at least 1"
severity error;
end gpio_ext;
architecture rtl of gpio_ext is
type STATEMACHINE_MAIN_STEP_TYPE is
(
SM_WAIT_SELECTED, SM_GET_CMD, SM_CHECK_CMD, SM_GET_INPUT, SM_GET_DUMMY, SM_SET_OUTPUT, SM_GET_COUNTER_MAX, SM_GET_COUNTER_MID
);
type GPIO_TYPE is
(
GPIO_INPUT, GPIO_OUTPUT, GPIO_PWM
);
subtype BYTE_IDX_TYPE is integer range 0 to 3;
type REG_TYPE is record
sm_step : STATEMACHINE_MAIN_STEP_TYPE;
data : std_ulogic_vector(7 downto 0);
counter : natural;
counter_max : natural;
counter_mid : natural;
byte_idx : BYTE_IDX_TYPE;
tmp : std_ulogic_vector(23 downto 0);
gpio_type : GPIO_TYPE;
gpio : std_ulogic;
end record;
constant RSET_INIT_VAL : REG_TYPE :=
(
sm_step => SM_WAIT_SELECTED,
data => (others => '0'),
counter => 0,
counter_max => 0,
counter_mid => 0,
byte_idx => 0,
tmp => (others => '0'),
gpio_type => GPIO_INPUT,
gpio => '0'
);
signal R, NxR : REG_TYPE;
begin
proc_comb: process(R, spi_cs, data, data_is_id, data_valid, gpio_in)
begin
NxR <= R;
input_state <= '0';
input_state_valid <= '0';
cmd_done <= '0';
gpio_out <= R.gpio;
if(R.gpio_type = GPIO_OUTPUT or R.gpio_type = GPIO_PWM)then
gpio_en <= '1';
else
gpio_en <= '0';
end if;
if(R.gpio_type = GPIO_PWM)then
if(R.counter < R.counter_max - 1)then
NxR.counter <= R.counter + 1;
else
NxR.counter <= 0;
end if;
if(R.counter < R.counter_mid)then
NxR.gpio <= '1';
else
NxR.gpio <= '0';
end if;
end if;
case R.sm_step is
when SM_WAIT_SELECTED =>
if(data_is_id = '1' and to_integer(unsigned(data)) = my_id)then
NxR.sm_step <= SM_GET_CMD;
end if;
when SM_GET_CMD =>
if(data_valid = '1')then
NxR.data <= data;
NxR.sm_step <= SM_CHECK_CMD;
end if;
when SM_CHECK_CMD =>
if(R.data(1 downto 0) = "00")then -- read
NxR.gpio_type <= GPIO_INPUT;
NxR.sm_step <= SM_GET_INPUT;
elsif(R.data(1 downto 0) = "01")then -- write
NxR.gpio_type <= GPIO_OUTPUT;
NxR.sm_step <= SM_SET_OUTPUT;
else -- pwm
NxR.byte_idx <= 3;
NxR.sm_step <= SM_GET_COUNTER_MAX;
end if;
when SM_GET_INPUT =>
input_state <= gpio_in;
input_state_valid <= '1';
NxR.sm_step <= SM_GET_DUMMY;
when SM_GET_DUMMY =>
if(data_valid = '1')then
cmd_done <= '1';
NxR.sm_step <= SM_WAIT_SELECTED;
end if;
when SM_SET_OUTPUT =>
if(data_valid = '1')then
cmd_done <= '1';
NxR.gpio <= data(0);
NxR.sm_step <= SM_WAIT_SELECTED;
end if;
when SM_GET_COUNTER_MAX =>
if(data_valid = '1')then
if(R.byte_idx = 0)then
NxR.counter_max <= to_integer(unsigned(R.tmp & data));
NxR.byte_idx <= 3;
NxR.sm_step <= SM_GET_COUNTER_MID;
else
NxR.tmp(8 * R.byte_idx - 1 downto 8 * (R.byte_idx - 1)) <= data;
NxR.byte_idx <= R.byte_idx - 1;
end if;
end if;
when SM_GET_COUNTER_MID =>
if(data_valid = '1')then
if(R.byte_idx = 0)then
NxR.counter_mid <= to_integer(unsigned(R.tmp & data));
NxR.gpio_type <= GPIO_PWM;
cmd_done <= '1';
NxR.sm_step <= SM_WAIT_SELECTED;
else
NxR.tmp(8 * R.byte_idx - 1 downto 8 * (R.byte_idx - 1)) <= data;
NxR.byte_idx <= R.byte_idx - 1;
end if;
end if;
when others =>
NxR.sm_step <= SM_WAIT_SELECTED;
end case;
if(spi_cs = '1')then
NxR.sm_step <= SM_WAIT_SELECTED;
end if;
end process;
proc_reg: process(n_reset_async, clock)
begin
if(n_reset_async = '0')then
R <= RSET_INIT_VAL;
elsif(clock'event and clock = '1')then
R <= NxR;
end if;
end process;
end architecture rtl;
| gpl-2.0 | 3d70dcbeb36878794289f1c902dd6880 | 0.477905 | 3.153996 | false | false | false | false |
FrankBuss/YaGraphCon | spartan3e/src/Framebuffer.vhd | 1 | 1,789 | -- Copyright (c) 2009 Frank Buss ([email protected])
-- See license.txt for license
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
use work.YaGraphConPackage.all;
entity Framebuffer is
generic(
ADDRESS_WIDTH: natural;
BIT_DEPTH: natural
);
port(
clock: in std_logic;
-- 1st RAM port for read-only access
readAddress1: in unsigned(ADDRESS_WIDTH-1 downto 0);
q1: out unsigned(BIT_DEPTH-1 downto 0);
-- 2nd RAM port for read-only access
readAddress2: in unsigned(ADDRESS_WIDTH-1 downto 0);
q2: out unsigned(BIT_DEPTH-1 downto 0);
-- 3rd RAM port for write access
writeAddress: in unsigned(ADDRESS_WIDTH-1 downto 0);
data: in unsigned(BIT_DEPTH-1 downto 0);
writeEnable: in std_logic
);
end entity Framebuffer;
architecture rtl of Framebuffer is
-- infering template for Xilinx block RAM
constant ADDR_WIDTH : integer := ADDRESS_WIDTH;
constant DATA_WIDTH : integer := BIT_DEPTH;
type framebufferType is array (2**ADDR_WIDTH-1 downto 0) of unsigned(DATA_WIDTH-1 downto 0);
signal framebufferRam1: framebufferType;
signal framebufferRam2: framebufferType;
begin
-- infering template for Xilinx block RAM
ram1: process(clock)
begin
if rising_edge(clock) then
--if (clock'event and clock = '1') then
if writeEnable = '1' then
framebufferRam1(to_integer(writeAddress)) <= data;
end if;
q1 <= framebufferRam1(to_integer(readAddress1));
end if;
end process;
-- infering template for Xilinx block RAM
ram2: process(clock)
begin
if rising_edge(clock) then
--if (clock'event and clock = '1') then
if writeEnable = '1' then
framebufferRam2(to_integer(writeAddress)) <= data;
end if;
q2 <= framebufferRam2(to_integer(readAddress2));
end if;
end process;
end architecture rtl;
| mit | 1072b65a7e51fa130805ec758fe51e53 | 0.721073 | 3.211849 | false | false | false | false |
pkerling/ethernet_mac | utility.vhd | 1 | 2,361 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Utility functions
library ieee;
use ieee.std_logic_1164.all;
package utility is
-- Return the reverse of the given vector
function reverse_vector(vec : in std_ulogic_vector) return std_ulogic_vector;
-- Return a vector with the bytes in opposite order but the content of the bytes unchanged (e.g. for big/little endian conversion)
function reverse_bytes(vec : in std_ulogic_vector) return std_ulogic_vector;
-- Extract a byte out of a vector
function extract_byte(vec : in std_ulogic_vector; byteno : in natural) return std_ulogic_vector;
-- Set a byte in a vector
procedure set_byte(vec : inout std_ulogic_vector; byteno : in natural; value : in std_ulogic_vector(7 downto 0));
end package;
package body utility is
function reverse_vector(vec : in std_ulogic_vector) return std_ulogic_vector is
variable result : std_ulogic_vector(vec'range);
alias rev_vec : std_ulogic_vector(vec'reverse_range) is vec;
begin
for i in rev_vec'range loop
result(i) := rev_vec(i);
end loop;
return result;
end function;
function reverse_bytes(vec : in std_ulogic_vector) return std_ulogic_vector is
variable result : std_ulogic_vector(vec'range);
begin
assert vec'length mod 8 = 0 report "Vector length must be a multiple of 8 for byte reversal" severity failure;
assert vec'low = 0 report "Vector must start at 0 for byte reversal" severity failure;
for byte in 0 to vec'high / 8 loop
set_byte(result, vec'high / 8 - byte, extract_byte(vec, byte));
end loop;
return result;
end function;
function extract_byte(vec : in std_ulogic_vector; byteno : in natural) return std_ulogic_vector is
begin
-- Support both vector directions
if vec'ascending then
return vec(byteno * 8 to (byteno + 1) * 8 - 1);
else
return vec((byteno + 1) * 8 - 1 downto byteno * 8);
end if;
end function;
procedure set_byte(vec : inout std_ulogic_vector; byteno : in natural; value : in std_ulogic_vector(7 downto 0)) is
begin
-- Support both vector directions
if vec'ascending then
vec(byteno * 8 to (byteno + 1) * 8 - 1) := value;
else
vec((byteno + 1) * 8 - 1 downto byteno * 8) := value;
end if;
end procedure;
end package body;
| bsd-3-clause | e62aa49aefab3df91b1b808fec8a3990 | 0.717916 | 3.297486 | false | false | false | false |
PsiStarPsi/firmware-general | General/sim/EncodeDecode8b10b.vhd | 1 | 8,592 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:46:53 12/30/2015
-- Design Name:
-- Module Name: C:/Users/Kurtis/Desktop/mtcSvn/temp/LucaIRS3D_Ethernet_firmware/src/firmware-general/General/sim/EncodeDecode8b10b.vhd
-- Project Name: scrodMtc
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Encode8b10b
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY std;
use std.textio.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_textio.all; -- I/O for logic types
use work.utilitypkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY EncodeDecode8b10b IS
END EncodeDecode8b10b;
ARCHITECTURE behavior OF EncodeDecode8b10b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Encode8b10b
PORT(
clk : IN std_logic;
clkEn : IN std_logic;
rst : IN std_logic;
dataIn : IN std_logic_vector(7 downto 0);
dataKIn : IN std_logic;
dispIn : IN std_logic;
dataOut : OUT std_logic_vector(9 downto 0);
dispOut : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal clkEn : std_logic := '0';
signal rst : std_logic := '0';
signal encodeDataIn : std_logic_vector(7 downto 0) := (others => '0');
signal encodeDataKIn : std_logic := '0';
--Outputs
signal encodeDataOut : std_logic_vector(9 downto 0);
signal encodeDispOut : std_logic;
signal decodeDispOut : std_logic;
signal decodeDataOut : std_logic_vector(7 downto 0) := (others => '0');
signal decodeDataKOut : std_logic;
signal decodeCodeErr : std_logic;
signal decodeDispErr : std_logic;
signal encodeVDataOut : std_logic_vector(9 downto 0);
signal encodeVDispIn : std_logic := '0';
signal encodeVDispOut : std_logic := '0';
signal decodeVDispIn : std_logic := '0';
signal decodeVDispOut : std_logic := '0';
signal decodeVDataOut : std_logic_vector(7 downto 0) := (others => '0');
signal decodeVDataKOut : std_logic;
signal decodeVCodeErr : std_logic;
signal decodeVDispErr : std_logic;
signal encodeDataInPipe : Word8Array(1 downto 0) := (others => (others => '0'));
signal encodeDataKInPipe : std_logic_vector(1 downto 0) := (others => '0');
signal counter : integer range 0 to 255 := 0;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant clkEn_period : time := 10 ns;
BEGIN
-- Instantiate the Units Under Test (UUTs)
U_Encode8b10b : entity work.Encode8b10b
PORT MAP (
clk => clk,
clkEn => clkEn,
rst => rst,
dataIn => encodeDataIn,
dataKIn => encodeDataKIn,
dispIn => encodeDispOut,
dataOut => encodeDataOut,
dispOut => encodeDispOut
);
U_Decode8b10b : entity work.Decode8b10b
PORT MAP (
clk => clk,
clkEn => clkEn,
rst => rst,
dataIn => encodeDataOut,
dispIn => decodeDispOut,
dataOut => decodeDataOut,
dataKOut => decodeDataKOut,
dispOut => decodeDispOut,
codeErr => decodeCodeErr,
dispErr => decodeDispErr
);
-- Comparisons to original verilog
U_VEncode8b10b : entity work.encode
PORT MAP (
dataIn(8) => encodeDataKInPipe(1),
dataIn(7 downto 0) => encodeDataInPipe(1),
dispIn => encodeVDispIn,
dataOut => encodeVDataOut,
dispOut => encodeVDispOut
);
U_VDecode8b10b : entity work.decode
PORT MAP (
dataIn => encodeVDataOut,
dispIn => decodeVDispIn,
dataOut(8) => decodeVDataKOut,
dataOut(7 downto 0) => decodeVDataOut,
dispOut => decodeVDispOut,
code_err => decodeVCodeErr,
disp_err => decodeVDispErr
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
clkEn_process :process
begin
clkEn <= '0';
wait for clkEn_period/2;
clkEn <= '1';
wait for clkEn_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
rst <= '0';
-- insert stimulus here
wait;
end process;
process(clk)
variable my_line : line;
variable counter : integer range 0 to 255;
variable kValue : std_logic := '0';
begin
if rising_edge(clk) then
if rst = '1' then
encodeDataIn <= (others => '0');
encodeDataKIn <= '0';
else
encodeDataInPipe(0) <= encodeDataIn;
encodeDataInPipe(1) <= encodeDataInPipe(0);
encodeDataKInPipe(0) <= encodeDataKIn;
encodeDataKInPipe(1) <= encodeDataKInPipe(0);
encodeDataKIn <= kValue;
if kValue = '0' then
encodeDataIn <= conv_std_logic_vector(255-counter, 8);
else
case(counter) is
when 0 => encodeDataIn <= conv_std_logic_vector( 28, 8);
when 1 => encodeDataIn <= conv_std_logic_vector( 60, 8);
when 2 => encodeDataIn <= conv_std_logic_vector( 92, 8);
when 3 => encodeDataIn <= conv_std_logic_vector(124, 8);
when 4 => encodeDataIn <= conv_std_logic_vector(156, 8);
when 5 => encodeDataIn <= conv_std_logic_vector(188, 8);
when 6 => encodeDataIn <= conv_std_logic_vector(220, 8);
when 7 => encodeDataIn <= conv_std_logic_vector(252, 8);
when 8 => encodeDataIn <= conv_std_logic_vector(247, 8);
when 9 => encodeDataIn <= conv_std_logic_vector(251, 8);
when 10 => encodeDataIn <= conv_std_logic_vector(253, 8);
when 11 => encodeDataIn <= conv_std_logic_vector(254, 8);
when others => encodeDataIn <= x"BC";
end case;
end if;
if kValue = '0' then
if (counter < 255) then
counter := counter + 1;
else
counter := 0;
kValue := '1';
end if;
else
if (counter < 255) then
-- if (counter < 11) then
counter := counter + 1;
else
counter := 0;
kValue := '0';
end if;
end if;
write(my_line, string'("IN: "));
hwrite(my_line, encodeDataInPipe(1));
write(my_line, string'(","));
write(my_line, encodeDataKInPipe(1));
write(my_line, string'(" OUT: "));
hwrite(my_line, decodeDataOut);
write(my_line, string'(","));
write(my_line, decodeDataKOut);
if encodeDataInPipe(1) /= decodeDataOut then
write(my_line, string'(" <-- ERROR"));
end if;
writeline(output, my_line);
end if;
end if;
end process;
process(clk) begin
if rising_edge(clk) then
encodeVDispIn <= encodeVDispOut;
decodeVDispIn <= decodeVDispOut;
end if;
end process;
END;
| lgpl-2.1 | 7da5933727a65da45c4d0386df31f2dd | 0.529097 | 3.985158 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/Encode8b10b.vhd | 1 | 6,211 | -- Translated to vhdl from verilog module encode_8b10b.v
-- by Kurtis Nishimura, 2015
-- from source obtained at:
--
-- http://asics.chuckbenz.com/encode.v
--
-- Original copyright information:
-- // Chuck Benz, Hollis, NH Copyright (c)2002
-- //
-- // The information and description contained herein is the
-- // property of Chuck Benz.
-- //
-- // Permission is granted for any reuse of this information
-- // and description as long as this copyright notice is
-- // preserved. Modifications may be made as long as this
-- // notice is preserved.
--
-- // per Widmer and Franaszek
--
--
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.UtilityPkg.all;
entity Encode8b10b is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
clk : in sl;
clkEn : in sl := '1';
rst : in sl := '0';
dataIn : in slv(7 downto 0);
dataKIn : in sl;
dispIn : in sl;
dataOut : out slv(9 downto 0);
dispOut : out sl
);
end Encode8b10b;
architecture rtl of Encode8b10b is
signal ai, bi, ci, di, ei, fi, gi, hi, ki : sl;
signal aeqb, ceqd, l22, l40, l04, l13, l31 : sl;
signal ao, bo, co, do, eo, fo, go, ho, io, jo : sl;
signal pds16, nds16 : sl;
signal ndos6, pdos6 : sl;
signal alt7 : sl;
signal nd1s4, pd1s4 : sl;
signal ndos4, pdos4 : sl;
signal illegalk : sl;
signal compls6, disp6, compls4 : sl;
signal dispOutRaw : sl;
signal dataOutRaw : slv(9 downto 0);
begin
-- Rename variables to abcdefgh format
ai <= dataIn(0);
bi <= dataIn(1);
ci <= dataIn(2);
di <= dataIn(3);
ei <= dataIn(4);
fi <= dataIn(5);
gi <= dataIn(6);
hi <= dataIn(7);
ki <= dataKIn;
-- Combinatorial calculations
aeqb <= (ai and bi) or ( not(ai) and not(bi) );
ceqd <= (ci and di) or ( not(ci) and not(di) );
l22 <= (ai and bi and not(ci) and not(di)) or
(ci and di and not(ai) and not(bi)) or
(not(aeqb) and not(ceqd));
l40 <= ai and bi and ci and di;
l04 <= not(ai) and not(bi) and not(ci) and not(di);
l13 <= (not(aeqb) and not(ci) and not(di)) or
(not(ceqd) and not(ai) and not(bi));
l31 <= (not(aeqb) and ci and di) or
(not(ceqd) and ai and bi);
-- 5B/6B encoding
ao <= ai;
bo <= (bi and not(l40)) or (l04);
co <= l04 or ci or (ei and di and not(ci) and not(bi) and not(ai));
do <= di and not(ai and bi and ci);
eo <= (ei or l13) and not( ei and di and not(ci) and not(bi) and not(ai) );
io <= (l22 and not(ei)) or
(ei and not(di) and not(ci) and not(ai and bi)) or -- D16, D17, D18
(ei and l40) or
(ki and ei and di and ci and not(bi) and not(ai)) or -- K.28
(ei and not(di) and ci and not(bi) and not(ai));
-- pds16 indicates cases where d-1 is assumed + to get our encoded value
pds16 <= (ei and di and not(ci) and not(bi) and not(ai)) or (not(ei) and not(l22) and not(l31));
-- nds16 indicates cases where d-1 is assumed - to get our encoded value
nds16 <= ki or
(ei and not(l22) and not(l13)) or
(not(ei) and not(di) and ci and bi and ai);
-- ndos6 is pds16 cases where d-1 is + yields - disp out - all of them
ndos6 <= pds16 ;
-- pdos6 is nds16 cases where d-1 is - yields + disp out - all but one
pdos6 <= ki or
(ei and not(l22) and not(l13));
-- some Dx.7 and all Kx.7 cases result in run length of 5 case unless
-- an alternate coding is used (referred to as Dx.A7, normal is Dx.P7)
-- specifically, D11, D13, D14, D17, D18, D19.
alt7 <= fi and gi and hi and (ki or (not(ei) and di and l31)) when dispIn = '1' else
fi and gi and hi and (ki or (ei and not(di) and l13));
fo <= fi and not(alt7);
go <= gi or (not(fi) and not(gi) and not(hi));
ho <= hi;
jo <= (not(hi) and(gi xor fi)) or alt7;
-- nd1s4 is cases where d-1 is assumed - to get our encoded value
nd1s4 <= fi and gi;
-- pd1s4 is cases where d-1 is assumed + to get our encoded value
pd1s4 <= (not(fi) and not(gi)) or (ki and ((fi and not(gi)) or (not(fi) and gi)));
-- ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some
ndos4 <= (not(fi) and not(gi));
-- pdos4 is nd1s4 cases where d-1 is - yields + disp out
pdos4 <= fi and gi and hi;
-- only legal K codes are K28.0->.7, K23/27/29/30.7
-- K28.0->7 is ei=di=ci=1,bi=ai=0
-- K23 is 10111
-- K27 is 11011
-- K29 is 11101
-- K30 is 11110 - so K23/27/29/30 are ei & l31
illegalk <= ki and
(ai or bi or not(ci) or not(ei)) and -- Not K28.0->7
(not(fi) or not(gi) or not(hi) or not(ei) or not(l31)); -- Not K23/27/29/30.7
-- now determine whether to do the complementing
-- complement if prev disp is - and pds16 is set, or + and nds16 is set
compls6 <= (pds16 and not(dispin)) or (nds16 and dispin);
-- disparity out of 5b6b is disp in with pdso6 and ndso6
-- pds16 indicates cases where d-1 is assumed + to get our encoded value
-- ndos6 is cases where d-1 is + yields - disp out
-- nds16 indicates cases where d-1 is assumed - to get our encoded value
-- pdos6 is cases where d-1 is - yields + disp out
-- disp toggles in all ndis16 cases, and all but that 1 nds16 case
disp6 <= dispin xor (ndos6 or pdos6);
compls4 <= (pd1s4 and not(disp6)) or (nd1s4 and disp6);
-- Assign disparity and data out
dispOutRaw <= disp6 xor (ndos4 or pdos4);
-- Is the bit order right here?
dataOutRaw(9) <= jo xor compls4;
dataOutRaw(8) <= ho xor compls4;
dataOutRaw(7) <= go xor compls4;
dataOutRaw(6) <= fo xor compls4;
dataOutRaw(5) <= io xor compls6;
dataOutRaw(4) <= eo xor compls6;
dataOutRaw(3) <= do xor compls6;
dataOutRaw(2) <= co xor compls6;
dataOutRaw(1) <= bo xor compls6;
dataOutRaw(0) <= ao xor compls6;
process(clk) begin
if rising_edge(clk) then
if rst = '1' then
dataOut <= (others => '0');
dispOut <= '0';
elsif clkEn = '1' then
dataOut <= dataOutRaw;
dispOut <= dispOutRaw;
end if;
end if;
end process;
end rtl;
| lgpl-2.1 | f150c06ba406954b55b618ae5a1b6339 | 0.589277 | 3.003385 | false | false | false | false |
DSP-Crowd/software | _install/de0_nano/src/tbd_rr_base_tb.vhd | 1 | 6,732 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_rr_base is
end tb_rr_base;
architecture bhv of tb_rr_base is
----------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------
-- User
constant c_clk_frequency : natural := 50E6;
constant c_use_issi_sdram : std_ulogic := '1';
constant c_use_sdram_pll : std_ulogic := '1';
-- Derived
----------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------
signal clk : std_ulogic := '1';
signal keys : std_ulogic_vector(1 downto 0);
signal switches : std_ulogic_vector(3 downto 0);
signal leds : std_ulogic_vector(7 downto 0);
signal gdb_tx : std_ulogic := '1';
signal gdb_rx : std_ulogic;
signal spi_cs : std_ulogic_vector(3 downto 0);
signal spi_miso : std_ulogic := '0';
signal spi_mosi : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_epcs_miso : std_ulogic;
signal spi_epcs_mosi : std_ulogic;
signal spi_epcs_clk : std_ulogic;
signal enc_clk : std_ulogic;
signal sdram_addr : std_logic_vector(12 downto 0);
signal sdram_ba : std_logic_vector(1 downto 0);
signal sdram_cke : std_logic;
signal sdram_clk : std_logic;
signal sdram_cs_n : std_logic;
signal sdram_dq : std_logic_vector(15 downto 0);
signal sdram_dqm : std_logic_vector(1 downto 0);
signal sdram_cas_n : std_logic;
signal sdram_ras_n : std_logic;
signal sdram_we_n : std_logic;
signal sdram_ctrl_str : string(1 to 5);
begin
clk <= not clk after 1E9 ns / (2 * c_clk_frequency);
keys <= (others => '1');
switches <= (others => '0');
testbed: entity work.tbd_de0_nano_linux(rtl)
generic map
(
use_sdram_pll => c_use_sdram_pll
)
port map
(
clock_50mhz => clk,
keys => keys,
switches => switches,
leds => leds,
uart_rx => gdb_tx,
uart_tx => gdb_rx,
spi_cs => spi_cs,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
spi_clk => spi_clk,
spi_epcs_miso => spi_epcs_miso,
spi_epcs_mosi => spi_epcs_mosi,
spi_epcs_clk => spi_epcs_clk,
enc_clk => enc_clk,
sdram_addr => sdram_addr,
sdram_ba => sdram_ba,
sdram_cke => sdram_cke,
sdram_clk => sdram_clk,
sdram_cs_n => sdram_cs_n,
sdram_dq => sdram_dq,
sdram_dqm => sdram_dqm,
sdram_cas_n => sdram_cas_n,
sdram_ras_n => sdram_ras_n,
sdram_we_n => sdram_we_n
);
altera_sdram : if (c_use_issi_sdram = '0') generate
eSDRAM : entity work.sdram_0_test_component(europa)
port map
(
-- inputs:
clk => sdram_clk,
ZS_ADDR => sdram_addr,
zs_ba => sdram_ba,
zs_cas_n => sdram_cas_n,
zs_cke => sdram_cke,
zs_cs_n => sdram_cs_n,
zs_dqm => sdram_dqm,
zs_ras_n => sdram_ras_n,
zs_we_n => sdram_we_n,
-- outputs:
zs_dq => sdram_dq
);
end generate;
issi_sdram : if (c_use_issi_sdram = '1') generate
eSDRAM_issi : entity work.IS42S16160
port map
(
Dq => sdram_dq,
Addr => sdram_addr,
Ba => sdram_ba,
Clk => sdram_clk,
Cke => sdram_cke,
Cs_n => sdram_cs_n,
Ras_n => sdram_ras_n,
Cas_n => sdram_cas_n,
We_n => sdram_we_n,
Dqm => sdram_dqm
);
end generate;
sdram_ctrl_debug: process(sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n)
variable ctrl_vect : std_logic_vector(2 downto 0);
begin
ctrl_vect := sdram_ras_n & sdram_cas_n & sdram_we_n;
if(sdram_cs_n = '1')then
sdram_ctrl_str <= "DESL ";
else
case ctrl_vect is
when "111" =>
sdram_ctrl_str <= "NOP ";
when "101" =>
sdram_ctrl_str <= "READ ";
when "100" =>
sdram_ctrl_str <= "WRITE";
when "011" =>
sdram_ctrl_str <= "ACT ";
when "010" =>
sdram_ctrl_str <= "PALL ";
when "001" =>
sdram_ctrl_str <= "REF ";
when "000" =>
sdram_ctrl_str <= "MRS ";
when others =>
sdram_ctrl_str <= "??? ";
end case;
end if;
end process;
end bhv;
| gpl-2.0 | c8b4913bfbdbf19883bbbb02b496e060 | 0.41934 | 3.756696 | false | false | false | false |
pkerling/ethernet_mac | tx_fifo_adapter.vhd | 1 | 4,834 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Read packets from a TX FIFO and send them to framing
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
entity tx_fifo_adapter is
port(
-- Interface to framing layer
mac_tx_reset_i : in std_ulogic;
mac_tx_clock_i : in std_ulogic;
mac_tx_enable_o : out std_ulogic;
mac_tx_data_o : out t_ethernet_data;
mac_tx_byte_sent_i : in std_ulogic;
mac_tx_busy_i : in std_ulogic;
-- FIFO interface
rd_en_o : out std_ulogic;
data_i : in t_ethernet_data;
empty_i : in std_ulogic;
read_count_i : in unsigned
);
end entity;
architecture rtl of tx_fifo_adapter is
type t_state is (
READ_SIZE_HIGH,
WAIT_READ_SIZE_LOW,
READ_SIZE_LOW,
WAIT_DATA_COUNT1,
WAIT_DATA_COUNT2,
WAIT_PACKET,
WAIT_DATA_READ,
READ_DATA,
SEND_DATA
);
constant TX_PACKET_SIZE_BITS : positive := 12;
constant TX_MAX_PACKET_SIZE : positive := ((2 ** TX_PACKET_SIZE_BITS) - 1);
signal state : t_state := READ_SIZE_HIGH;
signal remaining_packet_size : unsigned(TX_PACKET_SIZE_BITS - 1 downto 0);
signal next_data : t_ethernet_data := (others => '0');
signal rd_en : std_ulogic := '0';
begin
rd_en_o <= rd_en;
send_proc : process(mac_tx_reset_i, mac_tx_clock_i)
begin
if mac_tx_reset_i = '1' then
state <= READ_SIZE_HIGH;
rd_en <= '0';
mac_tx_enable_o <= '0';
elsif rising_edge(mac_tx_clock_i) then
rd_en <= '0';
mac_tx_enable_o <= '0';
case state is
when READ_SIZE_HIGH =>
-- Wait for FIFO nonempty
if empty_i = '0' then
-- Read packet size high byte
remaining_packet_size(TX_PACKET_SIZE_BITS - 1 downto 8) <= unsigned(data_i(TX_PACKET_SIZE_BITS - 1 - 8 downto 0));
-- Move FIFO to next byte
rd_en <= '1';
state <= WAIT_READ_SIZE_LOW;
end if;
when WAIT_READ_SIZE_LOW =>
-- Wait for EMPTY flag and data to update
state <= READ_SIZE_LOW;
when READ_SIZE_LOW =>
-- Wait for FIFO nonempty
if empty_i = '0' then
-- Read packet size low byte
remaining_packet_size(7 downto 0) <= unsigned(data_i);
-- Move FIFO to next byte
rd_en <= '1';
state <= WAIT_DATA_COUNT1;
end if;
when WAIT_DATA_COUNT1 =>
-- The FIFO read data count can over-report for up to two clock cycles according
-- to XILINX documentation. Make sure this doesn't happen here.
state <= WAIT_DATA_COUNT2;
when WAIT_DATA_COUNT2 =>
state <= WAIT_PACKET;
when WAIT_PACKET =>
-- Check for obviously wrong frame size to avoid lock-up
if remaining_packet_size = 0 then
-- Try again
state <= READ_SIZE_HIGH;
else
-- Wait for all data available and TX idle
if read_count_i >= remaining_packet_size and mac_tx_busy_i = '0' then
-- Remember the first byte
mac_tx_data_o <= data_i;
-- Start transmission already, delay through framing is long enough to not miss the first tx_byte_sent
mac_tx_enable_o <= '1';
-- Move FIFO on to the second byte
rd_en <= '1';
if remaining_packet_size = 1 then
-- No data to prefetch
state <= SEND_DATA;
else
-- Prefetch data
state <= WAIT_DATA_READ;
end if;
end if;
end if;
when WAIT_DATA_READ =>
-- Third byte
rd_en <= '1';
state <= READ_DATA;
mac_tx_enable_o <= '1';
when READ_DATA =>
next_data <= data_i;
state <= SEND_DATA;
mac_tx_enable_o <= '1';
when SEND_DATA =>
mac_tx_enable_o <= '1';
if mac_tx_byte_sent_i = '1' then
if remaining_packet_size = 1 then
-- This was the last byte
mac_tx_enable_o <= '0';
state <= READ_SIZE_HIGH;
else
if rd_en = '1' then
-- The buffer is exhausted if we've supplied its value
-- in the previous clock cycle, now supply data directly from the FIFO
mac_tx_data_o <= data_i;
else
-- Pass the buffered byte on
mac_tx_data_o <= next_data;
next_data <= data_i;
end if;
-- Get one byte out of FIFO
if remaining_packet_size >= 3 then
rd_en <= '1';
end if;
remaining_packet_size <= remaining_packet_size - 1;
end if;
end if;
end case;
end if;
end process;
end architecture;
| bsd-3-clause | dde931867c560fe7ca62e7978a152c2e | 0.557509 | 3.21196 | false | false | false | false |
Dragonturtle/SHERPA | HDL/FPGALink/seven_seg.vhdl | 1 | 3,125 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity seven_seg is
generic (
-- This can be overridden to change the refresh rate. The anode pattern will change at a
-- frequency given by F(clk_in) / (2**COUNTER_WIDTH). So for a 50MHz clk_in and
-- COUNTER_WIDTH=18, the anode pattern changes at ~191Hz, which means each digit gets
-- refreshed at ~48Hz.
COUNTER_WIDTH : integer := 16
);
port(
clk_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
dots_in : in std_logic_vector(3 downto 0);
segs_out : out std_logic_vector(7 downto 0);
anodes_out : out std_logic_vector(3 downto 0)
);
end entity;
architecture rtl of seven_seg is
signal count : unsigned(COUNTER_WIDTH-1 downto 0) := (others => '0');
signal count_next : unsigned(COUNTER_WIDTH-1 downto 0);
signal anodeSelect : std_logic_vector(1 downto 0);
signal nibble : std_logic_vector(3 downto 0);
signal segs : std_logic_vector(6 downto 0);
signal dot : std_logic;
begin
-- Infer counter register
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
count <= count_next;
end if;
end process;
-- Increment counter and derive anode select from top two bits
count_next <= count + 1;
anodeSelect <= std_logic_vector(count(COUNTER_WIDTH-1 downto COUNTER_WIDTH-2));
-- Drive anodes
with anodeSelect select anodes_out <=
"0111" when "00",
"1011" when "01",
"1101" when "10",
"1110" when others;
-- Select the appropriate bit from dots_in
with anodeSelect select dot <=
not(dots_in(3)) when "00",
not(dots_in(2)) when "01",
not(dots_in(1)) when "10",
not(dots_in(0)) when others;
-- Choose a nibble to display
with anodeSelect select nibble <=
data_in(15 downto 12) when "00",
data_in(11 downto 8) when "01",
data_in(7 downto 4) when "10",
data_in(3 downto 0) when others;
-- Decode chosen nibble
with nibble select segs <=
"1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
-- Drive segs_out
segs_out <= dot & segs;
end architecture;
| gpl-3.0 | 01db04d8a447f573693e0c6d65eb1211 | 0.67744 | 3.15338 | false | false | false | false |
FrankBuss/YaGraphCon | spartan3e/src/rs232_sender.vhd | 1 | 1,739 | -- Copyright (c) 2009 Frank Buss ([email protected])
-- See license.txt for license
--
-- Simple RS232 sender with generic baudrate and 8N1 mode.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE work.all;
entity rs232_sender is
generic(
-- clock frequency, in hz
SYSTEM_SPEED,
-- baudrate, in bps
BAUDRATE: integer
);
port(
clock: in std_logic;
-- RS232 for sending
data: in unsigned(7 downto 0);
-- RS232 TX pin
tx: out std_logic;
-- set this for one clock pulse to 1 for sending the data
sendTrigger: in std_logic;
-- this is set for one clock pulse to 1, when the data was sent
dataSent: out std_logic
);
end entity rs232_sender;
architecture rtl of rs232_sender is
constant MAX_COUNTER: natural := SYSTEM_SPEED / BAUDRATE;
signal baudrateCounter: natural range 0 to MAX_COUNTER := 0;
signal bitCounter: natural range 0 to 9 := 0;
signal shiftRegister: unsigned(9 downto 0) := (others => '0');
signal dataSendingStarted: std_logic := '0';
begin
process(clock)
begin
if rising_edge(clock) then
dataSent <= '0';
if dataSendingStarted = '1' then
if baudrateCounter = 0 then
tx <= shiftRegister(0);
shiftRegister <= shift_right(shiftRegister, 1);
if bitCounter > 0 then
bitCounter <= bitCounter - 1;
else
dataSendingStarted <= '0';
dataSent <= '1';
end if;
baudrateCounter <= MAX_COUNTER;
else
baudrateCounter <= baudrateCounter - 1;
end if;
else
tx <= '1';
if sendTrigger = '1' then
shiftRegister <= '1' & data & '0';
bitCounter <= 9;
baudrateCounter <= 0;
dataSendingStarted <= '1';
end if;
end if;
end if;
end process;
end architecture rtl;
| mit | 080fff37c5d78ef9734e6144a04e3eb8 | 0.651524 | 3.226345 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/niosii/synthesis/niosii.vhd | 1 | 106,835 | -- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
epcs_flash_dclk : out std_logic; -- epcs_flash.dclk
epcs_flash_sce : out std_logic; -- .sce
epcs_flash_sdo : out std_logic; -- .sdo
epcs_flash_data0 : in std_logic := '0'; -- .data0
ip_pwm_dir : out std_logic_vector(1 downto 0); -- ip_pwm.dir
ip_pwm_out : out std_logic_vector(1 downto 0); -- .out
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- pio_0_external_connection.export
reset_reset_n : in std_logic := '0'; -- reset.reset_n
uart_0_rxd : in std_logic := '0'; -- uart_0.rxd
uart_0_txd : out std_logic -- .txd
);
end entity niosii;
architecture rtl of niosii is
component niosii_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
c2 : out std_logic; -- clk
c3 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component niosii_altpll_0;
component niosii_epcs_flash_controller_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
chipselect : in std_logic := 'X'; -- chipselect
dataavailable : out std_logic; -- dataavailable
endofpacket : out std_logic; -- endofpacket
read_n : in std_logic := 'X'; -- read_n
readdata : out std_logic_vector(31 downto 0); -- readdata
readyfordata : out std_logic; -- readyfordata
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
irq : out std_logic; -- irq
dclk : out std_logic; -- export
sce : out std_logic; -- export
sdo : out std_logic; -- export
data0 : in std_logic := 'X' -- export
);
end component niosii_epcs_flash_controller_0;
component ip_pwm_top is
port (
avs_s0_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
avs_s0_read : in std_logic := 'X'; -- read
avs_s0_readdata : out std_logic_vector(31 downto 0); -- readdata
avs_s0_write : in std_logic := 'X'; -- write
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avs_s0_waitrequest : out std_logic; -- waitrequest
clock_clk : in std_logic := 'X'; -- clk
reset_reset : in std_logic := 'X'; -- reset
pwm_dir : out std_logic_vector(1 downto 0); -- dir
pwm_out : out std_logic_vector(1 downto 0) -- out
);
end component ip_pwm_top;
component niosii_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosii_jtag_uart_0;
component niosii_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(22 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(22 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component niosii_nios2_gen2_0;
component niosii_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosii_onchip_memory2_0;
component niosii_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosii_pio_0;
component niosii_timer_ms is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosii_timer_ms;
component niosii_timer_us is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosii_timer_us;
component niosii_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
chipselect : in std_logic := 'X'; -- chipselect
read_n : in std_logic := 'X'; -- read_n
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
dataavailable : out std_logic; -- dataavailable
readyfordata : out std_logic; -- readyfordata
rxd : in std_logic := 'X'; -- export
txd : out std_logic; -- export
irq : out std_logic -- irq
);
end component niosii_uart_0;
component niosii_mm_interconnect_0 is
port (
altpll_0_c0_clk : in std_logic := 'X'; -- clk
altpll_0_c1_clk : in std_logic := 'X'; -- clk
altpll_0_c2_clk : in std_logic := 'X'; -- clk
altpll_0_c3_clk : in std_logic := 'X'; -- clk
clk_0_clk_clk : in std_logic := 'X'; -- clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
epcs_flash_controller_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
ip_pwm_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
timer_us_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(22 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(22 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address
altpll_0_pll_slave_write : out std_logic; -- write
altpll_0_pll_slave_read : out std_logic; -- read
altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
epcs_flash_controller_0_epcs_control_port_address : out std_logic_vector(8 downto 0); -- address
epcs_flash_controller_0_epcs_control_port_write : out std_logic; -- write
epcs_flash_controller_0_epcs_control_port_read : out std_logic; -- read
epcs_flash_controller_0_epcs_control_port_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
epcs_flash_controller_0_epcs_control_port_writedata : out std_logic_vector(31 downto 0); -- writedata
epcs_flash_controller_0_epcs_control_port_chipselect : out std_logic; -- chipselect
ip_pwm_0_avs_s0_address : out std_logic_vector(7 downto 0); -- address
ip_pwm_0_avs_s0_write : out std_logic; -- write
ip_pwm_0_avs_s0_read : out std_logic; -- read
ip_pwm_0_avs_s0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
ip_pwm_0_avs_s0_writedata : out std_logic_vector(31 downto 0); -- writedata
ip_pwm_0_avs_s0_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_address : out std_logic_vector(0 downto 0); -- address
jtag_uart_0_avalon_jtag_slave_write : out std_logic; -- write
jtag_uart_0_avalon_jtag_slave_read : out std_logic; -- read
jtag_uart_0_avalon_jtag_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_uart_0_avalon_jtag_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(13 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
timer_ms_s1_address : out std_logic_vector(2 downto 0); -- address
timer_ms_s1_write : out std_logic; -- write
timer_ms_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
timer_ms_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
timer_ms_s1_chipselect : out std_logic; -- chipselect
timer_us_s1_address : out std_logic_vector(2 downto 0); -- address
timer_us_s1_write : out std_logic; -- write
timer_us_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
timer_us_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
timer_us_s1_chipselect : out std_logic; -- chipselect
uart_0_s1_address : out std_logic_vector(2 downto 0); -- address
uart_0_s1_write : out std_logic; -- write
uart_0_s1_read : out std_logic; -- read
uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
uart_0_s1_begintransfer : out std_logic; -- begintransfer
uart_0_s1_chipselect : out std_logic -- chipselect
);
end component niosii_mm_interconnect_0;
component niosii_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
receiver2_irq : in std_logic := 'X'; -- irq
receiver3_irq : in std_logic := 'X'; -- irq
receiver4_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosii_irq_mapper;
component altera_irq_clock_crosser is
generic (
IRQ_WIDTH : integer := 1
);
port (
receiver_clk : in std_logic := 'X'; -- clk
sender_clk : in std_logic := 'X'; -- clk
receiver_reset : in std_logic := 'X'; -- reset
sender_reset : in std_logic := 'X'; -- reset
receiver_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
sender_irq : out std_logic_vector(0 downto 0) -- irq
);
end component altera_irq_clock_crosser;
component niosii_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller;
component niosii_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller_001;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [irq_mapper:clk, irq_synchronizer:sender_clk, irq_synchronizer_001:sender_clk, irq_synchronizer_002:sender_clk, irq_synchronizer_003:sender_clk, jtag_uart_0:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_memory2_0:clk, rst_controller_003:clk]
signal altpll_0_c1_clk : std_logic; -- altpll_0:c1 -> [ip_pwm_0:clock_clk, irq_synchronizer:receiver_clk, mm_interconnect_0:altpll_0_c1_clk, pio_0:clk, rst_controller_002:clk, uart_0:clk]
signal altpll_0_c2_clk : std_logic; -- altpll_0:c2 -> [irq_synchronizer_001:receiver_clk, irq_synchronizer_002:receiver_clk, mm_interconnect_0:altpll_0_c2_clk, rst_controller_004:clk, timer_ms:clk, timer_us:clk]
signal altpll_0_c3_clk : std_logic; -- altpll_0:c3 -> [epcs_flash_controller_0:clk, irq_synchronizer_003:receiver_clk, mm_interconnect_0:altpll_0_c3_clk, rst_controller_001:clk]
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(22 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(22 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
signal mm_interconnect_0_ip_pwm_0_avs_s0_readdata : std_logic_vector(31 downto 0); -- ip_pwm_0:avs_s0_readdata -> mm_interconnect_0:ip_pwm_0_avs_s0_readdata
signal mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest : std_logic; -- ip_pwm_0:avs_s0_waitrequest -> mm_interconnect_0:ip_pwm_0_avs_s0_waitrequest
signal mm_interconnect_0_ip_pwm_0_avs_s0_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:ip_pwm_0_avs_s0_address -> ip_pwm_0:avs_s0_address
signal mm_interconnect_0_ip_pwm_0_avs_s0_read : std_logic; -- mm_interconnect_0:ip_pwm_0_avs_s0_read -> ip_pwm_0:avs_s0_read
signal mm_interconnect_0_ip_pwm_0_avs_s0_write : std_logic; -- mm_interconnect_0:ip_pwm_0_avs_s0_write -> ip_pwm_0:avs_s0_write
signal mm_interconnect_0_ip_pwm_0_avs_s0_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:ip_pwm_0_avs_s0_writedata -> ip_pwm_0:avs_s0_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect : std_logic; -- mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_chipselect -> epcs_flash_controller_0:chipselect
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata : std_logic_vector(31 downto 0); -- epcs_flash_controller_0:readdata -> mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_readdata
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_address -> epcs_flash_controller_0:address
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read : std_logic; -- mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_read -> mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read:in
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write : std_logic; -- mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_write -> mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write:in
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_writedata -> epcs_flash_controller_0:writedata
signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata
signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address
signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read
signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write
signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(13 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address
signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in
signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in
signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
signal mm_interconnect_0_timer_us_s1_chipselect : std_logic; -- mm_interconnect_0:timer_us_s1_chipselect -> timer_us:chipselect
signal mm_interconnect_0_timer_us_s1_readdata : std_logic_vector(15 downto 0); -- timer_us:readdata -> mm_interconnect_0:timer_us_s1_readdata
signal mm_interconnect_0_timer_us_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:timer_us_s1_address -> timer_us:address
signal mm_interconnect_0_timer_us_s1_write : std_logic; -- mm_interconnect_0:timer_us_s1_write -> mm_interconnect_0_timer_us_s1_write:in
signal mm_interconnect_0_timer_us_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:timer_us_s1_writedata -> timer_us:writedata
signal mm_interconnect_0_timer_ms_s1_chipselect : std_logic; -- mm_interconnect_0:timer_ms_s1_chipselect -> timer_ms:chipselect
signal mm_interconnect_0_timer_ms_s1_readdata : std_logic_vector(15 downto 0); -- timer_ms:readdata -> mm_interconnect_0:timer_ms_s1_readdata
signal mm_interconnect_0_timer_ms_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:timer_ms_s1_address -> timer_ms:address
signal mm_interconnect_0_timer_ms_s1_write : std_logic; -- mm_interconnect_0:timer_ms_s1_write -> mm_interconnect_0_timer_ms_s1_write:in
signal mm_interconnect_0_timer_ms_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:timer_ms_s1_writedata -> timer_ms:writedata
signal irq_mapper_receiver0_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal irq_mapper_receiver1_irq : std_logic; -- irq_synchronizer:sender_irq -> irq_mapper:receiver1_irq
signal irq_synchronizer_receiver_irq : std_logic_vector(0 downto 0); -- uart_0:irq -> irq_synchronizer:receiver_irq
signal irq_mapper_receiver2_irq : std_logic; -- irq_synchronizer_001:sender_irq -> irq_mapper:receiver2_irq
signal irq_synchronizer_001_receiver_irq : std_logic_vector(0 downto 0); -- timer_us:irq -> irq_synchronizer_001:receiver_irq
signal irq_mapper_receiver3_irq : std_logic; -- irq_synchronizer_002:sender_irq -> irq_mapper:receiver3_irq
signal irq_synchronizer_002_receiver_irq : std_logic_vector(0 downto 0); -- timer_ms:irq -> irq_synchronizer_002:receiver_irq
signal irq_mapper_receiver4_irq : std_logic; -- irq_synchronizer_003:sender_irq -> irq_mapper:receiver4_irq
signal irq_synchronizer_003_receiver_irq : std_logic_vector(0 downto 0); -- epcs_flash_controller_0:irq -> irq_synchronizer_003:receiver_irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [irq_synchronizer_003:receiver_reset, mm_interconnect_0:epcs_flash_controller_0_reset_reset_bridge_in_reset_reset, rst_controller_001_reset_out_reset:in]
signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [epcs_flash_controller_0:reset_req, rst_translator:reset_req_in]
signal rst_controller_002_reset_out_reset : std_logic; -- rst_controller_002:reset_out -> [ip_pwm_0:reset_reset, irq_synchronizer:receiver_reset, mm_interconnect_0:ip_pwm_0_reset_reset_bridge_in_reset_reset, rst_controller_002_reset_out_reset:in]
signal rst_controller_003_reset_out_reset : std_logic; -- rst_controller_003:reset_out -> [irq_mapper:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, irq_synchronizer_002:sender_reset, irq_synchronizer_003:sender_reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_003_reset_out_reset:in, rst_translator_001:in_reset]
signal rst_controller_003_reset_out_reset_req : std_logic; -- rst_controller_003:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator_001:reset_req_in]
signal rst_controller_004_reset_out_reset : std_logic; -- rst_controller_004:reset_out -> [irq_synchronizer_001:receiver_reset, irq_synchronizer_002:receiver_reset, mm_interconnect_0:timer_us_reset_reset_bridge_in_reset_reset, rst_controller_004_reset_out_reset:in]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0, rst_controller_003:reset_in0, rst_controller_004:reset_in0]
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:inv -> jtag_uart_0:av_read_n
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:inv -> jtag_uart_0:av_write_n
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read:inv -> epcs_flash_controller_0:read_n
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write:inv -> epcs_flash_controller_0:write_n
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n
signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n
signal mm_interconnect_0_timer_us_s1_write_ports_inv : std_logic; -- mm_interconnect_0_timer_us_s1_write:inv -> timer_us:write_n
signal mm_interconnect_0_timer_ms_s1_write_ports_inv : std_logic; -- mm_interconnect_0_timer_ms_s1_write:inv -> timer_ms:write_n
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> epcs_flash_controller_0:reset_n
signal rst_controller_002_reset_out_reset_ports_inv : std_logic; -- rst_controller_002_reset_out_reset:inv -> [pio_0:reset_n, uart_0:reset_n]
signal rst_controller_003_reset_out_reset_ports_inv : std_logic; -- rst_controller_003_reset_out_reset:inv -> [jtag_uart_0:rst_n, nios2_gen2_0:reset_n]
signal rst_controller_004_reset_out_reset_ports_inv : std_logic; -- rst_controller_004_reset_out_reset:inv -> [timer_ms:reset_n, timer_us:reset_n]
begin
altpll_0 : component niosii_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset
read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read
write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address
readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => altpll_0_c1_clk, -- c1.clk
c2 => altpll_0_c2_clk, -- c2.clk
c3 => altpll_0_c3_clk, -- c3.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
epcs_flash_controller_0 : component niosii_epcs_flash_controller_0
port map (
clk => altpll_0_c3_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
address => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address, -- epcs_control_port.address
chipselect => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect, -- .chipselect
dataavailable => open, -- .dataavailable
endofpacket => open, -- .endofpacket
read_n => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read_ports_inv, -- .read_n
readdata => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata, -- .readdata
readyfordata => open, -- .readyfordata
write_n => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata, -- .writedata
irq => irq_synchronizer_003_receiver_irq(0), -- irq.irq
dclk => epcs_flash_dclk, -- external.export
sce => epcs_flash_sce, -- .export
sdo => epcs_flash_sdo, -- .export
data0 => epcs_flash_data0 -- .export
);
ip_pwm_0 : component ip_pwm_top
port map (
avs_s0_address => mm_interconnect_0_ip_pwm_0_avs_s0_address, -- avs_s0.address
avs_s0_read => mm_interconnect_0_ip_pwm_0_avs_s0_read, -- .read
avs_s0_readdata => mm_interconnect_0_ip_pwm_0_avs_s0_readdata, -- .readdata
avs_s0_write => mm_interconnect_0_ip_pwm_0_avs_s0_write, -- .write
avs_s0_writedata => mm_interconnect_0_ip_pwm_0_avs_s0_writedata, -- .writedata
avs_s0_waitrequest => mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest, -- .waitrequest
clock_clk => altpll_0_c1_clk, -- clock.clk
reset_reset => rst_controller_002_reset_out_reset, -- reset.reset
pwm_dir => ip_pwm_dir, -- pwm.dir
pwm_out => ip_pwm_out -- .out
);
jtag_uart_0 : component niosii_jtag_uart_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
rst_n => rst_controller_003_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- avalon_jtag_slave.chipselect
av_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address(0), -- .address
av_read_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv, -- .read_n
av_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
av_write_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv, -- .write_n
av_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
av_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
av_irq => irq_mapper_receiver0_irq -- irq.irq
);
nios2_gen2_0 : component niosii_nios2_gen2_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_003_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_003_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosii_onchip_memory2_0
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_003_reset_out_reset, -- reset1.reset
reset_req => rst_controller_003_reset_out_reset_req -- .reset_req
);
pio_0 : component niosii_pio_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
out_port => pio_0_external_connection_export -- external_connection.export
);
timer_ms : component niosii_timer_ms
port map (
clk => altpll_0_c2_clk, -- clk.clk
reset_n => rst_controller_004_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_timer_ms_s1_address, -- s1.address
writedata => mm_interconnect_0_timer_ms_s1_writedata, -- .writedata
readdata => mm_interconnect_0_timer_ms_s1_readdata, -- .readdata
chipselect => mm_interconnect_0_timer_ms_s1_chipselect, -- .chipselect
write_n => mm_interconnect_0_timer_ms_s1_write_ports_inv, -- .write_n
irq => irq_synchronizer_002_receiver_irq(0) -- irq.irq
);
timer_us : component niosii_timer_us
port map (
clk => altpll_0_c2_clk, -- clk.clk
reset_n => rst_controller_004_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_timer_us_s1_address, -- s1.address
writedata => mm_interconnect_0_timer_us_s1_writedata, -- .writedata
readdata => mm_interconnect_0_timer_us_s1_readdata, -- .readdata
chipselect => mm_interconnect_0_timer_us_s1_chipselect, -- .chipselect
write_n => mm_interconnect_0_timer_us_s1_write_ports_inv, -- .write_n
irq => irq_synchronizer_001_receiver_irq(0) -- irq.irq
);
uart_0 : component niosii_uart_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_uart_0_s1_address, -- s1.address
begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect
read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n
write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
dataavailable => open, -- .dataavailable
readyfordata => open, -- .readyfordata
rxd => uart_0_rxd, -- external_connection.export
txd => uart_0_txd, -- .export
irq => irq_synchronizer_receiver_irq(0) -- irq.irq
);
mm_interconnect_0 : component niosii_mm_interconnect_0
port map (
altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk
altpll_0_c1_clk => altpll_0_c1_clk, -- altpll_0_c1.clk
altpll_0_c2_clk => altpll_0_c2_clk, -- altpll_0_c2.clk
altpll_0_c3_clk => altpll_0_c3_clk, -- altpll_0_c3.clk
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
epcs_flash_controller_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- epcs_flash_controller_0_reset_reset_bridge_in_reset.reset
ip_pwm_0_reset_reset_bridge_in_reset_reset => rst_controller_002_reset_out_reset, -- ip_pwm_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_003_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
timer_us_reset_reset_bridge_in_reset_reset => rst_controller_004_reset_out_reset, -- timer_us_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address
altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read
altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
epcs_flash_controller_0_epcs_control_port_address => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address, -- epcs_flash_controller_0_epcs_control_port.address
epcs_flash_controller_0_epcs_control_port_write => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write, -- .write
epcs_flash_controller_0_epcs_control_port_read => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read, -- .read
epcs_flash_controller_0_epcs_control_port_readdata => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata, -- .readdata
epcs_flash_controller_0_epcs_control_port_writedata => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata, -- .writedata
epcs_flash_controller_0_epcs_control_port_chipselect => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect, -- .chipselect
ip_pwm_0_avs_s0_address => mm_interconnect_0_ip_pwm_0_avs_s0_address, -- ip_pwm_0_avs_s0.address
ip_pwm_0_avs_s0_write => mm_interconnect_0_ip_pwm_0_avs_s0_write, -- .write
ip_pwm_0_avs_s0_read => mm_interconnect_0_ip_pwm_0_avs_s0_read, -- .read
ip_pwm_0_avs_s0_readdata => mm_interconnect_0_ip_pwm_0_avs_s0_readdata, -- .readdata
ip_pwm_0_avs_s0_writedata => mm_interconnect_0_ip_pwm_0_avs_s0_writedata, -- .writedata
ip_pwm_0_avs_s0_waitrequest => mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address, -- jtag_uart_0_avalon_jtag_slave.address
jtag_uart_0_avalon_jtag_slave_write => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write, -- .write
jtag_uart_0_avalon_jtag_slave_read => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read, -- .read
jtag_uart_0_avalon_jtag_slave_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
timer_ms_s1_address => mm_interconnect_0_timer_ms_s1_address, -- timer_ms_s1.address
timer_ms_s1_write => mm_interconnect_0_timer_ms_s1_write, -- .write
timer_ms_s1_readdata => mm_interconnect_0_timer_ms_s1_readdata, -- .readdata
timer_ms_s1_writedata => mm_interconnect_0_timer_ms_s1_writedata, -- .writedata
timer_ms_s1_chipselect => mm_interconnect_0_timer_ms_s1_chipselect, -- .chipselect
timer_us_s1_address => mm_interconnect_0_timer_us_s1_address, -- timer_us_s1.address
timer_us_s1_write => mm_interconnect_0_timer_us_s1_write, -- .write
timer_us_s1_readdata => mm_interconnect_0_timer_us_s1_readdata, -- .readdata
timer_us_s1_writedata => mm_interconnect_0_timer_us_s1_writedata, -- .writedata
timer_us_s1_chipselect => mm_interconnect_0_timer_us_s1_chipselect, -- .chipselect
uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address
uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write
uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read
uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect
);
irq_mapper : component niosii_irq_mapper
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_003_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq
receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq
receiver4_irq => irq_mapper_receiver4_irq, -- receiver4.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
irq_synchronizer : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c1_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_002_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_003_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver1_irq -- sender.irq
);
irq_synchronizer_001 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c2_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_004_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_003_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_001_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver2_irq -- sender.irq
);
irq_synchronizer_002 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c2_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_004_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_003_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_002_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver3_irq -- sender.irq
);
irq_synchronizer_003 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c3_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_001_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_003_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_003_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver4_irq -- sender.irq
);
rst_controller : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component niosii_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c3_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_002 : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c1_clk, -- clk.clk
reset_out => rst_controller_002_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_003 : component niosii_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_003_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_003_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_004 : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c2_clk, -- clk.clk
reset_out => rst_controller_004_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;
mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read_ports_inv <= not mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read;
mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write_ports_inv <= not mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read;
mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write;
mm_interconnect_0_timer_us_s1_write_ports_inv <= not mm_interconnect_0_timer_us_s1_write;
mm_interconnect_0_timer_ms_s1_write_ports_inv <= not mm_interconnect_0_timer_ms_s1_write;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
rst_controller_002_reset_out_reset_ports_inv <= not rst_controller_002_reset_out_reset;
rst_controller_003_reset_out_reset_ports_inv <= not rst_controller_003_reset_out_reset;
rst_controller_004_reset_out_reset_ports_inv <= not rst_controller_004_reset_out_reset;
end architecture rtl; -- of niosii
| mit | e6f83079039b9c230d5d874d3de4475e | 0.453438 | 3.848523 | false | false | false | false |
Dragonturtle/SHERPA | HDL/I2C/i2c_master.vhd | 1 | 14,466 | --------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/01/2012 Scott Larson
-- Initial Public Release
-- Version 2.0 06/20/2014 Scott Larson
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
-- Version 2.1 10/21/2014 Scott Larson
-- Replaced gated clock with clock enable
-- Adjusted timing of SCL during start and stop conditions
-- Version 2.2 02/05/2015 Scott Larson
-- Corrected small SDA glitch introduced in version 2.1
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
GENERIC(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = divider*4-1) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '0';
WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
busy <= '0'; --unflag busy
state <= ready; --go to idle state
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
WITH state SELECT
sda_ena_n <= data_clk_prev WHEN start, --generate start condition
NOT data_clk_prev WHEN stop, --generate stop condition
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
END logic;
| gpl-3.0 | 71d61981f10dfde3622b5010ca7ac2d8 | 0.481336 | 4.707452 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_led/led_top.vhd | 1 | 2,903 | ----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
----------------------------------------------------------------------------------
--The MIT License (MIT)
--
--Copyright (c) 2015
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
----------------------------------------------------------------------------------
-- 라이브러리 선언
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity led_top is
Port (
p_clk_50Mhz : in std_logic;
p_button : in std_logic_vector( 1 downto 0 );
p_led_out : out std_logic
);
end led_top;
architecture Behavioral of led_top is
signal s_reset : std_logic;
signal s_clk_50Mhz_cnt : std_logic_vector( 15 downto 0 );
signal s_clk_1Khz : std_logic := '0';
signal s_clk_1Khz_cnt : std_logic_vector( 15 downto 0 );
begin
-- reset 신호 생성
--
s_reset <= not p_button(0);
-- 분주 타이머
--
process( s_reset, p_clk_50Mhz ) is
begin
if rising_edge( p_clk_50Mhz ) then
if s_reset = '1' then
s_clk_50Mhz_cnt <= ( others => '0' );
else
if s_clk_50Mhz_cnt = (50000-1) then
s_clk_1Khz <= not s_clk_1Khz;
s_clk_50Mhz_cnt <= ( others => '0' );
else
s_clk_50Mhz_cnt <= s_clk_50Mhz_cnt + 1;
end if;
end if;
end if;
end process;
process( s_reset, s_clk_1Khz ) is
begin
if rising_edge( s_clk_1Khz ) then
if s_reset = '1' then
s_clk_1Khz_cnt <= ( others => '0' );
else
s_clk_1Khz_cnt <= s_clk_1Khz_cnt + 1;
end if;
end if;
end process;
p_led_out <= s_clk_1Khz_cnt(7);
end Behavioral;
| mit | 1144fe7a7e922d5b66d5efb6cf3c31cb | 0.605016 | 3.168874 | false | false | false | false |
pkerling/ethernet_mac | miim.vhd | 1 | 6,154 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Basic MIIM transaction functionality: read and write registers
library ieee;
use ieee.std_logic_1164.all;
use work.miim_types.all;
use work.utility.all;
-- MII Management Interface compliant to IEEE 802.3 clause 22
entity miim is
generic(
-- Resulting clock frequency fclock / clock_divider has to be below 2.5 MHz for IEEE conformance
-- Use only even numbers for 50% duty cycle of MDC
CLOCK_DIVIDER : integer range 8 to 1000 := 50
);
port(
-- Synchronous active-high reset
reset_i : in std_ulogic;
clock_i : in std_ulogic;
-- Transaction data
register_address_i : in t_register_address;
phy_address_i : in t_phy_address := (others => '0');
-- Output data read from the PHY when wr_en_i was low when the transaction was started
data_read_o : out t_data;
-- Input data to write to the PHY when wr_en_i is high when the transaction starts
data_write_i : in t_data;
-- Request transaction
-- Must stay asserted until the transaction has completed
req_i : in std_ulogic;
-- Transaction has completed
-- Deasserted after the user deasserts req_i
ack_o : out std_ulogic;
-- Transaction direction:
-- Low: read register from PHY
-- High: write register to PHY
wr_en_i : in std_ulogic;
-- MIIM interface: connect to top-level pins
mdc_o : out std_ulogic;
mdio_io : inout std_ulogic
);
end entity;
architecture rtl of miim is
type t_miim_txrx_state is (
IDLE,
TX_COMMAND,
RX_TURNAROUND_Z,
RX_TURNAROUND_Z_READLOW,
RX_DATA,
TX_TURNAROUND_HIGH,
TX_TURNAROUND_LOW,
TX_DATA,
DONE
);
signal state : t_miim_txrx_state := IDLE;
-- Operation type as defined by the standard
subtype t_operation_type is std_ulogic_vector(1 downto 0);
constant PREAMBLE_LENGTH : natural := 32;
-- The frame format as described in IEEE 802.3 clause 22.2.4.5 is LSB first, so the constants appear reversed here
constant START_OF_FRAME : std_ulogic_vector(1 downto 0) := "10";
constant OPERATION_READ : t_operation_type := "01";
constant OPERATION_WRITE : t_operation_type := "10";
-- Total length of a command on the interface
constant COMMAND_LENGTH : natural := PREAMBLE_LENGTH + START_OF_FRAME'length + t_operation_type'length + t_phy_address'length + t_register_address'length;
signal operation_code : t_operation_type;
-- Complete prebuffered command to send out
signal command : std_ulogic_vector(COMMAND_LENGTH - 1 downto 0);
-- Number of the command bit currently being sent
signal command_bit_position : integer range 0 to COMMAND_LENGTH;
-- Number of the data bit currently being sent
signal data_bit_position : integer range 0 to t_data'length;
signal clock_divide_counter : integer range 0 to CLOCK_DIVIDER;
-- Bit order:
-- PHYAD/REGAD/DATA: MSB first
begin
-- Disable clock when idle, apply division otherwise
mdc_o <= '1' when ((state /= IDLE) and (state /= DONE) and clock_divide_counter >= (CLOCK_DIVIDER / 2)) else '0';
with wr_en_i select operation_code <=
OPERATION_WRITE when '1',
OPERATION_READ when others;
-- Build command data array
command(PREAMBLE_LENGTH - 1 downto 0) <= (others => '1');
command(command'high(1) downto PREAMBLE_LENGTH) <= reverse_vector(std_ulogic_vector(register_address_i)) & reverse_vector(std_ulogic_vector(phy_address_i)) & operation_code & START_OF_FRAME;
output : process(state, command_bit_position, data_bit_position, command, data_write_i) is
begin
ack_o <= '0';
mdio_io <= 'Z';
case state is
when IDLE =>
null;
when TX_COMMAND =>
mdio_io <= command(command_bit_position);
when RX_TURNAROUND_Z =>
null;
when RX_TURNAROUND_Z_READLOW =>
null;
when RX_DATA =>
null;
when TX_TURNAROUND_HIGH =>
mdio_io <= '1';
when TX_TURNAROUND_LOW =>
mdio_io <= '0';
when TX_DATA =>
mdio_io <= data_write_i(data_bit_position);
when DONE =>
ack_o <= '1';
end case;
end process;
rx : process(clock_i) is
begin
-- Synchronize to rising as in the FSM process
if rising_edge(clock_i) then
-- and read just before rising (divided) MDC edge
-- / 2 - 1
if state = RX_DATA and (clock_divide_counter = (CLOCK_DIVIDER / 4)) then
data_read_o(data_bit_position) <= mdio_io;
end if;
end if;
end process;
fsm : process(clock_i) is
begin
if rising_edge(clock_i) then
if reset_i = '1' then
state <= IDLE;
clock_divide_counter <= 0;
else
if clock_divide_counter = CLOCK_DIVIDER - 1 then
clock_divide_counter <= 0;
else
clock_divide_counter <= clock_divide_counter + 1;
end if;
-- Run the FSM on the falling divided MDC edge
if (clock_divide_counter = 0) then
case state is
when IDLE =>
command_bit_position <= 0;
-- start at MSB
data_bit_position <= t_data'length - 1;
if req_i = '1' then
state <= TX_COMMAND;
end if;
when TX_COMMAND =>
command_bit_position <= command_bit_position + 1;
if command_bit_position = COMMAND_LENGTH - 1 then
if wr_en_i = '0' then
state <= RX_TURNAROUND_Z;
else
state <= TX_TURNAROUND_HIGH;
end if;
end if;
when RX_TURNAROUND_Z =>
state <= RX_TURNAROUND_Z_READLOW;
when RX_TURNAROUND_Z_READLOW =>
state <= RX_DATA;
when TX_TURNAROUND_HIGH =>
state <= TX_TURNAROUND_LOW;
when TX_TURNAROUND_LOW =>
state <= TX_DATA;
when RX_DATA | TX_DATA =>
if data_bit_position = 0 then
state <= DONE;
else
data_bit_position <= data_bit_position - 1;
end if;
when DONE =>
if req_i = '0' then
state <= IDLE;
end if;
end case;
end if;
end if;
end if;
end process;
end architecture;
| bsd-3-clause | ab5e126054f0fa0a93c4b119bb49814d | 0.630972 | 3.27689 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/src/spi-slave.vhd | 1 | 5,372 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DSP-Crowd project --
-- https://www.dsp-crowd.com --
-- --
-- Author(s): --
-- - Johannes Natter, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2017 Authors and www.dsp-crowd.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_slave is
port
(
clock : in std_ulogic;
n_reset_async : in std_ulogic;
spi_cs : in std_ulogic;
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
spi_miso : out std_ulogic;
data : out std_ulogic_vector(7 downto 0);
data_is_id : out std_ulogic;
data_valid : out std_ulogic;
input_state : in std_ulogic;
input_state_valid : in std_ulogic;
cmd_done : in std_ulogic
);
end spi_slave;
architecture rtl of spi_slave is
type STATEMACHINE_BIT_STEP_TYPE is
(
SMB_IDLE, SMB_GET_DATA_BIT, SMB_WAIT_CLK_LOW
);
type STATEMACHINE_MAIN_STEP_TYPE is
(
SM_WAIT_CS_LOW, SM_GET_ID, SM_GET_DATA
);
type REG_TYPE is record
smb_step : STATEMACHINE_BIT_STEP_TYPE;
sm_step : STATEMACHINE_MAIN_STEP_TYPE;
spi_byte : std_ulogic_vector(7 downto 0);
spi_byte_done : std_ulogic;
bit_idx : natural;
input_state : std_ulogic;
end record;
constant RSET_INIT_VAL : REG_TYPE :=
(
smb_step => SMB_IDLE,
sm_step => SM_WAIT_CS_LOW,
spi_byte => (others => '0'),
spi_byte_done => '0',
bit_idx => 0,
input_state => '0'
);
signal R, NxR : REG_TYPE;
begin
proc_comb: process(R, spi_cs, spi_clk, spi_mosi, input_state, input_state_valid, cmd_done)
begin
NxR <= R;
NxR.spi_byte_done <= '0';
data <= (others => '0');
data_is_id <= '0';
data_valid <= '0';
case R.smb_step is
when SMB_GET_DATA_BIT =>
if(spi_clk = '1')then
NxR.smb_step <= SMB_WAIT_CLK_LOW;
NxR.spi_byte(R.bit_idx) <= spi_mosi;
end if;
when SMB_WAIT_CLK_LOW =>
if(spi_clk = '0')then
NxR.smb_step <= SMB_GET_DATA_BIT;
if(R.bit_idx = 0)then
NxR.smb_step <= SMB_IDLE;
NxR.bit_idx <= 7;
NxR.spi_byte_done <= '1';
else
NxR.bit_idx <= R.bit_idx - 1;
end if;
if(R.bit_idx = 1)then
spi_miso <= R.input_state;
else
spi_miso <= '0';
end if;
end if;
when others =>
NxR.smb_step <= SMB_IDLE;
NxR.bit_idx <= 7;
NxR.spi_byte_done <= '0';
end case;
case R.sm_step is
when SM_WAIT_CS_LOW =>
if(spi_cs = '0')then
NxR.smb_step <= SMB_GET_DATA_BIT;
NxR.sm_step <= SM_GET_ID;
end if;
when SM_GET_ID =>
if(R.spi_byte_done = '1')then
data <= R.spi_byte;
data_is_id <= '1';
NxR.smb_step <= SMB_GET_DATA_BIT;
NxR.sm_step <= SM_GET_DATA;
end if;
when SM_GET_DATA =>
if(R.spi_byte_done = '1')then
data <= R.spi_byte;
data_valid <= '1';
NxR.smb_step <= SMB_GET_DATA_BIT;
end if;
when others =>
NxR.sm_step <= SM_WAIT_CS_LOW;
end case;
if(input_state_valid = '1')then
NxR.input_state <= input_state;
end if;
if(cmd_done = '1')then
NxR.input_state <= '0';
NxR.smb_step <= SMB_GET_DATA_BIT;
NxR.sm_step <= SM_GET_ID;
end if;
if(spi_cs = '1')then
NxR.smb_step <= SMB_IDLE;
NxR.sm_step <= SM_WAIT_CS_LOW;
end if;
end process;
proc_reg: process(n_reset_async, clock)
begin
if(n_reset_async = '0')then
R <= RSET_INIT_VAL;
elsif(clock'event and clock = '1')then
R <= NxR;
end if;
end process;
end architecture rtl;
| gpl-2.0 | daacc47c102d0c5b56c03b7b1e594538 | 0.458302 | 3.199524 | false | false | false | false |
takeshineshiro/utrasound_fpga_modelsim | fpga_sim/src_rec/matchfilter_ast.vhd | 2 | 6,826 | -- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- ================================================================================
--
-- Generated by: FIR Compiler 9.0
-- Generated on: 2014-8-27 12:08:48
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library auk_dspip_lib;
use auk_dspip_lib.auk_dspip_lib_pkg_fir_90.all;
entity matchfilter_ast is
port(
clk : in std_logic;
reset_n : in std_logic;
ast_sink_ready : out std_logic;
ast_source_data : out std_logic_vector (30 -1 downto 0);
ast_sink_data : in std_logic_vector (15 -1 downto 0);
ast_sink_valid : in std_logic;
ast_source_valid : out std_logic;
ast_source_ready : in std_logic;
ast_sink_error : in std_logic_vector (1 downto 0);
ast_source_error : out std_logic_vector (1 downto 0)
);
attribute altera_attribute : string;
attribute altera_attribute of matchfilter_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036";
end matchfilter_ast;
-- Warnings Suppression On
-- altera message_off 10036
architecture struct of matchfilter_ast is
signal sink_packet_error : std_logic_vector(1 downto 0);
signal data_in : std_logic_vector(15 -1 downto 0);
signal data_out : std_logic_vector(30 -1 downto 0);
signal core_out : std_logic_vector(30 -1 downto 0);
signal ready : std_logic;
signal reset_fir : std_logic;
signal sink_ready_ctrl : std_logic;
signal sink_stall : std_logic;
signal source_packet_error : std_logic_vector(1 downto 0);
signal source_stall : std_logic;
signal source_valid_ctrl : std_logic;
signal stall : std_logic;
signal valid : std_logic;
signal core_valid : std_logic;
signal enable_in : std_logic;
signal stall_delayed : std_logic;
constant ENABLE_PIPELINE_DEPTH_c : natural := 0;
component matchfilter_st is
port (
rst : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
rdy_to_ld : out std_logic;
done : out std_logic;
data_in : in std_logic_vector(15 - 1 downto 0);
fir_result : out std_logic_vector(30 - 1 downto 0));
end component matchfilter_st;
begin
sink : auk_dspip_avalon_streaming_sink_fir_90
generic map (
WIDTH_g => 15,
PACKET_SIZE_g => 1,
FIFO_DEPTH_g => 7,
FAMILY_g => "Cyclone III",
MEM_TYPE_g => "Auto")
port map (
clk => clk,
reset_n => reset_n,
data => data_in,
sink_ready_ctrl => sink_ready_ctrl,
sink_stall => sink_stall,
packet_error => sink_packet_error,
at_sink_ready => ast_sink_ready,
at_sink_valid => ast_sink_valid,
at_sink_data => ast_sink_data,
at_sink_error => ast_sink_error);
source : auk_dspip_avalon_streaming_source_fir_90
generic map (
WIDTH_g => 30,
packet_size_g => 1)
port map (
clk => clk,
reset_n => reset_n,
data => data_out,
source_valid_ctrl => source_valid_ctrl,
design_stall => stall_delayed,
source_stall => source_stall,
packet_error => source_packet_error,
at_source_ready => ast_source_ready,
at_source_valid => ast_source_valid,
at_source_data => ast_source_data,
at_source_error => ast_source_error);
intf_ctrl : auk_dspip_avalon_streaming_controller_fir_90
port map (
clk => clk,
ready => ready,
reset_n => reset_n,
sink_packet_error => sink_packet_error,
sink_stall => sink_stall,
source_stall => source_stall,
valid => valid,
reset_design => reset_fir,
sink_ready_ctrl => sink_ready_ctrl,
source_packet_error => source_packet_error,
source_valid_ctrl => source_valid_ctrl,
stall => stall);
fircore: matchfilter_st
port map (
rst => reset_fir,
clk => clk,
clk_en => enable_in,
rdy_to_ld => ready,
done => core_valid,
data_in => data_in,
fir_result => core_out);
data_out <= core_out;
valid <= core_valid;
enable_in <= not stall;
no_enable_pipeline: if ENABLE_PIPELINE_DEPTH_c = 0 generate
stall_delayed <= stall;
end generate no_enable_pipeline;
enable_pipeline: if ENABLE_PIPELINE_DEPTH_c > 0 generate
delay_core_enable : process (clk, reset_n)
variable stall_delay : std_logic_vector(ENABLE_PIPELINE_DEPTH_c downto 0);
begin -- process delay_core_enable
if reset_n = '0' then
stall_delay := (others => '0');
elsif rising_edge(clk) then
stall_delay := stall_delay(stall_delay'high-1 downto 0) & stall;
end if;
stall_delayed <= stall_delay(stall_delay'high);
end process delay_core_enable;
end generate enable_pipeline;
end struct;
| apache-2.0 | 87ee8854930cb2fc29c5bc09072b5fc7 | 0.605772 | 3.815539 | false | false | false | false |
ju994lo/syko_proj | reg_a.vhd | 1 | 922 | library ieee;
use ieee.std_logic_1164.all;
entity reg_a is
generic
(
LW : integer := 8
);
port
(
clk, ie, oe, reset : in std_logic;
data_in : in std_logic_vector(LW-1 downto 0);
data_out : out std_logic_vector(LW-1 downto 0)
);
end reg_a;
architecture behav of reg_a is
--signal reg: std_logic_vector(LW-1 downto 0);
begin
process(reset, clk, ie, oe)
variable reg : std_logic_vector(LW-1 downto 0);
begin
if falling_edge(clk) then
if(reset = '1') then
reg := "00000000";
elsif(ie = '1') then
reg := data_in;
elsif(oe = '1') then
data_out <= reg;
elsif (oe = '0') then
data_out <= (others => 'Z');
-- if(reset = '1') then
-- reg <= (others => '0');
-- elsif(ie = '1') then
-- reg <= data_in;
-- elsif(oe = '1') then
-- data_out <= reg;
-- elsif (oe = '0') then
-- data_out <= (others => 'Z');
end if;
end if;
end process;
end behav;
| gpl-2.0 | 7879040631a887874fcc10d5231627dc | 0.557484 | 2.426316 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/TpGenTx.vhd | 1 | 5,014 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:57:00 09/02/2015
-- Design Name:
-- Module Name: TpGenTx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TpGenTx is
generic (
-- NUM_WORDS_G : integer := 1000;
-- WAIT_CYCLES_G : integer := 125000000;
GATE_DELAY_G : time := 1 ns
);
port (
-- User clock and reset
userClk : in sl;
userRst : in sl;
-- Configuration
waitCycles : in slv(31 downto 0);
numWords : in slv(31 downto 0);
-- Connection to user logic
userTxData : out slv(31 downto 0);
userTxDataValid : out sl;
userTxDataLast : out sl;
userTxDataReady : in sl
);
end TpGenTx;
architecture Behavioral of TpGenTx is
type StateType is (IDLE_S, HEADER_S, DATA_S, LAST_S, WAIT_S);
type RegType is record
state : StateType;
eventNum : slv(31 downto 0);
eventData : slv(31 downto 0);
eventDataValid : sl;
eventDataLast : sl;
dataCount : slv(31 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
eventNum => (others => '0'),
eventData => (others => '0'),
eventDataValid => '0',
eventDataLast => '0',
dataCount => (others => '0')
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,userRst,userTxDataReady) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
v.eventDataValid := '0';
-- State machine
case(r.state) is
when IDLE_S =>
v.eventDataLast := '0';
v.eventData := (others => '0');
if userTxDataReady = '1' then
v.dataCount := numWords;
-- v.dataCount := conv_std_logic_vector(NUM_WORDS_G-1,32);
v.eventData := r.eventNum;
v.eventDataValid := '1';
v.state := HEADER_S;
end if;
when HEADER_S =>
v.eventDataValid := '1';
if userTxDataReady = '1' then
v.eventData := r.eventNum(15 downto 0) & v.dataCount(15 downto 0);
v.state := DATA_S;
end if;
when DATA_S =>
v.eventDataValid := '1';
if userTxDataReady = '1' then
v.dataCount := r.dataCount - 1;
v.eventData := r.eventNum(15 downto 0) & v.dataCount(15 downto 0);
if v.dataCount = 0 then
v.eventDataLast := '1';
v.state := LAST_S;
end if;
end if;
when LAST_S =>
v.eventDataValid := '1';
if userTxDataReady = '1' then
v.eventDataValid := '0';
v.eventDataLast := '0';
v.dataCount := waitCycles;
-- v.dataCount := conv_std_logic_vector(WAIT_CYCLES_G-1,32);
v.state := WAIT_S;
end if;
when WAIT_S =>
v.dataCount := r.dataCount - 1;
if r.dataCount = 0 then
v.eventNum := r.eventNum + 1;
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (userRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
userTxData <= r.eventData;
userTxDataValid <= r.eventDataValid;
userTxDataLast <= r.eventDataLast;
-- Assign variable to signal
rin <= v;
end process;
seq : process (userClk) is
begin
if (rising_edge(userClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end Behavioral;
| lgpl-2.1 | 8fdbaf9b6dc62f9030a7aaa16d163722 | 0.509374 | 4.017628 | false | false | false | false |
32bitmicro/Malinki | fabric/rio/bench/vhdl/TestRioSerial.vhd | 2 | 104,950 | -------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Contains automatic simulation test code to verify a RioSerial implementation.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestRioSerial.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for TestRioSerial.
-------------------------------------------------------------------------------
entity TestRioSerial is
end entity;
-------------------------------------------------------------------------------
-- Architecture for TestUart.
-------------------------------------------------------------------------------
architecture TestRioSerialImpl of TestRioSerial is
component TestSwitchPort is
port(
clk : in std_logic;
areset_n : in std_logic;
frameValid_i : in std_logic_vector(0 to 63);
frameWrite_i : in RioFrameArray(0 to 63);
frameComplete_o : out std_logic;
frameExpected_i : in std_logic;
frameRead_i : in RioFrame;
frameReceived_o : out std_logic;
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readWindowEmpty_o : out std_logic;
readWindowReset_i : in std_logic;
readWindowNext_i : in std_logic;
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(31 downto 0);
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(31 downto 0));
end component;
component RioSerial is
generic(
TIMEOUT_WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
portLinkTimeout_i : in std_logic_vector(TIMEOUT_WIDTH-1 downto 0);
linkInitialized_o : out std_logic;
inputPortEnable_i : in std_logic;
outputPortEnable_i : in std_logic;
localAckIdWrite_i : in std_logic;
clrOutstandingAckId_i : in std_logic;
inboundAckId_i : in std_logic_vector(4 downto 0);
outstandingAckId_i : in std_logic_vector(4 downto 0);
outboundAckId_i : in std_logic_vector(4 downto 0);
inboundAckId_o : out std_logic_vector(4 downto 0);
outstandingAckId_o : out std_logic_vector(4 downto 0);
outboundAckId_o : out std_logic_vector(4 downto 0);
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readFrameRestart_o : out std_logic;
readFrameAborted_i : in std_logic;
readWindowEmpty_i : in std_logic;
readWindowReset_o : out std_logic;
readWindowNext_o : out std_logic;
readContentEmpty_i : in std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0);
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0);
portInitialized_i : in std_logic;
outboundSymbolEmpty_o : out std_logic;
outboundSymbolRead_i : in std_logic;
outboundSymbol_o : out std_logic_vector(33 downto 0);
inboundSymbolFull_o : out std_logic;
inboundSymbolWrite_i : in std_logic;
inboundSymbol_i : in std_logic_vector(33 downto 0));
end component;
signal clk : std_logic;
signal areset_n : std_logic;
signal uartInbound : std_logic;
signal uartOutbound : std_logic;
signal portLinkTimeout : std_logic_vector(10 downto 0);
signal linkInitialized : std_logic;
signal inputPortEnable : std_logic;
signal outputPortEnable : std_logic;
signal localAckIdWrite : std_logic;
signal clrOutstandingAckId : std_logic;
signal inboundAckIdWrite : std_logic_vector(4 downto 0);
signal outstandingAckIdWrite : std_logic_vector(4 downto 0);
signal outboundAckIdWrite : std_logic_vector(4 downto 0);
signal inboundAckIdRead : std_logic_vector(4 downto 0);
signal outstandingAckIdRead : std_logic_vector(4 downto 0);
signal outboundAckIdRead : std_logic_vector(4 downto 0);
signal portInitialized : std_logic;
signal outboundSymbolEmpty : std_logic;
signal outboundSymbolRead : std_logic;
signal outboundSymbol : std_logic_vector(33 downto 0);
signal inboundSymbolFull : std_logic;
signal inboundSymbolWrite : std_logic;
signal inboundSymbol : std_logic_vector(33 downto 0);
signal readFrameEmpty : std_logic;
signal readFrame : std_logic;
signal readFrameRestart : std_logic;
signal readFrameAborted : std_logic;
signal readWindowEmpty : std_logic;
signal readWindowReset : std_logic;
signal readWindowNext : std_logic;
signal readContentEmpty : std_logic;
signal readContent : std_logic;
signal readContentEnd : std_logic;
signal readContentData : std_logic_vector(31 downto 0);
signal writeFrameFull : std_logic;
signal writeFrame : std_logic;
signal writeFrameAbort : std_logic;
signal writeContent : std_logic;
signal writeContentData : std_logic_vector(31 downto 0);
signal frameValid : std_logic_vector(0 to 63);
signal frameWrite : RioFrameArray(0 to 63);
signal frameComplete : std_logic;
signal frameExpected : std_logic;
signal frameRead : RioFrame;
signal frameReceived : std_logic;
begin
-----------------------------------------------------------------------------
-- Clock generation.
-----------------------------------------------------------------------------
ClockGenerator: process
begin
clk <= '0';
wait for 20 ns;
clk <= '1';
wait for 20 ns;
end process;
-----------------------------------------------------------------------------
-- Serial protocol test driver.
-----------------------------------------------------------------------------
TestDriver: process
---------------------------------------------------------------------------
-- Procedure to receive a symbol.
---------------------------------------------------------------------------
procedure ReceiveSymbol(
constant symbolType : in std_logic_vector(1 downto 0);
constant symbolContent : in std_logic_vector(31 downto 0) := x"00000000") is
begin
wait until outboundSymbolEmpty = '0' and clk'event and clk = '1';
assert symbolType = outboundSymbol(33 downto 32)
report "Missmatching symbol type:expected=" &
integer'image(to_integer(unsigned(symbolType))) &
" got=" &
integer'image(to_integer(unsigned(outboundSymbol(33 downto 32))))
severity error;
if ((outboundSymbol(33 downto 32) = SYMBOL_CONTROL) or
(outboundSymbol(33 downto 32) = SYMBOL_CONTROL)) then
assert symbolContent(31 downto 8) = outboundSymbol(31 downto 8)
report "Missmatching symbol content:expected=" &
integer'image(to_integer(unsigned(symbolContent(31 downto 8)))) &
" got=" &
integer'image(to_integer(unsigned(outboundSymbol(31 downto 8))))
severity error;
elsif (outboundSymbol(33 downto 32) = SYMBOL_DATA) then
assert symbolContent(31 downto 0) = outboundSymbol(31 downto 0)
report "Missmatching symbol content:expected=" &
integer'image(to_integer(unsigned(symbolContent(31 downto 0)))) &
" got=" &
integer'image(to_integer(unsigned(outboundSymbol(31 downto 0))))
severity error;
end if;
outboundSymbolRead <= '1';
wait until clk'event and clk = '1';
outboundSymbolRead <= '0';
end procedure;
---------------------------------------------------------------------------
-- Procedure to send a symbol.
---------------------------------------------------------------------------
procedure SendSymbol(
constant symbolType : in std_logic_vector(1 downto 0);
constant symbolContent : in std_logic_vector(31 downto 0) := x"00000000") is
begin
wait until inboundSymbolFull = '0' and clk'event and clk = '1';
inboundSymbolWrite <= '1';
inboundSymbol <= symbolType & symbolContent;
wait until clk'event and clk = '1';
inboundSymbolWrite <= '0';
end procedure;
---------------------------------------------------------------------------
-- Process variables.
---------------------------------------------------------------------------
variable seed1 : positive := 1;
variable seed2 : positive := 1;
variable payload : RioPayload;
variable frame : RioFrame;
begin
---------------------------------------------------------------------------
-- Test case initialization.
---------------------------------------------------------------------------
frameValid <= (others=>'0');
frameExpected <= '0';
portLinkTimeout <= (others=>'1');
inputPortEnable <= '1';
outputPortEnable <= '1';
portInitialized <= '0';
outboundSymbolRead <= '0';
inboundSymbolWrite <= '0';
inboundSymbol <= (others => '0');
localAckIdWrite <= '0';
clrOutstandingAckId <= '0';
inboundAckIdWrite <= (others=>'0');
outstandingAckIdWrite <= (others=>'0');
outboundAckIdWrite <= (others=>'0');
-- Generate a startup reset pulse.
areset_n <= '0';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
areset_n <= '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioSerial");
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioSerial-TC1");
PrintS("Description: Test idle-sequence transmission at startup.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Read transmission port.");
PrintS("Result: Idle sequence symbols should be read.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC1-Step1");
---------------------------------------------------------------------------
-- Make sure only idle-sequences are transmitted at startup.
for i in 0 to 1024 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioSerial-TC2");
PrintS("Description: Test idle-sequence and status symbol transmission");
PrintS(" when the port has been initialized.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Set port initialized and read transmission port.");
PrintS("Result: Idle sequence and status symbols should be read.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC2-Step1");
---------------------------------------------------------------------------
-- Initialize the port to trigger a change of state.
portInitialized <= '1';
-- The transmitter should send idle sequences at startup and a status once
-- in a while.
for i in 0 to 254 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
for i in 0 to 254 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 2:");
PrintS("Action: Toggle port initialized pin and check that no status ");
PrintS(" symbols are transmitted when uninitialized.");
PrintS("Result: Only idle sequences should be read when uninitialized.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC2-Step2");
---------------------------------------------------------------------------
-- Deassert the port initialized flag.
portInitialized <= '0';
-- Make sure only idle-sequences are transmitted at startup.
for i in 0 to 1024 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
-- Initialize the port to trigger a change of state.
portInitialized <= '1';
-- The transmitter should send idle sequences at startup and a status once
-- in a while.
for i in 0 to 254 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
for i in 0 to 254 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 3:");
PrintS("Action: Send one error free status symbol to trigger the ");
PrintS(" transmission of status symbols with a higher frequency.");
PrintS("Result: Idle sequence and status symbols should be read but ");
PrintS(" status symbols should be recived more often.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC2-Step3");
---------------------------------------------------------------------------
-- A received error-free status triggers transmission of status symbols in
-- a more rapid past.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
-- The transmitter should send at least 15 additional statuses after
-- receiving an error free status.
for j in 0 to 15 loop
for i in 0 to 15 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
end loop;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 4:");
PrintS("Action: Send one errornous status symbol to restart the status ");
PrintS(" counting.");
PrintS("Result: Idle sequence and status symbols should be read but ");
PrintS(" status symbols should still be received more often.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC2-Step4");
---------------------------------------------------------------------------
-- REMARK: Add this...
PrintR("Not implemented.");
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 5:");
PrintS("Action: Send one errornous status symbol to restart the status ");
PrintS(" counting.");
PrintS("Result: Idle sequence and status symbols should be read but ");
PrintS(" status symbols should still be received more often.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC2-Step5");
---------------------------------------------------------------------------
-- Make the link fully initialized by sending 7 additional statuses.
for i in 0 to 6 loop
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
end loop;
wait until linkInitialized = '1';
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioSerial-TC3");
PrintS("Description: Test port reception.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Send an inbound frame with pad after the CRC.");
PrintS("Result: The frame should end up in a frame buffer.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step1");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 1;
frame := RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- End the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 2:");
PrintS("Action: Send an inbound frame without a pad after the CRC.");
PrintS("Result: The frame should end up in a frame buffer.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step2");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 2;
frame := RioFrameCreate(ackId=>"00001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- End the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmited frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00001", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 3:");
PrintS("Action: Send an inbound frame with maximum size.");
PrintS("Result: The frame should end up in a frame buffer.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step3");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 133;
frame := RioFrameCreate(ackId=>"00010", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- End the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00010", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 4:");
PrintS("Action: Send two packets without end-of-packet in between.");
PrintS("Result: Both packets should be accepted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step4");
---------------------------------------------------------------------------
-- Create the first frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 10;
frame := RioFrameCreate(ackId=>"00011", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Start the reception of a frame, implicitly ending the previous.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
wait until clk'event and clk = '1';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00011", "11111",
STYPE1_NOP, "000"));
-- Create the second frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 13;
frame := RioFrameCreate(ackId=>"00100", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- End the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00100", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 5:");
PrintS("Action: Start to send a packet. Abort it with stomp. Then send ");
PrintS(" another packet.");
PrintS("Result: The first packet should be discarded and the second should");
PrintS(" be accepted. The retried packet should be acknowledged.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step5");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 7;
frame := RioFrameCreate(ackId=>"00101", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_STOMP, "000"));
-- Dont expect the aborted frame anymore.
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the retry was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "00101", "11111",
STYPE1_NOP, "000"));
-- Acknowledge the canceled packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_RESTART_FROM_RETRY, "000"));
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 8;
frame := RioFrameCreate(ackId=>"00101", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00101", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 6:");
PrintS("Action: Start to send a packet but dont send any payload. Abort it");
PrintS(" with stomp. Then send another packet.");
PrintS("Result: The first packet should be discarded and the second should");
PrintS(" be accepted. The retried packet should be acknowledged.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step6");
---------------------------------------------------------------------------
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_STOMP, "000"));
-- Receive an idle symbol left in the FIFO before the retry was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "00110", "11111",
STYPE1_NOP, "000"));
-- Acknowledge the canceled packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_RESTART_FROM_RETRY, "000"));
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 8;
frame := RioFrameCreate(ackId=>"00110", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00110", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 7:");
PrintS("Action: Start to send a packet with payload, then send a ");
PrintS(" link-request. Then send another packet.");
PrintS("Result: The first packet should be canceled without any ");
PrintS(" confirmation and a link-response should be returned. The");
PrintS(" second packet should be accepted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step7");
---------------------------------------------------------------------------
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 9;
frame := RioFrameCreate(ackId=>"00111", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Send a link-request/input-status to abort the current packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- The frame should be canceled by the link-request, dont expect it anymore.
frameExpected <= '0';
-- Receive link-response indicating normal operation and expected ackId.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "00111", "10000",
STYPE1_NOP, "000"));
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 10;
frame := RioFrameCreate(ackId=>"00111", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00111", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 8:");
PrintS("Action: Start to send a packet, no payload, then send a ");
PrintS(" link-request. Then send another packet.");
PrintS("Result: The first packet should be canceled without any ");
PrintS(" confirmation and a link-response should be returned. The");
PrintS(" second packet should be accepted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step8");
---------------------------------------------------------------------------
-- Expect an empty packet to be aborted.
frameExpected <= '1';
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send a link-request/input-status to abort the current packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Dont expect any frames anymore.
frameExpected <= '0';
-- Receive link-response indicating normal operation and expected ackId.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01000", "10000",
STYPE1_NOP, "000"));
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 11;
frame := RioFrameCreate(ackId=>"01000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 9:");
PrintS("Action: Send a packet when no buffers is available. Reset receiver");
PrintS(" with link-request.");
PrintS("Result: A packet-retry should be transmitted and receiver should");
PrintS(" enter input-retry-stopped.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step9");
---------------------------------------------------------------------------
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 11;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
SendSymbol(SYMBOL_DATA, frame.payload(0));
-- Receive notification about that the packet needs to be retried.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "01001", "11111",
STYPE1_NOP, "000"));
-- Check the status of the input port and verify the input-retry-stopped state.
-- This should also set the receiver into normal operation.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01001", "00100",
STYPE1_NOP, "000"));
-- Check the status of the input port and verify the input-retry-stopped state.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01001", "10000",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 10:");
PrintS("Action: Send a packet when no buffers is available. Reset receiver");
PrintS(" with restart-from-retry.");
PrintS("Result: A packet-retry should be transmitted and receiver should");
PrintS(" enter input-retry-stopped.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step10");
---------------------------------------------------------------------------
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 11;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
SendSymbol(SYMBOL_DATA, frame.payload(0));
-- Receive notification about that the packet needs to be retried.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "01001", "11111",
STYPE1_NOP, "000"));
-- Acknowledge the retried packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_RESTART_FROM_RETRY, "000"));
-- Check the status of the input port and verify the input-retry-stopped state.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01001", "10000",
STYPE1_NOP, "000"));
-- Always receive a status after a link response when leaving input-error-stopped.
-- ReceiveSymbol(SYMBOL_CONTROL,
-- RioControlSymbolCreate(STYPE0_STATUS, "01001", "11111",
-- STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 11:");
PrintS("Action: Start a new packet when in input-retry-stopped state.");
PrintS("Result: The packet should be discarded.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step11");
---------------------------------------------------------------------------
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 11;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
SendSymbol(SYMBOL_DATA, frame.payload(0));
-- Receive notification about that the packet needs to be retried.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "01001", "11111",
STYPE1_NOP, "000"));
-- Create a packet and send it. It should be discarded.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 12;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Acknowledge the retried packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_RESTART_FROM_RETRY, "000"));
-- Create a packet and send it.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 13;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01001", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 12:");
PrintS("Action: Send an erronous control-symbol. Then restore with");
PrintS(" link-request.");
PrintS("Result: Receiver should enter input-error-stopped and return to");
PrintS(" normal operation after the link-request was receiver.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step12");
---------------------------------------------------------------------------
-- Create, corrupt and send a control symbol.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000") xor x"00100000");
-- Receive a packet-not-accepted indicating error in control-symbol crc.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_NOT_ACCEPTED, "00000", "00010",
STYPE1_NOP, "000"));
-- Create a packet and send it. It should be discarded.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 14;
frame := RioFrameCreate(ackId=>"01010", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Make the receiver go back to normal operation by sending a link-request.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01010", "00101",
STYPE1_NOP, "000"));
-- Always receive a status after a link response when leaving input-error-stopped.
-- ReceiveSymbol(SYMBOL_CONTROL,
-- RioControlSymbolCreate(STYPE0_STATUS, "01010", "11111",
-- STYPE1_NOP, "000"));
-- Create a packet and send it.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 15;
frame := RioFrameCreate(ackId=>"01010", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01010", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 13:");
PrintS("Action: Send an erronous packet. Then restore with link-request.");
PrintS("Result: Receiver should enter input-error-stopped and return to");
PrintS(" normal operation after the link-request was receiver.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step13");
---------------------------------------------------------------------------
-- Create a packet and send it with a bit error. It should be discarded.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 15;
frame := RioFrameCreate(ackId=>"01011", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frame.payload(0) := frame.payload(0) xor x"00000010";
frameExpected <= '1';
frameRead <= frame;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Receive a packet-not-accepted indicating error in control-symbol crc.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_NOT_ACCEPTED, "00000", "00100",
STYPE1_NOP, "000"));
-- Dont expect any frame anymore.
frameExpected <= '0';
-- Make the receiver go back to normal operation by sending a link-request.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01011", "00101",
STYPE1_NOP, "000"));
-- Send a new frame without error.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 16;
frame := RioFrameCreate(ackId=>"01011", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01011", "11111",
STYPE1_NOP, "000"));
-- REMARK: Complete with some more error situations: invalid ackId, too
-- short packet, too long packet, etc...
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioSerial-TC4");
PrintS("Description: Test port transmission.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Send an outbound frame.");
PrintS("Result: The frame should be read from the frame buffer and ");
PrintS(" received as symbols.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step1");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 3;
frame := RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(0) <= '1';
frameWrite(0) <= frame;
-- Make sure the transmitter fills in the correct ackId and dont use the
-- one in the input packet.
frameWrite(0).payload(0)(31 downto 27) <= "UUUUU";
-- Receive an idle symbol left in the FIFO before the start of the frame was
-- generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive the start of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Wait for the frame to complete.
wait until frameComplete = '1';
frameValid(0) <= '0';
-- Receive the end of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send acknowledge that the frame was received.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 2:");
PrintS("Action: Send an outbound packet with maximum length.");
PrintS("Result: The packet should be fragmented and received in symbols.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step2");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 133;
frame := RioFrameCreate(ackId=>"00001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(1) <= '1';
frameWrite(1) <= frame;
-- Receive an idle symbol left in the FIFO before the start of the frame was
-- generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive the start of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Wait for the frame to complete.
wait until frameComplete = '1';
frameValid(1) <= '0';
-- Receive the end of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send acknowledge that the frame was received.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00001", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 3:");
PrintS("Action: Send a packet and confirm it with packet-retry.");
PrintS("Result: A restart-from-retry should be transmitted and the packet");
PrintS(" should be retransmitted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step3");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 4;
frame := RioFrameCreate(ackId=>"00010", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(2) <= '1';
frameWrite(2) <= frame;
-- Receive an idle symbol left in the FIFO before the start of the frame was
-- generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive the start of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Receive the end of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send packet-retry that the frame should be retransmitted.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "00010", "11111",
STYPE1_NOP, "000"));
-- Receive the acknowledgement for the retransmission.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_RESTART_FROM_RETRY, "000"));
-- Receive the start of the retransmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the retransmitted frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Wait for the frame to complete.
wait until frameComplete = '1' and clk'event and clk = '1';
frameValid(2) <= '0';
-- Receive the end of the retransmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send acknowledge that the frame was received.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00010", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 4:");
PrintS("Action: Send a packet and confirm it with packet-not-accepted. ");
PrintS("Result: A link-request should be transmitted and the packet should");
PrintS(" be retransmitted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step4");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 5;
frame := RioFrameCreate(ackId=>"00011", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(3) <= '1';
frameWrite(3) <= frame;
-- Receive the start of the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Receive the end of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send packet-retry that the frame should be retransmitted.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_NOT_ACCEPTED, "00000", "11111",
STYPE1_NOP, "000"));
-- Receive the acknowledgement for the retransmission.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "00011", "11111",
STYPE1_NOP, "000"));
-- Receive the start of the retransmitted frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the retransmitted frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Wait for the frame to complete.
wait until frameComplete = '1';
frameValid(3) <= '0';
-- Receive the end of the retransmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send acknowledge that the frame was received.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00011", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 5:");
PrintS("Action: Let a packet timeout expire. Then answer with link-response.");
PrintS("Result: A link-request should be transmitted and the packet should");
PrintS(" be retransmitted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step5");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 5;
frame := RioFrameCreate(ackId=>"00100", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(4) <= '1';
frameWrite(4) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response to make the transmitter to back to normal mode.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "00100", "11111",
STYPE1_NOP, "000"));
-- Receive the retransmitted frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Wait for the frame to complete.
wait until frameComplete = '1';
frameValid(4) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send acknowledge that the frame was received.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00100", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 6:");
PrintS("Action: Let a packet timeout expire. Then answer with link-response");
Prints(" that indicates that the packet was received.");
PrintS("Result: A link-request should be transmitted and the packet should");
PrintS(" not be retransmitted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step6");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 6;
frame := RioFrameCreate(ackId=>"00101", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(5) <= '1';
frameWrite(5) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(5) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response that indicates that the frame was received to make
-- the transmitter to back to normal mode.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "00110", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 7:");
PrintS("Action: Let a packet timeout expire. No more replies.");
PrintS("Result: Three link-requests should be transmitted. When the third");
PrintS(" times out the link will be restarted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step7");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 7;
frame := RioFrameCreate(ackId=>"00110", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(6) <= '1';
frameWrite(6) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
-- Reinitialize the transmitter.
for i in 0 to 255 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_NOP, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00110", "11111",
STYPE1_NOP, "000"));
for j in 0 to 14 loop
for i in 0 to 15 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_NOP, "000"));
end loop;
-- Receive the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(6) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00110", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 8:");
PrintS("Action: Let a packet timeout expire. Then answer with totally ");
PrintS(" unexpected ackId.");
PrintS("Result: A link request should be transmitted and the link should ");
PrintS(" be restarted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step8");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 8;
frame := RioFrameCreate(ackId=>"00111", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(7) <= '1';
frameWrite(7) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "10000", "11111",
STYPE1_NOP, "000"));
-- Reinitialize the transmitter.
for i in 0 to 255 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_NOP, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00111", "11111",
STYPE1_NOP, "000"));
for j in 0 to 14 loop
for i in 0 to 15 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_NOP, "000"));
end loop;
-- Receive the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(7) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00111", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 9:");
PrintS("Action: Send status with unexpected ackId in normal operation.");
PrintS("Result: The transmitter should disregard the error.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step9");
---------------------------------------------------------------------------
-- Send a status with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "10000", "11111",
STYPE1_NOP, "000"));
-- Receive no change.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 10:");
PrintS("Action: Send packet-retry with unexpected ackId in normal operation.");
PrintS("Result: The transmitter should enter output-error-stopped.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step10");
---------------------------------------------------------------------------
-- Send a packet-retry with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "10000", "11111",
STYPE1_NOP, "000"));
-- Receive link-request.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01000", "11111",
STYPE1_NOP, "000"));
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 10;
frame := RioFrameCreate(ackId=>"01000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(8) <= '1';
frameWrite(8) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(8) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 11:");
PrintS("Action: Send packet-accepted with unexpected ackId in normal ");
PrintS(" operation.");
PrintS("Result: The transmitter should enter output-error-stopped.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step11");
---------------------------------------------------------------------------
-- Send a packet-accepted with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "10000", "11111",
STYPE1_NOP, "000"));
-- Receive link-request.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01001", "11111",
STYPE1_NOP, "000"));
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 11;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(9) <= '1';
frameWrite(9) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(9) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01001", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 12:");
PrintS("Action: Send a packet and then accept it with unexpected ackId.");
PrintS("Result: The transmitter should enter output-error-stopped.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step12");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 12;
frame := RioFrameCreate(ackId=>"01010", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(10) <= '1';
frameWrite(10) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(10) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send unexpected ackId in packet-accepted.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "10000", "11111",
STYPE1_NOP, "000"));
-- Receive link-request.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response with expected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01011", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 13:");
PrintS("Action: Set two valid packets.");
PrintS("Result: The two packet should be sent without waiting for ");
PrintS(" packet-accepted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step13");
---------------------------------------------------------------------------
-- Create the first frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 13;
frame := RioFrameCreate(ackId=>"01011", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(11) <= '1';
frameWrite(11) <= frame;
-- Create the second frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 14;
frame := RioFrameCreate(ackId=>"01100", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(12) <= '1';
frameWrite(12) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frameWrite(11).length-1 loop
ReceiveSymbol(SYMBOL_DATA, frameWrite(11).payload(i));
end loop;
wait until frameComplete = '1';
frameValid(11) <= '0';
-- Receive the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frameWrite(12).length-1 loop
ReceiveSymbol(SYMBOL_DATA, frameWrite(12).payload(i));
end loop;
wait until frameComplete = '1';
frameValid(12) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send packet-accepted for both packets.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01011", "11111",
STYPE1_NOP, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01100", "11111",
STYPE1_NOP, "000"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 14:");
PrintS("Action: Set maximum number of valid packets.");
PrintS("Result: Maximum 31 packets should be sent without waiting for ");
PrintS(" packet-accepted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step14");
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Create the frames.
---------------------------------------------------------------------------
for j in 0 to 47 loop
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := j+13;
frame := RioFrameCreate(ackId=>std_logic_vector(to_unsigned((j+13) mod 32, 5)), vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(j+13) <= '1';
frameWrite(j+13) <= frame;
end loop;
---------------------------------------------------------------------------
-- Receive the frames.
---------------------------------------------------------------------------
ReceiveSymbol(SYMBOL_IDLE);
for j in 0 to 30 loop
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frameWrite(j+13).length-1 loop
ReceiveSymbol(SYMBOL_DATA, frameWrite(j+13).payload(i));
end loop;
wait until frameComplete = '1';
frameValid(j+13) <= '0';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_IDLE);
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01101", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step X:");
PrintS("Action: Start sending an outbound packet and while in transmission, ");
PrintS(" start and complete an inbound packet.");
PrintS("Result: The ack for the inbound packet should be inserted into the");
PrintS(" outbound packet.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-StepX");
---------------------------------------------------------------------------
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step X:");
PrintS("Action: Send a packet but not all content is available yet.");
PrintS("Result: Idle symbols should be inserted into the packet.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-StepX");
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- REMARK: Send long frames with a CRC in the middle...
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Test completed.
---------------------------------------------------------------------------
TestEnd;
end process;
-----------------------------------------------------------------------------
-- Instantiate the uart.
-----------------------------------------------------------------------------
TestPort: TestSwitchPort
port map(
clk=>clk, areset_n=>areset_n,
frameValid_i=>frameValid, frameWrite_i=>frameWrite, frameComplete_o=>frameComplete,
frameExpected_i=>frameExpected, frameRead_i=>frameRead, frameReceived_o=>frameReceived,
readFrameEmpty_o=>readFrameEmpty, readFrame_i=>readFrame,
readFrameRestart_i=>readFrameRestart, readFrameAborted_o=>readFrameAborted,
readWindowEmpty_o=>readWindowEmpty,
readWindowReset_i=>readWindowReset, readWindowNext_i=>readWindowNext,
readContentEmpty_o=>readContentEmpty, readContent_i=>readContent,
readContentEnd_o=>readContentEnd, readContentData_o=>readContentData,
writeFrameFull_o=>writeFrameFull, writeFrame_i=>writeFrame, writeFrameAbort_i=>writeFrameAbort,
writeContent_i=>writeContent, writeContentData_i=>writeContentData);
TestPhy: RioSerial
generic map(
TIMEOUT_WIDTH=>11)
port map(
clk=>clk, areset_n=>areset_n,
portLinkTimeout_i=>portLinkTimeout,
linkInitialized_o=>linkInitialized,
inputPortEnable_i=>inputPortEnable,
outputPortEnable_i=>outputPortEnable,
localAckIdWrite_i=>localAckIdWrite,
clrOutstandingAckId_i=>clrOutstandingAckId,
inboundAckId_i=>inboundAckIdWrite,
outstandingAckId_i=>outstandingAckIdWrite,
outboundAckId_i=>outboundAckIdWrite,
inboundAckId_o=>inboundAckIdRead,
outstandingAckId_o=>outstandingAckIdRead,
outboundAckId_o=>outboundAckIdRead,
readFrameEmpty_i=>readFrameEmpty, readFrame_o=>readFrame, readFrameRestart_o=>readFrameRestart,
readFrameAborted_i=>readFrameAborted,
readWindowEmpty_i=>readWindowEmpty,
readWindowReset_o=>readWindowReset, readWindowNext_o=>readWindowNext,
readContentEmpty_i=>readContentEmpty,
readContent_o=>readContent, readContentEnd_i=>readContentEnd, readContentData_i=>readContentData,
writeFrameFull_i=>writeFrameFull, writeFrame_o=>writeFrame, writeFrameAbort_o=>writeFrameAbort,
writeContent_o=>writeContent, writeContentData_o=>writeContentData,
portInitialized_i=>portInitialized,
outboundSymbolEmpty_o=>outboundSymbolEmpty, outboundSymbolRead_i=>outboundSymbolRead,
outboundSymbol_o=>outboundSymbol,
inboundSymbolFull_o=>inboundSymbolFull, inboundSymbolWrite_i=>inboundSymbolWrite,
inboundSymbol_i=>inboundSymbol);
end architecture;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
entity TestSwitchPort is
port(
clk : in std_logic;
areset_n : in std_logic;
frameValid_i : in std_logic_vector(0 to 63);
frameWrite_i : in RioFrameArray(0 to 63);
frameComplete_o : out std_logic;
frameExpected_i : in std_logic;
frameRead_i : in RioFrame;
frameReceived_o : out std_logic;
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readWindowEmpty_o : out std_logic;
readWindowReset_i : in std_logic;
readWindowNext_i : in std_logic;
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(31 downto 0);
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(31 downto 0));
end entity;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
architecture TestSwitchPortImpl of TestSwitchPort is
begin
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
FrameSender: process
variable frameIndex : natural range 0 to 70;
variable backIndex, frontIndex : natural range 0 to 63;
begin
readFrameEmpty_o <= '1';
readFrameAborted_o <= '0';
readWindowEmpty_o <= '1';
readContentEmpty_o <= '1';
readContentEnd_o <= '0';
readContentData_o <= (others=>'U');
frameComplete_o <= '0';
backIndex := 0;
frontIndex := 0;
wait until areset_n = '1';
loop
wait until clk'event and clk = '1';
if (readFrame_i = '1') then
assert (frontIndex - backIndex) >= 0 report "Unexpected readFrame." severity error;
if(backIndex < 63) then
backIndex := backIndex + 1;
else
backIndex := 0;
end if;
end if;
if (readWindowReset_i = '1') then
frameIndex := 0;
frontIndex := backIndex;
readContentEnd_o <= '0';
readContentData_o <= (others=>'U');
end if;
if (readWindowNext_i = '1') then
assert frameIndex = frameWrite_i(frontIndex).length report "Did not read all frame content." severity error;
frameComplete_o <= '1';
readContentEnd_o <= '0';
readContentData_o <= (others=>'U');
frameIndex := 0;
if(frontIndex < 63) then
frontIndex := frontIndex + 1;
else
frontIndex := 0;
end if;
else
frameComplete_o <= '0';
end if;
if (readFrameRestart_i = '1') then
frameIndex := 0;
readContentEnd_o <= '0';
readContentData_o <= (others=>'U');
end if;
if (readContent_i = '1') then
assert frameValid_i(frontIndex) = '1' report "Unexpected content read." severity error;
if (frameIndex /= frameWrite_i(frontIndex).length) then
readContentEnd_o <= '0';
readContentData_o <= frameWrite_i(frontIndex).payload(frameIndex);
frameIndex := frameIndex + 1;
else
readContentEnd_o <= '1';
readContentData_o <= (others=>'U');
end if;
end if;
if(frameValid_i(frontIndex) = '1') then
readFrameEmpty_o <= '0';
readWindowEmpty_o <= '0';
readContentEmpty_o <= '0';
else
readFrameEmpty_o <= '1';
readWindowEmpty_o <= '1';
readContentEmpty_o <= '1';
end if;
end loop;
end process;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
FrameReader: process
type StateType is (STATE_IDLE, STATE_READ, STATE_UPDATE);
variable state : StateType;
variable frameIndex : natural range 0 to 69;
begin
writeFrameFull_o <= '1';
frameReceived_o <= '0';
wait until areset_n = '1';
state := STATE_IDLE;
loop
wait until clk'event and clk = '1';
case state is
when STATE_IDLE =>
frameReceived_o <= '0';
if (frameExpected_i = '1') then
state := STATE_READ;
frameIndex := 0;
writeFrameFull_o <= '0';
end if;
assert writeFrame_i = '0' report "Unexpected frame received." severity error;
--assert writeFrameAbort_i = '0' report "Unexpected frame aborted received." severity error;
assert writeContent_i = '0' report "Unexpected content received." severity error;
when STATE_READ =>
if (writeFrame_i = '1') then
state := STATE_UPDATE;
frameReceived_o <= '1';
writeFrameFull_o <= '1';
assert frameIndex = frameRead_i.length report "Did not finish the expected frame." severity error;
end if;
if (writeFrameAbort_i = '1') then
frameIndex := 0;
end if;
if (writeContent_i = '1') then
assert writeContentData_i = frameRead_i.payload(frameIndex)
report "Unexpected frame content received." severity error;
frameIndex := frameIndex + 1;
end if;
if (frameExpected_i = '0') then
state := STATE_IDLE;
end if;
when STATE_UPDATE =>
if (frameExpected_i = '0') then
state := STATE_IDLE;
end if;
end case;
end loop;
end process;
end architecture;
| bsd-3-clause | f96e557bb809de7c47bc5a44436708f4 | 0.499943 | 5.306669 | false | false | false | false |
32bitmicro/Malinki | fabric/rio/rtl/vhdl/RioSerial.vhd | 2 | 106,078 | -------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Containing the transmission channel independent parts of the LP-Serial
-- Physical Layer Specification (RapidIO 2.2, part 6).
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RioSerial
--
-- clk - System clock.
-- areset_n - System reset. Asynchronous, active low.
--
-- portLinkTimeout_i - The number of ticks to wait for a packet-accepted before
-- a timeout occurrs.
-- linkInitialized_o - Indicates if a link partner is answering with valid
-- status-control-symbols.
-- inputPortEnable_i - Activate the input port for non-maintenance packets. If
-- deasserted, only non-maintenance packets are allowed.
-- outputPortEnable_i - Activate the output port for non-maintenance packets.
-- If deasserted, only non-maintenance packets are allowed.
--
-- This interface makes it possible to read and write ackId in both outbound
-- and inbound directions. All input signals are validated by localAckIdWrite.
-- localAckIdWrite_i - Indicate if a localAckId write operation is ongoing.
-- Usually this signal is high one tick.
-- clrOutstandingAckId_i - Clear outstanding ackId, i.e. reset the transmission
-- window. The signal is only read if localAckIdWrite_i is high.
-- inboundAckId_i - The value to set the inbound ackId (the ackId that the
-- next inbound packet should have) to. This signal is only read if localAckIdWrite
-- is high.
-- outstandingAckId_i - The value to set the outstanding ackId (the ackId
-- transmitted but not acknowledged) to. This signal is only read if localAckIdWrite
-- is high.
-- outboundAckId_i - The value to set the outbound ackId (the ackId that the
-- next outbound packet will have) to. This signal is only read if localAckIdWrite
-- is high.
-- inboundAckId_o - The current inbound ackId.
-- outstandingAckId_o - The current outstanding ackId.
-- outboundAckId_o - The current outbound ackId.
--
-- This is the interface to the packet buffering sublayer.
-- The window signals are used to send packets without removing them from the
-- memory storage. This way, many packet can be sent without awaiting
-- packet-accepted symbols and if a packet-accepted gets lost, it is possible
-- to revert and resend a packet. This is achived by reading readWindowEmpty
-- for new packet and asserting readWindowNext when a packet has been sent.
-- When the packet-accepted is received, readFrame should be asserted to remove the
-- packet from the storage. If a packet-accepted is missing, readWindowReset is
-- asserted to set the current packet to read to the one that has not received
-- a packet-accepted.
-- readFrameEmpty_i - Indicate if a packet is ready in the outbound direction.
-- Once deasserted, it is possible to read the packet content using
-- readContent_o to update readContentData and readContentEnd.
-- readFrame_o - Assert this signal for one tick to discard the oldest packet.
-- It should be used when a packet has been fully read, a linkpartner has
-- accepted it and the resources occupied by it should be returned to be
-- used for new packets.
-- readFrameRestart_o - Assert this signal to restart the reading of the
-- current packet. readContentData and readContentEnd will be reset to the
-- first content of the packet.
-- readFrameAborted_i - This signal is asserted if the current packet was
-- aborted while it was written. It is used when a transmitter starts to send a
-- packet before it has been fully received and it is cancelled before it is
-- completed. A one tick asserted readFrameRestart signal resets this signal.
-- readWindowEmpty_i - Indicate if there are more packets to send.
-- readWindowReset_o - Reset the current packet to the oldest stored in the memory.
-- readWindowNext_o - Indicate that a new packet should be read. Must only be
-- asserted if readWindowEmpty is deasserted. It should be high for one tick.
-- readContentEmpty_i - Indicate if there are any packet content to be read.
-- This signal is updated directly when packet content is written making it
-- possible to read packet content before the full packet has been written to
-- the memory storage.
-- readContent_o - Update readContentData and readContentEnd.
-- readContentEnd_i - Indicate if the end of the current packet has been
-- reached. When asserted, readContentData is not valid.
-- readContentData_i - The content of the current packet.
-- writeFrameFull_i - Indicate if the inbound packet storage is ready to accept
-- a new packet.
-- writeFrame_o - Indicate that a new complete inbound packet has been written.
-- writeFrameAbort_o - Indicate that the current packet is aborted and that all
-- data written for this packet should be discarded.
-- writeContent_o - Indicate that writeContentData is valid and should be
-- written into the packet content storage.
-- writeContentData_o - The content to write to the packet content storage.
--
-- This is the interface to the PCS (Physical Control Sublayer). Four types of
-- symbols exist, idle, control, data and error.
-- Idle symbols are transmitted when nothing else can be transmitted. They are
-- mainly intended to enforce a timing on the transmitted symbols. This is
-- needed to be able to guarantee that a status-control-symbol is transmitted
-- at least once every 256 symbol.
-- Control symbols contain control-symbols as described by the standard.
-- Data symbols contains a 32-bit fragment of a RapidIO packet.
-- Error symbols indicate that a corrupted symbol was received. This could be
-- used by a PCS layer to indicate that a transmission error was detected and
-- that the above layers should send link-requests to ensure the synchronism
-- between the link-partners.
-- The signals in this interface are:
-- portInitialized_i - An asserted signal on this pin indicates that the PCS
-- layer has established synchronization with the link and is ready to accept
-- symbols.
-- outboundSymbolEmpty_o - An asserted signal indicates that there are no
-- outbound symbols to read. Once deasserted, outboundSymbol_o will be
-- already be valid. This signal will be updated one tick after
-- outboundSymbolRead_i has been asserted.
-- outboundSymbolRead_i - Indicate that outboundSymbol_o has been read and a
-- new value could be accepted. It should be active for one tick.
-- outboundSymbol_o - The outbound symbol. The two MSB bits are the type of the
-- symbol.
-- bit 34-33
-- 00=IDLE, the rest of the bits are not used.
-- 01=CONTROL, the control symbols payload (24 bits) are placed in the MSB
-- part of the symbol data.
-- 10=ERROR, the rest of the bits are not used.
-- 11=DATA, all the remaining bits contain the data-symbol payload.
-- inboundSymbolFull_o - An asserted signal indicates that no more inbound
-- symbols can be accepted.
-- inboundSymbolWrite_i - Indicate that inboundSymbol_i contains valid
-- information that should be forwarded. Should be active for one tick.
-- inboundSymbol_i - The inbound symbol. See outboundSymbol_o for formating.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for RioSerial.
-------------------------------------------------------------------------------
entity RioSerial is
generic(
TIMEOUT_WIDTH : natural);
port(
-- System signals.
clk : in std_logic;
areset_n : in std_logic;
-- Status signals for maintenance operations.
portLinkTimeout_i : in std_logic_vector(TIMEOUT_WIDTH-1 downto 0);
linkInitialized_o : out std_logic;
inputPortEnable_i : in std_logic;
outputPortEnable_i : in std_logic;
-- Support for portLocalAckIdCSR.
localAckIdWrite_i : in std_logic;
clrOutstandingAckId_i : in std_logic;
inboundAckId_i : in std_logic_vector(4 downto 0);
outstandingAckId_i : in std_logic_vector(4 downto 0);
outboundAckId_i : in std_logic_vector(4 downto 0);
inboundAckId_o : out std_logic_vector(4 downto 0);
outstandingAckId_o : out std_logic_vector(4 downto 0);
outboundAckId_o : out std_logic_vector(4 downto 0);
-- Outbound frame interface.
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readFrameRestart_o : out std_logic;
readFrameAborted_i : in std_logic;
readWindowEmpty_i : in std_logic;
readWindowReset_o : out std_logic;
readWindowNext_o : out std_logic;
readContentEmpty_i : in std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0);
-- Inbound frame interface.
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0);
-- PCS layer signals.
portInitialized_i : in std_logic;
outboundSymbolEmpty_o : out std_logic;
outboundSymbolRead_i : in std_logic;
outboundSymbol_o : out std_logic_vector(33 downto 0);
inboundSymbolFull_o : out std_logic;
inboundSymbolWrite_i : in std_logic;
inboundSymbol_i : in std_logic_vector(33 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for RioSerial.
-------------------------------------------------------------------------------
architecture RioSerialImpl of RioSerial is
component RioFifo1 is
generic(
WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
empty_o : out std_logic;
read_i : in std_logic;
data_o : out std_logic_vector(WIDTH-1 downto 0);
full_o : out std_logic;
write_i : in std_logic;
data_i : in std_logic_vector(WIDTH-1 downto 0));
end component;
component RioTransmitter is
generic(
TIMEOUT_WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
portLinkTimeout_i : in std_logic_vector(TIMEOUT_WIDTH-1 downto 0);
portEnable_i : in std_logic;
localAckIdWrite_i : in std_logic;
clrOutstandingAckId_i : in std_logic;
outstandingAckId_i : in std_logic_vector(4 downto 0);
outboundAckId_i : in std_logic_vector(4 downto 0);
outstandingAckId_o : out std_logic_vector(4 downto 0);
outboundAckId_o : out std_logic_vector(4 downto 0);
portInitialized_i : in std_logic;
txFull_i : in std_logic;
txWrite_o : out std_logic;
txControl_o : out std_logic_vector(1 downto 0);
txData_o : out std_logic_vector(31 downto 0);
txControlEmpty_i : in std_logic;
txControlSymbol_i : in std_logic_vector(12 downto 0);
txControlUpdate_o : out std_logic;
rxControlEmpty_i : in std_logic;
rxControlSymbol_i : in std_logic_vector(12 downto 0);
rxControlUpdate_o : out std_logic;
linkInitialized_i : in std_logic;
linkInitialized_o : out std_logic;
ackIdStatus_i : in std_logic_vector(4 downto 0);
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readFrameRestart_o : out std_logic;
readFrameAborted_i : in std_logic;
readWindowEmpty_i : in std_logic;
readWindowReset_o : out std_logic;
readWindowNext_o : out std_logic;
readContentEmpty_i : in std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0));
end component;
component RioReceiver is
port(
clk : in std_logic;
areset_n : in std_logic;
portEnable_i : in std_logic;
localAckIdWrite_i : in std_logic;
inboundAckId_i : in std_logic_vector(4 downto 0);
inboundAckId_o : out std_logic_vector(4 downto 0);
portInitialized_i : in std_logic;
rxEmpty_i : in std_logic;
rxRead_o : out std_logic;
rxControl_i : in std_logic_vector(1 downto 0);
rxData_i : in std_logic_vector(31 downto 0);
txControlWrite_o : out std_logic;
txControlSymbol_o : out std_logic_vector(12 downto 0);
rxControlWrite_o : out std_logic;
rxControlSymbol_o : out std_logic_vector(12 downto 0);
ackIdStatus_o : out std_logic_vector(4 downto 0);
linkInitialized_o : out std_logic;
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0));
end component;
signal linkInitializedRx : std_logic;
signal linkInitializedTx : std_logic;
signal ackIdStatus : std_logic_vector(4 downto 0);
signal txControlWrite : std_logic;
signal txControlWriteSymbol : std_logic_vector(12 downto 0);
signal txControlReadEmpty : std_logic;
signal txControlRead : std_logic;
signal txControlReadSymbol : std_logic_vector(12 downto 0);
signal rxControlWrite : std_logic;
signal rxControlWriteSymbol : std_logic_vector(12 downto 0);
signal rxControlReadEmpty : std_logic;
signal rxControlRead : std_logic;
signal rxControlReadSymbol : std_logic_vector(12 downto 0);
signal outboundFull : std_logic;
signal outboundWrite : std_logic;
signal outboundControl : std_logic_vector(1 downto 0);
signal outboundData : std_logic_vector(31 downto 0);
signal outboundSymbol : std_logic_vector(33 downto 0);
signal inboundEmpty : std_logic;
signal inboundRead : std_logic;
signal inboundControl : std_logic_vector(1 downto 0);
signal inboundData : std_logic_vector(31 downto 0);
signal inboundSymbol : std_logic_vector(33 downto 0);
begin
linkInitialized_o <=
'1' when ((linkInitializedRx = '1') and (linkInitializedTx = '1')) else '0';
-----------------------------------------------------------------------------
-- Serial layer modules.
-----------------------------------------------------------------------------
Transmitter: RioTransmitter
generic map(
TIMEOUT_WIDTH=>TIMEOUT_WIDTH)
port map(
clk=>clk, areset_n=>areset_n,
portLinkTimeout_i=>portLinkTimeout_i,
portEnable_i=>outputPortEnable_i,
localAckIdWrite_i=>localAckIdWrite_i,
clrOutstandingAckId_i=>clrOutstandingAckId_i,
outstandingAckId_i=>outstandingAckId_i,
outboundAckId_i=>outboundAckId_i,
outstandingAckId_o=>outstandingAckId_o,
outboundAckId_o=>outboundAckId_o,
portInitialized_i=>portInitialized_i,
txFull_i=>outboundFull, txWrite_o=>outboundWrite,
txControl_o=>outboundControl, txData_o=>outboundData,
txControlEmpty_i=>txControlReadEmpty, txControlSymbol_i=>txControlReadSymbol,
txControlUpdate_o=>txControlRead,
rxControlEmpty_i=>rxControlReadEmpty, rxControlSymbol_i=>rxControlReadSymbol,
rxControlUpdate_o=>rxControlRead,
linkInitialized_o=>linkInitializedTx,
linkInitialized_i=>linkInitializedRx, ackIdStatus_i=>ackIdStatus,
readFrameEmpty_i=>readFrameEmpty_i, readFrame_o=>readFrame_o,
readFrameRestart_o=>readFrameRestart_o, readFrameAborted_i=>readFrameAborted_i,
readWindowEmpty_i=>readWindowEmpty_i,
readWindowReset_o=>readWindowReset_o, readWindowNext_o=>readWindowNext_o,
readContentEmpty_i=>readContentEmpty_i, readContent_o=>readContent_o,
readContentEnd_i=>readContentEnd_i, readContentData_i=>readContentData_i);
TxSymbolFifo: RioFifo1
generic map(WIDTH=>13)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>txControlReadEmpty, read_i=>txControlRead, data_o=>txControlReadSymbol,
full_o=>open, write_i=>txControlWrite, data_i=>txControlWriteSymbol);
RxSymbolFifo: RioFifo1
generic map(WIDTH=>13)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>rxControlReadEmpty, read_i=>rxControlRead, data_o=>rxControlReadSymbol,
full_o=>open, write_i=>rxControlWrite, data_i=>rxControlWriteSymbol);
Receiver: RioReceiver
port map(
clk=>clk, areset_n=>areset_n,
portEnable_i=>inputPortEnable_i,
localAckIdWrite_i=>localAckIdWrite_i,
inboundAckId_i=>inboundAckId_i,
inboundAckId_o=>inboundAckId_o,
portInitialized_i=>portInitialized_i,
rxEmpty_i=>inboundEmpty, rxRead_o=>inboundRead,
rxControl_i=>inboundControl, rxData_i=>inboundData,
txControlWrite_o=>txControlWrite, txControlSymbol_o=>txControlWriteSymbol,
rxControlWrite_o=>rxControlWrite, rxControlSymbol_o=>rxControlWriteSymbol,
ackIdStatus_o=>ackIdStatus,
linkInitialized_o=>linkInitializedRx,
writeFrameFull_i=>writeFrameFull_i,
writeFrame_o=>writeFrame_o, writeFrameAbort_o=>writeFrameAbort_o,
writeContent_o=>writeContent_o, writeContentData_o=>writeContentData_o);
-----------------------------------------------------------------------------
-- PCS layer FIFO interface.
-----------------------------------------------------------------------------
outboundSymbol <= outboundControl & outboundData;
OutboundSymbolFifo: RioFifo1
generic map(WIDTH=>34)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>outboundSymbolEmpty_o, read_i=>outboundSymbolRead_i, data_o=>outboundSymbol_o,
full_o=>outboundFull, write_i=>outboundWrite, data_i=>outboundSymbol);
inboundControl <= inboundSymbol(33 downto 32);
inboundData <= inboundSymbol(31 downto 0);
InboundSymbolFifo: RioFifo1
generic map(WIDTH=>34)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>inboundEmpty, read_i=>inboundRead, data_o=>inboundSymbol,
full_o=>inboundSymbolFull_o, write_i=>inboundSymbolWrite_i, data_i=>inboundSymbol_i);
end architecture;
-------------------------------------------------------------------------------
-- RioTransmitter
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for RioTransmitter.
-------------------------------------------------------------------------------
entity RioTransmitter is
generic(
TIMEOUT_WIDTH : natural);
port(
-- System signals.
clk : in std_logic;
areset_n : in std_logic;
-- Status signals used for maintenance.
portLinkTimeout_i : in std_logic_vector(TIMEOUT_WIDTH-1 downto 0);
portEnable_i : in std_logic;
-- Support for localAckIdCSR.
localAckIdWrite_i : in std_logic;
clrOutstandingAckId_i : in std_logic;
outstandingAckId_i : in std_logic_vector(4 downto 0);
outboundAckId_i : in std_logic_vector(4 downto 0);
outstandingAckId_o : out std_logic_vector(4 downto 0);
outboundAckId_o : out std_logic_vector(4 downto 0);
-- Port output interface.
portInitialized_i : in std_logic;
txFull_i : in std_logic;
txWrite_o : out std_logic;
txControl_o : out std_logic_vector(1 downto 0);
txData_o : out std_logic_vector(31 downto 0);
-- Control symbols aimed to the transmitter.
txControlEmpty_i : in std_logic;
txControlSymbol_i : in std_logic_vector(12 downto 0);
txControlUpdate_o : out std_logic;
-- Control symbols from the receiver to send.
rxControlEmpty_i : in std_logic;
rxControlSymbol_i : in std_logic_vector(12 downto 0);
rxControlUpdate_o : out std_logic;
-- Internal signalling from the receiver part.
linkInitialized_o : out std_logic;
linkInitialized_i : in std_logic;
ackIdStatus_i : in std_logic_vector(4 downto 0);
-- Frame buffer interface.
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readFrameRestart_o : out std_logic;
readFrameAborted_i : in std_logic;
readWindowEmpty_i : in std_logic;
readWindowReset_o : out std_logic;
readWindowNext_o : out std_logic;
readContentEmpty_i : in std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for RioTransmitter.
-------------------------------------------------------------------------------
architecture RioTransmitterImpl of RioTransmitter is
constant NUMBER_STATUS_TRANSMIT : natural := 15;
constant NUMBER_LINK_RESPONSE_RETRIES : natural := 2;
component MemorySimpleDualPortAsync is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1;
INIT_VALUE : std_logic := 'U');
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
component Crc5ITU is
port(
d_i : in std_logic_vector(18 downto 0);
crc_o : out std_logic_vector(4 downto 0));
end component;
type StateType is (STATE_UNINITIALIZED, STATE_PORT_INITIALIZED,
STATE_NORMAL,
STATE_OUTPUT_RETRY_STOPPED,
STATE_SEND_LINK_REQUEST, STATE_OUTPUT_ERROR_STOPPED,
STATE_RECOVER, STATE_FATAL_ERROR);
signal stateCurrent, stateNext : StateType;
signal statusReceivedCurrent, statusReceivedNext : std_logic;
signal counterCurrent, counterNext : natural range 0 to 15;
signal symbolsTransmittedCurrent, symbolsTransmittedNext : natural range 0 to 255;
type FrameStateType is (FRAME_START, FRAME_CHECK, FRAME_ACKID, FRAME_BODY, FRAME_END);
signal frameStateCurrent, frameStateNext : FrameStateType;
signal ackIdCurrent, ackIdNext : unsigned(4 downto 0) := (others=>'0');
signal ackIdWindowCurrent, ackIdWindowNext : unsigned(4 downto 0) := (others=>'0');
signal bufferStatusCurrent, bufferStatusNext : std_logic_vector(4 downto 0);
signal stype0 : std_logic_vector(2 downto 0);
signal parameter0 : std_logic_vector(4 downto 0);
signal parameter1 : std_logic_vector(4 downto 0);
signal stype1 : std_logic_vector(2 downto 0);
signal cmd : std_logic_vector(2 downto 0);
signal txControlStype0 : std_logic_vector(2 downto 0);
signal txControlParameter0 : std_logic_vector(4 downto 0);
signal txControlParameter1 : std_logic_vector(4 downto 0);
signal rxControlStype0 : std_logic_vector(2 downto 0);
signal rxControlParameter0 : std_logic_vector(4 downto 0);
signal rxControlParameter1 : std_logic_vector(4 downto 0);
signal symbolWrite : std_logic;
signal symbolType : std_logic_vector(1 downto 0);
signal symbolControl : std_logic_vector(31 downto 0);
signal symbolData : std_logic_vector(31 downto 0);
signal crcCalculated : std_logic_vector(4 downto 0);
signal timeoutWrite : std_logic;
signal timeoutCounter : unsigned(TIMEOUT_WIDTH downto 0);
signal timeoutFrame : unsigned(TIMEOUT_WIDTH downto 0);
signal timeoutElapsed : unsigned(TIMEOUT_WIDTH downto 0);
signal timeoutDelta : unsigned(TIMEOUT_WIDTH downto 0);
signal timeoutExpired : std_logic;
signal timeoutAddress : std_logic_vector(4 downto 0);
signal timeoutMemoryOut : std_logic_vector(TIMEOUT_WIDTH downto 0);
begin
linkInitialized_o <= '0' when ((stateCurrent = STATE_UNINITIALIZED) or
(stateCurrent = STATE_PORT_INITIALIZED)) else '1';
-----------------------------------------------------------------------------
-- Assign control symbol from fifo signals.
-----------------------------------------------------------------------------
txControlStype0 <= txControlSymbol_i(12 downto 10);
txControlParameter0 <= txControlSymbol_i(9 downto 5);
txControlParameter1 <= txControlSymbol_i(4 downto 0);
rxControlStype0 <= rxControlSymbol_i(12 downto 10);
rxControlParameter0 <= rxControlSymbol_i(9 downto 5);
rxControlParameter1 <= rxControlSymbol_i(4 downto 0);
-----------------------------------------------------------------------------
-- Outbound symbol creation logic.
-----------------------------------------------------------------------------
symbolControl(31 downto 29) <= stype0;
symbolControl(28 downto 24) <= parameter0;
symbolControl(23 downto 19) <= parameter1;
symbolControl(18 downto 16) <= stype1;
symbolControl(15 downto 13) <= cmd;
symbolControl(12 downto 8) <= crcCalculated;
symbolControl(7 downto 0) <= x"00";
Crc5Calculator: Crc5ITU
port map(
d_i=>symbolControl(31 downto 13), crc_o=>crcCalculated);
txWrite_o <= symbolWrite;
txControl_o <= symbolType;
txData_o <= symbolControl when (symbolType = SYMBOL_CONTROL) else symbolData;
-----------------------------------------------------------------------------
-- Packet timeout logic.
-----------------------------------------------------------------------------
-- Note that the timer is one bit larger to be able to detect a timeout on a
-- free-running counter.
process(areset_n, clk)
begin
if (areset_n = '0') then
timeoutCounter <= (others=>'0');
elsif (clk'event and clk = '1') then
timeoutCounter <= timeoutCounter + 1;
end if;
end process;
timeoutElapsed <= timeoutCounter - timeoutFrame;
timeoutDelta <= unsigned('0' & portLinkTimeout_i) - timeoutElapsed;
timeoutExpired <= timeoutDelta(TIMEOUT_WIDTH);
timeoutFrame <= unsigned(timeoutMemoryOut);
TimeoutMemory: MemorySimpleDualPortAsync
generic map(ADDRESS_WIDTH=>5, DATA_WIDTH=>TIMEOUT_WIDTH+1, INIT_VALUE=>'0')
port map(
clkA_i=>clk, enableA_i=>timeoutWrite,
addressA_i=>timeoutAddress, dataA_i=>std_logic_vector(timeoutCounter),
addressB_i=>std_logic_vector(ackIdCurrent), dataB_o=>timeoutMemoryOut);
-----------------------------------------------------------------------------
-- Main outbound symbol handler, synchronous part.
-----------------------------------------------------------------------------
process(areset_n, clk)
begin
if (areset_n = '0') then
stateCurrent <= STATE_UNINITIALIZED;
statusReceivedCurrent <= '0';
counterCurrent <= 0;
symbolsTransmittedCurrent <= 0;
frameStateCurrent <= FRAME_START;
ackIdCurrent <= (others => '0');
ackIdWindowCurrent <= (others => '0');
bufferStatusCurrent <= (others => '0');
elsif (clk'event and clk = '1') then
stateCurrent <= stateNext;
statusReceivedCurrent <= statusReceivedNext;
counterCurrent <= counterNext;
symbolsTransmittedCurrent <= symbolsTransmittedNext;
frameStateCurrent <= frameStateNext;
ackIdCurrent <= ackIdNext;
ackIdWindowCurrent <= ackIdWindowNext;
bufferStatusCurrent <= bufferStatusNext;
end if;
end process;
-----------------------------------------------------------------------------
-- Main outbound symbol handler, combinatorial part.
-----------------------------------------------------------------------------
process(stateCurrent,
statusReceivedCurrent, counterCurrent,
symbolsTransmittedCurrent,
frameStateCurrent, ackIdCurrent, ackIdWindowCurrent, bufferStatusCurrent,
txControlStype0, txControlParameter0, txControlParameter1,
rxControlStype0, rxControlParameter0, rxControlParameter1,
portEnable_i,
localAckIdWrite_i, clrOutstandingAckId_i,
outstandingAckId_i, outboundAckId_i,
txFull_i,
txControlEmpty_i, txControlSymbol_i,
rxControlEmpty_i, rxControlSymbol_i,
portInitialized_i, linkInitialized_i, ackIdStatus_i,
readFrameEmpty_i, readFrameAborted_i,
readWindowEmpty_i,
readContentEmpty_i, readContentEnd_i, readContentData_i,
timeoutExpired)
begin
stateNext <= stateCurrent;
statusReceivedNext <= statusReceivedCurrent;
counterNext <= counterCurrent;
symbolsTransmittedNext <= symbolsTransmittedCurrent;
frameStateNext <= frameStateCurrent;
ackIdNext <= ackIdCurrent;
ackIdWindowNext <= ackIdWindowCurrent;
bufferStatusNext <= bufferStatusCurrent;
txControlUpdate_o <= '0';
rxControlUpdate_o <= '0';
readFrame_o <= '0';
readFrameRestart_o <= '0';
readWindowReset_o <= '0';
readWindowNext_o <= '0';
readContent_o <= '0';
symbolWrite <= '0';
symbolType <= (others=>'U');
stype0 <= (others=>'U');
parameter0 <= (others=>'U');
parameter1 <= (others=>'U');
stype1 <= (others=>'U');
cmd <= (others=>'U');
symbolData <= (others=>'U');
timeoutWrite <= '0';
timeoutAddress <= (others=>'U');
outstandingAckId_o <= std_logic_vector(ackIdCurrent);
outboundAckId_o <= std_logic_vector(ackIdWindowCurrent);
-- Check if a localAckIdWrite is active.
if (localAckIdWrite_i = '1') then
-- A localAckIdWrite is active.
-- Check if all outstanding packets should be discarded.
if (clrOutstandingAckId_i = '1') then
-- Delete all outbound packets.
-- REMARK: Remove all packets in another way... what if uninitialized???
stateNext <= STATE_RECOVER;
end if;
-- Set ackIds.
ackIdNext <= unsigned(outstandingAckId_i);
ackIdWindowNext <= unsigned(outboundAckId_i);
else
-- A localAckIdWrite is not active.
-- Act on the current state.
case (stateCurrent) is
when STATE_UNINITIALIZED =>
-----------------------------------------------------------------------
-- This state is entered at startup. A port that is not initialized
-- should only transmit idle sequences.
-----------------------------------------------------------------------
-- Check if the port is initialized.
if (portInitialized_i = '0') then
-- Port not initialized.
-- Check if any new symbols from the link partner has been received.
if (txControlEmpty_i = '0') then
-- New symbols have been received.
-- Discard all new symbols in this state.
txControlUpdate_o <= '1';
else
-- No new symbols from the link partner.
-- Dont do anything.
end if;
-- Check if any new symbols should be transmitted to the link partner.
if (rxControlEmpty_i = '0') then
-- New symbols should be transmitted.
-- Do not forward any symbols in this state.
rxControlUpdate_o <= '1';
else
-- No new symbols to transmit.
-- Dont do anything.
end if;
-- Check if a new symbol should be transmitted.
if (txFull_i = '0') then
-- A new symbol should be transmitted.
-- Send idle sequence.
symbolWrite <= '1';
symbolType <= SYMBOL_IDLE;
else
-- The outbound fifo is full.
-- Dont do anything.
end if;
-- Check if a new full packet is ready.
if (readFrameEmpty_i = '0') then
-- A new full packet is ready.
-- It is not possible to send the packet now. If the packet is not
-- discarded it might congest the full system if the link does not
-- go initialized. To avoid a congested switch, the packet is
-- discarded and will have to be resent by the source when the link
-- is up and running.
readFrame_o <= '1';
else
-- No new full packets are ready.
-- Dont do anything.
end if;
else
-- Port is initialized.
-- Go to the initialized state and reset the counters.
statusReceivedNext <= '0';
counterNext <= NUMBER_STATUS_TRANSMIT;
symbolsTransmittedNext <= 0;
stateNext <= STATE_PORT_INITIALIZED;
end if;
when STATE_PORT_INITIALIZED =>
-----------------------------------------------------------------------
-- The specification requires a status control symbol being sent at
-- least every 1024 code word until an error-free status has been
-- received. This implies that at most 256 idle sequences should be
-- sent in between status control symbols. Once an error-free status has
-- been received, status symbols may be sent more rapidly. At least 15
-- statuses has to be transmitted once an error-free status has been
-- received.
---------------------------------------------------------------------
-- Check if the port is initialized.
if (portInitialized_i = '1') then
-- Port is initialized.
-- Check if we are ready to change state to linkInitialized.
if ((linkInitialized_i = '1') and (counterCurrent = 0)) then
-- Receiver has received enough error free status symbols and we have
-- transmitted enough.
-- Initialize framing before entering the normal state.
ackIdWindowNext <= ackIdCurrent;
frameStateNext <= FRAME_START;
readWindowReset_o <= '1';
-- Considder the link initialized.
stateNext <= STATE_NORMAL;
else
-- Not ready to change state to linkInitialized.
-- Dont do anything.
end if;
-- Check if any new symbols from the link partner has been received.
if (txControlEmpty_i = '0') then
-- New symbols have been received.
-- Check if the new symbol is a status.
if (txControlStype0 = STYPE0_STATUS) then
-- A new status control symbol has been received.
statusReceivedNext <= '1';
-- Set the ackId and the linkpartner buffer status to what is indicated
-- in the received control symbol.
ackIdNext <= unsigned(txControlParameter0);
bufferStatusNext <= txControlParameter1;
else
-- Did not receive a status control symbol.
-- Discard it.
end if;
-- Update to the next control symbol received by the receiver.
txControlUpdate_o <= '1';
else
-- No new symbols from the link partner.
-- Dont do anything.
end if;
-- Check if any new symbols should be transmitted to the link partner.
if (rxControlEmpty_i = '0') then
-- New symbols should be transmitted.
-- Do not forward any symbols in this state.
rxControlUpdate_o <= '1';
else
-- No new symbols to transmit.
-- Dont do anything.
end if;
-- Check if a new symbol may be transmitted.
if (txFull_i = '0') then
-- A new symbol can be transmitted.
-- Check if idle sequence or a status symbol should be transmitted.
if (((statusReceivedCurrent = '0') and (symbolsTransmittedCurrent = 255)) or
((statusReceivedCurrent = '1') and (symbolsTransmittedCurrent > 15))) then
-- A status symbol should be transmitted.
-- Send a status control symbol to the link partner.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_NOP;
cmd <= "000";
-- Reset idle sequence transmission counter.
symbolsTransmittedNext <= 0;
-- Check if the number of transmitted statuses should be updated.
if (statusReceivedCurrent = '1') and (counterCurrent /= 0) then
counterNext <= counterCurrent - 1;
end if;
else
-- A idle sequence should be transmitted.
symbolWrite <= '1';
symbolType <= SYMBOL_IDLE;
-- Increment the idle sequence transmission counter.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
end if;
else
-- Cannot send a new symbol.
-- Dont do anything.
end if;
else
-- Go back to the uninitialized state.
stateNext <= STATE_UNINITIALIZED;
end if;
when STATE_NORMAL =>
-------------------------------------------------------------------
-- This state is the normal state. It relays frames and handle flow
-- control.
-------------------------------------------------------------------
-- Check that both the port and link is initialized.
if (portInitialized_i = '1') and (linkInitialized_i = '1') then
-- The port and link is initialized.
-- Check if any control symbol has been received from the link
-- partner.
if (txControlEmpty_i = '0') then
-- A control symbol has been received.
-- Check the received control symbol.
case txControlStype0 is
when STYPE0_STATUS =>
-- Save the number of buffers in the link partner.
bufferStatusNext <= txControlParameter1;
when STYPE0_PACKET_ACCEPTED =>
-- The link partner is accepting a frame.
-- Save the number of buffers in the link partner.
bufferStatusNext <= txControlParameter1;
-- Check if expecting this type of reply and that the ackId is
-- expected.
if ((ackIdCurrent /= ackIdWindowCurrent) and
(ackIdCurrent = unsigned(txControlParameter0))) then
-- The packet-accepted is expected and the ackId is the expected.
-- The frame has been accepted by the link partner.
-- Update to a new buffer and increment the ackId.
readFrame_o <= '1';
ackIdNext <= ackIdCurrent + 1;
else
-- Unexpected packet-accepted or packet-accepted for
-- unexpected ackId.
counterNext <= NUMBER_LINK_RESPONSE_RETRIES;
stateNext <= STATE_SEND_LINK_REQUEST;
end if;
when STYPE0_PACKET_RETRY =>
-- The link partner has asked for a frame retransmission.
-- Save the number of buffers in the link partner.
bufferStatusNext <= txControlParameter1;
-- Check if the ackId is the one expected.
if (ackIdCurrent = unsigned(txControlParameter0)) then
-- The ackId to retry is expected.
-- Go to the output-retry-stopped state.
stateNext <= STATE_OUTPUT_RETRY_STOPPED;
else
-- Unexpected ackId to retry.
counterNext <= NUMBER_LINK_RESPONSE_RETRIES;
stateNext <= STATE_SEND_LINK_REQUEST;
end if;
when STYPE0_PACKET_NOT_ACCEPTED =>
-- Packet was rejected by the link-partner.
-- REMARK: Indicate that this has happened to the outside...
counterNext <= NUMBER_LINK_RESPONSE_RETRIES;
stateNext <= STATE_SEND_LINK_REQUEST;
when STYPE0_LINK_RESPONSE =>
-- Dont expect or need a link-response in this state.
-- Discard it.
when STYPE0_VC_STATUS =>
-- Not supported.
-- Discard it.
when STYPE0_RESERVED =>
-- Not supported.
-- Discard it.
when STYPE0_IMPLEMENTATION_DEFINED =>
-- Not supported.
-- Discard it.
when others =>
null;
end case;
-- Indicate the control symbol has been processed.
txControlUpdate_o <= '1';
else
-- No control symbol has been received.
-- Check if the oldest frame timeout has expired.
if ((ackIdCurrent /= ackIdWindowCurrent) and
(timeoutExpired = '1')) then
-- There has been a timeout on a transmitted frame.
-- Send link-request.
counterNext <= NUMBER_LINK_RESPONSE_RETRIES;
stateNext <= STATE_SEND_LINK_REQUEST;
else
-- There has been no timeout.
-- Check if the outbound fifo needs new data.
if (txFull_i = '0') then
-- There is room available in the outbound FIFO.
-- Check if there are any events from the receiver.
if (rxControlEmpty_i = '0') then
-- A symbol from the receiver should be transmitted.
-- Send the receiver symbol and a NOP.
-- REMARK: Combine this symbol with an STYPE1 to more effectivly
-- utilize the link.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= rxControlStype0;
parameter0 <= rxControlParameter0;
parameter1 <= rxControlParameter1;
stype1 <= STYPE1_NOP;
cmd <= "000";
-- Remove the symbol from the fifo.
rxControlUpdate_o <= '1';
-- Check if the transmitted symbol contains status about
-- available buffers.
if ((rxControlStype0 = STYPE0_PACKET_ACCEPTED) or
(rxControlStype0 = STYPE0_PACKET_RETRY)) then
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
else
-- A symbol not containing the bufferStatus has been sent.
-- REMARK: symbolsTransmitted might overflow...
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
end if;
else
-- No events from the receiver.
-- Check if a status symbol must be sent.
if (symbolsTransmittedCurrent = 255) then
-- A status symbol must be sent.
-- Reset the number of transmitted symbols between statuses.
symbolsTransmittedNext <= 0;
-- Send status.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_NOP;
cmd <= "000";
else
-- A status symbol does not have to be sent.
-- Check if a frame transfer is in progress.
case frameStateCurrent is
when FRAME_START =>
---------------------------------------------------------------
-- No frame has been started.
---------------------------------------------------------------
-- Wait for a new frame to arrive from the frame buffer,
-- for new buffers to be available at the link-partner
-- and also check that a maximum 31 frames are outstanding.
if ((readWindowEmpty_i = '0') and (bufferStatusCurrent /= "00000") and
((ackIdWindowCurrent - ackIdCurrent) /= 31)) then
-- New data is available for transmission and there
-- is room to receive it at the other side.
-- Indicate that a control symbol has been sent to start the
-- transmission of the frame.
frameStateNext <= FRAME_CHECK;
-- Update the output from the frame buffer to contain the
-- data when it is read later.
readContent_o <= '1';
else
-- There are no frame data to send or the link partner has
-- no available buffers.
-- Send idle-sequence.
symbolWrite <= '1';
symbolType <= SYMBOL_IDLE;
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
end if;
when FRAME_CHECK =>
-------------------------------------------------------
-- Check if we are allowed to transmit this packet.
-------------------------------------------------------
-- Check if this packet is allowed to be transmitted.
if ((portEnable_i = '1') or (readContentData_i(19 downto 16) = FTYPE_MAINTENANCE_CLASS)) then
-- The packet may be transmitted.
-- Indicate that a control symbol has been sent to start the
-- transmission of the frame.
frameStateNext <= FRAME_ACKID;
-- Send a control symbol to start the packet and a status to complete
-- the symbol.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_START_OF_PACKET;
cmd <= "000";
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
else
-- The packet should be discarded.
-- Check that there are no outstanding packets that
-- has not been acknowledged.
if(ackIdWindowCurrent /= ackIdCurrent) then
-- There are packets that has not been acknowledged.
-- Send idle-sequence.
symbolWrite <= '1';
symbolType <= SYMBOL_IDLE;
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
else
-- No unacknowledged packets.
-- It is now safe to remove the unallowed frame.
readFrame_o <= '1';
-- Go back and send a new frame.
frameStateNext <= FRAME_START;
end if;
end if;
when FRAME_ACKID =>
---------------------------------------------------------------
-- Send the first packet content containing our current
-- ackId.
---------------------------------------------------------------
-- Write a new data symbol and fill in our ackId on the
-- packet.
symbolWrite <= '1';
symbolType <= SYMBOL_DATA;
symbolData <= std_logic_vector(ackIdWindowCurrent) & "0" & readContentData_i(25 downto 0);
-- Continue to send the rest of the body of the packet.
readContent_o <= '1';
frameStateNext <= FRAME_BODY;
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
when FRAME_BODY =>
---------------------------------------------------------------
-- The frame has not been fully sent.
-- Send a data symbol.
---------------------------------------------------------------
-- REMARK: Add support for partial frames...
-- Check if the frame is ending.
if (readContentEnd_i = '0') then
-- The frame is not ending.
-- Write a new data symbol.
symbolWrite <= '1';
symbolType <= SYMBOL_DATA;
symbolData <= readContentData_i;
-- Continue to send the rest of the body of the packet.
readContent_o <= '1';
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
else
-- The frame is ending.
-- Update the window to the next frame.
-- It takes one tick for the output from the frame
-- buffer to get updated.
readWindowNext_o <= '1';
-- Proceed to check if there is another frame to start
-- with directly.
frameStateNext <= FRAME_END;
end if;
when FRAME_END =>
---------------------------------------------------------------
-- A frame has ended and the window has been updated.
-- Check if the next symbol should end the frame or if a
-- new one should be started.
---------------------------------------------------------------
-- Check if there is a new frame pending.
if (readWindowEmpty_i = '1') then
-- No new frame is pending.
-- Send a control symbol to end the packet.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_END_OF_PACKET;
cmd <= "000";
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
end if;
-- Update the window ackId.
ackIdWindowNext <= ackIdWindowCurrent + 1;
-- Start timeout supervision for transmitted frame.
timeoutWrite <= '1';
timeoutAddress <= std_logic_vector(ackIdWindowCurrent);
-- Start a new frame the next time.
frameStateNext <= FRAME_START;
when others =>
---------------------------------------------------------------
--
---------------------------------------------------------------
null;
end case;
end if;
end if;
else
-- Wait for new storage in the transmission FIFO to become
-- available.
-- Dont do anything.
end if;
end if;
end if;
else
-- The port or the link has become uninitialized.
-- Go back to the uninitialized state.
stateNext <= STATE_UNINITIALIZED;
end if;
when STATE_OUTPUT_RETRY_STOPPED =>
-----------------------------------------------------------------------
-- This is the output-retry-stopped state described in 5.9.1.5.
-----------------------------------------------------------------------
-- Check if the outbound fifo needs new data.
if (txFull_i = '0') then
-- There is room available in the outbound FIFO.
-- Send a restart-from-retry control symbol to acknowledge the restart
-- of the frame.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_RESTART_FROM_RETRY;
cmd <= "000";
-- Make sure there wont be any timeout before the frame is
-- starting to be retransmitted.
timeoutWrite <= '1';
timeoutAddress <= std_logic_vector(ackIdCurrent);
-- Restart the frame transmission.
ackIdWindowNext <= ackIdCurrent;
frameStateNext <= FRAME_START;
readWindowReset_o <= '1';
-- Proceed back to the normal state.
stateNext <= STATE_NORMAL;
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
end if;
when STATE_SEND_LINK_REQUEST =>
-----------------------------------------------------------------------
-- Send a link-request symbol when the transmission fifo is ready. Then
-- always proceed to the output-error-state.
-----------------------------------------------------------------------
-- Check if the outbound fifo needs new data.
if (txFull_i = '0') then
-- There is room available in the outbound FIFO.
-- Send a link-request symbol.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_LINK_REQUEST;
cmd <= LINK_REQUEST_CMD_INPUT_STATUS;
-- Write the current timer value.
timeoutWrite <= '1';
timeoutAddress <= std_logic_vector(ackIdCurrent);
-- Proceed to the output-error-stopped state.
stateNext <= STATE_OUTPUT_ERROR_STOPPED;
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
end if;
when STATE_OUTPUT_ERROR_STOPPED =>
-------------------------------------------------------------------
-- This state is the error stopped state described in 5.13.2.7.
-------------------------------------------------------------------
-- Check that both the port and link is initialized.
if (portInitialized_i = '1') and (linkInitialized_i = '1') then
-- The port and link is initialized.
-- Check if any control symbol has been received from the link
-- partner.
if (txControlEmpty_i = '0') then
-- A control symbol has been received.
-- Check the received control symbol.
case txControlStype0 is
when STYPE0_PACKET_ACCEPTED =>
-- Wait for a link-response.
-- Discard these.
when STYPE0_PACKET_RETRY =>
-- Wait for a link-response.
-- Discard these.
when STYPE0_PACKET_NOT_ACCEPTED =>
-- Wait for a link-response.
-- Discard these.
when STYPE0_STATUS =>
-- Wait for a link-response.
-- Discard these.
when STYPE0_LINK_RESPONSE =>
-- Check if the link partner return value is acceptable.
if ((unsigned(txControlParameter0) - ackIdCurrent) <=
(ackIdWindowCurrent - ackIdCurrent)) then
-- Recoverable error.
-- Use the received ackId and recover by removing packets
-- that were received by the link-partner.
ackIdWindowNext <= unsigned(txControlParameter0);
stateNext <= STATE_RECOVER;
else
-- Totally out of sync.
stateNext <= STATE_FATAL_ERROR;
end if;
when STYPE0_VC_STATUS =>
-- Not supported.
when STYPE0_RESERVED =>
-- Not supported.
when STYPE0_IMPLEMENTATION_DEFINED =>
-- Not supported.
when others =>
null;
end case;
-- Indicate the control symbol has been processed.
txControlUpdate_o <= '1';
else
-- No control symbol has been received.
-- Check if the timeout for a link-response has expired.
if (timeoutExpired = '1') then
-- There was no reply on the link-request.
-- Count the number of retransmissions and abort if
-- no reply has been received for too many times.
if (counterCurrent /= 0) then
-- Not sent link-request too many times.
-- Send another link-request.
counterNext <= counterCurrent - 1;
stateNext <= STATE_SEND_LINK_REQUEST;
else
-- No response for too many times.
stateNext <= STATE_FATAL_ERROR;
end if;
else
-- There has been no timeout.
-- Check if the outbound fifo needs new data.
if (txFull_i = '0') then
-- There is room available in the outbound FIFO.
-- Check if there are any events from the receiver.
if (rxControlEmpty_i = '0') then
-- A symbol from the receiver should be transmitted.
-- Send the receiver symbol and a NOP.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= rxControlStype0;
parameter0 <= rxControlParameter0;
parameter1 <= rxControlParameter1;
stype1 <= STYPE1_NOP;
cmd <= "000";
-- Remove the symbol from the fifo.
rxControlUpdate_o <= '1';
-- Check if the transmitted symbol contains status about
-- available buffers.
-- The receiver never send any status so that does not have
-- to be checked.
if ((rxControlStype0 = STYPE0_PACKET_ACCEPTED) or
(rxControlStype0 = STYPE0_PACKET_RETRY)) then
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
else
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
end if;
else
-- No events from the receiver.
-- There are no frame data to send or the link partner has
-- no available buffers.
-- Check if a status symbol must be sent.
if (symbolsTransmittedCurrent = 255) then
-- A status symbol must be sent.
-- Reset the number of transmitted symbols between statuses.
symbolsTransmittedNext <= 0;
-- Send status.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_NOP;
cmd <= "000";
else
-- A status symbol does not have to be sent.
-- Send idle-sequence.
symbolWrite <= '1';
symbolType <= SYMBOL_IDLE;
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
end if;
end if;
else
-- Wait for new storage in the transmission FIFO to become
-- available.
-- Dont do anything.
end if;
end if;
end if;
else
-- The port or the link has become uninitialized.
-- Go back to the uninitialized state.
stateNext <= STATE_UNINITIALIZED;
end if;
when STATE_RECOVER =>
-----------------------------------------------------------------------
-- A recoverable error condition has occurred.
-- When this state is entered, ackIdWindow should contain the ackId to
-- proceed with.
-----------------------------------------------------------------------
-- Check if the expected ackId has incremented enough.
if (ackIdCurrent /= ackIdWindowCurrent) then
-- Remove this frame. It has been received by the link-partner.
readFrame_o <= '1';
ackIdNext <= ackIdCurrent + 1;
else
-- Keep this frame.
-- Restart the window and the frame transmission.
frameStateNext <= FRAME_START;
readWindowReset_o <= '1';
stateNext <= STATE_NORMAL;
end if;
when STATE_FATAL_ERROR =>
-----------------------------------------------------------------------
-- A fatal error condition has occurred.
-----------------------------------------------------------------------
-- Reset the window and resynchronize the link.
-- REMARK: Count these situations...
-- REMARK: Do something else here???
readWindowReset_o <= '1';
stateNext <= STATE_UNINITIALIZED;
when others =>
-------------------------------------------------------------------
--
-------------------------------------------------------------------
null;
end case;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
entity RioReceiver is
port(
clk : in std_logic;
areset_n : in std_logic;
-- Status signals used for maintenance.
portEnable_i : in std_logic;
-- Support for localAckIdCSR.
localAckIdWrite_i : in std_logic;
inboundAckId_i : in std_logic_vector(4 downto 0);
inboundAckId_o : out std_logic_vector(4 downto 0);
-- Port input interface.
portInitialized_i : in std_logic;
rxEmpty_i : in std_logic;
rxRead_o : out std_logic;
rxControl_i : in std_logic_vector(1 downto 0);
rxData_i : in std_logic_vector(31 downto 0);
-- Receiver has received a control symbol containing:
-- packet-accepted, packet-retry, packet-not-accepted,
-- status, VC_status, link-response
txControlWrite_o : out std_logic;
txControlSymbol_o : out std_logic_vector(12 downto 0);
-- Reciever wants to signal the link partner:
-- a new frame has been accepted => packet-accepted(rxAckId, bufferStatus)
-- a frame needs to be retransmitted due to buffering =>
-- packet-retry(rxAckId, bufferStatus)
-- a frame is rejected due to errors => packet-not-accepted
-- a link-request should be answered => link-response
rxControlWrite_o : out std_logic;
rxControlSymbol_o : out std_logic_vector(12 downto 0);
-- Status signals used internally.
ackIdStatus_o : out std_logic_vector(4 downto 0);
linkInitialized_o : out std_logic;
-- Frame buffering interface.
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0));
end entity;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
architecture RioReceiverImpl of RioReceiver is
component Crc5ITU is
port(
d_i : in std_logic_vector(18 downto 0);
crc_o : out std_logic_vector(4 downto 0));
end component;
component Crc16CITT is
port(
d_i : in std_logic_vector(15 downto 0);
crc_i : in std_logic_vector(15 downto 0);
crc_o : out std_logic_vector(15 downto 0));
end component;
type StateType is (STATE_UNINITIALIZED, STATE_PORT_INITIALIZED,
STATE_NORMAL,
STATE_INPUT_RETRY_STOPPED, STATE_INPUT_ERROR_STOPPED);
signal state : StateType;
signal statusCounter : natural range 0 to 8;
signal ackId : unsigned(4 downto 0);
signal frameIndex : natural range 0 to 70;
signal stype0 : std_logic_vector(2 downto 0);
signal parameter0 : std_logic_vector(4 downto 0);
signal parameter1 : std_logic_vector(4 downto 0);
signal stype1 : std_logic_vector(2 downto 0);
signal cmd : std_logic_vector(2 downto 0);
signal crc5 : std_logic_vector(4 downto 0);
signal crc5Calculated : std_logic_vector(4 downto 0);
signal crc16Valid : std_logic;
signal crc16Data : std_logic_vector(31 downto 0);
signal crc16Current : std_logic_vector(15 downto 0);
signal crc16Temp : std_logic_vector(15 downto 0);
signal crc16Next : std_logic_vector(15 downto 0);
signal rxRead : std_logic;
begin
linkInitialized_o <= '0' when ((state = STATE_UNINITIALIZED) or
(state = STATE_PORT_INITIALIZED)) else '1';
ackIdStatus_o <= std_logic_vector(ackId);
-----------------------------------------------------------------------------
-- Get the entries in a control symbol.
-----------------------------------------------------------------------------
stype0 <= rxData_i(31 downto 29);
parameter0 <= rxData_i(28 downto 24);
parameter1 <= rxData_i(23 downto 19);
stype1 <= rxData_i(18 downto 16);
cmd <= rxData_i(15 downto 13);
crc5 <= rxData_i(12 downto 8);
-----------------------------------------------------------------------------
-- Entity for CRC-5 calculation on control symbols according to the standard.
-----------------------------------------------------------------------------
Crc5Calculator: Crc5ITU
port map(
d_i=>rxData_i(31 downto 13), crc_o=>crc5Calculated);
-----------------------------------------------------------------------------
-- Entities for CRC-16 calculation on 32-bit data in frames according to the
-- standard.
-----------------------------------------------------------------------------
-- If the CRC is correct, there is either zero in crc16Next if no pad exists
-- or zero in crc16Temp and crc16Data(15 downto 0). This means that crc16Next
-- will always be zero here if the CRC is correct.
crc16Valid <= '1' when (crc16Next = x"0000") else '0';
Crc16High: Crc16CITT
port map(
d_i=>crc16Data(31 downto 16), crc_i=>crc16Current, crc_o=>crc16Temp);
Crc16Low: Crc16CITT
port map(
d_i=>crc16Data(15 downto 0), crc_i=>crc16Temp, crc_o=>crc16Next);
-----------------------------------------------------------------------------
-- Main inbound symbol handler.
-----------------------------------------------------------------------------
rxRead_o <= rxRead;
inboundAckId_o <= std_logic_vector(ackId);
process(areset_n, clk)
begin
if (areset_n = '0') then
state <= STATE_UNINITIALIZED;
rxRead <= '0';
txControlWrite_o <= '0';
txControlSymbol_o <= (others => '0');
rxControlWrite_o <= '0';
rxControlSymbol_o <= (others => '0');
writeFrame_o <= '0';
writeFrameAbort_o <= '0';
writeContent_o <= '0';
writeContentData_o <= (others => '0');
-- REMARK: Use frameIndex instead of this...
statusCounter <= 0;
frameIndex <= 0;
ackId <= (others => '0');
crc16Current <= (others => '0');
crc16Data <= (others => '0');
elsif (clk'event and clk = '1') then
rxRead <= '0';
txControlWrite_o <= '0';
rxControlWrite_o <= '0';
writeFrame_o <= '0';
writeFrameAbort_o <= '0';
writeContent_o <= '0';
-- Check if a locakAckIdWrite is active.
if (localAckIdWrite_i = '1') then
-- A localAckIdWrite is active.
-- Set ackId.
ackId <= unsigned(inboundAckId_i);
else
-- A localAckIdWrite is not active.
-- Act on the current state.
case state is
when STATE_UNINITIALIZED =>
-----------------------------------------------------------------------
-- This state is entered at startup. A port that is not initialized
-- should discard all received symbols.
-----------------------------------------------------------------------
-- Check if the port is initialized.
if (portInitialized_i = '0') then
-- Port not initialized.
-- Check if a new symbol is ready to be read.
if (rxRead = '0') and (rxEmpty_i = '0') then
-- New symbol ready.
-- Discard all received symbols in this state.
rxRead <= '1';
else
-- No new symbol ready to be read.
-- Dont do anything.
end if;
else
-- Port is initialized.
-- Go to the initialized state and reset the counters.
state <= STATE_PORT_INITIALIZED;
statusCounter <= 0;
end if;
when STATE_PORT_INITIALIZED =>
---------------------------------------------------------------------
-- The port has been initialized and status control symbols are being
-- received on the link to check if it is working. Count the number
-- of error-free status symbols and considder the link initialized
-- when enough of them has been received. Frames are not allowed
-- here.
---------------------------------------------------------------------
-- Check if the port is initialized.
if (portInitialized_i = '1') then
-- Port is initialized.
-- Check if a new symbol is ready to be read.
if (rxRead = '0') and (rxEmpty_i = '0') then
-- There is a new symbol to read.
-- Check the type of symbol.
if (rxControl_i = SYMBOL_CONTROL) then
-- This is a control symbol that is not a packet delimiter.
-- Check if the control symbol has a valid checksum.
if (crc5Calculated = crc5) then
-- The control symbol has a valid checksum.
-- Forward the stype0 part of the symbol to the transmitter.
txControlWrite_o <= '1';
txControlSymbol_o <= stype0 & parameter0 & parameter1;
-- Check the stype0 part if we should count the number of
-- error-free status symbols.
if (stype0 = STYPE0_STATUS) then
-- The symbol is a status.
-- Check if enough status symbols have been received.
if (statusCounter = 7) then
-- Enough status symbols have been received.
-- Reset all packets.
frameIndex <= 0;
writeFrameAbort_o <= '1';
-- Set the link as initialized.
state <= STATE_NORMAL;
else
-- Increase the number of error-free status symbols that
-- has been received.
statusCounter <= statusCounter + 1;
end if;
else
-- The symbol is not a status.
-- Dont do anything.
end if;
else
-- A control symbol with CRC5 error was recevied.
statusCounter <= 0;
end if;
else
-- Symbol that is not allowed in this state have been received.
-- Discard it.
end if;
-- Update to the next symbol.
rxRead <= '1';
else
-- No new symbol ready to be read.
-- Dont do anything.
end if;
else
-- Go back to the uninitialized state.
state <= STATE_UNINITIALIZED;
end if;
when STATE_NORMAL =>
---------------------------------------------------------------------
-- The port has been initialized and enough error free status symbols
-- have been received. Forward data frames to the frame buffer
-- interface. This is the normal operational state.
---------------------------------------------------------------------
-- Check that the port is initialized.
if (portInitialized_i = '1') then
-- The port and link is initialized.
-- Check if a new symbol is ready to be read.
if (rxRead = '0') and (rxEmpty_i = '0') then
-- There is a new symbol to read.
-- Check the type of symbol.
if (rxControl_i = SYMBOL_CONTROL) then
-- This is a control symbol with or without a packet delimiter.
-- Check if the control symbol has a valid CRC-5.
if (crc5Calculated = crc5) then
-- The control symbol is correct.
-- Forward the stype0 part of the symbol to the transmitter.
txControlWrite_o <= '1';
txControlSymbol_o <= stype0 & parameter0 & parameter1;
-- Check the stype1 part.
case stype1 is
when STYPE1_START_OF_PACKET =>
-------------------------------------------------------------
-- Start the reception of a new frame or end a currently
-- ongoing frame.
-------------------------------------------------------------
-- Check if a frame has already been started.
if (frameIndex /= 0) then
-- A frame is already started.
-- Complete the last frame and start to ackumulate a new one
-- and update the ackId.
-- Check the CRC-16 and the length of the received frame.
if (crc16Valid = '1') and (frameIndex > 3) then
-- The CRC-16 is ok.
-- Reset the frame index to indicate the frame is started.
frameIndex <= 1;
-- Update the frame buffer to indicate that the frame has
-- been completly received.
writeFrame_o <= '1';
-- Update ackId.
ackId <= ackId + 1;
-- Send packet-accepted.
-- The buffer status is appended by the transmitter
-- when sent to get the latest number.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_ACCEPTED & std_logic_vector(ackId) & "11111";
else
-- The CRC-16 is not ok.
-- Make the transmitter send a packet-not-accepted to indicate
-- that the received packet contained a CRC error.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED &
"00000" &
PACKET_NOT_ACCEPTED_CAUSE_PACKET_CRC;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
else
-- No frame has been started.
-- Reset the frame index to indicate the frame is started.
frameIndex <= 1;
end if;
when STYPE1_END_OF_PACKET =>
-------------------------------------------------------------
-- End the reception of an old frame.
-------------------------------------------------------------
-- Check the CRC-16 and the length of the received frame.
if (crc16Valid = '1') and (frameIndex > 3) then
-- The CRC-16 is ok.
-- Reset frame reception to indicate that no frame is ongoing.
frameIndex <= 0;
-- Update the frame buffer to indicate that the frame has
-- been completly received.
writeFrame_o <= '1';
-- Update ackId.
ackId <= ackId + 1;
-- Send packet-accepted.
-- The buffer status is appended by the transmitter
-- when sent to get the latest number.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_ACCEPTED & std_logic_vector(ackId) & "11111";
else
-- The CRC-16 is not ok.
-- Make the transmitter send a packet-not-accepted to indicate
-- that the received packet contained a CRC error.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED &
"00000" &
PACKET_NOT_ACCEPTED_CAUSE_PACKET_CRC;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
when STYPE1_STOMP =>
-------------------------------------------------------------
-- Restart the reception of an old frame.
-------------------------------------------------------------
-- See 5.10 in the standard.
-- Make the transmitter send a packet-retry to indicate
-- that the packet cannot be accepted.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_RETRY & std_logic_vector(ackId) & "11111";
-- Enter the input retry-stopped state.
state <= STATE_INPUT_RETRY_STOPPED;
when STYPE1_RESTART_FROM_RETRY =>
-------------------------------------------------------------
-- The receiver indicates a restart from a retry sent
-- from us.
-------------------------------------------------------------
-- See 5.10 in the standard.
-- Protocol error, this symbol should not be received here since
-- we should have been in input-retry-stopped.
-- Send a packet-not-accepted to indicate that a protocol
-- error has occurred.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED &
"00000" &
PACKET_NOT_ACCEPTED_CAUSE_GENERAL_ERROR;
state <= STATE_INPUT_ERROR_STOPPED;
when STYPE1_LINK_REQUEST =>
-------------------------------------------------------------
-- Reply to a LINK-REQUEST.
-------------------------------------------------------------
-- Check the command part.
if (cmd = "100") then
-- Return input port status command.
-- This functions as a link-request(restart-from-error)
-- control symbol under error situations.
-- Send a link response containing an ok reply.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_LINK_RESPONSE & std_logic_vector(ackId) & "10000";
elsif (cmd = "011") then
-- Reset device command.
-- Discard this.
else
-- Unsupported command.
-- Discard this.
end if;
-- Abort the frame and reset frame reception.
frameIndex <= 0;
writeFrameAbort_o <= '1';
when STYPE1_MULTICAST_EVENT =>
-------------------------------------------------------------
-- Multicast symbol.
-------------------------------------------------------------
-- Discard the symbol.
when STYPE1_RESERVED =>
-------------------------------------------------------------
-- Reserved.
-------------------------------------------------------------
-- Not supported, dont do anything.
when STYPE1_NOP =>
-------------------------------------------------------------
-- NOP, no operation.
-------------------------------------------------------------
-- Dont do anything.
when others =>
-------------------------------------------------------------
--
-------------------------------------------------------------
-- NOP, no operation, dont do anything.
null;
end case;
else
-- The control symbol contains a crc error.
-- Send a packet-not-accepted to indicate that a corrupted
-- control-symbol has been received and change state.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED &
"00000" &
PACKET_NOT_ACCEPTED_CAUSE_CONTROL_CRC;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
elsif (rxControl_i = SYMBOL_DATA) then
-- This is a data symbol.
-- REMARK: Add check for in-the-middle-crc here...
-- Check if a frame has been started.
-- Index=0 not started
-- index=1 started and expecting to receive the first data.
-- index=others, the index of the received data.
if (frameIndex /= 0) and (frameIndex /= 70) then
-- A frame has been started and is not too long.
-- Check if the ackId is correct.
if (((frameIndex = 1) and (unsigned(rxData_i(31 downto 27)) = ackId)) or
(frameIndex /= 1)) then
-- This is the first data symbol containing the ackId which
-- is matching or receiving the rest of the frame.
-- Check if the packet ftype is allowed.
-- If the portEnable is deasserted only maintenance
-- packets are allowed.
if (((frameIndex = 1) and
((portEnable_i = '1') or (rxData_i(19 downto 16) = FTYPE_MAINTENANCE_CLASS))) or
(frameIndex /= 1)) then
-- The packet is allowed.
-- Check if there is buffers available to store the new packet.
if(writeFrameFull_i = '0') then
-- There is buffering space available to store the new data.
-- Write the data to the frame FIFO.
writeContent_o <= '1';
writeContentData_o <= rxData_i;
-- Increment the number of received data symbols.
frameIndex <= frameIndex + 1;
-- Update the saved crc result with the output from the CRC calculation.
if (frameIndex = 1) then
-- Note that the ackId should not be included when the CRC
-- is calculated.
crc16Data <= "000000" & rxData_i(25 downto 0);
crc16Current <= (others => '1');
else
crc16Data <= rxData_i;
crc16Current <= crc16Next;
end if;
else
-- The packet buffer is full.
-- Let the link-partner resend the packet.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_RETRY & std_logic_vector(ackId) & "11111";
state <= STATE_INPUT_RETRY_STOPPED;
end if;
else
-- The non-maintenance packets are not allowed.
-- Send packet-not-accepted.
rxControlWrite_o <= '1';
rxControlSymbol_o <=
STYPE0_PACKET_NOT_ACCEPTED & "00000" & PACKET_NOT_ACCEPTED_CAUSE_NON_MAINTENANCE_STOPPED;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
else
-- The ackId is unexpected.
-- Send packet-not-accepted.
rxControlWrite_o <= '1';
rxControlSymbol_o <=
STYPE0_PACKET_NOT_ACCEPTED & "00000" & PACKET_NOT_ACCEPTED_CAUSE_UNEXPECTED_ACKID;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
else
-- A frame has not been started or is too long.
-- Send packet-not-accepted.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED & "00000" & PACKET_NOT_ACCEPTED_CAUSE_GENERAL_ERROR;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
else
-- Idle sequence received.
-- Discard these.
end if;
-- Update to the next symbol.
rxRead <= '1';
else
-- No new symbol received.
-- Dont do anything.
end if;
else
-- The port has become uninitialized.
-- Go back to the uninitialized state.
state <= STATE_UNINITIALIZED;
end if;
when STATE_INPUT_RETRY_STOPPED =>
---------------------------------------------------------------------
-- This state is entered when a frame could not be accepted. All
-- symbols except restart-from-retry and link-request are discarded.
-- A restart-from-retry triggers a state change into the normal
-- link-initialized state.
---------------------------------------------------------------------
-- Check that the port is initialized.
if (portInitialized_i = '1') then
-- The port and link is initialized.
-- Check if a new symbol is ready to be read.
if (rxRead = '0') and (rxEmpty_i = '0') then
-- There is a new symbol to read.
-- Check the type of symbol.
if (rxControl_i = SYMBOL_CONTROL) then
-- This is a control symbol with or without a packet delimiter.
-- Check if the control symbol has a valid CRC-5.
if (crc5Calculated = crc5) then
-- The control symbol is correct.
-- Forward the stype0 part of the symbol to the transmitter.
txControlWrite_o <= '1';
txControlSymbol_o <= stype0 & parameter0 & parameter1;
-- Check the stype1 part.
case stype1 is
when STYPE1_RESTART_FROM_RETRY =>
-------------------------------------------------------------
-- The receiver indicates a restart from a retry sent
-- from us.
-------------------------------------------------------------
-- Abort the frame and reset frame reception.
frameIndex <= 0;
writeFrameAbort_o <= '1';
-- Go back to the normal operational state.
state <= STATE_NORMAL;
when STYPE1_LINK_REQUEST =>
-------------------------------------------------------------
-- Received a link-request.
-------------------------------------------------------------
-- Check the command part.
if (cmd = "100") then
-- Return input port status command.
-- This functions as a link-request(restart-from-error)
-- control symbol under error situations.
-- Send a link response containing an ok reply.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_LINK_RESPONSE & std_logic_vector(ackId) & "00100";
elsif (cmd = "011") then
-- Reset device command.
-- Discard this.
else
-- Unsupported command.
-- Discard this.
end if;
-- Abort the frame and reset frame reception.
frameIndex <= 0;
writeFrameAbort_o <= '1';
-- Go back to the normal operational state.
state <= STATE_NORMAL;
when others =>
-------------------------------------------------------------
--
-------------------------------------------------------------
-- Discard other control symbols.
null;
end case;
else
-- The control symbol contains a crc error.
-- Send a packet-not-accepted to indicate that a corrupted
-- control-symbol has been received and change state.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED &
"00000" &
PACKET_NOT_ACCEPTED_CAUSE_CONTROL_CRC;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
elsif (rxControl_i = SYMBOL_DATA) then
-- This is a data symbol.
-- Discard all data symbols in this state.
else
-- Idle sequence received.
-- Discard other symbols.
end if;
-- Update to the next symbol.
rxRead <= '1';
else
-- No new symbol received.
-- Dont do anything.
end if;
else
-- The port has become uninitialized.
-- Go back to the uninitialized state.
state <= STATE_UNINITIALIZED;
end if;
when STATE_INPUT_ERROR_STOPPED =>
---------------------------------------------------------------------
-- This state is entered when an error situation has occurred. When in this
-- state, all symbols should be discarded until a link-request-symbols has
-- been received. See section 5.13.2.6 in part 6 of the standard.
-- Note that it is only the input side of the port that are affected, not the
-- output side. Packets may still be transmitted and acknowledges should be
-- accepted.
---------------------------------------------------------------------
-- Check that the port is initialized.
if (portInitialized_i = '1') then
-- The port and link is initialized.
-- Check if a new symbol is ready to be read.
if (rxRead = '0') and (rxEmpty_i = '0') then
-- There is a new symbol to read.
-- Check the type of symbol.
if (rxControl_i = SYMBOL_CONTROL) then
-- This is a control symbol with or without a packet delimiter.
-- Check if the control symbol has a valid CRC-5.
if (crc5Calculated = crc5) then
-- The control symbol is correct.
-- Forward the stype0 part of the symbol to the transmitter.
txControlWrite_o <= '1';
txControlSymbol_o <= stype0 & parameter0 & parameter1;
-- Check the stype1 part.
case stype1 is
when STYPE1_LINK_REQUEST =>
-------------------------------------------------------------
-- Received a link-request.
-------------------------------------------------------------
-- Check the command part.
-- REMARK: Should also send a status-control-symbol
-- directly following this symbol...
if (cmd = "100") then
-- Return input port status command.
-- This functions as a link-request(restart-from-error)
-- control symbol under error situations.
-- Send a link response containing an ok reply.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_LINK_RESPONSE & std_logic_vector(ackId) & "00101";
elsif (cmd = "011") then
-- Reset device command.
-- Discard this.
else
-- Unsupported command.
-- Discard this.
end if;
-- Abort the frame and reset frame reception.
frameIndex <= 0;
writeFrameAbort_o <= '1';
-- Go back to the normal operational state.
state <= STATE_NORMAL;
when others =>
-------------------------------------------------------------
--
-------------------------------------------------------------
-- Discard other control symbols.
null;
end case;
else
-- The control symbol contains a crc error.
-- Error is ignored in this state.
end if;
else
-- Other symbol received.
-- All other symbols are discarded in this state.
end if;
-- Update to the next symbol.
rxRead <= '1';
else
-- No new symbol received.
-- Dont do anything.
end if;
else
-- The port has become uninitialized.
-- Go back to the uninitialized state.
state <= STATE_UNINITIALIZED;
end if;
when others =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
null;
end case;
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
-- A CRC-5 calculator following the implementation proposed in the 2.2
-- standard.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
entity Crc5ITU is
port(
d_i : in std_logic_vector(18 downto 0);
crc_o : out std_logic_vector(4 downto 0));
end entity;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
architecture Crc5Impl of Crc5ITU is
signal d : std_logic_vector(0 to 18);
signal c : std_logic_vector(0 to 4);
begin
-- Reverse the bit vector indexes to make them the same as in the standard.
d(18) <= d_i(0); d(17) <= d_i(1); d(16) <= d_i(2); d(15) <= d_i(3);
d(14) <= d_i(4); d(13) <= d_i(5); d(12) <= d_i(6); d(11) <= d_i(7);
d(10) <= d_i(8); d(9) <= d_i(9); d(8) <= d_i(10); d(7) <= d_i(11);
d(6) <= d_i(12); d(5) <= d_i(13); d(4) <= d_i(14); d(3) <= d_i(15);
d(2) <= d_i(16); d(1) <= d_i(17); d(0) <= d_i(18);
-- Calculate the resulting crc.
c(0) <= d(18) xor d(16) xor d(15) xor d(12) xor
d(10) xor d(5) xor d(4) xor d(3) xor
d(1) xor d(0);
c(1) <= (not d(18)) xor d(17) xor d(15) xor d(13) xor
d(12) xor d(11) xor d(10) xor d(6) xor
d(3) xor d(2) xor d(0);
c(2) <= (not d(18)) xor d(16) xor d(14) xor d(13) xor
d(12) xor d(11) xor d(7) xor d(4) xor
d(3) xor d(1);
c(3) <= (not d(18)) xor d(17) xor d(16) xor d(14) xor
d(13) xor d(10) xor d(8) xor d(3) xor
d(2) xor d(1);
c(4) <= d(18) xor d(17) xor d(15) xor d(14) xor
d(11) xor d(9) xor d(4) xor d(3) xor
d(2) xor d(0);
-- Reverse the bit vector indexes to make them the same as in the standard.
crc_o(4) <= c(0); crc_o(3) <= c(1); crc_o(2) <= c(2); crc_o(1) <= c(3);
crc_o(0) <= c(4);
end architecture;
| bsd-3-clause | 0124bb8b7ccee69d9cf47f74dee4dc94 | 0.484059 | 5.548883 | false | false | false | false |
pkerling/ethernet_mac | ethernet.vhd | 1 | 9,449 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
library ieee;
use ieee.std_logic_1164.all;
-- Prebuilt Ethernet MAC without FIFOs
use work.ethernet_types.all;
use work.miim_types.all;
entity ethernet is
generic(
MIIM_PHY_ADDRESS : t_phy_address := (others => '0');
MIIM_RESET_WAIT_TICKS : natural := 0;
MIIM_POLL_WAIT_TICKS : natural := DEFAULT_POLL_WAIT_TICKS;
MIIM_CLOCK_DIVIDER : positive := 50;
-- You need to supply the current speed via speed_override when MIIM is disabled
MIIM_DISABLE : boolean := FALSE
);
port(
clock_125_i : in std_ulogic;
-- Reset input synchronous to miim_clock_i
reset_i : in std_ulogic;
-- Asynchronous reset output
-- Reset may be asserted when the speed changes to get the system
-- back to a defined state (glitches might occur on the clock)
reset_o : out std_ulogic;
-- MAC address of this station
-- Must not change after reset is deasserted
mac_address_i : in t_mac_address;
-- MII (Media-independent interface)
mii_tx_clk_i : in std_ulogic;
mii_tx_er_o : out std_ulogic;
mii_tx_en_o : out std_ulogic;
mii_txd_o : out std_ulogic_vector(7 downto 0);
mii_rx_clk_i : in std_ulogic;
mii_rx_er_i : in std_ulogic;
mii_rx_dv_i : in std_ulogic;
mii_rxd_i : in std_ulogic_vector(7 downto 0);
-- GMII (Gigabit media-independent interface)
gmii_gtx_clk_o : out std_ulogic;
-- RGMII (Reduced pin count gigabit media-independent interface)
rgmii_tx_ctl_o : out std_ulogic;
rgmii_rx_ctl_i : in std_ulogic;
-- MII Management Interface
miim_clock_i : in std_ulogic;
mdc_o : out std_ulogic;
mdio_io : inout std_ulogic;
-- Status, synchronous to miim_clock_i
link_up_o : out std_ulogic;
speed_o : out t_ethernet_speed;
-- Also synchronous to miim_clock_i if used!
speed_override_i : in t_ethernet_speed := SPEED_UNSPECIFIED;
-- TX from client logic
tx_clock_o : out std_ulogic;
-- Asynchronous reset that deasserts synchronously to tx_clock_o
tx_reset_o : out std_ulogic;
tx_enable_i : in std_ulogic;
tx_data_i : in t_ethernet_data;
tx_byte_sent_o : out std_ulogic;
tx_busy_o : out std_ulogic;
-- RX to client logic
rx_clock_o : out std_ulogic;
-- Asynchronous reset that deasserts synchronously to rx_clock_o
rx_reset_o : out std_ulogic;
rx_frame_o : out std_ulogic;
rx_data_o : out t_ethernet_data;
rx_byte_received_o : out std_ulogic;
rx_error_o : out std_ulogic
);
end entity;
architecture rtl of ethernet is
signal tx_clock : std_ulogic;
signal rx_clock : std_ulogic;
signal reset : std_ulogic := '1';
signal rx_reset : std_ulogic;
signal tx_reset : std_ulogic;
-- Interface between mii_gmii and framing
signal mac_tx_enable : std_ulogic := '0';
signal mac_tx_data : t_ethernet_data;
signal mac_tx_byte_sent : std_ulogic;
signal mac_tx_gap : std_ulogic;
signal mac_rx_frame : std_ulogic;
signal mac_rx_data : t_ethernet_data;
signal mac_rx_byte_received : std_ulogic;
signal mac_rx_error : std_ulogic;
-- Internal MII bus between mii_gmii and mii_gmii_io
signal int_mii_tx_en : std_ulogic;
signal int_mii_txd : std_ulogic_vector(7 downto 0);
signal int_mii_rx_er : std_ulogic;
signal int_mii_rx_dv : std_ulogic;
signal int_mii_rxd : std_ulogic_vector(7 downto 0);
-- MIIM interconnection signals
signal miim_register_address : t_register_address;
signal miim_phy_address_sig : t_phy_address;
signal miim_data_read : t_data;
signal miim_data_write : t_data;
signal miim_req : std_ulogic;
signal miim_ack : std_ulogic;
signal miim_wr_en : std_ulogic;
signal miim_speed : t_ethernet_speed;
signal speed : t_ethernet_speed;
signal link_up : std_ulogic;
begin
reset_o <= reset;
rx_reset_o <= rx_reset;
tx_reset_o <= tx_reset;
tx_clock_o <= tx_clock;
rx_clock_o <= rx_clock;
link_up_o <= link_up;
speed_o <= speed;
miim_phy_address_sig <= MIIM_PHY_ADDRESS;
-- Errors are never transmitted in full-duplex mode
mii_tx_er_o <= '0';
with speed_override_i select speed <=
miim_speed when SPEED_UNSPECIFIED,
speed_override_i when others;
-- Generate MAC reset if necessary
reset_generator_inst : entity work.reset_generator
port map(
clock_i => miim_clock_i,
speed_i => speed,
reset_i => reset_i,
reset_o => reset
);
-- Bring reset into RX and TX clock domains, using:
-- * Asynchronous assertion of reset to guarantee resetting even when the MII clock is not running
-- * Synchronous deassertion of reset to guarantee meeting the reset recovery time of the flip flops
sync_rx_reset_inst : entity work.single_signal_synchronizer
port map(
clock_target_i => rx_clock,
preset_i => reset,
signal_i => '0',
signal_o => rx_reset
);
sync_tx_reset_inst : entity work.single_signal_synchronizer
port map(
clock_target_i => tx_clock,
preset_i => reset,
signal_i => '0',
signal_o => tx_reset
);
mii_gmii_inst : entity work.mii_gmii
port map(
rx_reset_i => rx_reset,
rx_clock_i => rx_clock,
tx_reset_i => tx_reset,
tx_clock_i => tx_clock,
-- MII (Media-independent interface)
mii_tx_en_o => int_mii_tx_en,
mii_txd_o => int_mii_txd,
mii_rx_er_i => int_mii_rx_er,
mii_rx_dv_i => int_mii_rx_dv,
mii_rxd_i => int_mii_rxd,
-- RGMII (Reduced pin count gigabit media-independent interface)
rgmii_tx_ctl_o => open,
rgmii_rx_ctl_i => '0',
-- Interface control signals
speed_select_i => speed,
tx_enable_i => mac_tx_enable,
tx_gap_i => mac_tx_gap,
tx_data_i => mac_tx_data,
tx_byte_sent_o => mac_tx_byte_sent,
rx_frame_o => mac_rx_frame,
rx_data_o => mac_rx_data,
rx_byte_received_o => mac_rx_byte_received,
rx_error_o => mac_rx_error
);
mii_gmii_io_inst : entity work.mii_gmii_io
port map(
clock_125_i => clock_125_i,
clock_tx_o => tx_clock,
clock_rx_o => rx_clock,
speed_select_i => speed,
mii_tx_clk_i => mii_tx_clk_i,
mii_tx_en_o => mii_tx_en_o,
mii_txd_o => mii_txd_o,
mii_rx_clk_i => mii_rx_clk_i,
mii_rx_er_i => mii_rx_er_i,
mii_rx_dv_i => mii_rx_dv_i,
mii_rxd_i => mii_rxd_i,
gmii_gtx_clk_o => gmii_gtx_clk_o,
int_mii_tx_en_i => int_mii_tx_en,
int_mii_txd_i => int_mii_txd,
int_mii_rx_er_o => int_mii_rx_er,
int_mii_rx_dv_o => int_mii_rx_dv,
int_mii_rxd_o => int_mii_rxd
);
framing_inst : entity work.framing
port map(
rx_reset_i => rx_reset,
tx_clock_i => tx_clock,
tx_reset_i => tx_reset,
rx_clock_i => rx_clock,
mac_address_i => mac_address_i,
tx_enable_i => tx_enable_i,
tx_data_i => tx_data_i,
tx_byte_sent_o => tx_byte_sent_o,
tx_busy_o => tx_busy_o,
rx_frame_o => rx_frame_o,
rx_data_o => rx_data_o,
rx_byte_received_o => rx_byte_received_o,
rx_error_o => rx_error_o,
mii_tx_enable_o => mac_tx_enable,
mii_tx_gap_o => mac_tx_gap,
mii_tx_data_o => mac_tx_data,
mii_tx_byte_sent_i => mac_tx_byte_sent,
mii_rx_frame_i => mac_rx_frame,
mii_rx_data_i => mac_rx_data,
mii_rx_byte_received_i => mac_rx_byte_received,
mii_rx_error_i => mac_rx_error
);
miim_gen : if MIIM_DISABLE = FALSE generate
miim_inst : entity work.miim
generic map(
CLOCK_DIVIDER => MIIM_CLOCK_DIVIDER
)
port map(
reset_i => reset_i,
clock_i => miim_clock_i,
register_address_i => miim_register_address,
phy_address_i => miim_phy_address_sig,
data_read_o => miim_data_read,
data_write_i => miim_data_write,
req_i => miim_req,
ack_o => miim_ack,
wr_en_i => miim_wr_en,
mdc_o => mdc_o,
mdio_io => mdio_io
);
miim_control_inst : entity work.miim_control
generic map(
RESET_WAIT_TICKS => MIIM_RESET_WAIT_TICKS,
POLL_WAIT_TICKS => MIIM_POLL_WAIT_TICKS,
DEBUG_OUTPUT => FALSE
)
port map(
reset_i => reset_i,
clock_i => miim_clock_i,
miim_register_address_o => miim_register_address,
miim_data_read_i => miim_data_read,
miim_data_write_o => miim_data_write,
miim_req_o => miim_req,
miim_ack_i => miim_ack,
miim_we_o => miim_wr_en,
link_up_o => link_up,
speed_o => miim_speed,
debug_fifo_we_o => open,
debug_fifo_write_data_o => open
);
end generate;
end architecture;
| bsd-3-clause | e5ba8f58ab64dd342113081228e162c0 | 0.570642 | 2.866808 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/project/altremote/synthesis/altremote.vhd | 6 | 2,971 | -- altremote.vhd
-- Generated using ACDS version 16.1 196
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity altremote is
port (
busy : out std_logic; -- busy.busy
clock : in std_logic := '0'; -- clock.clk
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.data_in
data_out : out std_logic_vector(28 downto 0); -- data_out.data_out
param : in std_logic_vector(2 downto 0) := (others => '0'); -- param.param
read_param : in std_logic := '0'; -- read_param.read_param
read_source : in std_logic_vector(1 downto 0) := (others => '0'); -- read_source.read_source
reconfig : in std_logic := '0'; -- reconfig.reconfig
reset : in std_logic := '0'; -- reset.reset
reset_timer : in std_logic := '0'; -- reset_timer.reset_timer
write_param : in std_logic := '0' -- write_param.write_param
);
end entity altremote;
architecture rtl of altremote is
component altremote_remote_update_0 is
port (
busy : out std_logic; -- busy
data_out : out std_logic_vector(28 downto 0); -- data_out
param : in std_logic_vector(2 downto 0) := (others => 'X'); -- param
read_param : in std_logic := 'X'; -- read_param
reconfig : in std_logic := 'X'; -- reconfig
reset_timer : in std_logic := 'X'; -- reset_timer
write_param : in std_logic := 'X'; -- write_param
data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- data_in
read_source : in std_logic_vector(1 downto 0) := (others => 'X'); -- read_source
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X' -- reset
);
end component altremote_remote_update_0;
begin
remote_update_0 : component altremote_remote_update_0
port map (
busy => busy, -- busy.busy
data_out => data_out, -- data_out.data_out
param => param, -- param.param
read_param => read_param, -- read_param.read_param
reconfig => reconfig, -- reconfig.reconfig
reset_timer => reset_timer, -- reset_timer.reset_timer
write_param => write_param, -- write_param.write_param
data_in => data_in, -- data_in.data_in
read_source => read_source, -- read_source.read_source
clock => clock, -- clock.clk
reset => reset -- reset.reset
);
end architecture rtl; -- of altremote
| gpl-2.0 | 77e21c80e1f79f8123a11b8e8214db36 | 0.47728 | 3.51182 | false | true | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_timer/niosii/synthesis/niosii.vhd | 1 | 84,598 | -- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- pio_0_external_connection.export
reset_reset_n : in std_logic := '0'; -- reset.reset_n
uart_0_rxd : in std_logic := '0'; -- uart_0.rxd
uart_0_txd : out std_logic -- .txd
);
end entity niosii;
architecture rtl of niosii is
component niosii_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
c2 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component niosii_altpll_0;
component niosii_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosii_jtag_uart_0;
component niosii_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(17 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(17 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component niosii_nios2_gen2_0;
component niosii_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosii_onchip_memory2_0;
component niosii_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosii_pio_0;
component niosii_timer_ms is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosii_timer_ms;
component niosii_timer_us is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosii_timer_us;
component niosii_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
chipselect : in std_logic := 'X'; -- chipselect
read_n : in std_logic := 'X'; -- read_n
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
dataavailable : out std_logic; -- dataavailable
readyfordata : out std_logic; -- readyfordata
rxd : in std_logic := 'X'; -- export
txd : out std_logic; -- export
irq : out std_logic -- irq
);
end component niosii_uart_0;
component niosii_mm_interconnect_0 is
port (
altpll_0_c0_clk : in std_logic := 'X'; -- clk
altpll_0_c1_clk : in std_logic := 'X'; -- clk
altpll_0_c2_clk : in std_logic := 'X'; -- clk
clk_0_clk_clk : in std_logic := 'X'; -- clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
pio_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
timer_us_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address
altpll_0_pll_slave_write : out std_logic; -- write
altpll_0_pll_slave_read : out std_logic; -- read
altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_address : out std_logic_vector(0 downto 0); -- address
jtag_uart_0_avalon_jtag_slave_write : out std_logic; -- write
jtag_uart_0_avalon_jtag_slave_read : out std_logic; -- read
jtag_uart_0_avalon_jtag_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_uart_0_avalon_jtag_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(13 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
timer_ms_s1_address : out std_logic_vector(2 downto 0); -- address
timer_ms_s1_write : out std_logic; -- write
timer_ms_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
timer_ms_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
timer_ms_s1_chipselect : out std_logic; -- chipselect
timer_us_s1_address : out std_logic_vector(2 downto 0); -- address
timer_us_s1_write : out std_logic; -- write
timer_us_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
timer_us_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
timer_us_s1_chipselect : out std_logic; -- chipselect
uart_0_s1_address : out std_logic_vector(2 downto 0); -- address
uart_0_s1_write : out std_logic; -- write
uart_0_s1_read : out std_logic; -- read
uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
uart_0_s1_begintransfer : out std_logic; -- begintransfer
uart_0_s1_chipselect : out std_logic -- chipselect
);
end component niosii_mm_interconnect_0;
component niosii_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
receiver2_irq : in std_logic := 'X'; -- irq
receiver3_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosii_irq_mapper;
component altera_irq_clock_crosser is
generic (
IRQ_WIDTH : integer := 1
);
port (
receiver_clk : in std_logic := 'X'; -- clk
sender_clk : in std_logic := 'X'; -- clk
receiver_reset : in std_logic := 'X'; -- reset
sender_reset : in std_logic := 'X'; -- reset
receiver_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
sender_irq : out std_logic_vector(0 downto 0) -- irq
);
end component altera_irq_clock_crosser;
component niosii_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller;
component niosii_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller_001;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [irq_mapper:clk, irq_synchronizer:sender_clk, irq_synchronizer_001:sender_clk, irq_synchronizer_002:sender_clk, jtag_uart_0:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_memory2_0:clk, rst_controller_001:clk]
signal altpll_0_c1_clk : std_logic; -- altpll_0:c1 -> [irq_synchronizer:receiver_clk, mm_interconnect_0:altpll_0_c1_clk, pio_0:clk, rst_controller_002:clk, uart_0:clk]
signal altpll_0_c2_clk : std_logic; -- altpll_0:c2 -> [irq_synchronizer_001:receiver_clk, irq_synchronizer_002:receiver_clk, mm_interconnect_0:altpll_0_c2_clk, rst_controller_003:clk, timer_ms:clk, timer_us:clk]
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata
signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address
signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read
signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write
signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(13 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address
signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in
signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in
signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
signal mm_interconnect_0_timer_us_s1_chipselect : std_logic; -- mm_interconnect_0:timer_us_s1_chipselect -> timer_us:chipselect
signal mm_interconnect_0_timer_us_s1_readdata : std_logic_vector(15 downto 0); -- timer_us:readdata -> mm_interconnect_0:timer_us_s1_readdata
signal mm_interconnect_0_timer_us_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:timer_us_s1_address -> timer_us:address
signal mm_interconnect_0_timer_us_s1_write : std_logic; -- mm_interconnect_0:timer_us_s1_write -> mm_interconnect_0_timer_us_s1_write:in
signal mm_interconnect_0_timer_us_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:timer_us_s1_writedata -> timer_us:writedata
signal mm_interconnect_0_timer_ms_s1_chipselect : std_logic; -- mm_interconnect_0:timer_ms_s1_chipselect -> timer_ms:chipselect
signal mm_interconnect_0_timer_ms_s1_readdata : std_logic_vector(15 downto 0); -- timer_ms:readdata -> mm_interconnect_0:timer_ms_s1_readdata
signal mm_interconnect_0_timer_ms_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:timer_ms_s1_address -> timer_ms:address
signal mm_interconnect_0_timer_ms_s1_write : std_logic; -- mm_interconnect_0:timer_ms_s1_write -> mm_interconnect_0_timer_ms_s1_write:in
signal mm_interconnect_0_timer_ms_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:timer_ms_s1_writedata -> timer_ms:writedata
signal irq_mapper_receiver0_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal irq_mapper_receiver1_irq : std_logic; -- irq_synchronizer:sender_irq -> irq_mapper:receiver1_irq
signal irq_synchronizer_receiver_irq : std_logic_vector(0 downto 0); -- uart_0:irq -> irq_synchronizer:receiver_irq
signal irq_mapper_receiver2_irq : std_logic; -- irq_synchronizer_001:sender_irq -> irq_mapper:receiver2_irq
signal irq_synchronizer_001_receiver_irq : std_logic_vector(0 downto 0); -- timer_us:irq -> irq_synchronizer_001:receiver_irq
signal irq_mapper_receiver3_irq : std_logic; -- irq_synchronizer_002:sender_irq -> irq_mapper:receiver3_irq
signal irq_synchronizer_002_receiver_irq : std_logic_vector(0 downto 0); -- timer_ms:irq -> irq_synchronizer_002:receiver_irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [irq_mapper:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, irq_synchronizer_002:sender_reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal rst_controller_002_reset_out_reset : std_logic; -- rst_controller_002:reset_out -> [irq_synchronizer:receiver_reset, mm_interconnect_0:pio_0_reset_reset_bridge_in_reset_reset, rst_controller_002_reset_out_reset:in]
signal rst_controller_003_reset_out_reset : std_logic; -- rst_controller_003:reset_out -> [irq_synchronizer_001:receiver_reset, irq_synchronizer_002:receiver_reset, mm_interconnect_0:timer_us_reset_reset_bridge_in_reset_reset, rst_controller_003_reset_out_reset:in]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0, rst_controller_003:reset_in0]
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:inv -> jtag_uart_0:av_read_n
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:inv -> jtag_uart_0:av_write_n
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n
signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n
signal mm_interconnect_0_timer_us_s1_write_ports_inv : std_logic; -- mm_interconnect_0_timer_us_s1_write:inv -> timer_us:write_n
signal mm_interconnect_0_timer_ms_s1_write_ports_inv : std_logic; -- mm_interconnect_0_timer_ms_s1_write:inv -> timer_ms:write_n
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [jtag_uart_0:rst_n, nios2_gen2_0:reset_n]
signal rst_controller_002_reset_out_reset_ports_inv : std_logic; -- rst_controller_002_reset_out_reset:inv -> [pio_0:reset_n, uart_0:reset_n]
signal rst_controller_003_reset_out_reset_ports_inv : std_logic; -- rst_controller_003_reset_out_reset:inv -> [timer_ms:reset_n, timer_us:reset_n]
begin
altpll_0 : component niosii_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset
read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read
write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address
readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => altpll_0_c1_clk, -- c1.clk
c2 => altpll_0_c2_clk, -- c2.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
jtag_uart_0 : component niosii_jtag_uart_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
rst_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- avalon_jtag_slave.chipselect
av_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address(0), -- .address
av_read_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv, -- .read_n
av_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
av_write_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv, -- .write_n
av_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
av_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
av_irq => irq_mapper_receiver0_irq -- irq.irq
);
nios2_gen2_0 : component niosii_nios2_gen2_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosii_onchip_memory2_0
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_001_reset_out_reset, -- reset1.reset
reset_req => rst_controller_001_reset_out_reset_req -- .reset_req
);
pio_0 : component niosii_pio_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
out_port => pio_0_external_connection_export -- external_connection.export
);
timer_ms : component niosii_timer_ms
port map (
clk => altpll_0_c2_clk, -- clk.clk
reset_n => rst_controller_003_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_timer_ms_s1_address, -- s1.address
writedata => mm_interconnect_0_timer_ms_s1_writedata, -- .writedata
readdata => mm_interconnect_0_timer_ms_s1_readdata, -- .readdata
chipselect => mm_interconnect_0_timer_ms_s1_chipselect, -- .chipselect
write_n => mm_interconnect_0_timer_ms_s1_write_ports_inv, -- .write_n
irq => irq_synchronizer_002_receiver_irq(0) -- irq.irq
);
timer_us : component niosii_timer_us
port map (
clk => altpll_0_c2_clk, -- clk.clk
reset_n => rst_controller_003_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_timer_us_s1_address, -- s1.address
writedata => mm_interconnect_0_timer_us_s1_writedata, -- .writedata
readdata => mm_interconnect_0_timer_us_s1_readdata, -- .readdata
chipselect => mm_interconnect_0_timer_us_s1_chipselect, -- .chipselect
write_n => mm_interconnect_0_timer_us_s1_write_ports_inv, -- .write_n
irq => irq_synchronizer_001_receiver_irq(0) -- irq.irq
);
uart_0 : component niosii_uart_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_uart_0_s1_address, -- s1.address
begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect
read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n
write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
dataavailable => open, -- .dataavailable
readyfordata => open, -- .readyfordata
rxd => uart_0_rxd, -- external_connection.export
txd => uart_0_txd, -- .export
irq => irq_synchronizer_receiver_irq(0) -- irq.irq
);
mm_interconnect_0 : component niosii_mm_interconnect_0
port map (
altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk
altpll_0_c1_clk => altpll_0_c1_clk, -- altpll_0_c1.clk
altpll_0_c2_clk => altpll_0_c2_clk, -- altpll_0_c2.clk
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
pio_0_reset_reset_bridge_in_reset_reset => rst_controller_002_reset_out_reset, -- pio_0_reset_reset_bridge_in_reset.reset
timer_us_reset_reset_bridge_in_reset_reset => rst_controller_003_reset_out_reset, -- timer_us_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address
altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read
altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address, -- jtag_uart_0_avalon_jtag_slave.address
jtag_uart_0_avalon_jtag_slave_write => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write, -- .write
jtag_uart_0_avalon_jtag_slave_read => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read, -- .read
jtag_uart_0_avalon_jtag_slave_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
timer_ms_s1_address => mm_interconnect_0_timer_ms_s1_address, -- timer_ms_s1.address
timer_ms_s1_write => mm_interconnect_0_timer_ms_s1_write, -- .write
timer_ms_s1_readdata => mm_interconnect_0_timer_ms_s1_readdata, -- .readdata
timer_ms_s1_writedata => mm_interconnect_0_timer_ms_s1_writedata, -- .writedata
timer_ms_s1_chipselect => mm_interconnect_0_timer_ms_s1_chipselect, -- .chipselect
timer_us_s1_address => mm_interconnect_0_timer_us_s1_address, -- timer_us_s1.address
timer_us_s1_write => mm_interconnect_0_timer_us_s1_write, -- .write
timer_us_s1_readdata => mm_interconnect_0_timer_us_s1_readdata, -- .readdata
timer_us_s1_writedata => mm_interconnect_0_timer_us_s1_writedata, -- .writedata
timer_us_s1_chipselect => mm_interconnect_0_timer_us_s1_chipselect, -- .chipselect
uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address
uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write
uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read
uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect
);
irq_mapper : component niosii_irq_mapper
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq
receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
irq_synchronizer : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c1_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_002_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_001_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver1_irq -- sender.irq
);
irq_synchronizer_001 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c2_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_003_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_001_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_001_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver2_irq -- sender.irq
);
irq_synchronizer_002 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c2_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_003_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_001_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_002_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver3_irq -- sender.irq
);
rst_controller : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component niosii_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_002 : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c1_clk, -- clk.clk
reset_out => rst_controller_002_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_003 : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c2_clk, -- clk.clk
reset_out => rst_controller_003_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read;
mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write;
mm_interconnect_0_timer_us_s1_write_ports_inv <= not mm_interconnect_0_timer_us_s1_write;
mm_interconnect_0_timer_ms_s1_write_ports_inv <= not mm_interconnect_0_timer_ms_s1_write;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
rst_controller_002_reset_out_reset_ports_inv <= not rst_controller_002_reset_out_reset;
rst_controller_003_reset_out_reset_ports_inv <= not rst_controller_003_reset_out_reset;
end architecture rtl; -- of niosii
| mit | 27148cfa7ed8b476462581ca7dd672e0 | 0.461039 | 3.759744 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/SyncEdge.vhd | 1 | 3,692 | ---------------------------------------------------------------------------------
-- Title : 1-bit synchronizer
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : SyncEdge.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Simple one-bit synchronizer with edge detect.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
library unisim;
use unisim.vcomponents.all;
entity SyncEdge is
generic (
SYNC_STAGES_G : integer := 2;
CLK_POL_G : sl := '1';
RST_POL_G : sl := '1';
INIT_STATE_G : sl := '0';
GATE_DELAY_G : time := 1 ns
);
port (
-- Clock and reset
clk : in sl;
rst : in sl;
-- Incoming bit, asynchronous
asyncBit : in sl;
-- Outgoing bit, synced to clk
syncBit : out sl;
syncREdge : out sl;
syncFEdge : out sl
);
end SyncEdge;
-- Define architecture
architecture structural of SyncEdge is
signal iSyncBit : sl;
signal syncBitPipe : slv(1 downto 0);
begin
syncBit <= iSyncBit;
U_SyncBit : entity work.SyncBit
generic map (
SYNC_STAGES_G => SYNC_STAGES_G,
CLK_POL_G => CLK_POL_G,
RST_POL_G => RST_POL_G,
INIT_STATE_G => INIT_STATE_G,
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => clk,
rst => rst,
asyncBit => asyncBit,
syncBit => iSyncBit
);
G_RISING : if CLK_POL_G = '1' generate
process (clk) begin
if rising_edge(clk) then
if rst = '1' then
syncREdge <= '0' after GATE_DELAY_G;
syncFEdge <= '0' after GATE_DELAY_G;
syncBitPipe <= (others => '0') after GATE_DELAY_G;
else
syncBitPipe(1) <= syncBitPipe(0) after GATE_DELAY_G;
syncBitPipe(0) <= iSyncBit after GATE_DELAY_G;
if syncBitPipe = "01" then
syncREdge <= '1' after GATE_DELAY_G;
else
syncREdge <= '0' after GATE_DELAY_G;
end if;
if syncBitPipe = "10" then
syncFEdge <= '1' after GATE_DELAY_G;
else
syncFEdge <= '0' after GATE_DELAY_G;
end if;
end if;
end if;
end process;
end generate;
G_FALLING : if CLK_POL_G = '0' generate
process (clk) begin
if falling_edge(clk) then
if rst = '1' then
syncREdge <= '0' after GATE_DELAY_G;
syncFEdge <= '0' after GATE_DELAY_G;
syncBitPipe <= (others => '0') after GATE_DELAY_G;
else
syncBitPipe(1) <= syncBitPipe(0) after GATE_DELAY_G;
syncBitPipe(0) <= iSyncBit after GATE_DELAY_G;
if syncBitPipe = "01" then
syncREdge <= '1' after GATE_DELAY_G;
else
syncREdge <= '0' after GATE_DELAY_G;
end if;
if syncBitPipe = "10" then
syncFEdge <= '1' after GATE_DELAY_G;
else
syncFEdge <= '0' after GATE_DELAY_G;
end if;
end if;
end if;
end process;
end generate;
end structural;
| lgpl-2.1 | b4b998111b7c82636aff5b012d63a153 | 0.444204 | 4.134378 | false | false | false | false |
josemonsalve2/cpeg324_calculator | vivado/hdl/blk_mem_gen_0/blk_mem_gen_0_sim_netlist.vhdl | 1 | 45,199 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Wed May 11 10:40:59 2016
-- Host : josem-Studio-XPS-435MT running 64-bit Ubuntu 14.04.2 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/josem/Documents/Academics/Spring2016/CPEG324TA/Labs/Lab2_VHDL_CALCULATOR/Project/vivadoProject/Lab2Calculator/Lab2Calculator.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_sim_netlist.vhdl
-- Design : blk_mem_gen_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end blk_mem_gen_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_13\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_5\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC;
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12 downto 5) => addra(7 downto 0),
ADDRARDADDR(4 downto 0) => B"00000",
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12 downto 5) => addra(7 downto 0),
ADDRBWRADDR(4 downto 0) => B"10000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 10) => B"000000",
DIADI(9 downto 8) => dina(3 downto 2),
DIADI(7 downto 2) => B"000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(15 downto 10) => B"000000",
DIBDI(9 downto 8) => dina(7 downto 6),
DIBDI(7 downto 2) => B"000000",
DIBDI(1 downto 0) => dina(5 downto 4),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\,
DOADO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\,
DOADO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\,
DOADO(10) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_5\,
DOADO(9 downto 8) => douta(3 downto 2),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\,
DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\,
DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\,
DOADO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_13\,
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\,
DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\,
DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\,
DOBDO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\,
DOBDO(10) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_21\,
DOBDO(9 downto 8) => douta(7 downto 6),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\,
DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\,
DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\,
DOBDO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\,
DOBDO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_29\,
DOBDO(1 downto 0) => douta(5 downto 4),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
ENARDEN => ena,
ENBWREN => ena,
REGCEAREGCE => ena,
REGCEB => ena,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => wea(0),
WEBWE(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end blk_mem_gen_0_blk_mem_gen_prim_width;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.blk_mem_gen_0_blk_mem_gen_prim_wrapper
port map (
addra(7 downto 0) => addra(7 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end blk_mem_gen_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.blk_mem_gen_0_blk_mem_gen_prim_width
port map (
addra(7 downto 0) => addra(7 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end blk_mem_gen_0_blk_mem_gen_top;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.blk_mem_gen_0_blk_mem_gen_generic_cstr
port map (
addra(7 downto 0) => addra(7 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_v8_3_1_synth is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end blk_mem_gen_0_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.blk_mem_gen_0_blk_mem_gen_top
port map (
addra(7 downto 0) => addra(7 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_v8_3_1 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 2.54005 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 256;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 256;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 256;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 256;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_0_blk_mem_gen_v8_3_1 : entity is "yes";
end blk_mem_gen_0_blk_mem_gen_v8_3_1;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_v8_3_1 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.blk_mem_gen_0_blk_mem_gen_v8_3_1_synth
port map (
addra(7 downto 0) => addra(7 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of blk_mem_gen_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_3_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.54005 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of blk_mem_gen_0 : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4";
end blk_mem_gen_0;
architecture STRUCTURE of blk_mem_gen_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 8;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 8;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.54005 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 256;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 256;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 256;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 256;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.blk_mem_gen_0_blk_mem_gen_v8_3_1
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => B"00000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => B"00000000",
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => NLW_U0_doutb_UNCONNECTED(7 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(7 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(7 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(7 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(7 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7 downto 0) => B"00000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 09ea23249643bdb2d1811422d86bd646 | 0.682958 | 3.074762 | false | false | false | false |
FrankBuss/YaGraphCon | spartan3e/src/YaGraphCon.vhd | 1 | 14,538 | -- Copyright (c) 2009 Frank Buss ([email protected])
-- See license.txt for license
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_bit.all;
use work.all;
use work.YaGraphConPackage.all;
entity YaGraphCon is
generic(
ADDRESS_WIDTH: natural;
BIT_DEPTH: natural
);
port(
-- main clock
clock: in std_logic;
-- microcontroller interface
spiChipSelect: in std_logic;
spiData: in std_logic;
spiClock: in std_logic;
busy: out std_logic;
vsync: out std_logic;
-- graphics output
pixel: out unsigned(BIT_DEPTH-1 downto 0);
vgaHsync: out std_logic;
vgaVsync: out std_logic
);
end entity YaGraphCon;
architecture rtl of YaGraphCon is
constant PITCH_WIDTH: natural := min(16, ADDRESS_WIDTH);
-- 1st RAM port for read-only access
signal framebufferReadAddress1: unsigned(ADDRESS_WIDTH-1 downto 0);
signal framebufferQ1: unsigned(BIT_DEPTH-1 downto 0);
-- 2nd RAM port for read-only access
signal framebufferReadAddress2: unsigned(ADDRESS_WIDTH-1 downto 0);
signal framebufferQ2: unsigned(BIT_DEPTH-1 downto 0);
-- 3rd RAM port for write access
signal framebufferWriteAddress: unsigned(ADDRESS_WIDTH-1 downto 0);
signal framebufferData: unsigned(BIT_DEPTH-1 downto 0);
signal framebufferWriteEnable: std_logic;
-- OutputGenerator signals
signal framebufferStart: unsigned(ADDRESS_WIDTH-1 downto 0) := (others => '0');
signal framebufferPitch: unsigned(PITCH_WIDTH-1 downto 0) := x"0280";
-- GraphicsAccelerator signals
signal reset: std_logic := '0';
signal writeStart: unsigned(ADDRESS_WIDTH-1 downto 0);
signal writeSize: unsigned(ADDRESS_WIDTH-1 downto 0);
signal srcStart: unsigned(ADDRESS_WIDTH-1 downto 0);
signal srcPitch: unsigned(PITCH_WIDTH-1 downto 0);
signal dstStart: unsigned(ADDRESS_WIDTH-1 downto 0);
signal dstPitch: unsigned(PITCH_WIDTH-1 downto 0);
signal color: unsigned(BIT_DEPTH-1 downto 0);
signal lineX0: unsigned(15 downto 0);
signal lineY0: unsigned(15 downto 0);
signal blitWidth: unsigned(15 downto 0);
signal blitHeight: unsigned(15 downto 0);
signal blitTransparent: std_logic;
signal srcX0: unsigned(15 downto 0);
signal srcY0: unsigned(15 downto 0);
signal srcX1: unsigned(15 downto 0);
signal dstX0: unsigned(15 downto 0);
signal dstY0: unsigned(15 downto 0);
signal dstX1: unsigned(15 downto 0);
signal dstY1: unsigned(15 downto 0);
signal command: unsigned(7 downto 0);
signal start: std_logic;
signal acceleratorBusy: std_logic;
signal acceleratorWriteAddress: unsigned(ADDRESS_WIDTH-1 downto 0);
signal acceleratorData: unsigned(BIT_DEPTH-1 downto 0);
signal acceleratorWriteEnable: std_logic;
-- SPI signals
signal spiChipSelectLatch: std_logic;
signal spiChipSelectVector: std_logic_vector(1 downto 0);
signal spiDataLatch: std_logic;
signal spiClockLatch: std_logic;
signal spiClockVector: std_logic_vector(1 downto 0);
signal receivedWord: unsigned(max(ADDRESS_WIDTH-1, 15) downto 0);
signal receivedBitsCount: natural range 0 to 24 := 0;
-- statemachine
type commandParserStateType is (
WAIT_FOR_COMMAND,
WAIT_FRAMEBUFFER_START_ADDRESS,
WAIT_FRAMEBUFFER_PITCH_OFFSET,
WAIT_DESTINATION_START_ADDRESS,
WAIT_DESTINATION_PITCH_OFFSET,
WAIT_SOURCE_START_ADDRESS,
WAIT_SOURCE_PITCH_ADDRESS,
WAIT_COLOR,
WAIT_SET_PIXEL_X,
WAIT_SET_PIXEL_Y,
WAIT_MOVE_TO_X,
WAIT_MOVE_TO_Y,
WAIT_LINE_TO_X,
WAIT_LINE_TO_Y,
WAIT_FILL_RECT_X0,
WAIT_FILL_RECT_Y0,
WAIT_FILL_RECT_WIDTH,
WAIT_FILL_RECT_HEIGHT,
WAIT_BLIT_SIZE_WIDTH,
WAIT_BLIT_SIZE_HEIGHT,
WAIT_BLIT_SOURCE_X,
WAIT_BLIT_SOURCE_Y,
WAIT_BLIT_DESTINATION_X,
WAIT_BLIT_DESTINATION_Y,
WAIT_WRITE_FRAMEBUFFER_ADDRESS,
WAIT_WRITE_FRAMEBUFFER_SIZE,
WAIT_WRITE_FRAMEBUFFER_BITS,
WAIT_FOR_COMMAND_END
);
signal commandParserState: commandParserStateType := WAIT_FOR_COMMAND;
begin
Framebuffer_instance: entity Framebuffer
generic map(ADDRESS_WIDTH, BIT_DEPTH)
port map(
clock => clock,
readAddress1 => framebufferReadAddress1,
q1 => framebufferQ1,
readAddress2 => framebufferReadAddress2,
q2 => framebufferQ2,
writeAddress => framebufferWriteAddress,
data => framebufferData,
writeEnable => framebufferWriteEnable
);
OutputGenerator_instance: entity OutputGenerator
generic map(ADDRESS_WIDTH, BIT_DEPTH, PITCH_WIDTH)
port map(
clock => clock,
pixel => pixel,
vgaHsync => vgaHsync,
vgaVsync => vgaVsync,
vsync => vsync,
readAddress => framebufferReadAddress1,
q => framebufferQ1,
framebufferStart => framebufferStart,
framebufferPitch => framebufferPitch
);
GraphicsAccelerator_instance: entity GraphicsAccelerator
generic map(ADDRESS_WIDTH, BIT_DEPTH, PITCH_WIDTH)
port map(
clock => clock,
reset => reset,
srcStart => srcStart,
srcPitch => srcPitch,
dstStart => dstStart,
dstPitch => dstPitch,
color => color,
srcX0 => srcX0,
srcY0 => srcY0,
srcX1 => srcX1,
dstX0 => dstX0,
dstY0 => dstY0,
dstX1 => dstX1,
dstY1 => dstY1,
blitTransparent => blitTransparent,
command => command,
start => start,
busy => acceleratorBusy,
readAddress => framebufferReadAddress2,
writeAddress => acceleratorWriteAddress,
data => acceleratorData,
q => framebufferQ2,
writeEnable => acceleratorWriteEnable
);
process(clock)
begin
if rising_edge(clock) then
reset <= '0';
start <= '0';
framebufferWriteAddress <= acceleratorWriteAddress;
framebufferData <= acceleratorData;
framebufferWriteEnable <= acceleratorWriteEnable;
spiChipSelectLatch <= spiChipSelect;
spiChipSelectVector <= spiChipSelectVector(0) & spiChipSelectLatch;
spiDataLatch <= spiData;
spiClockLatch <= spiClock;
spiClockVector <= spiClockVector(0) & spiClockLatch;
if spiChipSelectLatch = '0' then
if spiClockVector = "01" then
receivedWord <= receivedWord(receivedWord'high-1 downto 0) & spiDataLatch;
receivedBitsCount <= receivedBitsCount + 1;
end if;
busy <= acceleratorBusy;
end if;
if spiChipSelectVector = "01" then
receivedBitsCount <= 0;
commandParserState <= WAIT_FOR_COMMAND;
busy <= '1';
end if;
case commandParserState is
when WAIT_FOR_COMMAND =>
if receivedBitsCount = 8 then
command <= receivedWord(7 downto 0);
case receivedWord(7 downto 0) is
when RESET_COMMAND =>
reset <= '1';
srcStart <= (others => '0');
srcPitch <= (others => '0');
dstStart <= (others => '0');
dstPitch <= (others => '0');
color <= (others => '0');
srcX0 <= (others => '0');
srcY0 <= (others => '0');
srcX1 <= (others => '0');
dstX0 <= (others => '0');
dstY0 <= (others => '0');
dstX1 <= (others => '0');
dstY1 <= (others => '0');
blitTransparent <= '0';
commandParserState <= WAIT_FOR_COMMAND_END;
when SET_FRAMEBUFFER_START =>
commandParserState <= WAIT_FRAMEBUFFER_START_ADDRESS;
when SET_FRAMEBUFFER_PITCH =>
commandParserState <= WAIT_FRAMEBUFFER_PITCH_OFFSET;
when SET_DESTINATION_START =>
commandParserState <= WAIT_DESTINATION_START_ADDRESS;
when SET_DESTINATION_PITCH =>
commandParserState <= WAIT_DESTINATION_PITCH_OFFSET;
when SET_SOURCE_START =>
commandParserState <= WAIT_SOURCE_START_ADDRESS;
when SET_SOURCE_PITCH =>
commandParserState <= WAIT_SOURCE_PITCH_ADDRESS;
when SET_COLOR =>
commandParserState <= WAIT_COLOR;
when SET_PIXEL =>
commandParserState <= WAIT_SET_PIXEL_X;
when MOVE_TO =>
commandParserState <= WAIT_MOVE_TO_X;
when LINE_TO =>
commandParserState <= WAIT_LINE_TO_X;
when FILL_RECT =>
commandParserState <= WAIT_FILL_RECT_X0;
when BLIT_SIZE =>
commandParserState <= WAIT_BLIT_SIZE_WIDTH;
when BLIT_COMMAND =>
blitTransparent <= '0';
commandParserState <= WAIT_BLIT_SOURCE_X;
when BLIT_TRANSPARENT =>
blitTransparent <= '1';
commandParserState <= WAIT_BLIT_SOURCE_X;
when WRITE_FRAMEBUFFER =>
commandParserState <= WAIT_WRITE_FRAMEBUFFER_ADDRESS;
when others =>
end case;
receivedBitsCount <= 0;
end if;
when WAIT_FRAMEBUFFER_START_ADDRESS =>
if receivedBitsCount = 24 then
framebufferStart <= receivedWord(ADDRESS_WIDTH-1 downto 0);
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
when WAIT_FRAMEBUFFER_PITCH_OFFSET =>
if receivedBitsCount = 16 then
framebufferPitch <= receivedWord(PITCH_WIDTH-1 downto 0);
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
when WAIT_DESTINATION_START_ADDRESS =>
if receivedBitsCount = 24 then
dstStart <= receivedWord(ADDRESS_WIDTH-1 downto 0);
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
when WAIT_DESTINATION_PITCH_OFFSET =>
if receivedBitsCount = 16 then
dstPitch <= receivedWord(PITCH_WIDTH-1 downto 0);
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
when WAIT_SOURCE_START_ADDRESS =>
if receivedBitsCount = 24 then
srcStart <= receivedWord(ADDRESS_WIDTH-1 downto 0);
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
when WAIT_SOURCE_PITCH_ADDRESS =>
if receivedBitsCount = 16 then
srcPitch <= receivedWord(PITCH_WIDTH-1 downto 0);
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
when WAIT_COLOR =>
if receivedBitsCount = BIT_DEPTH then
color <= receivedWord(BIT_DEPTH-1 downto 0);
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
when WAIT_SET_PIXEL_X =>
if receivedBitsCount = 16 then
dstX0 <= receivedWord(15 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_SET_PIXEL_Y;
end if;
when WAIT_SET_PIXEL_Y =>
if receivedBitsCount = 16 then
dstY0 <= receivedWord(15 downto 0);
start <= '1';
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
when WAIT_MOVE_TO_X =>
if receivedBitsCount = 16 then
lineX0 <= receivedWord(15 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_MOVE_TO_Y;
end if;
when WAIT_MOVE_TO_Y =>
if receivedBitsCount = 16 then
lineY0 <= receivedWord(15 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
when WAIT_LINE_TO_X =>
if receivedBitsCount = 16 then
dstX0 <= receivedWord(15 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_LINE_TO_Y;
end if;
when WAIT_LINE_TO_Y =>
if receivedBitsCount = 16 then
dstY0 <= receivedWord(15 downto 0);
dstX1 <= lineX0;
dstY1 <= lineY0;
lineX0 <= dstX0;
lineY0 <= receivedWord(15 downto 0);
start <= '1';
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
when WAIT_FILL_RECT_X0 =>
if receivedBitsCount = 16 then
dstX0 <= receivedWord(15 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_FILL_RECT_Y0;
end if;
when WAIT_FILL_RECT_Y0 =>
if receivedBitsCount = 16 then
dstY0 <= receivedWord(15 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_FILL_RECT_WIDTH;
end if;
when WAIT_FILL_RECT_WIDTH =>
if receivedBitsCount = 16 then
if receivedWord(15 downto 0) = 0 then
commandParserState <= WAIT_FOR_COMMAND_END;
else
dstX1 <= receivedWord(15 downto 0) + dstX0 - 1;
receivedBitsCount <= 0;
commandParserState <= WAIT_FILL_RECT_HEIGHT;
end if;
end if;
when WAIT_FILL_RECT_HEIGHT =>
if receivedBitsCount = 16 then
if receivedWord(15 downto 0) = 0 then
commandParserState <= WAIT_FOR_COMMAND_END;
else
dstY1 <= receivedWord(15 downto 0) + dstY0 - 1;
start <= '1';
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
end if;
when WAIT_BLIT_SIZE_WIDTH =>
if receivedBitsCount = 16 then
blitWidth <= receivedWord(15 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_BLIT_SIZE_HEIGHT;
end if;
when WAIT_BLIT_SIZE_HEIGHT =>
if receivedBitsCount = 16 then
blitHeight <= receivedWord(15 downto 0);
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
when WAIT_BLIT_SOURCE_X =>
if receivedBitsCount = 16 then
srcX0 <= receivedWord(15 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_BLIT_SOURCE_Y;
end if;
when WAIT_BLIT_SOURCE_Y =>
if receivedBitsCount = 16 then
srcY0 <= receivedWord(15 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_BLIT_DESTINATION_X;
end if;
when WAIT_BLIT_DESTINATION_X =>
if receivedBitsCount = 16 then
dstX0 <= receivedWord(15 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_BLIT_DESTINATION_Y;
end if;
when WAIT_BLIT_DESTINATION_Y =>
if receivedBitsCount = 16 then
if blitWidth = 0 or blitHeight = 0 then
commandParserState <= WAIT_FOR_COMMAND_END;
else
dstY0 <= receivedWord(15 downto 0);
srcX1 <= srcX0 + blitWidth - 1;
dstX1 <= dstX0 + blitWidth - 1;
dstY1 <= receivedWord(15 downto 0) + blitHeight - 1;
start <= '1';
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
end if;
when WAIT_WRITE_FRAMEBUFFER_ADDRESS =>
if receivedBitsCount = 24 then
writeStart <= receivedWord(ADDRESS_WIDTH-1 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_WRITE_FRAMEBUFFER_SIZE;
end if;
when WAIT_WRITE_FRAMEBUFFER_SIZE =>
if receivedBitsCount = 24 then
writeSize <= receivedWord(ADDRESS_WIDTH-1 downto 0);
receivedBitsCount <= 0;
commandParserState <= WAIT_WRITE_FRAMEBUFFER_BITS;
end if;
when WAIT_WRITE_FRAMEBUFFER_BITS =>
if receivedBitsCount = BIT_DEPTH then
if writeSize > 0 then
framebufferWriteAddress <= writeStart;
framebufferData <= receivedWord(BIT_DEPTH - 1 downto 0);
framebufferWriteEnable <= '1';
writeStart <= writeStart + 1;
writeSize <= writeSize - 1;
else
commandParserState <= WAIT_FOR_COMMAND_END;
end if;
receivedBitsCount <= 0;
end if;
when WAIT_FOR_COMMAND_END => null;
when others =>
commandParserState <= WAIT_FOR_COMMAND;
end case;
end if;
end process;
end architecture rtl;
| mit | 918fd5d1f6ff1a83c7885a23c9d1466c | 0.66591 | 3.343606 | false | false | false | false |
pkerling/ethernet_mac | xilinx/single_signal_synchronizer_spartan6.vhd | 1 | 1,812 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Two-FF synchronizer that uses constraints to prohibit XST from
-- optimizing it away
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
architecture spartan6 of single_signal_synchronizer is
signal signal_tmp : std_ulogic := '0';
-- Constrain registers
attribute ASYNC_REG : string;
attribute ASYNC_REG of FDPE_tmp_inst : label is "TRUE";
attribute ASYNC_REG of FDPE_out_inst : label is "TRUE";
-- Do not allow conversion into a shift register
attribute shreg_extract : string;
attribute shreg_extract of signal_tmp : signal is "no";
-- Do not allow register balancing
attribute register_balancing : string;
attribute register_balancing of signal_tmp : signal is "no";
--attribute register_balancing of signal_i : signal is "no";
--attribute register_balancing of signal_o : signal is "no";
begin
FDPE_tmp_inst : FDPE
generic map(
INIT => '1') -- Initial value of register ('0' or '1')
port map(
Q => signal_tmp, -- Data output
C => clock_target_i, -- Clock input
CE => '1', -- Clock enable input
PRE => preset_i, -- Asynchronous preset input
D => signal_i -- Data input
);
FDPE_out_inst : FDPE
generic map(
INIT => '1') -- Initial value of register ('0' or '1')
port map(
Q => signal_o, -- Data output
C => clock_target_i, -- Clock input
CE => '1', -- Clock enable input
PRE => preset_i, -- Asynchronous preset input
D => signal_tmp -- Data input
);
end architecture; | bsd-3-clause | 9a7e29974d18f5b65ad71c4644a49da9 | 0.63245 | 3.675456 | false | false | false | false |
Dragonturtle/SHERPA | HDL/SPI/spi_master.vhd | 1 | 41,762 | -----------------------------------------------------------------------------------------------------------------------
-- Author: Jonny Doin, [email protected], [email protected]
--
-- Create Date: 12:18:12 04/25/2011
-- Module Name: SPI_MASTER - RTL
-- Project Name: SPI MASTER / SLAVE INTERFACE
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is the SPI master interface, implemented in one single entity.
-- All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
-- 'sclk_i' clock.
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling
-- ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
--
-- SPI CLOCK GENERATION
-- ====================
--
-- The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference
-- clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the
-- SPI_2X clock, which is 2x the desired SCK frequency.
-- All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
-- at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
-- by combinatorial clock dividers outputs.
-- The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
--
-- PARALLEL WRITE INTERFACE
-- ========================
-- The parallel interface has an input port 'di_i' and an output port 'do_o'.
-- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
-- that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the
-- next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
-- For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
-- if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
-- enters idle state and deasserts SSEL.
-- When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering
-- idle state, if a previously loaded data has already been transferred.
--
-- PARALLEL WRITE SEQUENCE
-- =======================
-- __ __ __ __ __ __ __
-- pclk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
-- ___________
-- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'pclk_i'
-- ______________ ___________________________...
-- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
-- _______
-- wren_i __________________________/ \_______... -- user strobes 'wren_i' for one cycle of 'pclk_i'
--
--
-- PARALLEL READ INTERFACE
-- =======================
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
-- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
-- The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
-- When the interface is idle, data at the 'do_o' port holds the last word received.
--
-- PARALLEL READ SEQUENCE
-- ======================
-- ______ ______ ______ ______
-- spi_clk bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- internal spi 2x base clock
-- _ __ __ __ __ __ __ __ __
-- pclk_i \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock (may be async to sclk_i)
-- _____________ _____________________________________... -- 1) rx data is transferred to 'do_buffer_reg'
-- do_o ___old_data__X__________new_data___________________... -- after last rx bit, at rising 'spi_clk'.
-- ____________
-- do_valid_o ____________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
-- -- on the 3rd 'pclk_i' rising edge.
--
--
-- The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
-- but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
-- of the interface, for full duplex operation.
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
--
-- Author(s): Jonny Doin, [email protected], [email protected]
--
-- Copyright (C) 2011 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/04/28 v0.01.0010 [JD] shifter implemented as a sequential process. timing problems and async issues in synthesis.
-- 2011/05/01 v0.01.0030 [JD] changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
-- 2011/05/05 v0.01.0034 [JD] added an internal buffer register for rx_data, to allow greater liberty in data load/store.
-- 2011/05/08 v0.10.0038 [JD] increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
-- logic, based on generics, and do_valid_o signal.
-- 2011/05/13 v0.20.0045 [JD] streamlined signal names, added PREFETCH parameter, added assertions.
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
-- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
-- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] streamlined wr_ack for all cases and eliminated unnecessary register resets.
-- 2011/06/14 v0.97.0083 [JD] (bug CPHA effect) : redesigned SCK output circuit.
-- (minor bug) : removed fsm registers from (not rst_i) chip enable.
-- 2011/06/15 v0.97.0086 [JD] removed master MISO input register, to relax MISO data setup time (to get higher speed).
-- 2011/07/09 v1.00.0095 [JD] changed all clocking scheme to use a single high-speed clock with clock enables to control lower
-- frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
-- 2011/07/17 v1.11.0080 [JD] BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
-- 2011/08/04 v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
-- integrated to your circuit.
--================================================================================================================
entity spi_master is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 5); -- for a 100MHz sclk_i, yields a 10MHz SCK
Port (
sclk_i : in std_logic := 'X'; -- high-speed serial interface system clock
pclk_i : in std_logic := 'X'; -- high-speed parallel interface system clock
rst_i : in std_logic := 'X'; -- reset core
---- serial interface ----
spi_ssel_o : out std_logic; -- spi bus slave select line
spi_sck_o : out std_logic; -- spi bus sck
spi_mosi_o : out std_logic; -- spi bus mosi output
spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- parallel interface ----
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
do_o : out std_logic_vector (N-1 downto 0) -- parallel output (clocked on rising spi_clk after last bit)
);
end spi_master;
--================================================================================================================
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture rtl of spi_master is
-- core clocks, generated from 'sclk_i': initialized at GSR to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
-- spi bus clock, generated from the CPOL selected core clock polarity
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
signal spi_clk : std_logic := '0'; -- spi bus output clock
signal spi_clk_reg : std_logic; -- output pipeline delay for spi sck (do NOT global initialize)
-- core fsm clock enables
signal fsm_ce : std_logic := '1'; -- fsm clock enable
signal sck_ena_ce : std_logic := '1'; -- SCK clock enable
signal samp_ce : std_logic := '1'; -- data sampling clock enable
--
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
-- especially for the Spartan-6 and newer CLB architectures, where a async reset can
-- reduce the usability of the slice registers, due to the need to share the control
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
-- By using GSR for the initialization, and reducing async RESET local init to the bare
-- essential, the model achieves better LUT/FF packing and CLB usability.
--
-- internal state signals for register and combinatorial stages
signal state_next : natural range N+1 downto 0 := 0;
signal state_reg : natural range N+1 downto 0 := 0;
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- input bit sampled buffer
signal rx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- internal SSEL enable control signals
signal ssel_ena_next : std_logic := '0';
signal ssel_ena_reg : std_logic := '0';
-- internal SCK enable control signals
signal sck_ena_next : std_logic;
signal sck_ena_reg : std_logic;
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
-- internal input data request signal
signal di_req_next : std_logic := '0';
signal di_req_reg : std_logic := '0';
-- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
signal do_valid_A : std_logic := '0';
signal do_valid_B : std_logic := '0';
signal do_valid_C : std_logic := '0';
signal do_valid_D : std_logic := '0';
signal do_valid_next : std_logic := '0';
signal do_valid_o_reg : std_logic := '0';
-- cross-clock di_req_reg -> di_req_o_reg pipeline
signal di_req_o_A : std_logic := '0';
signal di_req_o_B : std_logic := '0';
signal di_req_o_C : std_logic := '0';
signal di_req_o_D : std_logic := '0';
signal di_req_o_next : std_logic := '1';
signal di_req_o_reg : std_logic := '1';
begin
--=============================================================================================
-- GENERICS CONSTRAINTS CHECKING
--=============================================================================================
-- minimum word width is 8 bits
assert N >= 8
report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
severity FAILURE;
-- minimum prefetch lookahead check
assert PREFETCH >= 1
report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
severity FAILURE;
-- maximum prefetch lookahead check
assert PREFETCH <= N-5
report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
severity FAILURE;
-- SPI_2X_CLK_DIV clock divider value must not be zero
assert SPI_2X_CLK_DIV > 0
report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
severity FAILURE;
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
-- In order to preserve global clocking resources, the core clocking scheme is completely based
-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
-- the spi clock generator and the input sampling clock.
-- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock
-- for the core clocking.
-- The 2 clock phases are generated by separate and synchronous FFs, and should have only
-- differential interconnect delay skew.
-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
-- enables are used to control clocking of all internal synchronous circuitry.
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
-- based on the configuration of CPOL and CPHA.
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
-----------------------------------------------------------------------------------------------
-- generate the 2x spi base clock enable from the serial high-speed input clock
spi_2x_ce_gen_proc: process (sclk_i) is
variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
begin
if sclk_i'event and sclk_i = '1' then
if clk_cnt = SPI_2X_CLK_DIV-1 then
spi_2x_ce <= '1';
clk_cnt := 0;
else
spi_2x_ce <= '0';
clk_cnt := clk_cnt + 1;
end if;
end if;
end process spi_2x_ce_gen_proc;
-----------------------------------------------------------------------------------------------
-- generate the core antiphase clocks and clock enables from the 2x base CE.
core_clock_gen_proc : process (sclk_i) is
begin
if sclk_i'event and sclk_i = '1' then
if spi_2x_ce = '1' then
-- generate the 2 antiphase core clocks
core_clk <= core_n_clk;
core_n_clk <= not core_n_clk;
-- generate the 2 phase core clock enables
core_ce <= core_n_clk;
core_n_ce <= not core_n_clk;
else
core_ce <= '0';
core_n_ce <= '0';
end if;
end if;
end process core_clock_gen_proc;
--=============================================================================================
-- GENERATE BLOCKS
--=============================================================================================
-- spi clk generator: generate spi_clk from core_clk depending on CPOL
spi_sck_cpol_0_proc: if CPOL = '0' generate
begin
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW
end generate;
spi_sck_cpol_1_proc: if CPOL = '1' generate
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
end generate;
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
samp_ce_cpha_0_proc: if CPHA = '0' generate
begin
samp_ce <= core_ce;
end generate;
samp_ce_cpha_1_proc: if CPHA = '1' generate
begin
samp_ce <= core_n_ce;
end generate;
-----------------------------------------------------------------------------------------------
-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
fsm_ce_cpha_0_proc: if CPHA = '0' generate
begin
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
end generate;
fsm_ce_cpha_1_proc: if CPHA = '1' generate
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate;
-----------------------------------------------------------------------------------------------
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
-- REGISTERED INPUTS
--=============================================================================================
-- rx bit flop: capture rx bit after SAMPLE edge of sck
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if sclk_i'event and sclk_i = '1' then
if samp_ce = '1' then
rx_bit_reg <= spi_miso_i;
end if;
end if;
end process rx_bit_proc;
--=============================================================================================
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC
--=============================================================================================
-- do_valid_o and di_req_o strobe output logic
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
-- fixed-length delayed pulse for the output flags, at the parallel clock domain
out_transfer_proc : process ( pclk_i, do_transfer_reg, di_req_reg,
do_valid_A, do_valid_B, do_valid_D,
di_req_o_A, di_req_o_B, di_req_o_D ) is
begin
if pclk_i'event and pclk_i = '1' then -- clock at parallel port clock
-- do_transfer_reg -> do_valid_o_reg
do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long
do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs
do_valid_C <= do_valid_B;
do_valid_D <= do_valid_C;
do_valid_o_reg <= do_valid_next; -- registered output pulse
--------------------------------
-- di_req_reg -> di_req_o_reg
di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long
di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs
di_req_o_C <= di_req_o_B;
di_req_o_D <= di_req_o_C;
di_req_o_reg <= di_req_o_next; -- registered output pulse
end if;
-- generate a 2-clocks pulse at the 3rd clock cycle
do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
end process out_transfer_proc;
-- parallel load input registers: data register and write enable
in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is
begin
-- registered data input, input register with clock enable
if pclk_i'event and pclk_i = '1' then
if wren_i = '1' then
di_reg <= di_i; -- parallel data input buffer register
end if;
end if;
-- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
if pclk_i'event and pclk_i = '1' then
if wren_i = '1' then -- wren_i is the sync preset for wren
wren <= '1';
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren
wren <= '0';
end if;
end if;
end process in_transfer_proc;
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
core_reg_proc : process (sclk_i) is
begin
-- FF registers clocked on rising edge and cleared on sync rst_i
if sclk_i'event and sclk_i = '1' then
if rst_i = '1' then -- sync reset
state_reg <= 0; -- only provide local reset for the state machine
elsif fsm_ce = '1' then -- fsm_ce is clock enable for the fsm
state_reg <= state_next; -- state register
end if;
end if;
-- FF registers clocked synchronous to the fsm state
if sclk_i'event and sclk_i = '1' then
if fsm_ce = '1' then
sh_reg <= sh_next; -- shift register
ssel_ena_reg <= ssel_ena_next; -- spi select enable
do_buffer_reg <= do_buffer_next; -- registered output data buffer
do_transfer_reg <= do_transfer_next; -- output data transferred to buffer
di_req_reg <= di_req_next; -- input data request
wr_ack_reg <= wr_ack_next; -- write acknowledge for data load synchronization
end if;
end if;
-- FF registers clocked one-half cycle earlier than the fsm state
if sclk_i'event and sclk_i = '1' then
if sck_ena_ce = '1' then
sck_ena_reg <= sck_ena_next; -- spi clock enable: look ahead logic
end if;
end if;
end process core_reg_proc;
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is
begin
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches)
ssel_ena_next <= ssel_ena_reg; -- controls the slave select line
sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line
do_buffer_next <= do_buffer_reg; -- output data buffer
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write acknowledge
di_req_next <= di_req_reg; -- prefetch data request
spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference
state_next <= state_reg; -- next state
case state_reg is
when (N+1) => -- this state is to enable SSEL before SCK
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N) => -- deassert 'di_rdy' and stretch do_valid
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o' signal
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if new data is written
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
do_transfer_next <= '1'; -- signal transfer to do_buffer
if wren = '1' then -- load tx register if valid data present at di_i
state_next <= N; -- next state is top bit of new data
sh_next <= di_reg; -- load parallel data from di_reg into shifter
sck_ena_next <= '1'; -- SCK enabled
wr_ack_next <= '1'; -- acknowledge data in transfer
else
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
end if;
when 0 => -- idle state: start and end of transmission
di_req_next <= '1'; -- will request data if shifter empty
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
if wren = '1' then -- load tx register if valid data present at di_i
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
ssel_ena_next <= '1'; -- enable interface SSEL
state_next <= N+1; -- start from idle: let one cycle for SSEL settling
sh_next <= di_reg; -- load bits from di_reg into shifter
wr_ack_next <= '1'; -- acknowledge data in transfer
else
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= 0; -- when idle, keep this state
end if;
when others =>
state_next <= 0; -- state 0 is safe state
end case;
end process core_combi_proc;
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
spi_ssel_o_proc: spi_ssel_o <= not ssel_ena_reg; -- active-low slave select line
do_o_proc: do_o <= do_buffer_reg; -- parallel data out
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- data out valid
di_req_o_proc: di_req_o <= di_req_o_reg; -- input data request for next cycle
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- write acknowledge
-----------------------------------------------------------------------------------------------
-- SCK out logic: pipeline phase compensation for the SCK line
-----------------------------------------------------------------------------------------------
-- This is a MUX with an output register.
-- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore
-- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency.
spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is
begin
if sclk_i'event and sclk_i = '1' then
if sck_ena_reg = '1' then
spi_clk_reg <= spi_clk; -- copy the selected clock polarity
else
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
end if;
end if;
spi_sck_o <= spi_clk_reg; -- connect register to output
end process spi_sck_o_gen_proc;
end architecture rtl;
| gpl-3.0 | 6fbce01fc9d09675ebe956115d627243 | 0.485585 | 4.674502 | false | false | false | false |
pkerling/ethernet_mac | xilinx/tx_fifo.vhd | 1 | 2,162 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Combination of tx_fifo_adapter with a Xilinx core generator FIFO
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
entity tx_fifo is
port(
clock_i : in std_ulogic;
data_i : in t_ethernet_data;
wr_en_i : in std_ulogic;
full_o : out std_ulogic;
-- Interface to framing layer
mac_tx_reset_i : in std_ulogic;
mac_tx_clock_i : in std_ulogic;
mac_tx_enable_o : out std_ulogic;
mac_tx_data_o : out t_ethernet_data;
mac_tx_byte_sent_i : in std_ulogic;
mac_tx_busy_i : in std_ulogic
);
end entity;
architecture rtl of tx_fifo is
signal rd_en : std_ulogic := '0';
signal data_out : std_logic_vector(t_ethernet_data'range);
signal empty : std_ulogic := '1';
-- Intermediate signal needed for conversion between std_logic_vector and std_ulogic_vector
signal read_count_lv : std_logic_vector(11 downto 0);
signal read_count : unsigned(11 downto 0);
begin
-- Convert type
read_count <= unsigned(read_count_lv);
tx_data_fifo_inst : entity work.ethernet_mac_tx_fifo_xilinx
port map(
rst => mac_tx_reset_i,
wr_clk => clock_i,
rd_clk => mac_tx_clock_i,
din => std_logic_vector(data_i),
wr_en => wr_en_i,
rd_en => rd_en,
dout => data_out,
full => full_o,
empty => empty,
rd_data_count => read_count_lv
);
tx_fifo_adapter_inst : entity work.tx_fifo_adapter
port map(
mac_tx_reset_i => mac_tx_reset_i,
mac_tx_clock_i => mac_tx_clock_i,
mac_tx_enable_o => mac_tx_enable_o,
mac_tx_data_o => mac_tx_data_o,
mac_tx_byte_sent_i => mac_tx_byte_sent_i,
mac_tx_busy_i => mac_tx_busy_i,
rd_en_o => rd_en,
data_i => std_ulogic_vector(data_out),
empty_i => empty,
read_count_i => read_count
);
end architecture;
| bsd-3-clause | 96ab88e085c9a9d5ed08909be2c0376c | 0.592969 | 2.856011 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_test/niosii/synthesis/niosii.vhd | 1 | 62,188 | -- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- pio_0_external_connection.export
reset_reset_n : in std_logic := '0'; -- reset.reset_n
sdram_addr : out std_logic_vector(12 downto 0); -- sdram.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk_clk : out std_logic -- sdram_clk.clk
);
end entity niosii;
architecture rtl of niosii is
component niosii_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosii_jtag_uart_0;
component niosii_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(26 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(26 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component niosii_nios2_gen2_0;
component niosii_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosii_onchip_memory2_0;
component niosii_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosii_pio_0;
component niosii_sdram_controller_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address
az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n
az_cs : in std_logic := 'X'; -- chipselect
az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
az_rd_n : in std_logic := 'X'; -- read_n
az_wr_n : in std_logic := 'X'; -- write_n
za_data : out std_logic_vector(15 downto 0); -- readdata
za_valid : out std_logic; -- readdatavalid
za_waitrequest : out std_logic; -- waitrequest
zs_addr : out std_logic_vector(12 downto 0); -- export
zs_ba : out std_logic_vector(1 downto 0); -- export
zs_cas_n : out std_logic; -- export
zs_cke : out std_logic; -- export
zs_cs_n : out std_logic; -- export
zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
zs_dqm : out std_logic_vector(1 downto 0); -- export
zs_ras_n : out std_logic; -- export
zs_we_n : out std_logic -- export
);
end component niosii_sdram_controller_0;
component niosii_sys_sdram_pll_0 is
port (
ref_clk_clk : in std_logic := 'X'; -- clk
ref_reset_reset : in std_logic := 'X'; -- reset
sys_clk_clk : out std_logic; -- clk
sdram_clk_clk : out std_logic; -- clk
reset_source_reset : out std_logic -- reset
);
end component niosii_sys_sdram_pll_0;
component niosii_mm_interconnect_0 is
port (
clk_0_clk_clk : in std_logic := 'X'; -- clk
sys_sdram_pll_0_sys_clk_clk : in std_logic := 'X'; -- clk
jtag_uart_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
jtag_uart_0_avalon_jtag_slave_address : out std_logic_vector(0 downto 0); -- address
jtag_uart_0_avalon_jtag_slave_write : out std_logic; -- write
jtag_uart_0_avalon_jtag_slave_read : out std_logic; -- read
jtag_uart_0_avalon_jtag_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_uart_0_avalon_jtag_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(13 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
sdram_controller_0_s1_address : out std_logic_vector(23 downto 0); -- address
sdram_controller_0_s1_write : out std_logic; -- write
sdram_controller_0_s1_read : out std_logic; -- read
sdram_controller_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
sdram_controller_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
sdram_controller_0_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable
sdram_controller_0_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid
sdram_controller_0_s1_waitrequest : in std_logic := 'X'; -- waitrequest
sdram_controller_0_s1_chipselect : out std_logic -- chipselect
);
end component niosii_mm_interconnect_0;
component niosii_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosii_irq_mapper;
component altera_irq_clock_crosser is
generic (
IRQ_WIDTH : integer := 1
);
port (
receiver_clk : in std_logic := 'X'; -- clk
sender_clk : in std_logic := 'X'; -- clk
receiver_reset : in std_logic := 'X'; -- reset
sender_reset : in std_logic := 'X'; -- reset
receiver_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
sender_irq : out std_logic_vector(0 downto 0) -- irq
);
end component altera_irq_clock_crosser;
component niosii_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller;
component niosii_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller_001;
signal sys_sdram_pll_0_sys_clk_clk : std_logic; -- sys_sdram_pll_0:sys_clk_clk -> [irq_mapper:clk, irq_synchronizer:sender_clk, mm_interconnect_0:sys_sdram_pll_0_sys_clk_clk, nios2_gen2_0:clk, onchip_memory2_0:clk, pio_0:clk, rst_controller_001:clk, sdram_controller_0:clk]
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(13 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_sdram_controller_0_s1_chipselect : std_logic; -- mm_interconnect_0:sdram_controller_0_s1_chipselect -> sdram_controller_0:az_cs
signal mm_interconnect_0_sdram_controller_0_s1_readdata : std_logic_vector(15 downto 0); -- sdram_controller_0:za_data -> mm_interconnect_0:sdram_controller_0_s1_readdata
signal mm_interconnect_0_sdram_controller_0_s1_waitrequest : std_logic; -- sdram_controller_0:za_waitrequest -> mm_interconnect_0:sdram_controller_0_s1_waitrequest
signal mm_interconnect_0_sdram_controller_0_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:sdram_controller_0_s1_address -> sdram_controller_0:az_addr
signal mm_interconnect_0_sdram_controller_0_s1_read : std_logic; -- mm_interconnect_0:sdram_controller_0_s1_read -> mm_interconnect_0_sdram_controller_0_s1_read:in
signal mm_interconnect_0_sdram_controller_0_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:sdram_controller_0_s1_byteenable -> mm_interconnect_0_sdram_controller_0_s1_byteenable:in
signal mm_interconnect_0_sdram_controller_0_s1_readdatavalid : std_logic; -- sdram_controller_0:za_valid -> mm_interconnect_0:sdram_controller_0_s1_readdatavalid
signal mm_interconnect_0_sdram_controller_0_s1_write : std_logic; -- mm_interconnect_0:sdram_controller_0_s1_write -> mm_interconnect_0_sdram_controller_0_s1_write:in
signal mm_interconnect_0_sdram_controller_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sdram_controller_0_s1_writedata -> sdram_controller_0:az_data
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal irq_mapper_receiver0_irq : std_logic; -- irq_synchronizer:sender_irq -> irq_mapper:receiver0_irq
signal irq_synchronizer_receiver_irq : std_logic_vector(0 downto 0); -- jtag_uart_0:av_irq -> irq_synchronizer:receiver_irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [irq_synchronizer:receiver_reset, mm_interconnect_0:jtag_uart_0_reset_reset_bridge_in_reset_reset, rst_controller_reset_out_reset:in, sys_sdram_pll_0:ref_reset_reset]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [irq_mapper:reset, irq_synchronizer:sender_reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:inv -> jtag_uart_0:av_read_n
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:inv -> jtag_uart_0:av_write_n
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_sdram_controller_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_sdram_controller_0_s1_read:inv -> sdram_controller_0:az_rd_n
signal mm_interconnect_0_sdram_controller_0_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_sdram_controller_0_s1_byteenable:inv -> sdram_controller_0:az_be_n
signal mm_interconnect_0_sdram_controller_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_sdram_controller_0_s1_write:inv -> sdram_controller_0:az_wr_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> jtag_uart_0:rst_n
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [nios2_gen2_0:reset_n, pio_0:reset_n, sdram_controller_0:reset_n]
begin
jtag_uart_0 : component niosii_jtag_uart_0
port map (
clk => clk_clk, -- clk.clk
rst_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- avalon_jtag_slave.chipselect
av_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address(0), -- .address
av_read_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv, -- .read_n
av_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
av_write_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv, -- .write_n
av_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
av_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
av_irq => irq_synchronizer_receiver_irq(0) -- irq.irq
);
nios2_gen2_0 : component niosii_nios2_gen2_0
port map (
clk => sys_sdram_pll_0_sys_clk_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosii_onchip_memory2_0
port map (
clk => sys_sdram_pll_0_sys_clk_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_001_reset_out_reset, -- reset1.reset
reset_req => rst_controller_001_reset_out_reset_req -- .reset_req
);
pio_0 : component niosii_pio_0
port map (
clk => sys_sdram_pll_0_sys_clk_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
out_port => pio_0_external_connection_export -- external_connection.export
);
sdram_controller_0 : component niosii_sdram_controller_0
port map (
clk => sys_sdram_pll_0_sys_clk_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
az_addr => mm_interconnect_0_sdram_controller_0_s1_address, -- s1.address
az_be_n => mm_interconnect_0_sdram_controller_0_s1_byteenable_ports_inv, -- .byteenable_n
az_cs => mm_interconnect_0_sdram_controller_0_s1_chipselect, -- .chipselect
az_data => mm_interconnect_0_sdram_controller_0_s1_writedata, -- .writedata
az_rd_n => mm_interconnect_0_sdram_controller_0_s1_read_ports_inv, -- .read_n
az_wr_n => mm_interconnect_0_sdram_controller_0_s1_write_ports_inv, -- .write_n
za_data => mm_interconnect_0_sdram_controller_0_s1_readdata, -- .readdata
za_valid => mm_interconnect_0_sdram_controller_0_s1_readdatavalid, -- .readdatavalid
za_waitrequest => mm_interconnect_0_sdram_controller_0_s1_waitrequest, -- .waitrequest
zs_addr => sdram_addr, -- wire.export
zs_ba => sdram_ba, -- .export
zs_cas_n => sdram_cas_n, -- .export
zs_cke => sdram_cke, -- .export
zs_cs_n => sdram_cs_n, -- .export
zs_dq => sdram_dq, -- .export
zs_dqm => sdram_dqm, -- .export
zs_ras_n => sdram_ras_n, -- .export
zs_we_n => sdram_we_n -- .export
);
sys_sdram_pll_0 : component niosii_sys_sdram_pll_0
port map (
ref_clk_clk => clk_clk, -- ref_clk.clk
ref_reset_reset => rst_controller_reset_out_reset, -- ref_reset.reset
sys_clk_clk => sys_sdram_pll_0_sys_clk_clk, -- sys_clk.clk
sdram_clk_clk => sdram_clk_clk, -- sdram_clk.clk
reset_source_reset => open -- reset_source.reset
);
mm_interconnect_0 : component niosii_mm_interconnect_0
port map (
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
sys_sdram_pll_0_sys_clk_clk => sys_sdram_pll_0_sys_clk_clk, -- sys_sdram_pll_0_sys_clk.clk
jtag_uart_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- jtag_uart_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address, -- jtag_uart_0_avalon_jtag_slave.address
jtag_uart_0_avalon_jtag_slave_write => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write, -- .write
jtag_uart_0_avalon_jtag_slave_read => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read, -- .read
jtag_uart_0_avalon_jtag_slave_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
sdram_controller_0_s1_address => mm_interconnect_0_sdram_controller_0_s1_address, -- sdram_controller_0_s1.address
sdram_controller_0_s1_write => mm_interconnect_0_sdram_controller_0_s1_write, -- .write
sdram_controller_0_s1_read => mm_interconnect_0_sdram_controller_0_s1_read, -- .read
sdram_controller_0_s1_readdata => mm_interconnect_0_sdram_controller_0_s1_readdata, -- .readdata
sdram_controller_0_s1_writedata => mm_interconnect_0_sdram_controller_0_s1_writedata, -- .writedata
sdram_controller_0_s1_byteenable => mm_interconnect_0_sdram_controller_0_s1_byteenable, -- .byteenable
sdram_controller_0_s1_readdatavalid => mm_interconnect_0_sdram_controller_0_s1_readdatavalid, -- .readdatavalid
sdram_controller_0_s1_waitrequest => mm_interconnect_0_sdram_controller_0_s1_waitrequest, -- .waitrequest
sdram_controller_0_s1_chipselect => mm_interconnect_0_sdram_controller_0_s1_chipselect -- .chipselect
);
irq_mapper : component niosii_irq_mapper
port map (
clk => sys_sdram_pll_0_sys_clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
irq_synchronizer : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => clk_clk, -- receiver_clk.clk
sender_clk => sys_sdram_pll_0_sys_clk_clk, -- sender_clk.clk
receiver_reset => rst_controller_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_001_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver0_irq -- sender.irq
);
rst_controller : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component niosii_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => sys_sdram_pll_0_sys_clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_sdram_controller_0_s1_read_ports_inv <= not mm_interconnect_0_sdram_controller_0_s1_read;
mm_interconnect_0_sdram_controller_0_s1_byteenable_ports_inv <= not mm_interconnect_0_sdram_controller_0_s1_byteenable;
mm_interconnect_0_sdram_controller_0_s1_write_ports_inv <= not mm_interconnect_0_sdram_controller_0_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
end architecture rtl; -- of niosii
| mit | 2506639aeffe63712c84db8f56e5def5 | 0.489596 | 3.593436 | false | false | false | false |
Dragonturtle/SHERPA | HDL/FPGALink/FIFO/fifo_wrapper_xilinx.vhdl | 1 | 2,101 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_wrapper is
port(
-- Clock and depth
wr_clk_in : in std_logic;
rd_clk_in : in std_logic;
depth_out : out std_logic_vector(14 downto 0);
-- Data is clocked into the FIFO on each clock edge where both valid & ready are high
inputData_in : in std_logic_vector(7 downto 0);
inputValid_in : in std_logic;
inputReady_out : out std_logic;
-- Data is clocked out of the FIFO on each clock edge where both valid & ready are high
outputData_out : out std_logic_vector(7 downto 0);
outputValid_out : out std_logic;
outputReady_in : in std_logic
);
end entity;
architecture structural of fifo_wrapper is
signal inputFull : std_logic;
signal outputEmpty : std_logic;
begin
-- Invert "full/empty" signals to give "ready/valid" signals
inputReady_out <= not(inputFull);
outputValid_out <= not(outputEmpty);
-- The encapsulated FIFO
fifo : entity work.xilinx_fifo
port map(
wr_clk => wr_clk_in,
rd_clk => rd_clk_in,
rd_data_count => depth_out,
-- Production end
din => inputData_in,
wr_en => inputValid_in,
full => inputFull,
-- Consumption end
dout => outputData_out,
empty => outputEmpty,
rd_en => outputReady_in
);
end architecture;
| gpl-3.0 | 8eeecaeb49bb102641f6e9b36c10cc74 | 0.674441 | 3.478477 | false | false | false | false |
Dragonturtle/SHERPA | HDL/Test Bench/SHERPA_tb.vhd | 1 | 4,980 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SHERPA_tb IS
END SHERPA_tb;
ARCHITECTURE behavior OF SHERPA_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_level
PORT(
fx2Clk_in : IN std_logic;
fx2Addr_out : OUT std_logic_vector(1 downto 0);
fx2Data_io : INOUT std_logic_vector(7 downto 0);
fx2Read_out : OUT std_logic;
fx2OE_out : OUT std_logic;
fx2GotData_in : IN std_logic;
fx2Write_out : OUT std_logic;
fx2GotRoom_in : IN std_logic;
fx2PktEnd_out : OUT std_logic;
sseg_out : OUT std_logic_vector(7 downto 0);
anode_out : OUT std_logic_vector(3 downto 0);
led_out : OUT std_logic_vector(7 downto 0);
sw_in : IN std_logic_vector(7 downto 0);
ADC_I : IN std_logic_vector(7 downto 0);
ADC_Q : IN std_logic_vector(7 downto 0);
CLOCK : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
CONFIG_SDA : INOUT std_logic;
CONFIG_SCL : INOUT std_logic;
CONFIG_DIN : OUT std_logic;
CONFIG_SCLK : OUT std_logic;
CONFIG_CS : OUT std_logic;
CONFIG_SHDN : OUT std_logic;
CONFIG_RXTX : OUT std_logic;
CONFIG_CW : OUT std_logic
);
END COMPONENT;
--Inputs
signal fx2Clk_in : std_logic := '0';
signal fx2GotData_in : std_logic := '0';
signal fx2GotRoom_in : std_logic := '0';
signal sw_in : std_logic_vector(7 downto 0) := (others => '0');
signal ADC_I : std_logic_vector(7 downto 0) := (others => '0');
signal ADC_Q : std_logic_vector(7 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal CLOCK : std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal fx2Data_io : std_logic_vector(7 downto 0);
signal CONFIG_SDA : std_logic;
signal CONFIG_SCL : std_logic;
--Outputs
signal fx2Addr_out : std_logic_vector(1 downto 0);
signal fx2Read_out : std_logic;
signal fx2OE_out : std_logic;
signal fx2Write_out : std_logic;
signal fx2PktEnd_out : std_logic;
signal sseg_out : std_logic_vector(7 downto 0);
signal anode_out : std_logic_vector(3 downto 0);
signal led_out : std_logic_vector(7 downto 0);
signal CONFIG_DIN : std_logic;
signal CONFIG_SCLK : std_logic;
signal CONFIG_CS : std_logic;
signal CONFIG_SHDN : std_logic;
signal CONFIG_RXTX : std_logic;
signal CONFIG_CW : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
constant fx2Clk_period : time := 20.8333333333333 ns;
constant clk0_period : time := 305.185 ns;
constant clk1_period : time := 25 ns;
constant clk2_period : time := 305.194 ns;
constant clk3_period : time := 400000 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_level PORT MAP (
fx2Clk_in => fx2Clk_in,
fx2Addr_out => fx2Addr_out,
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read_out,
fx2OE_out => fx2OE_out,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
sseg_out => sseg_out,
anode_out => anode_out,
led_out => led_out,
sw_in => sw_in,
ADC_I => ADC_I,
ADC_Q => ADC_Q,
clk => clk,
CLOCK => CLOCK,
CONFIG_SDA => CONFIG_SDA,
CONFIG_SCL => CONFIG_SCL,
CONFIG_DIN => CONFIG_DIN,
CONFIG_SCLK => CONFIG_SCLK,
CONFIG_CS => CONFIG_CS,
CONFIG_SHDN => CONFIG_SHDN,
CONFIG_RXTX => CONFIG_RXTX,
CONFIG_CW => CONFIG_CW
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
fx2Clk_process :process
begin
fx2Clk_in <= '0';
wait for fx2Clk_period/2;
fx2Clk_in <= '1';
wait for fx2Clk_period/2;
end process;
clk0_process :process
begin
CLOCK(0) <= '1';
wait for clk0_period/2;
CLOCK(0) <= '0';
wait for clk0_period/2;
end process;
clk1_process :process
begin
CLOCK(1) <= '1';
wait for clk1_period/2;
CLOCK(1) <= '0';
wait for clk1_period/2;
end process;
clk2_process :process
begin
CLOCK(2) <= '1';
wait for clk2_period/2;
CLOCK(2) <= '0';
wait for clk2_period/2;
end process;
clk3_process :process
begin
CLOCK(3) <= '1';
wait for clk3_period/2;
CLOCK(3) <= '0';
wait for clk3_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 47404b825711078812c45330804bf21c | 0.588153 | 3.182109 | false | true | false | false |
insop/hyos | hyos_plb_v1_00_e/hdl/vhdl/TSProject32.vhd | 1 | 4,186 | --
-- Title :TSProject32
--
-- Description: Tagged sorter project using TaggedSorter8.vhd
-- This component has 64 queue capacities
--
-- Note : based on Wang's algorith (TaggedSorter)
-- current fMax is 91.76Mhz (10.9 nsec)
-- if you do the timing sim faster than that, it will now work
-- make sure up and down clock can be read properly
--
-- design with Xilinx V4FX model (-10)
-- and fMax is (9.828ns), so got little faster than Altera
--
-- Author: Insop Song
-- Begin Date : 2007
-- Ver : 0.5
--
-- Revision History
-- --------------------------------------------------------------------
-- Date Author Comments
-- 2007 04 24 Insop Song fix the problem putting max to RI of Rn
-- 2007 05 01 Insop Song using the cleaned up tagged sorter
-- 2012 04 22 Insop Song update for Full/Empty and Tag
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- width_key, width_data definitions
use work.tagged_pak.all;
ENTITY TSProject32 IS
-- GENERIC (WIDTH_KEY: integer :=16;
-- WIDTH_DATA: integer :=16);
PORT
(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
insert : IN STD_LOGIC;
extract : IN STD_LOGIC;
-- LItag : IN STD_LOGIC;
LIkey : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
LIdata : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
-- ROtag : BUFFER STD_LOGIC;
ROkey : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
ROdata : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
Q_FULL : OUT STD_LOGIC;
Q_EMPTY : OUT STD_LOGIC
);
END TSProject32;
ARCHITECTURE struct OF TSProject32 IS
------------------------------------------
COMPONENT TaggedSorter32 IS
PORT
(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
insert : IN STD_LOGIC;
extract : IN STD_LOGIC;
LItag : IN STD_LOGIC;
LIkey : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
LIdata : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
ROtag : BUFFER STD_LOGIC;
ROkey : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
ROdata : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
LOtag : BUFFER STD_LOGIC;
LOkey : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
LOdata : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
RItag : IN STD_LOGIC;
RIkey : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
RIdata : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 )
);
END COMPONENT;
------------------------------------------
SIGNAL LItag1 : STD_LOGIC;
SIGNAL LOtag1 : STD_LOGIC;
SIGNAL LOkey1 : STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
SIGNAL LOdata1: STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
SIGNAL ROtag1 : STD_LOGIC;
SIGNAL ROtag2 : STD_LOGIC;
SIGNAL ROkey2 : STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
SIGNAL ROdata2: STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
-- to make maximum value for key
constant MAX_KEY_VAL : std_logic_vector ( 0 TO WIDTH_KEY -1 ) :=(others=>'1');
-- to make maximum value for key
constant MAX_DATA_VAL : std_logic_vector ( 0 TO WIDTH_DATA-1 ) :=(others=>'1');
BEGIN
-- this full indicator doesn't work
-- maybe need to add some counter type
--
Q_FULL <= '0' WHEN LOkey1 = MAX_KEY_VAL ELSE
'1';
Q_EMPTY <= '1' WHEN ROkey = MAX_KEY_VAL ELSE
'0';
--ext('1', LOkey5'length)
LItag1 <= '0';
-- ROtag2 <= '0';
-- ROkey2 <= MAX_KEY_VAL;
-- ROdata2 <= MAX_DATA_VAL;
ext: PROCESS(clk)
BEGIN
IF (rising_edge(clk)) THEN
IF (extract = '1') THEN
ROtag2 <= '0';
ROkey2 <= (others=>'1');
ROdata2 <= (others=>'1');
--ROkey2 <= MAX_KEY_VAL;
--ROdata2 <= MAX_DATA_VAL;
END IF;
END IF;
END PROCESS ext;
TS1: TaggedSorter32 PORT MAP( clk, reset , insert, extract,
LItag1, LIkey, LIdata,
ROtag1, ROkey, ROdata,
LOtag1, LOkey1, LOdata1,
ROtag2, ROkey2, ROdata2);
END struct;
| gpl-3.0 | 25b3d0410eef3cef61a1c0789220170c | 0.543478 | 3.23493 | false | false | false | false |
Subsets and Splits