// clang-format off

const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::base[OPCODE_TABLE_SIZE] =
{
  { Operation_ADD, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_ADD, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_ADD, {OperandSize_8, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_ADD, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_ADD, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_ADD, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_PUSH_Sreg, {OperandSize_16, OperandMode_SegmentRegister, Segment_ES} },
  { Operation_POP_Sreg, {OperandSize_16, OperandMode_SegmentRegister, Segment_ES} },
  { Operation_OR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_OR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_OR, {OperandSize_8, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_OR, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_OR, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_OR, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_PUSH_Sreg, {OperandSize_16, OperandMode_SegmentRegister, Segment_CS} },
  { Operation_Extension, {}, prefix_0F },
  { Operation_ADC, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_ADC, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_ADC, {OperandSize_8, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_ADC, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_ADC, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_ADC, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_PUSH_Sreg, {OperandSize_16, OperandMode_SegmentRegister, Segment_SS} },
  { Operation_POP_Sreg, {OperandSize_16, OperandMode_SegmentRegister, Segment_SS} },
  { Operation_SBB, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_SBB, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_SBB, {OperandSize_8, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SBB, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_SBB, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SBB, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_PUSH_Sreg, {OperandSize_16, OperandMode_SegmentRegister, Segment_DS} },
  { Operation_POP_Sreg, {OperandSize_16, OperandMode_SegmentRegister, Segment_DS} },
  { Operation_AND, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_AND, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_AND, {OperandSize_8, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_AND, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_AND, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_AND, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_Segment_Prefix, { { OperandSize_Count, OperandMode_SegmentRegister, Segment_ES } } },
  { Operation_DAA, {} },
  { Operation_SUB, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_SUB, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_SUB, {OperandSize_8, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SUB, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_SUB, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SUB, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_Segment_Prefix, { { OperandSize_Count, OperandMode_SegmentRegister, Segment_CS } } },
  { Operation_DAS, {} },
  { Operation_XOR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_XOR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_XOR, {OperandSize_8, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_XOR, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_XOR, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_XOR, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_Segment_Prefix, { { OperandSize_Count, OperandMode_SegmentRegister, Segment_SS } } },
  { Operation_AAA, {} },
  { Operation_CMP, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_CMP, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_CMP, {OperandSize_8, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_CMP, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMP, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_CMP, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_Segment_Prefix, { { OperandSize_Count, OperandMode_SegmentRegister, Segment_DS } } },
  { Operation_AAS, {} },
  { Operation_INC, {OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_INC, {OperandSize_Count, OperandMode_Register, Reg32_ECX} },
  { Operation_INC, {OperandSize_Count, OperandMode_Register, Reg32_EDX} },
  { Operation_INC, {OperandSize_Count, OperandMode_Register, Reg32_EBX} },
  { Operation_INC, {OperandSize_Count, OperandMode_Register, Reg32_ESP} },
  { Operation_INC, {OperandSize_Count, OperandMode_Register, Reg32_EBP} },
  { Operation_INC, {OperandSize_Count, OperandMode_Register, Reg32_ESI} },
  { Operation_INC, {OperandSize_Count, OperandMode_Register, Reg32_EDI} },
  { Operation_DEC, {OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_DEC, {OperandSize_Count, OperandMode_Register, Reg32_ECX} },
  { Operation_DEC, {OperandSize_Count, OperandMode_Register, Reg32_EDX} },
  { Operation_DEC, {OperandSize_Count, OperandMode_Register, Reg32_EBX} },
  { Operation_DEC, {OperandSize_Count, OperandMode_Register, Reg32_ESP} },
  { Operation_DEC, {OperandSize_Count, OperandMode_Register, Reg32_EBP} },
  { Operation_DEC, {OperandSize_Count, OperandMode_Register, Reg32_ESI} },
  { Operation_DEC, {OperandSize_Count, OperandMode_Register, Reg32_EDI} },
  { Operation_PUSH, {OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_PUSH, {OperandSize_Count, OperandMode_Register, Reg32_ECX} },
  { Operation_PUSH, {OperandSize_Count, OperandMode_Register, Reg32_EDX} },
  { Operation_PUSH, {OperandSize_Count, OperandMode_Register, Reg32_EBX} },
  { Operation_PUSH, {OperandSize_Count, OperandMode_Register, Reg32_ESP} },
  { Operation_PUSH, {OperandSize_Count, OperandMode_Register, Reg32_EBP} },
  { Operation_PUSH, {OperandSize_Count, OperandMode_Register, Reg32_ESI} },
  { Operation_PUSH, {OperandSize_Count, OperandMode_Register, Reg32_EDI} },
  { Operation_POP, {OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_POP, {OperandSize_Count, OperandMode_Register, Reg32_ECX} },
  { Operation_POP, {OperandSize_Count, OperandMode_Register, Reg32_EDX} },
  { Operation_POP, {OperandSize_Count, OperandMode_Register, Reg32_EBX} },
  { Operation_POP, {OperandSize_Count, OperandMode_Register, Reg32_ESP} },
  { Operation_POP, {OperandSize_Count, OperandMode_Register, Reg32_EBP} },
  { Operation_POP, {OperandSize_Count, OperandMode_Register, Reg32_ESI} },
  { Operation_POP, {OperandSize_Count, OperandMode_Register, Reg32_EDI} },
  { Operation_PUSHA, {} },
  { Operation_POPA, {} },
  { Operation_BOUND, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_ARPL, {OperandSize_16, OperandMode_ModRM_RM, 0, OperandSize_16, OperandMode_ModRM_Reg, 0} },
  { Operation_Segment_Prefix, { { OperandSize_Count, OperandMode_SegmentRegister, Segment_FS } } },
  { Operation_Segment_Prefix, { { OperandSize_Count, OperandMode_SegmentRegister, Segment_GS } } },
  { Operation_OperandSize_Prefix },
  { Operation_AddressSize_Prefix },
  { Operation_PUSH, {OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_IMUL, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_PUSH, {OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_IMUL, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_INS, {OperandSize_8, OperandMode_RegisterIndirect, Reg32_EDI, OperandSize_16, OperandMode_Register, Reg16_DX} },
  { Operation_INS, {OperandSize_Count, OperandMode_RegisterIndirect, Reg32_EDI, OperandSize_16, OperandMode_Register, Reg16_DX} },
  { Operation_OUTS, {OperandSize_16, OperandMode_Register, Reg16_DX, OperandSize_8, OperandMode_RegisterIndirect, Reg32_ESI} },
  { Operation_OUTS, {OperandSize_16, OperandMode_Register, Reg16_DX, OperandSize_Count, OperandMode_RegisterIndirect, Reg32_EDI} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Overflow}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotOverflow}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Below}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_AboveOrEqual}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Equal}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotEqual}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_BelowOrEqual}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Above}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Sign}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotSign}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Parity}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotParity}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Less}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_GreaterOrEqual}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_LessOrEqual}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Greater}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Extension_ModRM_Reg, {}, prefix_80 },
  { Operation_Extension_ModRM_Reg, {}, prefix_81 },
  { Operation_Extension_ModRM_Reg, {}, prefix_82 },
  { Operation_Extension_ModRM_Reg, {}, prefix_83 },
  { Operation_TEST, {OperandSize_8, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_TEST, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_XCHG, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_XCHG, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_MOV, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_MOV, {OperandSize_8, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_MOV_Sreg, {OperandSize_16, OperandMode_ModRM_RM, 0, OperandSize_16, OperandMode_ModRM_SegmentReg, 0} },
  { Operation_LEA, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_MOV_Sreg, {OperandSize_16, OperandMode_ModRM_SegmentReg, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_POP, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_NOP, {} },
  { Operation_XCHG, {OperandSize_Count, OperandMode_Register, Reg32_ECX, OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_XCHG, {OperandSize_Count, OperandMode_Register, Reg32_EDX, OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_XCHG, {OperandSize_Count, OperandMode_Register, Reg32_EBX, OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_XCHG, {OperandSize_Count, OperandMode_Register, Reg32_ESP, OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_XCHG, {OperandSize_Count, OperandMode_Register, Reg32_EBP, OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_XCHG, {OperandSize_Count, OperandMode_Register, Reg32_ESI, OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_XCHG, {OperandSize_Count, OperandMode_Register, Reg32_EDI, OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_CBW, {} },
  { Operation_CWD, {} },
  { Operation_CALL_Far, {OperandSize_Count, OperandMode_FarAddress, 0} },
  { Operation_WAIT, {} },
  { Operation_PUSHF, {} },
  { Operation_POPF, {} },
  { Operation_SAHF, {} },
  { Operation_LAHF, {} },
  { Operation_MOV, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Memory, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_Memory, 0} },
  { Operation_MOV, {OperandSize_8, OperandMode_Memory, 0, OperandSize_8, OperandMode_Register, Reg8_AL} },
  { Operation_MOV, {OperandSize_Count, OperandMode_Memory, 0, OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_MOVS, {OperandSize_8, OperandMode_RegisterIndirect, Reg32_EDI, OperandSize_8, OperandMode_RegisterIndirect, Reg32_ESI} },
  { Operation_MOVS, {OperandSize_Count, OperandMode_RegisterIndirect, Reg32_EDI, OperandSize_Count, OperandMode_RegisterIndirect, Reg32_ESI} },
  { Operation_CMPS, {OperandSize_8, OperandMode_RegisterIndirect, Reg32_ESI, OperandSize_8, OperandMode_RegisterIndirect, Reg32_EDI} },
  { Operation_CMPS, {OperandSize_Count, OperandMode_RegisterIndirect, Reg32_ESI, OperandSize_Count, OperandMode_RegisterIndirect, Reg32_EDI} },
  { Operation_TEST, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_TEST, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_STOS, {OperandSize_8, OperandMode_RegisterIndirect, Reg32_EDI, OperandSize_8, OperandMode_Register, Reg8_AL} },
  { Operation_STOS, {OperandSize_Count, OperandMode_RegisterIndirect, Reg32_EDI, OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_LODS, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_RegisterIndirect, Reg32_ESI} },
  { Operation_LODS, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_RegisterIndirect, Reg32_ESI} },
  { Operation_SCAS, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_RegisterIndirect, Reg32_EDI} },
  { Operation_SCAS, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_RegisterIndirect, Reg32_EDI} },
  { Operation_MOV, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_8, OperandMode_Register, Reg8_CL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_8, OperandMode_Register, Reg8_DL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_8, OperandMode_Register, Reg8_BL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_8, OperandMode_Register, Reg8_AH, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_8, OperandMode_Register, Reg8_CH, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_8, OperandMode_Register, Reg8_DH, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_8, OperandMode_Register, Reg8_BH, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_Register, Reg32_ECX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_Register, Reg32_EDX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_Register, Reg32_EBX, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_Register, Reg32_ESP, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_Register, Reg32_EBP, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_Register, Reg32_ESI, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_Register, Reg32_EDI, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_Extension_ModRM_Reg, {}, prefix_C0 },
  { Operation_Extension_ModRM_Reg, {}, prefix_C1 },
  { Operation_RET_Near, {OperandSize_16, OperandMode_Immediate, 0} },
  { Operation_RET_Near, {} },
  { Operation_LXS, {OperandSize_16, OperandMode_SegmentRegister, Segment_ES, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_LXS, {OperandSize_16, OperandMode_SegmentRegister, Segment_DS, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_MOV, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_MOV, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_ENTER, {OperandSize_16, OperandMode_Immediate, 0, OperandSize_8, OperandMode_Immediate2, 0} },
  { Operation_LEAVE, {} },
  { Operation_RET_Far, {OperandSize_16, OperandMode_Immediate, 0} },
  { Operation_RET_Far, {} },
  { Operation_INT3, {} },
  { Operation_INT, {OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_INTO, {} },
  { Operation_IRET, {} },
  { Operation_Extension_ModRM_Reg, {}, prefix_D0 },
  { Operation_Extension_ModRM_Reg, {}, prefix_D1 },
  { Operation_Extension_ModRM_Reg, {}, prefix_D2 },
  { Operation_Extension_ModRM_Reg, {}, prefix_D3 },
  { Operation_AAM, {OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_AAD, {OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SALC, {} },
  { Operation_XLAT, {} },
  { Operation_Extension_ModRM_X87, {}, prefix_D8 },
  { Operation_Extension_ModRM_X87, {}, prefix_D9 },
  { Operation_Extension_ModRM_X87, {}, prefix_DA },
  { Operation_Extension_ModRM_X87, {}, prefix_DB },
  { Operation_Extension_ModRM_X87, {}, prefix_DC },
  { Operation_Extension_ModRM_X87, {}, prefix_DD },
  { Operation_Extension_ModRM_X87, {}, prefix_DE },
  { Operation_Extension_ModRM_X87, {}, prefix_DF },
  { Operation_LOOP, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotEqual}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_LOOP, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Equal}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_LOOP, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Always}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_CXZero}, OperandSize_8, OperandMode_Relative, 0} },
  { Operation_IN, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_IN, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_OUT, {OperandSize_8, OperandMode_Immediate, 0, OperandSize_8, OperandMode_Register, Reg8_AL} },
  { Operation_OUT, {OperandSize_8, OperandMode_Immediate, 0, OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_CALL_Near, {OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_JMP_Near, {OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_JMP_Far, {OperandSize_Count, OperandMode_FarAddress, 0} },
  { Operation_JMP_Near, {OperandSize_8, OperandMode_Relative, 0} },
  { Operation_IN, {OperandSize_8, OperandMode_Register, Reg8_AL, OperandSize_16, OperandMode_Register, Reg16_DX} },
  { Operation_IN, {OperandSize_Count, OperandMode_Register, Reg32_EAX, OperandSize_16, OperandMode_Register, Reg16_DX} },
  { Operation_OUT, {OperandSize_16, OperandMode_Register, Reg16_DX, OperandSize_8, OperandMode_Register, Reg8_AL} },
  { Operation_OUT, {OperandSize_16, OperandMode_Register, Reg16_DX, OperandSize_Count, OperandMode_Register, Reg32_EAX} },
  { Operation_Lock_Prefix },
  { Operation_Invalid },
  { Operation_RepNE_Prefix },
  { Operation_Rep_Prefix },
  { Operation_HLT, {} },
  { Operation_CMC, {} },
  { Operation_Extension_ModRM_Reg, {}, prefix_F6 },
  { Operation_Extension_ModRM_Reg, {}, prefix_F7 },
  { Operation_CLC, {} },
  { Operation_STC, {} },
  { Operation_CLI, {} },
  { Operation_STI, {} },
  { Operation_CLD, {} },
  { Operation_STD, {} },
  { Operation_Extension_ModRM_Reg, {}, prefix_FE },
  { Operation_Extension_ModRM_Reg, {}, prefix_FF },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_0F[OPCODE_TABLE_SIZE] =
{
  { Operation_Extension_ModRM_Reg, {}, prefix_0F00 },
  { Operation_Extension_ModRM_Reg, {}, prefix_0F01 },
  { Operation_LAR, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_LSL, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_CLTS, {} },
  { Operation_Invalid },
  { Operation_INVD, {} },
  { Operation_WBINVD, {} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_MOV_CR, {OperandSize_32, OperandMode_ModRM_RM, 0, OperandSize_32, OperandMode_ModRM_ControlRegister, 0} },
  { Operation_MOV_DR, {OperandSize_32, OperandMode_ModRM_RM, 0, OperandSize_32, OperandMode_ModRM_DebugRegister, 0} },
  { Operation_MOV_CR, {OperandSize_32, OperandMode_ModRM_ControlRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_MOV_DR, {OperandSize_32, OperandMode_ModRM_DebugRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_MOV_TR, {OperandSize_32, OperandMode_ModRM_RM, 0, OperandSize_32, OperandMode_ModRM_TestRegister, 0} },
  { Operation_Invalid },
  { Operation_MOV_TR, {OperandSize_32, OperandMode_ModRM_TestRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_WRMSR, {} },
  { Operation_RDTSC, {} },
  { Operation_RDMSR, {} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Overflow}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotOverflow}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Below}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_AboveOrEqual}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Equal}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotEqual}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_BelowOrEqual}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Above}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Sign}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotSign}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Parity}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotParity}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Less}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_GreaterOrEqual}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_LessOrEqual}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMOVcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Greater}, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Overflow}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotOverflow}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Below}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_AboveOrEqual}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Equal}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotEqual}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_BelowOrEqual}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Above}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Sign}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotSign}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Parity}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotParity}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Less}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_GreaterOrEqual}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_LessOrEqual}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_Jcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Greater}, OperandSize_Count, OperandMode_Relative, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Overflow}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotOverflow}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Below}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_AboveOrEqual}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Equal}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotEqual}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_BelowOrEqual}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Above}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Sign}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotSign}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Parity}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_NotParity}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Less}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_GreaterOrEqual}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_LessOrEqual}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_SETcc, { { OperandSize_8, OperandMode_JumpCondition, JumpCondition_Greater}, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_PUSH_Sreg, {OperandSize_16, OperandMode_SegmentRegister, Segment_FS} },
  { Operation_POP_Sreg, {OperandSize_16, OperandMode_SegmentRegister, Segment_FS} },
  { Operation_CPUID, {} },
  { Operation_BT, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_SHLD, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SHLD, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_PUSH_Sreg, {OperandSize_16, OperandMode_SegmentRegister, Segment_GS} },
  { Operation_POP_Sreg, {OperandSize_16, OperandMode_SegmentRegister, Segment_GS} },
  { Operation_RSM, {} },
  { Operation_BTS, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_SHRD, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SHRD, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_Invalid },
  { Operation_IMUL, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CMPXCHG, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_CMPXCHG, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_LXS, {OperandSize_16, OperandMode_SegmentRegister, Segment_SS, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_BTR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_LXS, {OperandSize_16, OperandMode_SegmentRegister, Segment_FS, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_LXS, {OperandSize_16, OperandMode_SegmentRegister, Segment_GS, OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_MOVZX, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_MOVZX, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Extension_ModRM_Reg, {}, prefix_0FBA },
  { Operation_BTC, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_BSF, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_BSR, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_MOVSX, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_MOVSX, {OperandSize_Count, OperandMode_ModRM_Reg, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_XADD, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_ModRM_Reg, 0} },
  { Operation_XADD, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_ModRM_Reg, 0} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_CMPXCHG8B, {OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_BSWAP, {OperandSize_32, OperandMode_Register, Reg32_EAX} },
  { Operation_BSWAP, {OperandSize_32, OperandMode_Register, Reg32_ECX} },
  { Operation_BSWAP, {OperandSize_32, OperandMode_Register, Reg32_EDX} },
  { Operation_BSWAP, {OperandSize_32, OperandMode_Register, Reg32_EBX} },
  { Operation_BSWAP, {OperandSize_32, OperandMode_Register, Reg32_ESP} },
  { Operation_BSWAP, {OperandSize_32, OperandMode_Register, Reg32_EBP} },
  { Operation_BSWAP, {OperandSize_32, OperandMode_Register, Reg32_ESI} },
  { Operation_BSWAP, {OperandSize_32, OperandMode_Register, Reg32_EDI} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_0F00[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_SLDT, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_STR, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_LLDT, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_LTR, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_VERR, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_VERW, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_Invalid },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_0F01[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_SGDT, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_SIDT, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_LGDT, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_LIDT, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_SMSW, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_LMSW, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_INVLPG, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_0FBA[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_BT, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_BTS, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_BTR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_BTC, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_80[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_ADD, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_OR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_ADC, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SBB, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_AND, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SUB, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_XOR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_CMP, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_81[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_ADD, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_OR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_ADC, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_SBB, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_AND, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_SUB, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_XOR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_CMP, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_Immediate, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_82[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_ADD, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_OR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_ADC, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SBB, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_AND, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SUB, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_XOR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_CMP, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_83[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_ADD, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_OR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_ADC, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SBB, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_AND, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SUB, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_XOR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_CMP, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_C0[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_ROL, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_ROR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_RCL, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_RCR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SHL, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SHR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_Invalid },
  { Operation_SAR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_C1[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_ROL, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_ROR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_RCL, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_RCR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SHL, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_SHR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_Invalid },
  { Operation_SAR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_D0[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_ROL, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_ROR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_RCL, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_RCR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_SHL, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_SHR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_Invalid },
  { Operation_SAR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_D1[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_ROL, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_ROR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_RCL, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_RCR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_SHL, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_SHR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
  { Operation_Invalid },
  { Operation_SAR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Constant, 1} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_D2[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_ROL, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_ROR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_RCL, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_RCR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_SHL, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_SHR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_Invalid },
  { Operation_SAR, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_D3[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_ROL, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_ROR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_RCL, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_RCR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_SHL, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_SHR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
  { Operation_Invalid },
  { Operation_SAR, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Register, Reg8_CL} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_D8[X87_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 7} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_D9[X87_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_FLD, {OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_FST, {OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FSTP, {OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FLDENV, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_FLDCW, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FNSTENV, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_FNSTCW, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FLD, {OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FLD, {OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FLD, {OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FLD, {OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FLD, {OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FLD, {OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FLD, {OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FLD, {OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FXCH, {OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FXCH, {OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FXCH, {OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FXCH, {OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FXCH, {OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FXCH, {OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FXCH, {OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FXCH, {OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FNOP, {} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_FCHS, {} },
  { Operation_FABS, {} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_FTST, {} },
  { Operation_FXAM, {} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_FLD1, {} },
  { Operation_FLDL2T, {} },
  { Operation_FLDL2E, {} },
  { Operation_FLDPI, {} },
  { Operation_FLDLG2, {} },
  { Operation_FLDLN2, {} },
  { Operation_FLDZ, {} },
  { Operation_Invalid },
  { Operation_F2XM1, {} },
  { Operation_FYL2X, {} },
  { Operation_FPTAN, {} },
  { Operation_FPATAN, {} },
  { Operation_FXTRACT, {} },
  { Operation_FPREM1, {} },
  { Operation_FDECSTP, {} },
  { Operation_FINCSTP, {} },
  { Operation_FPREM, {} },
  { Operation_FYL2XP1, {} },
  { Operation_FSQRT, {} },
  { Operation_FSINCOS, {} },
  { Operation_FRNDINT, {} },
  { Operation_FSCALE, {} },
  { Operation_FSIN, {} },
  { Operation_FCOS, {} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_DA[X87_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_FIADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FIMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FICOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FICOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FISUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FISUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FIDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FIDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_FUCOMPP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_DB[X87_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_FILD, {OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_FIST, {OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_FISTP, {OperandSize_32, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_FLD, {OperandSize_80, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_FSTP, {OperandSize_80, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_FNENI, {} },
  { Operation_FNDISI, {} },
  { Operation_FNCLEX, {} },
  { Operation_FNINIT, {} },
  { Operation_FSETPM, {} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_DC[X87_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADD, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMUL, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOM, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FCOMP, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBR, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUB, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVR, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIV, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_DD[X87_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_FLD, {OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_FST, {OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_FSTP, {OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_FRSTOR, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_FNSAVE, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_FNSTSW, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FFREE, {OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FFREE, {OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FFREE, {OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FFREE, {OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FFREE, {OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FFREE, {OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FFREE, {OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FFREE, {OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_FST, {OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FST, {OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FST, {OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FST, {OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FST, {OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FST, {OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FST, {OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FST, {OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FSTP, {OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSTP, {OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FSTP, {OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FSTP, {OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FSTP, {OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FSTP, {OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FSTP, {OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FSTP, {OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FUCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FUCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FUCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FUCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FUCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FUCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FUCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FUCOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_FUCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FUCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_FUCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 2} },
  { Operation_FUCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 3} },
  { Operation_FUCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 4} },
  { Operation_FUCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 5} },
  { Operation_FUCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 6} },
  { Operation_FUCOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 7} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_DE[X87_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_FIADD, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FIMUL, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FICOM, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FICOMP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FISUB, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FISUBR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FIDIV, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FIDIVR, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FADDP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADDP, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADDP, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADDP, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADDP, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADDP, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADDP, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FADDP, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMULP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMULP, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMULP, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMULP, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMULP, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMULP, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMULP, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FMULP, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_FCOMPP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 1} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_FSUBRP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBRP, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBRP, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBRP, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBRP, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBRP, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBRP, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBRP, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBP, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBP, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBP, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBP, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBP, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBP, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FSUBP, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVRP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVRP, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVRP, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVRP, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVRP, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVRP, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVRP, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVRP, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVP, {OperandSize_80, OperandMode_FPRegister, 0, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVP, {OperandSize_80, OperandMode_FPRegister, 1, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVP, {OperandSize_80, OperandMode_FPRegister, 2, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVP, {OperandSize_80, OperandMode_FPRegister, 3, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVP, {OperandSize_80, OperandMode_FPRegister, 4, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVP, {OperandSize_80, OperandMode_FPRegister, 5, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVP, {OperandSize_80, OperandMode_FPRegister, 6, OperandSize_80, OperandMode_FPRegister, 0} },
  { Operation_FDIVP, {OperandSize_80, OperandMode_FPRegister, 7, OperandSize_80, OperandMode_FPRegister, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_DF[X87_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_FILD, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_FIST, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FISTP, {OperandSize_16, OperandMode_ModRM_RM, 0} },
  { Operation_FBLD, {OperandSize_80, OperandMode_ModRM_RM, 0} },
  { Operation_FILD, {OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_FBSTP, {OperandSize_80, OperandMode_ModRM_RM, 0} },
  { Operation_FISTP, {OperandSize_64, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_FNSTSW, {OperandSize_16, OperandMode_Register, Reg16_AX} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_F6[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_TEST, {OperandSize_8, OperandMode_ModRM_RM, 0, OperandSize_8, OperandMode_Immediate, 0} },
  { Operation_Invalid },
  { Operation_NOT, {OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_NEG, {OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_MUL, {OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_IMUL, {OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_DIV, {OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_IDIV, {OperandSize_8, OperandMode_ModRM_RM, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_F7[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_TEST, {OperandSize_Count, OperandMode_ModRM_RM, 0, OperandSize_Count, OperandMode_Immediate, 0} },
  { Operation_Invalid },
  { Operation_NOT, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_NEG, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_MUL, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_IMUL, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_DIV, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_IDIV, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_FE[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_INC, {OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_DEC, {OperandSize_8, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
  { Operation_Invalid },
};
const CPU_X86::Decoder::TableEntry CPU_X86::Decoder::prefix_FF[MODRM_EXTENSION_OPCODE_TABLE_SIZE] =
{
  { Operation_INC, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_DEC, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CALL_Near, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_CALL_Far, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_JMP_Near, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_JMP_Far, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_PUSH, {OperandSize_Count, OperandMode_ModRM_RM, 0} },
  { Operation_Invalid },
};

// clang-format on
