start
xhci_write_event: 
ER_PORT_STATUS_CHANGE
CC_SUCCESS
xhci_ring_fetch: 
CR_ENABLE_SLOT
xhci_write_event: 
ER_COMMAND_COMPLETE
CC_SUCCESS
xhci_ring_fetch: 
TRB_RESERVED
xhci_write_event: 
ER_PORT_STATUS_CHANGE
CC_SUCCESS
xhci_ring_fetch: 
CR_ADDRESS_DEVICE
xhci_write_event: 
ER_COMMAND_COMPLETE
CC_SUCCESS
xhci_ring_fetch: 
TRB_RESERVED
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SHORT_PACKET
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SHORT_PACKET
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SHORT_PACKET
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SHORT_PACKET
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
CR_CONFIGURE_ENDPOINT
xhci_write_event: 
ER_COMMAND_COMPLETE
CC_SUCCESS
xhci_ring_fetch: 
TRB_RESERVED
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SHORT_PACKET
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_SETUP
xhci_ring_fetch: 
TR_DATA
xhci_ring_fetch: 
TR_STATUS
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
xhci_ring_fetch: 
TR_NORMAL
xhci_write_event: 
ER_TRANSFER
CC_SUCCESS
start