#include "cycles.h"
namespace CPU_X86 {

// Most numbers from MAME: https://github.com/mamedev/mame/blob/master/src/devices/cpu/i386/cycles.h#L625 (BSD 3 Clause)

const u32 g_cycle_group_timings[NUM_CYCLE_GROUPS][3] = {
  // 386 486 Pentium
  {2, 1, 1},       // CYCLES_MOV_RM_MEM_REG
  {2, 1, 1},       // CYCLES_MOV_RM_REG_REG
  {4, 1, 1},       // CYCLES_MOV_REG_RM_MEM
  {2, 1, 1},       // CYCLES_MOV_REG_RM_REG
  {2, 1, 1},       // CYCLES_MOV_REG_IMM
  {4, 1, 1},       // CYCLES_MOV_REG_MEM
  {2, 3, 1},       // CYCLES_MOV_SREG_RM_MEM
  {18, 3, 2},      // CYCLES_MOV_SREG_RM_MEM_PMODE
  {5, 9, 3},       // CYCLES_MOV_SREG_RM_REG
  {19, 9, 3},      // CYCLES_MOV_SREG_RM_REG_PMODE
  {2, 3, 1},       // CYCLES_MOV_RM_MEM_SREG
  {2, 3, 1},       // CYCLES_MOV_RM_REG_SREG
  {6, 3, 3},       // CYCLES_MOVSX_REG_RM_MEM
  {3, 3, 3},       // CYCLES_MOVSX_REG_RM_REG
  {6, 3, 3},       // CYCLES_MOVZX_REG_RM_MEM
  {3, 3, 3},       // CYCLES_MOVZX_REG_RM_REG
  {5, 5, 3},       // CYCLES_XCHG_REG_RM_MEM
  {3, 3, 3},       // CYCLES_XCHG_REG_RM_REG
  {12, 14, 7},     // CYCLES_IN_IMM
  {26, 27, 19},    // CYCLES_IN_IMM_PMODE
  {13, 14, 7},     // CYCLES_IN_EDX
  {27, 27, 19},    // CYCLES_IN_EDX_PMODE
  {10, 16, 12},    // CYCLES_OUT_IMM
  {26, 27, 19},    // CYCLES_OUT_IMM_PMODE
  {11, 16, 12},    // CYCLES_OUT_EDX
  {25, 29, 24},    // CYCLES_OUT_EDX_PMODE
  {2, 1, 1},       // CYCLES_LEA
  {7, 6, 4},       // CYCLES_LxS
  {22, 12, 4},     // CYCLES_LxS_PMODE
  {2, 2, 2},       // CYCLES_CLEAR_SET_FLAG
  {8, 5, 7},       // CYCLES_CLI
  {6, 7, 10},      // CYCLES_CLTS
  {2, 3, 2},       // CYCLES_LAHF
  {3, 2, 2},       // CYCLES_SAHF
  {4, 4, 9},       // CYCLES_PUSHF
  {5, 9, 6},       // CYCLES_POPF
  {18, 11, 5},     // CYCLES_PUSHA
  {24, 9, 5},      // CYCLES_POPA
  {5, 4, 2},       // CYCLES_PUSH_MEM
  {2, 1, 1},       // CYCLES_PUSH_REG
  {2, 3, 1},       // CYCLES_PUSH_SREG
  {2, 1, 1},       // CYCLES_PUSH_IMM
  {4, 4, 1},       // CYCLES_POP_REG
  {5, 4, 3},       // CYCLES_POP_MEM
  {7, 3, 3},       // CYCLES_POP_SREG
  {21, 3, 3},      // CYCLES_POP_SREG_PMODE
  {4, 3, 3},       // CYCLES_BCD_ADDSUB
  {19, 14, 10},    // CYCLES_AAM
  {17, 15, 18},    // CYCLES_AAD
  {3, 3, 3},       // CYCLES_CBW
  {2, 2, 2},       // CYCLES_CWD
  {5, 4, 4},       // CYCLES_XLAT
  {2, 1, 1},       // CYCLES_ALU_REG_IMM
  {6, 2, 2},       // CYCLES_ALU_REG_RM_MEM
  {2, 1, 1},       // CYCLES_ALU_REG_RM_REG
  {7, 3, 3},       // CYCLES_ALU_RM_MEM_REG
  {2, 1, 1},       // CYCLES_ALU_RM_REG_REG
  {2, 1, 1},       // CYCLES_CMP_REG_IMM
  {6, 2, 2},       // CYCLES_CMP_REG_RM_MEM
  {2, 1, 1},       // CYCLES_CMP_REG_RM_REG
  {5, 2, 2},       // CYCLES_CMP_RM_MEM_REG
  {2, 1, 1},       // CYCLES_CMP_RM_REG_REG
  {6, 3, 3},       // CYCLES_INC_RM_MEM
  {2, 1, 1},       // CYCLES_INC_RM_REG
  {6, 3, 3},       // CYCLES_NEG_RM_MEM
  {2, 1, 1},       // CYCLES_NEG_RM_REG
  {5, 2, 2},       // CYCLES_TEST_REG_RM_MEM
  {2, 1, 1},       // CYCLES_TEST_REG_RM_REG
  {5, 2, 2},       // CYCLES_TEST_RM_MEM_REG
  {2, 1, 1},       // CYCLES_TEST_RM_REG_REG
  {20, 13, 11},    // CYCLES_MUL_8_RM_MEM
  {17, 13, 11},    // CYCLES_MUL_8_RM_REG
  {28, 13, 11},    // CYCLES_MUL_16_RM_MEM
  {25, 13, 11},    // CYCLES_MUL_16_RM_REG
  {44, 13, 10},    // CYCLES_MUL_32_RM_MEM
  {41, 13, 10},    // CYCLES_MUL_32_RM_REG
  {20, 18, 10},    // CYCLES_IMUL_8_RM_MEM
  {17, 18, 10},    // CYCLES_IMUL_8_RM_REG
  {28, 26, 10},    // CYCLES_IMUL_16_RM_MEM
  {25, 26, 10},    // CYCLES_IMUL_16_RM_REG
  {27, 26, 10},    // CYCLES_IMUL_16_REG_RM_MEM
  {26, 26, 10},    // CYCLES_IMUL_16_REG_RM_REG
  {44, 13, 10},    // CYCLES_IMUL_32_RM_MEM
  {41, 13, 10},    // CYCLES_IMUL_32_RM_REG
  {43, 42, 10},    // CYCLES_IMUL_32_REG_RM_MEM
  {42, 42, 10},    // CYCLES_IMUL_32_REG_RM_REG
  {17, 16, 17},    // CYCLES_DIV_8_RM_MEM
  {14, 16, 17},    // CYCLES_DIV_8_RM_REG
  {25, 24, 25},    // CYCLES_DIV_16_RM_MEM
  {22, 24, 25},    // CYCLES_DIV_16_RM_REG
  {41, 40, 41},    // CYCLES_DIV_32_RM_MEM
  {38, 40, 41},    // CYCLES_DIV_32_RM_REG
  {22, 20, 22},    // CYCLES_IDIV_8_RM_MEM
  {19, 19, 22},    // CYCLES_IDIV_8_RM_REG
  {30, 27, 30},    // CYCLES_IDIV_16_RM_MEM
  {27, 28, 30},    // CYCLES_IDIV_16_RM_REG
  {43, 44, 46},    // CYCLES_IDIV_32_RM_MEM
  {46, 43, 46},    // CYCLES_IDIV_32_RM_REG
  {7, 4, 3},       // CYCLES_ROL_RM_MEM
  {3, 3, 1},       // CYCLES_ROL_RM_REG
  {10, 9, 8},      // CYCLES_RCL_RM_MEM
  {9, 8, 7},       // CYCLES_RCL_RM_REG
  {7, 3, 4},       // CYCLES_SHLD_RM_MEM
  {3, 2, 4},       // CYCLES_SHLD_RM_REG
  {10, 8, 5},      // CYCLES_CMPS
  {15, 17, 9},     // CYCLES_INS
  {29, 30, 22},    // CYCLES_INS_PMODE
  {5, 5, 2},       // CYCLES_LODS
  {8, 7, 4},       // CYCLES_MOVS
  {14, 17, 13},    // CYCLES_OUTS
  {28, 30, 25},    // CYCLES_OUTS_PMODE
  {8, 6, 4},       // CYCLES_SCAS
  {5, 5, 3},       // CYCLES_STOS
  {5, 1, 1},       // CYCLES_REP_CMPS_BASE
  {14, 0, 0},      // CYCLES_REP_INS_BASE
  {8, 0, 0},       // CYCLES_REP_INS_PMODE_BASE
  {5, 0, 0},       // CYCLES_REP_LODS_BASE
  {8, 0, 0},       // CYCLES_REP_MOVS_BASE
  {12, 0, 0},      // CYCLES_REP_OUTS_BASE
  {6, 0, 0},       // CYCLES_REP_OUTS_PMODE_BASE
  {5, 0, 0},       // CYCLES_REP_SCAS_BASE
  {5, 0, 0},       // CYCLES_REP_STOS_BASE
  {5, 8, 5},       // CYCLES_REP_CMPS_N
  {14, 17, 9},     // CYCLES_REP_INS_N
  {8, 30, 22},     // CYCLES_REP_INS_PMODE_N
  {5, 5, 2},       // CYCLES_REP_LODS_N
  {8, 7, 4},       // CYCLES_REP_MOVS_N
  {12, 17, 13},    // CYCLES_REP_OUTS_N
  {6, 30, 25},     // CYCLES_REP_OUTS_PMODE_N
  {5, 6, 4},       // CYCLES_REP_SCAS_N
  {5, 5, 3},       // CYCLES_REP_STOS_N
  {44, 7, 8},      // CYCLES_BOUND_FAIL
  {10, 7, 8},      // CYCLES_BOUND_SUCCESS
  {0, 1, 1},       // CYCLES_BSWAP
  {0, 6, 5},       // CYCLES_CMPXCHG
  {0, 0, 10},      // CYCLES_CMPXCHG8B
  {0, 1, 1},       // CYCLES_CMOV
  {0, 4, 4},       // CYCLES_XADD
  {0, 4, 15},      // CYCLES_INVD
  {0, 4, 15},      // CYCLES_INVPLG   TODO
  {0, 0, 14},      // CYCLES_CPUID
  {0, 0, 1},       // CYCLES_RDTSC
  {0, 0, 57},      // CYCLES_RSM
  {0, 0, 1},       // CYCLES_RDMSR
  {10, 6, 6},      // CYCLES_BSF_BASE
  {4, 1, 1},       // CYCLES_BSF_N
  {12, 12, 8},     // CYCLES_BT_RM_MEM_REG
  {3, 3, 4},       // CYCLES_BT_RM_REG_REG
  {6, 6, 4},       // CYCLES_BT_RM_MEM_IMM
  {3, 3, 4},       // CYCLES_BT_RM_REG_IMM
  {13, 13, 13},    // CYCLES_BTx_RM_MEM_REG
  {6, 6, 7},       // CYCLES_BTx_RM_REG_REG
  {8, 8, 8},       // CYCLES_BTx_RM_MEM_IMM
  {6, 6, 7},       // CYCLES_BTx_RM_REG_IMM
  {3, 1, 1},       // CYCLES_Jcc_NOT_TAKEN
  {7, 1, 1},       // CYCLES_Jcc_TAKEN
  {5, 1, 1},       // CYCLES_JCXZ_NOT_TAKEN
  {9, 1, 1},       // CYCLES_JCXZ_TAKEN
  {11, 6, 5},      // CYCLES_LOOP
  {11, 9, 8},      // CYCLES_LOOPZ
  {5, 4, 2},       // CYCLES_SETcc_RM_MEM
  {4, 3, 2},       // CYCLES_SETcc_RM_REG
  {10, 14, 11},    // CYCLES_ENTER
  {4, 5, 3},       // CYCLES_LEAVE
  {7, 3, 1},       // CYCLES_CALL
  {10, 5, 2},      // CYCLES_CALL_NEAR_RM_MEM
  {7, 5, 2},       // CYCLES_CALL_NEAR_RM_REG
  {7, 3, 1},       // CYCLES_JMP
  {10, 5, 2},      // CYCLES_JMP_NEAR_RM_MEM
  {7, 5, 2},       // CYCLES_JMP_NEAR_RM_REG
  {17, 18, 4},     // CYCLES_CALL_FAR
  {34, 20, 13},    // CYCLES_CALL_FAR_PMODE
  {22, 17, 4},     // CYCLES_CALL_FAR_PTR
  {38, 20, 14},    // CYCLES_CALL_FAR_PTR_PMODE
  {12, 17, 3},     // CYCLES_JMP_FAR
  {27, 19, 3},     // CYCLES_JMP_FAR_PMODE
  {17, 13, 4},     // CYCLES_JMP_FAR_PTR
  {31, 18, 4},     // CYCLES_JMP_FAR_PTR_PMODE
  {10, 5, 2},      // CYCLES_RET_NEAR
  {18, 13, 4},     // CYCLES_RET_FAR
  {32, 13, 4},     // CYCLES_RET_FAR_PMODE
  {37, 30, 16},    // CYCLES_INT
  {33, 26, 13},    // CYCLES_INT3
  {3, 3, 4},       // CYCLES_INTO_FALSE
  {35, 28, 13},    // CYCLES_INTO_TRUE
  {22, 15, 8},     // CYCLES_IRET
  {38, 15, 1},     // CYCLES_IRET_PMODE
  {5, 4, 4},       // CYCLES_HLT
  {3, 1, 1},       // CYCLES_NOP
  {7, 1, 1},       // CYCLES_WAIT
  {11, 16, 16},    // CYCLES_MOV_CR0_REG
  {4, 4, 4},       // CYCLES_MOV_CR2_REG
  {5, 4, 4},       // CYCLES_MOV_CR3_REG
  {6, 4, 4},       // CYCLES_MOV_REG_CR
  {22, 10, 10},    // CYCLES_MOV_DR1_3_REG
  {16, 10, 10},    // CYCLES_MOV_DR6_7_REG
  {14, 11, 11},    // CYCLES_MOV_REG_DR1_3
  {22, 11, 11},    // CYCLES_MOV_REG_DR6_7
  {20, 9, 7},      // CYCLES_ARPL_RM_MEM
  {21, 9, 7},      // CYCLES_ARPL_RM_REG
  {16, 11, 8},     // CYCLES_LAR_RM_MEM
  {15, 11, 8},     // CYCLES_LAR_RM_REG
  {22, 10, 8},     // CYCLES_LSL_RM_MEM
  {21, 10, 8},     // CYCLES_LSL_RM_REG
  {23, 20, 10},    // CYCLES_LTR_RM_MEM
  {27, 20, 10},    // CYCLES_LTR_RM_REG
  {11, 11, 6},     // CYCLES_LGDT
  {24, 11, 9},     // CYCLES_LLDT_RM_MEM
  {20, 11, 9},     // CYCLES_LLDT_RM_REG
  {14, 13, 8},     // CYCLES_LMSW_RM_MEM
  {11, 13, 8},     // CYCLES_LMSW_RM_REG
  {2, 2, 4},       // CYCLES_SMSW_RM_MEM
  {2, 3, 4},       // CYCLES_SMSW_RM_REG
  {9, 10, 4},      // CYCLES_SGDT
  {2, 3, 2},       // CYCLES_SLDT_RM_MEM
  {2, 2, 2},       // CYCLES_SLDT_RM_REG
  {27, 3, 2},      // CYCLES_STR_RM_MEM
  {23, 2, 2},      // CYCLES_STR_RM_REG
  {11, 11, 7},     // CYCLES_VERR_RM_MEM
  {10, 11, 7},     // CYCLES_VERR_RM_REG
  {16, 11, 7},     // CYCLES_VERW_RM_MEM
  {15, 11, 7},     // CYCLES_VERW_RM_REG
  {1, 1, 1},       // CYCLES_F2XM1 TODO
  {3, 3, 1},       // CYCLES_FABS
  {8, 8, 3},       // CYCLES_FADD
  {70, 70, 48},    // CYCLES_FBLD
  {172, 172, 148}, // CYCLES_FBSTP
  {16, 6, 1},      // CYCLES_FCHS
  {4, 4, 1},       // CYCLES_FCOM
  {3, 3, 1},       // CYCLES_FDECSTP
  {73, 73, 39},    // CYCLES_FDIV
  {3, 3, 1},       // CYCLES_FFREE
  {20, 20, 7},     // CYCLES_FIADD
  {16, 16, 8},     // CYCLES_FICOM
  {85, 85, 42},    // CYCLES_FIDIV
  {13, 13, 3},     // CYCLES_FILD
  {23, 23, 7},     // CYCLES_FIMUL
  {3, 3, 1},       // CYCLES_FINCSTP
  {29, 29, 6},     // CYCLES_FIST
  {20, 20, 7},     // CYCLES_FISUB
  {4, 4, 1},       // CYCLES_FLD
  {4, 4, 2},       // CYCLES_FLD_CONSTANT
  {8, 8, 5},       // CYCLES_FLD_LONG_CONSTANT
  {4, 4, 7},       // CYCLES_FLDCW
  {44, 44, 37},    // CYCLES_FLDENV
  {16, 16, 3},     // CYCLES_FMUL
  {7, 7, 9},       // CYCLES_FNCLEX
  {3, 3, 1},       // CYCLES_FNDISI
  {3, 3, 1},       // CYCLES_FNENI
  {17, 17, 16},    // CYCLES_FNINIT
  {154, 154, 127}, // CYCLES_FNSAVE
  {3, 3, 2},       // CYCLES_FNSTCW
  {67, 67, 48},    // CYCLES_FNSTENV
  {3, 3, 2},       // CYCLES_FNSTSW
  {3, 3, 1},       // CYCLES_FNOP
  {218, 218, 173}, // CYCLES_FPATAN
  {70, 70, 16},    // CYCLES_FPREM
  {200, 200, 173}, // CYCLES_FPTAN
  {21, 21, 9},     // CYCLES_FRNDINT
  {131, 131, 75},  // CYCLES_FRSTOR
  {30, 30, 20},    // CYCLES_FSCALE
  {83, 83, 70},    // CYCLES_FSQRT
  {3, 3, 1},       // CYCLES_FST
  {8, 8, 3},       // CYCLES_FSUB
  {4, 4, 4},       // CYCLES_FTST
  {8, 8, 21},      // CYCLES_FXAM
  {4, 4, 1},       // CYCLES_FXCH
  {16, 16, 13},    // CYCLES_FXTRACT
  {196, 196, 111}, // CYCLES_FYL2X
  {171, 171, 103}, // CYCLES_FYL2XP1
  {3, 3, 1},       // CYCLES_FSETPM
  {255, 255, 124}, // CYCLES_FCOS
  {72, 72, 20},    // CYCLES_FPREM1
  {255, 255, 126}, // CYCLES_FSIN
  {255, 255, 137}, // CYCLES_FSINCOS
  {4, 4, 4},       // CYCLES_FUCOM
};
} // namespace CPU_X86