Ticket Name: DRA77P: ipu firmware build issue

Query Text:
Part Number: DRA77P Other Parts Discussed in Thread: SYSBIOS Hi, I am working on vision SDK v3.07, I was adding some sysbios codes from DisplayDss_main.c and have added it to main_common_ipu2.c so that I would able to initialise HDMI display as soon as the firmwares are loaded. I am facing some buid errors as follows, # Compiling tda2px-evm:ipu2:release:vision_sdk: /home/ubantu/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/apps/src/common/app_init/app_init_ipu_primary.c
# Compiling generated MAIN_APP_ipu2_pem4.oem4
# Linking into /home/ubantu/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2px_evm_linux_all/vision_sdk/bin/tda2px-evm/vision_sdk_ipu2_release.xem4...
#
"/home/ubantu/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2px_evm_linux_all/obj/vision_sdk/tda2px-evm/ipu2/release/vision_sdk_configuro/linker_mod.cmd", line 276: error: 
   program will not fit into available memory.  run placement with alignment
   fails for section "GROUP_1" size 0xf491bb2 .  Available memory ranges:
   IPU2_DATA_MEM   size: 0x1400000    unused: 0xeb5d01     max hole: 0xeb5cfc
error: errors encountered during linking;
   "/home/ubantu/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2
   px_evm_linux_all/vision_sdk/bin/tda2px-evm/vision_sdk_ipu2_release.xem4" not
   built
make[7]: *** [/home/ubantu/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2px_evm_linux_all/vision_sdk/bin/tda2px-evm/vision_sdk_ipu2_release.xem4] Error 1
make[6]: *** [ipu2] Error 2
make[5]: *** [apps_ipu2] Error 2
make[4]: *** [apps] Error 2
make[3]: *** [apps] Error 2
make[2]: *** [apps_exe] Error 2
make[1]: *** [apps] Error 2
make: *** [vision_sdk] Error 2
 Correct me if I am wrong. Are there any other alternatives ? Regards, Padmesh

Responses:
Hi Padmesh, This error shows that there is not enough memory left for placement. What code you are trying to add and how big is it? Can you remove unneeded links if you don't need them and try? Thanks RamPrasad

Hi Ram, This code is an dss example of vps drivers, which i have included in the main_common_ipu2.c. This code is intended to show a logo on the hdmi. Regards, Padmesh

Hi Padmesh, I checked internally on the compilation failure. This is clearly memory is not available for placement issue. You can adjust the size of IPU section for this. If the code is already available in vps library, you can call that specific function instead of copying the same code in ipu2. Thanks RamPrasad

Ticket Name: TDA4VM: Is there response time data for TDA4?

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2, Hi Expert, My customer concern the delay time very much, especially they experience long delay time of TDA2. Any delay time performance of TDA4 and AM62A that can show to my customer ? Thanks Daniel

Hello Daniel, Can you explain which delay time performance you are referencing? Is there a particular module such as memory (e.g. DDR) or perhaps CPU performance numbers? So we can find the right person to reply. Regards, Erick

Hello Erick, i'm the customer Daniel mentioned, we used 2 camera to detect object, such as car, person, bike, our usecase was changed from tidl_od, each ssd model(0.64GMACS) run on 2 EVEs, we used tda2sxbu with plus mode, ddr was configured as DDR3-1066 ,2 EMIF(256M+256M+256M+256M) ， the fps of alg_tidl_dsp link was 24~25 the system average delay time we calculated was about 0.15s so when bike speed up to 10km/hr, the detection results rectangle will be behind the bike, now we want to know if we porting the whole usecase to tda4VM or AM62A, Will it still be the same situation? It means that the application of AI model detection, how much the basic delay time? BR, Jay

TDA 2x supported less than 0.25 TOPS only, The TDA4VM supports 8 TOPS, so the latency would be much better in these devices compared to TDA2x

Ticket Name: TDA2: Conflict in power state and its status register

Part Number: TDA2 Hi Sir, As shown in the screen shot, PM_DSS_PWRSTCTRL DSS module power state is in off state but its status register showing it is in on state. Could you please explain why it is happening? Regards, Sagar

Hi Sagar, PM_DSS_PWRSTST is showing the reset values. Are you facing any issue? Regards, Rishabh

Hi Rishabh, Due to unused cores are in active state the power consumption is more beyond its limit. So need to verify whether these cores are in ON state or in OFF state. Regards, Sagar

Hi Sagar, PM_DSS_PWRSTCTRL - "This register controls the DSS power state to reach upon a domain sleep transition". So it is the state expected to be reached on domain sleep transition. It is more of configuration/control register, what state to be when domain sleep transition happens whereas PM_DSS_PWRSTST - "This register provides a status on the current DSS power domain state. [warm reset insensitive]" . This provides the current state. So it means the domain is not gone to sleep state and it is ON

Hi Sagar, DSS is not a CPU, you should look at unused CPUs. How are you making sure that unused CPUs are in low power state/turned off? What is the software that you are using? Regards, Rishabh

Hi Rishabh, I am checking PM_xxx_PWRSTCTRL register[1:0] POWERSTATE bits to confirm whether it is in ON or OFF state. I am using TI SBL and debugging using Lauterbach. Regards, Sagar

Hi Sagar, Did you build SBL for prod mode? As far as DSS is concerned, the module is off here as you can see in PWRSTCTRL register. Regards, Rishabh

Hi Rishabh, No, it is not build for prod mode. Yes, it is in off state as per PWRSTCTRL, but status register showing it is in active state. PM_xxx_PWRSTST[1:0] POWERSTATEST . Status register should be update with OFF state. Regards, Sagar

Hi Sagar, You need to build SBL for prod mode and then try. In dev mode SBL will enable all cores and power will be high. Regards, Rishabh

Hi Rishabh, Is PWRSTCTRL register is enough to put core in off state? Regards, Sagar

Hi, One reason not transition to OFF can be clocks still running. PD DSS encomapasses BB2D, DSS, HDMI, and HDMI_PHY. All these must be disabled from MODULEMODE and functional clocks stopped prior to issue PD collapse. Regards, Stan

Hi Sagar, It's not only about PWRSTCTRL register. I strong recommend that you run using SBL as suggested first. Regards, Rishabh

Hi Sagar, Did you see any different power numbers with TI SBL? Regards, Rishabh

Hi, I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Rishabh

Ticket Name: TDA2SX: nptrs = backtrace(buffer, BT_BUF_SIZE); returned nptrs is 0;

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 HI. backtrace returns 0, which is the same source code. I work in tda4 Linux x86 linux. Can return stack calls. tda2 Linux backtrace returns 0 tad2x linux : compile: gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-gcc -rdynamic call_stack.c -o progtda2 run: ./ progtda2 3 backtrace() returned 0 addresses tad4x: gcc-arm-9.2-2019.12-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-gcc -rdynamic call_stack.c -o prog run: root@j7-evm:~# ./prog 3 backtrace() returned 8 addresses ./prog(myfunc3+0x18) [0x400c04] ./prog() [0x400ca8] ./prog(myfunc+0x2c) [0x400ce0] ./prog(myfunc+0x24) [0x400cd8] ./prog(myfunc+0x24) [0x400cd8] ./prog(main+0x60) [0x400d4c] /lib/libc.so.6(__libc_start_main+0xe4) [0xffff9b890fac] ./prog() [0x400b2c] root@j7-evm:~# ./prog 3 backtrace() returned 8 addresses ./prog(myfunc3+0x18) [0x400c04] ./prog() [0x400ca8] ./prog(myfunc+0x2c) [0x400ce0] ./prog(myfunc+0x24) [0x400cd8] ./prog(myfunc+0x24) [0x400cd8] ./prog(main+0x60) [0x400d4c] /lib/libc.so.6(__libc_start_main+0xe4) [0xffffb6510fac] ./prog() [0x400b2c] Why does tda2 Linux run without stack call information? call_stack.c #include <execinfo.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>

#define BT_BUF_SIZE 100

void
myfunc3(void)
{
   int j, nptrs;
   void *buffer[BT_BUF_SIZE];
   char **strings;

   nptrs = backtrace(buffer, BT_BUF_SIZE);
   printf("backtrace() returned %d addresses\n", nptrs);

   /* The call backtrace_symbols_fd(buffer, nptrs, STDOUT_FILENO)
	  would produce similar output to the following: */

   strings = backtrace_symbols(buffer, nptrs);
   if (strings == NULL) {
	   perror("backtrace_symbols");
	   exit(EXIT_FAILURE);
   }

   for (j = 0; j < nptrs; j++)
	   printf("%s\n", strings[j]);
		   free(strings);
}

static void   /* "static" means don't export the symbol... */
myfunc2(void)
{
   myfunc3();
}

void
myfunc(int ncalls)
{
   if (ncalls > 1)
	   myfunc(ncalls - 1);
   else
	   myfunc2();
}

int
main(int argc, char *argv[])
{
   if (argc != 2) {
	   fprintf(stderr, "%s num-calls\n", argv[0]);
   }

   myfunc(atoi(argv[1]));
   exit(EXIT_SUCCESS);
}

Hello, This is probably generic for arm32 and not specific to TDA2. Can you check if this works: gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-g++ -g -rdynamic -funwind-tables -g call_stack.c -o prog Regards Hemant

Hello Hemant Thank you for your reply. The problem has been solved. Regards gj

Ticket Name: Linux/TDA2: a15 and c66 optimization which is faster for algorithm

Part Number: TDA2 Tool/software: Linux The same algorithm was optimized in A15 (NEON multithreading) and C66 (data DMA to L2 and Instruction Optimization) respectively. The result is obviously fast on A15. Is this normal? C66 should be specialized in making algorithms faster.

Hi Shuai, can you check this answer by Jesse for a list of documents related to DSP optimization and see if you can improve the performance of your DSP algorithm: e2e.ti.com/.../2371691 Regards, Yordan

Ticket Name: Linux/TDA2EVM5777: Self converted JDetNet model doesn't show same FPS with pre-installed JDetNet model

Part Number: TDA2EVM5777 Tool/software: Linux Hi, I downloaded JDetNet model from github and converted that model. In TIDL OD usecase, the installed JDetNet model that is contained in Vision SDK showed about 20 FPS. However, the converted JDetNet model shows about 10 FPS and file size was different. Moreover, the detected box of vehicle was pink color. The color of vehicle was green when is tested with original model. I also changed objectDraw link as related post says. The path of downloaded deploy.prototxt is 'ti_dl\test\testvecs\config\caffe-jacinto-models\trained\object_detection\voc0712\JDetNet\ssd768x320_ds_PSP_dsFac_32_hdDS8_0\test_quantize' and the name of pretrained model is voc0712_ssdJacintoNetV2_iter_120000.caffemodel. Is it normal situation? Regards, Yoo

Hi Yoo, Did you update the below parameters in the “deploy.prototxt” as indicated in the original thread keep_top_k: 20 confidence_threshold: 0.15 Thanks, Praveen

Hi Praveen, Yes, i did it. I already did all things that were refered in original question. (https://e2e.ti.com/support/processors/f/791/t/689617) Is the jetnet model that is provided when i install the vision sdk from the jdetnet model which is opened in caffe-jacinto git repo? Regards, Yoo

Hi Yoo, The jdetnet model that is provided when install the vision sdk is not same as one in the caffe-jacinto git repo. The jdetnet comes with VSDK had only 4 classes and the one in caffe-jacinto had 21 classes. Thanks, Praveen

Hi Praveen, Thanks for your useful information. I got a one more question about whether you used any optimization method in training JDetNet model that is provided in vision sdk. I used tidl_import_JDetNet.txt file that is provided in vision sdk. However, as i say above post, the FPS was slower 2 times when i converted JDetNet caffe model from git repo (provided JDetNet 20 FPS, self converted JDetNet 10 FPS). Is that caused only because of difference of number of classes? Regards, Yoo

Any updates here? I also wonder whether i can get deploy.prototxt and recipe txt file of provided JDetNet. Regards, Yoo

Hi, Yes, the degradation could be because of difference of number of classes. I am not sure that I can share that publicly here, but only difference is if had four classes. Thanks, Praven

Ticket Name: TDA2EVM5777: How mflash do load sbl image and appimage into qspi ?

Part Number: TDA2EVM5777 Hello TI expert, reference information: PROCESSOR_SDK_VISION_03_07_00_00 VAYU XC5777X EVM BOARD minicom setting and running results (VA! is present, not AL!): I got load sbl image and app image into QSPI flash with mflash utility ,as below. and put the board in qspi boot mode and restart it to boot the sbl and AppImage from flash. But target board is not work. but sbl is not working. please advising. user@ubuntu:/home/data1/tda2-eye-detection/ti_components/drivers/pdk_01_10_03_07/packages/ti/boot/sbl_auto/tools/mflash$ sudo ./mflash_run_config.sh Usage: mflash -M <sbl_mflash> -P <Port Number> -C [optional: to clean the QSPI Flash]-F <fileName> <offset> -F <fileName> <offset> ... [PC] sbl_mflash sbl_mflash_tda2xx-evm [PC] File 0 AppImage_BE [PC] Offset 0 0x80000 [PC] File 1 sbl [PC] Offset 1 0x00 [PC] com /dev/ttyUSB0 [PC] ##########Starting USB/UART Flasing Utility############## [PC] Put UART Boot Mode, make fresh UART connection & restart [PC] Press Enter when done... [PC] Opening serial port successful. [RBL]4 [RBL]90 [RBL]30 [RBL]40 [RBL]40 [RBL]80 [RBL]80 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]4 [RBL]1 [RBL]5 [RBL]1 [RBL]56 [RBL]41 [RBL]7 [RBL]2 [RBL]13 [RBL]2 [RBL]1 [RBL]0 [RBL]12 [RBL]15 [RBL]1 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [PC] Requesting the ASIC ID [RBL]4 [RBL]1 [RBL]5 [RBL]1 [RBL]56 [RBL]41 [RBL]7 [RBL]2 [RBL]13 [RBL]2 [RBL]1 [RBL]0 [RBL]12 [RBL]15 [RBL]1 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]14 [RBL]21 [RBL]1 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [PC] Requesting PERI_REQ mode [PC] Sending SBL_MFLASH filesize. [PC] Size of sbl_mflash = 49660 [PC] Sending SBL_MFLASH... Please wait [PC] File Size = 49660 [PC] # [PC] Transfer Complete. Time = 5.000 [PC] Opening port for sbl_mflash. [PC] Opening serial port successful. [PC] sbl_mflash switch On Request Sent. [TDAxx] Utility mflash will Execute now. [TDAxx] Setting up QSPI [TDAxx] QSPI Spansion 4 bit Device type [TDAxx] MID - 0x1 [TDAxx] DID - 0x18 [TDAxx] !!______TDAxx flashing utility______!!1 [TDAxx] Erasing entire QSPI Flash..This takes 50-60 seconds. 0x000DAxx] Erase Completed!!!2 [PC] Download started[PC] File Size = 49660 [PC] # [PC] Write File Completed. 0x800002e taken to download file = 1.002 [PC] Download started[PC] File Size = 19931332 [PC] #################### [PC] Write File Completed. [PC] Time taken to download file = 282.003 [TDAxx] Exiting. [PC] ##############!!!!mflash shutting down!!!!############# Matt

Hello TI experts, Could you please advise which next step we need to check? Switching sysboot & SW5 as below after loading image into QSPI flash. Console setting and No working image after loading image into QSPI flash, as below Matt

Hello TI experts, I have fixed issue to 'No sbl image running'. A new question is to 'How Appimage does build into big endian' ? Please advising reference document to build in Linux platform,thanks Matt

Hi Matt, Can you please look at the SBL user guide: https://processors.wiki.ti.com/images/b/b7/TDA_SBL_UserGuide.pdf Command is "tiimage.exe 0x40300000 BE SBL.bin SBL.tiimage" Regards, Rishabh

Ticket Name: Does TI have Deep-Learning tools : Pruning, Quantization, Compression ?

Other Parts Discussed in Thread: TDA2 Hi, expert: My customer is asking whether TI has the tools as following? Pruning Quantization (both post-training quantization and quantization aware training) Compression I can find some slides about Quantization in the TIDL training slides. it seems the Quantization is part of TIDL Import tool. Please kindly share your comments. Many thanks.

Hi, We are planning to publish tools for quantization - both post training calibration and quantization aware training. There are also several other training examples that we are including. It is expected to be made available at the following location very soon - hopefully in just a few days: https://git.ti.com/jacinto-ai-devkit/ In each repository at that link, click on the "about" tab to read the documentation for that repository. Also, here is a collection of the e2e queries related to jacinto-ai-devkit: https://e2e.ti.com/support/j721e/f/1026/tags/jacinto_2D00_ai_2D00_devkit When you post a question, you can include: jacinto-ai-devkit in the tags as you create the query, for a faster response. Best regards, Manu.

Hi, Manu: Many thanks for the information regarding quantization tool. How about Pruning and Compression? Thanks.

Hi Peter, This devkit can be used to train models for Jacinto7 TDA4x. Jacinto7 TDA4x does not benefit from sparsity. The MAC throughput is quite high anyway. So there is no point in applying pruning of weight coefficients like we used to do for Jacinto6 TDA2/TDA3. We need to add pruning/weight sparsity only if we want to enable training of sparse models for Jacinto6 TDA2/TDA3 through this devkit. We do not want to rule out adding that support - but it is not in the current plan. At present, you can use caffe-jacinto for that.

To explain further, TIDL import tool does a simple calibration. It works reasonably well for common networks, but not so well for networks have Depthwise convolution layers. These is also a plan to address these short comings and implement advanced calibration in TIDL import tool for Jacinto7, but that will take a few months to be released. You can use jacinto-ai-devkit if: - you want to use advanced calibration before it is incorporated in TIDL import tool. - you want to use quantization aware training (which may be slightly better than advanced calibration). I hope it is clear. Let me know if you have further questions.

Hi, We have make pytorch-jacinto-ai-devkit available. Please start by reading here: https://github.com/TexasInstruments/jacinto-ai-devkit It has tools to help with Calibration for Quantization and Quantization Aware Training. Best regards, Manu

Ticket Name: TDA2: How many EMU lines of JTAG port are necessary to be connected to access all the processors?

Part Number: TDA2 Due to space-constraint, I am trying to minimize the JTAG connector size. However, I have some doubts on questions below: 1. Is it enough to connect only JTAG and EMU[1:0] to TDA2SG to access all the processors using 14-pins connections? 2. What will be left non-accessible without EMU[4:2]? 3. Is nSRST a must-have connection?

CTY Lim said: 1. Is it enough to connect only JTAG and EMU[1:0] to TDA2SG to access all the processors using 14-pins connections? Yes, that would get you the regular jtag support. See the below excerpt from TRM chapter: " Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various debug capabilities beyond only JTAG support. Because this device supports the export of processor trace and system trace over the EMU pins, if you want your target to be compatible with XDS products capable of acquiring either trace types, see the following document for guidelines: Emulation and Trace Headers (literature number SPRU655). " CTY Lim said: 2. What will be left non-accessible without EMU[4:2]? See above comment. Also, there will not be many options for concurrent debugging with only 2 emu signals (for triggering or data). See section "Concurrent Debug Modes" in the On-Chip Debug Support chapter of the Technical Reference Manual. CTY Lim said: 3. Is nSRST a must-have connection? No. This is an optional signal that if integrated into your applications power-up-reset circuit may be used to remotely reset the target board from a debugger. See this wiki for details: Thanks, Alex

Hello, I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread gets locked due to time-out). thanks, Alex

Ticket Name: TDA2EG-17: TDA2E How to find the UUID of TDA2x

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2 hi.master Do tda2x and tda4x have UUID? How to find the UUID of TDA2x ?How to get tda4x TDA2x UUID? Is the UUID of each SOC unique？

Hello, Yes, the TDA2x and TDA4x have a unique "DIE ID". This is described in the TRM Table 1-2. DIE_ID. Regards, Kyle

Hello, How to read tda4x/tda2x TDA2x DIE ID in linux?

Hi, devmem2 0x4AE0C200 w Should give you the die-id for tda2.in Linux. As suggested by Kyle refer to the section for the physical address and use devmem2 tool in Linux to read physical address. Best Regards, Keerthy

Ticket Name: TDA2EX17EVM: OpenVX Support on TDA2EX17x17

Part Number: TDA2EX17EVM Dear Sir: We are using PSDK VISION 03_08_00_00 on TDA2EX17x17EVM. The OpenVX support on it is v1.1. My question is that does TI has any plan to upgrade the OpenVX support from 1.1 to 1.2 or even 1.3? Regards, /ckhsu

Hello, As you said, we are currently supporting OpenVX 1.1 on our J6 platforms. Is there a feature that you need from the OpenVX 1.2 or 1.3 specifications? Regards, Lucas

Hi Lucas: In OpenVX 1.2 or 1.3, there is hough line detection api but not in 1.1. This is what we want. We have normal houghline detection algorithm in C/C++ but we need a TI optimal solution in C66 to see how fast we can reach in C66 in comparing to our C implementation. Regards, /ckhsu

Hello, As of now, we do not have any plans to implement the hough line detection api in TIOVX. Regards, Lucas

Hi Lucas: Thank you for the information. Regards, /ckhsu

Ticket Name: Linux/TDA2: Performance comparison between A15 and C66

Part Number: TDA2 Tool/software: Linux i am useing tda2 evm ？ （sample_app\src\hlos\chains_common\chains_main.c ） in the main i move the usecase , read a img and run a cnn. There is no multithreading in CNN. use time is 1667ms. then i put the same cnn in (sample_app\src\rtos\alg_plugins\framecopy) done by dsp1 . buf cnn use is p_FRMem = (MVoid*)Utils_memAlloc(UTILS_HEAPID_DDR_CACHED_SR, FR_MEM_BUF_SIZE, 32); this time use time is 6378ms ! A15 1667ms. and c66 6378ms. Is the result reasonable? Why C66 is so slow？how can it fast ? thanks! shuai

Hi, DSP clock is slow compared to A15. You can check the same by below command omapconf show opp Across what code are you measuring time. Check the time only to run CNN not for reading the image. Regards, Anuj

Hi Anuj yes measuring time only the cnn part! clock is slow but I don't think the gap is so big. shuai

Hi, It could be possible due to some other thread is running on DSP at the same time when you run cnn and due to task scheduling, time is increased. Regards, Anuj

Ticket Name: TDA2: Questions in radarDspProcessCfar_priv.c

Part Number: TDA2 Dear respecful TI experts, I have a couple of questions regarding software logics in radarDspProcessCfar_priv.c which is included in PROCESSOR_SDK_RADAR_03_04_00_00. - Question #1 In the function named "AlgorithmFxn_RadarDspCfar_caall", the loop variable "i" is converted into i_doppler depending on whether "i" is odd/even. Could you tell me what is the purpose of this conversion or the purpose of the "i_doppler". I think there a bug which is related to i_doppler, but to get to the bottom of it, I need to detailed purpose of the variable. -Question #2 In the function named "AlgorithmFxn_RadarDspCfar_caall", below codes which are performed when pCfarCreateParams->enableSecondPassSearch == 0 seem not correct the stop condition in the second for loop should be corrected, otherwise all the variables in the for loop will be overflowed. please let me know if there is what I missed. if (tempDetected < pCfarCreateParams->maxNumDetObj) { for (j = 0; j < (Int32)tempDetected; j++) { cfarOut->noise[detected] = tempNoise[j]; cfarOut->rangeInd[detected] = tempRangeIndex[j]; cfarOut->dopplerInd[detected++] = i_doppler; } } else { for (j = 0; j < pCfarCreateParams->maxNumDetObj; j++) { cfarOut->noise[detected] = tempNoise[j]; cfarOut->rangeInd[detected] = tempRangeIndex[j]; cfarOut->dopplerInd[detected++] = i_doppler; } break; }

Hi, Apologies for the delayed response on this one. The i_doppler is used to perform a shift on the Doppler dimension to incorporate positive and negative relative velocties. The data is arranged after FFT and energy sum in Doppler Dim x Range Dim (The x-axis is Dopper and y-axis is Range.). The doppler bins are however 0, 1, 2, 3, and so on till the N doppler - 1. The i_doppler will loop as below assuming N doppler is 64. 0, 63, 1, 62, and so on till 31, 32 The first pass search in along the range dimension. The second pass in on the doppler dimension. During the second pass search the i_doppler is used to find the window in the positive relative velocity and negative relative velocity doppler bins for a particular detected range cell to find the noise floor in the doppler dimension and check if the energy at the first pass detected cell is indeed greater than the noise floor in the doppler direction. I am not sure I follow your second comment regarding the loops. The expectation is that if the tempDetected is less than max array size given by pCfarCreateParams->maxNumDetObj then only tempDetected number of objects is copied to the array. If not then the full array is populated till the maximum allowed objects given by pCfarCreateParams->maxNumDetObj. Thanks and Regards, Piyali

Ticket Name: DRA756: dra756 custom board, Vision SDK 3.7, video capture

Part Number: DRA756 Other Parts Discussed in Thread: TDA2 Hi, i have been debuging the single camera usecase. hardware structure is that: ar0231 > ap0202 > ds90ub933 > ds90ub934 > tda2(ipu2) > HDMI 1920*1080. everything goes well but displaying. The video always displayed as follows, i used the usecase "1: 1CH VIP capture + SGX Copy + DISPLAY": I have no idea to solve this problem, could you guys give me some suggestiones? Thanks a lot.

I solved this problem, polarity of HSYNC and VSYNC.

Ticket Name: Linux/TDA2: HOW debug use gdb

Part Number: TDA2 Tool/software: Linux i have some problem in my code [ 89.228570] Alignment trap: not handling instruction edc37a00 at [<00050702>] [ 89.235743] Unhandled fault: alignment exception (0x811) at 0x00000249 [ 89.242342] pgd = edbd0000 [ 89.245148] [00000249] *pgd=be17a831 ./start: line 3: 857 Bus error (core dumped) ./sample_app.out i want to know where is the problem , how to run gdb debug? thanks!

Hi, GDB binary is already available with VSDK 3.5 file system. You can run this and debug in a similar way as gdb is used to debug any linux application. Regards, Anuj

Hi: Anuj what about VSDK3.4? Could you tell me the path of GDB binary ! shuai

Hi, Can you check in /usr/bin inside the file system. Regards, Anuj

Hi, Is the issue resolved? Regards, Anuj

Ticket Name: RTOS/TDA2EVM5777: What other RTOS can be used in TDA2x cores?

Part Number: TDA2EVM5777 Tool/software: TI-RTOS Hello everyone, I have a doubt about the types of RTOS that can be used in TDA2x cores, I refer to the ARMs, I know that the default OS is TI-RTOS that provide TI, but I don´t very sure if this OS is safety and recommended for automotive applications. Someone know if is possible to port some OS with certification in automotive?, because I see in TDAx ADAS SoCs - Support & training (http://www.ti.com/processors/automotive-processors/tdax-adas-socs/support.html ) a part who mention Elektrobit, is possible to have a OS safety EB in some of the cores of this DSP. I already know that this number part have multiple cores, and I'am asking for a port of some safety OS for one of them. I mean, in some of the Dual ARM M4 or ARM A15. Regards,

Hi, What is the end equipment you are looking at and what is the safety level for the same? You may want to explore the possibility of using QNX or GHS OS running on A15 for your safety story. Thanks and Regards, Piyali

Mainly I want an OSEK compatible OS, like EB tresos AutoCore OS, I want to know if TI has a port of some operatng system like this.

Hi Moises, Third party such as EB, Vector, KPIT do support TDA2xx/TDA3xx family of devices in their AUTOSAR offering. Regards, Sujith

Thank you, this solve my question. Regards,

Ticket Name: TDA2SX: TIDL OD usecase

Part Number: TDA2SX Hi, I converted SSD based object detection model and output is as expected on PC. However, when I am running this model in TIDL OD usecase, I don't get detected objects at all. I checked the output of the TIDL algorithm link on DSP and I can see that there is no valid bounding boxes detected. I scaled input to fit to expected dimensions of model (300x300), so the input shouldn't be a problem. Is there anything you can suggest me to try to figure out what makes this problem? Regards, Sasa

Hi Sasa, can you go thru this thread and see if you can find something useful: e2e.ti.com/.../689617 Regards, Yordan

Hi, this thread is useful for some understanding of usecase, but as I already discovered that I don't have proper results on the output of tidl link, I hope that someone could tell me what could be making that problem. Results are ok during import, but I can't get the same results with usecase. Do you have any idea what could cause that? Regards, Sasa

Is the input to import and use case same?n If not first try with the same input and make sure that basic integration is right.

Input is same file. What mostly make me wondering is that I am getting good results in stats_tool_out.bin when running full net with eve_test_dl_algo.exe, even this is SSD based model. So, should it work like that in first place?

If the model is working in the import step, Mostly it shall work in target flow also.

Ticket Name: TDA2HA-17: Q: Should the power consumption for TDA2x ES2.0 and ES1.1 be equivalent or 'the same' assuming identical configuration?

Part Number: TDA2HA-17 Question: Should the power consumption for TDA2x ES2.0 and ES1.1 be equivalent or 'the same' assuming identical configuration? Alternatively, should a TI EVM with a TDA2x ES2.0 device have the same or similar power consumption as a TI EVM with a TDA2x ES1.1 device? Alternatively, should a customer target board with a TDA2x ES2.0 device have the same or similar power consumption as a customer target board with a TDA2x ES1.1 device? Does TI have available a spreadsheet that calculates power consumption for a set of used components and IP? Is there a version for TDA2x ES2.0 and TDA ES1.1? Or are they available separately? Many thanks!

Hi Jason, I have forwarded the question to an expert to help. Regards, Yordan

Jason, Yordan, Generally speaking, the power consumption for TDA2x ES2.0 and ES1.1 are the same. There are die to die differences that exist due to normal manufacturing variations. Regards Kyle

Ticket Name: TDA2: Direct connection VIN signal into VIP without isolation?

Part Number: TDA2 1. Can I connect VIN signal directly into VIP without isolation using SN74CBTLV16212GR? Does SN74CBTLV16212GR served any purpose, like isolation from backflow current, other than multiplexer?

In case of TI EVM, this is used as both a mux as well as a driver buffer. Depending on the drive capacity of the sensor/decoder you may have this or not in your board.

Ticket Name: TDA2PXEVM: VisionSDK3.07 usecase DCAN cannot communicate with other CAN device.

Part Number: TDA2PXEVM Hi, I try to use DCAN to communicate with other CAN device in TDA2Px-ACD EVM in VisionSDK3.07. I heard this usecase is for TDA3 but not TDA2Px. So I met some problem. Follow the TDA3 user guide, I compiled DCAN usecase into VisionSDK by setting "DCAN_INCLUDE=yes". But it seems it only run once and send nothing data to the CAN bus, Because my logic analysis do not capture any signal and my CAN device do not receive any data. And then I set ENABLE_B2B_DCAN_TEST to 0U to enable loopback mode. After that it can receive data that it transmit. My CAN device also receive data from TDA2Px. But TDA2Px still cannot receive the data that my CAN device transmit. I've created a topic about how to use DCAN and found some relevant topic https://e2e.ti.com/support/processors/f/791/p/885983/3301649 I created before. https://e2e.ti.com/support/processors/f/791/p/889985/3302997#3302997 A relevant topic he met a same problem Then then I found a important topic. The author said he resolve this problem through Need modify "platform_tda2xx_pad_config.c" setting to modify RX pin of DCAN form AD17 (Wakeup0) to G19(dcan1_rx) if use TDA2x EVM. But I still don't know how to modify because I didn't find this configuration. Perhaps we use the different VisionSDK version and different Board. https://e2e.ti.com/support/processors/f/791/t/726840?tisearch=e2e-sitesearch&keymatch=tda2%25252525252520dcan It seems it's a hardware problem. So could you give me some help ? Regards

Hi Wall-E, To port existing DCAN use-case from TDA3x to TDA2Px, you need to take care of the following: Module and clock enable for the DCAN module, this probably will be same for both the SoCs IO PAD (dcan_xta nd dcan_rx) configurations interrupt configurations I'll check with the colleague on PAD configurations and will get back to you. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi Wall-E, To configure the DCAN_RX pad, you can add your own API in the file 'ti_components\drivers\pdk_xx_xx_xx_xx\packages\ti\drv\stw_lld\platform\src\tda2xx\platform_tda2xx_pad_config.c' and call it in the application OR you can modify the existing one also. Please refer to 'PlatformDCAN1PadConfig' API present in the same file for more details. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Ticket Name: TDA2: Surround view projection on TDA2SX

Part Number: TDA2 Hi team, My customer wants to use most powerful TDA2SX to combine frontcamera with sign/cars/object recognision and surround view application in one block. But they noticed that TDA2SX have no ISS block. The ISS block used to create projection for surround view application. Do we have a way to create surround view projection on TDA2SX?

Hi, ISS block is available only on TDA3x and TDA2Px. But you can use surround view application using the VIP capture. Please use below usecase. vision_sdk\apps\src\rtos\usecases\lvds_vip_sv_standalone Regards, Anuj

Ticket Name: TDA2: DDR DQ signal swapping rules

Part Number: TDA2 In the DDR2/DDR3 interface design, can we swap DQs with in the same byte? is there any rules on this? such as dq0 swapped with dq3 dq2 with dq7, etc Thanks Jianming

Hi, Yes, it is okay to swap DQ bits within the same byte on the TDA2x DDR2/DDR3 interface. The only rule for DQ bit swapping on the TDA2x DDR2/DDR3 interface is that the DQ bits must be routed with their associated strobe (DQS) and mask (DM). (i.e, all signals within a byte of the TDA2x must be routed to the same byte of the DDR2/3 memory). Best regards, Kevin

Ticket Name: TDA2EVM5777: IPU EDMA configuration for slave SPI transfers

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello, Using starterware/PDK and running on a TDA2 we want to have IPU10 configure the EDMA to move data between SPI module 2 and DDR. The TDA will be the SPI slave for the data transfer. Transfers start when the TDA sets a GPIO high. A version of this driver was created for the A15_0, where the A15 configured the EDMA for transfers, and is working OK. Porting it to IPU10 though has not worked. Currently on IPU10 the EDMA and SPI are configured similarly to how they are in A15_0 (where EDMA does work when A15_0 does the configuration). However, when IPU10 sets the GPIO high to initiate the SPI transfer it seems the EDMA isn't moving data. Other than not seeing the SPI data in memory, the EDMA destination address register never shows movement and remains on the initial memory address despite SPI having burst hundreds of bytes. How do you configure the EDMA from IPU10 to move data to and from SPI 2 when SPI is configured as slave? Since this works on A15_0, what are the differences when configuring EDMA and/or SPI on IPU cores instead of A15 core? (SPI was configured same on both cores but the CPU ID and corresponding interrupt xbar instance numbers were changed for EDMA on IPU instead of A15.) Thank you.

Hi, For configuring the EDMA from IPU there are few changes required. 1. The EDMA register space address area starting from (0x4330_0000) is a bit band region from IPU memory map. You need to do the AMMU mapping for this area and use the EDMA register space from mapped address. You can refer the PDK edma example running from IPU1_0. 2. If you are using the EDMA interrupts then you need to update the interrupt configurations. You can refer the edma example for this. 3. You need to make sure that the DMA crossbar configuration is done properly to route the SPI dma event to a dma channel and the same is configured from IPU. Regards, Prasad

Hello Prasad, Thank you for the reply. There were some things we were already doing prior to adding this EDMA SPI driver and so we were already configuring the AMMU through the TI provided function StwUtils_appConfigIPU1DefaultAMMU(). The EDMA interrupts are being used and configured in a similar manner as when configured in A15 where they do work. Is there any difference in their configuration in IPU versus A15? I will be further reviewing the DMA crossbars on IPU. On A15 only the EDMA channel was requested and no explicit crossbar configuration was done. Thank you.

Hi, Which software are you using for the edma configuration? edma3lld or the starterware edma? Regards, Prasad

Ticket Name: XDS560V2 Emulator connection failure

Other Parts Discussed in Thread: TDA2 Our project is developing in Linux environment. We have custom TDA3 board. I have connected Spectrum Digial XDS560V2 STM JTAG Emulator with our custom board. I try to launch debug configuration. I checked the all connection and initialized the gel files. After few minutes i got the following error. Error initializing emulator: (Error -2083 @ 0x0) Unable to communicate with the emulator. Confirm emulator configuration and connections, reset the emulator, and retry the operation. (Emulation package 5.1.73.0)

Hi Jaganathan, Did you try to eliminate the host PC factor? I mean did you try on another PC? Also, the front PC ports are often using cheap wires to the main board and fail to communicate. Rear USBs are always preferred. You can also try with another known good USB cable. Also, do you use known good power supply for the debugger unit? Regards, Stan

Hi Stan, Same XDS560V2 JTAG Emulator is using in TDA2 EVM board. It is working in windows environment. I did test connection. Below are report generated by Code Composer Studio [Start: Spectrum Digital XDS560V2 STM USB Emulator_0] Execute the command: %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity [Result] -----[Print the board config pathname(s)]------------------------------------ /home/gnanaveluj/.ti/ti/0/0/BrdDat/testBoard.dat -----[Print the reset-command software log-file]----------------------------- This utility has selected a 560/2xx-class product. This utility will load the program 'sd560v2u.out'. E_RPCENV_IO_ERROR(-6) No connection: DTC_IO_Open::dtc_conf Download failed for file /home/gnanaveluj/ti/ccsv6/ccs_base/common/uscif/./././././xds560v2.out An error occurred while soft opening the controller. -----[An error has occurred and this utility has aborted]-------------------- This error is generated by TI's USCIF driver or utilities. The value is '-250' (0xffffff06). The title is 'SC_ERR_ECOM_EMUNAME'. The explanation is: An attempt to access the debug probe via USCIF ECOM has failed. [End: Spectrum Digital XDS560V2 STM USB Emulator_0]

Hi, I resolved the issue. My laptop was connected with docking station. So it was not connected. I removed from docking station. Now i can able to connect with the board.

Ticket Name: Linux/TDA2: Can access the camera via v4l2 on TDA2PX

Part Number: TDA2 Tool/software: Linux Hello: we want to porting some demo to TDA2PX which using v4l2 to capture the video, for TDA2Px,using IMI modules (OV10640 Rev E sensor) & LVDS cables to connect camera modules to UB960 application board. can we access the camera by v4l2? if possible, any sample? Thanks!

Hello, We do not support raw cameras from Linux. - Linux CSI driver does not support virtual channel feature - Cannot connect more than one camera via one CSI port using UB960 - Does not have ISS driver for any raw image processing to be done from Linux The M4 based capture model is designed to exercise one set of FPDlink drivers, CSI drivers, ISS drivers, algorithms, etc TI recommends to use the capture from M4 itself. You can get the video to A15 by connecting the capture link to any of the link running on A15 Linux Regards, NIkhil D

Hi: got it and thanks.

Ticket Name: Linux/TDA2EXEVM: Object Detection on DSP

Part Number: TDA2EXEVM Tool/software: Linux Dear Sir: Base on the usecase lvds_vip_single_cam_analytics inside VSDK 03_03_00_00, the Object Detection algorithm running on the DSP always needs the FPCompute output from the EVE processor. Is it possible to run the FPCompute on DSP? Does TI have any plane to move the FPCompute into DSP? If the EVE is necessary, it seems that the OD demo can not run on a DRA71x/72x EVM board Am I correct? Regards, /ckhsu

Yes EVE is necessary for OD demo.

Ticket Name: Linux/TDA2: OV490 VIP input , split Link seems not to work.

Part Number: TDA2 Tool/software: Linux Hi all, The SDK version is PROCESSOR_SDK_VISION_03_00_00_00 . There are 4CH OV10640 capture via OV490 on my TDA2xx board， i tested with lvds_vip_multi_cam_view_sgx_display usecase under linux. The changes as below: 1. change capture settings with 2560 width; 2. add the split link. capture -> split ->sync -> sgxfrmcpy -> display and it can display 2 camera video. I changed the sgxFrmcpyLink_drv.c with texProp.width * 2 (line 321:) ,the output video as below; it seems split link doesnot work? In sgxFrmcpyLink_drv.c, texYuv[] = System_eglGetTexYuv(&pObj->eglObj, &texProp, pVideoFrame->dmaFd[0]); I note that It used the dma transfer. Query: How can I split the video correctly?

Hi John, Let us check it out in the release. Rgds, Brijesh

Hi John, Can you please just tell us what are you trying to achieve with split link or what problem are you trying to solve with split link ? Regards Surya

Ticket Name: PROCESSOR-SDK-DRA8X-TDA4X: How can I download TDA4 processor SDK?

Part Number: PROCESSOR-SDK-DRA8X-TDA4X Dear Sir, I am a software manager working in Longhorn at Shenzhen of China ,We has implemented 360 surround view with TDA2S, but some scenes are not very good, such as APS automatic parking，so we want to using TDA4 to doing APS or AVP. I found that TI has released TDA4 processor SDK, but it can not be download, TI website tips that customer need to fill out the form for downloading。 Could you tell me how to fill form? Best Regards, Bob Deng qibao.deng@long-horn.com

Hi Bob, please check here: you can select Processor SDK RTOS or Linux for TDA4 device. regards, Yortdan

Hi Yortdan, Thanks for your reply! I have another question is that, what is difference between Processor SDK RTOS and Processor SDK Linux? Whether do we need download both version to build surround view park assist system? Regards, Bob Deng

Hello Bob, Both the PSDK RTOS and PSDK Linux are needed for the surround view application. The PSDK Linux is used in this demo because the A72 core is running Linux whereas all the remote cores are running RTOS. Therefore both of these are needed. Regards, Lucas

Ticket Name: Linux/TDA2: Linux/TDA2 to Jetson TX2 PCIe communication

Part Number: TDA2 Tool/software: Linux Hi, I have been doing for communicating Jetson TX2 and Ti TDA2X via PICe in Linux platform. I tried to workout configuring TDA2X as end point and Jetson TX2 and Host. Both have configured properly but during enumeration pci device is not detected at host side. Is there any option to configure TDA2x as generic end point device in linux?

Hi Sreerag, can you check this wiki and see if you can find something useful: processors.wiki.ti.com/.../Linux_Core_PCIe_EP_User's_Guide Regards, Yordan

Hi Yordan, I have gone through the same configurations mentioned in the link. I got TDA2X as end point device. But that device is not detected in the Jetson. I am communicating between Jetson and TDA2x.

Hi Sreerag, You may find this thread useful. You may need a modification on your board and apply the patch posted on this thread. e2e.ti.com/.../688574 Regards Shravan

Hi, Is there any option to try the PCI test between two TDA2X boards in RTOS platform?

Hi, We have a simple driver to configure in RC and EP mode present in PDK. Please refer to pdk\packages\ti\csl\example\pcie\write_loopback for more information. The issue pertaining to PCIe communication between Jetson TX2 and TDA2 seems to be resolved. Please create a new thread if you have any further questions. Regards Shravan

Ticket Name: Linux/TDA2: SPI Slave driver Implementation for TDA2x

Part Number: TDA2 Tool/software: Linux Hi, As per my project requirement, I need to configure one McSPI modules as SPI Slave mode for TDA2x. for this, I need SPI Slave driver to communicate with another Master Controller device. I am using Vision SDK 03_04 for this project. As my search or knowledge, i didnot find any SPI Slave driver in this SDK. Is any driver available in this SDK for TDA2x? Please help me to get any similar spi slave driver for TDA2x which is capable to communicate with master. Please provide any link/code/information regarding this. Thanks, Anand Kumar

Hi Anand, McSPI driver is here: PROCESSOR_SDK_VISION_03_05_00_00\ti_components\drivers\pdk_01_10_01_06\packages\ti\drv\bsp_lld\mcspi Regards, Rishabh

Hi Rishabh, Thanks for this link. I will go through and will check it will solve my problem or not. could you Please help me to find document/forum which related to integrate this driver and application guide in Vision SDK Doc. Thanks, Anand Kumar

Hi Anand, You can search for Utils_mcspiInit in Vision SDK and see how it is used. Regards, Rishabh

Hi Rishabh, Thanks for support. Thanks, Anand Kumar

Ticket Name: TDA2: VIP & CSI2

Part Number: TDA2 HI As the TRM shown, there are VIP modules & CAL-CSI2 module. Does the VIP modules & CSI2 module could work simultaneously? Thx.

Hi, First, TDA2x does not have CSI2 input. TDA3x, TDA2Px and TDA2Ex support CSI2 input. On these devices, yes VIP and CSI2 input can run simultaneously. Rgds, Brijesh

Ticket Name: Linux/TDA2: OpenCV, OpenCL and openCX

Part Number: TDA2 Tool/software: Linux Dear Officer, I am working on TDA2x with VSDK3.4. and notice there are OpenCV, OpenCL and OpenCX in VSDK: 1. There is pre-build openCV libs in folder \ti_components\open_compute\opencv\opencv-3.1.0\libs_linux ( I am more interested on Linux version) 2. Make option : tda2xx_evm_linux_opencl 3. Make option: tda2xx_evm_linux_opencx What is the relationship in TI for these 3 options? My target is trying to use the pre-build Linux OpenCV lib, Should I enable to OpenCX or OpenCL build option to get OpenCV? (There is no make option for OpenCV). Thanks and best regards He Wei

Hi He Wei, 1. There is pre-build openCV libs in folder \ti_components\open_compute\opencv\opencv-3.1.0\libs_linux ( I am more interested on Linux version) [Surya] Yes, use this pre-built openCV libs while building linux side openCV applications 2. Make option : tda2xx_evm_linux_opencl [Surya] MAKECOFIG=tda2xx_evm_linux_opencl will build OpenCL applications only 3. Make option: tda2xx_evm_linux_opencx [Surya] MAKECOFIG=tda2xx_evm_linux_opencx will build both OpenCV & OpenCL applications, Since OpenCV has some dependency over openCL, so no separate make option for OpenCV You should enable OpenCX option to get OpenCV Regards Surya

Ticket Name: Linux/TDA2: cores parallel

Part Number: TDA2 Other Parts Discussed in Thread: TDA3MA Tool/software: Linux The development board I use now is TDA2X, and SDK uses SDK_VISION_03_02_00_00. But we're going to use TDA3MA, which has two C66 and one EVE . I have four CNNs to implement, and my idea is follow m4 link capture + dsp1 a c66 link (1cnn) +dsp2 a c66 link (1cnn) +eve1 a eve link (2cnn) +m4 link display i think like this 3 cores parallel but there processing on diffrent frame. right? can i do like this ?

Yes. You can do this. Provided, your CNN compute requirements are with in the MACs bugdets of DSP and EVE clocks. Please refer the TIDl datasheet for DSP and EVE CNN layer level performances.

Ticket Name: OpenVX object detection on TDA2XX

I am trying to make application to recognize traffic signs using OpenVX. Can someone recomend me what functions should I use to recognize object (for example square,triangle, circle) or even help me with some object detection examples so i can modify it? I am using VIsion SDK 03_03_00_00 on TDA2XX chip and I started from your example for Harris corners detection.

Hi, Did you check our TIDL based object detection use cases @ /vision_sdk/apps/src/rtos/usecases/tidl/ in the latest Vision SDK https://www.ti.com/tool/PROCESSOR-SDK-TDAX Thanks, Praveen

I did, but as I can see in latest Vision SDK is used network (i do not have network access on my TDA2XX) and there are none of OpenVX node functions (for example vxColorConvertNode, vxExtractNode...) I need to make OpenVX program that recognize traffic signs so I would like first to recognize some shapes and than to adapt it to recognize signs.

There are multiple ways to recognize shapes and there are enough literature available online. Two main approaches are, 1. Computer vision based 2. Deep learning based For either one of them you will have use some of the existing kernels in OpenVx or write your custom kernel. Steps to try are, Narrow down on the approach how you want to recognize a shape? Deep learning approach provides better accuracy these days. Train a network to identify the shapes using TensorFlow/PyTorch/Caffe. Use the TIDL library to import a trained model. Try it standalone on EVM. Then switch to an OpenVx based application which uses TIDL. Regards, Shyam

Ticket Name: TDA2SX: How to use VIP BT1120 on TDA2?

Other Parts Discussed in Thread: TDA2SX art Number: TDA2SX Hi, My requirement is 1920*1080P、30fps、3ch(VIP2 S2 A、VIP3 S1 A、VIP3 S2 A) SDK : PROCESSOR_SDK_VISION_03_05_00_00 usecase : Chains_lvdsVipMultiCam_Display decoder : techpoint TP2824 * 2 Q1: How to set in the orange box in the second picture below For example, if I use 25fps, do I need to modify the fps parameter? Q2: I have seen channel 2(vout 6) but other channels only have black screens First, I modified the PINMUX and Capture parameters as shown below: C:\PROCESSOR_SDK_VISION_03_05_00_00\ti_components\drivers\pdk_01_10_01_06\packages\ti\drv\vps\src\boards\src\bsp_boardTda2xx.c And then i modify the VidSensor_CreateParams below: C:\PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\apps\src\rtos\video_sensor\src\vid_sensor.c vcaptureSrc = CHAINS_CAPTURE_SRC_OV10635 vChainsCommon_MultiCam_StartCaptureDevice v=> vChainsCommon_SetVidSensorPrms v=> vChainsCommon_SetVidSensorMultiOV10635Prms C:\PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\apps\src\rtos\usecases\common\chains_common_vision.c 8 bits changed to 16 bits have an impact Result Capture link can capture 30 frame

Hi YiTing, From the capture links stats, three channels are already being captured at 30fps rate. Which means, capture is working fine. You need to check your rest of the data flow and see where other 2 channels are dropped. Regards, Brijesh

Hi Brijesh, Thanks for your reply. To ensure the chain simple that I only use capture link to display link. I use funtion"chains_lvdsVipMultiCam_Display_SwitchDisplayChannel" to check that the rest of the data flow is all black screens. In multi-channel capture, if I can capture one channel, other channels are also set correctly? I just want to confirm whether bt1120 is set correctly. Regards, YiTing

Hi YiTing, Atleast from the stats, it looks like all channels are getting captured at 30fps. Can you try saving a frame from each channel and analyze it offline? Also Can you please check VIP size register to see if VIP detects correct size for each channel? Rgds, Brijesh

Hi Brijesh, I don’t understand what the analysis frame means Do you need me to analyze the pixels in the display link frame? I will check VIP size register within two days Regards, YiTing

Hi YiTing, I wanted you to save a captured frame and view it offline to see if the captured frame is correct and is not black.. Regards, Brijesh

Hi Brijesh, How to save frame in the CAPTURELINK, do I need to add Link like null link ?

Hi YiTing, One way is, you could put break-point on CaptureLink_drvProcessData API and then run the code upto line 758. Once you get pFrame (Fvid2_Frame), you could get the buffer address from pFrame->addr[0][0] and from that address, you could dump the memory from CCS memory window. Rgds, Brijesh

Hi Brijesh I will tyr the break-point tomorrow. Regards, YiTing

Ticket Name: RTOS/TDA2: Core clock initialization

Part Number: TDA2 Tool/software: TI-RTOS Hi, In VSDK3.3 example program "apps", I can not find clock initialization. In BIOS configuration script BIOS.cpuFreq is set to 750MHz, and in the C files I can only find program reads this configuration(by call BIOS_getCpuFreq), but program setting PRCM registers can not be found. So how is each core clock initialized? Thanks&regards.

Hi Yang, PRCM is configured by SBL using PM HAL library APIs. You need to see PROCESSOR_SDK_VISION_03_03_00_00\ti_components\drivers\pdk_01_09_00_17\packages\ti\boot\sbl_auto\sbl_app\src\tda2xx\sbl_tda2xx_main.c and see DPLL calls. Regards, Rishabh

Hi Rishabh, OK. So BIOS.cpuFreq in BIOS configuration script is only used to tell OS that the core clock frequency configured by SBL, am I right?

Hi Yang, BIOS.cpuFreq in BIOS configuration script is used to tell the particular CPU's frequency to the OS. It can be configured by anyone, in this case it is configured by SBL. Regards, Rishabh

Hi Rishabh, OK. Thank you!

Hi Yang, I am closing the thread as issue has been resolved. Regards, Rishabh

Ticket Name: How to boot TDA2 from eMMC whether SD card is inserted or not?

Other Parts Discussed in Thread: TDA2 Hi, I boot TDA2 EVM from eMMC. In file "uenv-emmc.txt", I have to define "root". But something make me confused. If SD card is inserted while booting, it will be defined as /dev/mmcblk0 and eMMC will be defined as /dev/mmcblk1. If SD card is not inserted while booting, eMMC will be defined as /dev/mmcblk0. How to define "root" if I want to boot from eMMC whether SD card is inserted or not? Or I can fix eMMC as /dev/mmcblk0? And how to do it? Thanks, Kevin Tsai

Hi Kevin, I have forwarded your question to VisionSDK expert. Regards, Yordan

Kevin Please provide the details of kernel release version you are using. In linux kernel, eMMC is enumarated as the mmcblk0 and SD card as mmcblk1. Regards Ravi

Hi Ravi, Following is my Linux kernel version: Linux dra7xx-evm 3.14.63-00013-gcb5f01e-dirty #11 SMP PREEMPT Wed Mar 15 11:40:54 CST 2017 armv7l GNU/Linux BTW, where can I verify the enumaration of eMMC? Thanks, Kevin

Kevin The mmcblk0 or mmcblk1 depends on order in which the devices are enumerated and valid device found. Another option is use UUID (Universally unique identifier), refer to TI-release, Check u-boot scripts, environment variables args_mmc, which setups the UUID for specific mmc boot partition. # part uuid mmc 0:2 uuid # run args_mmc # pri boot_args Regards Ravi

Ticket Name: RTOS/TDA2: About reading XML file

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir We used VisionSDk RTOS version for development on TDA2. Do you know how to read xml file by using application program ? thanks BR Yimin

Hi, Vision SDK support normal file read or write operation and you can open any file using that. Please check the below file for the supported apis vision_sdk\links_fw\src\rtos\utils_common\src\file_api.c Regards, Anuj

Ticket Name: Compiler/TDA2PXEVM: TDA2PX DCAN configuration

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi TI team, I am trying to send and receive CAN data wit DCAN module but there is some issues I am facing. Vision sdk : PROCESSOR_SDK_VISION_03_07_00_00(BIOS) Hardware : TDA2PX-ACD EVM customer board. I have set 'DCAN_INCLUDE=yes' in file 'PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\apps\configs\tda2px_evm_bios_all\cfg.mk' and compiled. I also changed the pinmux refer to this link https://e2e.ti.com/support/processors/f/791/t/893425 ,we can find those register value as below information and I tried two cases to confirm DCAN state: 1.#define ENABLE_B2B_DCAN_TEST (1U) in file "PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\apps\src\rtos\modules\dcan\system_dcan.c" I can not find any CAN data TDA send to bus and we failed to send CAN data to TDA , register value as below: " [HOST ] 71.383639 s: CTRL_CORE_PAD_DCAN1_TX Reg: 60000 [HOST ] 71.383639 s: CTRL_CORE_PAD_DCAN1_RX Reg: 60000 [HOST ] 71.383639 s: CM_WKUPAON_DCAN1_CLKCTRL Reg: 2 [HOST ] 71.383669 s: DCAN_CTL Reg: 21420 [HOST ] 71.383669 s: DCAN_ES Reg: 7 [HOST ] 71.383669 s: DCAN_TEST Reg: 0 [HOST ] 71.383700 s: GPIO1 Reg: 50602001 [HOST ] 71.383700 s: CTRL_CORE_CONTROL_SPARE_RW Reg: 0 " 2.#define ENABLE_B2B_DCAN_TEST (0U) in file "PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\apps\src\rtos\modules\dcan\system_dcan.c" I can receive CAN message followed TDA configuration but can not send CAN data to TDA. " [HOST ] 11.385408 s: CTRL_CORE_PAD_DCAN1_TX Reg: 60000 [HOST ] 11.385408 s: CTRL_CORE_PAD_DCAN1_RX Reg: 60000 [HOST ] 11.385408 s: CM_WKUPAON_DCAN1_CLKCTRL Reg: 2 [HOST ] 11.385438 s: DCAN_CTL Reg: 214A0 [HOST ] 11.385438 s: DCAN_ES Reg: 8 [HOST ] 11.385438 s: DCAN_TEST Reg: 100 [HOST ] 11.385469 s: GPIO1 Reg: 50602001 [HOST ] 11.385469 s: CTRL_CORE_CONTROL_SPARE_RW Reg: 0 " according above two cases , I think TX pin configuration is done and RX pin looks not good , but I can not find where is the root cause . I am not sure above modification are sufficient. could you please help me to look into this issue and give me a bit of advice ? by the way , I tested those two cased on develop board which from TI and it shown me same issue. Thanks a lot. Best Regards. Lan.

Hi, Can you please set '#define ENABLE_B2B_DCAN_TEST (1U) ' and send a message from TDA? Once the message is sent (successful/unsuccessful), please send me the DCAN register dump. While doing the above, please make sure that solution from 'https://e2e.ti.com/support/processors/f/791/t/893425' is applied. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi Vivek, Thanks for your reply. We updated out soc to TDA4 and stopped developing on TDA2. anyway , thanks for your reply. Best regards. Lan.

Ticket Name: Linux/TDA2: TDA2xx Compile Opencl usecase

Part Number: TDA2 Tool/software: Linux when i compile opencl usecase ,There is a mistake as follows: Compiling OpenCL file copy.cl >> WARNING: invalid compiler option --bc_file=copy.bc (ignored) "/home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/../ti_components/os_tools/linux/targetfs/usr/share/ti/opencl/dsp.syms", line 9: error #10022-D: invalid option: --single_data_segment "/home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/../ti_components/os_tools/linux/targetfs/usr/share/ti/opencl/dsp.syms", line 10: error #10022-D: invalid option: --no_entry_point warning #10247-D: creating output section ".stack" without a SECTIONS specification warning #10210-D: creating ".stack" section with default size of 0x400; use the -stack option to change the default size undefined first referenced symbol in file --------- ---------------- main /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/ti_components/cg_tools/linux/ti-cgt-c6000_8.1.0/lib/rts6600_elf.lib<args_main.obj> error #10234-D: unresolved symbols remain error #10010: errors encountered during linking; "copy.out" not built >> Compilation failure make[7]: *** [copy.dsp_h] Error 255 make[6]: *** [opencl_build] Error 2 make[5]: *** [vision_sdk_linux_demo] Error 2 make[4]: *** [apps] Error 2 make[3]: *** [apps_exe_hlos] Error 2 make[2]: *** [apps_hlos] Error 2 make[1]: *** [apps] Error 2 make: *** [vision_sdk] Error 2 Do anyone know how to do it?

Hi Xie Baojian, What all commands you run till now? Regards Surya

Hi Xie Baojian, If the compilation issue is resolved, Can you close this thread ? Regards Surya

Hi Surya, the issue is resolved, thank you very much. Regards, Xie Baojian

Ticket Name: RTOS/TDA2PXEVM: How to process the data what tda2 receive by yuv422_8B from ub964, but ub964 send data by raw12

Part Number: TDA2PXEVM Tool/software: TI-RTOS my hardware is tda2p + ub964 + Camera module, the Camera module output yuv422_8B data, but it use the raw12 of ub913 and ub 964 to transmit. when i receive the data in tda2p by yuv422_8b, it it not correct. How i should process this thing.

Hi, You could probably work in 10bit mode for UB913 and UB964 and in Ub964 select the 8bit processing in RAW10_8BIT_CTL field. Please note that this field might not be supported in all UB964, so please check your ub964 data sheet. Rgds, Brijesh

Ticket Name: TDA2: Output dimension of argmax layer is same as input layer

Part Number: TDA2 Hi, I am using LeNet model for classification. The final layer is argmax with input of 1x1x1x40. When I import the model, the output of argmax is also 1x1x1x40. I expected it to be 1x1x1x1. And all the values of the argmax layer are zero. Regards, Navinprashath.R.R

Hi Navin, Please check the limitations of ArgMax layer in the section 3.9 (TIDL Limitation) of the user guide. Thanks, Praveen

Hi Praveen, Thanks. Looks like argmax is supported only across the channels. Regards, Navinprashath.R.R

Also for the same network, if I change the numParamBits from 8 to 12 import fails. Any idea why this is happening? Regards, Navinprashath.R.R

Hi Navin, I am not sure, ideally it should work. What kind of failure are you seeing? Thanks, Praveen

Also, can you try with numParamBits = 10 ? Thanks, Praveen

With numParamBits= 10 also, the import module throws error. I get a windows pop up telling eve_test_dl_algo.out.exe has stopped working. The default CIFAR10 example works fine with both 8 and 12 bits. Regards, Navinprashath.R.R

Hi Praveen, Compared to the usual LeNet network, we have two Eltwise Sum layers. Regards, Navinprashath.R.R

The issue your observing may be because of the limitation mentioned in the below thread. Update your network to handle this e2e.ti.com/.../694032

Ticket Name: TDA4VM: Power consumption on TDA4

Part Number: TDA4VM Other Parts Discussed in Thread: INA226, TDA2 Hello, we are analyzing TDA4 SoC as a base for developing new platform. We are wondering are there recommended methods or guides and tools in Processor SDK Automotive we can use to measure power consumption on TDA4? Regards. Uros

Uros, There are series resistors that can be used to measure power on the EVM, however that software is not provided in the SDK. In general, we don't recommend that you measure power directly since it is easy for incorrect conclusions to be drawn. Namely, the power consumption for the SoC will vary with manufacturing process. Instead, we recommend you work with your local FAE to have TI provide worst case power estimate for the SoC that will cover temperature and process variations. Regards, Kyle

Hi Kyle, Will this software be available any time soon? We have interest in being able to measure power consumption our selves, because the custom device we are developing have certain power requirements, and we need to optimize power consumption during development. Having worst case power estimate information is ok at this point, but later the need for more precise power measurement will increase. Regards, Uros

Hi Uros, I will need a week to check on this specific topic and come back to you. Regards Karthik,

Hi Uros, We do not currently have support for measuring power measurement using software. This is going to be scheduled for a future SDK - don't have a date right now. However, if you are need to do this urgently, then you can refer to the INA226 driver that exists on our J6/TDA2 SDKs and use that as a reference to adapt to your needs. Regards Karthik

You can simply add the INA226 devices to the device tree. Use the EVM schematic to find i2c addresses. Then a hwmon interface will appear for each supply which allows you to read back voltage, power, current.

Hi Karthik, Just to be clear, if we decide to use the INA current shunt to measure voltage, are drivers for TDA4 supported and included in Process SDK or do we need to port them from TDA2 Vision SDK? Also, regarding power consumption and load, we noticed that OS gets randomly stuck on TDA4 EVM board after it is active for couple of minutes. Here is the kernel error: [ 61.973359] mmc1: Got data interrupt 0x00000002 even though no data operation was in progress. [ 61.981948] mmc1: sdhci: ============ SDHCI REGISTER DUMP =========== [ 61.988368] mmc1: sdhci: Sys addr: 0x00000008 | Version: 0x00001004 [ 61.994788] mmc1: sdhci: Blk size: 0x00007040 | Blk cnt: 0x00000008 [ 62.001209] mmc1: sdhci: Argument: 0x00000000 | Trn mode: 0x00000010 [ 62.007629] mmc1: sdhci: Present: 0x01f70000 | Host ctl: 0x0000001f [ 62.014050] mmc1: sdhci: Power: 0x0000000f | Blk gap: 0x00000080 [ 62.020471] mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x00000207 [ 62.026892] mmc1: sdhci: Timeout: 0x00000000 | Int stat: 0x00018000 [ 62.033312] mmc1: sdhci: Int enab: 0x03ff008b | Sig enab: 0x03ff008b [ 62.039734] mmc1: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000001 [ 62.046153] mmc1: sdhci: Caps: 0x3fe8c801 | Caps_1: 0x18000407 [ 62.052573] mmc1: sdhci: Cmd: 0x00000c1a | Max curr: 0x00000000 [ 62.058993] mmc1: sdhci: Resp[0]: 0x00000000 | Resp[1]: 0x0077dd7f [ 62.065413] mmc1: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x00000000 [ 62.071834] mmc1: sdhci: Host ctl2: 0x0000000c [ 62.076261] mmc1: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000008c2d70200 [ 62.083375] mmc1: sdhci: ============================================ We have installed active cooler on one of EVM modules and haven't had this problem on that board ever since. Is this power/temperature measurement related issue? Or should i create separate thread on forum for this? Regards, Uros.

Uros, We do know that early samples had some devices that are "hotter" than expected during production. That said, we haven't seen issues with the EVM in a room temp configuration which is their intended use model. Since the EVM is not really comparable to your end system for thermal purposes, we recommend that you build up a thermal model of your system including our SoC thermal model with a mock-up of your heat sink configuration and SoC + system power consumption. That will help you to determine what type of cooling may be necessary for your system. Regards, Kyle

Ticket Name: TDA2: TDA2 availability

Part Number: TDA2 When is the TDA2 range of automotive processors due for release, samples and volume production ?

Hi Mark, there are several TDA2x processors in production, please check here: www.ti.com/.../TDA2 Regards, Yordan

The TI website states 'Refer to TI', 'No stock', 'price not available' against all of the TDA2 processor variants. Am I missing something ?

Mark, The TDA family of processors are targeted specifically for Automotive customers and can be ordered through a TI authorized distributor based on pre-communicated demand forecast and orders covering standard lead-times for these automotive grade processors. Best regards, Joe

Thanks for your feedback Joe. I appreciate the emphasis on the availability of data being limited to credible automotive product suppliers. Is the TDA2 family intended for applications requiring an ASIL rating (in a similar manner to the Hercules family) or is the family more suited to infotainment products for which an ASIL-based safety case is required ? Regards Mark Saunders

'not required' that last sentence should have said. Regards Mark Saunders

The TDAx family is targeted towards Advanced Driver Assistance Systems (ADAS) applications while the DRAx family is targeted at Infotainment/Digital Cockpit applications. While there is certainly some overlap across these two automotive spaces, the TDAx family is the primary solution typically used for ADAS systems, which generally have ASIL ratings associated with them.

Ticket Name: Linux/PROCESSOR-SDK-DRA7X: What is the size limit for MLO ？

Part Number: PROCESSOR-SDK-DRA7X Tool/software: Linux hi first booting image store into internal RAM，MLO is second booting image，u-boot is Third booting image. I want to remove third booting image， MLO needs to do many functions，My question is whether MLO has size limitations?

Hi, What's the expected size of your MLO? There's a total 512KB OCM RAM in most of the devices where the MLO is first downloaded. Check the data manual of your device to know this number. However, please note about 32KB of OCM may be used by ROM at the time of booting. Regards, Somnath

Hi, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Ticket Name: Linux/TDA2EVM5777: About Opencv building issue in VisionSDK 3.2

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hi Sir we used TDA2 platform for development and would like to build opencv function. we can build default tda2xx_evm_linux_opencx use case successfully. But if we set BUILD_OPENCV_SRC=yes, the build procedure fails. My procedure is described below. Download opencv source from git://git.ti.com/opencv/tiopencv.git Install cmake by "apt-get install cmake". make -s opencv ==> fail In /vision_sdk/build/hlos/makerules/linux/build_opencv.mk, the cmake file is not found in the downloaded opencv source. $(CMAKE) -DCMAKE_TOOLCHAIN_FILE=../platforms/linux/arm-gnueabi.toolchain_vsdk.cmake -DBUILD_DOCS:BOOL=OFF -DBUILD_PACKAGE:BOOL=OFF -DBUILD_PERF_TESTS:BOOL=OFF -DBUILD_SHARED_LIBS:BOOL=OFF -DBUILD_TESTS:BOOL=OFF -DBUILD_WITH_DEBUG_INFO:BOOL=ON -DBUILD_opencv_apps:BOOL=OFF -DCMAKE_BUILD_TYPE:STRING=Debug -DCMAKE_VERBOSE_MAKEFILE:BOOL=TRUE -DENABLE_NEON:BOOL=ON -DWITH_1394:BOOL=OFF -DWITH_CUFFT:BOOL=OFF -DWITH_EIGEN:BOOL=OFF -DWITH_FFMPEG:BOOL=OFF -DWITH_GIGEAPI:BOOL=OFF -DWITH_GSTREAMER:BOOL=OFF -DWITH_JASPER:BOOL=OFF -DWITH_JPEG:BOOL=OFF -DWITH_MATLAB:BOOL=OFF -DWITH_OPENCL:BOOL=ON WITH_OPENCLAMDBLAS:BOOL=OFF -DWITH_OPENCLAMDFFT:BOOL=OFF -DWITH_OPENEXR:BOOL=OFF -DWITH_PNG:BOOL=OFF -DWITH_PTHREADS_PF:BOOL=ON -DWITH_PVAPI:BOOL=OFF -DWITH_TIFF:BOOL=OFF -DWITH_WEBP:BOOL=OFF ../ please advise and thanks for your help BR Yimin

HI Yimin, Please use pre-built library of openCV. It will not be possible to support you on how to build it because the openCV support infrastructure is deprecated. Thanks, With Regards, Pramod

Ticket Name: TDA2: EVE : KERNEL_C OPTIMISATION & PIPELINING

Part Number: TDA2 Hi, I am writing a KERNEL_C code. I have tried the optimisations to reduce the cycles. so, want to know: - is their any other method for optimisation apart from 16 SIMD alignment? - can we do pipe-lining in the KERNEL_C? Regards Surbhi

Hi Surbhi, can you check if this thread can be useful: e2e.ti.com/.../2688022 Also you can contact your local TI representative to get access to EVE Programmers Guide (SPRUHC1G.pdf). Regards, Yordan

Ticket Name: TDA2: EVE can not perform simple DMA transfer after executing TIDL

Part Number: TDA2 Hi, When EVE tries to perform the simple 1-D DMA transfer from external memory to IBUFA after executing TIDL library, the simple 1-D DMA transfer does not work. . In our case EVE first runs our simple 1-D DMA transfer and it performs well, then EVE runs TIDL and later EVE run our simple 1-D DMA transfer again and it does not work. (the data in external memory is not actually copied to IBUFA on the completion of the simple 1-D DMA transfer) Our module implemented the simple 1-D DMA transfer by following the source code in eve_sw_01_12_00_00\starterware\examples\edma_simple_eve\src\main.c, which uses register level CSL for edma to setup single 1D -> 1D transfer. However, the TIDL uses DMA_UTILS to perform auto-increment DMA and somehow it nullifies the later our simple 1-D DMA transfer. Even we change our 1-D DMA transfer by not using register level CSL APIs but using DMA_UTILS APIs. our 1-D DMA still did not work after running TIDL. We wonder if there is a universal method to implement our 1-D DMA (moreover, 1D -> 2D, 2D -> 1D DMA) and work well with other coexistent module using DMA such as TIDL? Mark.

Hi Mark, Can you check the status of edmaCC->IPR register after executing TIDL? Regards, Anshu

Hi Mark, We haven't heard from you on this. Is this issue resolved? Regards, Anshu

Hi Mark, We haven't heard back from you on this issue. We are closing this issue, if you still have problems you can reopen it again. Regards, Anshu

Hi Anshu, We try three test cases and two scenarios and get the same interesting result. DMA works well when source and destination are both DRAM, but DMA fails at 2nd time when destination is IBUFA(EVE internal RAM). So the problem could be related to why IBUFA can't be accessed by DMA after executing TIDL. We doubt TIDL does not restore EVE internal buffer switch so that DMA can't not access IBUFA. Our test cases and scenarios are: [test A] use our simple 1D dma to do the test step 1: run our simple 1D DMA. step 2: run TIDL. step 3: run our simple 1D DMA again. [test B] use the example the same as file REL.DMAUTILS.00.08.00.02\dmautils\test\edma_utils_autoincrement_1d_test\src\edma_utils_autoincrement_1d_test.c to do the test step 1: run edma_utils_autoincrement_1d_test. step 2: run TIDL. step 3: run edma_utils_autoincrement_1d_test again. (OK for DMA transfer from DRAM to DRAM. Fail for DMA transfer from DRAM to EVE IBUF_A) [test C]: use the API EDMA_UTILS_memcpy2D() to do the test step 1: run EDMA_UTILS_memcpy2D(). step 2: run TIDL. step 3: run EDMA_UTILS_memcpy2D() again. <scenario 1>: DMA transfer from DRAM to DRAM, for all three tests. DMA transfer OK in step 1. DMA transfer OK in step 3. <scenario 2>: DMA transfer from DRAM to IBUFA, for all three tests. DMA transfer OK in step 1. DMA transfer fails in step 3. (but the return code of DMA function shows no error) Mark.

Hi Mark, As requested earlier can you check the value IPR register before and after executing TIDL just to check if there are any interrupts pending in EDMA. You can see the value of this register using CSL overlay structure for EDMA (CSL_EdmaccRegsOvly->IPR). Also can you mention the version of TIDL which you are using? Regards, Anshu

Hi Anshu, The version of TIDL we used is REL.TIDLSRC.01.00.00.00 Mark.

Mark, Can you read the value (32bits) at the following memory location before and after executing TIDL 0x400A1068 ( This corresponds to IPR register)? Regards, Anshu

Hi Anshu, I use the following code to get the content of IPR register: volatile unsigned int IPR_value; volatile unsigned int *pEDMA_CC_IPR = (volatile unsigned int *) 0x400A1068; IPR_value = *pEDMA_CC_IPR; printf("EDMA_CC_IPR(0x%08x) = 0x%08x \r\n", pEDMA_CC_IPR, IPR_value); And the results are: Before running TIDL: EDMA_CC_IPR(0x400a1068) = 0x00000000 After running TIDL: EDMA_CC_IPR(0x400a1068) = 0x00000000 Mark.

Hi Mark, I dont see any issue which could cause the behavior which you are observing. Can you share you simple DMA code so that we can try it at our end? Regards, Anshu

Hi Anshu, We find out the root cause is not only related to EDMA but also EVE IBUF switch. After switching to correct IBUF view, EDMA can transfer from DRAM to IBUFA correctly in [test B] and [test C]. Mark.

Ticket Name: RTOS/TDA2: TIDL File I/O Usecase

Part Number: TDA2 Tool/software: TI-RTOS Hey, I was able to import the tensorflow mobilenet model. Now I want to use the TIDL File I/O usecase to run the inference on the tda2x. I put the .pb files on the sd card and placed an image (.bng) that should be used for a simple classification in two classes 0,1 for cat or dog. The resulting Out.bin looks as follows. This does not show proper classification in 0,1. What am I missing? Is this usecase able to do this by just changing the net and params file and the config? best regards, nico

Hi, First check that, you are getting correct result (proper classification) while importing. Then you can check on the use case. Thanks, Praveen

what do you mean by "while importing"? I´d like to run the inference in host emulation mode, but I can´t create eve_test_dl_algo.out.exe. When I run the gmake command to build it, it says "nothing to be done for all". Took me a while to get to this point since nowhere in the documentation is any information about the need of TIDLSRC to do this. I now tried it with TIDLSRC, but didn´t work either. Do you have any idea how I can create eve_test_dl_algo.out.exe? best regards, nico

You need to use below command mentioned in section 3.5.2 (Building source in host emulation) in the user guide. gmake CORE=eve TARGET_PLATFORM=PC all Thanks, Praveen

yes I know, that is what I meant above when I said I tried the gmake command, but it says nothing to be done for all.

Okay then can you share screenshot of the build console to check this Thanks, Praveen

Nicolas, Since we haven't heard back from you. I hope yoou could find solution for this. So closing the thread.

Ticket Name: Compiler/TDA2EVM5777: How to enable/use the C++ libraries for the usecases?

Part Number: TDA2EVM5777 Tool/software: TI C/C++ Compiler Hi, I am trying to do the post processing on the tidl_postprocessing link and want to write my own functions on this link. I have replaced the tidl_postproc link from A15 to DSP1 to utilize my DSP. How can I simply add the libraries into the same code and kick start my post processing. Thank you. With best regards, Owais

HI, If you want to write your own function then go ahead and write and build the code. For adding your library please take a reference of below file \vision_sdk\apps\MAKEFILE.MK Regards, Anuj

Hi Anuj, Thank you for your reply. I tried to add the vector library and call the std or other functions in the tild_postproc file but it gives me error. Moreover, the reference you have added, I can find the vlib added into it but still can't find the STL for C++. Can you help me with it. Thank you. With best regards, Owais

Hi, If you want to add for dsp then add something like below DSP_ALG_LIBS += $($(MAKEAPPNAME)_PATH)/src/rtos/alg_plugins/commonutils/lib/commonutils_c66xdsp_$(PROFILE_c66xdsp_1).ae66 And build without using -s option and check while linking the lib is present. Please make sure the library you are adding is compatible with c66x architecture. Regards, Anuj

Hi Anuj, Thank you once again for your quick response. I have added as per your suggestion but I am still having the compilation error.

Hi, These are different error and not related to any library issue. inData_c is declared but you are not using that variable so you are getting these error. Please try to resolve this error by yourself or google it. These generic C query and not related to TI specific. Regards, Anuj

Hi Anuj, These are not errors but are just warnings. The code works fine with these warnings. However, when I add the std function into it, it generates the error which probably either due to the proper linking of the c++ library or may be it is not supported in it. With best regards, Owais

Hi, Is there anyone else can answer this problem. Thank you. With best regards, H.M. Owais

Hi Owais, as Anuj is out of office I will ping other VisionSDK experts to help, they will reply here soon. Regards, Yordan

If you are trying to build C++ file, you can follow the example under ~/vision_sdk/apps/src/rtos/alg_plugins/common/sample.cpp. You can also refer to below document regarding C++ support in C6000 compiler. You can find what's supported and what's not.

Ticket Name: Linux/TDA2: #pragma DATA_SECTION (L2SRAM,"DSP1_L2_SRAM_ADDR");

Part Number: TDA2 Tool/software: Linux i add my algorithm code in (vision_sdk\sample_app\src\rtos\alg_plugins\framecopy\frameCopyAlgoLocalDma.c ) ,after copy do my algorithm. but int BUFFER_SIZE = (1024 * 1024 * 20 * sizeof(char)); failed canot get buffer. another problem is #pragma DATA_SECTION (L2SRAM,"DSP1_L2_SRAM_ADDR"); warning: creating output section "DSP1_L2_SRAM_ADDR" without a SECTIONS specification Does this warning need to be ignored?

Hi, Please refer to the below threads to get more idea about #pragma DATA_SECTION e2e.ti.com/.../277661 e2e.ti.com/.../773554 Regards, Anuj

Hi: Anuj then how about int BUFFER_SIZE = (1024 * 1024 * 20 * sizeof(char)); //3M is OK g_pBuffer = (unsigned char *)malloc(BUFFER_SIZE); i try to get buffer in vision_sdk\sample_app\src\rtos\alg_plugins\framecopy\frameCopyAlgoLocalDma.c Alg_FrameCopyProcess function but failed! cloud you give me some advice? BESTWISHES! shuai

Hi, You are trying to allocate a large memory using malloc which is not correct. Please use Utils_memAlloc() API to allocate large buffers. Regards, Anuj

Hi Anuj in ccs this is my CMD , #pragma DATA_SECTION (L2SRAM,".L2SramSect"); is successful! -stack 0x4000 -heap 0x2000000 MEMORY { L1P_SRAM : origin = 0x00E00000, len = 0x8000 L1D_SRAM : origin = 0x00F00000, len = 0x4000 /* 16 KB SRAM */ L1D_CACHE : origin = 0x00F04000, len = 0x4000 /* 16 KB cache */ // L1D_CACHE : origin = 0x00F00000, len = 0x8000 /* 16 KB cache */ L2_SRAM : origin = 0x00800000, len = 0x48000 /* SARAM in L2, = 256 + 32 - 128 = 160 KB*/ // L2_CACHE : origin = 0x00828000, len = 0x20000 /* Cache for L2, which is configured as 128 KB*/ DSP2_L2_SRAM : origin = 0x40800000, len = 0x48000 SL2_SRAM : origin = 0x5B000000, len = 0x40000 EXT_MEM_CACHE : origin = 0x80000000, len = 0x06000000 /* DSP Used cachable area */ EXT_MEM_heap : origin = 0x86000000, len = 0x02000000 /* DSP Used cachable area */ } SECTIONS { vectors :> EXT_MEM_CACHE .cio :> EXT_MEM_CACHE .bss :> EXT_MEM_CACHE ////usually reserves space for uninitialized variables .text :> EXT_MEM_CACHE //////contains executable code .cinit :> EXT_MEM_CACHE .const :> EXT_MEM_CACHE .far :> EXT_MEM_CACHE .fardata :> EXT_MEM_CACHE /////usually contains initialized data .neardata :> EXT_MEM_CACHE ///////usually contains initialized data .rodata :> EXT_MEM_CACHE .sysmem :> EXT_MEM_CACHE .switch :> EXT_MEM_CACHE .L2SramSect :> L2_SRAM .stack :> L2_SRAM .heap :> EXT_MEM_heap } but in the SDK #pragma DATA_SECTION(L2SRAM, ".bss:taskStackSection") it have some problem ,,follow is the log [HOST] [DSP1 ] 91.979930 s: wordWidth2: DMA: height2 CH (TCC) = 192 (576) [HOST] [DSP1 ] 91.980021 s: L2SRAM: DMA: L2TMP CH (TCC) = a16646e0 (a85.545478] omap-iommu 40d01000.mmu: iommu fault: da 0x20202020 flags 0x0 [ 85.622270] remoteproc1: crash detected in 40800000.dsp: type mmufault [ 85.628923] omap-iommu 40d01000.mmu: 40d01000.mmu: errs:0x00000002 da:0x20202020 pgd:0xed514808 *pgd:px00000000 616c6e0) [ 85.639260] remoteproc1: handling crash #1 in 40800000.dsp (TCC) = 84600000 (84600000) [HOST] [DSP1 ] 92.229488 s: ppu8Plane[0]: DMA: height4 C (TCC) = 8448b000 (576) [HOST] [DSP1 ] 92.229518 s: wordWidth42: DMA: height42 CH (TCC) = 192 (576) [ 85.653811] remoteproc1: recovering 40800000.dsp [ 85.681217] omap_hwmod: timer5: _wait_target_disable failed [ HOST] [HOST ] 92.359635 s: SYSTEM: IPC: [DSP1] Notify recfrom failed (Link has been severed, 67) !!! [HOST] [HOST ] 92.359665 s: SYSTEM: IPC: [DSP1] Notify recvfrom failed (Link has been severed, 67) !!! [HOST] [HOST ] 92.359665 s: SYSTEM: IPC: [DSP1] Notify recvfrom failed (Link has been severed, 67) !!! [HOST] [HOST ] 92.359665 s: SYSTEM: IPC: [DSP1] Notify recvfrom failed (Link has been severed, 67) !!! i dont know what is problem mean! BESTWISHES! SHUAI

Hi Anuj get buf is like this? g_pBuffer=Utils_memAlloc(UTILS_HEAPID_DDR_CACHED_LOCAL,BUFFER_SIZE,32); BESTWISHES shuai

Hi Anuj g_pBuffer=Utils_memAlloc(UTILS_HEAPID_DDR_CACHED_LOCAL,BUFFER_SIZE,32); have ERROR out of memory: handle=0xa1561ab0, size=20971520 BESTWISHES shuai

Hi Shuai, Please try this g_pBuffer=Utils_memAlloc(UTILS_HEAPID_DDR_CACHED_SR,BUFFER_SIZE,32); And in the below line your buffer size is 20M not 3M int BUFFER_SIZE = (1024 * 1024 * 20 * sizeof(char)); //3M is OK Please replace the 20 with 3. Regards, Anuj

Ticket Name: TDA2: Use-case Development for Cascaded Radar Design

Part Number: TDA2 Other Parts Discussed in Thread: AWR1243 Hello, I am trying to understand the fundamental differences between different use-case and develop my own use-case for my application. In the use-case "multi_radar_capture_fft_display," you have used 'ISSCapture' algorithm process to collect CSI-2 data from AWR1243 radar sensor. However, in the use-case "cascade_radar_object_detect", you have used "Capture" algorithm process to collect CSI-2 radar data. What is the fundamental difference between these two processes? Is there any advantage of using one over another? I look forward to your reply. Thank you! Best Regards, Nishant

Hi Nishant, ISSCapture is using CAL driver to capture the data in the underlying link. "Capture" is using VIP driver to capture the data in the underlying link. The choice is based on how the AWR1243 is connected to the TDA (via CSI/CAL or via VIP (parallel)). Thanks and Regards, Piyali

Ticket Name: TDA2: Host emulation build for SDK0304

Part Number: TDA2 hi,dear In the paper called deep learning user guide , I could not bringup the host emulation mode ,the ref information and the error as following: The command is so simple, however it did not work. Could you please help me figure out how to set it ? BR

Hi, You need source code release of TIDL to build in host emulation mode. Do you have access to it? Thanks, Praveen

No,I did not have that code. However I really saw the makefile. There is the ./src directory in the make process. Could you please kind enough to offer me the code? I want to research that and do some important examples to show the capability of tda2x processer. If it can do well (especially DL related algorithm) and develop easily , there will be more cooperation.

Hi, Source code will be shared only through CDDS. Please contact you local TI FAE to get access to CDDS account and source code release. Thanks, Praveen

Any other method? The communication process of the FAE in China is too Inefficient. Let me offer you the order of your company's TDA2x EVM, is it OK ?

No, I cannot help here further. Please contact your local TI representative only, that is the only way many customer got the source code. Thanks, Praveen

In fact, the representative delayed me so long. I could not get the feedback from him/her. How can I get forward to my work? Could I talk the manager with yours or the departmant manager?

Hi , The TIDL Host emulation is NOT needed for running a CNN network on TI device (It is only needed for de-bugging purpose). The binary release available in VSDK package could run CNN inference in TI devices, use this binary release for your network deployment. Regards, Kumar.D

hi, dear Now although I bought serveral tda2x boards, I have only got part service from the TI tech support in Shanghai of China. I could not get the source code of TIDL. So if I want to run my improved cnn model , I can only run it on the tda2x board not on PC simulator. I have imported the cnn model to the bin format which is suitable for TIDL. Yet the input data need to be resize to 368 X 368，and I should resize it by myself( It has to be the TI method to resize). Even worse, the configuration file (only seg , ssd detection included)on the tda2x board looks like that below: TIDL Configuration parameters ----------------------------- ################################################################################ IMP: Make sure the size of the file names (excluding extension) is not more than 8 characters. ################################################################################ inputWidth=1024 inputHeight=512 inputFile=IN.RGB outputFile=OUT.BIN netFileName=NET.BIN paramFileName=PRM.BIN My cnn net is not for detection or classifcation, but pose recognition. I do not know if I can use this demo cfg file to run my cnn model successfully on the tda2x. If not , could you please be kind enough to offer me new cfg file or make some change for me to run? tks, looking forward to your reply.

Hi, this question is discussed here: e2e.ti.com/.../723315 I will close this thread. Regards, Yordan

Ticket Name: TDA2E: EDMA3 Emulator/Simulator for Desktop PC

Part Number: TDA2E Dear Experts, is there some kind of an emulator/simulator available for EDMA3 for Host PC, similar to EVE SW which can be compiled for Host PC? I am not aware of anything like that. Could You please confirm? Many thanks and best regards, ROGERG

Hi, Your question has been forwarded to a customer support lead. Regards, Mariya

Hi Rogerg, We do not have standalone EDMA simulator. However, EVE simulator includes the internal EDMA module so you can simulate EDMA functionality with EVE simulator. Regards, Stanley

The dmautils similar to EVE are also provided on DSP which can be used for host emulation. You can find the package at VISION_SDK_XX_XX_XX_XX\ti_components\algorithms_codecs\200.V.OD.C66X.xx.xx\dmautils Note that here OD is an example, which is object deetction algorithm. But the directory also exists under the other algorithm directory such as CLR, LD, SFM, etc. Thanks, With Regards, Pramod

Ticket Name: TDA2xx_EVM_BIOS : Error in importing tensorflow pretrained model

Other Parts Discussed in Thread: TDA2 Hi I have installed PROCESSOR_SDK_VISION_03_07_00_00 which i have configured for tda2xx_evm_bios_all. I have copied the REL.TIDL.01.01.03.00 folder to my windows pc and using the tidl import tool tidl_model_import.out.exe. when i give the pretrained tensorflow model frozen_graph file x.pb to import tool tidl_model_import.out.exe the command executed is tidl_model_import.out.exe ..\..\test\testvecs\config\import\tidl_import_x.txt then it gives me this message " TF Model File : ..\..\test\testvecs\config\tensorflow_models\x\x.pb Op Type Cast is Not suported will be By passed Op Type Shape is Not suported will be By passed Could not find the requested input Data : mul !! " I was referring the text file in the path ..\..\test\testvecs\config\import\*.txt file There are paramters mentioned as quantizationStyle quantRoundAdd numParamBits preProcType conv2dKernelType I referred the documentation TIDeepLearningLibrary_UserGuide.pdf where the explanation of each parameters is given but how can we determine that for my particular model which paramters need to set and to what value. Request you for your inputs. Regards Pratik

Hello , Any update on this ?? Regards Pratik Brid

Hi Pratik, Sorry for the delay. The error is because of your models has unsupported layers, please refer to "TIDeepLearningLibrary_DataSheet.pdf" for supported layers. Refer to section "3.6.2 Importing the Model and Parameters" for the explanation about the parameters in the import.txt file. Thanks, Praveen

Hi Praveen, For the above two errors on the unsupported layers, Op Type Cast is Not suported will be By passed Op Type Shape is Not suported will be By passed is there any alternative available which can be used in model re-training so that the layers would be supported with respect to TIDL? I am trying to import face-detection which was trained in tensorflow

Hi Sudhanshu, One way to use only those layers which are supported in TIDL in your network, please refer to TIDL datasheet for supported layers. Other way would be split network up to TIDL supported layers and run that using TIDL and run remaining network outside the TIDL. Thanks, Praveen

Hi Praveen, Thank you for the reply I had referred to TIDL datasheet and understood about the unsupported layers. I am a beginner in DL, so can you suggest how am I supposed to split my layers/networks in model file(x.pb). The model I am using is pre-trained model on Face-detection(Facebox). Also, with respect to running supported layers on TIDL and remaining outside the TIDL, by outside do you mean importing the layers on EVE cores or is it something else? Regards Sudhanshu

Hi Sudhanshu, You need to freeze and optimize the graph with all the layers from input to the last supported layer and run this on EVE core and remaining on the DSP core, please refer tp FAQ 24 in the TIDL user guide for more details. Thanks, Praveen

Hi Praveen, Sorry the late reply and thanks for your above response. I am using PROCESSOR_SDK_VISION_03_07_00_00 which had TIDL version 01.01.03.00... So, in the UserGuide, there is no FAQ 24(Kindly mention what version u are referring to, so that latest TIDL import tool can be referred) However, in the above mentioned TIDL user-guide's FAQ 22, it mentions about how to run the splitted networks on EVE and DSP respectively.. I saw that DSP take input of bin files.. I am still not able to understand how are we going to create binaries for the unsupported layers? SInce TIDL's import tool will create bin file only for the supported layers. Thanks

Hi I am referring to latest release of PROCESSOR_SDK_VISION_03_08_00_00 which had TIDL version 01.02.00.00... which had this FAQ24.Please refer to that. If you have unsupported layers in the middle of the network then that model can't be run on TDA2 (you may have to re-train your model with supported layers), but if you have unsupported layers at the end then those can be offloaded to DSP. Thanks, Praveen

Ticket Name: CCS/TDA2PXEVM: Hwi_disable() function definition

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: Code Composer Studio Hi, I'm trying to test whether interrupts are enabled for a vision SDK usecase by setting a breakpoint at Hwi_disable(), but I can't seem to find the function definition? Thanks, Richard

Hi Richard, Hwi_disable is a BIOS API. You will have to build SDK in debug mode and step into BIOS APIs to see the definition. You are trying this on which CPU? Regards, Rishabh

Hi Rishabh, I'm not interested in the internals of hwi_disable per se, I just wanted to be able to set a breakpoint there for debugging. Since it's a BIOS API, does this mean I can't set a breakpoint at its definition? I am trying this for the camera + radar combo usecase, which registers the interrupt handler to GPIO7_9 on the TDA2PxEVM board. However, I am not sure which CPU GPIO7_9 corresponds to. My problem is that when I probe GPIO7_9, I can see the interrupt request come over. In the software for the usecase, the interrupt handler is also registered to GPIO7_9. However, when I add a breakpoint at and printf() to the interrupt handler, I can tell that it's never invoked. Alternatively, is there some better way for me to verify whether interrupts are enabled correctly for this usecase, rather than stepping through the code and examining every call to hwi_enable and hwi_disable? Thanks, Richard

Hi Richard, GPIO7_9 does not correspond to any CPU. User decides to run on a particular CPU for a particular use case. Can you point to the name of exact use case which you are trying to run. Regards, Rishabh

Hi Rishabh, I am running the "Camera and Radar Capture + Radar Processing (DSP1) + Display (HDMI)" usecase, under "Camera and Radar Combo Use Cases". Based on the usecase files, it looks like the CPUs IPU1_0 and DSP1 are used. Thanks, Richard

Hi Richard, You need to know what is the exact CPU where you are running this code. In case you want to check if interrupt is getting set you should check the GPIO registers for IPR bit. In case IPR is set in GPIO you should make sure that crossbar is configured correctly. Regards, Rishabh

Hi Rishabh, The IPU1_0 is the CPU running this code. Here is what my CCS registers tab looks like: How can I tell which are the GPIO registers? Thanks, Richard

Hi Richard, Ok so you are running on IPU. Can you refer to TRM for GPIO7 registers. Regards, Rishabh

Hi Rishabh, I looked in the TRM and found the "PM_L4PER_GPIO7_WKDEP" register. Is this the relevant interrupt enable register? When I view the register after loading binaries onto the TDA2 board, the value indicates all wakeup dependencies are disabled. When I try to view it again once the code has progressed to the point at which it's waiting for the interrupt, I get a "target failed to read" error. Are there additional settings I need to configure in order to view the register once the code has begun to execute? In addition, I don't see any reference to an IPR bit for any of the GPIO registers. Thanks, Richard

Hi Rishabh, I figured out that the interrupts were correctly enabled. Thanks, Richard

Hi Richard, It is not clear to me if the issue is resolved or not. Can you let me know what was the root cause? Regards, Rishabh

Hi Rishabh, I rolled back my modified Vision SDK to an earlier version, added only the essential modifications from the current version, and interrupts from the radar chip were successfully detected. I was not able to identify a specific root cause. Thanks, Richard

Ok thanks. I will close this thread. Regards, Rishabh

Ticket Name: TDA2: NOR FLASH using TDA2XX and QNX

Part Number: TDA2 hi, I am using TDA2XX board an qnx software.sd boot is working here but i try to boot based on NOR flash using QNX in tda2xx , its not working so please can u share switch settings for NOR flashing. i tried our vision sdk datasheet and QNX datasheet for NOR FLASH. thanks kalai

The DIP switch on EVM represents the setting for SYSBOOT0~15. Please refer to page 7539 in TDA2x ADAS Applications Processor Public Technical Reference Manual (Rev. E) www.ti.com/.../sprui29 You should find SYSBOOT[5:0] = 110101 is for NOR Flash boot.

HI, thanks for your reply. NOR FLASH IN TDA2xx with QNX this pin setting is not working .i used TDA2xx vayu evm xc5777x cpu board assy 516580 REV H board, so please tell the pin settings SW2,SW3 and SW5. thanks kalai

HI , i made all switch combination of this board .i got error like this,so please give the solution. thanks kalai

Hi Kalai, This is QSPI NOR flash. Hence you should try QSPI boot. Also can you have one thread instead of multiple threads with similar questions. Regards, Rishabh

Ticket Name: TDA2E: Questions: about mipicsi and edma

Part Number: TDA2E Other Parts Discussed in Thread: TDA2, hi ti support The processor we use is TDA2 ECO 23*23. There are 4 cameras in our system. The interface connected to the deserializer (DS90UB960) is the mipicsi interface. We put this part of the software in the ipu, and now our data stream is ipu (mipicsi->edma->4 pictures)->a15, is this possible? If not, how can we save resources most? thanks！

Hi, team: Add more background information: four 1280(width)*1280(height)@30fps YUV422 output camera sensors these sensors are connected to UB960 via SerDes UB960 CSI0 output to TDA2Ex SOC, UB960 CSI1 output to XXX SOC Due to XXX SOC limitation, virtual channel cannot be used For TDA2Ex: the 1280*1280 input camera inputs need to be resized to 1280*720 for Surround View applications.

Hi, team: According to the above information, please help to advise the best solution for this requirement: UB960 configuration Basic Synchronized CSI-2 Forwarding? Line-Interleaved CSI-2 Forwarding ? Line-Concatenated CSI-2 Forwarding ? which is our best choice? In TDA2Ex, we need to design the camera data capture with EDMA. The input will be a huge buffer which contains/mixes four camera sensor inputs, and we need to retrieve each of the four independent camera sensor inputs, and get separate data buffer for each camera sensor. Please kindly guide us.

We have confirmed with our partners that we use Line-Interleaved CSI-2.

Hi, expert: The UB960 output is as below: So, I think the TDA2E CSI will capture the frame and store it to DDR memory as one big camera input: 1280 width, 1280*4 height (at 30fps). We need to configure EDMA (probably 4 channels) to separate this big buffer into 4 sensor data buffers. Please help us: whether the above understanding is correct? how to configure EDMA for this purpose? Many thanks.

Hi Peter, Do you mean UB960 merges 4 sensors data into a single frame? Typically UB960 does not merge sensors data, instead it sends them over separate virtual channels. And since they are in separate virtual channels, they will be stored in separate buffers by CAL. Rgds, Brijesh

Hi, Brijesh Jadav: Due to other SOC's limitation in the system, the virtual channel cannot be used. So, UB960 "Line-Interleaved CSI-2" mode will be used in the project. Please refer to "7.4.25.4 Line-Interleaved CSI-2 Forwarding" in UB960 datasheet.

Hello Peter, It really depends on what you want to do with YUV data once it is stored in memory. For e.g. if you intend to process the images on GPU, then GPU can be configured to read an image with start_offset and line_stride. By doing this you will not need to split the superframe into 4 frames. Regards, Mayank

Ticket Name: Linux/TDA2: Windows CCS failed to connect to the board through the emulator

Part Number: TDA2 Tool/software: Linux hi, Windows CCS failed to connect to the board through the emulator， the error info is ： The explanation is: The controller has detected a target power loss. The user must turn-on or connect the power supply for the target. How to solve the problem of power loss?

Can you make sure the board is powered correctly, also power cycle it? Can you try first the "Test connection" option while creating the target configuration first? Thanks, Alex

Ticket Name: RTOS/TDA2: Links and Chains Document support?

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, Do you have more about Links and Chains Document support? Thanks Walter

Walter, You could find documentation in the doc folder.. Rgds, Brijesh

Ticket Name: Compiler/TDA2HG: Can TDA2 support TVI-FHD 2 channel input ?

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi All, Can TDA2x support 2-channel TVI-FHD input? (we are using TP3810 now) or TDA2 can only support TVI-HD input? Thanks. Ranny.

Ranny, TDA2x can support digital parallel input with both embedded sync and discrete sync input interface. If TVI-FHD can output in this format, it can be supported. Rgds, Brijesh

Hi Brijesh, Ok, thanks your replay. Ranny.

Ticket Name: TDA4VM: MCU only BOOTMODE usecase of TDA4

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Dear Champs, My customer is very confusing on the complex boot mode in TDA4. I think the basic boot procedure is MCU boot -> Normal boot Is this right? Why MCU should be boot before Normal boot? What is the purpose of MCU only boot? Thanks and Best Regards, SI.

Hi SI, Think of the MCU's R5F processor as the boot master of the SoC. Note that boot master of J6/TDA2 was the A15 MPU, J6 didn't have an MCU island. The boot master runs its ROM code after reset and loads the SBL image. SBL then can load other cores images, in turn. The whole MCU island/domain is there for safety and diagnostics purposes in the automotive applications. The MCU-only boot allows sucessful boot even if main domain is not powered (due to power failure). MCU then can send message to other nodes in the vehicle that this node is not functional or can perform other tasks. The MCU-only boot is tryed only from MCU domain's peripherals, that's why it can be successful when main domain is OFF. Please refer also to section 4.2.3 Boot Process Flow of the TRM. Regards, Stan

Ticket Name: DRA756: How to disable J6 emmc power save mode.

Part Number: DRA756 Hi experts: Our customer need use PON (Power off notification) function at their project. Micron eMMC when received PON command -- CMD6, Micron emmc need long time to process the PON command. But J6 emmc driver will stop eMMC_CLK very quickly. So micron emmc can not successful finish PON command. Could you please suggest how to disable J6 emmc power save mode? We have try to modify omap_hsmmc_set_ios() power_off case and delete all those POWER_OFF function. it can not keep eMMC send out clock. Best Regars! Han Tao

Hi Tao Han, Could you share the procedure you are using to test Power Off Notification on Linux? Regards, Vishal

Hi Han Tao, In Linux Kernel omap_hsmmc driver we don't think there is an issue handling power off notification. -1- In poweroff_notify timeout is correctly chosen based on SHORT or LONG static int mmc_poweroff_notify(struct mmc_card *card, unsigned int notify_type)
{
        unsigned int timeout = card->ext_csd.generic_cmd6_time;
        int err;

        /* Use EXT_CSD_POWER_OFF_SHORT as default notification type. */
        if (notify_type == EXT_CSD_POWER_OFF_LONG)
                timeout = card->ext_csd.power_off_longtime;

        err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
                        EXT_CSD_POWER_OFF_NOTIFICATION,
                        notify_type, timeout, true, false, false);
        if (err)
                pr_err("%s: Power Off Notification timed out, %u\n",
                       mmc_hostname(card->host), timeout);

        /* Disable the power off notification after the switch operation. */
        card->ext_csd.power_off_notification = EXT_CSD_NO_POWER_NOTIFICATION;

        return err;
} -2- In __mmc_switch API, this timeout is stored as busy_timeout int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value,
                unsigned int timeout_ms, bool use_busy_signal, bool send_status,
                bool ignore_crc)
{
.
.
                cmd.busy_timeout = timeout_ms;
 -3- In omap_hsmmc driver, this busy_timeout is used as data timeout. static int
omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
{
        int ret;
        unsigned long long timeout;

        host->data = req->data;

        if (req->data == NULL) {
                OMAP_HSMMC_WRITE(host->base, BLK, 0);
                if (req->cmd->flags & MMC_RSP_BUSY) {
                        timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;

                        /*
                         * Set an arbitrary 100ms data timeout for commands with
                         * busy signal and no indication of busy_timeout.
                         */
                        if (!timeout)
                                timeout = 100000000U;

                        set_data_timeout(host, timeout, 0);
               }
                return 0;
        }
 Regards, Vishal

Hi Vishal: Thanks for your help. Except your provided driver modify. At linux PSDK release use below command can continue send out MMC clock. With below command, now can continue send out eMMC_CLK at EVM board. Believe this method can work. dd if=/dev/mmcblk0 of=/dev/null count=1000000 & omapconf write 0x480B4010 0x14 omapconf write 0x480b4110 0x130C omapconf write 0x480b412C 0x118620 Best Regards! Han Tao

Ticket Name: TDA2: EVE: Calculate VCOP cycles

Part Number: TDA2 Hi, I saw in the data sheet (eve_sw_datasheet.pdf) that the performances for TI provided kernels and apps is given in cycles per pixel. For kernel, this is based on the block size and for apps it is based on the image size. Can you please share with us how to calculate these cycles per pixel for both apps and kernels? Do we use EVE core utilization to calculate this? What is the operating frequency of EVE? Will there be a difference in the performance metric (cycles per pixel, local link latency etc), if the application is run through VisionSDK and when run standalone? Regards, Surbhi

Hello, Any updates?? Regards, Surbhi

Hi Surbhi, Please find my answers inline : Can you please share with us how to calculate these cycles per pixel for both apps and kernels? Anshu >>> Cycles per pixels are calculated by dividing the total cycles taken by the kernel/apps by the number of pixels in block/image respectively. Do we use EVE core utilization to calculate this? Anshu >>> Please refer the above answer. What is the operating frequency of EVE? Anshu >>> It depends on the part number of the SOC. For Tda2x/3x its 500MHz. Will there be a difference in the performance metric (cycles per pixel, local link latency etc), if the application is run through VisionSDK and when run standalone? Anshu >>> In standalone only EVE is accessing the DDR but in system there could be other initiators for DDR and hence there may be slight degradation when an application is running with full system. Generally if the compute on VCOP is much larger then this will have less impact but if the application is more DMA bound then it may have more impact in system. Regards, Anshu

Ticket Name: TDA2EXEVM: Flashing Utility - mflash: flashing the binary images to QSPI Flash memory using the UART interface for the TDA2xx Boards.

Part Number: TDA2EXEVM Other Parts Discussed in Thread: X5777BX, X5777BXGABC, TDA2 Hi, We are working flash binary image via UART interface on the TDA2X Vision board. The board information as following: Vision SDK Version : [REL_VISION_SDK_03_07_00_00] FVID2 Version : [FVID_02_01_00_01] BSP Version : [PDK_01_10_03_xx] Platform : [EVM] SOC : [TDA2XX] SOC Revision : [ES2.0] Board Detected : [Vision] EEPROM Board Info Header Mismatch!! Base Board Revision : [REV A] Daughter Card Revision: [REV D] As the user guide of Appnote_mflash (pg#2), we configured the SYSBOOT (SW2 &SW3 ) & BOOT_SWITCH (SW5) switch SW2[0:7], SW4[8:15] to [11001000][10000001] and SW5 to [0000100000] At the same time, I setup a serial connection (115200, 8/Even/1 , no flow control) by Tera term on PC side . But I don't receive any "AL!" chars from UART on TDA2XX board even though power reset for several times. Could you help teach me how to solve the issue ? Thanks. ps. I could burn successfully flash image via ccs. BRs, Sam Hsieh

Hi, The mflash user-guide mentioned "With correct settings, it should continuously display AL! on the TeraTerm for TDA3xx. The printed characters may vary for different platforms." For the TDA2xx platform, it can display anything & when you connect the USB cable from the board to PC, it will show multiple COM ports. So try to connect each COM port & make sure the correct port you are going to use for flashing the images. Thanks Gaviraju

Hi Gaviraju, Thank you for your feedback. I confirmed that the connection of COM port via USB cable to PC is OK. Even though I add a USB hub between PC and TDA2xx board, the result is same FAIL. BRs, Sam Hsieh

Hi Gaviraju, As for the connection, we connected TDA2x with PC via UART1 interface (J1 connector). Because the message of boot from SD mode could work fine. The COM port configuration of PC side should be OK. regards, Sam Hsieh

Hi, I followed the steps mentioned in the user-guide & I saw the below character on the UART console. @D(▒ @▒▒ Can I know which application are you using to view the UART console? I mean TeraTerm or MobaxTerm or Minicom or Putty, etc. I used Mobaxterm & I'm getting expected output in the terminal. So please try with different applications. Thanks Gaviraju @D(▒ @▒▒

HI Gaviraju: Could you provide the soc number , I was used x5777BX(TDA2xx), But I can not see the messages(AL!AL!AL!.....) from UART. Thanks, Ethan

XC5777x TDA2xx

Hi Gaviraju: Our chip is X5777BXGABC. May be the part number. Can not support the function. Could you track the part number ? Thanks,

Hi Gaviraju, We used Putty and TeraTerm application to verify it, both the same phenomenon (NG). I don't think which it results from the different application. We are worried about the TDA2XX EVM board doesn't support the feature of mflash due to the micro-code of TDA2XX (X5777BXGABC) is out-of-date. or we made a mistake in the configuration of SYSBOOT (SW2 &SW3 ) & BOOT_SWITCH (SW5). Could you help confirm the following questions ? Thanks. Q1. Does it TDA2XX (X5777BXGABC) support the mflash feature? Q2. Is the DIP SW configuration OK? BRs, Sam Hsieh

Hi Gaviraju, I uesed mflash to burn my code, TDA2 is crash and hold. [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [PC] Requesting the ASIC ID [RBL]4 [RBL]1 [RBL]5 [RBL]1 [RBL]56 [RBL]41 [RBL]7 [RBL]2 [RBL]13 [RBL]2 [RBL]1 [RBL]0 [RBL]12 [RBL]15 [RBL]1 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]14 [RBL]21 [RBL]1 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [RBL]0 [PC] Requesting PERI_REQ mode [PC] Sending SBL_MFLASH filesize. [PC] Size of sbl_mflash = 69477 [PC] Sending SBL_MFLASH... Please wait [PC] File Size = 69477 [PC] ## [PC] Transfer Complete. Time = 1.000 [PC] Opening port for sbl_mflash. Baud = 12000000 Parity = 0 StopBits = 0 ByteSize = 8 [PC] Opening serial port successful.

Hi, I will check with my teammate's whether "x5777BX" board will support mflash or not & I will update you soon. The previous issue is resolved? I mean printing the character "AL!" continuously. Basically mflash tool used to flash the images to the QSPI memory & this can be done using CCS & JTAG. So why don't you make use of this method? Thanks Gaviraju

Ticket Name: TDA2SX: I2C Internal FIFO buffers depth

Part Number: TDA2SX Hi, In TDA2X TRM, I could see the internal FIFO depth is 64-bytes (reset value). But when I read back the I2C_BUFSTAT register after reset, it is set to 16-bytes. Have something been changed or should we revise the TRM? Regards, James

Hi James, Looks like a document bug. I've also read 0x1 (16 bytes) on a AM572x board. I will file an incident to correct this. Regards, Stan

Ticket Name: RTOS/TDA2: TCP ACK segments comprising payload

Part Number: TDA2 Tool/software: TI-RTOS Hi everyone! We have established a set-up in the following manner: We are using two of TDA2x SoCs. The first SoC is a TX side device. We run a use case that captures video contents from cameras, encodes the data using H.264 encoder and pushes the data to the network by Null link. The second SoC is an RX side device. We have created a new link that is the same as the NullSrc link, with one exception, which implies that the link initiates a TCP connection (by default, the NullSrc link waits for a connection request from a PC, but in our case it sends a connection request). This means that our modified NullSrc link sends SYN segments to the TX device's Null link. The video contents are decoded and previewed using Display links. We performed network traffic observation between these two devices using Wireshark. During the observation we have noticed that TCP ACK segments comprise payload data. We suspect that this issue induces the bufferbloat effect on the sending side's TCP TX buffer. The latency between cameras (TX side) and displays (RX side) sometimes reaches 2 to 3 seconds. Is is necessary for ACK segments to comprise payload and is there any option to disable payload transmission within ACK segments? Best regards, Marko Gostović

Hi Marko, Marko Gostovic said: Is is necessary for ACK segments to comprise payload and is there any option to disable payload transmission within ACK segments? Yes, ACK segments are needed for TCP. I will check about disabling payload transmission. Have you tried using the TCP_NODELAY option to decrease this latency? Thanks, Gerardo

Marko, I haven’t heard back from you, I’m assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out) Prasad Jondhale Sr. Software Engineer, Automotive Processors, TI India

Hi, Prasad! We have invoked the setsockopt function with TCP_NODELAY flag and got similar behaviour. However, we omitted that the ACK segments comprising payload have been generated on the stream sending side, not on the receiving side. The ACK segments on the receiving side have been correctly generated with size of ~60 bytes. We succeeded to achieve the stream with acceptable performance running on the other test environment, so the size of segments is currently not important. Since there are ACK flags set within the forward-way stream segments (from video capture device to the stream acceptor device), we are wondering whether it is required for these flags to get set and is there any way to disable this issue in order to avoid the generation of segments with slightly confusing header contents? Best regards, Marko

Hi Marko, On TCP all packets after the initial SYN packet should have the ACK flag set. Unless the ACK was being sent without payload data (just the header), then this is the correct behavior. BR, Gerardo

Ticket Name: Linux/TDA2EVM5777: how to use TDA2 Linux USB otg link USB Storage

Part Number: TDA2EVM5777 Tool/software: Linux I want to be on a Linux system use USB Storage in TDA2EVM5777 USB otg it can't work

Hi Martin, The USB host mode is supported on Processor-SDK Linux. You may find the below thread useful. e2e.ti.com/.../553432 Regards Shravan

Ticket Name: TDA2P: Write Back channel cause SYNCLOST1 error

Other Parts Discussed in Thread: SYSBIOS Hello All, Hello All, We are using TDA2P Soc. In Display driver, we have configured VID1 pipeline to display live picture through LCD output. We are using NV12 Video format to input VID1 Pipeline and output is RGB24. We also need to capture same LCD out and store in system memory. Hence we used Write Back pipeline to capture the display frame with capture mode and video format is RGB888. Surprisingly, once we enable the WB pipeline, we got the SYNCLOST1 Error and lost the live picture on LCD display. By further debugging, we check the IRQ_STATUS register and found that we are getting WBUNCOMPLETEERROR_IRQ along with SYNCLOST1 IRQ. To overcome WBUNCOMPLETEERROR_IRQ error, we have set the DISPC_WB_ATTRIBUTES2[7:0] WBDELAYCOUNT bit field to maximum but unfortunately we got the same errors again. WE thought there will be timing issue and we change the WB configuring from CAPTURE to Memory to memory transfer, but unfortunately again the we got the SYNCLOST1 error without WBUNCOMPLETEERROR_IRQ. We even try different burst size and burst type in WB and VID1 config with different arbitration priority. We also used WB_MFLAG mechanism to avoid WBUNCOMPLETEERROR, but result is the same, SYNCLOST1. Could you please help us and let us know what could be necessary to avoid this issue. Best regards Naresh

Hi Naresh, Please refer to WB-CRC usecase vision sdk and use WB pipeline accordingly. Rgds, Brijesh

HI Brijesh, Thank you so much for your prompt response. Yes I will do that but this will be time consuming for us. Do you have anything in your mind on first glance what could be the wrong in configuration or what could be missed in init. Best regards, Naresh

Hi Naresh, We also do have few examples in PDK in vision_sdk\ti_components\drivers\pdk_01_10_02_07\packages\ti\drv\vps\examples\dss\displayDssWb\src\DisplayDssWb_main.c. You could try and refer this example. Rgds, Brijesh

Hi Brijesh, I have tried DisplayDSS eample code. While running the code I got below error. We running the code on our own TDA2p Board. Please let me know What must be we need to modify so this example code will work on our ECU. [Cortex_M4_IPU1_C0] DISP_DSS_APP: Sample Application - STARTS !!! ti.sysbios.family.arm.m3.Hwi: line 1105: E_hardFault: FORCED ti.sysbios.family.arm.m3.Hwi: line 1182: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: d1082800 Exception occurred in background thread at PC = 0x800af426. Core 0: Exception occurred in ThreadType_Task. Task name: {unknown-instance-name}, handle: 0x80200008. Task stack base: 0x80272f80. Task stack size: 0x2800. R0 = 0x0000000c R8 = 0x8007ec86 R1 = 0xd1082800 R9 = 0x00000000 R2 = 0x00000000 R10 = 0xffffffff R3 = 0x00000001 R11 = 0xffffffff R4 = 0x00000000 R12 = 0x17e60300 R5 = 0x8007eadc SP(R13) = 0x80275698 R6 = 0x8007ead4 LR(R14) = 0x800cd9cb R7 = 0x8007ead8 PC(R15) = 0x800af426 PSR = 0x01000000 ICSR = 0x0440f803 MMFSR = 0x00 BFSR = 0x82 UFSR = 0x0000 HFSR = 0x40000000 DFSR = 0x00000001 MMAR = 0xd1082800 BFAR = 0xd1082800 AFSR = 0x00000000 Terminating execution... Mfg, Naresh

Hi Brijesh, I have debug the code further and found that Fvid2_create is returning a null pointer. No idea how it could happen. Mfg, Naresh

Hi Brijesh, While running DisplayDSS vision sdk code on our own ECU, we are not able to access the memory mapped register. I have attached debug image. Best regards, Naresh

Hi Naresh, How are you running this example? Are you running after loading and running gel files on A15? Please note that without running 'OnTargetConnect' Option on A15 gel files, this example can't be run. This option powers on the modules and enables clock.. Rgds, Brijesh

Hello Brijesh, I am running the code on IPU1 C0. Yes, I am running by loading the gel files and running the script TDA2Px_MULTIPLECORES_EnableAllcores, OnTargetConnect and IPU1SSClkenable_API. Then Load the vps_examples_displayDssWb_ipu1_0_debug.xem4 on ipu1 c0. This is the build command. gmake -s vps_examples_displayDssWb BOARD=tda2px-evm CORE=ipu1_0 BUILD_PROFILE=debug Best regards, Nares

Ticket Name: Linux/TDA2: Can network_tx.out in network tool be set to TCP/IP mode, not using TFDTP, how to set

Part Number: TDA2 Tool/software: Linux Create a Vision SDK use-case on target side. Specify the source of data as “Network_rx” link. NDK runs on A15 CPU. NDK_PROC_TO_USE=a15_0. Set NetworkRxLink_CreateParams.dataRxMode as NETWORK_RX_LINK_DATA_RX_MODE_TCPIP I use the network tool to send image data on the pc side, Network Tx: Connecting to server 172.18.0.205:29171 ... # ERROR: NETWORK: Server connect Failed (172.18.0.205:29171)!!! # INFO: Closing connection to Server

Hi Hua Liu Liu, Do you want to send the captured data to the PC via the network (network_rx) or File from PC to the evm for HDMI Display (network_tx) ? These are the commands you should use respectively Network Tx ---------------- network_tx.out --target_ip <TARGET_IP> --host_ip <HOST_IP> --files <YOUR_FILE_IN_PC> Network_Rx ---------------- network_tx.exe --target_ip <TARGET_IP> --host_ip <HOST_IP> --files <FILE_PATH_IN_PC_WHERE_THE_CAPTURE_IS_TO_BE_SAVED> If you don't use --usetfdtp in the command, it'll use tcp/ip for default. Regards, Anand

Hi Anand, I want to sent File from PC to the evm for HDMI Display (network_tx) , Network TX ----------------------- root@ubuntu:/home/ti/vision_sdk/apps/tools/network_tools/bin# ./network_tx.out --target_ip 172.18.0.200 --host_ip 172.18.0.156 --files airshow_1280x720_5frs.yuv # Network Tx: Connecting to server 172.18.0.200:29171 ... # ERROR: NETWORK: Server connect Failed (172.18.0.200:29171)!!! # INFO: Closing connection to Server # Network Tx: Connecting to server 172.18.0.200:29171 ...

Hi Hua Liu Liu, Please try the ping and make sure it works before trying out a network usecase. I'm assuming you're using dynamic IP here. Regards, Anand

Hi Anand, Thanks, In the windows environment,I sent File from PC to the evm for HDMI Display (network_tx) ,is ok. I ported the networ_rx code to Linux and it is a bit of a problem. Let me check the code myself.

Sure, Hua Liu Liu. Let me know of any updates! Regards, Anand

Hi Anand, NDK_PROC_TO_USE=a15_0, #define VIDEO_SENSOR_NUM_LVDS_CAMERAS (4) Camera 1, Camera 2, Camera 3 and Camera 4 are used for 4 channel LVDS use-case I joined NetworkRx (A15) in lvds_vip_sv_standalone, there is no image output in the loop, and there is a conflict when the camera is used with the network.

Hi, What exact changes did you make when you ported the code to linux? I suppose the usecase was working for you in Windows. Have you made any additional changes? Regards, Anand

No code changed during the migration process。I am running under windows, no problem, I am transplanted to linux to run the following problems ASSERT (chains_lvdsVipSurroundViewStandalone_priv.c|chains_lvdsVipSurroundViewStandalone_Create|332) line332：status = System_linkCreate(pObj->NetworkRxLinkID, &pObj->NetworkRxPrm, sizeof(pObj->NetworkRxPrm)); UTILS_assert(status == SYSTEM_LINK_STATUS_SOK);

Hi Hua Liu Liu, I am not sure how these changes would affect the 'TCP/IP or TFDTP' parameter. So the System_linkCreate is not successful in your linux code? I mean the assert is failing? Regards, Anand

Hi Hua Liu Liu, It's been a while since I've heard from you. Were you able to resolve the issue? :) Regards, Anand

Ticket Name: TDA2: How does TDA2 achieve video processing?

Part Number: TDA2 TDA3 SOC achieves live video processing in purely hardware using Imaging Subystem(ISS). How does TDA2 achieve live video processing? Regards, Amer

Amer, ISS is mainly used for converting RAW bayer data into YUV format, RAW data is captured from the bayer sensor. TDA2x does not have ISS, TDA2x uses sensors which outputs YUV data directly. Rgds, Brijesh

RAW monochrome data will be captured from our sensor. No companding. Typically, how would TDA2x process live RAW monochrome video? Regards, Amer

Amer, As far as i know, there is no algorithm to process monochrome data. You will need to add this algorithm. Rgds, Brijesh

Ticket Name: TDA2SX: Spec for TDA2 gpu?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi Expert, Is there spec for TDA2 GPU? How many GFLOPS? Thanks Daniel

Hi Daniel, The GPU used in TDA2 is a dual core SGX544 GPU, and at 532 MHz, it performs at 34 GFLOPS. Regards, Takuma

Ticket Name: Linux/DRA744: RGMII-ID ( Internal delay) setting....

Part Number: DRA744 Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hi , I use the RGMII interface connect with Marvell Ethernet SW (88E6390). I set RGMII delay setting enable ( rgmii-id ) but it seems not work. Below is my device setting... &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; phy-mode = "rgmii-id"; dual_emac_res_vlan = <1>; fixed-link = <1 1000 0 0>; }; How to ensure the RGMII-ID enable setting is correct?

Hi Shawn, which is the version of your SDK/Linux kernel? Regards, Yordan

GLSDK 7.04.03. Linux dra7xx-evm 3.14.63

Hi Shawn, I have forwarded your question to an ethernet expert. Regards, Yordan

Shawn, Till Linux Ethernet expert helps you, can you please refer to http://www.ti.com/lit/an/snla243/snla243.pdf for RGMII delay settings?

I find the RGMII features that only SR2.0 can enable or disable internal TXC delay. and I got the Chip Revision by dev2mem command 0x1B99002F --> SR 1.1 Is that mean i can not use RGMII-ID setting????

The RGMII-ID is not supported on SR1.1. The internal TXC delays are always enabled on this and remote side/PHY needs to take care of not reapplying the delay for Rx lines as TDA2 has already applied it.

TXC delay is always enable..but it still have no delay on by board Below image is J6 RGMII TXC and TXD0 and do not connect anything.

Could you check DRA7x Ethernet statistics registers? Is there any error bits set? Also check on PHY side too if any align/CRC issues.

Ticket Name: TDA2: TDA2SXBTQABCRQ1

Part Number: TDA2 We are using SOC TDA2SXBTQABCRQ1 in our ADAS project. Could you please provide AVS voltage (typ, min & Max), current and power dissipation for all voltage rails. Camera Interface: 4 Camera 4XDe-Serializer data format: 1280X800@30fps YUV422 BT.656 format 1XSerializer: LVDS out 1024X768@30fps RGB888 Please find the attached document to know the operating frequency for all the core.

Hi Raja, the attached documents is not visible, can you try to reattach it? Regards, Yordan

TDA2SXBTQABCRQ1.pdf Hi Yordan, Please check now.

Hi Raja, they are visible now. I have pinged power experts to comment. Regards, Yordan

Hi Yordan, Thanks. Actually this information is blocking the PI simulation. If possible please provide ASAP.

Raju, For the AVS values for the different OPPs: The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the STD_FUSE_OPP. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the TRM. The power supply should be adjustable over the following ranges for each required OPP: – OPP_NOM for MPU: 0.85 V - 1.15 V – OPP_NOM for CORE and Others: 0.85 V - 1.15 V – OPP_OD: 0.885 V - 1.15 V – OPP_HIGH: 0.95 V - 1.25 V The AVS voltages will be within the above specified ranges For the power dissipation based on the usecase, can you please post this question with your TI contact? We can help you evaluate the power dissipation through the private forums. Thanks and Regards, Piyali

Hi Piyali, Thanks. I will request power dissipation to our TI contact. I need exact min, Typ and Max voltage for all the cores. Is it possible to provide these values If I share STD_FUSE_OPP Registers settings? Kind Regards, Raja

Hi Raja, The min and max is as per the data manual information I had shared in the earlier post. I see from the picture of the table you are looking at OPP_HIGH configuration. The min for all rails for OPP_HIGH is 0.95 V, the max for OPP_HIGH is 1.25 V. The distribution is usually like a gaussian bell curve, so the "typ" value is concentrated near the mid point of these two values. Thanks and Regards, Piyali

Ticket Name: TDA2HG: [Opengl] -- the cube usage in fbo

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 hi: I have a question about the usage of cubemap in fbo; the simple code as bellow: { glGenFramebuffers(1, &fboID); glBindFramebuffer(GL_FRAMEBUFFER,fboID); glGenTextures(1, &cubemapID); glBindTexture(GL_TEXTURE_CUBE_MAP, cubemapID); for (unsigned int i = 0; i < 6; ++i) { glTexImage2D(GL_TEXTURE_CUBE_MAP_POSITIVE_X + i, 0, GL_RGB, 256, 256, 0, GL_RGB, GL_UNSIGNED_BYTE, nullptr); } glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_S, GL_CLAMP_TO_EDGE); glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_T, GL_CLAMP_TO_EDGE); glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MIN_FILTER, GL_LINEAR); glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MAG_FILTER, GL_LINEAR); glUniform.. //update the uniform variable glViewport(0, 0, 256, 256); for (unsigned int i = 0; i < 6; ++i) { glFramebufferTexture2D(GL_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_CUBE_MAP_POSITIVE_X + i, cubemapID, 0); if (glCheckFramebufferStatus(GL_FRAMEBUFFER) != GL_FRAMEBUFFER_COMPLETE) { printf("glCheckFramebufferStatus error!\n"); } glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT); renderCube(); } } when i test the code, it works well on windows, but when i move it to the tda2 platform, the question is comming, sometimes the effiect is black , or is white, or white and black , or other colors, it's change every time. how is this? and how to resolved it? thanks

Hello, Can you try and see if this works:     // Setup texture for cubemap
    glGenTextures(1, &textureCubeMap);
    char buffer0[CUBEMAP_TEX_LEN * CUBEMAP_TEX_LEN * 6];

    glBindTexture(GL_TEXTURE_CUBE_MAP, textureCubeMap);
    memset((void *)buffer0, 0x50, CUBEMAP_TEX_LEN*CUBEMAP_TEX_LEN*6);
    for(GLuint i = 0; i < 6; i++)
    {
            glTexImage2D(
                            GL_TEXTURE_CUBE_MAP_POSITIVE_X + i,
                            0, GL_RGBA8, CUBEMAP_TEX_LEN, CUBEMAP_TEX_LEN,
                            0, GL_RGBA, GL_UNSIGNED_BYTE, (char *)buffer0
                        );
    }

    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MAG_FILTER, GL_LINEAR);
    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MIN_FILTER, GL_LINEAR);
    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_S, GL_CLAMP_TO_EDGE);
    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_T, GL_CLAMP_TO_EDGE);
    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_R, GL_CLAMP_TO_EDGE);

    // Setup Framebuffer for cubemap
    glGenFramebuffers(1, &fbCubeMap);
    
    // Rendering part
    GLint current_fbo;
    glGetIntegerv(GL_FRAMEBUFFER_BINDING, &current_fbo);
    glBindFramebuffer(GL_FRAMEBUFFER, fbCubeMap);
    
    // Render to cubemap
    for (int i = 0; i < 6; i++)
	{
        glFramebufferTexture2D(GL_FRAMEBUFFER,
		    GL_COLOR_ATTACHMENT0,
		    GL_TEXTURE_CUBE_MAP_POSITIVE_X + i,
		    textureCubeMap,
		    0);
	    glClear(GL_COLOR_BUFFER_BIT|GL_DEPTH_BUFFER_BIT);
	    //.... draw/render to cube map surface
	}
	
	// Bind the original frame buffer
	glBindFramebuffer(GL_FRAMEBUFFER, current_fbo);
	
	// Use cubemap texture
	glBindTexture(GL_TEXTURE_CUBE_MAP, textureCubeMap);

    //... draw to the final framebuffer using cubemap
    // In the shader code, use samplerCube to sample texture
    // e.g:
    // uniform samplerCube skybox;
    // ...
    // vec4 colorval = texture(skybox, direction);
    
 If it still doesn't work, can you try and use glGetError to check for any errors? Regards Hemant

Ticket Name: RTOS/TDA2: How can I make change in eve kernel rebuild?

Part Number: TDA2 Tool/software: TI-RTOS Hi, I make some changes in one of eve kernel algorithm. When I build with "gmake TARGET_PLATFORM=PC" in eve root directory, and run test app, the changes in eve kernel algorithm doesn't work. When I use make clean for the whole eve and make again, it works. But it is too slow. How can I rebuild eve kernel algorithm and make it work quickly? Thanks! Best Regards, Derek Yang

Hi Derek Yang, can you try the following and see if it works: follow the instructions in "eve_sw_01_19_00_00\kernels\docs\eve_kernels_userguide.pdf to rebuild just the modified kernel and then rebuild eve sw with "gmake TARGET_PLATFORM=PC". Regards, Yordan

Ticket Name: RTOS/TDA2: Can provide more use case using the source from SD card, not the camera

Part Number: TDA2 Tool/software: TI-RTOS Hi, as title we using version 3.03 SDK on TDA2 Can provide more use case using the source from SD card, not the camera BR Allen

Hi Allen, Refer below UCs (under vision_sdk\apps\src\rtos\usecases) which uses source from SD card 1. null_src_display UC 2. null_src_dec_display UC 3. tidl UC 4.tidl_OD UC Regards Suryamani Jena

Hi Have any more use case? BR Allen

Hi Allen, You can modify existing UCs which all are using capture source as camera to SD card Regenerate UCs with Null Source as capture source Set Null Source params for file read (refer null_src_dec_display UC) Ensure the output from NullSrc link is in correct format for next link to process Regards Suryamani Jena

Hi Allen, If you are able to generate & test with Null Source as capture source Can we close this thread ? You can open a new thread anytime you need any assistance & will be glad to help you Regards Suryamani Jena

Ticket Name: CCS/TDA2EXEVM: How to write those 3 files onto the EMMC?

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Tool/software: Code Composer Studio Hi Champs: Customer is asking how to Read/Write those 3 files onto the EMMC of the TDA2? A. TIDLCFG.TXT，NET / PRM.BIN? B. And how those 3 files are generated? What are those 3 files' purpose? how to use them? Thanks. BR Rio

Hi Rio, These files are needed for running TIDL. We don't support eMMC driver in RTOS whereas TIDL use cases are supported only for BIOS configuration. Can you ask customer to use SD card instead of eMMC. Regards, Rishabh

Ticket Name: TDA2: Usecase inputdata file(inData_OD) and usecase input header file(inHeader_OD) for object detection(Vision SDK_03.03.00.00)

Part Number: TDA2 Hi, In the VisionSDK_UserGuide_TI_DeepLearning.pdf it mentioned that for the object detection usecase it is mentioned that 4 file are needed. o TIDL OD Network file (NET_OD.bin) o TIDL OD Parameter file (PRM_OD.bin) o TIDL OD Usecase input data file (inData_OD) o TIDL OD Usecase input header file (inHeader_OD) In case of semantic segmentation usecase 2 more files are needed i.e. TIDLCFG.TXT and Input file. I have few questions regarding these files: 1) Network file and Parameter file can be generated by the import tool from TIDL. How to generate the Usecase data input file and usecase input header file? 2) Is the usecase data input file generated from Input file? If yes, why both Input file and Usecase data input file are needed for semantic segmentation usecase? Thanks in advance, Navinprashath.R.R

Hi, From these links (https://e2e.ti.com/support/arm/automotive_processors/f/1021/t/660676 and https://e2e.ti.com/support/arm/automotive_processors/f/1021/p/639881/2391227#pi239031350filter=all&pi239031350scroll=false&pi239031350=2), I am able to found out that inData_OD and inHeader_OD can be generated with the help of ffmpeg. a)inData_OD generation >ffmpeg -i output.avi -y -c:v libx264 -vframes 50 inData_OD b)inHeader_OD generation >ffprobe -show_packets ./inData_OD >index.idx >PAT=size >sed -n "/$PAT/p" index.idx | cut -d' ' -f3 >> size_extracted.txt After this step, size_extracted.txt will contain size of the frames. Remove the string "size=" from each line in the file and save only the numbers in size_extracted_jelly.txt. >cat size_extracted_jelly.txt | perl -n -e 'printf("%08x\n",$_)' | sed 's/\(..\)\(..\)\(..\)\(..\)/0x\4\n0x\3\n0x\2\n0x\1/' | xxd -r -p > Size_test.bin && du -b Size_test.bin >cp Size_test.bin inHeader_OD

Hi Navin, thanks for sharing your findings. Regards, Yordan

Ticket Name: TDA2: Number of cores

Part Number: TDA2 Hi Sir, I want to know how many cores are there in the TDA2xx SoC? As per my knowledge, A15(MPU_0 or a0), M4(IPU_0 or m0), M4(IPU_1 or m1), 2 DSP cores, 4 EVE cores. I am right.? Thanks in advance! Regards, Sagar K

Hi Sagar, It depends on the part that you are using. Superset part has the configuration you mentioned. See www.ti.com/.../products.html for details. Regards, Rishabh

Hi Rishabh, I know that it is TDA2xx but how can I know last XX digit? Like TDA2HG, TDA2HX etc among all these which one I am using how could I know that? Based one last XX I will get to know how many cores are inside. Am I right? Is there written on the SoC? Thank You, Sagar

Hi Sagar, You can know this information by reading CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24]. Please refer to Data Manual for TDA2xx for all the possible values and their meanings. Regards, Rishabh

Hi Rishabh, As per your reply, I got these value in CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24] register and referring Data Manual I didn't find any match value. As per the values please let me know which device I am using. Thank You, Sagar K

Hi Sagar, This is a pre production super set device. Hence you see 0x3F as the value. For production parts this value will be e-fused correctly. Regards, Rishabh

Hi Rishabh, So, how can I find it that which super set it is? Regards, Sagar

Hi Sagar, It will match TDA2SXx. Regards, Rishabh

Ticket Name: TDA2SX: Does the configuration of DDR in the MLO file prevent entry to BOOT？

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi team, Here's an issue from the customer may need your help: Log info of the TDA2S DEMO board: DRAM: 4 GiB. And the self-made reference board is only 2GB. The customer suspect this will cause the system to enter a dead loop after BOOT is up, and DDR on the DEMO board to EMIF1 also does not work. Is this possible? Modify the configuration of DDR in the TDA2 MLO file to be configured as one EMIF interface. How to modify the MLO? Source code: PROCESSOR-SDK-VISION_03.07.01.00 | TI.com Could you help check this case? Thanks. Best Regards, Cherry

Hi, May I know is there any update? Thanks, Cherry

Hi Cherry, Is your customer booting Linux or RTOS on A15? If Linux, they have to modify SPL/u-boot to update the DDR config. If RTOS, they have to update DDR config in SBL. Please refer to EMIF config tool. https://www.ti.com/lit/pdf/sprac36 Regards, Stanley

Ticket Name: RTOS/TDA2: Could we storage DL files on other memory?

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, From DL document tutorial, we can save AppImage(FW file) and NET.bin + PRM.bin(DL files) to SD card and boot up system. Because we need more space to storage DL files. We are not sure whether can storage above files(FW and DL) to separate memory device and load to DDR? Could you give us some advice? Thanks for your support.

Hi , Please look at the following you can use qspi itself to store the files e2e.ti.com/.../2527927 Regards Chetan.M

Hi Chetan.M, Sorry for the late reply. Above link show we can storage DL files to QSPI. But we would storage FW to QSPI and DL files to SD card (because DL model file will large after traning). Is workable if we storage FW and DL on different memory? (booting from QSPI , reload DL from SD card) Many thanks.

Ya , You can always have the Appimage in QSPI and read the DL form SD card . Regards Chetan.M

Many thanks ,

Ticket Name: TDA2EVM5777: Is TDA2x a processor or evaluation board?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2, DM505 Is TDA2EVM5777 evaluation board? What SOC or processor is on this evaluation board?

Hi Amer, it is evaluation board with TDA2x SoC, you can check it's page on ti.com for description: www.ti.com/.../TDA2EVM5777 Regards, Yordan

In addition to what Yordan suggested, I wanted to clarify that the 5777 is the superset chip that contains all features of all TDA2x parts for your evaluation purposes. Thanks, Alex

What is 5777? Is it a SOC like TDA2x? Could you provide complete part number for 5777?

It's just labeling of the superset TDA2x SOC found on your EVM. There is no part number because you can't order it. Like I said it's for evaluation. When you decide which features you will use from the superset, then you can pick a particular TDA2 part number. thanks, Alex

Currently, I'm unable to access TDA2 link provided above. We need to know all SOC's that are similar to DM505. We want to read about SOCs that DM505 resources such as Image Signal Processor(ISP) and Display Subsystem(DSS) but also have features such as H.264 engine and USB 3.0. Regards, Amer

Hi Amer, you can check this page where you can filter the processors by features: www.ti.com/.../products.html Regards, Yordan

If you really need a twin device to the DM505x, you should look at TDA3x, here is its datasheet: www.ti.com/.../tda3.pdf Or you can also look at the TDA2Px (TDA2 Plus) which is TDA2 "plus" the ISS and other stuff, here is the datashet of the ACD package: www.ti.com/.../tda2phg-acd.pdf Right now your EVM is with TDA2x superset (but still not the Plus device) which doesn't contain ISS. thanks, Alex

TDA2 is Automotive. Are there non-automotive versions of TDA2? Like DM505 is non-automotive version of TDA3.

Hi Amer, you can check Sitara processors: www.ti.com/.../products.html Regards, Yordan

TDA2 Plus meets our needs. Is there a non-automotive version of this SOC. We need ISS, USB 3.0, DSS, IVA-HD Regards, Amer

Can you contact your TI representative? There may be some Sitara parts similar to the TDA2 Plus which are not part of the public catalog right now. thanks, Alex

Ticket Name: TDA4VM: Does TDA4 ISP support RGB-IR sensor ?

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 The TDA2/TDA3 vision SDK 3.8 has the demosaicing function implemented on c66x . Was wondering if the TDA4 ISP is flexible enough to avoid using the DSP for such pixel intensive task. regards, Victor

Hi Victor, There are 2 kinds of RGB-Ir sensors 1. 2x2 CFA : This type is natively supported by TDA4 ISP. Any 2x2 CFA is supported. 2. 4x4 CFA : This requires a pre-processing step similar to what was done on TDA2P and TDA3. Regards, Mayank

Thanks !

Ticket Name: CCS/TDA2: CCS5.4 crashes when launching the target configurations ( Vayu simulator, ubuntu 14.04)

Part Number: TDA2 Tool/software: Code Composer Studio Hi, I have installed CCS5.4 on ubuntu 14.04, along with the Vayu simulator. When I try to launch a target configuration with Vayu, sometimes CCS crashes without any error and the other times gives the following error. The same scenario happens for Windows as well. I tried making new target configurations but the results are the same. I had posted the same question on CCS forum, but they directed me to ask this in TDA2x. Can anyone please help me resolve this issue? Regards, Shruti Joshi

Hello, Can you try with the latest CCS device support? Download it from here and install it. Hopefully, that will fix the problem, if not we can dig further. processors.wiki.ti.com/.../Device_support_files Thanks, Alex

Hi Alex, I tried by installing the latest device support files, but I continue to see the problem. Can you please help me with that? One more query , on the device support files page, I downloaded the files for Automotive. But in the targetdb folder I do not see support files for module EVE. The error that I get is for EVE. Are there any latest packages available for EVE? Thanks, Shruti

Hello Shruti, That I was afraid of. Unfortunately, CCSv5 along with the simulators are not supported/outdated with the latest register. However, it may be possible to fix this. That particular error you see, can you find the to TMS700C4X_regid.xml and delete the vcop.xml references? see if that will work, or you can even replace the reference with <your install path>\ccs_base\common\targetdb\Modules\TDA2x\EVE1_VCOP.xml which is the latest xml. thanks Alex

Hello Shruti, Did you manage to solve your issue? Can we close this thread? thanks, Alex

Hi Alex, Sorry for the late response. Thanks a lot for the help. The issue is resolved and now the simulator is working fine. I had to remove some references from the 'vcop_sim_regs.xml' file as it was giving the same error for other registers as well. After these changes, the simulator started working. Below are the changes which I made: Will these changes affect any other functionality? Once again, thank you for helping me get this issue resolved. Thanks & Regards, Shruti

Hello Shruti, Shruti Joshi said: Will these changes affect any other functionality? Once again, thank you for helping me get this issue resolved. Sure no problem, glad you got it fixed and thanks for confirming. Regarding the deleted reference: No, the simulator work shouldn't be affected by this as far as I know. Basically, these references are linking to xmls that are used by the CCS register view to display those registers. So if you are using the register view, you won't see the deleted registers(well because they are missing anyway). Thanks, Alex

Ticket Name: Linux/TDA2-17: Creating tidl_param_jdetNet_ssd.bin and tidl_net_jdetNet_ssd.bin on PROCESSOR_SDK_VISION_03_06_00_00

Part Number: TDA2-17 Tool/software: Linux Hello, We have an installation of PROCESSOR_SDK_VISION_03_06_00_00 on UBUNTU 16.04 LTS - based on PROCESSOR_SDK_VISION_03_06_00_00_setuplinux.bin. The files tidl_net_jdetNet_ssd.bin and tidl_param_jdetNet_ssd.bin are located at PROCESSOR_SDK_VISION_03_06_00_00/ti_components/algorithms/REL.TIDL.01.01.03.00/modules/ti_dl/test/testvecs/config/tidl_models/jdetnet/ As we understand it - in order to create this files - we need to run the import tool on PROCESSOR_SDK_VISION_03_06_00_00/ti_components/algorithms/REL.TIDL.01.01.03.00/modules/ti_dl/test/testvecs/config/import/tidl_import_JDetNet.txt file. The problem is that there is no any caffe_jacinto_models/trained/image_detection directory within this installation, so - we can't create the files. Can you please help addressing this issue?

Hi Yoav, you need to clone this repository: please check chapter "3.6.4 Importing Caffe-Jacinto-Models" in PROCESSOR_SDK_VISION_03_06_00_00/ti_components/algorithms/REL.TIDL.01.01.03.00/modules/ti_dl/docs/TIDeepLearningLibrary_UserGuide.pdf Regards, Yordan

Hello Praveen & Yordan, Thank you for your fast response. I already cloned this repository , but couldn't find image_detection directory. The directories image_classification, image_segmentation are there, though. https://github.com/tidsp/caffe-jacinto-models/tree/caffe-0.17/trained shows the same results. Best regards, Yoav

Hi Yoav, You may have to update import config file with these GitHub paths to import detection models. Refer to below thread will help in this.. Thanks, Praveen

Ticket Name: Jacinto dra756apabcq1 uboot cannot be started.

Other Parts Discussed in Thread: DRA756, TDA2SX HI. SDK: PROCESSOR_SDK_VISION_03_05_00_00 Our original main chip is TDA TDA2sxbtqabcq1, and uboot can start normally, Now Jacinto dra756apabcq1 of pin to pin cannot be started. What needs to be modified

Hi gj y, Can you share the u-boot logs on your board? I want to know where exactly is the u-boot failing. Best Regards, Keerthy

If the SOC is tda2s, it will boot normally. If it is dra756, there is no log output。 Is there a difference between the configuration of dra756 and tda2sx bootmode? tda2sx bootmod config:

There should be no difference of boot setting between the two devices.

Ticket Name: TDA2EVM5777: Caffe Jacinto Input data channel

Part Number: TDA2EVM5777 Hello, The provided script has no toggle for using signle-channel images (grayscale) as input. What needs to be changed for training a SSD model that take a single channel images as input? Thanks, Wei Chih

Wei Chih, Frankly, I have not trained using gray scale images in Caffe - so i don't know. A workaround is - convert your images into 3 channels and save them - I think you can use Python packages such as opencv or PIL to do that. Best regards, Manu.

Ticket Name: TDA2HG: [OpenGL RGB ] What's the effect way to exchange the RGB data

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 Hi: we're working on visonsdk 3.08 ,recently, we integrate the transparent bottom feature of AVM, that we need to save the parts render texture by FBO. as the FBO is RGB texture, we use the YUV by glEGLImageTargetTexture2DOES and use export DMA to share data between ARM and GPU. per my understanding that RGB FBO and yuv texture can not be rendering together, that we have to change the yuv input from rgb input that all FBO and texture are same format if we change the YUV input from RGB input, then what's the efficent way to exchange the image data between arm and GPU？ Thanks

Hello, You can use YUV texture and render to RGB output. Are you facing any problems with rendering to RGB? Regards Hemant

Hi Hemant: Hemant Hariyani said: You can use YUV texture and render to RGB output yes， it's ok to do that, but later we need to render the YUV and RGB together as the camera input is YUV, that sound impossible. so we expect the convert the camera yuv to rgb by ourself, and then render all textures with RGB. in yuv we can use dmafd to exchange the data between CPU and GPU, and how about the RGB data?

Hello, Apologies for the late response. If you use YUV texture using TEXTURE_EXTERNAL_OES, the shader will receive RGB. This way, everything can be treated as RGB. Regards Hemant

Hi Hemant: Thanks! when OpengGL do converting the YUV to RGB, in glbind? or in shader program?

Hello, The conversion should happen in hardware when texture data is fetched by the shader code. Regards Hemant

Thread is unlocked now.

hi Karthik: thanks for unlocking. but i still don't understand how is the fbo usage; how can i create fbo and write NV12 format texture into the fbo? would you reply it? thanks.

YUV is input only. You can create an RGB fbo and use OpenGL ES to read YUV as an external texture. This will convert YUV to RGB. You will have to create an eglmage with EGL_LINUX_DMA_BUF_EXT and provide dmabuf parameters for NV12 Y/UV planes. Please note that the GPU cannot output YUV. If that is a requirement, you will have to "trick" the GPU and process YUV as two planes - Y plane as a single channel texture and UV plane as a dual channel texture. From GPU and application perspective, this is not YUV any more - you are just dealing with components (e.g R component and RG component). Hope this helps. Regards Hemant

You can create an RGB fbo and use OpenGL ES to read YUV as an external texture. This will convert YUV to RGB. You will have to create an eglmage with EGL_LINUX_DMA_BUF_EXT and provide dmabuf parameters for NV12 Y/UV planes. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- I have a question about create RGB fbo: create an RGB fbo: I still need to create an eglmage with EGL_LINUX_DMA_BUF_EXT and provide dmabuf parameters for RGB planes, is right? And i do like that. But the eglCreateImageKHR returned EGL_BAD_MATCH when I set EGL_LINUX_DRM_FOURCC_EXT attribute as FOURCC_STR("AR24"); Is the TDA2 don't support "AR24"? or RGB format use other FOURCC_STR? my sdk version is 3.06. if don't support ,do you have any other method? thanks

Hello, Are you still facing this issue? The suggestion was to create a YUV (NV12) EGLImage. Regards Hemant

Hello, In addition, Can you please look at the code here for reference? There are some examples on how to use YUV. You can refer to util/display-kmscube.c https://git.ti.com/cgit/glsdk/omapdrmtest/ Regards Hemant

thanks for replying, i have already resolved it about three or four month ago.

Ticket Name: TDA2E: Parameters to tweak for higher model sparsity during SSD stage-3 sparsity training

Part Number: TDA2E Hello, Sometimes during SSD's sparsity training, the weights' sparsity stuck at some point (0.32, etc) where keep training won't increase the sparsity level. Is there any suggestions on hyper-parameters tweaking to achieve higher model sparsity? Thank you, Wei Chih

Hi Wei Chih, Please check if this can help.. - Starting from this line, you can see several factors that affect sparsification: https://github.com/tidsp/caffe-jacinto/blob/caffe-0.17/src/caffe/proto/caffe.proto#L524 Starting with a value of sparsity_start_factor Starting from iteration: sparsity_start_iter And increasing by: sparsity_step_factor Once in every: sparsity_step_iter iterations Until it reaches: sparsity_target You can adjust these parameters to control how sparsity is induced. In order to reach sparsity target abruptly - set sparsity_start_factor to 0.7 and sparsity_target to 0.7 will try to induce 70% sparsity in sparsity_start_iter In order to reach sparsity target gradually - do more iterations if your sparsity_start_factor or sparsity_step_factor is small. Thanks, Praveen

Ticket Name: TDA2EG-17: TDA2EG-17: Split time for H.264 encode

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2 Hi, I try to make DVR use case on TDA2 platform. Record capture to h.264 file by Encode link. I using system command to get 1 minute file. System_linkControl(chainsObj.ucObj.NullLinkID, SYSTEM_CMD_STOP, NULL, 0, (Bool)TRUE); System_linkControl(chainsObj.ucObj.EncodeLinkID, SYSTEM_CMD_STOP, NULL, 0, (Bool)TRUE); System_linkControl(chainsObj.ucObj.EncodeLinkID, SYSTEM_CMD_START, NULL, 0, (Bool)TRUE); System_linkControl(chainsObj.ucObj.NullLinkID, SYSTEM_CMD_START, NULL, 0, (Bool)TRUE); But only first file will be normal. Other files can not play on PC (VLC media player) How to split h.264 encode result ? Thanks.

Hi, Please refer to the below thread Thanks Gaviraju

Hi Gaviraju, It's working. Result codes System_linkControl(chainsObj.ucObj.NullLinkID, SYSTEM_CMD_STOP, NULL, 0, (Bool)TRUE); EncLink_ChannelInfo params; params.chId = 0; System_linkControl(chainsObj.ucObj.EncodeLinkID, ENC_LINK_CMD_SET_CODEC_FORCEI, &params, sizeof(EncLink_ChannelInfo), (Bool)TRUE); System_linkControl(chainsObj.ucObj.NullLinkID, SYSTEM_CMD_START, NULL, 0, (Bool)TRUE); Thanks. Jay

Ticket Name: TDA2: TDA2/AM574x video stream encoder throughput

Part Number: TDA2 Hello, I ask myself how much throughput the encoder for video streams can be reached on TDA2/AM574x devices. I would like store up to 8 video streams which we presumably encode best to keep the memory requirements and bandwidth to the storage medium as low as possible. From the description of the SDK (processors.wiki.ti.com/.../Processor_Training:_Multimedia) is not clear for me exactly how many streams can be processed parallel or which coding scheme has which restrictions. If I understand correctly, the VPE is used as input to the encoding. It exists on the SoC once. In the VPE description, I found nothing about multiplexing input data. However, the VPE seems to use the DSP cores for some of the encodings and those are available more than one time on some of the the mentioned SoC's. So my question is if anyone has experience in encoding more than one videostream on the mentioned SoC's? Best Regards Markus

Hi, Yes, you can encode multiple video stream using different channels of 1 enc link. Currently 8 channel support is there. But keep in mind that IVA can only encode upto 1080p at 60FPS. Regards, Anuj

Ticket Name: Linux/TDA2E: Software design for connecting SOC to MMC1 to SD card

Part Number: TDA2E Tool/software: Linux When the SD card is taken out, the SOC does not need to read and write the SD card, so we want to configure the MMC1 port to be a zero-level output. But the information we learned is that the software can't configure pinmux as gpio, can't set gpio function, we want to confirm whether the information is correct? . How can we set the MMC1 port output zero level when the card is pulled? Our current hardware design: SD card VCC power supply is controlled by a controllable 3.3v, SOC MMC1 I / O power supply is supplied by SOC VDDSHV8, and SOC MMC1 port is used as SDBOOT function.

Hi, Which pin cannot be configured as GPIO? If the pinmux has an option for GPIO, the padconf be configured to use as GPIO. Regards, Vishal

Hi Vishal, It is not always configured as GPIO or SD/SDIO, but also needs to be switched as the TF card is inserted or removed. When the SD card is unplugged, we want to configure these pins first to exit the SD/SDIO signal mode， and then configure them to be low level output： W6, Y6, AA6, Y4, AA5, Y3 However, the SOC needs to detect the status signal that the SD card is reinserted, so this pin may still have the function of retaining the SD_CD signal : W7 We want to know if the software can implement the above functional description?

Hi Feng Xiaoyu, The omap_hsmmc driver in Linux Kernel does pinctrl operations based on speed modes (for IODELAY reasons). You can do something similar based on when card is inserted or removed. Regards, Vishal

Hi Feng Xiaoyu, Do you have any more questions on this? This support is not available currently in omap_hsmmc driver, you have to add the pinctrl operations needed for your design. Regards, Vishal

Ticket Name: TDA2EXEVM: How to get a single frame from camera?

Part Number: TDA2EXEVM Hi sir, As my previous thread ( ) I still not solve my problem, so I start a new post here. --- I'm using VIP way to capture image. Is it possible to do this: I'll set a flag. When the flag is false, the camera will drop all the frames. When the flag is true, a function will get frames until flag is set to false. If above case is possible, how can I do this via VIP capture link. Thank you, Gary

Gary, The VIP driver is a streaming model. As long as the application provide a frame for capture, the driver will capture it. If the application stops providing the buffer, the driver will drop the frames automatically. You should use this default behavior for achieving your usecase. Regards Sivaraj R

Hi, We haven't heard back from you on this and we hope you were able to solve your issue. We are closing this thread. If you have any more follow-up, feel free to raise another thread. Regards Sivaraj R

Ticket Name: TDA2EXEVM: Processors forum

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 This is actually a follow up question for E2E ticket - https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1000532/tda2exevm-communication-with-another-spi-slave/3736466 The above ticket was asked 7 months ago. We are now in integration and begin activating the SPI instance 0 to communicate with our slave device. We are hoping to have a small consultation time instead of asking questions thru E2E to minimize on the back and forth before a point is getting across. A half an hour call would do us a great deal and get us over the hurdle since our integration schedule is tight. Please respond to this ticket and let us know if our requested is granted. Thank you and looking forward to hearing from you.

Stanley Wrote in above e2e link in quote below: " If yes, radar SPI driver is implemented in ~/pdk_xx_xx_xx_xx/packages/ti/drv/vps/src/devices/radar_ar12xx/src/bspdrv_ar12xxMcspiCfgPriv.c. Only Utils_mcspiInit() is called from use case to add the McSPI instace to GIO device and configure crossbar for interrupt. The instance will be opened later by radar SPI driver in PDK. To configure radar, we use radar APIs from rl_sensor.c in ~/mmwave_dfp/ti/control/mmwavelink/src/rl_sensor.c, which has the callback hooked to radar SPI driver. " From what you said in quote above, the usecase application does not interact with the SPI driver directly (ie: it doesn't gain access to the commHdl of the SPI channel instance). Is there a way to gain access to the commHdl of a SPI instance so we can close its commHdl to free up channel resource for another SPI slave using the same SPI instance? Thank you.

Hi, I am looping in TDA2 experts to answer the above query. Khai Trinh said: We are now in integration and begin activating the SPI instance 0 to communicate with our slave device. Meanwhile, can you please share the details on what issues are you facing? Regards, Parth

Ticket Name: TDA2E: Searching TI solution

Part Number: TDA2E Other Parts Discussed in Thread: TDA2, TVP5147 Hi Team There is good new that we could DIN our device! RD need CVBS Decoder for TDA2! Is there NTSC(VGA) Video Signal [CVBS+, CVBS-] to BT656(8Bits) [D0~D7, PCLK, Hsync, Vsync], and adopt the Video conversion IC that I2C issues the control command? (The input of TDA2 is the requirement of CVBS Decoder, the mode of CVBS to BT656 (8Bits).)

Hi, Yes, you could check TVP5147 device. It supports CVBS input for NTSC/PAL signals and can convert into 8bit BT656 signal, which can be received by TDA2x. Regards, Brijesh

Ticket Name: PROCESSOR-SDK-DRA7X: How do we enable nfs server in busybox ?

Part Number: PROCESSOR-SDK-DRA7X Other Parts Discussed in Thread: TDA2 First of all, the first problem we encountered is that we do not have the busybox source code used by the DRA7X SDK. Therefore, we may need the source code that TI provides to our busybox, which contains the defconfig used by the DRA7X SDK. In summary, we hope TI will provide us with the following two things suitable for DRA7X. 1. defconfig 2. The source code of the busybox can be used with the defconfig provided by TI

Hi Allen, The busybox source code is provided as part of the Yocto - please check the oe-core/meta/recipes-core/busybox/busybox_1.29.3.bb for the reference to the original source code and also check the meta-arago layer for further details on the patches on top of busybox. All of these are provided as source. The defconfig is also part of the same set of recipes and you can look further into that. Regards Karthik

Hi Karthik, Thank you for your reply. So in the TDA2 project, have TI already introduced the Yocto system to manage the subsystem? It is not in the TDA4 project that TI start using Yocto to manage the subsystem? I started to participate in the TDA series of projects in a relatively late stage.

Hi Allen, Yes, even for the TDA2 we were using the Yocto system to build the filesystem. Please refer to the Vision SDK documentation to find the related sections for enabling you with this. Regards Karthik

Ticket Name: TDA2: Dose TDA2X have an autorun script?

Part Number: TDA2 Hi, I want TDA2X to be able to select sensor I specify and load SRV usecase automatically when power on. What do I need to do? \ Regards, Daniel

Hi, Do you want to enable in case of BIOS or Linux ? Regards Surya

Hi, Surya, Both of them are needed. Regards, Daniel

Hi Daniel, No such script is there But with few modifications i.e by disabling read char and hard coding the demo use-case number you can still do it In case of BIOS: ------------------------- 1. Define CHAINS_DISABLE_GET_CHAR in file chains_main_bios.c (under vision_sdk\apps\src\rtos\common) 2. Copy the SRV UC config (refer chains_main_bios_multi_cam.c --> switch case 2) inside below block in file chains_main_bios_viison.c (under vision_sdk\apps\src\rtos\common) #ifdef CHAINS_DISABLE_GET_CHAR #endif 3. Rebuild the vision_sdk In case of Linux: ------------------------- 1. Instead of ch = getchar() in file chains_main.c (under vision_sdk\apps\src\hlos\adas\src\common) hard code the demo use-case number ch = 2 (to select mulicam uc ) ch = 3 (to select srv uc) 2. Rebuild the vision sdk Regards Surya

Hi Surya, Thanks for your reply. I will try it. Regards, Daniel

Ticket Name: RTOS/TDA2: genereate inHeader(.hdr) file

Part Number: TDA2 Tool/software: TI-RTOS Hi, I'm using TDA2x to run the usecase null Src Dec Display and TIDL Object detection using my own input data, every time I run the usecase I got the Decode Error, after reading some other threads from this forum, I noticed that my hdr file contains only zeros which probably cause the Decode Error.(Part of the error is shown below) [IPU1-0] 29.926554 s: DEC_LINK: outArgs->viddec3OutArgs.extendedError for channel 0 Error: 0x4400 [IPU1-0] 29.926645 s: DEC_LINK: Sequence called number 1 [IPU1-0] 29.959403 s: DECODE: ERROR: ALGPROCESS FAILED (status=0x00004400) !!! [IPU1-0] 29.959525 s: DEC_LINK: outArgs->viddec3OutArgs.extendedError for channel 0 Error: 0x4400 [IPU1-0] 29.959616 s: DEC_LINK: Sequence called number 2 The OS I'm using is Win7 and I compiled my VSDK using MAKECONFIG=tda2xx_evm_bios_all, I download a sizeBin.exe from other thread but it's not working, so how can I generate my own input data to get the usecase to work? Thanks~!

Hi Lyra, can you share how you generated the header file? Also please check if this post can help you: e2e.ti.com/.../2401993 Regards, Yordan

Hi Yordan, I found out what's wrong and I've got solution. Thanks for your reply. Just remove the string " size=" from the size_extracted.txt and then generate the .hdr

Ticket Name: Linux: USB 3.0 device tree configuration

Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hi, We have custom tda2px board and want to enable USB 3.0 in device tree. This is schematic for USB module: I have 5V on VBUS on CN8. Is everything ok with schematic? If everything is ok which changes should I implement in device tree to enable this module? Regards, Suzana Komarcevski

Hi Suzana, One little comment about the schematic - USB2.0 data pins also need an ESD protection. Regards, Stan

Hi Suzana, Few questions: Looking at the schematics, it has the USB-A 3.0 receptacle. So we assume you are planning to have the USB Host mode functionality only. Is that correct? To comment on the device tree entries, Can you tell us which TI SDK release version are you using/referring. So that we can point you to the correct file to refer? Thanks, Praveen

Hi Praveen, Yes, you are correct. We are planning to have host mode functionality only. We are using PROCESSOR_SDK_VISION_03_03_00_00. Thanks, Suzana

Hi Suzana, I am assuming that along with the PROCESSOR_SDK_VISION_03_03_00_00,you are using one of the TI Linux SDKs to run the Linux OS on the A15 core. If this is correct, then the device tree files can be found in the the Linux Kernel path ./arch/arm/boot/dts. Please identify the correct dts files to use for your platform. Please refer the vision sdk release documentation for this information. For USB1 DT entry example: Refer to dra7.dtsi file - Search for the section start with line: omap_dwc3_1: omap_dwc3_1@48880000 { The only change required for your case is: dr_mode = "host"; Thanks, Praveen

Hi, I made following change in dra76-evm.dts but usb device is not detected: &usb1 { dr_mode = "host"; }; When I plug in usb 2.0 (4GB) this is the output of lsusb and lsblk commands: Do I need to set USB1_DRV_VBUS as GPIO in oreder to get 5V output? Do I need to use extcon driver? Regards, Suzana

Suzana, In your initial post you said: "I have 5V on VBUS on CN8. ". Did you mean "I don't have..."?

Stanislav, I have 5V when I change muxmode for USB1_DRV_VBUS to 14. Sorry, my mistake, I did not explain well.

Suzana, The default muxmode 0 for USB1_DRVVBUS is sufficient to get the VBUS ON. Once the USB1 is configured in host mode, the usb1_drvvbus line is asserted such that it enables the external charge pump/power switch. There is no need to configure it is as GPIO (muxmode 14). In your case, extcon driver is not need. This is only required if there is a need for vbus detect and/or ID detect logic. In the attached schematics we does not see that this is present. Since your need is to have the USB1 is host mode only, this is not necessary. For more detailed undersanding, please refer the "Figure 24-142. SuperSpeed USB Controller Application: USB3.0 DRD" of the TDA2 TRM. Regarding the usb device not getting detected , have you made sure that the clock and power to the USB2 PHY are properly taken care? Can you share the kernel log by running "dmesg"? Thanks, Praveen

Praveen, I refered to Linux_kernel _path/arch/arm/boot/dts/dra72-evm-common.dtsi and made similar changes in dra76-evm.dts:     extcon_usb1: extcon_usb1 {
		    compatible = "linux,extcon-usb-gpio";
		    id-gpio = <&gpio6 12 GPIO_ACTIVE_HIGH>;
	    };

&dra7_pmx_core {
	gpio6_pins: gpio6_pins {
		pinctrl-single,pins = <
			0x280 (PIN_OUTPUT_PULLUP | MUX_MODE14)
		>;
	};
};

&gpio6 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&gpio6_pins>;
};

&omap_dwc3_1 {
	status = "okay";
	extcon = <&extcon_usb1>;
};

&usb1 {
	dr_mode = "host";
}; This resolved my issue. From your previous post I conclude that this is the wrong way but it works in my case, so my question is should I leave it like this or not? Thanks, Suzana

Suzana, Good to know that the issue is resolved. Would like to leave the decision to you if you want to go with this or analyze further why this works. In case, you are happy with the resolution, suggest you to close this thread. Thanks, Praveen

Ticket Name: Linux/TDA2: TDA2xx\linux build my own usecase

Part Number: TDA2 Tool/software: Linux i am a newer to learn TI\TDA2xx ， i have write a new usecase ，the config file is： UseCase: chains_newTestDisplay NullSource (A15) -> Decode -> Alg_FrameCopy (A15) -> VPE -> Display and i refer to the example of chains_nullSrc_Display.c to write my chains_newTestDisplay.c file typedef struct { UInt32 NullSourceLinkID; UInt32 IPCOut_A15_0_IPU1_0_0LinkID; UInt32 IPCIn_IPU1_0_A15_0_0LinkID; UInt32 DecodeLinkID; UInt32 IPCOut_IPU1_0_A15_0_0LinkID; UInt32 IPCIn_A15_0_IPU1_0_0LinkID; UInt32 Alg_FrameCopyLinkID; UInt32 IPCOut_A15_0_IPU1_0_1LinkID; UInt32 IPCIn_IPU1_0_A15_0_1LinkID; UInt32 VPELinkID; UInt32 DisplayLinkID; NullSrcLink_CreateParams NullSourcePrm; IpcLink_CreateParams IPCOut_A15_0_IPU1_0_0Prm; IpcLink_CreateParams IPCIn_IPU1_0_A15_0_0Prm; DecLink_CreateParams DecodePrm; IpcLink_CreateParams IPCOut_IPU1_0_A15_0_0Prm; IpcLink_CreateParams IPCIn_A15_0_IPU1_0_0Prm; AlgorithmLink_FrameCopyCreateParams Alg_FrameCopyPrm; IpcLink_CreateParams IPCOut_A15_0_IPU1_0_1Prm; IpcLink_CreateParams IPCIn_IPU1_0_A15_0_1Prm; VpeLink_CreateParams VPEPrm; DisplayLink_CreateParams DisplayPrm; } chains_newTestDisplayObj; But when i run my usecase on the HW environment，it crashed ，the info is： [HOST] [HOST ] 806.707100 s: IPC_OUT_0 : Create in progress !!! [HOST] [HOST ] 806.707161 s: IPC_OUT_0 : Create Done !!! [HOST] [IPU2 ] 806.707344 s: IPC_IN_0 : Create in progress !!! [HOST] [IPU2 ] 806.708534 s: IPC_IN_0 : Create Done !!! [HOST] [IPU2 ] 806.708930 s: DECODE: Create in progress ... !!! ASSERT (frameCopyLink_algPlugin.c|AlgorithmLink_frameCopyCreate|369) [HOST] [HOST ] 806.938479 s: IPC_IN_0 : Create in progress !!! [HOST] [HOST ] 806.938937 s: IPC_IN_0 : Create Done !!! [HOST] [HOST ] 806.938998 s: ALGORITHM: Create in progress (algId = 0) !!! [HOST] [IPU2 ] 806.934697 s: DECODE: Creating CH0 of 1280 x 720 [1] [0],target bitrate = 10000 Kbps ... I want to know the rules and more details of how to write the file of chains_nullSrc_Display.c，Is I missing some functions in chains_nullSrc_Display.c？ when i change my ALG（Alg_FrameCopy），How to modify my file of chains_nullSrc_Display.c？ Looking forward to answering me，thank you very much！

Hi , Please refer the frame copy usecase and set the required framecopy alg id in usecase. vision_sdk\apps\src\rtos\usecases\vip_single_cam_frame_copy Regards Chetan.M

Ticket Name: PROCESSOR-SDK-TDAX: Capture raw radar data by RVP-TDA3X

Part Number: PROCESSOR-SDK-TDAX Other Parts Discussed in Thread: TDA2 Hi supports, We are working on development of radar system by RVP-TDA3X. And I want to capture raw data via ethernet. Firstly, I generated new usecase as below config. IssCapture -> Select -> NetworkTx (IPU1_1) And, I tried to capture by your sample code for TDA2 cascade radar. (save 'dataArray' on line 882) as blow. ...\PROCESSOR_SDK_RADAR_03_08_00_00\vision_sdk\apps\src\rtos\radar\src\usecases\cascade_radar_object_detect\radar_cascade_demo.m I used default radar parameter (width:128,height:128,15fps) for raw dara capturing. But packet loss seems to occur. So, I decreased data size (width:32,height:32,1fps) and captured again. It seems that there is no packet loss but data size is very large(more than 700KByte). I understand the data size of radar cube would be 49152Byte (2byte×2(IQ)×3(Tx)×4(Rx)×32(width)×32(height)). Therefore 'dataArray' in your sample code should be 49152Byte. Is my understanding correct? If correct, let me know why are data size so big? Regards, Kazuki

Sorry, I attached image again,

Can anyone give me a comment? Regards, Kazuki

Hi, Cascade Radar script is for Cascade Radar EVM to capture object data. You can use ~\vision_sdk\apps\tools\network_tools\bin\network_rx.exe for capturing raw data from RVP. Refer to the user guide under ~\vision_sdk\apps\tools\network_tools\docs for how to use the tool.

Ticket Name: TDA3XEVM: TDA3X RJ45 video output

Part Number: TDA3XEVM For TDA3X EVM board, there is a RJ45 connector, I would like to use this RJ45 interface to output video streaming, how can I do ? do I need video codec? thank you! Steven

Steven, You mean over ethernet? We dont have exact usecase. rgds, Brijesh

Brijesh: how about TDA2x or TRA4x ? can I use them to output video streaming from Ethernet to other equipment with Ethernet interface? thank you! steven

I find Ethernet connector RJ45 on TDA2x/3z/4x EVM board on following photos, I would like to know if I can use this Ethernet interface to output vidieo streaming to other equipment. Thank you! stevenictures,

Hello Steven, Sorry for pitching late. Would like to know your use-case in detail for TDA3xx. We can check if it can be supported in TDA3 without the video codec.

Ticket Name: TDA2: Radar SDK v3.3 usecase generation tool error

Part Number: TDA2 Hi, I am trying to use the Usecase generation tool to create the .jpg file in radar SDK. I am using the following command to create these files(usecase_name.priv.c , usecase_name.priv.h, usecase_name.jpg files) Command is: vsdk_win32.exe PATH_TO_USECASE_FOLDER/usecase.txt -img -file -path PATH_TO_USECASE_FOLDER/ I was able to create all the files successfully in Vision-SDK, But here I came across with an error saying about the compatibility issue since my system is of 64 bit. (Didnt come across this error while in Vision-SDK ) When I use vsdk_win64.exe trying with the same command, jpeg file is not created and the rest of the files are being created. And when I use executable "vsdk_win32.exe" present in visionSDK 3.2 and provide the usecase of RADAR-SDK , the jpeg is being created. Command is: vsdk_win32.exe PATH_TO_USECASE_FOLDER_IN_RADAR-SDK/usecase.txt -img -file -path PATH_TO_USECASE_FOLDER_IN_RADAR-SDK In all the cases I have set the PATH to the Graphviz tool. I do not understand what is the issue with the RADAR-SDK's vsdk_win32 .exe Thanks & Regards, Varsha

Varsha, The usecase generation tool is the same between Processor SDK Radar and Processor SDK Vision. The summary of the question I am understanding from 3.2 release to 3.3 release you are seeing a difference in the behavior. I will ask one of my collegues to check this and get back to you. Regards, Piyali

Hi Varsha, We followed procedures mentioned by you & we didn't face any issues Below are few more experiments we did & no issues observed Exp1: cmd prompt - 32 bit UC gen tool - 32 bit cmd - vsdk_win32.exe PATH_TO_USECASE_FOLDER/usecase.txt -img -file -path PATH_TO_USECASE_FOLDER/ observation - no issues Exp2: cmd prompt - 32 bit UC gen tool - 64 bit cmd - vsdk_win64.exe PATH_TO_USECASE_FOLDER/usecase.txt -img -file -path PATH_TO_USECASE_FOLDER/ observation - no issues Exp3: cmd prompt - 64 bit UC gen tool - 64 bit cmd - vsdk_win64.exe PATH_TO_USECASE_FOLDER/usecase.txt -img -file -path PATH_TO_USECASE_FOLDER/ observation - no issues Could you please check once in your end & let us know your observations Are you still facing issues ? Regards Surya

Hi Surya, Thanks for the informative reply. Are these observations made by using vsdk_win32.exe present in Processor VisionSDK version-3.2? I faced no issues when I was using the tool from VisionSDK. But when I tried the same thing in RadarSDK version-3.3 I faced issues with the tool present in RadarSDK. And my windows versions is of 64-bit These are my experiments: Exp 1:vsdk_win32.exe present in VisionSDK UC generation tool: 32 bit command: vsdk_win32.exe PATH_TO_USECASE_FOLDER_IN_VisionSDK/usecase.txt -img -file -path PATH_TO_USECASE_FOLDER_VisionSDK observation: No issues Exp2: vsdk_win32.exe present in RadarSDK UC generation tool: 32 bit command: vsdk_win32.exe PATH_TO_USECASE_FOLDER_IN_RADARSDK/usecase.txt -img -file -path PATH_TO_USECASE_FOLDER_IN_RADARSDK observation: compatibility issues Exp3: vsdk_win32.exe present in VisionSDK and usecase in RadarSDK UC generation tool: 32 bit command: vsdk_win32.exe PATH_TO_USECASE_FOLDER_IN_RADARSDK/usecase.txt -img -file -path PATH_TO_USECASE_FOLDER_IN_RADARSDK observations: works fine. jpg file also created. Exp 4: vsdk_win64 in vision SDK UC generation tool: 64 bit command: vsdk_win64.exe PATH_TO_USECASE_FOLDER_IN_RADARSDK/usecase.txt -img -file -path PATH_TO_USECASE_FOLDER_IN_RADARSDK observations: All files are created except .jpg file Thanks & regards, Varsha

Hi Varsha, For Exp2, Could you please check with the binary file "vsdk_win32" present under "apps\tools\vision_sdk_usecase_gen\bin" folder (Don't use the binary file "vsdk_win32" present under "build\rtos\scripts" folder ) For Exp4, Regarding UC generation tool 64 bit, did you recompile the src on a 64 bit machine & generate the "vsdk_win64" or how is it ? Regards Surya

Hi Surya, For Exp2, I tried with the binary file from the folder you suggested. But still I encounter the same error. For Exp4, I did not recompile it. I downloaded it from one of the threads in the e2e forum. I also read about the following command to manually create the jpg file: dot chains_new_usecase_img.txt -o chains_new_usecase.jpg Thanks & regards, Varsha

Hi Varsha, Could you please try with attached binary file "vsdk_win64" ? vsdk_win64.zip Regards Surya

Hi, Yes, This worked!!! But, why 32 bit file of RADAR SDK gives an error and not of Vision SDK? regards, Varsha

Hi Varsha, Can you try building the use-case gen tool ? Please refer UG under "apps\tools\vision_sdk_usecase_gen\docs" folder Regards Surya

Ticket Name: TDA2EVM5777: I am getting I2C error please do help i am stuck here for more than a month

Part Number: TDA2EVM5777 [HOST] [IPU2 ] 72.047215 s: CHAINS: Sensor create in progress [HOST] [IPU2 ] 72.050173 s: VIDEO_SENSOR: INST0 : I2C1 : I2C Addr = 0x30 [HOST] [IPU2 ] 72.051698 s: src/bsp_deviceI2c.c @ Line 789: [HOST] [IPU2 ] 72.051820 s: I2C1: DEV 0x30: RD 0x300a ... ERROR Here is our error!!! [HOST] [IPU2 ] 72.052125 s: src/bsp_deviceI2c.c @ Line 862: [HOST] [IPU2 ] 72.052217 s: I2C1: Error timeout 1 ms!!! [HOST] [IPU2 ] 72.053528 s: Assertion @ Line: 512 in /home/ee212844/Desktop/PROCESSOR_SDK_VISION_03_08_00_00/vision_sdk/apps/src/rtos/video_sensor/src/vid_sensor.c: status == SYSTEM_LINK_STATUS_SOK : failed !!!

This is failing in trying to configure one video sensor, can you check which video sensor you are using and if it is properly mounted? Please refer to vision sdk user guide for more details. Regards, Brijesh

Hi Brijesh, Thank you for responding. We have checked the video sensor it is working fine but don't know how to configure I2C, as there are many dts files and its confusing. If you have any idea please do help. we are following the vision sdk user guide only. For you reference we are getting this error mentioned in the below link https://e2e.ti.com/support/processors-group/processors/f/processors-forum/770984/rtos-tda2-i2c-error-using-sat0089-daughter-board-after-connecting-ov10635-camera-module Looking forward for your reply.

Hi Sankalp, Not exactly sure where the issue is. Are you able to talk with deserializer over i2c? If you probe i2c lines, do you see deserializer probed correctly? Lets first check if deserializer and then if serializer is working fine. Regards, Brijesh

Ticket Name: TDA2: SD-Card booting: Jumping to MPU CPU0 Application

Part Number: TDA2 Hello, I included into Vision SDK a new Link and Usecase. With the Debugger the Code works fine. I tried to boot from an SD card. The TDA2 only works until "Jumping to MPU CPU0 Application..." appears in the Terminal. The whole Terminal output is shown below. The SD card works, I tried a functional Appimage and everything was fine. I am not sure in what could be wrong. Is there anything I have to add in the Imagegenerator when I include a new Usecase? Vayu SBL Boot AVS class-0 has been completed already DPLL configuration completed PRCM clock domain force wake-up completed PRCM module enable completed TI tda2xx evm pad configuration completed DDR3 configuration completed AppImage download begins WARNING: Device Id Doesnot match MPU CPU0 image load completed IPU1 CPU0 image load completed IPU1 CPU1 image load completed DSP1 image load completed DSP2 image load completed EVE1 image load completed EVE2 image load completed EVE3 image load completed EVE4 image load completed SBL boot completed succesfully **************SBL Boot-up clock cycles******************* PMCCNTR counts once every 64 clock cycles. To get actual CPU cycle multiple by 64 VM init clock cycles - 416436 soc prcm init clock cycles - 184688 ddr3 init clock cycles - 35867 appImage load clock cycles - 35223999 slavecore bring-up clock cycles - 14292 sbl total boot-up clock cycles - 35946449 ***************************************************************** Flush DCache... Putting CPU1 in OFF... Jumping to MPU CPU0 Application...

Hi Julian, It seems as if IPC attach did not happen. Can you connect CCS and see which core has died? Regards, Rishabh

Hi Rishabh, I can connect CCS and load the Code in Debuge Mode. There every core looks fine and the Programm is Code is working. Is there any other methode in CCS to see which core died, when I use SD card booting? Regards, Julian

Hi Julian, Can you share a screenshot of CCS when all CPUs are connected. Make sure that you load symbols for all CPUs. Regards, Rishabh

Hi Rishabh, I loaded a Program on every core. Whats the difference between load a symbol and a Programm?

Hi Julian, Are you using the same binaries to create application image when SD boot fails? In order to debug boot failure issue you should try SD boot and then load symbols for individual CPUs to identify the problem. Regards, Rishabh

Hi Rishabh Yes I use the same binaries to create the application image when SD boot fails. Regards, Julian

Hi Rishabh, I am now loading symbols while booting from the SD card. I can not connect to the EVE cores in the Debugger. The screenshot shows what I can see in the Dubugger.

Julian, Have you removed gels before connecting? Regards, Rishabh

No I didn't remove the gels before connecting.

Can you remove the gels and load symbols again to identify the reason. Regards, Rishabh

Where can I find the gels? Regards, Julian

Julian, You need to right click on the CPU, choose "Open Gel Files View" and then remove gels. This will not change the target configuration permanently. Alternatively you can modify the target configuration itself. Double click on target configuration. Go to advanced tab and remove initialization script. Regards, Rishabh

Ok i removed the Gel before connecting with the Cores. EVE2 is still not connectible. The Screenshot shows the other Cores loaded with the symbols.

Hi Julian, From this we know that EVE2 is having some problem. To confirm this you should disable EVE2 and then try the boot. The boot should work. Then you need to analyze what exactly EVE2 is doing after coming to main. What are the changes you have made that can cause EVE2 to crash. Does it need some additional MMU mapping? Regards, Rishabh

Ticket Name: CCS/TDA2: How to Configure the GPU

Part Number: TDA2 Tool/software: Code Composer Studio Dear i want to work on the GPU in TDA2x. please help me how i can configure GPU for the device TDA2x.

Hi, The programming model for GPU is via standard OpenGLES API. In addition, the GPU driver is available on Linux and can be exercised only from A72. Please let us know if you have some other question. Regards, Anand

Thank you for reply Anand. i am using TDA2x SOC and this SOC only cortex a15, cortex M4. soc does not have any A72 core .

Hi, Sorry for the typo. I meant the Cortex-A core on this device which is A15. The programming model for GPU is via standard OpenGLES API. In addition, the GPU driver is available on Linux and can be exercised only from A15. Did that answer the question? If you have further questions, please elaborate on exact needs. Regards, Anand

Hi, I want to start working on OpenGL ES API using LINUX platform. Please guide me through the procedure to set up OpenGL ES API on LINUX and how to further use its functionality. If possible, please explain with an example. Regards

Hi, Can you please open a E2E new thread? The original question was on CCS and I believe it has been answered. Regards, Anand

Ticket Name: Compiler/TDA2SG: how can the tda2 support LCD output BT656 ,BT1120

Part Number: TDA2SG Tool/software: TI C/C++ Compiler HI, LCD default output Is LVDS 。How can it support BT656，BT1120，what I Need to do？

I see the detail Connect TDA2S to ADV7393, but I have a question about adv7393 support Input RGB444, TDA2S output format is RGB555,how can it work?

Hi, You could find AppNote explaining how to interface ADV7393 with TDA2x at http://www.ti.com/lit/an/sprac23a/sprac23a.pdf. Rgds, Brijesh

but I have a question about adv7393 support Input RGB444, TDA2S output format is RGB555,how can it work?

Hi Zhangsc, I think RGB444 is not supported ADV7393. Could you please check again? Rgds, Brijesh

Ticket Name: RTOS/TDA2: How to make changes in algorithm kernel work?

Part Number: TDA2 Tool/software: TI-RTOS I change kernel code in ti_components/algorithms/eve_sw_01_19_00_00/kernels/imgsiglib/Filter/src_kernelC/vcop_filter_kernel.k file and build successfully. I checked the built file ti_components/algorithms/eve_sw_01_19_00_00/kernels/lib/debug/libevekernels.eve.lib, and it is updated. After that, I build with "make -s -j depend" and "make -s -j" successfully. But the changes in kernel doesn't work. The result is the same as before. How can I make the change in kernel work? Thanks! BRs Derek Yang

Find I change wrong function. :(

Hi Derek, I am glad to hear that the issue is resolved and thanks for updating the thread! Regards. Yordan

Ticket Name: Linux/TDA2: VIP Configuration For Linux

Part Number: TDA2 Tool/software: Linux Hello everyone, I am working on DRA74x EVM REV H.0 board with vision SDK 3.04 in Linux, I want to connect four cameras in the ports vin1a,vin2a,vin6a,vin1b respectively in 8 bit mode. 1. What all are the changes to be done for this in Linux ? 2. I want to change SerDes config. How it can be possible? 3. Can i follow the "Video Driver Porting Guide for TDA2xx, TDA2Ex and TDA3xx" for Linux side changes? It would be greateful if you share an example ( how to set vin1b port instance/capture) Regards, Renjith

Hi Renjith, "Video Driver Porting Guide for TDA2xx, TDA2Ex and TDA3xx" is for RTOS drivers and not applicable to linux. I will loop in linux experts to answer other questions. Regards, Rishabh

Hi Renjith, Please clarify if you plan for using Linux drivers or the RTOS drivers. For vision use cases, TI receommends to use all capture drivers from RTOS/PDK Nikhil D

Hi Nikhil, I want to use the vision use cases. But system should run in Linux. Can i use the PDK drivers for Linux ? Could you tell me which all are the possible ways? Regards, Renjith

Hi Renjith, You can use the Vision SDK linux for this where you run the linux on A15 but your VIP driver will still run on IPU. Regards, Rishabh

Hi, My actual need is connect four cameras in the ports vin1a,vin2a,vin6a,vin1b respectively in 8 bit mode. 1. What all are the changes to be done for this in Linux ? 2. I want to change SerDes config. How it can be possible? could you help ? Regards, Renjith

Hi Renjith, No changes required in Linux. Make sure to add the right pinmux values in u-boot. All the camera and serdes configuration is handled in the PDK drivers NikhilD

Hi, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Rishabh

Ticket Name: Linux/TDA2-17: AVB surround view, Ethernet switch band width issue.

Part Number: TDA2-17 Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hi Sir, I am running AVB surround view case. There are 4 AVB cameras through a 100/1000 base Ethernet switch to connect to TDA2 EVM. My AVB camera uses 100 Mbps phy to transmit the data. Because of this Ethernet switch limit, when connecting camera with 100 Mbps data rate, All switch port becomes 100Mbps band width. It means if amount data rate of 4 cameras is over than 100 Mbps, Ethernet switch can't handle it. May you suggest which "Ethernet switch" can handle 100 Mbps camera input and output 1000Mbps at the same time? May provide the product brand and part number. Thank you. Ranny.

Hi Ranny, On the TDA side, we support upto 1Gbps datarate. There shouldn't be any issues on that. Regarding the Ethernet switch problem you've mentioned, it seems rather strange, as I have never came across this rate limiting on the ports. I'm afraid we can't provide product brand or related information. I would suggest to use the TI Ethernet Surround View Board for your usecase, which wouldn't require you to use off the shelf ethernet switches. Regards, Anand

Ok, I got. Thank you very much. Ranny.

Hi Sir, May you provide website or web link of " TI Ethernet Surround View Board" to me? Thanks. Ranny.

Hi Ranny, Will you be interested in the purchase of the board or do you just want to review the specifications of the board? Regards, Anand

Hi Anand, I just want to review the specifications of the board, we will put the Ethernet switch circuit and TDA2 platform together on our own design PCB. Thanks. Ranny.

Ticket Name: TDA2EXEVM: TIDL import Warning: TIDL_ConvolutionLayer, paramater combination has gone with limited validation

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi, I have the following warning when converting a customized onnx model to TIDL format. WARNING: [TIDL_ConvolutionLayer] Conv_11 Layer paramater combination has gone with limited validation and may have some issues. Following are the parameters Kernel 5x5 Stride 1x1 dilation 1x1 Pad 0x0 Bias 1 According to the documentation of TIDL (Jacinto 7 Version: 01.02.00), the Kernel Size passes the validation: TIDL_ConvolutionLayer:

Regular & depth-wise conv will be imported as conv.
For TF and tflite DepthwiseConv2dNative, depth_multiplier shall be 1 in Number of input channels > 1.
ReLU & BN & Pooling will be merged into conv to get better performance. 1x1 conv will be converted to innerproduct.
Validated kernel size: 1x1, 3x3, 5x5, 7x7,1x3,3x1,1x5,5x1,1x7,7x1.
If stride == 4, only supported kernel == 11x11.
if stride == 2, kernel should be less than 7. Even dimensions of kernel like 2x2, 4x4, 6x6 are not supported.
Depthwise Separable Convolution only supports 3x3,5x5,7x7 with stride 1 and 3x3 with stride 2.
Its recommended to have kernelH*kernelW*input channel/groupNum+enableBias % 64 == 0 whereever possible as it results into better utilization of hardware. I have tried to change dilation, padding, stride and Bias and the Warning remains. Only reducing the Kernel to 3x3 solves the Warning. Shouldn't a 5x5 Kernel be valid? What is wrong with my parameter combination? Best Regards Gildardo

Hi Gildardo, Are you using TDA2 EVM or TDA4 EVM ? kindly clarify because they use different code bases. Thanks, Praveen

Hi Praveen, I am using TDA4, it was linked to TD2 because I created the issue from "Ask a related question" Sorry for the confusion Best Gildardo

Hi Gildardo, The warning is mainly coming because this particular combination of parameters is not tested as part of our testing. But most likely it should work. Are you seeing any specific issue with this particular layer? Regards, Anshu

Hi Anshu, Thank you for your answer. I don't have a particular problem with the model . I have tested with the bare-metal application but I have not validated the correctness of the output yet. Could it be possible to enumerate the validated parameter combinations for kernel 7x7 so that I can get rid of the warning? Best Regards Gildardo

Hi Gildardo, Following is the terminology used here : Ni = number of input channels No = number of output channels G = number of groups NiPerG = number of input channels per group' NoPerG = number of output channels per group Fr = Kernel dimension in row ( 7 in this case) Fr = Kernel dimension in col ( 7 in this case) ) Currently following are the restriction of 7x7 kernels : 7x7 stride 1x1 : Supported 7x7 Stride 2x2 : Dilation 1x1 K = 1: currently natural C ( i.e. Not Optimized) K = 2: currently natural C ( i.e. Not Optimized) K = 3: optimized 8 bit tested, 16 bit K > 3: optimized Here K is NiPerG * Fr * Fc + bias ( if enabled) 7x7 Stride 2x2 : Dilation nxn ( n > 1 ) : Not supported. 3x3 5x5 7x7 with stride 1x1 and NiPerG = NoPerG = 1, You can also refer the following document to see the supported convolutions : Regards, Anshu

Ticket Name: RTOS/TDA2: Send i2c to camera

Part Number: TDA2 Tool/software: TI-RTOS I using TDA2x + multideserializer. My camera have Device Address 0x20 I modified as follow and tried to send i2c but unsuccessful. Can you please assist?

Hi Chee Peng, You will have to set BSPUTILS_OV1063x_I2C_ADDR to 0x10 also note that the sensor should be accessible at address BSPUTILS_OV1063x_1_ALIAS_I2C_ADDR, which is 0x38. Regards, Sujith

Hi Chee Peng, Is your query answered? Regards, Sujith

Yes. I can communicate with my camera thru i2c. Thank you

Ticket Name: PROCESSOR-SDK-TDAX: TDA2X

Part Number: PROCESSOR-SDK-TDAX Other Parts Discussed in Thread: TDA2 Question 1: Hello: when I was debugging the TDA2 driver, the file directory is as follows "PROCESSOR_SDK_VISION_03_05_00_00 / vision_sdk/apps/SRC/hlos/adas/SRC/usecases/disp_dist_src_display" The file VDRM_CRTC = 26 chains_dispDistSrc_Display. C, That is: PUcObj - > DispDistSrc_westonPrm. VDrmControllerObjectId = VDRM_CRTC; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * excuse me: VDRM_CRTC 26 here is how to determine?If HDMI LCD1, LCD2, and LCD3 are used, what should the vDrmControllerObjectId be assigned? Question 1: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * excuse me: if the HDMI LCD1 LCD2 LCD3 used, that here I am in terminal execution "weston - flower", how to specify the HDMI, LCD1 one shown on the screen? Root @ dra7xx - evm entry: ~ # Root @ dra7xx - evm entry: ~ # Root @ dra7xx - evm entry: ~ # Root @ dra7xx - evm entry: ~ # Root @ dra7xx - evm entry: ~ # weston - flower

Hi, can you check this document and see if it you can find the answers to your questions: Regards, Yordan

Hello, I just refer to the above link to do it. Now I output 4 channels, HDMI, lcd1/2, and adopt 4 independent VDRM. How do I specify weston-flower to be displayed in these 4 channels?Like HDMI, or LCD3? The document above did not seem to say!!!!! The document above did not seem to say!!!!! Here is my video card device： root@dra7xx-evm:/dev# ls -al vdr* crw------- 1 root root 246, 0 Sep 25 10:00 vdrm-controller-0 crw------- 1 root root 246, 1 Sep 25 10:00 vdrm-controller-1 crw------- 1 root root 246, 2 Sep 25 10:00 vdrm-controller-2 crw------- 1 root root 246, 3 Sep 25 10:00 vdrm-controller-3 root@dra7xx-evm:/dev# The following is the command I executed, which is displayed on HDMI. Now I want to display it on LCD2. What should I do? root@dra7xx-evm:/dev# root@dra7xx-evm:/dev# root@dra7xx-evm:/dev# weston-flower

Hi, I have forwarded your question to DRM experts for further help. (note that some delay in response due to the holidays in India might be expected) Regards, Yordan

Do you see weston background on the LCDs? Can you provide me the the output of "ls -l /dev", "ls -l /dev/dri" and "ls -l /dev/dri/by-path"? - Subhajit

Ticket Name: TDA2SX: Evaluation Module for TDA2SX

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2P-ACD, TDA2EVM5777, , TDA2E TI (Spectrum Digital) offers an evaluation module TDA2x Vision EVM Kit with part number TDA2EVM5777. I want to know whether its processor is TDA2P-ACD or TDA2S or TDA2H? I am interested in getting evaluation module based on TDA2S which has 4 EVE while others have 2 EVE. Regards

Hi, TDA2EVM5777 is a super set part and it has four EVEs. You can order this EVM for the purpose mentioned. Refer this for details - https://e2e.ti.com/support/processors/f/791/t/777316?TDA2EVM5777-Is-TDA2x-a-processor-or-evaluation-board-

Thanks for your reply. I did not know about the concept of Super set part number. Just for further knowledge, could you please further elaborate my following query: Question: Since TDA2S is super set part number. Is there any difference between part number TDA2S and X5777x? Although part number X5777x is mentioned in datasheet of tda2sx.pdf but never mentioned in "Mechanical Packaging and Orderable Information" section of the datasheet. So my question is whether both TDA2S and X5777x are same part numbers? If not, where can I find datasheet of X5777x part number? Regards, Dr. Imran Ali

Moreover, I guess that Pin configuration of following components is different: TDA2E, TDA2H, TDA2L, TDA2P, TDA2S. So how will X5777x serve as super set of this TDA2x family? If I purchase the development board based on X5777x, and later on I develop my own board based on any TDA2x component, I will have to make the schematic myself which would be very difficult task. Kindly reply me. Thanks in advance.

TDA2EVM5777 is a superset part for TDA2SX/TDA2HX etc. It is not for all TDA2x devices - specifically not for for TDA2Px. Since you are looking for TDA2Sx, you can go ahead with TDA2EVM5777. If you change the part number you need, please check an EVM for that specific part.

Ticket Name: RTOS/TDA2: H.264 low lantancy encode

Part Number: TDA2 Tool/software: TI-RTOS Hello, We are trying to enable low latency encoding by setting parameters for sliced mode on encoder link, but we keep getting errors in creation phase. Our video input is 1280x720. We are not sure about the slice size as well, so we are open to suggestions. Note: We are using TDA2xx chip and vision_sdk_2.12. This is what we changed so far: In usecase: pLinkChPrm->encodingPreset = SYSTEM_XDM_USER_DEFINED; pLinkChPrm->rateControlPreset = SYSTEM_IVIDEO_USER_DEFINED; In encLink_h264.c: staticParams->videnc2Params.inputDataMode = IVIDEO_NUMROWS; staticParams->videnc2Params.outputDataMode = IVIDEO_SLICEMODE; staticParams->sliceCodingParams.sliceCodingPreset = 1; //IH264_SLICECODING_USERDEFINED; staticParams->sliceCodingParams.sliceMode = 1; //IH264_SLICEMODE_MBUNIT; staticParams->sliceCodingParams.sliceUnitSize = 6; staticParams->sliceCodingParams.streamFormat = IH264_BYTE_STREAM; dynamicParams->videnc2DynamicParams.ignoreOutbufSizeFlag = XDAS_TRUE; dynamicParams->videnc2DynamicParams.getBufferFxn = enclink_h264_get_buffer_fxn; static XDAS_Int32 enclink_h264_get_buffer_fxn(XDM_DataSyncHandle dataSyncHandle, XDM_DataSyncDesc *dataSyncDesc) { dataSyncDesc->baseAddr = NULL; dataSyncDesc->numBlocks = 1;//gConfigOrg.numBlocks[block_count]; dataSyncDesc->varBlockSizesFlag = 1; dataSyncDesc->blockSizes = (XDAS_Int32*)Input_BlockSizeArray; return ENC_LINK_S_SUCCESS; } The error occurs at enclink_h264_control call with XDM_SETPARAMS. Thank you, Marijana

Hi Marijana, Please refer below sections in Encoder User Guide here: git.ti.com/.../docs Table 4-12: Default and Supported Values for IH264ENC_SliceCodingParams. Appendix G: Low Latency / Sub Frame Level Synchronization And Sample test application provided in the codec package @ path: ..\ivahd_h264enc_02_00_09_01_production\packages\ti\sdo\codecs\h264enc\app\test\src Please refer putDataFxn & getDataFxn implementation.

Ticket Name: TDA2SX: Link VLIB in visionSDK

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi, Where can I include VLib Libraries (common.lib, vlib.lib, vlib_cn.lib) to build on visionSDK2.10? I would like to to know which setting file to set these libraries. If I use VLib functions on frameCopyAlgoLocalDma.c, the build has link errors as follows: # Linking into C:/VisionSDK/VISION_SDK_02_10_00_00/vision_sdk/binaries/vision_sd k/bin/tda2xx-evm/vision_sdk_c66xdsp_1_release.xe66... warning: creating output section ".sram_start" without a SECTIONS specification undefined first referenced symbol in file --------- ---------------- _sram_start C:\VisionSDK\VISION_SDK_02_10_00_00\ti_components\algorithms_codecs \vlib_c66x_3_3_0_3\packages\ti\vlib\lib\common.ae66<VLIB_memory.oe66> error: unresolved symbols remain error: errors encountered during linking; "C:/VisionSDK/VISION_SDK_02_10_00_00/vision_sdk/binaries/vision_sdk/bin/tda2 xx-evm/vision_sdk_c66xdsp_1_release.xe66" not built gmake[6]: *** [C:/VisionSDK/VISION_SDK_02_10_00_00/vision_sdk/binaries/vision_sd k/bin/tda2xx-evm/vision_sdk_c66xdsp_1_release.xe66] Error 1 gmake[5]: *** [c66xdsp_1] Error 2 gmake[4]: *** [apps_dsp1] Error 2 gmake[3]: *** [apps] Error 2 gmake[2]: *** [apps] Error 2 gmake[1]: *** [vision_sdk_apps] Error 2 gmake: *** [vision_sdk] Error 2 Thanks, Kenshow

Hi, Kenshow, Your question has been forwarded to VSDK experts with a copy to VLIB expert. They will commnet directly here. Regards, Mariya

Hi you can list these libs in either \vision_sdk\build\makerules\rules_66.mk (if its some kernel libs) or \vision_sdk\examples\MAKEFILE.MK (if they are application specific libs) regards, Shiju

Hi Shiju, The default file of makerules_66.mk has already set the lib path. Also, should I add the path in \vision_sdk\examples\MAKEFILE.MK ? [vision_sdk\build\makerules\rules_66.mk] (Line-223): LIB_PATHS += $(vlib_PATH)/packages/ti/vlib/lib/vlib.ae66 (Line-224): LIB_PATHS += $(vlib_PATH)/packages/ti/vlib/lib/vlib_cn.ae66 (Line-225): LIB_PATHS += $(vlib_PATH)/packages/ti/vlib/lib/common.lib In this case, I just added vlib function into a file, C:\VISION_SDK_02_10_00_00\vision_sdk\examples\tda2xx\src\alg_plugins\framecopy\frameCopyAlgoLocalDma.c Should I set the lib path any more? and which file? Regards, Kenshow

Kenshow no, you do not need to add this in any other files. One more thing is, include the VLIB header file that defines these functions in framecopy\frameCopyAlgoLocalDma.c regards, Shiju

Hi Shiji, I had already defined the header. And, it seems link error. my AlgoLocalDma.c file is follows: --------------------------- : : #include <ti/vlib/src/common/VLIB_test.h> #include <ti/vlib/src/common/VLIB_memory.h> #include <ti/vlib/src/common/VLIB_profile.h> Int32 Alg_FrameCopyProcess(Alg_FrameCopy_Obj *algHandle, UInt32 *inPtr[], UInt32 *outPtr[], UInt32 width, UInt32 height, UInt32 inPitch[], UInt32 outPitch[], UInt32 dataFormat, Uint32 copyMode ) { Int32 rowIdx; Int32 colIdx; UInt32 *inputPtr; UInt32 *outputPtr; UInt32 numPlanes; UInt32 wordWidth; UInt32 lineSizeInBytes; UInt32 opt; uint16_t tccStatus; Alg_FrameCopyDma_Obj * pAlgHandle; pAlgHandle = (Alg_FrameCopyDma_Obj *)algHandle; // TEST VLIB LINK VLIB_cache_init(); : : --------------------------- Regards, Kenshow

The common.lib is intended to test VLIB in stand-alone, bare metal DSP environment. When you integrate VLIB into an application in VSDK, you don't need common.lib or the functions associated with them. For example, VLIB_cache_init() shouldn't be used if the VSDK has already initialized the cache, and VLIB_malloc() should not be used as this is just the testbench way of allocating memory. In your example above, you probably don't need VLIB_cache_init() or the 3 common header files you included. Is there some reason you feel that you need these?

Ticket Name: Linux/TDA2: PinMuxing in TDA2XX for linux

Part Number: TDA2 Tool/software: Linux Hi Everyone , I am working on Pin muxing for our custom board with respect to TDA2XX . Since we planned to run the board on linux system , I like to know where we can find files of Pin Muxing for LInux configuration . I am also referring to the below link : e2e.ti.com/.../2702399 but I could not find where we can do VIP port pinmuxing for linux . Is there any reference you can suggest to do the same .

Hi Surender, On IPU pin mux is done in board module and u-boot does the pin mux in linux. You can modify board/ti/dra7xx/mux_data.h as suggested by Nikhil in the mentioned thread. Kindly post follow up questions on the same thread instead of starting a new one. Regards, Rishabh

Ticket Name: TDA2EG-17: caffe-jacinto-models/script/train_image_object_detection.sh error

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2 Hi, After following installation instructions and solving some issue myself, when I tried to run the ./train_image_object_detection.sh to test my installation result, I got the error of: I0218 09:36:55.522869 14830 net.cpp:110] Using FLOAT as default forward math type I0218 09:36:55.522889 14830 net.cpp:116] Using FLOAT as default backward math type I0218 09:36:55.522899 14830 layer_factory.hpp:172] Creating layer 'data' of type 'AnnotatedData' I0218 09:36:55.522907 14830 layer_factory.hpp:184] Layer's types are Ftype:FLOAT Btype:FLOAT Fmath:FLOAT Bmath:FLOAT I0218 09:36:55.523039 14830 internal_thread.cpp:19] Starting 1 internal thread(s) on device 0 I0218 09:36:55.523171 14830 net.cpp:200] Created Layer data (0) I0218 09:36:55.523180 14830 net.cpp:542] data -> data I0218 09:36:55.523205 14830 net.cpp:542] data -> label I0218 09:36:55.523224 14830 data_reader.cpp:58] Data Reader threads: 1, out queues: 1, depth: 10 I0218 09:36:55.523243 14830 internal_thread.cpp:19] Starting 1 internal thread(s) on device 0 I0218 09:36:55.523627 14842 blocking_queue.cpp:40] Data layer prefetch queue empty F0218 09:36:55.523803 14843 db_lmdb.hpp:16] Check failed: mdb_status == 0 (2 vs. 0) No such file or directory *** Check failure stack trace: *** @ 0x7f7e0c8074dd google::LogMessage::Fail() @ 0x7f7e0c80f071 google::LogMessage::SendToLog() @ 0x7f7e0c806ecd google::LogMessage::Flush() @ 0x7f7e0c80876a google::LogMessageFatal::~LogMessageFatal() @ 0x7f7e0bb120ca caffe::db::LMDB::Open() @ 0x7f7e0b6936b3 caffe::DataReader<>::InternalThreadEntryN() @ 0x7f7e0b6bb19e caffe::InternalThread::entry() @ 0x7f7e0b6bcefb boost::detail::thread_data<>::run() @ 0x7f7e0ad007ee thread_proxy @ 0x7f7e098926db start_thread @ 0x7f7e09bcb88f clone @ (nil) (unknown) During make runtest, i did get some errors but I looked up online and someone mentioned these errors won't interfere training processes. But for debug references, they are: [----------] Global test environment tear-down [==========] 2101 tests from 283 test cases ran. (459627 ms total) [ PASSED ] 2094 tests. [ FAILED ] 7 tests, listed below: [ FAILED ] IOTest.TestDecodeDatum [ FAILED ] IOTest.TestCVMatToDatumReference [ FAILED ] IOTest.TestDecodeDatumNative [ FAILED ] LayerFactoryTest/0.TestCreateLayer, where TypeParam = caffe::CPUDevice<float> [ FAILED ] LayerFactoryTest/1.TestCreateLayer, where TypeParam = caffe::CPUDevice<double> [ FAILED ] LayerFactoryTest/2.TestCreateLayer, where TypeParam = caffe::GPUDevice<float> [ FAILED ] LayerFactoryTest/3.TestCreateLayer, where TypeParam = caffe::GPUDevice<double> Thank you for the time and assistance. Best regards, WeiChih

Hi, The following line is saying that your lmdb file (dataset file) could not be found: F0218 09:36:55.523803 14843 db_lmdb.hpp:16] Check failed: mdb_status == 0 (2 vs. 0) No such file or directory Please check the path.

Hi Manu, Thanks for the heads up, I am able to run training script on voc0712 dataset now, but also got some questions regarding training on my own custom dataset: 1. Am I able to modify the SSD's network and still run on TDA2 fine? e.g. simplifying base VGG net's structure to my custom dataset for detecting fewer classes like 2~5 classes rather than so many classes as in voc0712? 2. Does tda2 support running other networks like Yolo? Thanks a lot & best regards, Wei

Hi Wei, Yes - you can customize the number of classes other such similar parameters for the SSD object detector. Yolo is not supported. If you are running ./train_image_object_detection.sh, you are not using VGGNet - but a much simpler network. VGG is quite heavy for not only for TDA2x, but also for any embedded platform. Best regards,

Hi Manu, Thanks for the swift reply. So, tuning hyper-parameters of the SSD detector, and number of classes of course, is fine as long as no changes in the network structure from ./train_image_object_detection.sh, right? Best regards, Wei

Yes. That is fine.

Ticket Name: Linux/TDA2SG: About the electromagnetic compatibility of TDA2

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hello ， I have two questions: Q1: In addition to the EMI content mentioned in the data sheet, I would like to know if TI can provide some summary or recommendation for solving EMI problems. For example, the software code of the spread spectrum DDR3 , etc. Q2: Where can I find out the EMC test report for TDA2? Especially the part of the RE test.

Hello Feng, Spread spectrum is supported on the VOUT interfaces only. The suggested usage is documented in this app note: http://www.ti.com/lit/an/spraby0a/spraby0a.pdf Thanks, Kyle

Ticket Name: TDA2EG-17: Whether we can delete TDA2E-17 QSPI1_RTCLK signal when QSPI memory work at Mode 3?

Part Number: TDA2EG-17 Hi Expert: At TRM 24.5.2 table 24-355 gave the QSPI signal description. Because we are using spansion and Micron QSPI work at 4-bits QSPI mode. It is follow SPI mode 3. We want to remove the QSPI1_RTCLK signal ( pin H3 at TDA2E-17 ) , just connect QSPI1_SCLK signal to spainsion QSPI memory. Does it can work at TDA2E-17? Best Regards! han tao

Hi Tao, On TDA2-17x17 you also should not need to connect qspi1_sclk to qspi1_rtclk (in mode 3). Regards, Yordan

Hi Yordan: Thanks for help me confirm it. Best Regards! Han Tao

Ticket Name: TDA2: How to Updating latest vision sdk

Part Number: TDA2 Dear TI I just notice you are just release a newer visionsdk version 3.4. I am using 3.3 are you able to advise how is should update to this latest vision?

Hi Wilson, You should refer to release notes for the list of new features, upgrade and compatibility information, etc. The release notes can be downloaded here: software-dl.ti.com/.../VisionSDK_ReleaseNotes.pdf Regards, Rishabh

Dear Rishabh I mean i want to update my version from 3.3 to version 3.4. Can i just copy the file and replace with the old version just like that?

Hi Wilson, Have you made any changes on top of Vision SDK 3.3 or you are using default SDK. Regards, Rishabh

Dear Rishabh There is no changes but it compile to for see the demo

Hi WIlson, In that case you can just download SDK 3.4 and install it in a different folder as compared to SDK 3.3. By default the folders should be PROCESSOR_SDK_VISION_03_03_00_00 and PROCESSOR_SDK_VISION_03_04_00_00. Regards, Rishabh

Hi Wilson, Is this issue resolved? Can we close the thread. Regards, Rishabh

Yes i just close this

Ok thanks for the confirmation. Regards, Rishabh

Ticket Name: TDA2SX: caffe model compression and quantition

Part Number: TDA2SX whether the TDA2S importTool can process the NCNN converted caffe model files

Hi, No, it won't support. Please refer to "TI Deep learning Library Datasheet" for supported model types and supported layers. Thanks, Praveen

Ticket Name: TDA2: dsp and eve real-time control and algorithm partition

Part Number: TDA2 Hi , One question, is there any paper or link about how to code into both dsp and eve together? I mean some example code and the responding detailed paper. Even more, I want to run many tasks onto both dsp and eve, so how to partition so many task or algorithm to different cores？ Could you please show me the paper and code about what I am so interested in？ Looking forward to your reply！ Yours Lv

Any one can answer this question？

Hi, I can not provide you some paper but you can take refrence of some docs available with vision sdk and understand the MCFW framework. You have to develope your link which can run on both dsp and eve cores. For code you can refer to vision_sdk\apps\src\rtos\alg_plugins\tidl For docs vision_sdk\docs\Architecture vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_DevelopmentGuide.pdf Regards, Anuj

Ticket Name: Compiler/TDA2SX: I want to use GPU to accelerate my algorithm. Does tda2's GPU support opencl?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler I want to use GPU to accelerate my algorithm. Does tda2's GPU support opencl?

Which SDK are you using? PSDKLA / PSDKRA does not support openCL - Subhajit

Hi Subhajit, Thanks for your reply, I am using VSDK, but VSDK support only openGL on GPU, is there any way to use GPU to accelerate general algorithms？

Since we do not support OpenCL, there is no method to use the GPU to perform GPGPU tasks, and therefore you cannot use TDA2X GPUs to accelerate algorithms

Ticket Name: Linux/TDA2: Bit-stream input files for running NullSrc, Decode and Display UC of VSDK Linux

Part Number: TDA2 Tool/software: Linux Bit-stream input files for running NullSrc, Decode and Display UC of VSDK Linux

streams.zip

Closed

Hi Shiju, thanks for sharing this. Regards, Yordan

streams_1280x720.zipstreams_1920x1080.zip

Ticket Name: TDA2EVM5777: Master core

Part Number: TDA2EVM5777 Hello, The Vision SDK documentation talks about master cores. If BIOS is used on the A15 core, the IPU1_0 core is treated as the master core. If Linux is used on the A15 core, then the A15 core itself is treated as the master core. What exactly does the concept of "master core" mean? Thank you.

Hi, The usecase and filesystem and some other key things will be controlled by the master core. Regards, Anuj

Hello, Where can I find more information about this concept? Thank you.

Hi, there is no specific doc for the master core. But you can check below docs vision_sdk\docs\Architecture Regards, Anuj

Ticket Name: Compiler/AM5728: AM5728 without HDMI port how to configure G streamer video codec things through serial port?

Part Number: AM5728 Tool/software: TI C/C++ Compiler Hai sir, Before I am worked on AM5728 evaluation module through HDMI output port i have connected hdmi monitor through command prompt i have given commands? HIKVISION camera:1920x1080(25fps) a. sudo ifconfig eth1 10.10.11.85 netmask 255.255.254.0 up b.export RTSP_PATH=rtsp://admin:password@10.10.11.84:554 c.Less delay(80ms) & less frmaes missing command: Gst-launch-1.0 -v rtsp location="$RTSP_PATH" latency=0 ! rtpjitterbuffer ! rtph264depay ! h264parse ! ducatih264dec ! vpe ! videoconvert ! kmssink d.More delay(200ms) & More frmaes missing command: Gst-launch-1.0 -v rtsp location="$RTSP_PATH" latency=0 ! 'application/x-rtp, media=(string)video, clock-rate=(int)90000, encoding-name=(string)H264' ! rtpjitterbuffer ! rtph264depay ! h264parse ! ducatih264dec ! vpe ! 'video/x-raw, width=1920, height=1080, framerate=25/1, videoconvert ! kmssin Through HDMI output it will works but serial port not working? Actually through serial port i have given commands but not working any thing gstreamer error occuring but in HDMI port side it's working fine, please give me some suggestions. Thanking you, Regards, Ramachandra.

Hi Ramchandra, Could you share the info on the TI baseline release you are using here. Thanks, Gowtham

Ticket Name: RTOS/TDA2: Something wrong in new use case

Part Number: TDA2 Tool/software: TI-RTOS Hi, I change the "vip_single_cam_lane_detection" use case with the video as input I got the output below,but It seen look something wrong Can you tell us where is wrong? BR Allen

Hi Allen , From the video it looks the input resolution is not correct . It is less than the required . Any changes in the usecase .? If no changes Please verify source (player) video resolution . Regards Chetan.M

Hi, We use the input resolution is 768x320, and output resolution is 1920x1080 but, we use the same file being input resolution in "null_src_dec_display" use case We can get the right result (full screen) How can we get the full screen in this question? Where setting we should to change? BR Allen

Please verify the decoder output width and height ,and input parameters of the algorithm. Regards Chetan.M

Hi, I got the right result Thanks a lot Allen

Ticket Name: TDA2P-ABZ: rebuilding image for SDcard issues with TIDL case

Part Number: TDA2P-ABZ Other Parts Discussed in Thread: TDA2 Hi everybody , I have a TI evm for TDA2 and a D3 board mounting TDA2P . using latest SDK by TI modifying rules.make as : MAKECONFIG?=tda2xx_evm_bios_all I can build generate a card which is working in TI TDA2 board . now modifying to compile for TDA2P changing rules.make as MAKECONFIG?=tda2px_evm_bios_all I can build --> D3 TDA2P can boot but TIDL use case is empty : why ? (attached screenshot) what is missing ? on top if I use TDA2P image it doesn t run on TDA2 board : why ? is tda2px reffering to superset with different package ? best regards Carlo

Hi Carlo, TIDL use cases are supported only on TDA2x. TDA2Px is a different device as compared to TDA2xx. Hence you can't run TDA2P image on TDA2 board. Regards, Rishabh

Hi Rishabh , TIDL can work on TDA2P ? not supported use case means TIDL example not ported on TDA2P or no way at all to have any neural on TDA2P using tensorflow + TIDL ? thank you regards Carlo

Hi Carlo, TIDL can work on TDA2P. Not supported means TIDL example is not ported on TDA2P. Regards, Rishabh

Hi Rishabh ok thakn you please any directions/suggestion on how to port it on TDA2P ? I have a D3 TDA2P kit and a camera and TIDL use case as a basis will help a lot best regards Carlo

Hi Carlo, I am not an expert on TIDL yet to help you with porting steps :) Can you please post a different thread so that TIDL experts can help you. Regards, Rishabh

Ticket Name: RTOS/TDA2: Files needed for running SemSeg Semantic Segmentation usecase (Vision SDK, tidl)

Part Number: TDA2 Tool/software: TI-RTOS Hi, We have a TDA2X dev board and using Vision SDK 3.2.0.0 If I understand it correctly, we need additional files (besides the code in AppImage) to run this example: 1) Input video and header files. At this point we would love to have sample files, but I do not have access to CDDS yet. Is there a specific requirements for video format, resolution required, etc? I saw some info and even sample files 700x400 in another thread here, but now sure if this video works or not. I can try. 2) Since SemSeg uses TIDL, we probably need the right converted model files like NET.BIN, PRM.BIN, etc ? Right? Where can I find them? There are some example files in vision_sdk\apps\tools\TIDL_files folder, but I do not think these are the right ones for SemSeg usecase... Thanks, Mikhail

Hi, 1. You can further refer to below thread e2e.ti.com/.../660676 2. Please refer section 3.6 in TIDeepLearningLibrary_UserGuide.pdf to generate model files like NET.BIN, PRM.BIN for your trained models or inputs. Thanks, Praveen

Hi Praveen, Thanks you! I understand part 1. We can try to generate our own video or wait for CDDS access to get the sample one. Regarding part 2 (NET.BIN, etc). At this moment, our model cannot be converted to TIDL (not supported). I was under impression that there is a sample model from TI specifically for the Semantic Segmentation usecase. Am I wrong? Thanks, Mikhail

Hi Mikhail, I mean to say there are some sample model bin files in TIDL package to run Semantic Segmentation usecase, but if you want to run a caffe model trained by you then you need to generate these bin files. Thanks, Praveen

Hi Praveen, Do you know where I can get some sample model bin files for SemSeg usecase? Through CDDS ? I could not find anything in Vision SDK itself. Thanks, Mikhail

Hi Mikhail, The model files like NET.BIN, PRM.BIN for SemSeg usecase are in Vision SDK in the below folder.. "REL.TIDL.01.01.00.00\modules\ti_dl\test\testvecs\config\tidl_models\jsegnet21" tidl_net_jsegnet21v2.bin tidl_param_jsegnet21v2.bin Thanks, Praveen

Thank you! SemSeg example works! Mikhail

Ticket Name: CCS/TDA2EVM5777: CCS/TDAEVM577

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: Code Composer Studio Hi export: How to update software via USB. Thanks,

Hi Jemy, Can you please add details on what is the question here? What SW is it that you need to update? Is it flashing/loading SW to the TDA2 EVM? Regards, Karan

Ticket Name: TDA2PXEVM: TDA2Px EVM board software warm reset will not reset LP87565?

Part Number: TDA2PXEVM Hi Experts: We are working with customer review our TDA2P EVM design. When software warm reset trigger or PORz signal trigger, TDA2P pin D23 RSTOUTN will trigger TPS65917 pin 13 (GPIO_1 OTP configure as reset in). It will successful reset TPS65917 return to OTP default voltage output. But LP87565 will not be reset, The VDD_MPU and VDD_GPU power rail will keep to reset start voltage. We think this design is not right, it can not match snvu590.pdf guide introduced boot mode voltage. Can you help us double check the LP87565 whether been reset when TDA2P PORz/warm reset triggered? Best Regards! han Tao

The LP87565 device does not support a 'warm reset input' similar to that on the TPS65917 device. The TPS65917 warm reset input is typically critical as the SD card voltage must be reset to the default voltage for booting. The remaining power supply voltages (including LP87565) will remain as they were prior to the warm reset event.

Hi Robert: Whether this will be have problem at warm reset boot? Because DM Table 5-3 said that boot mode need > 1.11V power supply. but when A15 work at OPP_NOM mode, the VDD_MPU voltage is maybe < 1.0V. At this time software trigger warm reset signal, LP87565+TPS65917 keep the power supply voltage is OPP_NOM, it below than DM request. Old TPS659039 PMIC when warm reset the output voltage will return to default setting as swcu175c.pdf user guide introduce. So J6P EVM board warm reset whether have risk can not successful boot up? Best Regards! Han Tao

During development of the J6Plus EVM, TI SW team made an assessment on the value of warm reset & decided that this operation had minimal value. Please kindly refer to note #5 captured on the J6Plus EVM PDN diagram that clearly states the following: 5. This PDN does not support a “Warm Reset” that can be initiated by SW running on SoC by asserting the RSTOUTn ball. The LM87xxx PMIC family does not support this type of SW reset functionality that is supported by the TPS659xx PMIC family.

Hi Bill & Robert: Thanks clarify it to me. Because customer when MCU probe TDA2P software hung, it will pull down PORz and restart TDA2P. Very low probability some board can not successful boot up i am worry that it have relationship with PMIC do not reset to the default voltage. It is clear that J6P/TDA2P EVM board warm reset will not trigger LP87565+TPS65917 output voltage return to the default value. Best Regards! Han Tao

Tao, If the PMIC was at a safe AVS voltage prior to reboot, then the SoC should be able to boot just fine at that same voltage. Regards, Kyle

Ticket Name: AM5718: 13MP camera on MIPI interface

Part Number: AM5718 Other Parts Discussed in Thread: TDA2 Hello, I have been read the Document for AM571x Processor but i have below query. I have been checked "AM571x Industrial Development Kit" User's Guide. but this Development kit does not support mipi csi-2 camera interface. it has only provision for parallel camera interface. is there any another development kit which support USB 3.0 and Camera MIPI interface Support? Can we interface 13MP Camera on MIPI CSI-2 interface on AM571x Processor? Please provide us the support as soon as possible. Thanks & Best Support.

Hi, 1. No, there is no other EVM for AM571x. 2. The AM571x CSI interface is described in section 8 of the AM571x TRM Rev. E.

Thanks for your reply. 2. I have been check AM571x TRM Rev. E. Document but there is no any description for Camera support(How much Mega Pixel). I mean this processor is capable to interface the 13MP Camera?

What is the video format of your camera - resolution, frames per second?

Thanks for your reply. We don't required the video streaming. We captured the raw data of image (8bit/pixel) from camera. We have some query as below. is there possible to get the line by line raw image data instead of whole image data? is there any Evolution board which support the USB 3.0 and camera (MIPI) interface? Thanks & Best Regards;

Gentle Reminder.. Thanks & Best Regards;

Sorry about this delay. I have escalated this to the factory team.

Hello: Regarding to USB3 camera support: The USB driver in the SDK may support standard Linux USB3 camera modules, though there is no examples in the SDK. You may reference to www.ti.com/.../tidep0076 where a PointGrey ( https://www.ptgrey.com/) camera module was used with an AM57 EVM. You may also want to check if the camera vendor support UVC driver or not. Regarding to 13MP support over CSI-2: Please confirm the spec of the camera module CSI-2 interface, with respect to required clock speed and number of lanes. This will allow us to confirm if the CSI-2 PHY is compatible with the camera. In the meantime, I am confirming maximum line width of our internal buffers to ensure it can support 4k pixel line width. regards jian

Hi jian, Thanks for your quick answer. We have not concern with USB3.0 camera. We are asking for is there any evolution kit which support USB 3.0 (usb core (host+device)) and camera mipi CSI-2 interface support. Best Regards; Nikunj Patel

gentle reminder. Thanks & Best Regards; Nikunj Patel

Hello everyone; I want to download the "ti-processor-sdk-linux-automotive-omap5-uevm-6.04.00.02-installer.bin" sdk for Omap5432 evm board. Please provide me the link for that. Thanks & Best Regards; Nikunj Patel

Hello everyone; Gentle reminder. Thanks & Best Regards; Nikunj Patel.

Hi Nikunj Sorry for keeping you waiting on this thread. Unfortunately no one on the team supporting these forums are familiar with OMAP5 SDK etc, and will likely not be able to support any queries on it. To your original query on TI EVM supporting MIPI CSI , unfortunately currently none of the AM57x family EVMs have support for this. You can look at the following post e2e.ti.com/.../2262820 You can search for the TDA2 family evaluation boards, available from Spectrum Digital. Hope this helps some. Regards Mukul

Ticket Name: Linux/TDA2: HDMI 1080p@60Hz capture doesn't work

Part Number: TDA2 Tool/software: Linux Hi, I have one question about VSDK 03.02 linux version. I'm wondering if the HDMI 1080p 60Hz capturing is works well when " tda2xx_evm_linux_all" configuration is used. When I tried to do test with "tda2xx_evm_bios_all" configuration, I could see the screen well. Of course, I set the capture source with "HDMI Capture 1080P60" and set the display device as HDMI 1080p from System Setting menu. Please let me know if I do something more. Thanks, BR, Ungsin

Hi Ungsin, HDMI Capture is not supported in Linux version. Please check vision_sdk/docs/VisionSDK_ReleaseNotes.pdf for which usecases are supported in Bios or Linus variants. Regards, Yordan

Ticket Name: RTOS/TDA2P-ACD: Changing IP address of TDA2P in Runtime

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hello All, Is there a way to change the IP address of EVM in Vision SDK 03.03. We want to change the IP address for testing NulSrc + Display Usecase. We do not want to set the IP address everytime in NDK.cfg file. We want user to input the IP from usecase menu. Is it possible to achieve this ? Thanks, Abhay

Hi Abhay, First off you will need your app to start off with no ip address. In your *.cfg file do you have the following line? Global.enableCodeGeneration = false; Based on your answer it will change what we need to do next. Regards, Dalton

Hi Dalton, Thanks for your reply. I searched for "Global.enableCodeGeneration" in my "NDK.cfg" file at "\links_fw\src\rtos\bios_app_common\tda2px\cfg\NDK_config.cfg". This line is not present in this file. Regards, Abhay

Hi Abhay, Okay that's great. You can then go ahead and add the following line to your *.cfg file: Ip.address = "none"; This will setup the app to neither use DHCP or a static ip address on startup. With this setup you can create a C function in your app to setup an IP address. The function would look like this: /* Static IP Address settings */
char *LocalIPAddr = "192.168.1.4";
char *LocalIPMask = "255.255.255.0";
char *GatewayIP   = "192.168.1.1";
char *DomainName  = "demo.net";

void changeIP()
{
    /* Configure IP address manually on interface 1 */    
    CI_IPNET NA;
    CI_ROUTE RT;
    /* Setup manual IP address */
    memset(&NA, 0, sizeof(NA));
    NA.IPAddr  = inet_addr(LocalIPAddr);
    NA.IPMask  = inet_addr(LocalIPMask);
    strcpy(NA.Domain, DomainName);
    NA.NetType = 0;

    CfgAddEntry(0, CFGTAG_IPNET, 1, 0,
            sizeof(CI_IPNET), (unsigned char *)&NA, 0);

    /*
     *  Add the default gateway. Since it is the default, the
     *  destination address and mask are both zero (we go ahead
     *  and show the assignment for clarity).
     */
    memset(&RT, 0, sizeof(RT));
    RT.IPDestAddr = 0;
    RT.IPDestMask = 0;
    RT.IPGateAddr = inet_addr(GatewayIP);

    CfgAddEntry(0, CFGTAG_ROUTE, 0, 0,
            sizeof(CI_ROUTE), (unsigned char *)&RT, 0);
} The IP address does not need to be global, I just wrote it that way for illustrative purposes. I'm not familiar with how Display Usecase works, but I'm guessing you could have it call this C function? Regards, Dalton

Hi Dalton, I have now added the similar function in my code which I call from the usecase menu of Vision SDK. But while compiling I get following linking errors, " undefined first referenced symbol in file --------- ---------------- CfgAddEntry /home/abhay/FFC/source/vision/platform/ti/tda2/binaries/apps/tda2px_evm_bios_all/lib/tda2px-evm/ipu1_0/debug/app_libs.aem4<chains_ main_bios_settings_vision.oem4> inet_addr /home/abhay/FFC/source/vision/platform/ti/tda2/binaries/apps/tda2px_evm_bios_all/lib/tda2px-evm/ipu1_0/debug/app_libs.aem4<chains_ main_bios_settings_vision.oem4> " One thing I want to mention, I have set "NDK_PROC_TO_USE=a15_0" in our configuration file. Regards, Abhay

Hi Abhay, My apologies, I didn't tell you what includes you will need for this. The inet_addr function needs the following include: #include <ti/ndk/inc/nettools/inc/inet.h> Another one that would work would be this include: #include <ti/ndk/inc/netmain.h> However, netmain.h essentially brings the whole ndk world in with it, so that might be a bit overkill. As for the "NDK_PROC_TO_USE" setting, that shouldn't impact what we are doing here. Regards, Dalton

Can I mark this as closed? Todd

Hi Dalton, I included both the headers but still getting the same linking error as above. Regards, Abhay

Todd I am not able to fix this yet. Regards, Abhay

Hi Abhay, Can you upload your full verbose build output when you get these linker errors? If a linker.cmd file is being generated can you upload that as well? Regards, Dalton

Hi Dalton, We were able to fix the linking issue as well as we are able to set IP address to our TDA2P in runtime. As we are using NDK on A15 core, we need to compile the function given by you on A15 core itself. Also went through the linker.cmd file for both A15 and IPU cores, and we could see that paths for NDK were set in the A15's linker.cmd file. Thanks for your help. I will close this thread. Regards, Abhay

Ticket Name: TDA4VM: ERROR: 'dot' tool not found. Make sure 'graphviz' is installed and 'dot' command is added to system PATH !!!

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 i get this error when i run the sample code in tiovx. I have installed graphiz. ERROR: 'dot' tool not found. Make sure 'graphviz' is installed and 'dot' command is added to system PATH !!! ERROR: Cannot generate .jpg file !!!

Hello, Could you please provide the following details? 1. Which SDK version are you using? 2. Which sample code are you running? 3. Are you running on the EVM or PC emulation mode? 4. Have you run the script "./psdk_rtos/scripts/setup_psdk_rtos.sh"? Regards, Lucas

1. the SDK version i was using is this :-https://git.ti.com/cgit/processor-sdk/tiovx/tree?h=master 2. same code given in this path:- /tiovx/tools/sample_use_cases. I followed this link:- http://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/tiovx/docs/user_guide/PYTIOVX.html 3. PC emulation mode currently. 4. no. where can i find the script??

Hello, The TIOVX version you linked to is an older version of TIOVX intended for support on TDA2/TDA3 SoC's. If you are intending to run TIOVX on TDA4, I would recommend downloading TIOVX as a part of the below SDK, as it includes the dependencies as well as scripts to download external tools needed to run the SDK. Additionally, the PyTIOVX tool is only supported for kernel generation. The use case development feature is experimental and is thus unsupported in our SDK. For developing applications using OpenVX, we recommend referencing the vision_apps project included within the SDK linked to above. Regards, Lucas

Does this require ubuntu18.04?? Will it wok on Ubuntu 16.04??

Hello, It is untested on Ubuntu 16.04, so it is recommended to upgrade to Ubuntu 18.04. Regards, Lucas

Okay Let me try.

is this windows installer??can it be used in linux??

Hello, Yes, all components are supported in Linux. Regards, Lucas

Okay , thank you resolved the issue.

Ticket Name: TDA2: TDA2x (TDA2P) UseCase EUNCAP perfermance

Part Number: TDA2 Dear All, I have some question about the performance of object detection use case (No TIDL_OD) on TDA2x (or TDA2p). 1. According VisionSDK_DataSheet.pdf Chapter 9(EUNCAP), the input video resolution is 1M(720p). What is the input(processing) resolution of the actual algorithm(PD, VD, TSR, TLR, FCW(with SFM) and processing frame rate ? 2. If using TDA2x( or TDA2p) fully, What is the Max performance such as framerate and resolution ? BR, Khethan

Hi, Yes the input resolution is 720p as no VPE link is used. For further info on individual algorithm, please refer the algorithm datasheet inside ti_components/algorithm/ Regards, Anuj

Hi Thank for reply BR, Khethan

Ticket Name: Linux/TDA2: Cannot run EVE edge detection on Linux

Part Number: TDA2 Tool/software: Linux Im trying to use existing rtos edged etection algorithm but ported on linux. Its kinda working, but very strange, and i cant find out whats wrong. The resolution is very low and it is packing multiple screens on display (you can see four screens packed next to each other on image):

Hello Please check video pitch and data format passed to the display after the edge detect alg. I guess you do not need any changes in ED Alg or Alg plugin as this run on EVE in both RTOS and Linux case, only the usecase need porting from rtos to Linux to get this working on Linux regards, Shiju

Hi, I have tried changing pitch and frame format, input, output resolution, and i always get the similar result. I was thinking that maybe problem was in display setting so i saved the output from ED link and when i try to open it on my PC (using ffplay) i get this: [rawvideo @ 0x7f94b40008c0] Invalid buffer size, packet size 16384 < expected frame_size 3110400 for 1920x1080 output [rawvideo @ 0x7f69ac0008c0] Invalid buffer size, packet size 16384 < expected frame_size 1382400 for 1280x720 output [rawvideo @ 0x7f3ec80008c0] Invalid buffer size, packet size 7984 < expected frame_size 8400 for 280x20 Its like it is always compressed, or that algorithm does not give complete output, which makes no sense cause it is working perfectly fine running on sys-bios. Any thoughts on this?

Hi ED Alg link output full frame, but only the Luma (Y) portion of the video frame. Is ED on Linux is your ultimate goal or is this a experimental UC? Can you please help me to understand your final UC/data flow? Regards, Shiju

Ticket Name: TDA2 Initialisation via JTAG

Other Parts Discussed in Thread: TDA2 Hello, We are having issues finding any information on how to access a TDA2 device (specifically TDA2HGBRAQ) via JTAG. We don't use a 3rd party tool, but are building the JTAG communications ourselves. The steps we would follow are: 1. Physically connect to JTAG pins on TDA2 device. 2. Trigger TDA2 reset (or JTAG reset) and initialise the device via JTAG (halt core(s), setup memory, etc.). 3. Upload a boot loader to the RAM of the device and execute it. Steps 1 and 3 aren't really the issue, but we need help with step 2. We can access this same target device with a Lauterbach, so the information for how to do this initialisation via JTAG must be available. As of yet, we haven't been able to find the right contact and/or documentation for this. If someone can help us find the correct contact and/or documentation, that would be very helpful.

To use the correct terminology, I am looking for the JTAG scan path details for third party programming support.

Hello Daniel, How about refering to the CCS device scan chain tree (attached) for example. The xml clearly shows processor sub-paths. TDA2x.xml You may also refer to "30.6 Power, Reset, and Clock Management Debug Support" in the device TRM and in general to the "Chapter 30 On-Chip Debug Support" for additional JTAG debug support details. Hope it helps, thanks, Alex

Hello Alex, Thank you for this information. We've tried to use it, but still encounter some issues. Primarily, we need to know how to navigate to IcePick-D so that we can access the Cortex core. Currently we can't find any information on the correct TAP states or flow we need to reach this goal. We've "guessed" some values to shift and seem to get some limited data when we clock out in the shift state, but this is just trail and error with no real understanding of what the commands we send and receive really are. Do you know where we can find the information to access the Cortex via IcePick-D? TAP states, Shift-IR commands, Shift-DR data, etc? Once we have access to the Cortex, the reading/wring of RAM (and registers) becomes trivial. Thanks in advance, Daniel.

Hello Daniel, Could you please also refer to the following doc then. Looks like it has enough information to enable a third party debugger on the processor JTAG test access ports (TAPs) connected to the ICEPick-D. Let me know thanks, Alex

Hello Alex, Thanks for this. We use this sequence with a P value of 15 and Q value of 0. The P value we estimated based on ADAS reference manuals, the Q is just taken from practice. Are these correct? After we do these initialisation steps, we try to setup the Cortex-A15. However, at this point, we have really no information. Currently we are trying to perform similar commands as we did for Cortex-A9, but even the A9 commands were a kind of guess work. Are you able to provide any documentation at this point, so that we can ensure proper access to the Cortex and read/write the RAM. Thanks, Daniel.

Hi Daniel, I think you are correct: P = 15 (dec); Q = 0 (dec); P is for tap number, Q for Core number, and referring to TRM debug chapter, your values look correct (see attached screenshot) Thanks, Alex

Hi Alex, The attached screenshot didn't work, but thanks for clarifying. Regarding the point about setting up the Cortex-A15 after the ICEPick-D initialisation; do you have any documents or contacts who could support us?

Hi Daniel, Reattached screenshot. Moreover, I received feedback that the Emulation developer community has this information and you should have access to the below url. Could you please check there if more docs are available for you to clarify your questions? https://www.ti.com/securesoftware/docs/securesoftwarehome.tsp Thanks, Alex

Hello Alex, Thanks for the help. We'll look through the documentation in the Emulation Developer Community and see what we can find. Regards, Daniel.

Ticket Name: TDA2: Vision_sdk compile error

Part Number: TDA2 Hello: The error info is below, I could not find TI_OD_VISION_FXNS anyway. Where can I find "TI_OD_VISION_FXNS" or which lib may be missed? regards # Linking into /home/test/vision_sdk/binaries/vision_sdk/bin/tda2xx-evm/vision_sdk_c66xdsp_1_debug.xe66... undefined first referenced symbol in file --------- ---------------- TI_OD_VISION_FXNS /home/test/vision_sdk/binaries/lib/tda2xx-evm/66/debug/vision_sdk_alg_plugins.ae66<objectDetectionLink_algPlugin.oe66> error: unresolved symbols remain error: errors encountered during linking; "/home/test/vision_sdk/binaries/vision_sdk/bin/tda2xx-evm/vision_sdk_c66xdsp_1_debug.xe66" not built make[4]: *** [/home/test/vision_sdk/binaries/vision_sdk/bin/tda2xx-evm/vision_sdk_c66xdsp_1_debug.xe66] Error 1 make[3]: *** [apps] Error 2 make[2]: *** [apps] Error 2 make[1]: *** [vision_sdk_apps] Error 2 make: *** [vision_sdk] Error 2

Hi Bin Ye, which version is your VisionSDK and what changes you made? Regards, Yordan

Hi Bin Ye, For "TI_OD_VISION_FXNS" - please grep inside vision_sdk/apps/src/rtos/alg_plugins/objectdetection folder And for library, Could you check inside the object_detect_PATH set in tools_path.mk file (under vision_sdk/build folder like below) ? object_detect_PATH ?= $(TI_SW_ROOT)/algorithms/REL.200.V.OD.C66X.00.06.02.00/200.V.OD.C66X.00.06 Regards Surya

We have found lib configuration in rules_66.mk as the vision is 2.x, thanks.^_^

Ticket Name: TDA2: EVE/BAM/writing short int data back to external memory :

Part Number: TDA2 Hi guys, i am trying to write int16_t (short int) type data output to the sink node, but the Pointer to external memory buffer is of uint8_t type. --> So can i use another pointer of type int16_t which could hold the output data --> why it is specific of type uint8_t ? typedef struct { uint16_t roiWidth; uint16_t roiHeight; uint16_t blkWidth; uint16_t blkHeight; uint16_t extBlkIncrementX; uint16_t extBlkIncrementY; uint16_t intBlkIncrementX; uint16_t intBlkIncrementY; uint32_t roiOffset; uint16_t blkOffset; uint8_t *extMemPtr; uint8_t *interMemPtr; uint16_t extMemPtrStride; uint16_t interMemPtrStride; uint8_t dmaQueNo; }EDMA_UTILS_autoIncrement_transferProperties; Regards Surbhi

Surbhi, Its just a pointer so its original type doesn't matter. Just typecast your pointer to uint8_t * and provide all the other parameters in terms of bytes as mentioned in the interface file. Regards, Anshu

okay, but i need uint8_t type pointer for my input data at source side & for output data i require a pointer of int16_t type.

DMA just transfer data from one memory location to other irrespective of its data type ( all the DMA parameters are in terms of bytes). So I am not sure what exactly you are asking? As mentioned earlier you just have to provide the pointer to the location from where to where you want to transfer. How you use these pointers is upto you, you can treat them as uint8_t or int16_t. Regards, Anshu

Ticket Name: RTOS/TDA2: How to config MPU 's frequency from 750M to 1G hz in visionSDK3

Part Number: TDA2 Tool/software: TI-RTOS Hi, How to config MPU(A15) 's frequency from 750M to 1G hz in visionSDK3 ? We use bios OS on A15.

Hi, Please opp_high folder's MLO. Regards, Anuj

Thank you very much.

Hi Bao, In addition to what Anuj said kindly note that A15 will be set at 1176 MHz in case of OPP High. Regards, Rishabh

Hi Rshabh, Actually, we use TDA2x with 17x17 package, nearly all the OPP configured the same as Nom, I modify the code to get 1G Hz. /* Configuration for DPLL MPU */ #if defined (SOC_TDA2XX) static pmhalPrcmDpllConfig_t *pDpllMpuCfg_23x23Package_20[] = { &dpllMpuCfgOppLow_20, &dpllMpuCfgOppNom_20, &dpllMpuCfgOppOd_20, &dpllMpuCfgOppOd_20, &dpllMpuCfgOppOd_20 }; static pmhalPrcmDpllConfig_t *pDpllMpuCfg_17x17Package_20[] = { &dpllMpuCfgOppLow_20, &dpllMpuCfgOppNom_20, &dpllMpuCfgOppNom_20, &dpllMpuCfgOppNom_20, &dpllMpuCfgOppNom_20 };

Hi Bao, You should make sure that frequency is within limits specified in Data Manual. For 17x17 package max frequency supported is 750 MHz. Regards, Rishabh

Ticket Name: RTOS/TDA2: Code example for reading and saving CSI-2 data in TDA2x

Part Number: TDA2 Other Parts Discussed in Thread: AWR1243 Tool/software: TI-RTOS Hello, I am new to designing the ADAS solutions using TDA2x board. I want to integrate 4 cascaded radar sensors with my TDA-2 processor for my application. I read few posts on TI's website which mentions about using DS90UB960 Deserializer Hub which receives 4 inputs and transmits into one (or two) CSI-2 output port. This interleaved data is then set to TDA2 processor. Is there any example code on how to decode this interleaved data on the TDA2 processor end and store it somewhere( maybe in SD card or PC) so that I can use this CSI-2 data to perform few radar algorithms? Thank you!

Hi Nishant, TDA2x dosen't have CSI2, The CAL driver (hw) performs the de-interleaving. Please refer any of the SRV demos. Regards, Sujith

Thank you Sujith! I shall look into it and get back to you if I have any questions. Do you have the link for the SRV demos? Best Regards, Nishant

Hello Sujith, Referring to the answer given by Piyali to this post: https://e2e.ti.com/support/arm/automotive_processors/f/1021/t/662898, where can I find the "single AWR 4 Rx 3Tx de-interleaving done by the EVE FFT functions on the TDA " reference document? I tried searching online but I couldn't find it. Also could you mention the best sources for reading more about the Camera Adaptation Layer (CAL) drivers? Best Regards, Nishant

Hi Nishant, For CAL details, can i ask you to refer the TRM (Data Manual) of TDA2Px or TDA3x. For the demo applications please refer \apps\src\rtos\usecases\iss_mult_capture_isp_dewarp_3dsv_tda3xx I will have to check on the AWR and get back to you. Regards, Sujith

Hello Sujith, Thank you for providing the file location for understanding CAL implementation. I have a related question to my original question I asked before, can CSI-2 data be read directly by the TDA3 processor? In Fig 2.7 of the "ProcessorSDKRadar_UserGuide.pdf", there is an image where the CSI-2 Data from AWR1243 is directly connected to TDA3X. I had asked my local TI engineer for help in designing the hardware for the connection board (DIB+VAB boards) for interfacing AWR1243 with TDA3 and she asked me to refer fig 2.7 to create my own customized board for it. So do we need CAL driver hardware only for TDA2 or does TDA3 also require it for collecting data from various sensors? Thank you, Nishant

Hi Nishant, TDA2x dosen't come with a CSI2 receiver. Only TDA2Px, TDA2Ex and TDA3x has this hardware. Regards, Sujith

Thank you! Best Regards, Nishant

Ticket Name: Linux/TDA2: Where to get the SCH. PDF?

Part Number: TDA2 Other Parts Discussed in Thread: J6EVM5777 Tool/software: Linux Dear Sir: We have a DRA7xEVM with the LG10.1" LCD, however we can not found the SCHEMATIC of that LCD board in DRA7xEVM page below. Would you please let me know where to download it? Regards, /ckhsu

Hi CK Hsu, please check "Design Files" here: www.ti.com/.../tda2evm5777 (LG10.1 LCD should be the one with "1280 X 800", "1920x1200" if for the OSD Panel) Regards, Yordan

Hi Yodan: 1280 X 800 is for the AUO. And 1920x1200 is for the OSD panel, both of them are not LG. Is the SCH. file of AUO same as LG? Regards, /ckhsu

Hi CK Hsu, I pinged an expert to help with the right documents. Regards, Yordan

Hi Yordan: Thank you, I will wait for the response. Regards, /ckhsu

CK, The LG 10" display is obsolete and is no longer shipping. That's why the newer display schematics are available on the ti.com link. Please send me your email address with a private message, and I can email them to you. Thanks, Kyle

Ticket Name: PROCESSOR-SDK-TDAX: I can't train ssdJacintoNetV2 in caffe-jacinto-model-0.17 with 768x320 size.

Part Number: PROCESSOR-SDK-TDAX Hi , when I use train_image_object_detection.sh to train ssdJacintoNetV2 in caffe-jacinto-model-0.17 with 768x320 size, an error list: when I switch to 512x512 is OK,and also switch to caffe-jacinto-model-0.16 is OK. why? I1216 17:11:22.872642 40400 solver.cpp:229] Starting Optimization on GPU 0 I1216 17:11:22.872648 40401 solver.cpp:229] Starting Optimization on GPU 1 I1216 17:11:22.872804 40400 solver.cpp:269] [MultiGPU] Initial Test started... I1216 17:11:22.872872 40400 solver.cpp:635] Iteration 0, Testing net (#0) I1216 17:11:22.872974 40428 common.cpp:550] NVML succeeded to set CPU affinity on device 0, thread 40428 I1216 17:11:22.873769 40429 common.cpp:550] NVML succeeded to set CPU affinity on device 1, thread 40429 I1216 17:11:23.038713 40400 net.cpp:1071] Ignoring source layer mbox_loss I1216 17:11:23.060695 40401 net.cpp:1071] Ignoring source layer mbox_loss F1216 17:11:23.424778 40401 solver.cpp:668] Check failed: result[j]->width() == 5 (3 vs. 5) *** Check failure stack trace: *** @ 0x7fec048d35cd google::LogMessage::Fail() @ 0x7fec048d5433 google::LogMessage::SendToLog() @ 0x7fec048d315b google::LogMessage::Flush() @ 0x7fec048d5e1e google::LogMessageFatal::~LogMessageFatal() @ 0x7fec054921e0 caffe::Solver::TestDetection() @ 0x7fec054950f7 caffe::Solver::TestAll() F1216 17:11:23.452100 40400 solver.cpp:668] Check failed: result[j]->width() == 5 (3 vs. 5) *** Check failure stack trace: *** @ 0x7fec05496406 caffe::Solver::Step() @ 0x7fec048d35cd google::LogMessage::Fail() @ 0x7fec054973d2 caffe::Solver::Solve() @ 0x7fec048d5433 google::LogMessage::SendToLog() @ 0x7fec0590628a caffe::P2PSync::InternalThreadEntry() @ 0x7fec048d315b google::LogMessage::Flush() @ 0x7fec048d5e1e google::LogMessageFatal::~LogMessageFatal() @ 0x7fec059c538c caffe::InternalThread::entry() @ 0x7fec054921e0 caffe::Solver::TestDetection() @ 0x7fec059c73eb boost::detail::thread_data<>::run() @ 0x7fec054950f7 caffe::Solver::TestAll() @ 0x7fec02dbe5d5 (unknown) @ 0x7fec05496406 caffe::Solver::Step() @ 0x7fec0288f6ba start_thread @ 0x7fec054973d2 caffe::Solver::Solve() @ 0x7fec030da41d clone @ (nil) (unknown)

Can you pls set chop_num_heads to 0 in caffe-jacinto-models/scripts/train_image_object_detection.sh and try training?

Hi， It's amazing, it can work now, but I want to know what this parameter does. Why did it work on the previous version caffe-jacinto-model-0.16?

It was some experimental option not supposed to be used in the final release.

Hi Soyeb： Can I ask you a question： When marking targets with marking label software, what are the functions of marking attributes, such as occluded, truncation, difficulty and pose? How do I use it on ssdJacintoNetV2? Thank you very much!

like this: <size> <width>1280</width> <height>720</height> <depth>3</depth> </size> <segmented>0</segmented> <object> <name>VehicleFull</name> <pose>Unspecified</pose> <truncated>0</truncated> <difficult>0</difficult> <bndbox> <xmin>474</xmin> <ymin>257</ymin> <xmax>495</xmax> <ymax>275</ymax> </bndbox> </object>

You may find information about these attributes by looking at PASCAL VOC dataset. Also you may go through some blog like the following, https://towardsdatascience.com/coco-data-format-for-object-detection-a4c5eaf518c5

Hi Soyeb： I know what these tags mean, but what I want to know is how do I use these tags when I train the model? I can't find any place to call these tags, right? So what exactly do these tags do? Convenient data statistics? <object> <name>VehicleFull</name> <pose>Unspecified</pose> <truncated>0</truncated> <difficult>0</difficult> <bndbox> <xmin>474</xmin> <ymin>257</ymin> <xmax>495</xmax> <ymax>275</ymax> </bndbox> truncated: Indicates that the bounding box specified for the object does not correspond to the full extent of the object. For example, if an object is visible partially in the image then we set truncated to 1. If the object is fully visible then set truncated to 0 difficult: An object is marked as difficult when the object is considered difficult to recognize. If the object is difficult to recognize then we set difficult to 1 else set it to 0

Now I understand the question better. 'pose' and 'truncated' are not used in the code. However 'difficult' is used. Pls look at the config param, use_difficult_gt. You may refer the caffe-jacinto code to find out how exactly it is used?

Ticket Name: RTOS/TDA2: TDA2xx rvp: Null source

Part Number: TDA2 Tool/software: TI-RTOS Dear All, We are working on TI TDA2X (Both RVP and EVM). So far: 1. Able to run "apps" use cases. 2. Able to run "sample_app" config use case. i.e The "sample_apps" i.e. from file of /vision_sdk/sample_app/src/rtos/* has "NullSource -> Alg_FrameCopy (DSP1) ->Display" We are able to see the "TI logo" in the center of the HDMI output display. Question: Where is the nullsource center "TI logo" frame buffer or source buffer? We tried to look into the links of nullsrc i.e. links_fw/src/rtos/links_common/nullSrc/nullSrcLink_tsk.c but not much progress could be made. Need your support in explaining the "NullSource" input buffer and where is the buffer filled for the first time. Knowing this would help us to give our own predefined test scenario buffer data. Regards, KK

Ti Logo is included as a static array from the following header file #include <src/common/TI_logo_640_224_sp.h> Regards Chetan.M

Hello Chetan, The information was helpful, I see that : null_src_display/chains_nullSrcDisplay.c 223 static Void fillSrcBuf(chains_nullSrcDisplayObj *pObj) 224 { ... 236 status = System_linkControl( 237 pObj->NullSourceLinkID, 238 NULL_SRC_LINK_CMD_GET_BUF_INFO, 239 &getBufInfoPrm, 240 sizeof(NullSrcLink_GetBufInfoParams), //==> where is this destination buf created? 241 TRUE); 244 for (bufCnt = 0;bufCnt < getBufInfoPrm.numBuf;bufCnt ++) 245 { 262 offset = (logoStartY * NULLSRC_OUT_WIDTH) + logoStartX; 263 dstAddr = (UInt8*)((UInt32)pVideoFrame->bufAddr[0] + offset); //==>destination buffer address. 264 srcAddr = tiLogo_640_224; //==> This is where it is used as a source .. 283 Cache_wb(); //==> What is the role of this? 294 } 295 } Thanks, KK

Hi KK, Please find answers below: Que 1 : where is this destination buf created? destination buffers has been created by the Null_src link at the create time. In line no 240 its a size of buffer information structures. by calling the api at line 236 with the given params its asking the link about how many no of buffers has been created and information of all buffers. Que 2 : destination buffer address. this is the destination address from where the Ti logo will start. Que 3 : This is where it is used as a source Yes that is the address of source buffer. Que 4 : What is the role of this? this api is called to write back the cache data on the ddr so that it will be shown to other cores as well. Regards, Anuj

Thanks Anuj, The information was helpful and understood Q2 , Q3, Q4. Que 1 : where is this destination buf created? "its asking the link about how many no of buffers has been created and information of all buffers." Q 1.1. Which source file should we refer to understand the NullSource link. Q1.2. If design needs to change the Number of buffer and the size of the buffer, where/what is the procedure? Thanks for the support, Regards, KK

Hi, Q 1.1. Which source file should we refer to understand the NullSource link vision_sdk\links_fw\src\rtos\links_common\nullSrc\ vision_sdk\links_fw\include\link_api\nullSrcLink.h Q1.2. If design needs to change the Number of buffer and the size of the buffer, where/what is the procedure This things you need to change in usecase file (vision_sdk\apps\src\rtos\usecases\null_src_display\chains_nullSrcDisplay.c) check the implemetation of this function chains_nullSrcDisplay_SetAppPrms() Please go through the below doc for more information vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_DevelopmentGuide.pdf Regards, Anuj

Hello Anuj, Information about the SetAppPrms and document is helpful. I will read through the document and will get back if still there are some questions. Thanks, KK

Ticket Name: DRA756: EMMC linux driver issue

Part Number: DRA756 Hi. sdk: PROCESSOR_SDK_VISION_03_05_00_00 For the same software, only the SOC of the two boards is different. One uses tda2s and the other uses dra756. Tda2s can use EMMC ddr50 mode.while dra756 cannot use ddr50 mode,Dra756 can use EMMC HS mode dts: &mmc2 { status = "okay"; vmmc-supply = <&evm_3v3_sw>; bus-width = <8>; max-frequency = <192000000>; pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v","ddr50"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev11_conf>; pinctrl-3 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev20_conf>; pinctrl-4 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev11_conf>; pinctrl-5 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev20_conf>; }; dr756 emmc ddr50 mode log: [ 1.072168] ldousb: disabling [ 1.073427] omap8250 4806a000.serial: failed to request DMA [ 1.074258] Waiting for root device PARTUUID=dda7f685-03... [ 1.163294] mmc0: host does not support reading read-only switch, assuming write-enable [ 1.168022] mmc0: new ultra high speed DDR50 SDHC card at address aaaa [ 1.169218] mmcblk0: mmc0:aaaa SS08G 7.40 GiB [ 1.174636] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 p8 p9 > [ 1.220299] mmc1: MAN_BKOPS_EN bit is not set [ 1.223227] mmc1: new DDR MMC card at address 0001 [ 1.224159] mmcblk1: mmc1:0001 8GUF4R 7.28 GiB [ 1.224893] mmcblk1boot0: mmc1:0001 8GUF4R partition 1 31.9 MiB [ 1.225796] mmcblk1boot1: mmc1:0001 8GUF4R partition 2 31.9 MiB [ 1.226886] omap_hsmmc 480b4000.mmc: ADMA err: ST_TFR, desc at 0xfe441008 follows the erroneous one [ 1.228069] mmcblk1: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00 [ 1.229261] mmcblk1: retrying using single block read [ 1.229960] mmcblk1: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 1.231130] blk_update_request: I/O error, dev mmcblk1, sector 0 [ 1.231951] mmcblk1: error -84 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 [ 1.233120] blk_update_request: I/O error, dev mmcblk1, sector 1 [ 1.233945] mmcblk1: error -84 transferring data, sector 2, nr 6, cmd response 0x900, card status 0x0 [ 1.235114] blk_update_request: I/O error, dev mmcblk1, sector 2 [ 1.235931] mmcblk1: error -84 transferring data, sector 3, nr 5, cmd response 0x900, card status 0x0 [ 1.237100] blk_update_request: I/O error, dev mmcblk1, sector 3 [ 1.237917] mmcblk1: error -84 transferring data, sector 4, nr 4, cmd response 0x900, card status 0x0 [ 1.239084] blk_update_request: I/O error, dev mmcblk1, sector 4 [ 1.239903] mmcblk1: error -84 transferring data, sector 5, nr 3, cmd response 0x900, card status 0x0 [ 1.241072] blk_update_request: I/O error, dev mmcblk1, sector 5 [ 1.241890] mmcblk1: error -84 transferring data, sector 6, nr 2, cmd response 0x900, card status 0x0 [ 1.243057] blk_update_request: I/O error, dev mmcblk1, sector 6 [ 1.243873] mmcblk1: error -84 transferring data, sector 7, nr 1, cmd response 0x900, card status 0x0 [ 1.245057] blk_update_request: I/O error, dev mmcblk1, sector 7 [ 1.245822] Buffer I/O error on dev mmcblk1, logical block 0, async page read [ 1.246800] omap_hsmmc 480b4000.mmc: ADMA err: ST_TFR, desc at 0xfe441008 follows the erroneous one [ 1.247980] mmcblk1: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00 [ 1.249170] mmcblk1: retrying using single block read [ 1.249869] mmcblk1: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 1.251036] blk_update_request: I/O error, dev mmcblk1, sector 0 [ 1.251859] mmcblk1: error -84 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 [ 1.253027] blk_update_request: I/O error, dev mmcblk1, sector 1 [ 1.253845] mmcblk1: error -84 transferring data, sector 2, nr 6, cmd response 0x900, card status 0x0 [ 1.255082] mmcblk1: error -84 transferring data, sector 3, nr 5, cmd response 0x900, card status 0x0 [ 1.256310] mmcblk1: error -84 transferring data, sector 4, nr 4, cmd response 0x900, card status 0x0 [ 1.257532] mmcblk1: error -84 transferring data, sector 5, nr 3, cmd response 0x900, card status 0x0 [ 1.258760] mmcblk1: error -84 transferring data, sector 6, nr 2, cmd response 0x900, card status 0x0 [ 1.259982] mmcblk1: error -84 transferring data, sector 7, nr 1, cmd response 0x900, card status 0x0 [ 1.261153] Buffer I/O error on dev mmcblk1, logical block 0, async page read [ 1.262070] mmcblk1: unable to read partition table [ 1.532364] EXT4-fs (mmcblk0p3): recovery complete

Hi GJ, Is this still an open issue for you or were you able to resolve the issue yourself? regards Suman

Ticket Name: CCSTUDIO: Using CCS scripting with Lauterbach debugger.

Part Number: CCSTUDIO Other Parts Discussed in Thread: TDA2 Hi, I have a TDA2XX-EVM on which i'm loading and running few binaries of different cores. Here i'm using Spectrum Digital XDS560V2 STM USB Emulator. Also i'm using scripts to launch ccxml, load and run binaries. But i need to use Lauterbach debugger instead of this spectrum digital debugger. But i could'nt find any example scripts with respect to Lauterbach debugger. Can anyone please tell me or send me a reference links that specifies the use of Lauterbach debugger for my TDA2XX regards, Likhith

-0- Which TDA2 chip are you using? Does it have a single A15 or a dual-A15? I do have TRACE32 CMMs which are converted versions of GELs which I use. Typically these are shared via TI-CDDS. If you have access I could upload there. If you tell exactly which CPU you have I can see about uploading a subset here. -1- Lauterbach on their website (and in their release images) has simplified scripts which allow running code on TDA2 systems. It might be one of these is sufficient for whatever you are trying to run. https://www.lauterbach.com/scripts/hardware/arm~tda2x~vayu_evm/hardware-arm-tda2x-vayu_evm_20200205093516_all_files.zip https://www.lauterbach.com/scripts/hardware/arm~dra72x~j6_eco_evm/hardware-arm-dra72x-j6_eco_evm_20200205093452_all_files.zip https://www.lauterbach.com/scripts/hardware/arm~dra7xx/hardware-arm-dra7xx_20200205093452_all_files.zip Regards, Richard W.

Ticket Name: Compiler/AM5749: Running pytorch-ai-devkit Demos on AM5749 IDK

Part Number: AM5749 Other Parts Discussed in Thread: TDA4VM Tool/software: TI C/C++ Compiler Hi Experts, I have two specific questions: 1) I have already tested caffe-jacinto-models and they seem to work fine on my device. Now I am trying to test pytorch-jacinto-ai-devkit! I believe the models supposed to work on my device as well. Is it correct? If so, what adjustments should I be making in order to run any demo in pytorch-jacinto-ai-devkit. 2) Can I run the models available in pytorch-jacinto-ai-devkit using CPU-ONLY? I currently don't have access to GPU, so would it be possible to run these demos? Thanks in Advance,

Hi Adnan, from GIT I see this works on latest J7 (TDA4VM) devices. Not on AM57x. If you are starting evaluation/testing this might be OK, but just wanted to clarify. From https://github.com/TexasInstruments/jacinto-ai-devkit we have: "Deep Learning Examples for Jacinto7 family of devices - e.g. TDA4VM" With respect to your questions, I will come back soon after checking with one of our experts. thank you, Paula

Thanks Paula - your answer is correct. We have tested the models in pytorch-jacinto-ai-devkit only on TDA4VM. We do not know whether they work on the older devices. Best regards,

Ticket Name: Linux/TDA2: PCI configuration space access is not aligned

Part Number: TDA2 Tool/software: Linux Hello, I have got an issue with Linux 4.4.84 from PSDK 3.03 running on TDA2xx EVA board. I have noticed that the accesses to PCI configuration space registers are not aligned to 4B boundary which results in incorrect reading of the, for example, status register. Upon implementing the accesses using pci_bus_read_config_dword they are being read correctly. Thinking that this is a problem related solely to the Linux version, I've had a look into the same code from more recent kernels and it is the same. However, on my PC where I run kernel 4.16.7 all my PCI devices' registers are correctly read using those non-aligned accesses. What I would like to ask is if this problem is in any way related to the board itself and its A15 core. I'm seeing much more non-aligned accesses which probably need to be patched. Is this a known problem when it comes to TI boards? If yes, is there any official patch for this? Thank you in advance. Nick

Hi Nick, There are known issues with configuration space access for registers not aligned to 4B boundary. This is documented in the DRA7xx Silicon Errata found here (Errata ID i870) www.ti.com/.../sprz398i.pdf A work around patch has been pushed and is available in later kernel versions. The patch can be accessed here. patchwork.kernel.org/.../ Regards Shravan

Hi Shravan, This patch resolved my issue and I would just like to inform whoever uses this patch in the future to go through each of the 4 parts since this one alone is not enough, at least for kernel 4.4.84 that comes with PSDK 3.03. Another thing that is worth mentioning is that the 'pci-dra7xx.c' patch from part 4 is not directly applicable to pci-dra7xx.c of kernel 4.4.84 so I had to pick some parts manually. This leads me to the question why are there TI patches for newer kernel versions but kernel 4.4.84 without any critical patches always comes with PSDK which leads to so much unnecessary confusion and issues. Regards, Nick

Hi Nick, Thank you for the information. We will be making a PSDK release next month which is based off K-4.14 , and this will include all these fixes, thus avoiding the confusion with back-porting some of these patches. Regards Shravan

Hi Shravan, I'm very glad to hear that. Thank you for the help, you can now close this thread. Regards, Nick

Ticket Name: CCS/TDA2EX17EVM: TDA2, Boot from SD card, and flash the image onto EMMC?

Part Number: TDA2EX17EVM Tool/software: Code Composer Studio Hi Champs: I wonder if the TDA2 can Boot from SD card, and flash the image onto EMMC? If yes, where is the document to explain the detail about this? BR Rio

Hi Rio, Please refer here : . This is for other Boards, but steps should be similar and you can take reference from it

Hi R. The link is for Linux. Do you have the RTOS version? BR Rio

Hi Rio, Please refer to these links and see if it is helpful. Particularly this point : "You can refer to mmc app present here: PROCESSOR_SDK_VISION_03_03_00_00\ti_components\drivers\pdk_01_09_00_17\packages\ti\csl\example\mmcsd\mmc_raw_access\. We don't have a lot of SW support for eMMC on RTOS side. I would recommend you to use QSPI or NOR flash for storing data instead of eMMC." e2e.ti.com/.../495282

Hi R. So, you mean to boot from the QSPI / NOR flash directly? And dont need to use the EMMC boot? Is my understanding correct? BR Rio

Hi Rio, Yes you can boot from QSPI flash or NOR and there is no need for eMMC boot. Regards, Rishabh

Ticket Name: CCS/AM5749: AM574x IDK target configuration

Part Number: AM5749 Other Parts Discussed in Thread: TDA2 Tool/software: Code Composer Studio Dear TI Team, There is no target configuration listed to connect IDK_AM574x board(XDS 100v2 USB debug probe) to EVE_1 or EVE_2 core. Kindly share the files needed for the configuraion. CCS version using is: Code Composer Studio 9.0.1 Thanks and Regards, Deepa

Hi Deepa, The EVE programming toolchain is not publicly available, and as such, we do not expose the EVE cores in CCS. Regards, Mike

Hi Mike, We have that EVE cores available for TDA platforms. And we are having PROCESSOR_SDK_VISION_03_07_00_00 and arp32_1.0.7 cg tool as a part of it. Thanks and Regards, Deepa

Hi Deepa, At this time programming of the EVE is not supported on the AM57xx family. AM57xx treats the EVE as a black-box module for machine learning offload through the TIDL API. TDA2 and vision SDK have a different support model. What are you trying to do? Regards, Mike

Ticket Name: TDA3MV: DSP model number for LAPACK

Part Number: TDA3MV Hello, Please tell me the model number of DSP that LAPACK can use.

Hi, I believe that this is getting discussed in a thread already: https://e2e.ti.com/support/processors/f/791/t/947670 I request you to post on the same thread and ping for further questions on the same topic. Closing this thread now. Regards Karthik

Ticket Name: PROCESSOR-SDK-J721E: Migrating sensor support from J6 to J7 SDK

Part Number: PROCESSOR-SDK-J721E Other Parts Discussed in Thread: TDA2 Hello, My customer would like to use the OV2311 sensor along with TDA4 as he was formerly using it with TDA2 processors. Do we have any plan to support OV2311 or OV2312 in a J7 SDK? If not, what would it take for one to migrate the driver from the J6 SDK to the J7 SDK? Thank you. Best regards, François.

OV231x is not planned in J7 SDK. To add new sensor, please follow the steps at http://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/psdk_rtos/docs/user_guide/developer_notes_image_sensor.html

Ticket Name: Linux/TDA2: PSDK3.4 can't start weston normally?

Part Number: TDA2 Tool/software: Linux Hi TI, I run PSDKLA3.4 in tda2x evm. Because I want to run the QT app in it. But the weston can't start up.like this: root@dra7xx-evm:~#
root@dra7xx-evm:~# cat /var/log/weston.log
Date: 2018-10-23 UTC
[07:36:18.772] weston 1.9.0
               http://wayland.freedesktop.org
               Bug reports to: bugs.freedesktop.org/enter_bug.cgi
               Build: 1.8.93-2-gb05cdb8 configure.ac: bump to version 1.9.0 for the official release (2015-09-21 18:11:26 -0700)
[07:36:18.772] OS: Linux, 4.4.84-00027-g018eb62-dirty, #7 SMP PREEMPT Sat Sep 29 11:18:05 HKT 2018, armv7l
[07:36:18.775] Using config file '/etc//weston.ini'
[07:36:18.779] Loading module '/usr/lib/weston/drm-backend.so'
[07:36:18.862] Output repaint window is 7 ms maximum.
[07:36:18.862] initializing drm backend
[07:36:18.865] using /dev/dri/card0
[07:36:18.867] Loading module '/usr/lib/weston/gl-renderer.so'
loaded module : gbm_pvr.so
found valid GBM backend : gbm_pvr.so
[07:36:19.175] warning: either no EGL_EXT_platform_base support or specific platform support; falling back to eglGetDisplay.
[07:36:19.205] failed to initialize display
[07:36:19.205] EGL error state: EGL_BAD_ALLOC (0x3003)
[07:36:19.205] failed to initialize egl
[07:36:19.205] fatal: failed to create compositor backend
PVR:(Error): OpenServices: PVRDRMOpenRender failed [0, ]
PVR:(Error): PVRSRVConnect: Unable to open connection. [0, ]
PVR:(Error): Couldn't connect to services [0, ]
root@dra7xx-evm:~#
root@dra7xx-evm:~# and the /etc/powervr.ini is : root@dra7xx-evm:~#
root@dra7xx-evm:~# cat /etc/powervr.ini
[default]
#WindowSystem=libpvrws_WAYLAND.so

[weston]
DbmDriverName=vdrm

[weston-simple-egl]

#QT app
[animatedtiles]
 And I have add the cma=128M. Have any suggestions ? Thanks! Regards, Sam.

Hi Sam, Are you using the PSDKLA 3.04 filesystem or vision-sdk 3.04 filesystem? Vision-sdk filesystem doesn't provide QT applications

Hi Ramprasad, I'm using PSDKLA3.04 filesystem . Regards, Sam.

Hi Sam, vDRM feature can be currently used only with VISION-SDK. It can not work with PSDKLA3.04.

Hi Ramprasad, So how can I run the QT app in the PSDK3.04? The weston start up failed, as you see . Regards, Sam.

Hi Ramprasad, Maybe I made a mistake. I just want to run a QT app by using PSDKLA3.04. Can you give me some suggestions? Thank you very much . Regards, Sam.

Hi Sam, If you want to use only PSDKLA, please download latest SDK from this link downloads.ti.com/.../index_FDS.html and prepare SD card. This should work fine for QT application. You don't need to make any changes in powervr.ini Thanks Ram

Hi Ram, Thanks for your reply. I'm confusing the VSDK with the PSDKLA. And now I can see the matrix-gui. Thank you ! Regards, Sam.

Ticket Name: TDA2PXEVM: code to select QSPI mode in SBL for TDA2Px could be wrong?

Part Number: TDA2PXEVM Hi, I am not sure if the code below in the SBL is handling incorreclty the TDA2Px SoC. Basically is taking the same path as the TDA2xx which seems to have an issue with rev. 1.0 and then selecting an slower mode. //code in platform_tda2xx.c uint32_t PlatformGetQspiMode(void) { uint32_t mode; #if defined (SOC_TDA2EX) mode = 0U; #else uint32_t siliconRev = PlatformGetSiliconRev(); if (0U == siliconRev) { /* On ES 1.0 TDA2xx silicon only mode 3 works */ mode = 3U; } else { /* On ES 1.1 TDA2xx silicon both mode 0 & 3 work */ /* Reutrning 0 as it can work at higher frequency */ mode = 0U; } #endif return mode; } I am guessing that the code needs the following fix: ... #if defined (SOC_TDA2EX) || defined (SOC_TDA2PX) mode = 0U; #else ... May anybody confirm if I am right about that? Thanks in advance. Regards, Alexander

Hi Alex, it looks like a bug, let me check and get back to you. Regards, Brijesh

Hi Brijesh any progress on this? BTW, I have a question related to one comment in that function: ... /* Reutrning 0 as it can work at higher frequency */ ... why is telling that mode 0 is faster than mode 0? AFAIK the SPI clock mode does not affect the speed setup...or is this some specific to TDAx? Regards, Alexander

Hi, well, I found myself the answer to my question concerning the different clock speeds supported, depending of the QSPI clock mode. It is in the datasheet: I did not see that table before and I was even clocking the QSPI to 128 MHz (and it was working). Since it is working @ 128 MHz, I can imaging that with 96Mhz (10.41nS) is going to work too. But I still would like to hear an official statement from TI that the TDA2Px Rev 1.0 may work in QSPI in mode 0 @ 96 Mhz. Thanks. Regards, Alexander

Hi Alex, Yes, this is confirmed. It is a bug in the driver. TDA2Px does support Mode0 and Mode3 for QSPI. Rgds, Brijesh

Thanks a lot for the confirmation Brijesh! Regards, alexander

Ticket Name: RTOS/TDA2: Have image sensor driver sample code can provide to refer?

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, As CMOS Image Sensor Solutions pdf from TI we know TDA2 support AR0136 of OnSemi and OV10640 of Omnivison. Have AR0136 or OV10640 image sensor driver sample code can provide to us refer? Thanks for your support. P.S We can find seem like image sensor driver sample code at ($SDKv3.3_INSTALL)\ti_components\drivers\pdk_01_09_00_17\packages\ti\drv\vps\src\devices.

Hi, Yes, you could find the code for the sensor in VSDK under path vision_sdk\apps\src\rtos\iss\src\sensor\ov10640\iss_sensor_ov10640.c or in the PDK drivers.. Rgds, Brijesh

Hi Brijesh, I find it, thanks. Which one sample code can refer if we want to control AR0136 ?

Hi, AR0136 is not supported in VSDK. Rgds, Brijesh

Understand, thanks.

Ticket Name: RTOS/TDA2PXEVM: I want to know how to boot eMMC of TDA2PX at TI-RTOS

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hi, Sir As title, I want to know how to boot eMMC of TDA2PX at TI-RTOS. We are doing OS changes from linux to TI-RTOS. So. We downloaded RTOS image(appimage and MLO) in uboot. But,The log looks like this and it does not read the image in emmc. SD Boot - File open fails Valid App Image is not Available Could tou please advice us how to achieve it. Thanks,

Hi, SBL supports QSPI, NOR and SD boot for TDA2 devices. eMMC boot is supported only by Linux i.e. Uboot. Regards, Rishabh

Ticket Name: TDA2: Any limit for eltwise in tidl?

Part Number: TDA2 Hi, I use the the following block in cifar-10 network, but it always go wrong. And I try to change it to the following block, and it works well, but accuracy has a large drop There is something wrong with the first block or something limits for eltwise block? Thanks

Both the cases are suported by TIDL. are your using caffe or tensorflow trained model? For the first case are you oberserving import issue or wrong inference output? Can you share the model, we will have look. Rgerda, Kumar.D

Hi, Please help to check the model, thanks eltwise_without_relu_previous.tar.gzeltwise_with_relu_previous.tar.gz

Hi , Do you have any updates about this issue? Thanks. Jerry

Hi Jerry, I am working on it, I will post my response here as soon as I have some update. Thanks for your patience. Regards, Praveen

Hi Jerry, As indicated in the TIDL user guide section 3.9 TIDL Limitation, Eltwise layer only supported on inputs of same types, but in the first case (eltwise_without_relu_previous), one input "layer_64_1_bn3" is signed and other input "conv1_pool" unsigned, so it is not supported and hence not working. Please make sure both the input should be of same type (either both are unsigned or signed inputs). Thanks, Praveen

Hi Praveen, Got it. I'll modify the net structure to satisfy this limitation, and make a validation later. thanks for your help. Thanks, Jerry

Ticket Name: TDA2: Error in building TestAppOmap4 from ivahd_h264enc_02_00_09_01_production package

Part Number: TDA2 Hi I am trying to build the TestAppOmap4 from ivahd_h264enc_02_00_09_01_production package but i am getting the following error: C:\PROCESSOR_SDK_VISION_03_03_00_00\ti_components\codecs\ivahd_h264enc_02_00_09_01_production\packages\ti\sdo\codecs\h264enc\app\build\TestAppOmap4\make>gmake -s deps Scaning dependencies... process_begin: CreateProcess(NULL, del /f libs.dep, ...) failed. make (e=2): The system cannot find the file specified. Some_path/Local/Temp/make10828-1.sh: 1: Syntax error: "(" unexpected gmake: *** [deps] Error 2 I am following the instructions as mentioned in H264_Encoder_HDVICP2_UserGuide.pdf for build steps. Please help in resolving the issue. Regards Mayank

Hi Mayank, I Hope all the environmental variable setting done as mentioned in ReleaseNotes. from path : \h264enc\app\build\TestAppOmap4\make gmake -s -k clean gmake -s -k deps gmake -s -k all -> This will build the TestAppEncoder.out @ ..\h264enc\app\build\TestAppOmap4\out I have verified building this at my setup.

Hi Prasanth, Thanks for your reply. After executing the commands you have listed in your mail i got the following output: C:\PROCESSOR_SDK_VISION_03_03_00_00\ti_components\codecs\ivahd_h264enc_02_00_09_01_production\packages\ti\sdo\codecs\h264enc\app\build\TestAppOmap4\make>gmake -s -k clean process_begin: CreateProcess(NULL, del /f alg_control.PP alg_create.PP alg_malloc.PP buffermanager.PP h264enc_ti_config.PP h264enc.PP H264EncRmanConfig.PP H264EncTest.PP h264enc_ti_trace.PP t libs.dep, ...) failed. make (e=2): The system cannot find the file specified. C:\PROCESSOR_SDK_VISION_03_03_00_00\ti_components\codecs\ivahd_h264enc_02_00_09_01_production\packages\ti\sdo\codecs\h264enc\app\build\TestAppOmap4\make>gmake -s -k deps Scaning dependencies... C:/Users/magarwa1/AppData/Local/Temp/make2336-1.sh: 1: Syntax error: "(" unexpected gmake: *** [deps] Error 2 C:\PROCESSOR_SDK_VISION_03_03_00_00\ti_components\codecs\ivahd_h264enc_02_00_09_01_production\packages\ti\sdo\codecs\h264enc\app\build\TestAppOmap4\make>gmake -s -k all Compiling C:ticgtoolsbinarmcl: not found gmake: *** [..\..\..\..\app\Build\TestAppOMAP4\Obj\alg_control.obj] Error 127 Compiling C:ticgtoolsbinarmcl: not found gmake: *** [..\..\..\..\app\Build\TestAppOMAP4\Obj\alg_create.obj] Error 127 Compiling C:ticgtoolsbinarmcl: not found gmake: *** [..\..\..\..\app\Build\TestAppOMAP4\Obj\alg_malloc.obj] Error 127 Compiling C:ticgtoolsbinarmcl: not found gmake: *** [..\..\..\..\app\Build\TestAppOMAP4\Obj\buffermanager.obj] Error 127 Compiling C:ticgtoolsbinarmcl: not found gmake: *** [..\..\..\..\app\Build\TestAppOMAP4\Obj\h264enc_ti_config.obj] Error 127 Compiling C:ticgtoolsbinarmcl: not found gmake: *** [..\..\..\..\app\Build\TestAppOMAP4\Obj\h264enc.obj] Error 127 Compiling C:ticgtoolsbinarmcl: not found gmake: *** [..\..\..\..\app\Build\TestAppOMAP4\Obj\H264EncRmanConfig.obj] Error 127 Compiling C:ticgtoolsbinarmcl: not found gmake: *** [..\..\..\..\app\Build\TestAppOMAP4\Obj\H264EncTest.obj] Error 127 Compiling C:ticgtoolsbinarmcl: not found gmake: *** [..\..\..\..\app\Build\TestAppOMAP4\Obj\h264enc_ti_trace.obj] Error 127 Compiling C:ticgtoolsbinarmcl: not found gmake: *** [..\..\..\..\app\Build\TestAppOMAP4\Obj\InterruptVecTable.obj] Error 127 Compiling C:ticgtoolsbinarmcl: not found gmake: *** [..\..\..\..\app\Build\TestAppOMAP4\Obj\h264e_host_scalingmatrix.obj] Error 127 gmake: Target `all' not remade because of errors. C:\PROCESSOR_SDK_VISION_03_03_00_00\ti_components\codecs\ivahd_h264enc_02_00_09_01_production\packages\ti\sdo\codecs\h264enc\app\build\TestAppOmap4\make> Regards Mayank

Hi Mayank, I will let Prashant look into this further. However, my two cents is that the "/" does not seem to be taking effect in your case. Notice "C:ticgtoolsbinarmcl" Thanks and Regards, Piyali

Hi Mayank, Please check the environmental variables(said in the release notes) are set correct and the paths set have taken effect.

Hi, Thanks Prashanth and Piyali.I am able to build now. Regards Mayank

Ticket Name: TDA2PXEVM: To synchronize the time between data of A15 and data of IPU1

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Dear， We need to synchronize the time between image data collected by A15 and IMU data collected by IPU1, and then store the data for analysis. Is there any way to do that? Thank you very much! Terence Xia from ECARX China.

Hi Terence, You could use sync link to synchronize two or more frames, coming from different chain. but please note that you need to add time stamp in the data collected on IMU. Rgds, Brijesh

Hi Brijesh, Is there a global time in TDA2 that can be used by all processors , including A15,IPU, DSP, etc. If so, where can I find it in the vision SDK. I need to send this time to the external device, I mean to synchronize the time with the external device.For example, an external MCU linked to TDA2. Thank you very much! Terence Xia from ECARX China.

Yes, you could use Utils_getCurGlobalTimeInUsec API to get the current timestamp. This API uses global timer. Rgds, Brijesh

Hi Brijesh, I have a question about that, In this code path: vision_sdk/links_fw/src/hlos/osa/src/osa_global_time.c，there is a function of OSA_getCurGlobalTimeInUsec, like Utils_getCurGlobalTimeInUsec API，Are they all getting the same timer? When I get the time, how can I send it to the external MCU, and TDA2 and MCU connected with UART. Thank you very much ! Terence Xia from ECARX China

Hi Terence, Yes, both of them uses same UTC timer. Rgds, Brijesh

Ticket Name: TDA2E: Caffe jacinto quantization aware training

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Hello, \ As title, I wonder does the caffe-jacinto offer quantization aware training for the SSD? I've tried the offered two different base-networks SSDs: jacintoNetV2 & mobilenet: \ As previously noted by a TI's engineer, depth-wise convolution will suffer more from the runtime weights quantization, and that is also the result I got as well: JacintoNet_v2 SSD: After sparse training: mAP = 0.88 Quantization test shows: mAP = 0.74 MobileNet SSD: After sparse training: mAP=0.89 Quantization test shows: mAP=0.62 \ Though the quantization loss is lesser in jacintoNet, but I still want to minimize the quantization loss, therefore: (1.) I'm asking if the quantization aware training is offered for caffe-jacinto? (2.) Any other suggestions to minimize the quantization loss? (3.) Is there a way to turn off the runtime quantization (for accuracy experiment purposes) when running the model on TDA2 dev board? Thank you, Wei Chih

Hi Wei Chih, I will check with the team internally and come back you. Thanks, Praveen

Hi, Here are the answers. >>(1.) I'm asking if the quantization aware training is offered for caffe-jacinto? No. It is not offered in caffe-jacinto. It is offered for PyTorch, but that PyTorch repository is targeted towards TDA4, not TDA2. >>(2.) Any other suggestions to minimize the quantization loss? Increasing weight decay during training causes the weights to be more suitable for quantization. So, you can try training with a higher weight decay. But this has to be done in all the training phases, right from the beginning. >>(3.) Is there a way to turn off the runtime quantization (for accuracy experiment purposes) when running the model on TDA2 dev board? No. Only quantized inference is supported on the EVM. Best regards,

Ticket Name: TDA3MV: Detailed model number of DSP (C66x)

Part Number: TDA3MV Other Parts Discussed in Thread: TDA2 Please tell me the detailed model number of DSP (C66x) of TDA3MV. Does this DSP support LAPACK? Also, do I have to port LACACK myself?

Hi, Please follow the below link. Thanks Gaviraju

Fast of all, Please tell me the detailed model number of DSP (C66x) of TDA3MV.

Hi, It is the same as the TDA2 and therefore you should check this post: https://e2e.ti.com/support/processors/f/791/p/947670/3506002#3506002 Regards Karthik

Hello, TDA3MV DSP information is not provided here. Please tell me the detailed model number of DSP (C66x) of TDA3MV.

Ticket Name: TDA2EXEVM: How to set the TIDL config.mk?

Part Number: TDA2EXEVM Other Parts Discussed in Thread: MATHLIB, TDA2 DSP_TOOLS ?="C:\PROCESSOR_SDK_VISION_03_07_01_00\ti_components\cg_tools\windows\ti-cgt-c6000_8.2.4" ARP32_TOOLS ?="C:\PROCESSOR_SDK_VISION_03_07_01_00\ti_components\cg_tools\windows\arp32_1.0.7" TIARM_TOOLS ?="C:\PROCESSOR_SDK_VISION_03_07_01_00\ti_components\cg_tools\windows\ti-cgt-arm_16.9.2.LTS" XDAIS_PATH ?="C:\PROCESSOR_SDK_VISION_03_07_01_00\ti_components\codecs\xdais_7_24_00_04" UTILS_PATH ?="C:\TI\ccsv5\utils\cygwin" VXLIB_PATH ?="C:\PROCESSOR_SDK_VISION_03_07_01_00\ti_components\algorithms\vxlib_c66x_1_1_3_0" DMAUTILS_PATH ?="C:\PROCESSOR_SDK_VISION_03_07_01_00\ti_components\algorithms\REL.DMAUTILS.00.08.00.02\dmautils" ALGFRAMEWORK_PATH ?="C:\PROCESSOR_SDK_VISION_03_07_01_00\ti_components\algorithms\REL.ALGFRAMEWORK.02.08.00.00\algframework" MATHLIB_INSTALL_DIR ?="C:\PROCESSOR_SDK_VISION_03_07_01_00\ti_components\algorithms\mathlib_c66x_3_1_0_0" SHOW_COMMANDS ?= 0 LINUXENV ?= x86 LINUX_BUILD_TOOLS ?="/home/uid/tools/linaro-2017.11" # Default platform # Supported values: vayu,vme TARGET_SOC ?= vayu # Default CORE is dsp # Supported values: dsp, eve, arm CORE ?= dsp # Default TI_DEVICE # Supported values: PC, TI_DEVICE (SIMULATORS or EMULATOR ) TARGET_PLATFORM ?= TI_DEVICE # Default C66 # Supported C64T, C64P, C64, C66, C674, C67, C67P, m4 TARGET_CPU ?= C66 ifeq ($(CORE),eve) TARGET_CPU:= endif Hi Champs: #1. We now know the TIDL for TDA2/3 only be able built in the Windows environment, as Praveen Said. So, in this path: C:\PROCESSOR_SDK_VISION_03_07_01_00\ti_components\algorithms\REL.TIDL.01.01.03.00\makerules The config.mk needs to be set according the Windows CG tool envs. My questions are how to set those 2 parameters in the below config.mk? if we are now in the windows? --> LINUXENV ?= x86 LINUX_BUILD_TOOLS ?="/home/uid/tools/linaro-2017.11" #2.What's the x86 means? #3. How to set this file for TDA2 and TDA3? According this section, is the Vayu = TDA2 and Vme = TDA3? # Default platform # Supported values: vayu,vme TARGET_SOC ?= vayu #4.is the Core set as DSP and Target CPU = DSP, does this mean the EVE / ARM won't spend the effort for TIDL? #5. How to set the DSP + EVE working concurrently for TDA2? BR Rio

Hi Rio, This config.mk file is used to build standalone TIDL out files for either DSP or EVE cores separately. 1, 2 -> Linux build is not supported, so you can ignore them. 3 -> "TARGET_SOC " can also be ignored for TIDL build because the out files build will be for specific core (DSP or EVE) not for SOC. VSDK builds for specific SOC. 4-> For building for EVE set Target CPU = EVE 5-> This is done through VSDK use cases and layers partition for EVE and DSP cores is done by import tool, please refer to FAQ21 and 22 for more details on this partioiton. Thanks, Praveen

Ticket Name: RTOS/TDA2: tidl_OD Usecase error

Part Number: TDA2 Tool/software: TI-RTOS Hi Everyone, I am trying to run "TIDL OD usecase" on VSDK 3.4 , I believe the following bin files are required for the successful execution of usecase > TIDL OD Network file (NET_OD.bin) > TIDL OD Parameter file (PRM_OD.bin) > TIDL OD Usecase input data file (inData_OD) > TIDL OD Usecase input header file (inHeader_OD) For the network file and parameter file I have copied below files from the path , vision_sdk\apps\tools\TIDL_files\ > tidl_net_jdetNet_ssd.bin > tidl_param_jdetNet_ssd.bin For the Use case input data , I have downloaded the clip files from CDDS (currently trying with clip2.avi under single_cam_video_input_clips) and followed the below procedure to generate header file and data file 1) inData_OD generation > ffmpeg -i clip2.avi -y -c:v libx264 -vframes 50 inData_OD 2) inHeader_OD generation >ffprobe -show_packets ./inData_OD >index.idx >PAT=size >sed -n "/$PAT/p" index.idx | cut -d' ' -f3 >> size_extracted.txt After this step, size_extracted.txt will contain size of the frames. Remove the string "size=" from each line in the file and save only the numbers in size_extracted_jelly.txt. >cat size_extracted_jelly.txt | perl -n -e 'printf("%08x\n",$_)' | sed 's/\(..\)\(..\)\(..\)\(..\)/0x\4\n0x\3\n0x\2\n0x\1/' | xxd -r -p > Size_test.bin && du -b Size_test.bin >cp Size_test.bin inHeader_OD I have also copied the respective text file with below details TIDL Configuration parameters ----------------------------- inputWidth=736 inputHeight=320 inputFile=inData_OD inputHDRFile=inHeader_OD netFileName=tidl_net_jdetNet_ssd.bin paramFileName=tidl_param_jdetNet_ssd.bin fps=30 threshold=0.3 However , I am getting following error while running the usecase DECODE: ERROR: ALGPROCESS FAILED (status=0x20208001) !!! DEC_LINK: outArgs->viddec3OutArgs.extendedError for channel 0 Error: 0x20208001 DEC_LINK: Sequence called number 1 Kindly help me on resolving this issue . I have tried same for Semantic segmentation usecase with net and param bin files from the path /ti_components/algorithms/REL.TIDL.01.01.01.00/modules/ti_dl/test/testvecs/config/tidl_models/jsegnet21/ but i got the same error. I have referred below forum links for it

Hi Surendra, Could you please verify inputWidth & inputHeight of the file you generated is same as you are passing in .txt file ? TIDL inData_OD & inHeader_OD file also available in CDDS Could you please download & verify with that ? cdds.ext.ti.com/.../emxNavigator.jsp Regards Surya

Hi Surya, I have used input files from the same CDDS link which you mentioned only , I am using single cam video input files for my testing . I have performed the steps I mentioned before to create the inData and inHeader files . I couldn't find inHeader_OD files in the link so I have generated it . In .txt file I have metioned the width and height as 736 & 320 respectively . The resolution of the video is 1920x1080 will that cause issue . Regards, Surendar

Hi Surya , I have fousnd inHeader and inData under xcam folder , I am not sure whether that is the file you are mentioning about . Anyway I have renamed both as inHeader_OD and inData_OD and copied into SD card . When I ran the tidl_OD usecase I am getting the following error : Assertion @ Line: 220 in nullSrcLink_tsk.c: frameLength < bitstreamBuf->bufSize : failed !!! Regards, Surendar

Hi, The difference in resolution will cause issue. You can find the files in below link cdds.ext.ti.com/.../emxNavigator.jsp Regards, Anuj

Hi Anuj , I have downloaded the files from the link you mentioned only , I am using clips under "single cam video input" . I am maintaining the resolution of the video in txt file as 736x320 , if I change that to 1920 x 1080 which is resolution of the clips given in the link , assertion is throwing out as below Set DSS parameter failed [IPU1-0] 26.733910 s: Assertion @ Line: 459 in displayLink_drv.c: status==SYSTEM_LINK_STATUS_SOK : failed !!! [IPU1-0] 26.734398 s: Assertion @ Line: 459 in displayLink_drv.c: status==SYSTEM_LINK_STATUS_SOK : failed !!! Kindly help me in sorting out this issue

Hi Anuj & Surya, Is there any update on this Regards, V.B.Surendar

Hi, Please check for the correct files in that link. You are using wrong files. Regards, Anuj

Hi Anuj, I have used the files from the following path , please verify it is wrong or not : VISION_SDK_02.XX.XX.XX_INPUTS -> single_cam_video_input_clips -> clip2.avi I have used clip2.avi as inData_OD and also created inHeader_OD using this . Kindly guide me on this Regards , Surendar

Yes. This is wrong. You are searching in wrong folder.there will be a TIDl_files folder. In That folder you will find inData_OD. You do not need to rename any file. Regards, Anuj

Hi Anuj , Thank you , it is working as you said the files are wrong Regards, surendar

Ticket Name: TDA2SX: Why is the header file name and type of this reference different from that of your demo?

Part Number: TDA2SX Why is the reference header file name and type different from demo? I used the gentool you provided to generate this file (errors are reported at compile time and can only be compiled after manually changing it to be the same as your file). What is the reason for this? This is your demo. This is automatically generated by gentool. The compiler will report errors. SDK is th V3.06 and path is "vision_sdk\apps\src\hlos\adas\src\usecases\vip_single_cam_opencvcanny_sgx_display".

Hi, I have forwarded your question to respective team and they will reply here. Thanks, Praveen

Hi, Thanks for the update. The auto-generation tool is not updated & you can update the "link.cpp" then rebuild the code to get an updated auto-generation tool. Thanks Gaviraju

After I update gentool, the compiled code will prompt you about the use error of OpenCV library. After consulting the forum, it seems that opencv is not supported. If opencv is not supported by sdk v3.06, I will not enable opencv's usecase in the future.Would you like to confirm it with you?

Yes, openCV & OpenCL is deprecated from vision SDK Thanks Gaviraju

Ticket Name: Linux/TDA2EVM5777: The VPE link couldn't receive frame from previous Select link

Part Number: TDA2EVM5777 Tool/software: Linux Hi, My chain is consists of --------------------------------------------------------------------------------------------------- NullSource(A15) (ch0~3) -> Merge_cap(A15) -> Decode -> VPE_cap -> Dup_cap -> Sync_cap -> SgxFrmcpy(A15) -> Display Dup_cap -> Select Select -> VPE_dl -> Dup_dl Dup_dl -> Merge_dl Dup_dl -> Alg_tidlpreproc (DSP1) Alg_tidlpreproc (DSP1) -> Alg_tidl_Eve1 (EVE1) Alg_tidlpreproc (DSP1) -> Alg_tidl_Eve2 (EVE2) Alg_tidlpreproc (DSP1) -> Alg_tidl_Eve3 (EVE3) Alg_tidlpreproc (DSP1) -> Alg_tidl_Eve4 (EVE4) Alg_tidl_Eve1 (EVE1) -> Merge_OD(DSP1) Alg_tidl_Eve2 (EVE2) -> Merge_OD(DSP1) Alg_tidl_Eve3 (EVE3) -> Merge_OD(DSP1) Alg_tidl_Eve4 (EVE4) -> Merge_OD(DSP1) Merge_OD(DSP1) -> Alg_tidl_Dsp (DSP1) -> Merge_dl Merge_dl -> Sync_dl -> Alg_tiop(DSP1) -> Null(A15) --------------------------------------------------------------------------------------------------- The Sgx side is working normally but the VPE link of TIDL side (that is after Select link) is not receiving any frames from Select link. When i print each link statistics, the links in TIDL side didn't show any input & output FPS. I changed the ProcessData func in Select link link below. --------------------------------------------------------------------------------------------------- if (inBufList.numBuf) { Vps_printf("SELECT : inBufList numBuf %d", inBufList.numBuf); for (bufId = 0; bufId < inBufList.numBuf; bufId++) { #if 1 pBuf = inBufList.buffers[bufId]; UTILS_assert(pBuf->chNum < SYSTEM_MAX_CH_PER_OUT_QUE); pChInfo = &pObj->inChInfo[pBuf->chNum]; pSysCompBuf = (System_VideoFrameCompositeBuffer *)pBuf->payload; for (frameId = 0; frameId < pSysCompBuf->numFrames; frameId++) { for (planeId = 0; planeId < SYSTEM_MAX_PLANES; planeId++) { pVidBuf->bufAddr[planeId] = pSysCompBuf->bufAddr[planeId][frameId]; } pVidBuf->metaBufSize = pSysCompBuf->metaBufSize; pVidBuf->metaFillLength = pSysCompBuf->metaFillLength; pVidBuf->chInfo = pSysCompBuf->chInfo; pVidBuf->flags = pSysCompBuf->flags; } pOutBuf->payload = pVidBuf; pOutBuf->bufType = SYSTEM_BUFFER_TYPE_VIDEO_FRAME; pOutBuf->payloadSize = sizeof(System_VideoFrameBuffer); pOutBuf->chNum = 1; UTILS_assert(pOutBuf != NULL); #else --------------------------------------------------------------------------------------------------- Could you please let me know whether there is any incorrect things in that? Thanks & Regards, YOO

Hi Yoo, what is the type of 'pVidBuf'? Is it System_VideoFrameCompositeBuffer like pSysCompBuf? If so, then shouldn't you have: pVidBuf->bufAddr[planeId][frameId] = pSysCompBuf->bufAddr[planeId][frameId]; in the inner for loop? Regards, Yordan

The type of pVidBuf is System_VideoFrameBuffer. I refered 'SyncLink_makeCompositeBuffer' function in syncLink_tsk.c Regards, Yoo

Hi, Usecase does not seems proper. Where is the previous link of Dup_cap. Can you share the usecase stats. And share the jpg file of the usecase also. Regards, Anuj

My bad, previous link of Dup_cap is Vpe_cap. The actual connection was set correctly. The status of each link in SV side, input & output FPS were showed normally and displayed well. However, in TIDL side, Select link received videoComposite buffer normally from Dup link but VPE link couldn't received composite type. So, we tried to convert type from composite to videoframe buffer in Select link. Regards, Yoo

Hi, So i hope this issue is resolved. Regards, Anuj

Ticket Name: TDA2SX: Is it OK to mix VIN(VIP) pin groups?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Due to routing constraint, we cannot have a group of consecutive pins (for example VOUT1_D0 to VOUT1_D7) on the TDA2 to be assigned to the same VIN(VIP) group input. Is it OK to break the group? For example, as the picture below indicated, we have some of them assigned to VIN3 and some of them assigned to VIN4. Based on the TDA2 datasheet, all these pins can be mux-ed to either to VIN3 or VIN4. we couldn't find any document confirm or disconfirm if the pin groups can be mixed and matched. We have our product on the line waiting for this... we'd really appreciate you guys input! Li

Hi LI, Well, this depends really on your input data format. If your input data format is YUV422, which requires just D0 to D15 datalines, it should be ok. But if your input data format on VIN3A is RGB888, then it is not possible to mix the data lines as shown above. Also please check pinmux and see if above VIN4A datalines also support missing VIN3A datalines, there is a possibility to mix them. Regards, Brijesh

Hi Brijesh, Thanks for your reply. We are using this in image radar application where all 24 bit data lines are being used. (which is similar to your RGB888 example. We did checked the TDA2's pinmux and they support the above-mentioned pin functions. Could you please elaborate why in RGB888 case we cannot mix data lines? THanks Li

Hi LI, Li Niu said: Could you please elaborate why in RGB888 case we cannot mix data lines? Because then we need to use two VIN ports to capture data and then need to manually merge the captured data.. I would not recommend doing this. Instead, if single VIN port can be used for capturing RGB888 format, by changing pinmux, it would be easier. Regards, Brijesh

Ticket Name: TDA2: Flickering is observed on displaying fisheye frame by using Opengl es in Vision Sdk 3.02

Part Number: TDA2 HI, We have a problem about displaying fisheye frames by using Opengl es in Vision Sdk 3.02. We have posted a question which is flagged as solved, but the problem is still unsolved actually. e2e.ti.com/.../2700090 We also saw a bug fix in release note for Vision Sdk 3.04. According to the description, it seems like our problem. ADASVISION-1877 [TDA2xx Linux] Flickering is observed on running back to back sgx related UC S1-Critical VISION_SDK_03_03_00_00 Can you describe this bug fix in depth? And because we have developed our system on vision sdk 3.02 a lot, can we get a patch for this bug for vision sdk 3.02. Mason Su Best regards

ADASVISION_1877.txtHi, PFA of the patch on top of VSDK 3.3. Regards, Anuj

Ticket Name: TDA2: SSD different result between quantStatusTool and TDA2EXVEM

Part Number: TDA2 Hi: I traine a SSD model changed on "github.com/tidsp/caffe-jacinto-models/tree/caffe-0.16/trained/object_detection/voc0712". With quantStatusTool,the result is good,almost every target object is detected,But when I run the model on TDA2EXEVM,some object could't be detected in some frames.for example,as below this result is runned with quantStatusTool;but the "1" object couldn't be detected with TIDL_OD usecase when runned on TDA2EXEVM. And with quantStatusTool,I found the "1" object's confidence is 0.316087,so I set the "scoreThreshold" to 0.3 in TIDL_OD usecase,but the "1" object still couldn't be detected. Is there something I missed? My import config file is below: # Default - 0 randParams = 0 # 0: Caffe, 1: TensorFlow, Default - 0 modelType = 0 # 0: Fixed quantization By tarininng Framework, 1: Dyanamic quantization by TIDL, Default - 1 quantizationStyle = 1 # quantRoundAdd/100 will be added while rounding to integer, Default - 50 quantRoundAdd = 25 numParamBits = 8 # 0 : 8bit Unsigned, 1 : 8bit Signed Default - 1 inElementType = 0 inputNetFile = "..\..\test\testvecs\config\caffe_modesl\ssd480x192\sparse\deploy.prototxt inputParamsFile = "..\..\test\testvecs\config\caffe_modesl\ssd480x192\sparse\ssd480x192_sparse_iter_100000.caffemodel" outputNetFile = "..\..\test\testvecs\config\tidl_models\tidl_net_jdetNet_480x192_ssd.bin" outputParamsFile = "..\..\test\testvecs\config\tidl_models\tidl_param_jdetNet_480x192_ssd.bin" rawSampleInData = 1 preProcType = 4 sampleInData = "..\..\test\testvecs\input\trace_480x192.y" tidlStatsTool = "..\quantStatsTool\eve_test_dl_algo.out.exe" layersGroupId = 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 2 2 2 2 2 0 conv2dKernelType = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 #conv2dKernelType = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Regards

Hi Lee, Can you please share the caffe model and prototxt to replicate the issue at our end? Thanks, Praveen

Hi: there is my caffe model and prototxt.My model only detect 1 calss:car. models&prototxt.7z Looking forward to your reply. Regards

Hi, Can you please also share the input image that you used to replicate the issue quickly? Thanks, Praveen

Hi: there is some images from my test video;I test part of them:In most of images ,the object could be detected with quantStatusTool,but couldn't be on on TDA2EXEVM with TIDL_OD.for example,the image "cqh20.jpg". test imgs.7z

Hi, Thanks for sharing the input. I could replicate the issue. I will debug and send you the fix. Thanks, Praveen

Hi Lee, Did you run single image (or frame) on TIDL use case and comparing the output with import tool output and detentions are not matching ? or If you running a video and output (some dectections) are not matching with import tool detentions, then this is expected as there could be some issue with quantization and this output will come to stable after some time. Please refer to section 3.8 Matching TIDL inference result in the user guide on how to set the quantization parameters for a video sequence. Thanks, Praveen

Hi: I run a video;and I tryed the "quantHistoryParam1"、"quantHistoryParam2" and "quantMargin" with several different values,like "quantHistoryParam1 = 20(or 0,10); quantHistoryParam2 = 10(or 0,5) ; quantMargin = 20(or 0,10)" But result is stille same:in some frame of input video,the "1" object can't be detected. What value shoule I set for the the "quantHistoryParam1"、"quantHistoryParam2" and "quantMargin"? there is a clip of my test video data and header: data&header.7z Regards

Hi Lee, To debug this issue, first we need to replicate it on the single image instead of video. Could please first run the input image (used to import the models) on the EVM using standalone and check the issue is observed on not? Please refer to section 3.3.5 in the user guide to run on the standalone. Thanks, Praveen

sorry I don't have a "USB Emulator";I only can work as "Load using SD card".

Hi Lee, Okay, I will try to replicate the issue in VSDK at our end and will let you know. Thanks, Praveen

Hi Lee, There is no problem in the code for this issue. This issue may be because of quantization , for this kind of issues, use first frame of the video for quant stats collection in the import and then use those for inference, first frame detection's will match exactly and will take some time for the rest of the frames for quantization to stabilise. Thanks, Praveen

Hi: Thanks very much. But then what could I do to resolve this object detection lost problem? Regards

Hi, Did you try matching the first frame that you imported? I would recommend you to try our training model shared on github , the link is below.. github.com/.../JDetNet Thanks, Praveen

Ticket Name: Compiler/TDA2: Open the Demo project onto CCS

Part Number: TDA2 Tool/software: TI C/C++ Compiler Dear TI Can you advise how can i open the demo project file which is generated by you onto the CCS IDE platform

Hello, Which demo project are you looking at? If it's a binary, you can create a target configuration, connect to a core and load the binary to run it on. thanks Alex

Hi Alex I sorry to say still dont understand your reply as i am new in this SOC area. Could you explain further. As for which demo project, there is no specify i am trying to link the function together to understand the codes. So i have where to modify on the codes to develop my own project.

Ok, are you going to be using the Vision SDK? Can you try some Vision SDK demos? You can download it from here www.ti.com/.../PROCESSOR-SDK-TDAX, after you install it there are gettings started gides in vision_sdk\docs\UserGuides. Perhaps it will help you boost your understanding of the code and demos. Please try it and let us know. Thanks, Alex

Hello Willson Toh , We have not heard back from you on this one. I assume you were able to move ahead. Please let us know if otherwise. The thread would be closed automatically if there is no reply. Thanks, Alex

Dear Alex We would like to know which is the 1st file that TDA2 execute upon power up as we are trying to remove some of the un-used component for our project to make the board smaller.

Willson Toh59 said: We would like to know which is the 1st file that TDA2 execute upon power up I am not sure about that, we will bring in more experts for help on this. They will comment here directly soon. thanks Alex

Hi Wilson, As such there is no file that is executed. When the TDA device is powered up first code that is executed is RBL. RBL (present on SoC itself) will initialize the device depending on the SYSBOOT. RBL will then load the SBL depending on boot mode. In case you load using CCS and there are gel files in the target configuration then gel files will initialize SoC. Regards, Rishabh

Dear Rishabh I would like to know how should we go about which components we are able to remove to implement for our project development.

Hi Wilson, It is not very clear to me what you want to do. You can remove all SW components except RBL. If you set the SYSBOOT to one of the reserved boot modes, SBL won't be loaded. Please see Initialization chapter from the TRM. Regards, Rishabh

Dear Rishabh, My colleague is now working on a new hardware based on TDA2x evaluation kit design. You mentioned that RBL (present on SoC) will initialize the device depending on the SYSBOOT. For proper boot up of our new hardware, do we need to do any programming on this SoC? Can we safely assume that this part of first code for SoC is already programmed by TI when we purchase the SoC component from TI?

Hi, RBL is already present inside the SoC. Can you please read chapter Initialization from the TRM. Regards, Rishabh

Dear Rishabh, Where to find the initialization chapter from the TRM?

Hi, It is chapter 29 from TDA2 TRM. Regards, Rishabh

noted. thanks

Hi, Kindly mark the post that answers your query as "This resolved my issue" and close the thread. Regards, Rishabh

Ticket Name: Linux/TDA2: diffrent of vision_sdk\apps\src\rtos\alg_plugins and vision_sdk\apps\src\hlos\adas\src\alg_plugins

Part Number: TDA2 Tool/software: Linux in vision_sdk\apps\src\rtos\alg_plugins have so many link but vision_sdk\apps\src\hlos\adas\src\alg_plugins poor ,so how can i move vision_sdk\apps\src\rtos\alg_plugins link to vision_sdk\apps\src\hlos\adas\src\alg_plugins ?

Hi Why do you want to do this? Are you looking for any specific Alg plug-in? Many of the Algorithms can only work on DSP or EVE, moving those to A15 doesn't make any sense regards, Shiju

Hi Shiju i have run null_src_decode_display in vision_sdk\apps\src\hlos\adas\src\usecases successful ， in this case have 6 links UInt32 NullSourceLinkID; UInt32 IPCOut_A15_0_IPU1_0_0LinkID; UInt32 IPCIn_IPU1_0_A15_0_0LinkID; UInt32 DecodeLinkID; where is this link code ?? UInt32 VPELinkID; where is this link code ?? UInt32 DisplayLinkID; where is this link code ?? i have not found in hlos , and in vision_sdk\links_fw\src\rtos\links_ipu\iva\iva_dec have DecodeLink . but i donot know links Under the RTOS directory should be use by hlos . SO i try to add some print inf in decLink_h264.c , when i run null_src_decode_display the inf i add in decLink_h264.c doesnot out. where is DecodeLink?? BESTWISHES SHUAI

Hi Shuai, Not all links will be on A15 , Links will be on different cores depending on hardware and drivers access . Please have a look at the jpg image in the usecase folder to get a better idea as which link is on which core. IPC links help in transfer of frame buffer pointers from one core to another The usecase you have mentioned has the following img which shows the details regards Chetan.M

Hi : Chetan.M I have read the image , i donnot know where is the souce code of decode link ! BEST WISHES SHUAI

Hi Shuai, vision_sdk\links_fw\src\rtos\links_ipu\iva\iva_dec The decode and encode links use IVA hardware Hence its under iva folder of links_ipu Regards Chetan.M

Hi Chetan.M vision_sdk\links_fw\src\rtos\links_ipu\iva\iva_dec this is in RTOS also can be used by hlos? BESTWISHIS SHUAI

SHUAI yes, you can use the IVA (enc/dec) links from HLOS also, please refer the below HLOS UC \vision_sdk\apps\src\hlos\adas\src\usecases\vip_single_cam_enc_dec_sgx_display regards, Shiju

Hi Shiju should i use links ( vision_sdk\apps\src\rtos\alg_plugins ) in HOLS ?? BESTWISHES shuai

SHUAI Yes, many of this Alg links can be used from a A15 Usecases as well. In all cases, These Alg links will be running on native DSP or EVE cores, but the same can be created and controlled from a usecase on A15 Linux. regards, Shiju

Ticket Name: RTOS/TDA2: Does dmaSwMs link supports resizing and then display frame?

Part Number: TDA2 Tool/software: TI-RTOS Hello, I want display two different frames at a time using dmaswms link. I observed that, dmaswms link crops the frame as per given parameter and then displays cropped frame. But I want to display a resized frame. So, does dmaSwMs link supports resizing and then display frame? Currently parameters are set as, Alg_swmsPrmObj->maxOutBufWidth = 1920; Alg_swmsPrmObj->maxOutBufHeight = 1080; Alg_swmsPrmObj->numOutBuf = 5; Alg_swmsPrmObj->useLocalEdma = FALSE; Alg_swmsPrmObj->initLayoutParams.numWin = 1; Alg_swmsPrmObj->initLayoutParams.outBufHeight = 1920; Alg_swmsPrmObj->initLayoutParams.outBufWidth = 1080; Alg_swmsPrmObj->initLayoutParams.winInfo[0].chId = 0; Alg_swmsPrmObj->initLayoutParams.winInfo[0].height = 500; Alg_swmsPrmObj->initLayoutParams.winInfo[0].width = 500; Alg_swmsPrmObj->initLayoutParams.winInfo[0].inStartX = 0; Alg_swmsPrmObj->initLayoutParams.winInfo[0].inStartY = 0; Alg_swmsPrmObj->initLayoutParams.winInfo[0].outStartX =100; Alg_swmsPrmObj->initLayoutParams.winInfo[0].outStartY =100; Regards, Kajal

Hi Kajal, You can resize using the display link and then use that as a input for SwMs. Which use case are you trying to run? You can see <vision_sdk>\apps\src\rtos\usecases\lvds_vip_multi_cam_view_tda3xx\chains_lvdsVipMultiCam_Display_tda3xx.c as an example. Regards, Rishabh

Hello Rishab, As per my knowledge, vpe link do resizing. How to do resizing with display link? Also dmaswms link requires input as composite buffer. Regards, Kajal

Hi Kajal, Both VPE and DSS can do the scaling. In display link you need to set a different tarWidth and tarHeight for scaling. Regards, Rishabh

Hello Rishabh, You : You can resize using the display link and then use that as a input for SwMs. >>1. What about dmaSwMs link, because it requires composite buffer as input. 2. Display cannot outputs any buffer, the how come output of display link will goto dmaSwMs link? Also suggested use case by you ( <vision_sdk>\apps\src\rtos\usecases\lvds_vip_multi_cam_view_tda3xx\chains_lvdsVipMultiCam_Display_tda3xx.c) doesn't have scenario where resized output by display is given to dmaSwMs link. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// You: In display link you need to set a different tarWidth and tarHeight for scaling. >>Setting tarHeight and tarWidth parameters of display link doesn't give me resized frame. Regards, Kajal

Hi Kajal, I meant DSS M2M WB link. Can you try to set different output width & height? One example is setting pPrm->chParams[chId].outParams[0].width in PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\apps\src\rtos\usecases\lvds_vip_multi_cam_view\chains_lvdsVipMultiCam_Display.c Regards, Rishabh

Hello Rishabh, One example is setting pPrm->chParams[chId].outParams[0].width in PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\apps\src\rtos\usecases\lvds_vip_multi_cam_view\chains_lvdsVipMultiCam_Display.c >>This parameter is set for vpe link. I am working for single channel camera. First using VPE link we need to resize frame and then give it to swms link and then display link . This flow works for me. Thank you for your suggestions! Regards, Kajal

Hi Kajal, Glad that your issue is resolved. Please mark the posts that help you to resolve the issue as "This resolved my issue". Regards, Rishabh

Ticket Name: Linux/TDA2: about vcop_sobel_xy

Part Number: TDA2 Tool/software: Linux Hi : in vcop_sobel_xy vcop_sobel_xy_tb.c have compared vcop_sobelXY_3x3_separable_uchar and vcop_sobelXY_3x3_separable_uchar_cn src of vcop_sobelXY_3x3_separable_uchar is a vector function (src_kernelC/vcop_sobel_xy_kernel.k) i canot finde the source code of vcop_sobelXY_3x3_separable_uchar_cn

Hi Shuai, The natural C code is released only in library form. For natural C source code you will need to get full source release of EVE SW. Regards, Anshu

Ticket Name: TDA2E: TDA2x Lane detection algorithm

Part Number: TDA2E 1.We call the API lane detect to draw the lane.The draw lane seems doesn't coincide with the actual lane but cross. So Is that a question of algorithm itself or icalling parameters? How to fix it? 2.And we found Lane detection algorithe call the api AlgIvision,but we can't see this api's defination. So is there any references about it?Can it be modified? Thanks!

Hi, Can you please add details on which SDK you are using? Regards, Karan

Hi Our VSDK version is 3.06 and Lane detection version is 00.02.03.00.

Hi, The algorithm source code is not available in the vision-SDK & we used the library. The line detection demo use-case is already available in the vision SDK, so why don't you make use of it instead of creating your own use-case? use-case path: vision_sdk/apps/src/rtos/usecases/vip_single_cam_lane_detection Thanks Gaviraju

Ticket Name: Linux/TDA2: EVE: I have written a kernel file, Is there a tool to generate the driver C file?

Part Number: TDA2 Tool/software: Linux EVE: If I have written a kernel function(void kernel_func_name(full_argument_list)), Is there a tool to generate these functions: 1、kernel_func_name_init(full_argument_list, unsigned short* pblock); 2、kernel_func_name_vloops(pblock); 3、kernel_func_name_param_count();

Hi, These functions will get generated when you compile the .k file with -kh and -kv option. Regards, Anshu

Ticket Name: TDA2: ABB mode

Hi sir, Could you pls explain the ABB feature of LDO in detail? Tks so much BR jason_Koo

Please provide complete details - what device are you asking about?

it is TDA2x， picture as attachment.

Hi jason_Koo, can you check if you can find what you look for in "ADAS Power Management" application note: www.ti.com.cn/.../sprac22.pdf and also this training: training.ti.com/introduction-adas-power-management-software Regards, Yordan

Hi Yordan， Thank you for help! BR Jason Koo

Ticket Name: TDA2EVM5777: I2C2 & HDMI I2C in EVM

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello Why HDMI I2C & I2C2's SDL & SDA are swap in TDA2? There is a RU108 to uncross the I2C2 & HDMI I2C in EVM. Could I use I2C2 to read hdmi I2C directly? thank you

Hi user3829173, This swap is in TDA2Ex and rev e version of EVM provides a option swap these lines. To use I2C2 to read the EDID, you would require to perform board modification to swap these lines. Please ensure the swap is applicable for HDMI only. Regards, Sujith

Hello Sujith Our design is connecting I2C2 to image sensor & HDMI i2c, we use I2C2 to read both image sensor & EDID　 is it working? thank you

Hi user3829173, If the electrical characteristics are aligned then it should work. Regards, Sujith

Hi Sujith There is a level shift between SoC & HDMI connector, so it shout work. Thank you

Thanks user3829173, Regards, Sujith

Ticket Name: Linux/TDA2: DDR DQ signal swapping TDA2SX

Part Number: TDA2 Tool/software: Linux Hello, We are working on a custom board based on TDA2SX. We did some swapping in DQs with in the same bytes (DDR1_D0-> DQ0, D1->DQ5, D2->DQ1 ....D8->DQ8,.....). We hope this swapping is fine. Could you please confirm this with relevant software changes. Thanks Akesh

There is no issue with swapping data bits (within a byte) when interfacing TDA2SX with either DDR2 or DDR3. No software changes are required.

Ticket Name: RTOS/TDA2: remain size of SD card

Part Number: TDA2 Tool/software: TI-RTOS Hi, how can I get the remain size of SD card? Thanks!

Hi, We dont have such support on target running with BIOS. You need to connect the sd card to pc and get it. Regards, Anuj

Ticket Name: TDA2: Enquiry on TI device translator tool and other question

Part Number: TDA2 Dear TI Below are some of my question. Q1) We are try to using some of the third party software like caffe and tensorflow. I had read one of your document "Embedded low-power deep learning with TIDL" there is tool call TI device translator tool where can i find these tools? Q2) On top do we are try to bring Dlib and RPPG to the TDA2 are we able to accomplish using the TIDL deceive translator tool? Q3) Where can i find this TIDL deceive translator tool user guide? Q4) What is the latest version use in VisionSDK for opencv and are we to upgrade the opencv to the lastest version which is 3.3.1 ?

Hi, 1) This tool is name is "tidlModelImport" and is part of TIDL component in VSDK release and you can find this in "ti_dl\utils" folder in TIDL 2) Please refer to "TIDeepLearningLibrary_DataSheet.pdf" for supported layers with this tool and with TIDL library. Note that this tool source code is also available in the package so that it can be extended as per your requirements. 3) For this, refer to section 3.6 in the "TIDeepLearningLibrary_UserGuide.pdf". 4) Refer to user guide in latest Vision SDK release( www.ti.com/.../PROCESSOR-SDK-TDAX) Thanks, Praveen

Dear Praveen The link for answer 4 is unable to be found please advise

I think it is adding extra closing brace at the end, so not opening, try this.. www.ti.com/.../PROCESSOR-SDK-TDAX Thanks, Praveen

Dear Praveen As for the reply for question 2 you mean that i am able to import DLib and rppg to this TDA2 ?

Hi, I don't know the network layers structure used in Dlib and rppg, so as long as any network which has the layers supported by tool (mentioned in the user guide), then our tool can import those networks. More ever source code is open to user, so any one can add any missing layers for this tool to import their own models. Thanks, Praveen

Ticket Name: about the omap x5777

Other Parts Discussed in Thread: TDA2 Hi, I have a VAYU EVM XC5777C CPU BOARD, however I can't find the reference documents about the omap x5777 on 'www.ti.com' online. Could you give some help, Thanks.

Hi, This is TDA2xx EVM. You can see the documents on TDA2 here: www.ti.com/.../tda2. Regards, Rishabh

Dear Rishab, Thanks for your reply, it resolve my question. Thanks a lot. Regards, Tianxing

Ticket Name: Compiler/TDA2: TIDL: I have TIDL library, undefined symbol assembly function of arp32

Part Number: TDA2 Tool/software: TI C/C++ Compiler I have TIDL library built successfully and works fine with the test application. When I include it with my own project the Library throws the following errors. undefined first referenced symbol in file --------- ---------------- __arp32abi_addf D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_conv2d_base.obj> __arp32abi_cmpf D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_concat.obj> __arp32abi_cvtdf D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_concat.obj> __arp32abi_cvtfd D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_concat.obj> __arp32abi_divf D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_conv2d_base.obj> __arp32abi_fixfi D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_concat.obj> __arp32abi_fixfu D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_conv2d_base.obj> __arp32abi_fltif D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_concat.obj> __arp32abi_fltuf D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_conv2d_base.obj> __arp32abi_mpyf D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_concat.obj> __arp32abi_strasgi D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_alg.obj> __arp32abi_subf D:\LIQOR\PCA_Latest\04_Engineering\02_Development_Tools\ti_tools\compiler\arp32\lib\tidl_algo.lib<tidl_conv2d_base.obj> These look like assembly functions that come with TI compiler. I used the same Arp32 compiler for both TIDL and my project. What could be the issue.

Looks like RTS library from ARP32 compiler folder is not included in your project linking. Include RTS library to your project

I have included.

I think I got the issue. I use scons to build my project, In Scons the libraries have to passed in series w.r.t their dependencies. Thanx for the support

Ticket Name: RTOS/TDA2EVM5777:

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hello, For the RTOS PCIE RC to RTOS PCIE EP example developed for the AM5728 IDK, can I use this example for the TDA2EVM5777. If so, what do I need to change? Thanks, -iFer

Hi, Yes you can use this example. Maybe some basic porting will be needed. You might need to change lane configuration if number of lanes is different on two boards, pin mux changes. Regards, Rishabh

Hello Rishabh, thank you for the reply. Using CCS, I imported the TI RTOS project "PCIE_idkAM572x_wSoCFile_armExampleProject" of the PCIE example found here: C:\ti\pdk_am57xx_1_0_10\packages\ti\drv\pcie\example\sample\am572x I built the project successfully. I have a known working CCS/Target Config File setup with the TDA2x EVM5777 board, so without changing any pinmux or porting variables, I loaded the default project onto the TDA2 using JTAG. When loading the project .out file through JTAG onto the TDA2x EVM5777 board, I get an exception shortly after hitting play. I am noticing that the exception is happening when the function Task_create() is ran. Once the exception gets thrown, I see in the console window "CortexA15_0: Unhandled ADP_Stopped exception 0x20023". This should just be a BIOS configuration, correct? If I place a breakpoint on any line after Task_create() it never gets called. Any suggestions for determining what in Task_create would cause the exception? With respect to porting between EVMs, I looked at the current configurations in the idkAM572x CIE_idkAM572x_wSoCFile_armExampleProject and the registers being accessed on the AM572x look to be the same on the TDA2. The only address that seems odd is 0x48447000 which is for VCP1_CFG_TARG. That address is defined as a peripheral base in the idkAM572x example but the TDA2 has that address under Reserved space. The AM572x TRM though has a note saying that VCP is not supported in this family of devices so is it just defined and not used? For the number of PCIE lanes, the base example looks to be doing only 1 lane so that shouldn't be a problem with TDA2. Is that correct?

Hi, TDA2xx EVM has single lane and hence it should not be a problem. I would suggest you to first download Processor SDK Vision release for TDAx devices from www.ti.com/.../PROCESSOR-SDK-TDAX This release has a makefile based PCIE RC to EP example in PROCESSOR_SDK_VISION_03_03_00_00\ti_components\drivers\pdk_01_09_00_17\packages\ti\csl\example\pcie\write_loopback. You can look at build instructions here: processors.wiki.ti.com/.../PDK_TDA_Software_Developer_Guide I made a wrong assumption with the previous reply that you are using CSL example. PCIe RTOS driver has not been validated on TDA2x device. In order to get the PCIe RTOS example from AM57xx to TDA2xx you will need to port the driver which will be an involved effort. Regards, Rishabh

Ticket Name: CCS/BEAGLE-3P-BBONE-AI: what is the recommended GEL file to attach BBB AI board?

Part Number: BEAGLE-3P-BBONE-AI Other Parts Discussed in Thread: TDA2, AM5729 Tool/software: Code Composer Studio Dear Champs, My customer is trying to connect BBB Ai board using CCS, and what is the recommended GEL file to attach BBB Ai board using CCS? Could you please share the GEL file for BBB Ai board? Thanks and Best Regards, SI.

Sung-IL, There is not a specific GEL bundled with the TI tools for the BB-AI a this time, but you can use much of the AM572x GEL files that are bundled with Code Composer Studio. Start with the gpevm_am572x, which will load the common AM572x gel files. Best regards, Dave

Hi Dave, Is it possible to use TDA2 processor in this case? My customer succeed to connect Beaglebone AI using AM572x gel file and by reducing memory size to 1GB. When my customer tried to add AM5729, they found there was no EVE core in the processor, and want to connect EVE core when debugging issue was occurred. So, I would like to check if TDA2 processor can be used to connect Beagleboard AI. Thanks and Best Regards, SI.

SI, Yes, you should be able to load the TDA2 gel. Best regards, Dave

Ticket Name: [FAQ] TDA4VM: Linux DTS DTB FAQs

Part Number: TDA4VM I have the following questions: How to know which driver is probed with a particular Device tree node? How to know which CONFIG to be enabled to probe a particular Device tree node? How to get the DTS(device tree source) of a particular DTB(device tree binary)?

Answers to questions in the order: How to know which driver is probed with a particular Device tree node? They key lies in the compatible string. For example ospi0 node:  ospi0: spi@47040000 {
                        compatible = "ti,j721e-ospi", "ti,am654-ospi";
                        reg = <0x0 0x47040000 0x0 0x100>,
                                <0x5 0x00000000 0x1 0x0000000>;
                        interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
                        cdns,fifo-depth = <256>;
 Search for compatible strings under drivers folder of Linux repository starting from first to last in order. Continuing with our ospi0 example: git grep ti,j721e-ospi drivers/
 No matches found so search for the next compatible. git grep ti,am654-ospi drivers/ drivers/mtd/spi-nor/cadence-quadspi.c: .compatible = "ti,am654-ospi", Ospi0 probes the drivers/mtd/spi-nor/cadence-quadspi.c driver. How to know which CONFIG to be enabled to probe a particular Device tree node? Follow the steps for Q1 and once you know the driver name. Continuing with our ospi0 example. Couple of more steps to get to the CONFIG option: Driver: drivers/mtd/spi-nor/cadence-quadspi.c driver. Open the Makefile in the folder that has the driver. vi drivers/mtd/spi-nor/Makefile
 Search for cadence-quadspi.o (Driver name with object extension) obj-$(CONFIG_SPI_CADENCE_QUADSPI)       += cadence-quadspi.o CONFIG_SPI_CADENCE_QUADSPI option corresponds to ospi0 node. How to get the DTS(device tree source) of a particular DTB(device tree binary)? cd to the Linux repo. Example: Source for k3-am654-r5-base-board.dtb. scripts/dtc/dtc -I dtb -O dts  -o devicetree.dts arch/arm/dts/k3-am654-r5-base-board.dtb The source will be saved as devicetree.dts Regards, Keerthy

Ticket Name: Linux: Do we have support of HDMI on "Linux+ Bios" with TDA2XX SOC?.

Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hi There, I am using "VSDK_03_01_00_00" version of "VSDK" with TDA2XX SOC and able to build "VSDK" successfully for "Linux + Bios" platform . After that I have tried to execute below mentioned use case. "NullSrc + Decode + Display". For executing this use case I have followed below mentioned steps. 1. I did some configuration for Display and Capture by using "Setting" option(S) (Here I have selected "HDMI 1080P60 for Capture" and "HDMI 1080P60 for Display"). 2. Ran the "NullSrc + Decode + Display" use case and used the "H.264 " codec. 3. During the execution of use case I got "ASSERT (nullSrcLink_tsk.c|NullSrcLink_fillData|202)" on the console. I read somewhere that "Linux+ Bios" doesn't have HDMI" support and I am not sure is this the case with Linux build. Could someone please give clarification on this?. Regards, Anshul Jain.

Hi Anshul, the Linux version of VisionSDK supports HDMI (also in ver 3.01 was added support for LCD). Your problem looks more like issue with reading the input file. I have pinged VisonSDK experts to help. Regards, Yordan

Yes, Yordan is correct. VSDK_03_01_00_00 support HDMI display for both "Bios only" and "Linux + Bios" builds. HDMI capture is not supported in VSDK Linux+Bios, and this feature is available only with Bios only version regards, Shiju

Hi Shiju, Thank you for your response. As you have confirmed that HDMI capture is not supported in VSDK Linux+Bios. So in the same environment, can we have a input from "AVB" port and see the output on HDMI display. Regards, Anshul Jain.

Anshual Yes, AVB capture and HDMI display is supported on VSDK Linux+Bios. please refer Linux user guide to build binaries and set-up for AVB regards, Shiju

Hi Shiju, Thanks for the inputs. Regards, Anshul Jain.

Hi Shiju, wanted to check, if HDMI supported on "TDA3x " and "TDA2+" soc with Linux+Bios config on VSDK_03_01_00_00? Thanks, Mohammed

Hi No HDMI capture is not supported with vision SDK Linux (Linux+Bios) on any TDAxx. HDMI caprure is supported on TDA3x and TDA2x with VSDK Bios only cnfig. This is available with VSDK_03_01_00_00. for TDA2+, HDMI capture will be supported in next VSDK release version VSDK_03_02_00_00 regards, Shiju

Thanks Shiju, it helps. regards, Mohammed

Ticket Name: RTOS/TDA2PXEVM: RTOS/TDA2PXEVM: Support for multiple NetworkRx link instances

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hi We are working on TDA2PX based Hw and vision SDK version is SDK_03_03_00_00 .Here , when we try to initiate two NetworkRx link in usecase for testing we want to send the image in one port and sensor data in another port, second NetworkRx link fails during the link creation time as below mentioned debug logs (attachment): … [HOST ]     15.723144 s: NSP GMAC: PHY 2 Found on MAC Port 0 [HOST ]     17.523851 s: NDK: Link Status: 10Mb/s Full Duplex on PHY 2 [HOST ]     17.723388 s: NDK: Link Status: No Link on PHY 2 [HOST ]     18.328951 s: NETWORK_CTRL: Starting Server (port=5000) !!! [HOST ]     18.328981 s: NETWORK_CTRL: Starting Server ... DONE (port=5000) !!! [HOST ]     21.123589 s: NDK: Link Status: 1000Mb/s Full Duplex on PHY 2 … [HOST ] 33.475660 s: NETWORK_TX: NETWORK_TX: Server listening (port=29172) !!! [HOST ] 33.475873 s: SYSTEM: ERROR: No link registered at link ID [68] !!! When we further debug the code then find that, we can have maximum one NetworkRx link objects as per below mentioned sdk source code vision/platform/ti/tda2/links_fw/include/links_fw/include/link_api/networkRxLink.h #define NETWORK_RX_LINK_OBJ_MAX (1U) Can we support for multiple NetworkRx link instances in existing code base ? what are all the changes needs to be done to enable this, Is there any specific patches required for this feature. Can you please support on this ? Regards, Raj

Ti Raj Dual Ethernet port support was not available in VSDK 3.3 release. This is only supported with latest VSDK 3.6 (released on early Jan) please refer this link to download the same - www.ti.com/.../processor-sdk-tdax Mainly NSP package updated to support Dual Mac. VSDK also has some configuration changes and sample UC to support Dual Mac. you either move to VSDK 3.6 release or use the latest NSP package from 3.6. BTW, are you using both ports with static IP or dynamic IP config? we have an open issue for setting one port as static and other as dynamic IP. But both Static or both dynamic is functional. Regards, Shiju

Ticket Name: TDA2: Is the external clock module needed for the AVB audio to sync with local audio clocks?

Part Number: TDA2 Hi, expert: To implement AVB on J6/J6P, in case both talker and listener are needed, do we need an external clock module for the AVB audio to sync with local audio clocks? If needed, is there a reference schematic? Thanks.

Hi Peter, can you check if this thread can help you: e2e.ti.com/.../2691094 Regards, Yordan

Hi Peter, I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Ticket Name: TDA2: how to integrate vision SDK to autonomous drive application

Part Number: TDA2 Hi, I have read the chain and link mechanism. And also run sample_app successfully, go through most of documents of TI vison SDK, but still struggling. My question is how to integrate my autonomous drive application to TI Vision SDK? i have sensor fusion , decision and planning modules, etc. Based on my understanding to sdk, i should put each module as a algorithm module ,integrate with a algorithm link. Maybe also develop some common link to receive and send data as interface with peripherals. Am i right? does TI have any general document to guide users in high level how to integrate TI vision SDK, not fall down in details at the beginning. Thank you in advance. Best regards HUI

Hi HUI, did you checked the documents in "vision_sdk\docs\Architecture", there you can find higher level overview of VsiionSDK's architecture. Regards, Yordan

Ticket Name: RTOS/TDA2: TDA2X Booting process

Part Number: TDA2 Tool/software: TI-RTOS Dear All, We are using EVM and RVP board for Objection detection and data logger project. Due to required customization, need to understand the booting processing of TDA2X. We did not find the document which can provide the booting flow procedure, we attempted to analyze the source code. Considering the DSP1 core got the flow as: vision_sdk/sample_app/src/common/main_app/tda2xx/dsp1/src/main_c6xdsp1.c 91 /** 92 ******************************************************************************* 93 * 94 * \brief This is the main() implementation of DSP1. 95 * 96 * This is the first function and entry point to DSP1, does 97 * - Set the correct/required CPU frequency 98 * - Call the System_start with C6XDSP_main() and loops there 99 * 100 * \return SYSTEM_LINK_STATUS_SOK 101 * 102 ******************************************************************************* 103 */ 104 Int32 main(void) 105 { 106 Uint32 status; 107 108 status = main_common(); 109 110 return (status); 111 } This in turn calls main_common_c6xdsp1.c, i.e. vision_sdk/links_fw/src/rtos/bios_app_common/tda2xx/dsp1/src/main_common_c6xdsp1.c 167 Int32 main_common(void) 168 { 169 /* This is for debug purpose- see the description of function header */ 170 StartupEmulatorWaitFxn(); . . . //code truncated 207 System_start(C6XDSP_main); 208 BIOS_start(); // Q1: Where is the defination of BIOS_start() function? 209 210 return (SYSTEM_LINK_STATUS_SOK); 211 } Q2. Document or guide on the booting process of DSP or EVE to the point where application is started. Thanks, KK

Hi, Please find your answers below Q1: Where is the defination of BIOS_start() function? This function will start the TI-RTOS and do the necessary initializationfor DSP core. Q2. Document or guide on the booting process of DSP or EVE to the point where application is started. There is no such document which explains about the details of all files. you can start with Chains_main() function available in vision_sdk\apps\src\rtos\common\chains_main_bios_vision.c for bios_all config. And main() available in vision_sdk\apps\src\hlos\adas\src\common\chains_main.c file for linux all config. These are the files from where the usecases starts. Regards, Anuj

Hello Anuj, Q1. Could you guide us to the source code? Q2. The source path and the description are helpful. We will go through it and get back. Thanks, KK

Hi, These are c codes and that you need to go through yourself. If you face any issue in running any usecase or in order to modify that usecase , you can post a new question. Regards, Anuj

Hello Anuj, We will go through the C code, we have expertise on it. Q1. Was referring to " BIOS_start() function definition. We could not find it. Could you guide us to the file containing the function BIOS_start() definition?. Regards, KK

Hi, BIOS_start() is a library function. Please go through the below docs to understand the VSDK framework VisionSDK_SW_Architecture_Overview.pdf VisionSDK_SW_Architecture_Details.pdf VisionSDK_DevelopmentGuide.pdf Regards, Anuj

Ticket Name: Linux: The performance of TIDL OD usecase are different when using different input video.

Tool/software: Linux Hi, I'm testing TIDL OD usecase in linux. The format of chain is same with TIDL OD in BIOS except for TIDL Preprocessing. (It is running on DSP) The problem is the performance of that converted usecase is different each time when i use another video. The below video is normal case. And this is abnormal case. The usecase is running but all frames are dropped after showing some initial frames. And this is normal case that uses same video with upper case. I don't know why the results are different even though the input video was same. Could you suggest any cause of this problem or solution? Thanks & Regards, Yoo

Hi, Can you try to run preproc link on ipu and check. And lower the FPS also. Regards, Anuj

Hi, Actually, we already tried on IPU. (in Vision SDK 3.6ver). However, the FPS was too low (about 1.2FPS in display link). We would try to that using Vision SDK 3.7ver and will update the result in this thread. If you have any other solution or reason of this problem, please tell me. BTW, there is frame reversing problem, is that caused by Sync link? Thanks & Regards, Yoo

Hi, I tried to run preproc link on IPU in Vision_sdk 3.7ver. The boxes are drawed normally but FPS was 1~2FPS. When i run preproc link on DSP (also Vision_sdk 3.7ver), At least once every 10 times, the result is as strange as the video above. Could you please suggest any reason or solution about this prob? Thanks & Regards, Yoo

Hi, So when you use preproc link on IPU then it works fine but on DSP its not working. Have you tried the same running on DSP with lower FPS. It will be better if you can share logs. Regards, Anuj

Hi, Its been long since any update on this thread. I hope the issue is resolved. If not then please reply below or create anew thread for different query. Regards, Anuj

Ticket Name: TDA2: tidl_src convolution layer input data tranfer

Part Number: TDA2 Hi, Now we use tidl for object detection, but i don't understand the convolution layer input data tranfer. In TIDL_conv2dDmaSrcInit() function, there are both scatthergather and autoincrement dma utils as follow: in TIDL_conv2dDmaSrcAutoIncrementInit() function, what the parameter 'roiWith' 'roiHeight' 'exeMemPtr' point to, i debug the code, but i still not konw what the extMemPtr point to thanks

Hi, Yes, the convolution layer input data transfers require both Auto Increment and scatter gather as per our design and this is not correct place to discuss more about these details as it is a public forum. BTW, what are changes you are planning to do in this convolution layer ? Thanks, Praveen

Hi, Now, we use ssd model to do object detecting. But the local latency in eve is about 180ms, I want to do some work to refine the convolution layer code, expecting to reduce the time. Can i use scattergather or autoincrement, one of them to do input data transfer? thanks.

Kumar, Please check if you are able to reply now. Regards Karthik

Convolution layers are fully optimized, we don't expect any further imporments.

Ticket Name: TDA2SG: Tidl in vsdk3.7 , how many network can I run in the tda2s.

Part Number: TDA2SG Hi, All experts: I want to run more than one networks in the tda2s,I can run ok like the demo run, but it only can run one network, how can I run more network and different networks in the tidl? Thanks!

Hi, We have maximum 4 EVEs, each of them can run separate/different networks, please refer to TIDL use cases in vision SDK. Thanks, Praveen

if I want to 1 eve can process 15-20 frames ,how can I do? Now I find it only can do 4-5 frames

Hi, You may have to update the below parameters in the "deploy.prototxt" file and re-import the model and check. keep_top_k: 20 confidence_threshold: 0.15 For more details pls refer to below e2e thread. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/689617/tda2-how-to-run-ssd-based-tidl-od-use-case-in-vision-sdk-with-pre-trained-model Thanks, Praveen

Hi，this setting can do 20 frames when usecase use 4eves,but I want only 1eve to process 15-20frams, Has 1 eve can satisfy?

No, one eve can't satisfy. Thanks, Praveen

Ticket Name: TDA4VM: GPU and asynchronous VX nodes processing

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi, When I was working with TDA2 SoCs in System Link API there was possibility to process buffers asynchronously. It heled to utilize better GPU without GPU-stalling calls like glFinish(). With old Vision SDK it was supported by default as GBM framework and PVR backend implementation hides from you handling of framebuffers with eglSwapBuffer() and you can just get the current buffer by the call gbm_surface_lock_front_buffer(). This call will give you access to recent ready framebuffer. (could be previous frame if GPU has high workload). In the latest PSDK for TDA4 there is no such functionality and in SRV test sample there is explicit glFinish() which affects PVR GPU performance (tiler and renderer works only sequentially without overlapping in pipeline for two subsequent output framebuffers). Are there any design guides or sample on how to implement similar asynchronous pipeline?

Hello Grigory, We are aware of the limitation and do intend to implement asynchronous processing to better utilize the GPU. As you guessed this will require some changes to the way GPU and OpenVX display nodes work. And this is because the display is being handled by R5F and not by A72. I presume your end goal is to have OpenVX based R5F display node support asynchronous buffer processing so that Tiler and Renderer can run in parallel. Or are you looking for A72 directly interacting with the display using Wayland/GBM. Regards Hemant

Hi Hemant, Thank you for the reply. Yes, the goal is to utilize TI OVX display node on R5F and have pipeline with parallel Tiler/Renderer parts (without explicit synchronization calls like glFinish()). We have one suggestion that it can be done by using GPU outside of TI VX node. At the level of control application (that maintains VX graph) we can use glFence()/glClientWaitSync() in separate threads and submit rendered output buffer to vxGraph with display node when it is ready. But I was wondering how can we do that by using only TI VX API. When do you think it could be avaialble as a part of PSDK? -- Grigory

Hello Grigory, Thank you very much for the suggestion. We will certainly look into this and try it out. We are also looking at VX API and how to handle this in the context of the API. Regarding the PSDK, we do not have a date that I can give you yet - but it is being looked into. I will update you as soon as this is integrated. If it is okay with you, can we close this E2E ticket with the action on us to work this out in the SDK context? Regards Hemant

Ticket Name: RTOS/TDA2EXEVM: bios pdk

Part Number: TDA2EXEVM Other Parts Discussed in Thread: SYSCONFIG Tool/software: TI-RTOS hello, i have a same issue in tda2ex, details below: after runing into system, i check the gpio2 reg CM_L4PER_GPIO2_CLKCTRL = 0x00020001 GPIO_SYSCONFIG = 0x1d after i reset gpio2 by set GPIO_SYSCONFIG = 0x1f the GPIO_SYSSTATUS can't Reset completed , the value is always 0x0 the question i want ask is that : why i can't reset gpio2 again but , when i set CM_L4PER_GPIO2_CLKCTRL [8] = 1, it reset ok. can you give me some help?

Hi, When CM_L4PER_GPIO2_CLKCTRL = 0x00020001, GPIO is in idle state. Hence you are not able to reset the GPIO. You need to make sure that GPIO2 is fully functional i.e. CM_L4PER_GPIO2_CLKCTRL =0x00000001. Regards, Rishabh

Ticket Name: CCS/TDA2: The controller has detected a dead JTAG clock

Part Number: TDA2 Tool/software: Code Composer Studio Hi i am using EVMx5777 board(TDA2x). but during debugging with emulator i found one error "The controller has detected a dead JTAG clock". i am using XDS560v2 STM emulator and CCS version 8.0. in the JTAG port i am using 60 PIN MIPI connector. please tell me how i can solve my this issue.

Hello, Can you try lowering the TCLK of your emulator? Try clocking down see if the error persists. If you are using adaptive clocking adapter try without it or setting the adaptive clocking setting in CCS as explained in this e2e: thanks, Alex

Ticket Name: Compiler/TDA2PXEVM: TDA2PX target reset due to over temperature with SDK3.06 OPP_PLUS mode

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi , In the latest 3.06 , we observed that , TD2px based HW reset due to linear increase in current and temperature when we execute below mentioned ADAS specific HM perception use case: UseCase: chains_hm_odld_adas NetworkRx_IMG (A15) -> Decode -> Dup_capture Dup_capture -> Merge_caputre Dup_capture -> Merge_caputre Merge_caputre -> VPE -> Dup_Imgs -> Select -> Alg_SvDraw (A15) -> Display_Result Dup_Imgs -> Alg_HMEve_0 (EVE1) Dup_Imgs -> Alg_HMEve_1 (EVE2) Alg_HMEve_0(EVE1) -> Alg_HModRcnnC66 (DSP1) -> Alg_HMAdasA15 (A15) Alg_HMEve_0(EVE1) -> Alg_HMldUpsampleC66 (DSP2) -> Alg_HMldPostA15 (A15) -> Alg_HMAdasA15 (A15) Alg_HMAdasA15 (A15) -> Dup_OD -> Alg_SvDraw (A15) Alg_HMAdasA15 (A15) -> Dup_LD -> Alg_SvDraw (A15) NetworkRx_CAN (A15) -> Dup_Can Dup_Can -> Alg_HMldPostA15 (A15) Dup_Can -> Alg_HMAdasA15 (A15) Dup_OD -> NetworkTx_Od(A15) Dup_LD -> NetworkTx_Ld(A15) GrpxSrc -> Display_Grpx SDK_VISION_03_06 software and HW configuration details : [IPU1-0] 15.317117 s: Vision SDK Version : [DEV_VISION_SDK_03_06_00_09] [IPU1-0] 15.317178 s: FVID2 Version : [FVID_02_01_00_01] [IPU1-0] 15.317269 s: BSP Version : [PDK_01_10_02_xx] [IPU1-0] 15.317330 s: Platform : [EVM] [IPU1-0] 15.317391 s: SOC : [TDA2PX] [IPU1-0] 15.317483 s: SOC Revision : [ES1.0] [IPU1-0] 15.317544 s: Board Detected : [TDA3XX BASE] [IPU1-0] 15.323705 s: Base Board Revision : [REV A] [IPU1-0] 15.323766 s: Daughter Card Revision: [REV A] DPLL CONFIG : OPP_PLUS DDR Config : DUAL_EMIF_2X1GB TDA2Px DDR Configuration Two EMIFs 1GB each (Total = 2GB) Here, The board has fan-less design . We are using MLO OPP Plus image with the DDR3 interleaved configuration as our library is designed on OPP_PLUS(EVE 0.9GHz, DSP 1GHz, A15 1.5GHz) and dual EMIF environment for meet to throughput. We didn’t touch anything related to temp and power management in our usecase. As per debug console logs analysis ,we find that, all DSP (at 60%) and EVE (at 90%) load. A15 and IPU are not utilized beyond 20-25% load. Note: We didn’t observe this issue with sdk3.03 release with same SW & HW configuration. Do we need to take care any specific configuration in TD2Px HW or software to prevent form over temperature issue for above usecase? Please let me know your inputs to resolve the above issue. Regards Raj

Raj Couple of things to check would be 1. Are you making sure you are setting AVS for the voltage rails correctly in your setup? 2. Are you setting CPU_IDLE_ENABLED=yes in your configuration file? Thanks and Regards Piyali

Hi Piyali, Thank you for comments. We didn't modified in AVS .Using default AVS setting for Opp_plus mode. This is provided by TI released SDK-3.6(SBL). I also crossed check about "CPU_IDLE_ENABLED=yes" flag in our SDK code base. It's already configured as below. source/vision/platform/ti/tda2/apps/configs/xxxx_proto_A_bios/cfg.mk:134:CPU_IDLE_ENABLED=yes Regards Raj

Raj OPP_PLUS support was added in the 3.6 release so there is a good chance where the 3.3 did not have OPP_PLUS frequency. Do you need OPP_PLUS for your compute requirement? Can you review if based on the compute requirement you can reduce the OPP to HIGH or OD in your usecase? Also can you review if all the rails need OPP_PLUS or only few rails need OPP_PLUS? Also, is this being run on EVM or your own custom board? Thanks and Regards Piyali

Ticket Name: TDA3LA: TDA4x

Part Number: TDA3LA Other Parts Discussed in Thread: TDA2 Hello, I was going through the ISP training in the CDDS. The specified DCC tool seems to assist us with the tuning process. I found in the RTOS SDK only xml & binary file for specific cameras sensors and various modes, but Unfortunately, I haven't found the DCC tool itself. Where can I download it? does it come with documentation? Thanks, Rotem Bernstein

Hello Rotem, DCC tuning tool is not yet released and will be available soon. Rgds, Brijesh

To clarify... TDA3 tool is available but TDA4 tool is under development.

Thanks for the quick response. It was written under TDA3 because there's no "TDA4x" topic in my scroll bar yet. BTW - Could I get the DCC tool for TDA2, so I'll be able to practice it with my previous EVM until TDA4x DCC will be released? Thanks, Rotem Bernstein

Hello Rotem, TDA2 is an ISP less device, so the tool does not apply. If you are referring to TDA2Plus, then you can use the same tool as TDA3 since the ISP is exactly the same from tuning point of view. Regards, Mayank

Ticket Name: Linux/TDA2: add lib

Part Number: TDA2 Tool/software: Linux i try to add mylib in framecopy link for test include $(vision_sdk_PATH)/build/hlos/makerules/linux/common_header_a15.mk INCLUDE+= -I$(vision_sdk_PATH)/mylibs/include -I$(ipc_PATH)/hlos_common/include -I$(ipc_PATH)/packages -I$(kernel_PATH)/include/generated/uapi $(OSA_INC) -I$(ipc_PATH)/linux/include -I$($(MAKEAPPNAME)_PATH) LIBS += $(vision_sdk_PATH)/mylibs/libarcsoft_face_base.a LIBS += $(vision_sdk_PATH)/mylibs/libarcsoft_face_detection.a LIBS += $(vision_sdk_PATH)/mylibs/mpbase.a LIBS += $(LIB_BASE_DIR)/vision_sdk_linux_demo.a LIBS += $(shell cat $(DEST_ROOT)/appLiblist_a15_0.txt) include $(vision_sdk_PATH)/build/hlos/makerules/linux/common_footer_a15.mk have follow problem /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/lib/tda2xx-evm/a15_0/release/apps.a(frameCopyAlgoCpu.o): In function `Alg_FrameCopyProcess': frameCopyAlgoCpu.c:(.text+0xda): undefined reference to `MMemMgrCreate' frameCopyAlgoCpu.c:(.text+0xea): undefined reference to `AFD_InitialFaceEngine' frameCopyAlgoCpu.c:(.text+0x152): undefined reference to `AFD_StillImageFaceDetection' frameCopyAlgoCpu.c:(.text+0x164): undefined reference to `AFD_UninitialFaceEngine' frameCopyAlgoCpu.c:(.text+0x16a): undefined reference to `MMemMgrDestroy

Hello changes in \vision_sdk\apps\src\hlos\adas\src\alg_plugins\openclframecopy\MAKEFILE.MK are correct. please check you placed your libs and header files under $(vision_sdk_PATH)/mylibs/include and $(vision_sdk_PATH)/mylibs/ regards, Shiju

If still not working try to include your libs in \vision_sdk\build\hlos\makerules\linux\common_footer_a15.mk regards, Shiju

Hi: Shiju check you placed your libs and header files under $(vision_sdk_PATH)/mylibs/include and $(vision_sdk_PATH)/mylibs/ i have check this . include my libs in \vision_sdk\build\hlos\makerules\linux\common_footer_a15.mk you mean like this ?? ////////////////// ifndef $(COMMON_FOOTER_MK) COMMON_FOOTER_MK = 1 OBJS=$(subst .c,.o, $(FILES) ) OBJSCPP=$(subst .cpp,.o, $(FILESCPP) ) OBJ_DIR=$(OBJ_BASE_DIR) vpath %.o $(OBJ_DIR) LIB = $(MODNAME).a LIB += $(vision_sdk_PATH)/mylibs/libarcsoft_face_detection.a LIB += $(vision_sdk_PATH)/mylibs/libarcsoft_face_base.a LIB += $(vision_sdk_PATH)/mylibs/mpbase.a //////////////////////////////// thanks shuai

Hi: Shiju add in common_footer_a15.mk but still the same LIB += $(vision_sdk_PATH)/mylibs/libarcsoft_face_detection.a LIB += $(vision_sdk_PATH)/mylibs/libarcsoft_face_base.a LIB += $(vision_sdk_PATH)/mylibs/mpbase.a BEST WISHES SHUAI

Hello Try to add similar way of "OPENCV_LIBS" are included in \vision_sdk\build\hlos\makerules\linux\common_footer_a15.mk This is the way we have included various libraries regards, Shiju

Ticket Name: Compiler/TDA2: Advantage and disadvantage using JTAG XDS110 vs XDS560v2 on TDA2 platform and other question.

Part Number: TDA2 Tool/software: TI C/C++ Compiler Dear TI, i am currently doing some development on this TDA2 EVM board and i am not sure which debugger kit is useful on it. Question 1) i found currently there are 2, XDS110 and XDS560v2 are you able to help to list the advantage over it? so i am able to decided which one to purchase over it. Question 2) is it a must to use the debugger in order to do programming onto the in EVM?

Hello Willson Toh59, Willson Toh59 said: Question 1) i found currently there are 2, XDS110 and XDS560v2 are you able to help to list the advantage over it? so i am able to decided which one to purchase over it. See my post here. It should give you guidance deciding over which jtag to buy. Willson Toh59 said: Question 2) is it a must to use the debugger in order to do programming onto the in EVM? Without Jtag, the CCS leverages and debugging options are very limited. Though, you should be able to use a UART console for example. Thanks, Alex

Hi, In addition to what Alex said I would suggest you to prefer XDS560v2 over XDS100 during development phase due to considerable speed advantage while loading big applications on multiple CPUs. Regards, Rishabh

Dear Rishabh So i other word i can still do the development by using the existing demo project to edit and re-compile and generate the MLO and Applmage and transfer it to the SDcard as well without the JTAG. I am correct?

Hi Wilson, Yes this is correct. But you need JTAG in case you want to single step in order to debug. Regards, Rishabh

Ticket Name: RTOS/TDA2: TIDL Reference executable

Part Number: TDA2 Tool/software: TI-RTOS Hi Everyone , I am trying to run the TIDL reference executable by compiling the source code given under the folder REL.TIDL.01.01.03.00 in ubuntu . We are planning to import caffe model into the tool for generation of files . When I tried to make it , I am getting following error . ======== tidl ALGO ================= make -C ./algo -f makefile make[1]: *** algo: No such file or directory. Stop. makefile:76: recipe for target 'all' failed make: *** [all] Error 2 can anyone kindly guide what is the error and how to resolve this .

Hi Surendar, do you try to build the source release (REL.TIDLSRC.01.01.01.00) or the object release which is included in VisionSDK (REL.TIDL.01.01.03.00)? You can rebuild only the source release. I think you do not need to rebuild TIDL if you want to import caffe model, please check chapter "3.6.4 Importing Caffe-Jacinto-Models" of the userguide. Regards, Yordan

Ticket Name: TDA2P-ABZ: TDA2P-ABZ

Part Number: TDA2P-ABZ Other Parts Discussed in Thread: TDA2 We're using IS25LP512M flash memory device in TDA2P based design. This device supports different modes such as Standard SPI, Fast, Dual, Dual I/O, Quad, Quad I/O, SPI DTR, Dual I/O DTR, Quad I/O DTR, and QPI Could you please recommend which mode is preferred when we interface this device with TDA2PHGrRQACD(R)-Q1 device? Please note that there will be single flash memory device interfaced over QSPI.

Hi, According to TDA2 TRM, QSPI interface supports Quad read mode and one-bit write mode. Regards, Stan

Hi, QSPI supports one bit read as well. Regards, Rishabh

Ticket Name: TDA2PXEVM: TDA2 - Tidl_OD usecase

Part Number: TDA2PXEVM Hi Sirs, Based on previous discussions -> https://e2e.ti.com/support/processors/f/791/t/886542 If use chains_tidlOD_1 usecase Two-channel run the same SSD model, but different weight. The alg_pluging whether to add an extra tidl, and give another alg_id. Or is there another method? Thanks Horace

Hi, I will check with TIDL team & get back Thanks Gaviraju

Hi, Yes, you have to add an extra tidl, and give another alg_id. Thanks Gaviraju

Hi, Thanks for your reply. BR. Horace

Ticket Name: TDA2: Power management: LPM(standby) and wakeup support for TDA2XX

Part Number: TDA2 Hello: this document(http://www.ti.com.cn/cn/lit/an/sprac22/sprac22.pdf) introduce the power manage for TDA2xx about the standby and wakeup. my question is : 1. Can one of M4 core control the MPU(A15) step into standby mode and wakeup it? after wakeup, can A15(linux) recover and continue to run properly? 2. Can one of M4 core also control other IPU DSP step into standby mode? and wake up them sequencely ? 3. Is there external PINs to control the whole TDA2xx SOC step into standby mode and wakeup? Thanks!

Hi Andy, The MPU (A15) would need to exceute the WFI instruction to enter into the standby mode. Additionally any MPU_LPRM registers to be programmed depending on what power mode you would like to enter from the A15 should be programmed by the A15 itself as these registers are not programmable from IPU M4. The IPU could potentially only program the SoC level PRCM MPU registers. I would imagine a potential scheme to be IPU sends a message to the A15 to enter Standby. The A15 programs the SoC PRCM, LPRM and runs the WFI instruction to enter standby. (This may involve some other steps to make sure other tasks on the A15 are quiescent, if there is a peripheral interaction that the A15 talks to and likely to generate interrupts that too is kept quiescent). When the IPU wants to wake up the A15 it can send a message over mailbox. The interrupt of the Mailbox will then wakeup the A15 to restore and continue to run. Again for the DSP case, the DSP itself needs to run the IDLE instruction and write to the PWRCMD register in the C66x corepac. IPU could potentially program the SoC PRCM registers. A similar scheme as the A15 described above can be used. Note the lowest power state of the DSP is power domain off state. If you try to "wakeup" the DSP from this state, you would need to restart the C66x DSP. HW_AUTO (clock gated) state does not require a C66x restart. The code can continue from where it entered clock gate state. TDA2xx does not support gating the clocks of the Core power domain IPs. The external pin can be used to tie up to an interrupt which is routed to the desired core in order to wake up the device. For example, one of the GPIO lines can be used to take an input and the GPIO interrupt can then be routed to the A15/IPU . This interrupt can be used to wakeup the CPU core which then wakes up the rest of the device. Thanks and Regards, Piyali

Hi Piyali: Thanks . Just one more to confirm that if any cores wakeup, all context will restore and continue to run, no exception?

Hi Andy, If you are going to HW_AUTO clock gated state or Retention (in the case of A15), all the context is retained even after low power mode. No Exceptions from the hardware behavior. If you are going to PD_OFF state, then you would need to restart that particular CPU. Thanks and Regards, Piyali

Hi Piyali: Thanks very much.

Ticket Name: TDA2PXEVM: Synchronization time between A15 and MCU

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello, My name terence Xia from ECARX China. Our company is using the chip model of TDA2PXEVM. At present, there is a demand: the A15 use to collect video data and the MCU collects IMU data. How to synchronize the time of these two groups of data? I'm using vision SDK which released by TI. thanks.

Hello If you use Vision SDK (SW development Kit) from TI, we insert a unique timestamp to each and every video frames while it getting captured. This information can be used for sync-up. For MCU side also you may need to do something similar to synchronize the time of these two groups of data regards., Shiju

Hi Shiju, I have a question about that, I'm using this function of OSA_getCurGlobalTimeInUsec to get the UTC time. When I get the time in A15, how can I send it to the external MCU, and synchronize MCU and TDA2 time. The MCU is external to TDA2,which use UART to connect with each other.

Hello I think, you need to use the SPI if its a data path with Video. UART is fine if its only ultrasonic data. I guess you might need some kind of Fusion and I do not know where it happen, but you need to pass this time stamp information to ECU or MCU, where this fusion logic runs regards, Shiju

Ticket Name: TDA2SX: NDK Change static IP configuration

Part Number: TDA2SX Hi, TI Experts! We use TDA2X custom board with PROCESSOR_SDK_RADAR_03_07_00_00 and set up IP configuration in PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\links_fw\src\rtos\bios_app_common\tda2xx\cfg\NDK_config.cfg Can we change static IP configuration in our application at runtime? Can you advice any examples? Best Regards, Dmitry

Hi, Please refer to the below thread. https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/681655/ccs-msp432e401y-how-does-the-udpecho-sample-code-configure-static-ip Regards, Stanley

Thanks a lot!

Ticket Name: TDA2PXEVM: How can I extract two CNN output tensors on TIDL (TDA2)

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hi sir! My network have two (maybe more) output layers (CxHxW) : Cx56x56 & Cx28x28. How can I get two outputs from TDIL?

Hi IIuo, Sorry for the delay. This is not supported in TIDL on TDA2. Thanks, Praveen

Hi Praveen I proposed a method to solve this problem ： using Transpose Conv and Concat. Step 1. I add a Transposed Conv layer with 4x4 kernel, stride 2 to the small size layer (for upsampling : Cx28x28 -> Cx56x56) Step 2. I fill filter manually to make Transposed Conv layer working as insert 0 between original output elements [e11 e12 -> [ e11 0 e12 0 e21 e22] 0 0 0 0 e21 0 e22 0 0 0 0 0 ] Step 3. I use Concat layer to get my output tensor : 2Cx56x56 So I can simply add stride =1 / 2 to decode different output tensor. Those works have been tested on Caffe. Hope that can help others.

Thanks for sharing.

Ticket Name: CCS/TDA2: Problem of allocation of heap in core using Vision SDK

Part Number: TDA2 Other Parts Discussed in Thread: SYSBIOS Tool/software: Code Composer Studio Hi, I'm using Vision SDK 3 for loading my program onto tda2x. At first, I could read necessary binary file and save it into memory during Use-case initailization proces. I guess it is contained in DDR heap memory. However, when I tried to allocate memory in DSP1 (C66) using malloc(), I got a message. ' ti.sysbios.heaps.heapmem line 221 out of memory: handle=.... size-.... ' How can I increase heap size in each core when I'm using Vision SDK? I tried to understand the memory mapping guide but it wasn't easy. I'm using A15, DSP1, DSP2 core to load program on them and sometime I may need to allocate large amount of heap memories during each program(Use-case). Thank you.

Hi , Please use Utils_memAlloc when allocating a larger buffer Regards Chetan.M

Ticket Name: RTOS/TDA2: Part number selection

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, Now we are using TDA2x part number is TDA2SXBTQABCQ1 to implement TIDL OD, LD and TSR, but could we use TDA2SGBRQABCQ1 (only 1xA15, the rest of functions are the same) or lower version (e.g. TDA2HGBRQABCQ1) for cost saving w/o performance degradation? Please refer to the attachment to help double check what's minimum version of HW chipset for PROCESSOR SDK-VISION-03.04 OD, LD and TSR (we are combining OD, LD and TSR functions). Thank you. SidneyADAS TDA2 Part number.xlsx

Hi Sidney, The TDA2x part number selection depends on your use case and fps requirement. We provide the performance of our modules in Mega Cycles in their respective data sheets and from these numbers you can calculate the performance and can choose required TDA2x part number. For example, TIDL OD usecase need "96.24 Mcycles" on EVE and need "5.87 Mcycles" on DSP, mentioned in the data sheet. Thanks, Praveen

Hi Praveen, I can not find it from datasheet (Silicon Revision 2.0), could you advise me which one document to show TIDL OD usecase need "96.24 Mcycles" on EVE and need "5.87 Mcycles" on DSP ? BTW, except EVE and DSP, will it also tell me when we need 2xA15 or 1xA15 only due to local FAE informed me TIDL OD needs 2xA15? Sidney

Hi Sidney, You can find this document (TIDeepLearningLibrary_DataSheet.pdf) in VSDK at <install_dir>\ti_components\algorithms\REL.TIDL.01.01.01.00\modules\ti_dl\docs folder. Also, this A15 core details will be given in use case chains and this can be find in VSDK at "<install_dir>\vision_sdk\apps\src\rtos\usecases\tidl_OD\chains_tidlOD.jpg". Thanks, Praveen

Hi Praveen, Thank you for prompt reply. For EVE and DSP, I can learn from the document of TIDeepLearningLibrary_DataSheet.pdf. But from chains_tidlOD.jpg, there is only one A15 on the diagram, does it mean TIDL OD just needs one A15? Now we are using TDA2x part number is TDA2SXBTQABCQ1 (2xA15) to implement TIDL OD, LD and TSR, but we would like to change to use TDA2SGBRQABCQ1 (only 1xA15) and not sure it is available for TIDL OD, LD and TSR applications. Thank you. Sidney

>> But from chains_tidlOD.jpg, there is only one A15 on the diagram, does it mean TIDL OD just needs one A15? Yes, correct. TIDL OD needs one A15 core. For other use cases also you can check the use case diagrams. Thanks, Praveen

Ticket Name: Compiler/TDA2PXEVM: SPI driver on SDK

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi, I try to run SPI driver on IPC1_C0 core. 1. I delete all the code from Chains_main.. 2. I add the SPI driver code for test as below: Void Chains_main(UArg arg0, UArg arg1) { UInt8 Datatest[8] = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08}; UInt8 *ptest; ptest = &Datatest[0]; Utils_mcspiInit(0); IPU1_0_edmaHandle = Utils_dmaGetEdma3Hndl(0); IPU1_0_SpiHandle[0] = Utils_mcspiOpen(0,0,0,IPU1_0_edmaHandle); Vps_printf(" ####test aaaaaa #### \n"); while(1) { BspOsal_sleep(100U); Utils_mcspiWrite(IPU1_0_SpiHandle[0],ptest,(UInt16)0x0008); Vps_printf(" SPI send succeed! \r\n"); } } 3. I measured on the TDA2 EVM. CS/Clock drive failed. there is no output. I have two question: 1. Is it possible to RUN SPI on IPU1_0. 2. How to enable IPU1_0_main function since the default is IPU_PRIMARY_CORE_IPU1 enabled.

Hi, Yes, it is possible to run SPI driver on IPU. If you are using Linux then change IPU_PRIMARY_CORE_IPU to ipu1_0. By default, it is set to ipu2. Rgds, Brijesh

Hi, background: SDK 3.0.7. TDA2P EVM The default configuration in cfg.mk: IPU_PRIMARY_CORE=ipu1_0 IPU_SECONDARY_CORE=ipu2 What is the concept for IPU_PRIMARY_CORE and IPU_SECONDARY_CORE? If I want to drive SPI. Which one should be set to IPU_PRIMARY_CORE? Thanks for your info.

Hi, That depends on which core you want to access SPI driver. You could access from any core, as long as SPI driver is supported on that core. Please refer to PDK driver documentation to understand about drivers support. Rgds, Brijesh

Ticket Name: TDA2: VCOP and memory access

Part Number: TDA2 Hi, Following is environment detail : Platform - TDA2X - EVM. VisionSDK 3.x I have a Link that runs on EVE and accesses the buffer allocated from shared memory (Say camera buffer from SDRAM) -- allocated via Vision SDK Link and Chain framework. I wanted to use write VCOP kernel and call it from EVE/ARP32, which would execute algorithm/computation on this buffer on VCOP and get the result back on EVE . However, it seems that: 1. VCOP would work always on IBUFLA, IBUFLB, IBUFHA, IBUFHB and WBUF internal memory. 2. VCOP Can not access DMEM of ARP32 3. EVE can access IBUFLA, IBUFLB, IBUFHA, IBUFHB and WBUF Queries : Q1. Can you please confirm understanding on #1, #2 #3? Q2. If this is the case, then is it expected to do memcpy/dma from external memory to VCOP internal memory before executing kernel on VCOP ? Q3. Is there is way to avoid this memory copy / block copy ? Thanks, Uday

Hi Uday, Please find my answers as follows: Q1. Can you please confirm understanding on #1, #2 #3? Understanding of #1 and #2 are correct. Regarding #3, what do you mean by EVE can access? If you meant ARP32 then yes ARP32 can access all the internal memories ( including DMEM) but the access is still dependent on the ownership of the buffer. Both ARP32 and VCOP cannot simultaneously access the same buffer. Q2. If this is the case, then is it expected to do memcpy/dma from external memory to VCOP internal memory before executing kernel on VCOP ? Yes, you need to DMA the data first from external memory to internal memories of EVE subsystem before VCOP can process it. Q3. Is there is way to avoid this memory copy / block copy ? No, this cannot be avoided as VCOP can only work with data being in internal memory of EVE (IBUF's and WBUF). Regards, Anshu

Hello Uday, Please refer to the attached presentation. It covers the topics you are referring to: Q1. Can you please confirm understanding on #1, #2 #3? Your understanding is correct for #1, #2. For #3, I assume you meant ARP32 can access IBUFLA, IBUFLB, IBUFHA, IBUFHB and WBUF. Q2. If this is the case, then is it expected to do memcpy/dma from external memory to VCOP internal memory before executing kernel on VCOP ? Yes, this is correct. Q3. Is there is way to avoid this memory copy / block copy ? No there isn't any other way for VCOP to access external memory as there is no data cache, neither any direct access to memories other than the image buffers and working buffer. However the copy can be done concurrently with VCOP processing so you are not wasting any cycles as long as your compute cycles exceed the transfer cycles. Implementation of an EVE App.pdf

Ticket Name: Linux/TDA2: EVE Computing power benchmark for deep learning, DSP benchmark for machine learning

Part Number: TDA2 Tool/software: Linux As we understand, EVE Computing power is used for deep learning, DSP is used for machine learning Would you please provide EVE Computing power benchmark table for deep learning and DSP benchmark table for machine learning ? Or EVE and DSP performance comparison table with popular deep learning SOC?

Hi Joseph, you can check PROCESSOR_SDK_VISION_03_06_00_00\ti_components\algorithms\REL.TIDL.01.01.03.00\modules\ti_dl\docs\TIDeepLearningLibrary_DataSheet.pdf for TIDL performance info. Regards, Yordan

Ticket Name: Linux/TDA2: How does dual core C66 parallel the same CNN?

Part Number: TDA2 Other Parts Discussed in Thread: TDA3MA Tool/software: Linux The development board I use now is TDA2X, and SDK uses SDK_VISION_03_02_00_00. But we're going to use TDA3MA, which has two C66 and one EVE, and I don't know how these three cores work together. I have four CNNs to implement, and my idea is that I make a C66 link in which I will implement three CNNs (two C66 in parallel) and build an EVE LINK and the last CNN to implement in EVE, right? Then a LINK uses a single C66 to implement a CNN I know how to do it, but how about two C66 processes a CNN in parallel? Is there a sample use dual core parallel processing a algorithm in SDK?

Hi, Refer below User guides of TIDL in VSDK, we had TIDL OD use case which uses multiple EVE cores and C66 for processing. 1. <install_dir>\vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_TI_DeepLearning.pdf <install_dir>\vision_sdk\vision_sdk\apps\src\rtos\usecases\tidl_OD\chains_tidlOD.jpg 2. <install_dir>\ti_components\algorithms\REL.TIDL.01.01.01.00\modules\ti_dl\docs\TIDeepLearningLibrary_UserGuide.pdf Thanks, Praveen

Hi Praveen: in my sdk have ti_SDK_VISION_03_02_00_00\vision_sdk\apps\src\rtos\usecases\tidl no vision_sdk\vision_sdk\apps\src\rtos\usecases\tidl_OD tidl is tidl_OD the same ??? in tidl have chains_tidlEveTda3x.jpg use eve1 only

in VisionSDK_UserGuide_TI_DeepLearning.pdf Entire input frame is processed on a single core and there are 2 processing pipelines which process the input frames alternatively: this mean the same frame is copy processed same time by DSP1 and DSP2 ,DSP1 is done cnn1 and cnn2 ?

Hi, Please refer to latest VSDK release ti_SDK_VISION_03_04_00_00 , the mentioned use case is not there in the ti_SDK_VISION_03_02_00_00 release. Thanks, Praveen

Hi:Praveen in VisionSDK_UserGuide_TI_DeepLearning.pdf Entire input frame is processed on a single core and there are 2 processing pipelines which process the input frames alternatively: this mean the same frame is copy processed same time by DSP1 and DSP2 ,DSP1 is done cnn1 and cnn2 ? Shuai

Hi Shuai, Yes, your understanding is right. Thanks, Praveen

Ticket Name: TDA2E: Cascade Radar AWR1243 VCO error

Part Number: TDA2E Other Parts Discussed in Thread: AWR1243 Hello, I am using the TI Cascade radar with 4 AWR1243 chips, for this I am using the PROCESSOR_SDK_RADAR_03_07_00_00 also the MMWave studio. I have a problem when i set the frequency to 76.566Ghz with radar slope to 14.677048 with .pfVcoSelect as 0, the SW give me an assert Assertion @ Line: 376 in C:/PROCESSOR_SDK_RADAR_03_07_00_00/vision_sdk/apps/src/rtos/radar/src/common/chains_common_ar12xx.c: SYSTEM_LINK_STATUS_SOK == retVal : failed !!! . I debugged it with MMwave studio there it was more clear Status: Failed, Error Type: RAMP END FREQUENCY IS NOT WITHIN VCO RANGE. if we check the user guide it says following PF_VCO_Select b1 VCO_SEL 0 VCO1(77G; 76-78Ghz) Note: 2. xWR1xxx devices: there is an overlap region of 77-78Ghz in which any of the VCOs can be used, for any other regions use only the VCO ccan work in that region ..... Going by this our setting of VCO1 should have worked but seems like its giving a problem, Is there something we missed or some feature like FUSA is activated. Can somebody give me a pointer on this regard how to check this either using mmWave or PROCESSOR_SDK_RADAR_03_07_00_00 Sw. Best Regards Deepak Joshi

Hi I will check with RADAR expert & get back to you. Thanks Gaviraju

Hi Deepak, It is better to debug this with mmWave Studio. Regards, Stanley

Hi Deepak, Valid VCO frequency range is a function of chirp start_frequency and end_frequency. That bandwidth is calculated as start_freq + chip_slope * ramp_end_time. Can you please verify if the full chirp bandwidth is valid for the VCO you are selecting? I also suggest giving problems like this a run in the mmWave Studio script environment. You can easily test which VCO ranges are valid or not. Please check the DFP ICD for valid values: http://downloads.ti.com/ra-processors/esd/MMWAVE-DFP/latest/exports/mmWave-Radar-Interface-Control.pdf Thanks, -Randy

Ticket Name: TDA2E: about mipi csi data type issues

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 hi, ti support The processor we use is TDA2 ECO 23*23. There are 4 cameras in our system. The interface connected to the deserializer (DS90UB960) is the mipicsi interface. The resolution of our camera is 1280*1280, and the format is yuv422 uyvy, On tda2, we use datatype 0x1e( pOutPrm->inCsi2DataFormat = SYSTEM_CSI2_YUV422_8B) to receive .but now we have a new requirement. We have added a line (1281*1280), this line is embed line, datatype It is 0x12. How should we configure it to receive data of two datatypes in tda2? The picture shows the value of the ub960 register：

Hi yongzheng, You would just require to add DMA channel to capturing blanking data, as show below. Please note this is capture link parameters. for(ch = 0;ch < 2;ch++) { pOutPrm = &pCapturePrm->outParams[ch]; pOutPrm->dataFormat = pOutPrm0->dataFormat; pOutPrm->width = pOutPrm0->width; pOutPrm->height = pOutPrm0->height; pOutPrm->maxWidth = pOutPrm0->maxWidth; pOutPrm->maxHeight = pOutPrm0->maxHeight; pOutPrm->numOutBuf = pOutPrm0->numOutBuf; if (0 == i) pOutPrm->inCsi2DataFormat = 0x1B; // for YUV422 8bit data else pOutPrm->inCsi2DataFormat = 0x12; // for embedded data. pOutPrm->inCsi2VirtualChanNum = ch; } Regards, Brijesh

Ticket Name: DRA726: 360 degree surround view support

Part Number: DRA726 Other Parts Discussed in Thread: TDA2E, , TDA2, TDA4VM Hello all, I'm working on an automotive DRA726 based design and I have asked about the possibility of implementing 360º surround view in this processor. I know this is more related with TDA2e than with DRA726 as it is an ADAS function, but I would like to know if there is any HW or SW limitation that makes impossible/hard to implement this function in a DRA726. (IE: no SW native support, HW limitation...) Thank you very much for your time.

Hello, DRA72x has the same GPU as TDA2 and you should be able to support 3D Surround View. You can also consider newer TDA4VM with newer graphics engine. Regards Hemant

Hello Hemant, I have discussed with the customer. Their application is a DRA72x infotainment one built onto the DRA7x Linux SDK 6.0.0.3. They want to add onto it a surround view application from our TDAx Vision SDK 3.8.0.0. Do you expect any compatibility issue there? These 2 SDKs have been released in December 2019 and seem to include the same versions of the software components, but maybe one needs more than just matching versions to use a Vision SDK example in the DRA7x SDK environment. Thank you. Best regards, François.

Ticket Name: Linux/TDA2: what databuf do when ipc out ipc in

Part Number: TDA2 Tool/software: Linux a15 ipcout c66ipcin In the process of IPC, is the data need to be copied from A15buf to c66buf, or buf is shared by A15 and C66, without copying data.

Hello No need to copy, the buffer memory is shared and you can just use the sane on C66x without any copy regards, Shiju

Ticket Name: RTOS/TDA2PXEVM: Creating folder and copying the files into the SD card using network Ctrl

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS hello, I need to create a folder in the SD card and copy the files into the folder. I am able to create the folder but not able to copy the files into it. And also if the folder is already present,it gives assertion fail. Assertion @ Line: 195 in /source/vision/platform/ti/tda2/apps/src/rtos/modules/network_ctrl/network_ctrl_handle_mmc_wr.c: 0 == status : failed !!! 1. how to create a folder into the sd card? 2. how to change the directory to copy the files into the folder created? Below is my code: status = File_getcwd(cwd, (Int32)1000); if(0 == status) { char godfolder[NETWORK_CTRL_CMD_STRLEN_MAX]={'G','O','D'}; // new folder :GOD strcat(cwd, "/GOD"); System_linkControl( linkId, SYSTEM_LINK_CMD_MAKE_DIR, godfolder, strlen(godfolder)+1, TRUE); status = File_chDir(cwd); }

Hi Vijeetkumar, Which version of VSDK are you using? I am supposing that the MAKE_DIR is a custom command you have added. If yes, can you please share your version of the network_ctrl_handle_mmc_wr.c(both pc side and evm side) file so that I can have a closer look at it :) Regards, Anand

Hello Anand, I am using PROCESSOR_SDK_VISION_03_03_00_00. But anyways folder is getting created now. Thanks for the help. I want one more help on deleting the folder. I am using the below function: status = File_delete(dirPath); f_unlink(filename) is returning 7, which means access denied. FR_DENIED, /* (7) Access denied due to prohibited access or directory full */ Note: I am able to delete the file with the same api but not directory.

Hi Vijeetkumar, This is strange. The same api should work for both file or directory delete. Can you put a breakpoint in f_unlink() and step through to find out why exactly does it go to FR_DENIED? It could be due to attempting to delete a read-only dir/file, or other reasons like that. Meanwhile, I'll try to replicate this on my side. Regards, Anand

Hello Anand, I cant find definition for f_unlink() and also debugging is slightly difficult for me as I am not using jtag. I putting print statements for debugging. if its denying due to read-only how to make it write? were you able to replicate it?

Hi Vijeetkumar, I have not yet been able to replicate the setup. Hmm. It is strange that you can't find the definition of f_unlink(). You should be able to find it in some of the fatfs library files. Then you can try putting printfs under each ifdef. I would recommend using a debugger though. Regards, Anand

Hi Vijeetkumar, Were you able to find the function f_unlink()? I believe you were able to fix the issue/you don't see the issue anymore? Regards, Anand

Ticket Name: TDA2: NEW CNN MODEL SUPPORT

Part Number: TDA2 Hi， dear Could tda2x support the open-pose( you can google to find which is a kind of cnn model for pose recognition) demo？ If not， when to support it？ Or any idea for me to improve the current vision TIDL to support the pose model recognition? Looking forward to your best reply! Tks!

Hi, Please refer to TIDL data sheet (TIDeepLearningLibrary_DataSheet.pdf) for supported layers by TIDL. If the open pose CNN model has only layers supported TIDL then tda2x can support this model, and we don't have any plans to add new layers for TIDL. Thanks, Praveen

Ticket Name: TDA2SA: Is there a Code Composer Studio(CCS) project existing to build the "VISION SDK/project" on OS (Linux/or windows) Platform ?

Part Number: TDA2SA Other Parts Discussed in Thread: TDA2 Hi Expert, My platform is TDA2 I want to confirm again. Is there a Code Composer Studio(CCS) project existing to build the "VISION SDK/project" on OS (Linux/or windows) Platform ? Thanks Daniel

Hi Expert Is there any update? Thanks Daniel

Hi, No, we use commend line and makefile to build Vision SDK. CCS build takes longer time than command-line build/makefile build. Regards, Stanley

Ticket Name: Differences between TDA2XX and TDA3XX

Other Parts Discussed in Thread: TDA2 Hi I am trying to port source code that works on TDA2xx on TDA3xx.I have following doubts: 1.Master core in TDA2XX is a15 and in TDA3XX it is m4,so we have to shift all modules that are being used by a15 in TDA2XX to m4 in TDA3xx. 2.Modules on which the functionality like ethernet,camera capture depends in TDA2xx.At the bare minimum i want ethernet and camera capture functionality to be working on TDA3xx. 3.vip module uses tda2xx video driver which has 12 capture,but tda3xx supports 4 camera,this needs to be identified where all changes are required. Regards Mayank

Hi, Moving your post to right forum to be better answered. Thanks & regards, Sivaraj K

Mayank, You could start with Vision SDK. It already supports Ethernet, camera capture and other drivers on TDA2 and TDA3. In both cases the SW runs on the M4. On TDA2 the physical master is the A15, which will launch the secondary boot loader (SBL). The SBL will load and start the code from the M4.

Hi Ejs, Thanks for your mail.I am proceeding the following steps: 1. Take all the TI packages namely bios,starterware,edma,ipc,xdc,bsp from Vision SDK and compile them for TDA3XX.(I could do this for starterware and bsp only.For other packages are they compatible with TDA3xx as they are for TDA2XX or they also need separate compilation) 2.Compile my application code with tda3xx toolchain. I still have following doubts; 1. Will i have to shift modules running on a15 core to dsp/m4 core or simply disabling a15 compilation while compiling the application for tda3xx will work. 2.Will tda3xx compilation require altogether different toolchain from what i was using when compiling for tda2xx. 3.Bootloader packages will be generated from starterware module using sbl user guide and using that will boot the board. 4.If i compile the code for dsp and m4 cores and then generate the combined disc image and flash it in tda3xx,will it work or i have to make other changes. Regards Mayank

Hi Mayank, All TI packages are compatible with TDA3xx. In case you have designed your application to run some particular operations on A15, you will need to shift it to dsp/m4. You can refer to Vision SDK as an example. TDA3xx compilation uses same tool chains as TDA2xx. M4 uses TMS470, DSP uses C6000 and EVE uses TI ARP32 compiler. You can create multi-core application image including both dsp and m4 cores (you can follow steps given in SBL user guide) and it will work. Regards, Rishabh

Ticket Name: Linux/TDA2: vision_sdk\links_fw\src\hlos\links_a15 this links only for A15 or common?

Part Number: TDA2 Tool/software: Linux in vision_sdk\links_fw\src\hlos\links_a15 have some links , this links only for A15 or common? i think i can run IPCOUT on A15 and IPCIN on C66 CORE, should i ??

Hi Shuai, the links in "vision_sdk\links_fw\src\hlos\links_a15" are for High Level OS (e.g. Linux) which can run only on A15. The links in "vision_sdk\links_fw\src\rtos" are for Bios and can run on the other cores. In particular you can check "vision_sdk\links_fw\src\rtos\links_common\ipcOut" and "vision_sdk\links_fw\src\rtos\links_common\ipcIn". Regards, Yordan

Ticket Name: TDA2EXEVM: Expansion Interface Details

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 I need to use TDA2 for a custom application utilizing 3-5 mcasp interfaces, I am trying to see if it's possible to use one of the existing EVM and attach my custom design through the existing expansion interfaces but I can't find the details of the interface for TDA2EX-17 or TDA2EX in the user guide, it only mentions it's for specific application?! does this mean it's only usable for TI's expansion boards!? can you provide these document?!

Hi, I will check with an expert, get back asap.

Hello, You'll need to check the schematics to see what's pinned out on the connectors. Regards, Kyle

Ticket Name: RTOS/TDA2: [Vlib in vision sdk]. Is Vlib function thread safe ?

Part Number: TDA2 Tool/software: TI-RTOS Hi Ti, I am currently use Vlib with links-chain concept in the latest rtos vision SDK for TI TDA2X (2 dsp core). I have used vlib's connected component function and it works fine. Now i plane to use this function to multiple 'link'(thread) on 2 dsp cores. (2 links on 2 dsp core each. total 4 links) Problem is, this function does not work correctly when I use it with multiple link with 2 dsp cores. (It works fine if I use just one link on one dsp core.) All the memories for each connected component functions are allocated in inside of link, and, I checked that the memories not invaded each other. They have a different address. But It seems that the results of each functions are mixed. Have Vlib function tested with multiple link? Is it thread safe ?

No, VLIB is not thread-safe and was not designed or tested as such. This may explain the issue you are seeing.

Thank you Jesse.

Ticket Name: RTOS/TDA2: Error of create an new use case

Part Number: TDA2 Tool/software: TI-RTOS Hi We fallow the user guide and want to create an new use case but We got an error below ========================================================================== undefined first referenced symbol in file --------- ---------------- Chains_tidlODPrimax C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/binaries/app s/tda2xx_evm_bios_all/lib/tda2xx-evm/ipu1_0/release/app_libs.aem4<chains_main_bi os_tidl.oem4> error: unresolved symbols remain error: errors encountered during linking; "C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/binaries/apps/tda2xx_evm_bio s_all/vision_sdk/bin/tda2xx-evm/vision_sdk_ipu1_0_release.xem4" not built gmake[7]: *** [C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/binaries/apps/tda2 xx_evm_bios_all/vision_sdk/bin/tda2xx-evm/vision_sdk_ipu1_0_release.xem4] Error 1 gmake[6]: *** [ipu1_0] Error 2 gmake[5]: *** [apps_ipu1_0] Error 2 gmake[4]: *** [apps] Error 2 gmake[3]: *** [apps] Error 2 gmake[2]: *** [apps_exe] Error 2 gmake[1]: *** [apps] Error 2 gmake: *** [vision_sdk] Error 2 ========================================================================== Can you tell us what's wrong with the error? How can we fix this error? BR Allen

Hi Allen, when you run make command can you try to run it without "-j" option (this option creates several build processes and some dependencies might not get calculated correctly). Regards, Yordan

Hi I retry to run it without "-j" option but I get same error Even I make a clean build (rm rf binary and gmake clean) what's mean with the error? How do we do? BR Allen

Hi Have any solution? Our new use case is want to read the source from SD card and do the lane detect so we reference "vip_single_cam_lane_detection" and "null_src_dec_display" two use case but we got the error Do you know we have any problem? BR Allen

Hi Allen, I pinged VisionSDK experts for further help. Regards, Yordan

Hi Allen , Are there changes done in the code or its out of release . ? Regards Chetan.M

Hi I solve this problem,but I got the another problem I post a new question below Can you help us to solve the question? BR Allen

Ticket Name: Linux/TDA2: HAO CAN i use 2 A15

Part Number: TDA2 Tool/software: Linux I HAVE build vision_sdk,and run it , but in use case use only one A15 ,i have to use 2 A15 , what can i do ? in file configs\tda2xx_evm_linux_all cfg.mk PROC_IPU1_0_INCLUDE=no PROC_IPU1_1_INCLUDE=no PROC_IPU2_INCLUDE=yes PROC_A15_0_INCLUDE=yes PROC_DSP1_INCLUDE=yes PROC_DSP2_INCLUDE=yes PROC_EVE1_INCLUDE=yes PROC_EVE2_INCLUDE=yes PROC_EVE3_INCLUDE=yes PROC_EVE4_INCLUDE=yes should i add PROC_A15_1_INCLUDE=yes thanks

Hello By default VSDK Linux uses both the A15 in SMP mode, no need to do any separate configuration here. Even if the cfg file has set PROC_A15_0_INCLUDE=yes, the Linux kernel uses both the A15 cores and this is abstracted from the application. regards, Shiju

Hi Shiju which usecase in the visonSDK use both A15? Can refer to！ regards, shuai

Hello All the demos of vision SDK HLOS (Linux) uses dual A15. For the user/application its appears to be as a single A15 core, but underneath the OS uses both A15 cores in SMP mode. You can think as a single A15 core with CPU clock/frequency doubled. regards, Shiju

thankyou!

Ticket Name: CCS/PROCESSOR-SDK-DRA8X-TDA4X: how to test time on TDA4 c66

Part Number: PROCESSOR-SDK-DRA8X-TDA4X Tool/software: Code Composer Studio Hi : on tda2 EVM i test time function cost use TSCH and TSCL. what about TDA4 evm ? unsigned long long WH_time[10]; double WH_cost[10]; TSCH = 0; TSCL = 0; WH_time[0] = _itoll(TSCH,TSCL); Thanks Shuai

Hi Shuai, you should be able to use the same functionality in TDA4x. For some directions you can see "Example 17. Profiling Example" in this AppNote: and this E2E post: Regards, Yordan

Ticket Name: Compiler/PROCESSOR-SDK-DRA8X-TDA4X: TDA4X kernel quickly start use init-demo.sh

Part Number: PROCESSOR-SDK-DRA8X-TDA4X Tool/software: TI C/C++ Compiler Hi all, we use init-demo.sh on tda2x platform, it can start the kernel quickly without some unnecessary services, so we hope to use similar script like init-demo.sh to start the kernel on the tda4x platform.Is it any scripts fix it? Thanks a lot! Regards, Jason

Hi Jason, Yes, you can use the same script or a similar script even on the TDA4 platform. Regards Karthik

Hi Karthik, Thanks for your reply, but we know the init-demo.sh must work at falcon mode, could the tda4x work at falcon mode? Regards, Jason

Hi Jason, From a user space script perspective, it shouldn't matter whether it is falcon mode or not as long as the dependencies are met at the time of execution. If you need additional details, please provide further information on your trials with TDA4. Regards Karthik

Hi Karthik, I use TDA4VM chip. On tda2xx, we just need to config CONFIG_SPL_OS_BOOT=y in the file u-boot/spl/include/autoconf.mk, so the falcon mode could be enable. But I can't found the file in the folder ~/ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3 ,please tell me how to enable the falcon mode in the TDA4VM. Regards, Jason

Hi Jason Currently our SDK does not support falcon boot mode on TDA4VM. Hope this answers your question. - Keerthy

Hi Keerthy, Thanks for you help, would it be supported in the future?For the kernel started so slowly, we need to start it quickly. Regards, Jason

Hi Keerthy, I tried to set the falcon mode like TDA2, so I added CONFIG_SYS_SPL_ARGS_ADDR=0x82f80000 and CONFIG_SPL_OS_BOOT=y to the j721e_evm_a72_defconfig file, and set the environment variables like this: setenv falcon_image_file Image; setenv falcon_args_file single-stage-boot.dtb; setenv boot_os 1; and I put the single-stage-boot.dtb and Image files in the BOOT partition, but an error is reported when running boot: spl: falcon_args_file not set in environment, falling back to default spl_load_image_fat_os: error reading image args, err--2, and there are falcon_args_file=single-stage-boot.dtb and falcon_image_file=Image in the environment variables, I don’t know why it can’t be found. Anyway, if the falcon mode wouldn't be supported on the TDA4VM in the future, how could we started the kernel as quickly as on the TDA2X? Regards, Jason

Hi Jason, TDA4 Boot architecture different compared to TDA2: Refer Section: 3.1.1.2.3 Link: http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_U-Boot.html#general-information So first we boot with the R5 SPL which in turn get ATF(Arm Trusted Firmware) on A72 followed by OPTEE & only then we get to A72 SPL Followed by A72 u-boot. Enabling falcon mode on TDA4 will not be same as TDA2. Hence i kindly advise you to not try based on TDA2. I will get back on the availability of falcon mode in the future releases. Best Regards, Keerthy

Hi keerthy, Thanks very much for you help.Our project needs to be applied to falcon mode of the kernel as soon as possible, like using init-demo.sh to start apps.out on TDA2X. We hope to receive further information from you. If there is any information, please tell me through this issue, or send an email to huangjiasheng@yihang.ai to inform me about how to obtain the release package including the availability of falcon mode. Thanks. Best Regards, Jason

Hi Jason, There is a rtos based bootloader called SBL(Secondary boot loader). There is a way to jump from SBL to Linux which is a sort of falcon mode: One can jump from SBL to kernel Image. The next release PSDKRA 7.1 will have this supported. Hope you can resolve this. - Keerthy

Ticket Name: RTOS/TDA2: I can't find SFM_POSE.bin

Part Number: TDA2 Tool/software: TI-RTOS Single channel demos with HDMI input IMPORTANT NOTE: To demonstrate better output all single channel usecases that require HDMI input should use video clips mentioned in the table below. These clips are part of PROCESSOR_SDK_VISION_03.XX.XX.XX_INPUTS.tar.gz c: 1CH VIP capture (HDMI) + SOF (EVE1) + SFM (DSP1) + Display f: 1CH VIP capture (HDMI) + FrontCam Analytics 2 (PD+TSR+VD+LD+TLR+SFM) (DSPx, EVEx) + Display (HDMI) SFM_POSE.bin - SFM (Usecase ‘c’) and EUNCAP demo (Usecase ‘f’) needs SFM_POSE.bin on the SD card. It is part of VISION_SDK_02.XX.XX.XX_INPUTS.tar.gz，but I can't find VISION_SDK_02.XX.XX.XX_INPUTS.tar.gz，

Hi @hua liu liu , VISION_SDK_02.XX.XX.XX_INPUTS.tar.gz can be found on CDDS here: https://cdds.ext.ti.com/ematrix/common/TIemxNavigator.jsp?objectId=28670.42872.37371.48714 (If you do not have access to CDDS, please contact your local TI FAE) Regards, Yordan

Ticket Name: TDA2: TIDL-1.1 edma utility

Part Number: TDA2 Hi: in tidl src code, in the convolution layer, there are edma_utils_scatthergather and edma_utils_autoincrement, and I don't understand why use both of them, here what the difference between them. I refer the edma docs and learn the convolution layer code, but still can't understand them.

Hi @lin rimao, is this the document you referred: PROCESSOR_SDK_VISION_03_05_00_00\ti_components\algorithms\REL.DMAUTILS.00.08.00.02\dmautils\docs\DMAUtilsLibrary_UserGuide.pdf? It has quite detailed explanation of Scater/Gather and Autoincrement mechanisms. Regards, Yordan

yes, I refered that doc. But in TIDL convolution layer, I can not understand why need both of them. And now, we have trained a ssd model, current the ssd model can run 15 frames in one sec, is there any solution I can take to run the ssd model 30 frames in one sec through refine the tidl code or something else. thanks.

Hi, I have forwarded your question to TIDL experts for further help. Regards, Yordan

Hi, TIDL convolution layer is a complex layer implementation in which we had integrated many data flows to support different kernel sizes and different stride and dilation cases and hence used scatter gather DMA when data is spread across different channels ( for example for input and output feature map data transfers), used auto increment when the data is in continues blocks ( for example Bias data). You can refer to each function header is documented with usage of these DMA implementation functions. Regarding the other question, did you exploit the sparsity in the model to improve the run time performance. We have a extension of caffe training framework called caffe-jacinto ( github.com/.../caffe-jacinto) which can help to induce sparsity in the model. Thanks, Praveen

Hi Praveen: In convolution layer, I noticed for input and output feature map data transfers, both the scatter gather and autoincrement dma utility are used. I don't understand what's the relationship between them. We have exploit the sparsity used caffe-jacinto, now for 640x320 input model, on one eve the local latency is 180ms, is there any ways (for example through modify the dma tranfer or something in the tidl src code for fixed model) to reduce the latency on one eve. thanks.

Hi, And for the bias value, if I can use TIDL_edmaCopy transfer the all bias value, but not use autoincrement dma more times, because the bias value num depend numOutCh.

why these kernels are initialized two times?

why are these kernels initialised two times?

We ahve run kernek from both ping and pong buffer. So we are intilaizing the params in both buffers

Ticket Name: Linux/TDA2EVM5777: Is it possible to use only meta data in TIOP link?

Part Number: TDA2EVM5777 Tool/software: Linux Hi, I wonder that is possible to use only meta data in TIOP link. In original TIOP link, that uses Video composite buffer in algProcess. However, i don't want to use Dup link in TIDL usecase. I mean i want to see only detected bbox information. Is it possible? Regards, Yoo

HI, You can dump the output of tidl link running on DSP. But as TIOP link output data as composite buffer, so that will not be possible. You can modify the object draw link and dump data from there only, this should be possible. Regards, Anuj

HI, I haven’t heard from you, I'm assuming the issue is resolved. I will close the thread. Regards, Anuj

Ticket Name: Linux/TDA2: Linux BSP validation testcases for TDA2x EVM

Part Number: TDA2 Tool/software: Linux I’m in the process of getting my custom hardware based on TDA2x, so in this regard I’m looking for “Testcases and Test code for validating the Linux BSP” (bootloaders, drivers etc..). Can you please let me know if I can get the BSP Test cases and test codes for TDA2x EVM ?

Hi The test plan and scripts are not included as part of the release package - they are mainly TI internal and we rely on Test Management System to manage execution of these You can use generic driver validation tests - dd,hdparm etc for storage, iperf for network class of devices, V4l2 test for video capture, modetest for display etc

Ticket Name: Linux/TDA2: FLASHING TOOLS

Part Number: TDA2 Tool/software: Linux Dear All, I would like to know some of the below question answers Q1:Way of flashing NAND/NOR for TDA2x evm - is there any tool ? Q2:What is the size of MLO, uboot, linux and filesystem, - running on our current TDA2x EVM and also on D3 board. Q3:Current DDR3 memory usage on TDA2x evm needs to be found Q4: List of various drivers involved in TDA2x evm linux - eg: i2c, usb, camera, hdmi and so on…

Hello, I'll let software teams comment regarding your other questions. But for Q1, one way to do it is via the flash tool. Here are a couple related forum posts: Thanks, Alex

Hi, Q2: here are some example sizes: MLO: 125K ; u-boot.img: 819K ; zImage: 3.4M note that this sizes may vary based on your config. the default rootfs from here: software-dl.ti.com/.../index_FDS.html has size 296M, you can add more features to it and size will increase. Q3: Please follow the document <VSDK_INST_DIR>/vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_UserGuide_MemoryMap.pdf for description of how to configure memory in VisionSDK. The default Linux configuration for TDA2x is 1GB. Q4: Linux version of VisionSDK is based on Processor SDK Linux Automotive (PSDKLA), so you can check the supported features in the Data Sheet: processors.wiki.ti.com/index.php Also helpful can be PSDKLA Developer guide and FAQ: processors.wiki.ti.com/index.php processors.wiki.ti.com/index.php Please let me know if you have any further questions. Regards, Yordan

Hello Yordan, RA72x Evaluation module is same a TDA2x EVM? i.e processors.wiki.ti.com/index.php I have a some more question on TDA2x board, please find below list . ------------------------------------------------------------------------------------------ Q5:compile procedure for TDA2x rootfile system/Linux/Uboot? Q6:How to choose MLO for TDA2x? is it processor specific ? Q7:Flashing MLO/UBOOT/KERNEL/ROOTFS on NAND/NOR memory procedure? Q8:TDA2x EVM peripheral like i2c,spi,.... all soc peripherals test suite either unit/system testing procedure? ------------------------------------------------------------------------------------------ Regards, Raghu

Raghu, vhg jgyj said: Q5:compile procedure for TDA2x rootfile system/Linux/Uboot? Q6:How to choose MLO for TDA2x? is it processor specific ? Q7:Flashing MLO/UBOOT/KERNEL/ROOTFS on NAND/NOR memory procedure? Q8:TDA2x EVM peripheral like i2c,spi,.... all soc peripherals test suite either unit/system testing procedure? Are you using Vision SDK? If so please follow the user guides provided along the SDK. There is a lot of information to answer your general questions above. thanks, Alex

Hello Alex, I am using vision DSK, but below some question required more information or any link to cover below please send me. Q7:Flashing MLO/UBOOT/KERNEL/ROOTFS on NAND/NOR memory procedure? Q8:TDA2x EVM peripheral like i2c,spi,.... all soc peripherals test suite either unit/system testing procedure? Regards, Raghu

Hi Raghu, can you check here for flashing to NAND: processors.wiki.ti.com/.../Linux_Core_U-Boot_User's_Guide Regards, Yordan

Ticket Name: Linux/TDA2: I copy some function codes form use-case and add into the others use-case. Error message : Faulty address is 0x4, called from 0x1b155.

Part Number: TDA2 Tool/software: Linux Hi Sir, My HW is TDA2x CPU board + Vision Board + daughter board + LVDS sensor and SDK is PROCESSOR_SDK_VISION_03_04_00_00 with TDA2XX_EVM_LINUX_ALL define. I select use-case "4CH VIP LVDS capture + SGX MOSAIC + DISPLAY". I want to save the source image in this ues-case, then I add some function code in this case (chains_lvdsVipMultiCam_SgxDisplay.c), example "static Void mountFatFs()", "static Void saveCaptureFrames(chains_srvCalibration_DisplayAppObj *pObj)"....etc. After boot on the EVK and select this use-case, it can't be executed successfully, console mode shows below error message: ****** Segmentation fault caught .... Faulty address is 0x4, called from 0x1b155 Totally Obtained 0 stack frames. signal number =11 Signal number = 11, Signal errno = 0 SI code = 1 (Address not mapped to object) Fault addr = 0x4 [bt] Execution path: root@dra7xx-evm:/opt/vision_sdk# What does it mean? Please help and thanks. Ranny.

Hi Ranny, here a few things you can check: - as you take saveCaptureFrames() from another usecase, the struct which is taken as argument might have some fields that your usecase do not have (for example the saveFrameSync mutex). Can you make sure that the fields which the function access exists in the struct (you can also look for suspicious warnings when recompiling). - in saveCaptureFrames() function can you try to just open the file, write some bytes to it and close it and see if it is written correctly - this will show if FS operations work correctly. - do you see Vps_printf() messages in your log, can you add some more prints to narrow down where exactly segmentation occurs? Regards, Yordan

Hi Sir, 1. Attachend file is the log file that I execute boot and use-case process. 2. I only go inside the use-case, I didn't execute "mountFatFs()" & "saveCaptureFrames()" function yet, console alread shows the error message. 3. I try to add the Vps_printf to check exactly issue occurs, seems after creating a new struct and then segmention occurs, - the error structure creating is: "chains_srvCalibration_DisplayAppObj srvCalib_chainsObj; " Thanks. Ranny.

20190221_01_Save_Img-fail.txtI forget to upload the log file. Ranny.

Hi Sir, I modify the function name "saveCaptureFrames()" as the other name, this issue is fixed. I thought this function is a internal function, so I use the same name which I copyed from, I don't know why the same function name will cause this error, even two functions are in different use-case. Anyway, I modify the function name and this error is fixed. Thanks. Ranny.

Ticket Name: Deep Learning and Inference accelerated on DSPs

Other Parts Discussed in Thread: TDA2 Hi, With the multitude of DSPs built into the processors from J6 -> Sitara -> Multicore ARM+DSP, is TI working on or already supporting Deep Learning inference acceleration support? Specially as it applies to applications very similar to the ADAS and autonomous navigation applications targeted by the Jacinto series?

Hi Anup, I will ask our experts to comment on the keystone device support on "Deep Learning inference acceleration" and road map if any. For Jacinto, I knew it is for automotive devices. Can you please post it on Automotive forum for appropriate and faster response. Thank you.

Hi Anoop, We have the vision library - VLIB 3.3 ( software-dl.ti.com/.../index_FDS.html) supporting some of the important kernels of deep learning (convolution, maxpooling, Fully connected) - please refer the library and documentation. This library is for C6x DSP and can be used on any TI device with C6x DSP. We have on our roadmap to add more functions for deep learning and appropriate framework support. On Jacinto family (specifically ADAS parts like TDA2/3x) we offer this as part of vision SDK. Please get in touch with TI field representative to get access to vision SDK. Thanks, With Regards, Pramod

Hi Pramod, Thanks a lot for the pointers. We will check out the VLIB, and get in touch with the local FAE at an appropriate juncture. Wish to see a lot more proofs of concepts to add confidence on TI DSPs though! :)

I wouldn't hold my breath ... the C66x architecture is quite old by now. It does not have enough processing power for most deep learning algorithms. -Robby

HI Robby, TI SOCs have hetrogenous processors (EVE and DSP) and multiple instances of those which gives a good horse power for many applications using deep learning technologies. Stay tuned to see some cool demos on this technology at CES - Jan 2017 @ TI booth Thanks, With Regards, Pramod

That's good to know. I'd be interested to seeing those demos. -Robby

Dear Champs, TIDL (TI deep learining library) was introduced in CES2017 (Youtube link below). Could you share more info about TIDL? Is there a landing web page for TIDL?

Hi Luke, We are planning to release it and you should see more documentation and information with that. The releases will be during 1Q and 2Q this year. Thanks, with Regards, Pramod

Hello Pramod, Is the TI Deep Learning library available for usage? I am planning to use this on J6 (DRA75x) EVM running Android. Can you please let me know if this is possible? From the video of TI demo at CES 2017, it seems that the demo was on TDA2 and not on J6 but from the spec of TDA2 it seems similar to J6. Regards, Pavan D

HI Pavan, On J6 we have 2xEVE and this demo was done using 4xEVE on TDA2x. You can run the demo on J6 with half the speed. Thanks, with Regards, Pramod

Ticket Name: TDA2SX: TDA2SXBU PMIC Selection

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi Expert, Could TDA2SXBU PMIC Select TPS659039-O9039A387? If TDA2SXBU PMIC could not select TPS659039-O9039A387,do you have any suggestions? Thanks Daniel

Hi Daniel, Sorry for the delay. Is this issue still open ? Regards Vineet

Hi Vineet Issue is still open. Could you help me? Thanks Daniel

Hi Daniel, Will take a look at this internally and get back. Regards Vineet

Vineet, We recommend the PMIC that is implemented on the TDA2 EVM. Regards, Kyle

Ticket Name: RTOS/TDA2-17: Crashing when using simple OpenCV functions

Part Number: TDA2-17 Tool/software: TI-RTOS Hello everyone! I am trying to use some OpenCV functions from the precompiled libraries on A15 provided with the Vision SDK, version 3.04. These functions work within the given alg-plugin examples, such as in opencvcanny. I can even modify these plugins with other OpenCV calls successfully, as long as I keep everything contained within the "cannyThreadFunc()" in alg_plugins/opencvcanny/canny.cpp However, as soon as I try to move the OpenCV code outside of this function, it crashes with output that looks like this: [HOST  ]     51.719971 s: Unhandled Exception:
[HOST  ]     51.720002 s: Exception occurred in ThreadType_Task
[HOST  ]     51.720002 s: Exception occured in A15 with exception type 18 
[HOST  ]     51.720002 s: handle: 0x848ab5b8.
[HOST  ]     51.720002 s: stack base: 0x848adb60.
[HOST  ]     51.720032 s: stack size: 0x100000.
[HOST  ]     51.720032 s: R0 = 0x00000000  R8  = 0x849ac670
[HOST  ]     51.720032 s: R1 = 0x00000001  R9  = 0x849adc5c
[HOST  ]     51.720063 s: R2 = 0x00000098  R10 = 0x849adc34
[HOST  ]     51.720063 s: R3 = 0x048c0010  R11 = 0x849ac53c
[HOST  ]     51.720063 s: R4 = 0x849ac6c8  R12 = 0x2000015f
[HOST  ]     51.720093 s: R5 = 0x849ac660  SP(R13) = 0x8409c430
[HOST  ]     51.720093 s: R6 = 0x849ac670  LR(R14) = 0x8a7350e4
[HOST  ]     51.720093 s: R7 = 0x3ff00000  PC(R15) = 0x8409c430
[HOST  ]     51.720093 s: PSR = 0x849adc5c
[HOST  ]     51.720124 s: DFSR = 0x00000206
[HOST  ]     51.720124 s: IFSR = 0x00000000
[HOST  ]     51.720124 s: DFAR = 0x00000010
[HOST  ]     51.720124 s: IFAR = 0x00000000
[HOST  ]     51.720154 s: Terminating Execution...
[HOST  ]     51.720154 s: 
[HOST  ]     51.720154 s:  ### XDC ASSERT - ERROR CALLBACK START ### 
[HOST  ]     51.720185 s: 
[HOST  ]     51.720185 s: E_dataAbort: pc = 0x8409c430, lr = 0x8a7350e4.
[HOST  ]     51.720215 s: 
[HOST  ]     51.720215 s:  ### XDC ASSERT - ERROR CALLBACK END ### 
 This particular output was caused by multiplying two cv::mat objects inside a .cpp function that was called directly from the "AlgorithmLink_xxxxProcess()" function of a custom-written plugin. Matrix addition and certain constructors were also demonstrated to fail in a similar manner. It seems that there are certain restrictions on how the precompiled OpenCV libraries should be used... or else they will crash the application. Does anyone know what exactly these restrictions are? Much appreciated, Ying

Update! It looks like the application is crashing because I am calling functions from two different threads. This explains why any links using OpenCV dedicate an entire, isolated thread to its use (see opencvcanny or opencvopencldilation, for example). Lesson learned: You cannot use two links that utilize OpenCV in the same chain. You will have to combine their functionality into a single link, or somehow funnel the entire chain's OpenCV usage into a single thread.

Hi Ying, Thanks for sharing your findings. Regards, Yordan

Ticket Name: TDA2EVM5777: Cannot see any output of semantic segmentation, trained based on the Caffe-Jacinto's Jsegnet

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi, After successful training and testing on the PC till the sparsification stage, I used the import tool to to generate the net and prm files of jsegnet. Converted the video as well which is also based on my previous experience of testing the demo version. However, when I run these files on the tda2, all I can see is the static output frame of my video which isn't moving at all. I didn't see any error while importation and execution, so I assume that there is no problem in the network. I used the semseg usecase with default settings to run my trained model and input video, however, my model is trained on two classes rather than four as I have only two objects. Things I noticed while execution: Cannot allocate the object for sync1,2,3 and algorithm 0,1,2,3,...7. Other than this, I cannot find any possible error. Another thing is that when I pause and resume my video it runs for that particular interval without any segmentation result otherwise it is stuck. Here is the log file.2330.log.txt. Kindly respond me as soon as possible. Thank you. With best regards, H.M. Owais

Hi, Please refer to below two e2e threads for training and running custom data set using semantic segmentation use case e2e.ti.com/.../660676 e2e.ti.com/.../794965 Thanks, Praveen

Hi Praveen, Thank you for your reply, however, I have already seen these threads and couldn't find any relevant solution after searching a lot on e2e threads. I am dealing with different problem. I can try to explain it again. 1. I have done successful training with my own dataset (not using cityscape). My dataset has only two objects which need pixel-wise classification. 2. I used caffe-jacinto to train and tested on the PC successfully. My test dataset shows output successfully on the PC. 3. I converted the sparsed model using the import tool and generated BIN files for parameter and network. The import tool showed successful importation and generation of files. 4. I have also converted the test video as per the given instructions. My test video works well with other models. 5. I am using the same usecase, semSeg given in the demo codes with all default settings to display the results. This is what I have done so far. Now here are my questions, 1. Why I can't see the output of my two objects? it just shows me the test video frame, nothing else. 2. Where I can find the network output in the tidl_algplugin.c? can you precisely tell me the function to display it?\ 3. I have also attached the log file in the above question, can you have a look at it and tell me where the problem is ? 4.. If there is any helpful document which contains all the information about tidl_algplugin.c. Kindly share it with me as well. Thank you. With best regards, H.M. Owais

Hi, From the log it seems sync link is dropping frame. Can you increase SYNC_THRESHOLD to 3000 is your semseg usecase. Regards, Anuj

Hi, Its been long since any update on this. I hope the issue is resolved, if not then please reply below or create anew thread for different issue. Regards, Anuj

Hi Anuj, Sorry for being late in replying the answer. The issue was with the input inData file. I resolved it back then. Thank you for your response. With best regards, H.M. Owais

Hi, You can mark any answer as it resolved your thread and close it. Regards, Anuj

Ticket Name: TDA4VM: How to dump Clock tree for CTT on TDA4VM

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Dear experts, Is there a tool to dump clock tree for CTT from TDA4VM? I am using PSDKRA 6.2. In TDA2 gen, we have "omapconf ctt dump". Thanks & Best Regards! ZM

Hello ZM, git.ti.com/.../ This is k3conf Tool. Similar to omapconf. Please follow the readme. k3conf dump clock Gives the dump of all the clocks this might not be exactly like omapconf but this is the closest you can get with that. Attaching the binary for your reference. Just copy that your file system and run the command: k3conf dump clock Note: Attachment is k3conf.txt just download it and rename it to k3confk3conf.zip Hope this thread can be resolved. Regards, Keerthy￼

Ticket Name: Linux/TDA2: sxgFrmcpy and Display buffer address issue.

Part Number: TDA2 Tool/software: Linux Hi Sir, I am using sgxFrameCopy as use-case to develop a function, HW is TDA2x CPU board + Vision Board + daughter board + OV1652x sensor and SDK is PROCESSOR_SDK_VISION_03_04_00_00 with TDA2XX_EVM_LINUX_ALL define. There are two issue that need your help. 1. When sgxFrmcpy() function gets capture buffer, it uses below function to transfer capture buffer into a texYuv value, “texYuv[0] = System_eglWindowGetTexYuv(&pObj->eglWindowObj, &texProp, pVideoCompositeFrame->dmaFd[0][0]”); I found “dmaFD[]” is not the image buffer point, how do I correspond the image buffer point by “dmaFd” ? Actually I don’t know what the “texYuv[ ]” and “dmaFd[ ]” are? And how the code uses “texYuv[ ]” and “dmaFD[ ]” to get the real image buffer? 2. I try to change some image data in sgxFrmCpy and then send the data to display buffer, I trace the link between sgxFrmcpy and Display, I am not sure which information structure is sent to next link for display recognize and which parameter is for point to display buffer? I think below function is for scaling image and describe image information, including the img buffer point, but I have no idea which parameter of structure records the img buffer point? “SgxRender1x1_renderFrame1x1(&pObj->render1x1Obj, pEglWindowObj, gTriangleVertices_toplefttop, texYuv[0]);” Thanks. Ranny.

Hi, dmaFd is internally mapped to video data in case of linux. Please look the below comments UInt32 dmaFd; /**< userspace handle to represent buffer For 4.4 kernel all buffer handled by Linux need to be as dmaFd. Each of the bios allocaed buffer needs to be mapped to a dmaFd */ Ipc links running on A15 will take care of mapping of dmaFd. Regards, Anuj

Ticket Name: RTOS/TDA2: Understanding of statistics shown by GRPX : CPU loads

Part Number: TDA2 Tool/software: TI-RTOS I have some queries regarding utilization of each processor/CPU in % given by statistics. 1. On what basis that % count is decided for a processor? 2. Except processing a frame , what else particular CPU do ( to increase % utilization )? 3. What is mean by each term, below highlighted part ? [IPU1-0] 67.555725 s: CPU [EVE1 ] Statistics, [IPU1-0] 67.555786 s: ************************* [IPU1-0] 67.555847 s: [IPU1-0] 67.555908 s: LOAD: CPU: 26.3% HWI: 1.5%, SWI:0.2%, Low Power: 63.5% [IPU1-0] 67.556091 s: [IPU1-0] 67.556152 s: LOAD: TSK: SYSTEM_TSK_MULTI_MBX: 24.4% [IPU1-0] 67.556243 s: LOAD: TSK: MISC : 0.2% [IPU1-0] 67.556335 s: Regards, Kajal

Hi Kajal, CPU load is decided on basis of time when CPU is processing data vs the idle time. Total CPU utilization can be increased by adding any extra processing that you might need for your use case. It can be as simple as a CPU memcpy. Total CPU utilization is sum of HWI+SWI+SYSTEM_TSK_MULTI_MBX+MISC. Low power percentage is amount of time a particular CPU spends in low power mode. Hope this clarifies. Regards, Rishabh

Thank you Rishabh for clear explanation. May I know meaning of HWI+SWI+SYSTEM_TSK_MULTI_MBX+MISC. Do we have any reference document for these terms? Regards, Kajal

Hi Kajal, You can find HWI and SWI in bios documentation (search in All Modules in cdoc). SYSTEM_TSK_MULTI_MBX is defined in links_common. You can search the code to how it is used by IPC. MISC are miscellaneous tasks. Regards, Rishabh

Hello Rishabh, In my 2nd query i.e 2. Except processing a frame , what else particular CPU do ( to increase % utilization )? I meant including processing a frame what else a processor do? so that it's utilization is increases. Regards, Kajal

Hi Kajal, You can start more tasks on a processor to increase the utilization. You need to keep in mind that power will increase with increase in CPU load. Hope this helps. Regards, Rishabh

Hi Rishabh, I mean in opposite way ( I don't want to increase utilization rather why it gets increase is my query). For Example. 1. capture -> alg1( EVE1) -> Display In this use case it is taking 20% EVE1 utilized . ---------------------- 2. Capture -> Dup Dup->alg1(EVE1)->Merge Dup->alg2(EVE2)->Merge->sync->Display In this use case it is taking 45% EVE1 utilized . ---------------------- I found difference in utilization( although both EVEs processing a frame, just chain structure is different). So my query is, except frame processing what else processor( EVE1 in above example) do? Hope this clarify my query. Regards, Kajal

Hi Kajal, You can print statistics using "p" while running both use cases and find the tasks that are using EVE1 and compare. Regards, Rishabh

Thank you for the information. Regards, Kajal

Hi Kajal, Closing the thread as issue has been resolved. Regards, Rishabh

Ticket Name: TDA2HF: About import tool sampleInData

Part Number: TDA2HF Hello， I have two questions about import configuration parameters: (1).does sampleInData support video input or multiple images ? (2).if sampleInData support,how to set and how to prepare the video and images? and other question about caffe-jacinto quantize test: I test the imagenet_jacintonet11v2_iter_160000.caffemodel and set quantize: true in deploy.prototxt, save the output of pool5, and then remove quantize: true only,save the output of pool5 again, the results are same."quantize: true" doesn't seem to work.So if quantize: true does work,What happens to the output? Thanks, chen poca

Hi Chen poca, 1. You can set "numSampleInData" variable in the import config file and set "numFrames" variable in the infer config file for running multiple images. 2. You can concatenate multiple images to prepare the multiple image input The test results with and without quantize are available here in "caffe_jacinto_models\trained\image_classification\imagenet_jacintonet11v2" folder in the github (https://github.com/tidsp/caffe-jacinto-models), please refer to "run.log" in "test_quantize" and "test" folders. Thanks, Praveen

hello, thank you for your replying. my reason to setting numSampleInData variable >1 is for import process not for inference.if numSampleInData>1,can I set sampleInData to multiple images?

Yes

so how to set multiple image to the sample InData ？using the txt file to list image path？or concatenate multiple images to one .y file？

Concatenate multiple images to one .y file

Sorry for the late reply and thank you for your answer.I have another question,if using multiple images to the sampleInData,would this improve the effect and generalization ability of the quantization?

No

Ticket Name: Linux/TDA2EVM5777: I want to connect Null link after TIOP link.

Part Number: TDA2EVM5777 Tool/software: Linux Hi, I'm testing the TIDL usecase in linux with changing the last two link(ObjectDraw, Display) with Null link. The null link just read meta data from TIOP link and do nothing. The usecase was executed but FPS was too slow in each link. Could you suggest any points what i missed? Regards, Yoo

Hi, Whats the FPS are you getting when you run without modifying the usecase? Can you share the usecase stats logs after running the usecase for 1 min. Regards, Anuj

Ticket Name: TDA2PXEVM: Is there a way to build yocto but not thud on TDA2Px-EVM to build python3 Tensorflow-lite

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello all, I Have TDA2Px-EVM board and I was able to build yocto file system on using this guide: http://software-dl.ti.com/processor-sdk-linux/esd/docs/06_00_00_07/linux/Overview_Building_the_SDK.html I was also able to customize the image as i have added some layers like meta-ros, meta-scipy and I was also able to create custom layer to install and build some libraries, packages and package groups. I was installing some python packages and the changes I made to the image allowed me to install most of the needed python3 packages using pip3. I am currently facing a problem in installing tensorflow or tensorflow-lite when I added meta-tensorflow-lite layer https://github.com/NobuoTsukamoto/meta-tensorflow-lite/ and appended to my image recipe IMAGE_INSTALL += " python3-tensorflow-lite " I have got "ERROR: Layer meta-tensorflow-lite is not compatible with the core layer which only supports these series: thud" So I am currently facing a problem as processor sdk 6.x are all based on thud and this distro is not supported in the tensorflow-lite meta layer and When I tried to build a different version of processor SDK there was a toolchain error "ERROR: Failed to parse external Linaro toolchain version from: gcc version 8.3.0 " as probably the other versions of processor SDK doesn't support "dra7xx-evm". My problem shortly is there any way to build yocto file system on TDA2Px-EVM based on another yocto distro rather than thud or is there a way to build and install python3 tensorflow or tensorflow-lite on TDA2Px-EVM using the built and working yocto with this version of processor SDK. Thanks in Advance. Best regards, Kirollos Henry

Hi Kirollos, Apologies for the delay in the response to this. Kirollos Henry said: is there any way to build yocto file system on TDA2Px-EVM based on another yocto distro rather than thud The short answer is no, thud is the last release with a completely validated offering with DRA7/TDA2. You will have to take care of the migration at your end. Kirollos Henry said: is there a way to build and install python3 tensorflow or tensorflow-lite on TDA2Px-EVM using the built and working yocto with this version of processor SDK. I dont think anyone in TI has spent time on this problem, therefore we are unable to provide you with any further instructions. Regards Karthik

Ticket Name: TDA2SX: The TDA2SX processor on MMWCAS-DSP-EVM does not enable the USB3.0 port

Part Number: TDA2SX Other Parts Discussed in Thread: MMWCAS-DSP-EVM, , TDA2, MMWCAS-RF-EVM, AM68, AM69 Hi, I am using the PROCESSOR-SDK-VISION Version: 03.08.00.00 to build a custom firmware for the MMWCAS-DSP-EVM. The goal is to use the USB3.0 available on the MMWCAS-DSP-EVM as shown in the figure below. The issue is the USB3.0 port seems not working. I compiled the PROCESSOR-SDK-RADAR, then the PROCESSOR-SDK-VISION, yet the USB3.0 is not enabled on both SDKs. Going more in details, I understand that the USB3.0 port can operate as OTG. I tried in both "gadget" and "host" mode, yet the port seems not functioning. Going through the design files, the port is powered from the TDA2SX processor as shown in the three below figures. The USB1_DRVBUS (AB10) pin on the TDA2 processor should be high to enable the TPS chip and power up the USB stick (gadget) on the USB3.0 port. Yet, when I probed the TDA_USB1_DRVBUS wire using a multi-meter on the board, the signal is low. I followed this thread which succeeded in connecting an external Hard drive to the TDA2x Demo board. Even after modifying the linux kernel using kernel_menuconfig to load USB related drivers on boot, it still does not work. I am wondering if the pin is faulty or disabled by design? If it is disabled, can you provide a way to modify the firmware to enable it. Thank you,

Hi, USB was not validated on this EVM and there is no plan to support it in SDK. Regards, Stanley

Hi, There is no plan to support USB on this EVM. Regards, Ajay

Hi, I understand it is not supported. Can you point out which is the closest evaluation board and SDK compatible with the MMWCAS-RF-EVM and has USB3.0 support? Based on this reply (Link) seems that all TDA2x boards have USB3.0 support enabled by default on the SDK. Does that mean that USB3.0 can be enabled from the SDK? Thank you,

Hi, USB support is available on DRA7x/TDA2x EVM. However, DRA7x/TDA2x device family is our previous generation device. Have you evaluated our current generation AM68/AM69 device family? I highly recommend you to consider the new device which has more active development/support. https://www.ti.com/product/AM68 Regards, Stanley

Ticket Name: RTOS: How EVE/DSP cores read the parameters of specific layers?

Tool/software: TI-RTOS Hi, I have a question about TIDL usecase. In TIDL OD, how eve/dsp cores read the parameters which are belonged to specific layers in SSD? I saw the usecase reads bin files which have information of Network architecture and real parameters in tidlODInit function. However, in AlgorithmLink_tidlProcess, which is a function that actually implements eve and dsp algorithms, i couldn't find the core verify each layer is designated to itself. Could you let me know where the source code implements that part? Thanks in advance. Regards, Yoo.

Hi Yoo, "LayergroupID" parameter in the import config decides which layer to run on EVE or DSP cores. Please check FAQ #21 and #22 in TIDeepLearningLibrary_UserGuide.pdf for more details on this. Thanks, Praveen

Hi, Thank you for reply. Yes, i already read that section. However, what I would like to know is how to pass each layer set in import config to eve and dsp when real TIDL OD usecase is running. In source code, there is AlgorithmLink_tidlProcess function in tidlLink_algPlugin.c file. However, i didn't find where to check each layer is set to be calculated on DSP/EVE. Could you let me know how to know DSP/EVE each layer is responsible for themselves? Thank you. Regards, Yoo.

Hi, In AlgorithmLink_tidlProcess, we check the input buffer type and depending on that we decide its running on DSp or EVE. If buftype is video frame then it is running on EVE and if its meta buffer then it is running on DSP. Regards, Anuj

Hi, If buffer type decides whether each layer is running on DSP or EVE, what LayerGroupID is for? Could you explain what is meta buffer? I understood the video buffer is for each frame. Then meta buffer is just for contains information of frame? So far as I understand it, check each layer group id in the AlgorithmLink_tidlCreate function. At this time, if the result of the layer assigned to eve is input to the next layer assigned to dsp, or vice versa, an input buffer and an output buffer are generated. Then, in AlgorithmLink_tidlProcess, it gets the input buffers from previous link and put them into temporary queue. The input buffers may be the input frame that is preprocessed by A15. And it prepares output buffers corresponding to input buffers. After that, it checks whether the input buffer is meta data or video frame. (which link sends meta data?) And algProcess executed using inBufs, outBufs, etc. After algProcess, it puts out buffer to queue and notify to previous link and release input buffers. Could you please let me know if i understand code incorrectly? In addition, if i understand correctly, i think it doesn't match with the flow of TIDL OD chains below image. (Maybe, i missed some point) Thanks for your reply. Regards, Yoo.

Hi, Meta frame is a kind of buffer holder in VSDK which contains meta information. We have different kind of buffer holder, please check below file. vision_sdk\links_fw\include\link_api\system_buffer.h TIDL link running on eve gives meta buffer as output. Regards, Anuj

Hi, Its been long since any update on this thread. I hope the issue is resolved. If not then please reply below or create a new thread for different issue. Regards, Anuj

Ticket Name: TDA2: Can H.264 encoding achievable purely in hardware using IVA HD Co-Processor?

Part Number: TDA2 In TDA2x Superset, can H.264 encoding achievable purely in hardware using IVA HD Co-Processor? Regards, Amer

Hi Amer, it can not encode directly, you need separate SW encoder. Regards, Yordan

Ticket Name: TDA2: MPU system secure state switch

Part Number: TDA2 Hi, ROM code provides some service for user by Secure Monitor Call. So is ROM code responsible for setting Monitor vector table? Can user redirect Monitro vector table? And it seems that ROM code doesn't provide a service to switch MPU to non-secure state, so how can I do this? Thanks and regards.

Hi, For security features please contact your sales representative. We cannot discuss them in a public forum. Best regards, Stan

Ticket Name: Linux/TDA2: TDA2xx Run in mnt mode， how to update the firmware

Part Number: TDA2 Tool/software: Linux I run the apps.out by mount my virtual machine path to my board，and my Startup script is: ifconfig eth0 172.17.123.117 netmask 255.255.224.0 mount -t nfs -o nolock,nfsvers=3,vers=3 172.17.123.14:/home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/ti_components/os_tools/linux/targetfs /mnt cd /mnt/opt/vision_sdk/ ./load_ocl_kos.sh source ./vision_sdk_load.sh ./apps.out and my SD card uenv.txt file is fdtfile=dra7-evm-infoadas.dtb args_mmc=part uuid mmc 0:2 uuid; setenv bootargs "console=ttyO0,115200n8 vram=16M root=PARTUUID=${uuid} rw rootwait ip=none mem=1024M" But Only usecase level changes can be displayed in this way. When I modify the file under the path \vision_sdk\apps\src\rtos\alg_plugins，My changes don't work. E.g I added the print does not come out。 But I put the folder under the path \ti_components\os_tools\linux\targetfs copy to the path of rootfs in SD card，My plus print can print it out. It seems that something compiled under alg_plugins is not mounted， or when the system is running, it didn't go to my mount path to find firware. I want that what I am modifying under the path can take effect by means of mounting. Because it takes too long to copy the targets folder to SD card every time. How should I do?

Please use nfs boot mode

Hi, I have changed to nfs mode ， my uenv.txt file is： fdtfile=dra7-evm-infoadas.dtb args_mmc=setenv bootargs 'console=ttyO0,115200n8 vram=16M root=/dev/nfs rw nfsroot=172.17.218.38:/home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/ti_components/os_tools/linux/targetfs rootwait ip=dhcp mem=1024M' But in this mode i cannot log in the system， the info is ： | _ |__ __ __ _ | |__ __ |_|__ __| |_ | | | .'| . | . | | | | . | | | -_| | | |__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_| |___| |___| Arago Project http://arago-project.org dra7xx-evm ttyS0 Arago 2016.12 dra7xx-evm ttyS0 dra7xx-evm login: root Login incorrect dra7xx-evm login: it report Login incorrect. Regards， Xie Baojian

when you created the file system you have given full permission to the files within the filesystem . You need to give permission to targetfs folder alone. 2.4.2.1.4 Download and untar file system Download Linux file system tisdk-rootfs-image-dra7xx-evm_vsdk_3_4.tar.xz, from ti.com - http://softwaredl. ti.com/processor-sdk-vision/esd/TDAx/vision-sdk/latest/index_FDS.html And keep under following directory $INSTALL_DIR/ti_components/os_tools/linux/targetfs Untar file system $> bash $> export INSTALL_DIR=<installation_directory_absolute_path> $> cd $INSTALL_DIR/ti_components/os_tools/linux/targetfs $> chmod 777 ../targetfs NOTE: Only targetfs folder needs to have full permission not the files within $> tar xf tisdk-rootfs-image-dra7xx-evm_vsdk_3_4.tar.xz $> exit Regards Chetan.M

Hello , Any updates on this thread Regards Chetan M

Hi Chetan M, I am sure that i have done the 2.4.2.1.4 Download and untar file system， and have chmod 777 ../targetfs. and i have done env default -fa saveenv in uboot stage But it still cannot log in use root. Is it logged in with another account in the mnt mode? Regards, Xie Baojian

No , This issue is seen if there are permission mismatch , Please retry with a new filesystem folder Regards Chetan.M

Ticket Name: TDA4VM: porting hardware surround view interface to app_srv_camera demo display unexpect

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 porting hardware surround view interface to app_srv_camera demo display unexpect Dear expert, I porting my surround view interface into app_srv_camera demo, add my init interface to tivxGlSrvCreate, which need 3 paramters (display, surface, context), replace render_renderFrame with my UpdataApp interface for doing surround view function, in my interface, there are create serval framebuffers use glGenFramebuffer, and when the app run, call glBindFramebuffer bind texture to each framebuffer, then glBindFramebuffer (GL_FRAMEBUFFER, 0) render all the contents to the window provided framebuffer, now on tda4vm linux sdk, because the surface is null, I don't know where the display content store and how to get it when do glBindFramebuffer (GL_FRAMEBUFFER, 0) . In tivxGlSrvProcess, I found appEglBindFramebuffer call glBindFramebuffer bind the display buffer , so I modify my UpdataApp interface , delete all glBindFramebuffer code line, after do that I can see one part of my materials dispaly on screen . my question: 1) if tda4vm can create surface for render, how to do it, I try to call eglCreatePbufferSurface to create it , but it failed 2) if can't create surface, how to modify my interface for dispaly all the materials or how to get the content buffer after render finish. sdk vision: 07_03_00_07 OS: Linux Thanks!

Hello, In case of TI's TDA4 surround view implementation, the display is controlled using R5 and the OpenVX display node abstracts this out. Look at vision_apps/utils/opengl/src/a72/app_gl_egl_utils_linux.c. There is a function to create render surface/texture from a pre-allocated dmabuf - appEglWindowCreateIMG. This function basically takes a dmabuf fd and creates an EGL Image that can be rendered to. This is used as a frame buffer in appEglBindFrameBuffer (in the same file). You can follow the same procedure. What are you trying to do in your use case? Do you need to send your GPU rendered buffer to R5 display? You can also look at a simpler example - vision_apps/apps/basic_demos/app_linux_arm_opengl_mosaic Regards Hemant

Thanks！ Yes， I need to send my GPU rendered buffer to R5 dispaly, but I don't know how to do it, I try to use glReadPixel read my gpu output to output_target_ptr, but it failed and return 0x506 error report. As you discribe I follow app_gl_egl_utils_linux.c , use the same procedure, in my own case which run on tda2 before, which need input 4 camera capture frames and load some other materials, then do surround view function and display the output render buffer.

hi， expert As my described， my function interface have many materials and textures need scale/render to one surface, It's hard for me modify the process flow, so I want to create a surface with pbuffer which can pass to function interface or use a opengl interface like glReadPixel copy the output buffer to display buffer. This problem bothered me for a long time, I need you help. Thanks!

Hello, glReadPixels should work - not sure why you are seeing that error. Can you please review all the arguments and make sure they are okay? But please know that glReadPixels may have a performance hit - but should certainly get you the required data. As I mentioned in my previous post, app_linux_arm_opengl_mosaic shows how to handle GPU to display. Regards Hemant

Thanks for your reply! I am already reference the app_linux_arm_opengl_mosaic demo, I modified my program, replace the function code call glBindFramebuffer (GL_FRAMEBUFFER, 0) to glBindFramebuffer (GL_FRAMEBUFFER, disp_fb), then call glFramebufferTexture2D bind the texture need render to current framebuffer, but there are some errors arised， This is the log ### glCheckFramebufferStatus not completed! status 36054 GL: after eglSwapBuffers() glError (0x506) If I deleted glFramebufferTexture2D , no error log print out, but there is also no display. If I keep call glBindFramebuffer (GL_FRAMEBUFFER, 0) in my app, the glCheckFramebufferStatus also report error, is't means there is no default framebuffer ?

hello: I did some test of that , when glBindFramebuffer(GL_FRAMEBUFFER, 0) glCheckFramebufferStatus return 0x8219 which GL_FRAMEBUFFER_UNDEFINED, so EGL_NO_SURFACE which means no default framebuffer, so I call glBindFramebuffer (GL_FRAMEBUFFER, fboid) and glFramebufferTexture2D , fixed some bugs of my app, glCheckFramebufferStatus return ok, and I can see some color output to my screen（but not correct）, I think this is because my default render flow not suitable the new draw flow。 I know on tda4vm QNX can create a surface with buffer, which can pass to my app, so there is't need modify the render flow. so my question is can I create a surface with a buffer on linux?

resolved! please close it!

Ticket Name: TIDL trace fixed point converted to floating point

Dear TIDL expert In order to check TIDL SSD model convert result, I try to convert fixed point into floating point, as following, I try to convert it based on CVPR workshop paper from Ti company I found I get no reasonale result, it's large floating point number and no normal. When I check TIDeepLearningLibrary_UserGuide.pdf, I find some useful information as following, And I also see log from model convert tools as following, Can I provide me with specific implementation plan to convert from fixed point to floating point? Thank you very much !

Hi, You no need to convert fixed point to floating point as we dump final output in the float mode for SSD, so you will get directly final float output in "stats_tool_out.bin" file. You just need to open and read the detection's from this file. You can refer to "markbox.c" file in the below thread to know how to read the detection's from this "stats_tool_out.bin" file. https://e2e.ti.com/support/processors/f/processors-forum/679186/tda2-tidl-1-1-ssd-model-test-application-output/2502331#2502331 Thanks, Praveen

Ticket Name: Linux/TDA2: some question about add some code in origin sample code

Part Number: TDA2 Tool/software: Linux Hi, i want to add some code with own head & c file. I include head file in origin code and add the file path in the NAKEFILE.MK, then make them i got "undefined reference to 'function_name' ". Should i need modify other files to make sure compiler link correctly? thanks, Chen-Wei

Hi Chen-Wei , Which location are you adding . Have you verified if the file is compiling after addition in the make file . Share more details so that we can help you better. Regards Chetan.M

Hi Chetan, My sample code is opencvcanny. Put my own code (head file and source code)in the folder of canny and add the path to MAKEFILE.MK after include just like " INCLUDE+= -I$(ipc_PATH)/hlos_common/include -I$(ipc_PATH)/packages -I$(kernel_PATH)/include/generated/uapi $(OSA_INC) -I$(ipc_PATH)/linux/include -I$($(MAKEAPPNAME)_PATH) -I$(OPENCV_INCLUDE) -I$(vision_sdk_PATH)/apps/src/hlos/adas/src/alg_plugins/opencvcanny/include " i checked my code is compiled after addition in the make file, but can't link to my function. Thanks, Chen-Wei

Hi Chen-Wei, All OPENCV_LIBS are linked in "common_footer_a15.mk" file under vision_sdk\build\hlos\makerules\linux folder Regards Surya

Hi, Surya Thanks for told me OPENCV_LIBS are linked in where, but in my situation is i want add some own function in the sample code of canny. It means that we want do some modify in the sample code(call other sub function in a new head file, which is created by me). which files should i need to modify to avoid the error i meet ? thanks, Chen-Wei

Chen Wei , Do you mean canny algorithm .. ? Or canny alg plugin. can you please send the entire error Regards Chetan.M

Hi Chetan, i want to add some code to the origin code in canny usecase, origin modify #include "iCanny.h" #include "iCanny.h" #include "opencv2/imgproc.hpp" #include "opencv2/imgproc.hpp" #include "/tda/vision_sdk/apps/src/hlos/adas/src/alg_plugins /opencvcanny/include/hllow_world.h" void iCanny(IplImage *inputImage, IplImage *outputImage) void iCanny(IplImage *inputImage, IplImage *outputImage) { { UInt32 lowThresh; UInt32 lowThresh; UInt32 highThresh; UInt32 highThresh; cv::Mat inputMat = cv::cvarrToMat(inputImage, false); cv::Mat inputMat = cv::cvarrToMat(inputImage, false); cv::Mat outputMat = cv::cvarrToMat(outputImage, false); cv::Mat outputMat = cv::cvarrToMat(outputImage, false); lowThresh = 30; lowThresh = 30; highThresh = lowThresh * 3; highThresh = lowThresh * 3; cv::Canny(inputMat, outputMat, lowThresh, highThresh, 3); cv::Canny(inputMat, outputMat, lowThresh, highThresh, 3); hw(); } } and entire error is : /tda/vision_sdk/binaries/apps/tda2xx_evm_linux_opencx/lib/tda2xx-evm/a15_0/release/apps.a(canny.o): In function `iCanny': canny.cpp:(.text+0x5e): undefined reference to `hw()' Thanks, Chen-Wei

Hi , Where is the function hw() Regards Chetan.M

Hi Chetan, the function hw() is in /tda/vision_sdk/apps/src/hlos/adas/src/alg_plugins/opencvcanny/include/hllow_world.h and i also add " /tda/vision_sdk/apps/src/hlos/adas/src/alg_plugins/opencvcanny/include/" in MAKEFILE.MK thanks, Chen-Wei

where is it implemented .? Its present in which .a lib . Regards Chetan.M

Hi Chetan, this is created by myself. Should i need to build them as a .a or .lib file and add them in MAKEFILE.MK? Thanks, Chen-Wei

Chen-Wei sorry for repeated asking same question , where is the hw() declared and where is it defined . ? Regards Chetan.M

Hi Chetan, i declared it in /tda/vision_sdk/apps/src/hlos/adas/src/alg_plugins/opencvcanny/include/hllow_world.h and defined it in /tda/vision_sdk/apps/src/hlos/adas/src/alg_plugins/opencvcanny/hllow_world.c Thanks, Chen-Wei

Hi Chen-Wei, I see a C and CPP file combination , Have you taken care of extern c and other parameters in your hllow_world files .? Try google search and see if some thing missed. stackoverflow.com/.../call-a-c-function-from-c-code Regards Chetan.M

Hi, Chetan Thanks for your suggest, and i add the extern C in my code. I think maybe i need to compile them first, just like the website you gave build my code into a .o file and link them, or maybe not. If i build my code, i don't know the path of .o file should add in which file to make them linked. if i don't build them first, i still got the same error Should i need modify any files? Thanks, Chen-Wei

Please try a clean build

Ticket Name: TDA2: VisionSDK_UserGuide_TDA2px help

Part Number: TDA2 I am following the VisionSDK_UserGuide_TDA2px.pdf and have difficulties building the application. I have downloaded CCS, A15, and the vision SDK and set up my environmental variable path to C:\ti\ti_components\os_tools\windows\xdctools_3_32_01_22_core. I am trying to follow step 4a. however I get the message "gmake: *** No rule to make target `depend'. Stop." I also don't see a "binaries" folder created in the vision_sdk file. What should I do ?

From which folder you are sending this command? it should be done from vision_sdk\build folder.. Rgds, Brijesh

I sent it from the vision_sdk folder. In the user guide, it just says to do it from the vision_sdk directory. Is my environment variables set up correctly?

Hi Sally, The environment variables look ok. You need to go to the path vision_sdk\build from windows command prompt and then invoke "gmake -s depend" command. Usually this path is C:\PROCESSOR_SDK_VISION_03_03_00_00\vision_sdk\build. Regards, Rishabh

Hi Rishabh, I am having a different error when I try to use the gmake command.

Hi Sally, this happens when there is mismatch between installation path of A15 compiler and variable CODEGEN_PATH_A15 from "vision_sdk/build/tools_path.mk". You can rename the compiler path to "<install dir>/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3" (by default when installed A15 compiler directory is named something like "4_9-2015q3") or modify the value of CODEGEN_PATH_A15 to match your path. Please check those threads for the same issue: e2e.ti.com/.../703809 e2e.ti.com/.../2545614 Regards, Yordan

Hi Sally, It looks like windows limitation only (even though file present in installation path but still give an error file not found in the specified path) Refer below thread e2e.ti.com/.../2601535 Regards Surya

Hi Sally, I am closing this thread as the issue is resolved. Regards, Rishabh

Ticket Name: TDA2EVM5777: Adaboost object detection training tool

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi, everyone I saw Adaboost object detection training tool (Matlab based) is publicly available at https://github.com/tidsp/acf-jacinto And I download the Adaboost object detection training tool I have some questions 1. the training data's format should be .vbb .mp4 .seq ? Is .jpeg ( picture's format ) ok ? 2. What kind of file will be created if I use training tool to train the model ? (.xml or .bin or .....?) 3. If I want to use this file in TDA2 , where should I put ? Thanks Regards, Andy

Hi Andy, I have forwarded your question to an expert for comment. Regards, Yordan

Hi Yordan, Is there any reply? Thanks! Regards, Andy

You need to provide both images and annotations. 1. The tool currently takes in .seq or .mp4 files for images. (It should be possible to modify the code to be able to specify a folder containing images instead of .seq or .mp4) 2. Annotation format supported is .vbb You can fiund lots of .seq files (with the corresponding .vbb annotations) here. http://www.vision.caltech.edu/Image_Datasets/CaltechPedestrians/ An annotations/labelling code (matlab based) is also available in the above link. An enhanced version of the same labeling tool (supporting annotation of .mp4 files) is also provided here: https://github.com/tidsp/acf-jacinto/blob/master/vbb/vbbLabeler.m Note - you don't have to annotate all the frames. acf-jacinto is intelligent to understand which are the annotated frames and use only those for training. This feature is especially useful when dealing with .mp4 videos. After you do the training a .descriptor file will be written out. You can use this file in TDA2 VisionSDK Object Detection module. You can get more details in the documentation for the Object Detection module. Best regards,

HI Andy, Manu answered q1 and q2. Regarding your 3rd question, there is a utility to convert from the descriptor format to a a binary file which can be understand by OD module, The utility is unfortunately not packaged as part of object detection module, but let me see how can I get you access to the utility. Thanks, with Regards, Pramod

Ticket Name: TDA2E: Error: Module ti.sysbios.knl.Task does not exist in the application's configuration - ROV

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Hi, I am trying to debug an application in our custom board wich uses a TDA2, I use CCS only for debug, my source code is build using our tools, these are the steps I perform: debugger = Blackhawk XDS560 v2 System Trace 1.- I create a new target configuration choosing the debugger and platform, then launch that configuration 2.-I load the symbols (vision_sdk_ipu1_0_release.xem4) only for 1 core, IPU 1_0 in this case, then I connect the target the target is running 3.- then I open ROV but I get this error how could I solve this?, thanks

Ticket Name: TDA2: Are there any step by step tutorials regarding how to use TI's deep learning Libs

Part Number: TDA2 Hi, I'm new in TDA2. So far, I'd like to use TI's deep learning Libs to fulfil some applications. Are there any step by step tutorials regarding how to use this Libs or any suggestions? Thanks.

Hi, Refer below User guides 1. <install_dir>\ti_components\algorithms\REL.TIDL.01.01.01.00\modules\ti_dl\docs\TIDeepLearningLibrary_UserGuide.pdf 2. <install_dir>\vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_TI_DeepLearning.pdf Regards Surya

Hi, Referring User guides, are you able to build & integrate TIDL libs to your application ? Can We close this thread ? Regards Surya

Yes, thanks.

Ticket Name: RTOS/TDA2: DCAN2 external loopback test mode stuck at Utils_dcanWaitForTxComplete()

Part Number: TDA2 Tool/software: TI-RTOS Hi, I have the same problem! It stuck at Utils_dcanWaitForTxComplete(). please help to give me some advisement Thanks~~

Hi, Have you tried all the things suggested in above e2e thread? If yes and still facing same issue, can you take a dump of DCAN2 registers and DCAN2 message RAM? Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi, I found the problem. Some default usecase would use the same pin and would modify pinmux after mine. Thanks~

Ticket Name: TDA2: TIDL Host emulation tool convolution output issues

Part Number: TDA2 Issue with the convolutional output in the function : TIDL_refConv2d_i8u_032s_cn in tidl_conv2d_base.c First, the test setup: A simple convolutional network with 3x3 kernel and bias with 2 output channels. The first kernel has all zeros and the second kernel has all ones. Bias for first channel is 1 and second channel is 2. Now all the variables involved: input raw rgb = 255 (all 1s) inQuantFactor = 65280 weightsQ = 65536 biasQ = 4194304 biasQFact = 255 rgb size input = 3x3x3 num of output channels = 2 In foating point: input = 1.0 weights = [0, 1] (1st kernel all weights are zero, and second kernel all weights are 1) bias = [ 1, 2] The convolved output of the first channel should be 1. Just bias, because all weights are zero. The convolved output of the second channel should be : 1.0 * (3x3x3) *1 + 2 = 29. Ti fixed point: weights having values[0,1] becomes approximately: [0,1]*weightsQ/255 = [0, 255]. biases [1, 2] becomes approximately: [1, 2]*biasQ/255 = [16384,32767]. Now checking the convolution in TIDL_refConv2d_i8u_032s_cn function: There, pInChannel contains inputs which is uint8, and all the values are 255. Bias is multiplied by the biasQFact (255). I understand this is because of the inQuantFactor, and the bias needs to be scaled. convolution happens as: input * weights + bias*biasQFact for first channel, output is = bias*biasQFact = 4177920 for second channel: 255* (3*3*3)*255 + 32767*255 = 10111260 So floating point 1 is represented as 4177920 and 29 is represented as 10111260 which is wrong. Since the bias and weights are not represented by the same Q factor, the output will match only when the input also has a QFactor, With inout Q factor, second channel should be: 255*64 * (3*3*3)*255 + 32767*255 = 120718785, which should be the output. What am i missing here? I have attached the model and inputs to reproduce this problem. ti.zip

Hi Vijay, Please refer to below e2e thread, where we had one simple cifar net example to understand the tidl layers. I would recommend to start with this to better understand the input,weights and output Q formats. Then on top of it you try your experiments to get the better results. e2e.ti.com/.../689876 Thanks, Praveen

Hi Praveen, The above example is created in such a way that one can figure out what the issue is without doing into the code to debug. Anyway, I went and fixed the TIDL_importQuantLayerParams function in tidl_tfimport.cpp to make the above toy example work. The issue arises when the min - max range of weights and bias are not same. By the way, the cifar net example also didnt match (TIDL .01.01). I loaded the model shared in the above link and obtained outputs from each of the layers to compare with the host emulation output. Outputs doesnt match. I have attached all the tools required to reproduce the issue, in case you guys want to try it. tidl_keras_example.zip

Hi Vijay, Thanks for pointing this. I am closing this thread as you could fix the issue and you can feel free to open this thread or create a new thread if you face any issues. Regards, Praveen

Ticket Name: TDA2: DDR address signal swapping rules

Part Number: TDA2 Hello TDA2 support DDR DQ pin swap for better PCB routing, But the address also can be swap? What is swap rule? Thank you

Hi, Address pins cannot be swapped because they are used to program the DDR Mode Registers. Only data pins can be swapped and they can only be swapped within a byte. As an example, DQ0 could be swapped with any of the pins DQ1 - DQ7. Best regards, Kevin

Ticket Name: RTOS/TDA2: What is the result of vector compare?

Part Number: TDA2 Tool/software: TI-RTOS Hi, I want to check what is the output when I compare two vectors. For example, if I set vector a = [0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7]; vector b = [0xfff1, 0xff01, 0xff02, 0xffff, 0xff01, 0xff02, 0xffff, 0xffff ], what is the result c = a > b ? If it is [0, 1, 1,0, 1, 1, 0, 0 ] ? Thanks a lot! BRs Yang Derek

Hi Derek, Comparison operation does an element wise comparison of all the 8 elements of the vectors and returns a vector holding the comparison for each elements of the vector. Regards, Anshu

Ticket Name: TDA2E: TDA2 modify memory map

Part Number: TDA2E Dear experts, As they DSP&EVE core not used, so our customer want modify TDA2E memory map to increase A15 DDR space, but it failed. could you please help solve this problem? they have proposed a ticket on E2E show as blew:TDA2E: 【TDA2XX】Remove DSP and EVE to increase A15 Linux memory space - Processors forum - Processors - TI E2E support forums

Please refer to below application note for memory map customization. ~/vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_UserGuide_MemoryMap.pdf

Ticket Name: TI-RTOS-PROC: Can I use the synchronization modules from the differents cores of a SMP application?

Part Number: TI-RTOS-PROC Other Parts Discussed in Thread: SYSBIOS, TDA2 Hi, lets suppose we have TI RTOS running an A53 with 4 cores, the synchronization modules you provide have effect over all the cores, for example, a mutex used in the task 1 running in the core 1 could block the task 2 running in the core 2? the doubt is because of this: "Mailboxes can be used to pass buffers from one task to another on the same processor." only in the mailboxes you said this, the other modules does not mention this, and I don´t know what do you understand for processor, for example, in a cluster of an A53 of 4 cores someone could say that we have 4 processors A53_0, A53_1, etc, do you call processor to the cluster of cores or to each core?

Hi Jairo, What SDK are you using and what SoC are you talking about? The references you used are from SYS/BIOS or TI-RTOS. The ti.sysbios.knl.Mailbox primarily provides a queueing functionality of messages with capabilities to wake-up another thread. The context obviously is all within the same RTOS. So, if you are running different TI RTOS instances on each of the above 4 cores, then this really can't be used. If you are running a single SMP-version of the RTOS, you can use the above. In anycase, we no longer support the TI-RTOS or any other RTOS on A72 cores in the SDKs (8.x for sure, 7.3 SDK may have limited support). regards Suman

Hi, a TDA2 and Processor SDK-Vision

Please refer to below link regarding SMP support in TI-RTOS. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/946557/faq-where-can-i-find-details-on-smp-with-sys-bios

Ticket Name: [RadarSDK] Break point for Radar processing data layout

Hi Expert, Radar proceesing data flow is described in "Appendix D: Radar Processing Data Flow" in EVE_Applets_UserGuide.pdf. Each Data layout of Radar processing is shown in following Figures. Figure 3: Output of ARxx sensor Figure 4: Output of Range FFT/Input to Doppler FFT Figure 5: Output of Doppler FFT Figure 6: Antenna Data out after Peak Detection Figure 7: CFAR CA Detection My customer wants to confirm each data above in DDR when running Radar SDK usecase with CCS. Can you please tell me the line number & file name to be set as break point and buffer name (structs and variables) to look at each DDR data in CCS memory window ? Data Layout Buffer name Break point (Line number) Filename ARxx sensor output Range-FFT output Doppler-FFT output Peak Detection output CFAR CA output RadarSDK : Processor SDK Radar 3.6 Usecase : "3: Radar (Single AR1243) Capture + Radar Object Detect (EVE1) + Display (TDA3xx Only)" Best regards, Saito

Hi, I am forwarding this question to a team member in the Automotive Processors group. Thank you, -Randy

ARxx sensor output : Function: AlgorithmFxn_RadarFftProcess Address: inBufAddr File: vision_sdk\apps\src\rtos\radar\src\alg_plugins\alg_fxns\radarfft2\radarFft2.c Range-FFT output: Function: AlgorithmFxn_RadarFftProcess Address: pObj->intermediateBuf File: vision_sdk\apps\src\rtos\radar\src\alg_plugins\alg_fxns\radarfft2\radarFft2.c Doppler-FFT output: Function: AlgorithmFxn_RadarFftProcess Address: outBufAddr and (AlgorithmFxn_RadarFftBuffDescriptor *) metaDataBuffAddr File: vision_sdk\apps\src\rtos\radar\src\alg_plugins\alg_fxns\radarfft2\radarFft2.c Peak Detection output and CFAR CA output are the same: Function: AlgorithmFxn_RadarPkDetectProcess File: vision_sdk\apps\src\rtos\radar\src\alg_plugins\alg_fxns\radarpeakdetect\radarPkDetect.c Address: outBuf Beam form Output: File: vision_sdk\apps\src\rtos\radar\src\alg_plugins\alg_fxns\radarbeamform\radarBeamForm.c Function: AlgorithmFxn_RadarBeamFormProcess Address: outBuf Thanks and Regards, Piyali Data LayoutBuffer nameBreak point (Line number)FilenameARxx sensor outputRange-FFT outputDoppler-FFT outputPeak Detection outputCFAR CA output

Ticket Name: TDA2EVM5777: Binaries directory for running TIDL demo semantic segmentation

Part Number: TDA2EVM5777 Hi Team, Good day! I am posting this in behalf of the customer. Could you please help. As described in the following video for TDA2x-EVM training.ti.com/tda2-evm-series-part-3-0 For illustration of TIDL demo using semantic segmentation, I am unable to find the binaries directory that contains DLNet.bin,DLPRM.bin, Indata, and In header files defined in it. Please share the link for the same, on an urgent basis. Thank you for your support. Best regards, Jonathan

Hi, Myself Nikunj. I only posted this query. Request the team to share the zip folder for all the files required to run TIDL demo as illustrated in TDA2x-EVM tutorial,using Semantic Segmentation on TDA2x-EVM board.

Ticket Name: TDA4VM: How to modify Encode to support 2560x1920 resolution video coding?

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi TI, Is there any way to configure Encode to support the encoding of 2560x1920 resolution video? (We've implemented it on TDA2) According to the user guaid of Encode, the upper limit of the resolution supported by Encode is 2048x2048. Could you please give me some advice on how to expand this restriction? Thanks & Regards Damon

Hi Damon, which sdk release are you using? As far as i remember, the max resolution tested is 1080p (1920x1080).. Beyond this resolution, it is not validated.. Regards, Brijesh

Hi Brijesh, My sdk is 07_03. I'm sorry I was wrong about the max resolution stated in user guaid。 It is indeed 1920x1080 However, according to the log error message and the settings in the code, it seems that the max resolution is 2048x2048(this may be the case of low frame rate?) But what I am most concerned about is whether we can make Encode support 2560x1920 through some special modification? Although it may be necessary to sacrifice a little frame rate. Regards, Damon

Hi Damon, As i said, we have not really tested more than 1920 frame width. This may also changes in the OpenVX/Vision_apps to provide memory, in addition to encoder support.. Regards, Brijesh

Hi, On latest SDK 07_ 03_ 00_ 07, it is tested for resolutions upto 1920x1080. There is an example standalone test-application inside SDK (ti-processor-sdk-rtos-j721e-evm-07_03_00_07/video_codec/examples/apps/encoder/app_encoder_test.c) You can refer to code with macro "TWO_SLICE_ENCODING". That might help you try encoder higher resolutions with multi slice enabled. You can try adapting those changes in your use case. Again, only the multi slice functionality was validated here and not the higher resolutions beyond 1920x1080.

Hi, Can we close this if the answer has resolved the query?

Ticket Name: RTOS/TDA2: modifying demo usecase of visionSDK (ver 3.3)

Part Number: TDA2 Tool/software: TI-RTOS Hi, I'm trying to implement my application into the TDA2x by using demo application Since my application uses openCV, I will use vip_single_cam_opencvopencldilation usecase. When using demo application, what variables or structure and which function should I refer ? - I want to crop the input image frame - I want to apply my image processing algorithm to the cropped image - I want to display the result image frame I tried it for a week........ but I failed ...... please help me

Hi please note that OpenCV in Vision SDK is a preliminary release with limited features and testing (Alpha Quality). It does not have the functions/features you are looking for. So I suggest you to use native VSDK links and chain architecture and not OpenCV . All the features you listed above can be supported with native VSDK links and chain architecture regards, Shiju

Ticket Name: TDA2HV: ISO21434 Compliance with TDA2 family

Part Number: TDA2HV Hello, Can you provide information about the SoC capabilities (accelerated hardware for example) for being compliance with ISO 21434? Can you provide information about this cybersecurity manual for SoC (like safety manual for iso26262)? Best regards, Andrés

Hi Andres, TDA2x does have an HS variant with security and crypto features which are covered by the Security(SPRUHS7) and Cryptographic(SPRUHS8) addendums. We will need to work offline with you for access to these documents and further discussion on IOS21434. Regards, kb

Ticket Name: TI-RTOS-PROC: Event module - what does "Only a single Task can pend on an Event object at a time." means?

Part Number: TI-RTOS-PROC Other Parts Discussed in Thread: TDA2, SYSBIOS Hi, does this means that two tasks can´t wait for the same event? Thanks

Hi Jairo, Can you please share more details like which device and which SDK you are using? Regards, Parth

It is design by contract. Please refer to SYSBIOS API reference guide available under docs/ folder in SYSBIOS.

"Unlike semaphores, Only a single Task can pend on an Event object", could you explain this please?

The API is designed that way. If that doesn't fit your need, please use some other method. In our experience, Semaphore should serve most of the use cases and is more widely used.

Ticket Name: TDA2: Termination Resistors on PCI-e TX and RX

Part Number: TDA2 Is the a requirement for termination resistors on TX and RX for the PCI-e layout? This PCI-e bus is chip to chip not to an off board device. I see in the recommended layout details for differential and single ended trace impedance. The is detail on the clock termination 50 ohm to GND on P and N. Other resources for PCI-e show TX and RX termination resistors both to GND and across P and N.

There is not much space to place the termination resistors to I am hoping I can get by without...

Hi Zach, PCIe data lanes are internally terminated. No need for external termination. Note the need for AC-coupling capacitors on the Tx path however (on both PCIe devices). Best regards, Stan

Regarding TDA2 clock input (LJCB): • If the clock is provided externally by a High-speed Current Steering Logic (HCSL) source, no termination at the TDA2 LJCB_CLKN and LJCB_CLKP differential input is needed, and the lines should be DC-coupled. The standard 50 Ohm single-ended termination that is inherent to HCSL should be implemented at the clock source. • If the clock is provided externally by a LVDS source, the lines must be AC-coupled and a parallel (differential) termination of 100 Ohm might be required at the receiver. In this case, check that 100 nF capacitors are present on the clock pair lines, and that a 100 Ohm resistor is connected between the TDA2 LJCB_CLKN and LJCB_CLKP pads.

I have one TDA2 on one side and another TDA2 on the other side as well. Both have sides for the clock diff pair have 50 ohms to ground of P and N, and AC coupling caps. Do we need the 100 ohms parallel resistor in this case?

Hi, Can you please post a diagram of the clocking? Including the clock generator IC, clock path, clock inputs of TDA2s. Thanks, Stan

Hi Zach, This must be like bullet (1) from my previous post. Assuming U1A is clock source and the other TDA2 is clock consumer, then you need only R301 and R302. Other components must be removed. Regards, Stan

Stan, Ok. Remove the capacitors as well so not AC coupled as I read in the datasheet. So my original question, the TX and RX signals. These do need to be AC coupled and don't need termination resistor just the impedance controlled trace? Thanks, Zach

Please see summary below:

Great! Thank you.

Ticket Name: TDA2: EVE application code does not execute on board

Part Number: TDA2 Hi, I have created an application that should run on EVE. When I execute this application on EVE Simulator (ccs v5 Vayu simulator), it runs correctly and generates expected output. But when I try to run the same application on TDA2x board via emulator (ccs v7), it gets stuck at one point. I have some other applications, which run seamlessly through both simulator and emulator, so does not seem to be hardware issue. What are the differences between simulator and emulator environment? Is there anything in the code that needs to be changed or configured? Regards, Shruti

Hi Shruti, If it works on the simulator then generally it should work on the emulator. Where did it get stuck ? Please make sure you follow all the instructions in paragraph 3.6 of the eve_sw_getting_started.pdf of the EVE sw release, especially set EVE_SW_CONFIG macro to 1 in TDA2xx_multicore_reset.gel file. regards, Victor

Hi Victor, The code works fine with the simulator. But when I run it onto the board, it gets stuck after one block of BAM execution. Can you help me figure out the problem? I tried adding the code one by one. There is a lookup table implemented in the function, and when I comment the lookup table loop, the code runs on the board. It is a simple lookup table similar to the ones given in TIs examples. The same lookup table works with another application correctly. Can this be some illegal memory access issue? or some configurational issue? Regards, Shruti

Hi Shruti, You said it gets stuck. If you halt the CPU, where the program counter points to ? Or is the ARP32 crashed and you cannot even reconnect to it ? If it crashed, it could be that that the VCOP error register got set and if you don't clear the error bit, before VCOP is ran again, it will cause ARP32 to disconnect. You can monitor the state of the vcop_error register by selecting the Code Composer menu View->Register and click on VCOP_Status_Registers. if any bits of the vcop_error register is set, you need to clear it by writing the same value again. If you don't do that, next time, VCOP is executed, ARP32 will disconnect. Please refer to the EVE programmer's guide section 9.3 for meaning of the vcop_register's fields. regards, Victor

Ticket Name: Compiler/TDA2SX: vector include

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler HI dear TIer, I am working on tda2, vision SDK 3.8 and A 15 works on Linux. I use stl vector in my code, but I don't know how to config to pass the compiling: facedetectcnn.h:53:10: fatal error: vector: No such file or directory #include <vector> ... Thanks for your help.

Hi Robert, Can you please give some more details on what you are trying to add? I didn't get what is stl vector and where you are trying to include vector.h . Thanks RamPrasad

hi I use a 3rd-party face detection algorithm in a usecase. NullSrc->A15 ALgorithm->Display in A15 ALgorithm , I do face detection, and it uses vector . Thanks!

hi Robert, Which vector.h you are trying to include? I found a vector.h in include/configs/frame of the kernel but this file is empty. Thanks RamPrasad

Hi , Thanks for your reply. What I want to use is the container vector, both the vector and iostream can't be found. #include <string.h> #include <vector> #include <iostream> using namespace std;

Hi, Sorry for the late response. You have to include the header file path in a MAKEFILE.MK file. ex: INCLUDE+= -I$(LINUX_TARGETFS)/usr/include -I$(kernel_PATH)/include/generated/uapi $(OSA_INC) -I$(ipc_PATH)/packages -I$(ipc_PATH)/linux/include -I$($(MAKEAPPNAME)_PATH) Do the same changes for the C++ header file to include in a MAKEFILE.MK. Thanks Gaviraju

Ticket Name: TDA2: TDA2P and TDA2SX

Part Number: TDA2 Other Parts Discussed in Thread: DRA756, , Please help us to clarify follwoing questions: 1. TDA4 product planning and datasheet release progress? 2. DRA756 and TDA2S development board should be the same ? As we know, DRA756 focus on car entertainment, TDA2X focus on ADAS, we develop series product based on DRA756 development board, shall we use DRA756 Demo Board to develop partial funcfuntion for TDA2X ADAS ? 3. TDA2X Model confirmation: We develop sensor fusion based on TAD2P-ACD, we know TDA2P is just prototype from printscreen of TDA2x datasheet. Shall we use TDA2SXTB at mass production phase? Or we get wrong information, TDA2P-ACD and TDA2SXTB are both different orderable model of mass production. Which performance is better for TDA2P-ACD and TDA2SXTB ? Functional safety certification product model is TDA2P-ACD or TDA2SXTB ?

Hi Joseph, 1. TDA4 is under development. Initial datasheet is expected to be available next week. 2. Yes, you can use same EVM. 3. TDA2P-ACD and TDA2SXTB are both different orderable models of mass production. Note that they are in different packages... Device evolution stage marking is on the first position (see Device Naming Convention) Thanks, Dian

Please provide website link of TDA2SXTB datasheet, if TDA2SXTB datasheet is same with TDA2, we have it;

Hi, Yes the datasheet is the same. Regards, Rishabh

Ticket Name: RTOS/TDA2: Data flow of TIDL Object detect use case?

Part Number: TDA2 Tool/software: TI-RTOS Hi OK, I see the pic. but it should be contained Lane Departure warning (LDW)、Vehicle Detection (VD)、Pedestrian, Bi-cyclist and Powered Two Wheeler Detection etc... Does't it ? but I doesn't see them in the flow. Can you tell me where they going?

No , This is object detect only , Lane Departure warning is not present. Only Vehicle Detect and Traffic sign is trained . Regards Chetan.M

Ticket Name: TDA2: TIDL library from vison SDK profiling cycles doesn't match with the prescribed cycles in the data sheet

Part Number: TDA2 I'm using TDA2X vision high board. I built the test application provided along with the TI deep learning library TIDL for EVE and loaded it on the EVE core from Debugger. The profiling results i got was: TEST_REPORT_INIT_PROFILE_DATA : TSC cycles = 1045023112, SCTM VCOP BUSY cycles = 0, SCTM VCOP Overhead = 0 TSC cycles are 1045023112 which is way higher than the promised cycles in the datasheet. What am I doing wrong. Please guide.

Hi Srinidhi, The number that you are observing the initialization cycles (it is one-time cycle, not the process cycle). The test execution is not complete. At end of execution below print is expected from TIDL test bench. below highlited is the cyclee required for one inference process TEST_REPORT_INIT_PROFILE_DATA : TSC cycles = 1090612854, SCTM VCOP BUSY cycles = 0, SCTM VCOP Overhead = 0 I/O Bytes : 183972592 ( 12396776 + 171575816 ) : 0 ( 0 + 0 ) Processing Frame Number : 0 TEST_REPORT_PROCESS_PROFILE_DATA : TSC cycles = 159966840, SCTM VCOP BUSY cycles = 115715684, SCTM VCOP Overhead = 0 I/O Bytes : 93366432 ( 61884464 + 31481968 ) : 197540112 ( 170210288 + 27329824 ) End of config list found !

Hi kumar, Yes this is in line with the numbers with the datasheet. But in "Embedded low-power deep learning with TIDL" document it says: It says at 0.700giga cycles(700 mega cycles) time was 194.44 ms. How to achieve this performance. Was this on EVE core? On vision High board i consider EVE at 535Mhz. What was the clock speed at which this was achieved? Thanks

The original question was for datasheet numbers in the TIDL SW release package. Regarding the new question abou the above table, this is for 4xEVEs running at 900Mhz. The model used for the abiove table is diffrenet from the one available in the TIDL SW. The above mentioned sparse model takes 188 mega cycles for one frame inference (Againt the 159 Mega cycles for the one in TIDL SW release opackage). The dense model number 700 mega cycles is for reference. I hope this clarifies your new question. Regards, Kumar.D

Hi Kumar, When will be the Single-shot detector based libraries out? Any date that we can expect of? Thanks

Refer here e2e.ti.com/.../675785

Ticket Name: TDA2: Does TDA2SG support HDMI out, DDR3L and have Gigabit switch?

Part Number: TDA2 Does TDA2SG support HDMI out, DDR3L and have Gigabit switch? It shows that they are not supported in parametric table. However, in TDA2x datasheet, 'Table 3-1 Device Comparison', it shows that they are supported. Which specifications are valid? http://www.ti.com/product/TDA2?keyMatch=tda2&tisearch=Search-EN-Everything http://www.ti.com/processors/automotive-processors/tdax-adas-socs/products.html

Hi, The Data Manual is correct - TDA2SG supports HDMI out, DDR3L and Gigabit switch. We will work to get table on the products page fixed. Regards, Yordan

Ticket Name: Linux/TDA2P-ACD: GMAC_SW

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hi Team, Can you please answer the following question, is it in general possible to configure the 3—Port GMAC_SW, that the data can be routed directly between port1 to port2? If yes, does this produce any CPU load? Thanks, Needhu

Yes the TDA2x supports a full featured L2 switch and it is possible to switch frame directly between external port1 and port2. The switching is done in hardware and does not cause any CPU load. Refer TDA2 TRM Gigabit Ethernet Switch section ,specifially Address Lookup Engine subsection section for understanding switch functionality

Ticket Name: TDA2: HDMI signals are not connected via companion IC TPD12S016RKTR

Part Number: TDA2 Other Parts Discussed in Thread: TPD1E05U06 How destructive are the HDMI signals if I am using TPD12S016RKTR for ESD protection instead of using TPD1E05U06, knowing the IO capacitance is higher (1.2pF) as compared to 0.47pF of TPD1E05U06? If I am using the HDMI port for lab-use purpose, is it good enough to use TPD12S016RKTR and DLW21SZ900HQ2L to save cost and mainly board space?

We cannot answer the question as we have not tested the described configuration. The higher capacitance will impact the interface at higher speeds. The amount of impact would depend on the display resolution, refresh rate, and color depth used in the application. We have seen to reach the highest speeds the interface needs to be optimally designed, including using components with lowest capacitance. It is expected the interface can operate at less than max frequency using less than optimal design components. Thanks Robert

Ticket Name: RTOS / TDA2： How to run TIDL_OD usecase?

Part Number: TDA2 Tool/software: TI-RTOS Hi, I try to run TIDL_OD usecase but I got fail Can you tell anything to me? How do I do? Can you provide guide for our reference?

VisionSDK_UserGuide_TI_DeepLearning.pdf describes the section 5 Build and Run TIDL Object detect use case Before running the Vision SDK binary,  Make sure the following files are present in the MMC/SD card: o TIDL OD Network file (NET_OD.bin) o TIDL OD Parameter file (PRM_OD.bin) o TIDL OD Usecase input data file (inData_OD) o TIDL OD Usecase input header file (inHeader_OD) The error is seen as the files are not copied into SD card . Please copy the input files and rerun the usecase . Regards Chetan.M

Allen, Are you able to test with the given changes , If not please mention what is the error you are facing. Regards Chetan.M

Oh ,thanks I can run the TIDL_OD use case. but, Can we use the frame by camera capture for input data in TIDL_OD use case? If yes, How do I do? Can you provide any guide for our reference? If no I want to run TIDL_OD Demo with OV Sensors. How can I to do this?

Hi Allen , Please close this thread and start another thread for running TIDL on live camera, You can always modify the use-case to remove the null src and have capture source and set the params accordingly I am not sure how to train the model and other details Regards Chetan.M

Ticket Name: TDA2P CTT - When will it be available?

Other Parts Discussed in Thread: TDA2 Team, Please advise when the TDA2P Clock Tree Tool (CTT) will be released. Can the TDA2 CTT be used (i.e. what are the differences in the clock tree)? Best,

Hi, Lina, The TDA2Px will be released mid July in Auto Package. In general, the differences in clock tree between TDA2Px and TDA2x will be only in the supported modules of the devices - add modules with their clocks or remove modules. You can compare Data Manuals to figure out the differences. For existing modules in both family of devices, I think that for now you can use TDA2x CTT. Also, there is a released Sitara Plus CTT under NDA, if you want I can sent you in a private mail. Regards, Mariya

Hi Mariya, I'm not familiar with the Sitara Plus. Will the clock tree tool be the same for both? If so, please send via email. Best,

Hi, The CTT was sent via mail. I will close the thread. Regards, Mariya

Ticket Name: Compiler/TDA2PXEVM: Usecase is crashing in IPU core with File_open() function call

Part Number: TDA2PXEVM Tool/software: TI C/C++ Compiler Hi, I was trying to create a very basic application on H264 decoding; objective was to achieve something similar to "null_src_dec_display" usecase from "Apps". So, I took the "Sample_app" as a staring point created the usecase: NullSource -> Decode -> Display On the target hardware, what i am observing is File_open() function hangs and i dont see any log, assert messages on the serial console. But the "null_src_dec_display" usecase which also deals with file input works properly. Vision SDK version: 03.07.00.00 # CPUs included in application, # PROC_IPU1_0_INCLUDE=yes # PROC_IPU1_1_INCLUDE=no # PROC_IPU2_INCLUDE=no # PROC_DSP1_INCLUDE=yes # PROC_DSP2_INCLUDE=no # PROC_EVE1_INCLUDE=no # PROC_EVE2_INCLUDE=no # PROC_EVE3_INCLUDE=no # PROC_EVE4_INCLUDE=no # PROC_A15_0_INCLUDE=no # Video Module config, # IVAHD_INCLUDE=yes # VPE_INCLUDE=yes # CAL_INCLUDE=yes # ISS_INCLUDE=yes # ISS_ENABLE_DEBUG_TAPS=no # WDR_LDC_INCLUDE=no # DSS_INCLUDE=yes

I found the issue. In "sample_app", the File_init() function not called. Following code at the beginning of ChainsCommon_Init() in chains_common.c solved the issue: #if defined(FATFS_PROC_TO_USE_IPU1_0) File_init(); #endif

Hi Suman, thanks for the update. regards, Yordan

Ticket Name: Linux/TDA2: algorithm causing delay

Part Number: TDA2 Tool/software: Linux Hi Expert, I'm running Linux Vision SDK v03.02.00(4.4.84) on TDA2Ex. reference usecase: "chains_lvdsVipMultiCam_Sgx3Dsrv" Modify as below： The usual operation display is smooth. However, increasing the amount of DSP operations will a serious delay in the display. How can I continue to display images without being affected by DSP delay? Only get the left image, Capture → Sync → Dup → ipc → Sgx3Dsrv. But it has not improved delay. sgx3DsrvLink_drv.c, Int32 Sgx3DsrvLink_drvDoProcessFrames(Sgx3DsrvLink_Obj *pObj) In addition, add Vps_printf in the capture, dup, sync link to observe each link's system_sendLinkCmd (, SYSTEM_CMD_NEW_DATA, The sending interval will become longer when the DSP to increase the load. Why? Could you please give some suggestion here? Thanks in advance.

Hi, I did not understand your question. Which operations are you trying to do in DSP? Is that running on parallel or serially with Display. Why there is ipc link in the image. It should not be there. Regards, Anuj

Hi, Which operations are you trying to do in DSP? DSP to do custom algorithm, it's work ok. why increasing the amount of DSP load will a serious delay in the chains? Is that running on parallel or serially with Display. I don't understand this meaning? Why there is ipc link in the image. It should not be there. Why not? It's reference usecase: "chains_lvdsVipMultiCam_Sgx3Dsrv" I try no ipc link is don't work. Thanks in advance.

Hi, The final FPS you will get for the entire chain depend upon the max time taken by all the links. Suppose you have a chain with 2 links and 1 link run at 10 fps and 2nd one at 30 fps so chain will run at 10 fps only. So if you increase the processing time of dsp link then that will affect the entire chain. Why not? It's reference usecase: "chains_lvdsVipMultiCam_Sgx3Dsrv" IPC links are automatically introduced by vsdk_usecase generation tool and that will not be shown in img or txt file but in actual usecase c file,Ipc links will be present. Regards, Anuj

Hi, Its been long since any update on this thread. Hoping you are able to resolve your issue with my inputs. Closing the thread. Regards, Anuj

Hi, The final FPS for the entire chain depend upon the max time taken by all the links. Any chain style will have this phenomenon? (Such as series or parallel) Why are multiple cores still affected? Could you please provide some guide on these questions? Thanks in advance.

Hi, A chain works in series means output of 1 link becomes input of other and so on capture -> vpe -> display If the input of a link does not depend on other chanin then its parallel capture-> display grpxsrc -> grpxdisplay Here both chain is independent of each other so they can work in parallel. Regards, Anuj

Hi, Will it be affected if used the below design? Thanks in advance.

Hi, Yes, suppose if your custom link is taking 100ms per frame and other link takes a max of 33ms still you wont get a 30FPS at display. you will get 10FPS as your custom link is not freeing the data and causing other links to drop frames and be in idle state. Please go through the below doc for more information on MCFW framework vision_sdk\docs\Architecture Regards, Anuj

Ticket Name: J7 TDA4 EVM - eDP Display support

Other Parts Discussed in Thread: TDA2 Hello all, We have received J7 SOM , Common Processor Board and Fusion Daughter board. We don't have the fan on the heat sink . Is it required to connect the FAN ? Is display is supported in common processor board ? I find two display ports in the Common Processor board. We have a eDP connector cable. In other end what to connect ? Can I connect HDMI ? Regards, Gokul

Hi Gokul, In case you have heat sink, you don't need fan. You can connect Display Port to a DP monitor. For HDMI you need infotainment daughter card. Regards, Rishabh

Hi, You can also refer to psdk_rtos_auto_j7_06_01_00_15/psdk_rtos_auto/docs/user_guide/evm_setup_j721e.html Regards, Rishabh

Thanks Rishabh. Regarding the power supply for evm , it is mentioned that "The power supply current requires more than 1A @12V input " Is it correct ? Please confirm. Regards, Gokul

Hi Gokul, Did you receive a power adapter with the EVM? If yes then please use the same. Regards, Rishabh

Hi Rishabh, We have not received the power adapter. Regards, Gokul

Gokul, I am using the same power adapter as TDA2, same should work for you as well. Regards, Rishabh

Hi Rishabh, We do not have TDA2 EVM board. Please let me know the power specification. Is the above values are correct ? Regards, Gokul

Hi Gokul, It seems that you were working on TDA2Px by looking at the history of your forum posts. You can use the same power supply as the one used for TDA2Px. I have contacted Mistral for exact recommendation. Regards, Rishabh

Hi Rishabh, I were working for J6-Customized board. Regards, Gokul

Hi Gokul, You need to use the power adapter as recommended in the HW user guide. 12V/5A is the recommended supply. DigiKey Part# Manufacturer Manufacturer Part # SDI65-12-U-P6-ND CUI Inc. SDI65-12-U-P6 SDI65-12-UD-P6-ND CUI Inc. SDI65-12-UD-P6 - Pratap.

Thanks Pratap for the confirmation.

Hi, I am closing the thread as confirmed by Mistral. Regards, Rishabh

Ticket Name: Linux/TDA2EVM5777: display link question

Part Number: TDA2EVM5777 Tool/software: Linux How to display a RGB_24_888 video frame via display link?

Hi, You cannot explicitly set input format for display link. You need to output frame in RGB_24_888 format from the previous link. Regards, Rishabh

Ticket Name: TDA2SX: TDA2SX

Part Number: TDA2SX Incidental TDA2s chips in my project cannot be successfully after performing a warm reset operation, such as using the devmem2 0x4ae07D00 w 1 and reboot - f instructions. The specific manifestation is that the system current does not increase again after decreasing, while other chips can succeed. May I ask what the reason is?

Hello, Please provide full details of your project including what TI EVM you are using and the TI SDK being used here. If it is a custom platform, we suggest you contact your hardware team to ensure they have followed the proper guidelines of TDA2s SOC on the platform. Thanks.

Ticket Name: TDA2: data flow of cascade_radar_object_detect

Part Number: TDA2 Hi, I am about to use TDA2 to collect and process cascaded 1243 data. I downloaded and installed the PROCESSOR_SDK_RADAR_03_04_00_00 package. For C:\ti\PROCESSOR_SDK_RADAR_03_04_00_00\vision_sdk\apps\src\rtos\radar\src\usecases\cascade_radar_object_detect this demo, I see the datapath is shown in the figure below: I am wondering if the Select step is to select data from different 1243 radar(Q0,Q1,Q2,Q3) and what is the order of merging the data after fft? And if possible, where could I find the source code doing this step? Thanks.

Hi, The order of merging is Q0, Q1, Q2, Q3. The merge would make a System_VideoFrameCompositeBuffer type container which contains the buffer addresses of individual buffer outputs in the multi-dimensional array bufAddr. If you are looking at how the data is read from these 4 separate buffer addresses captured in bufAddr, you can refer to PROCESSOR_SDK_RADAR_03_04_00_00\vision_sdk\apps\src\rtos\radar\src\alg_plugins\alg_fxns\radardspprocess\radarDspProcess.c function AlgorithmFxn_RadarDspProcessProcess onwards. Thanks and Regards, Piyali

Thanks for the quick response. you are right that AlgorithmFxn_RadarDspProcessProcess is a good function to know how data is processed separately. But I would like to know if the source code of Merge is available in the package? Can I assume that Q0 stands for data from master device and Q1, Q2 and Q3 stand for data from slave devices 1,2 and 3? If so, the order of output data of Merge would be master, slave 1, slave 2 and slave 3. Am I right about this? Thanks.

Hi The source for the merge is at PROCESSOR_SDK_RADAR_03_04_00_00\vision_sdk\links_fw\src\rtos\links_common\merge The Q0, Q1, Q2, Q3 would be based on how the board is designed to connect the VIN channels. On the TI cascade Radar EVM, VIN1A is connected to Slave 3 (Q0) , VIN2A is Master (Q1) , VIN3A is Slave 1 (Q2) , VIN4A is Slave 2 (Q3). Thanks and Regards, Piyali

Ticket Name: PROCESSOR-SDK-DRA8X-TDA4X: Compile OpenCV with OpenVX

Part Number: PROCESSOR-SDK-DRA8X-TDA4X Hello, We are working in TDA4 SOC. Is it possible to build opencv with Openvx ? https://www.ti.com/lit/wp/spry260/spry260.pdf?ts=1603377013741&ref_url=https%253A%252F%252Fwww.google.com%252F page 11 Regards, Gokul

Hi Gokul, We encourage the use of optimized OpenVx solution as the default in the TDA4 offerings. Regards Karthik

Hi Karthik, My question is what does the pdfs says https://www.ti.com/lit/wp/spry260/spry260.pdf?ts=1603377013741&ref_url=https%253A%252F%252Fwww.google.com%252F page 11 Is it possible to build opencv with openvx ? Regards, Gokul

Hi Gokul, That document is for TDA2, the path forward on the TDA4 is using OpenVx. Regards Karthik

Ticket Name: TDA2EVM5777: UART communication in RTOS on TDA2-EVM board

Part Number: TDA2EVM5777 HI experts: I have a project that uses the TIDL function on the TDA2-EVM board for image recognition and receiving ultrasonic signals (via GPIO), I would like to transmit the information calculated by TIDL to another device for data integration through UART interface. At present, because the function of TIDL can only run in the RTOS system, it is currently developed using RTOS. I found several UART related discussions on the e2e forum, which mentioned that it can only be transmitted through UART3. But there are no related examples in the usecase of the SDK, so few questions as below: (1) How to add UART transmission examples in usecase or have operation manual in detail? (2) If there are multiple communication interface requirements, does the board support more than 2 transmissions? (3) Or are there other suggestions for that project? thank you Best / Regard wxchen

Hi I will check with the team & get back Thanks Gaviraju

Hi, Thanks for your reply, how much time does your team need for checking? best / regard wxchen

Hi, Theoretically, it's possible to communicate with other devices using UART & for this, you have to short TX & RX. using existing PDK software you can read & write data & this is not verified from our side. 1) Refer to this "vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_DevelopmentGuide.pdf" if you want to add new use-case 2) It might support & look into the TRM for more info 3) You can use Network_TX link to transfer data to other devices. Thanks Gaviraju

Ticket Name: time measurement for each frame in EVE

Other Parts Discussed in Thread: TDA2 Hello, I have to integrate EVE Sparse optical flow into our project in TDA2. I ran the sparse optical flow test bench. Test video has 5 frames. In the console, i get the TSC cycle and SCTM VCOP BUSY cycles at every frame. I would like to calculate the time consuming to perform the optical flow in every frame. Can you please tell me to compute the time for each frame. Jagan

Hi Jagan, I have forwarded your question to the EVE experts to comment. Regards, Yordan

Hi Jagan, Once you have the TSC cycles per frame ( in terms of VCOP cycles) you can convert it to time by just dividing the cycles by the frequency at which EVE (VCOP) is running ( typically this value is 500MHz). Regards, Anshu

Ticket Name: Linux/TDA2: how to make link from A15 lib

Part Number: TDA2 Tool/software: Linux now i have a A15 lib mylib.a and header file mylib.h How can i make a A15 alg_plugins link ,where can i load mylib.a , and how to include mylib.h . any example?

Hi Please refer the sample HLOS Alg plug-in \vision_sdk\apps\src\hlos\adas\src\alg_plugins\framecopy regards, Shiju

Hi Shiju i try to add mylib in framecopy for test include $(vision_sdk_PATH)/build/hlos/makerules/linux/common_header_a15.mk INCLUDE+= -I$(vision_sdk_PATH)/mylibs/include -I$(ipc_PATH)/hlos_common/include -I$(ipc_PATH)/packages -I$(kernel_PATH)/include/generated/uapi $(OSA_INC) -I$(ipc_PATH)/linux/include -I$($(MAKEAPPNAME)_PATH) LIBS += $(vision_sdk_PATH)/mylibs/libarcsoft_face_base.a LIBS += $(vision_sdk_PATH)/mylibs/libarcsoft_face_detection.a LIBS += $(vision_sdk_PATH)/mylibs/mpbase.a LIBS += $(LIB_BASE_DIR)/vision_sdk_linux_demo.a LIBS += $(shell cat $(DEST_ROOT)/appLiblist_a15_0.txt) include $(vision_sdk_PATH)/build/hlos/makerules/linux/common_footer_a15.mk have follow problem /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/lib/tda2xx-evm/a15_0/release/apps.a(frameCopyAlgoCpu.o): In function `Alg_FrameCopyProcess': frameCopyAlgoCpu.c:(.text+0xda): undefined reference to `MMemMgrCreate' frameCopyAlgoCpu.c:(.text+0xea): undefined reference to `AFD_InitialFaceEngine' frameCopyAlgoCpu.c:(.text+0x152): undefined reference to `AFD_StillImageFaceDetection' frameCopyAlgoCpu.c:(.text+0x164): undefined reference to `AFD_UninitialFaceEngine' frameCopyAlgoCpu.c:(.text+0x16a): undefined reference to `MMemMgrDestroy'

This is a duplicated thread of e2e.ti.com/.../694486 will replay on other thread

HI Shiju SO I WAIT for it !

Ticket Name: TDA2: [TDA / opencv / usecase modification] want to implement my code by modifying the opencvopencldilation usecase

Part Number: TDA2 (vision SDK version : PROCESSOR_SDK_VISION_03_03_00_00) Hi I'm newbie of using TDA2x evb board and vision App board I'd like to implement my algorithm which is using openCV and implement it by modifying the sample usecase&alg_plugins ( vip_single_cam_opencvopencldilation / opencvopencldilation) [ Question ] I want to apply my alogirhtm code and display it to the monitor. Where the points that I should modify the code? I started modifying like below, however when I remove the "cv::dilate" code, it displays black image with processor usage. prior code <openclDilation.cpp> modified code <openclDilation.cpp> void* openclDilationThreadFunc(void* args) { while(1) { cv::Mat openCLDilationInputMat; cv::Mat openCLDilationOutputMat; cv::UMat openCLDilationInputUMat; cv::UMat openCLDilationOutputUMat; if(!gOpenCLDilationThreadStarted) { cv::ocl::setUseOpenCL(1); gOpenCLDilationThreadStarted = 1; } /* wait for the produce thread to point to the current input * and output buffers */ while(!g_cac) { usleep(1000); } pthread_mutex_lock(&gOpenCLDilationMtx); /* * \brief Compute using OpenCV */ openCLDilationInputMat = cv::cvarrToMat(gOpenCLDilationKernelArgs.inputImage, false); openCLDilationOutputMat = cv::cvarrToMat(gOpenCLDilationKernelArgs.outputImage, false); openCLDilationInputUMat = openCLDilationInputMat.getUMat(cv::ACCESS_RW); openCLDilationOutputUMat = openCLDilationOutputMat.getUMat(cv::ACCESS_RW); cv::dilate(openCLDilationInputUMat, openCLDilationOutputUMat, cv::Mat()); openCLDilationInputUMat.release(); openCLDilationOutputUMat.release(); openCLDilationInputMat.release(); openCLDilationOutputMat.release(); g_cac = 0; pthread_mutex_unlock(&gOpenCLDilationMtx); } pthread_exit(&gOpenCLDilationThreadRtn); return ((void*) 0); } void* openclDilationThreadFunc(void* args) { while(1) { cv::Mat openCLDilationInputMat; cv::Mat openCLDilationOutputMat; cv::UMat openCLDilationInputUMat; cv::UMat openCLDilationOutputUMat; if(!gOpenCLDilationThreadStarted) { cv::ocl::setUseOpenCL(1); gOpenCLDilationThreadStarted = 1; } /* wait for the produce thread to point to the current input * and output buffers */ while(!g_cac) { usleep(1000); } pthread_mutex_lock(&gOpenCLDilationMtx); /* * \brief Compute using OpenCV */ openCLDilationInputMat = cv::cvarrToMat(gOpenCLDilationKernelArgs.inputImage, false); openCLDilationOutputMat = cv::cvarrToMat(gOpenCLDilationKernelArgs.outputImage, false); openCLDilationInputUMat = openCLDilationInputMat.getUMat(cv::ACCESS_RW); openCLDilationOutputUMat = openCLDilationOutputMat.getUMat(cv::ACCESS_RW); openCLDilationOutputUMat = openCLDilationInputUMat; openCLDilationOutputMat = openCLDilationInputMat; openCLDilationInputUMat.release(); openCLDilationOutputUMat.release(); openCLDilationInputMat.release(); openCLDilationOutputMat.release(); g_cac = 0; pthread_mutex_unlock(&gOpenCLDilationMtx); } pthread_exit(&gOpenCLDilationThreadRtn); return ((void*) 0); }

Whats the image you were seeing before any change?

Ticket Name: TDA2: To add the 5th AWR1243 here are the pinout changes

Part Number: TDA2 Other Parts Discussed in Thread: AWR1243 To add the 5th AWR1243 here are the pinout changes we are planning to the cascade radar reference design. Can you confirm we are not using any pins incorrectly? With Muxmode = 7 Pins needed for 5th AWR1243: Pin remove add C14 open vin6a_fld0 G12 I2C5_SDA vin6a_vsyn F12 I2C5_SCL vin6a_hsyn B13 TDA_FPGA_SPI_SEL_A_GPIO5_12 VIN6A_D13 A12 TDA_FPGA_SPI_SEL_B_GPIO4_17 VIN6A_D12 E14 TDA_AWR1_GPIO0_GPIO4_18 VIN6A_D11 A13 TDA_AWR1_GPIO1_GPIO6_4 VIN6A_D10 G14 TDA_AWR1_GPIO2_GPIO6_5 VIN6A_D9 F14 open VIN6A_D8 B12 TDA_AWR2_SPI_INT_GPIO5_10 VIN6A_D15 A11 TDA_AWR3_SPI_INT_GPIO5_11 VIN6A_D14 D14 open VIN6A_DE0 A19 open VIN6A_D7 C15 open VIN6A_D5 A16 open VIN6A_D4 A18 open VIN6A_D6 B18 open VIN6A_D3 B19 open VIN6A_D1 C17 open VIN6A_D0 F15 open VIN6A_D2 E17 open VIN6A_CLK0 D18 open VIN6A_D0 Move these signals to new pins: Pin remove add AA3 TDA_VIN4A_D20 I2C5_SDA AB9 TDA_VIN4A_D21 I2C5_SCL C18 TDA_VIN4A_D16 TDA_AWR2_SPI_INT_GPIO5_10 A21 TDA_VIN4A_D17 TDA_AWR3_SPI_INT_GPIO5_11 G16 TDA_VIN4A_D18 TDA_AWR1_GPIO0_GPIO4_18 D17 TDA_VIN4A_D19 TDA_AWR1_GPIO1_GPIO6_4 AB3 TDA_VIN4A_D22 TDA_AWR1_GPIO2_GPIO6_5 R6 TDA_VIN3A_MUX_D16 TDA_FPGA_SPI_SEL_A_GPIO5_12 T9 TDA_VIN3A_MUX_D17 TDA_FPGA_SPI_SEL_B_GPIO4_17

Hi Zach, Please find some feedback on the pin list below: C18 TDA_VIN4A_D16 TDA_AWR2_SPI_INT_GPIO5_10 --> Pad does not support GPIO. A21 TDA_VIN4A_D17 TDA_AWR3_SPI_INT_GPIO5_11 --> Pad does not support GPIO G16 TDA_VIN4A_D18 TDA_AWR1_GPIO0_GPIO4_18 --> Pad does not support GPIO D17 TDA_VIN4A_D19 TDA_AWR1_GPIO1_GPIO6_4 --> Pad does not support GPIO AB3 TDA_VIN4A_D22 TDA_AWR1_GPIO2_GPIO6_5 --> Pad does not support GPIO R6 TDA_VIN3A_MUX_D16 gpio7_3 T9 TDA_VIN3A_MUX_D17 gpio7_4 Others are okay. Thanks and Regards, Piyali

Ticket Name: Linux/TDA2EXEVM: TDA2 ISSCAPTURE

Part Number: TDA2EXEVM Tool/software: Linux Dear Sir: We are using VSDK 03_04_00_00. We try to use the CSI2 format to capture from the MIPI interface. When setting the inCsi2DataFormat to SYSTEM_CSI2_YUV422_8B, it is okay. However when trying using the SYSTEM_CSI2_YUV420_8B or SYSTEM_CSI2_YUV420_8B_LEGACY, it fail to create the ISSCAPTURE link. By tracing the code, I see that the underlying link only support SYSTEM_CSI2_YUV422_8B, but not supporting the 420 format. But if tracing the PDK driver, we can see there is no such forbidden case in the PDK. Because the heat problem in the CPU, we want to try lower down the CSI2 transmitted data to reduce the heat when 8 channel(4CH in Parallel and 4 CH in CSI-2) are using in our board. My question is that: is it possible to use YUV420_8B or 420_8B_LEGACY in the PDK? Because both of these 2 types sending less data through the CSI-2 interface. Dos PDK support it? Or does TI has any plan to support it in ISSCAPTURE link in the future? Regards, /ckhsu

Hi ckhsu, ISS Capture driver supports all formats, but link is limited to few formats. You could easily add support for these formats in the iss capture link. The change required are in this check data format function and buffer allocation function. Can you make the changes and try it out? Regards, Brijesh

Hi Brijesh: I see. I paste the places that should be modified in the end of the response, please let me know whether it is correct place or not. However from what I understand, the LEGACY YUV420 8 bit frame is send through MIPI as following: U1Y1Y2 U3Y3Y4 ...... U637Y637Y638U639Y639Y640 ==> Odd line V1Y1Y2 V3Y3Y4 ...... V637Y637Y638V639Y639Y640 ==> Even line ...... In LEGACY YUV 420 8bit the pitch is fixed, it should be okay to add in the ISSCAPTURE link. But the YUV 420 8bit data in the MIPI is Y1Y2......Y639Y640 ==> Odd lines U1Y1V1Y2U3Y3V3Y4......U637Y637V637Y638U639Y639V639Y640==> Even Lines And the Odd and Even lines are in different sizes. And how this should be modify in the Link code? Or should this type be ignore in the link? Because This color space is quite different from the original UYVU422 or YUV420SP etc, I don't know how this should be done in described in the QueueInfo and Frames buffer struct. Can you give me some hints about this color space? I suppose the place to add the code is in this part inside IssCaptureLink_drvCreate. ////////////////////////////////////// for (chIdx = 0U; chIdx < pPrm->numCh; chIdx++) { pitchMul = getPitchMultiplier(&pPrm->outParams[chIdx], pObj->createArgs.videoIfMode, pObj->createArgs.videoIfWidth); pQueChInfo = &pObj->info.queInfo[0U].chInfo[chIdx]; pQueChInfo->width = pPrm->outParams[chIdx].width; pQueChInfo->height = pPrm->outParams[chIdx].height; pQueChInfo->startX = 0; pQueChInfo->startY = 0; pQueChInfo->pitch[0] = SystemUtils_align(pObj->createArgs.outParams[chIdx].maxWidth * pitchMul, ISSCAPTURE_LINK_BUF_ALIGNMENT); pQueChInfo->pitch[1] = 0; pQueChInfo->pitch[2] = 0; pQueChInfo->flags = System_Link_Ch_Info_Set_Flag_Data_Format(pQueChInfo->flags, pObj->createArgs.outParams[chIdx].dataFormat); pQueChInfo->flags = System_Link_Ch_Info_Set_Flag_Scan_Format(pQueChInfo->flags, SYSTEM_SF_PROGRESSIVE); /* Using complex IO cont flag instead of PHY/PPI, as CAL would require an instance of complex io for an instance of PHY */ UTILS_assert(VPS_ISS_CAL_MAX_CMPLXIO_INST > pObj->createArgs.outParams[chIdx].phyInstance); } ///////////////////////////////////////// I suppose the Bualloc is in Int32 IssCaptureLink_drvAllocFrames(IssCaptureLink_Obj *pObj) And in if(System_useLinkMemAllocInfo( &pObj->createArgs.memAllocInfo)==FALSE) { fvid2Frame->addr[0][0] = Utils_memAlloc( UTILS_HEAPID_DDR_CACHED_SR, pObj->outBufSize, SYSTEM_BUFFER_ALIGNMENT ); } else { fvid2Frame->addr[0][0] = System_allocLinkMemAllocInfo( &pObj->createArgs.memAllocInfo, pObj->outBufSize, SYSTEM_BUFFER_ALIGNMENT ); } ///////////////////////////////////////////////////////////// Regards, /ckhsu

Hi Brijesh: The MIPI 420 information can be found in the MIPI document. And there is a draft documents on net electronix.ru/.../index.php Please see the page 77 for YUV420 8 bit packet format. Regards, /ckhsu

Hi ckhsu, You could change the pitch and set the CSI data type to capture this frame. But how do you separate luma and chroma planes. Capture modules will not be able to separate them, they will be interleaved when captured.. Rgds, Brijesh

Ticket Name: TDA2EVM5777: TDA2EVM5777 DDR data pin connection

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello Why in TDA2EVM , DDR data pin connection are not in sequence? for example: U65 DQ15(A3) connect to DDR_D14 , DQ14(B8) connect to DDR_D9? thank you

Hi, When interfacing TDA2 to DDR3, the DQ bits can be swapped within a byte lane to ease routing on the PCB. Thus, the EVM design routed DQ15(A3) to DDR_D14 and DQ14(B8) to DDR_D9 , etc. because these mappings alleviated the challenges of the PCB routing. Please note that DQ bit swapping can only be done within a byte lane. Best regards, Kevin

Ticket Name: RTOS: SYS/BIOS: TDA2xx platform missing

Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hello, I have tried multiple versions of SYS/BIOS and I could not find a TDA2xx platform among offered ones. However, there is a TDA3xx one as can be seen in this image: Is there any version of SYS/BIOS where I can find the TDA2xx and if not where can I acquire it or which platform can I use that is equivalent? Thank you.

Hello Nick, Not an SYS/BIOS expert, however an equivalent platform that you may try with is AM572x. Thanks, Alex

Hello Alex, Thank you for the suggestion, I'll give it a try.

Nick, SYS/BIOS platform information for TDA2 and TDA3 is not included in CCS releases today. For TDA2 or TDA3 development you could start with Vision SDK (under NDA). In this case please contact your local TI representative.

Ticket Name: TDA2EXEVM: Enable Only 2AWRs on Cascade Board

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi E2e Support Team, We would like to use the TDA2 Cascade Board with 3.08 Radar SDK and enable only 2AWR to chirp and collect data in return. We understand this is more tricky to do than it looks. In an effort to try to understand a bit further how the SDK supports in Cascade board, I have the following questions: 1. If we only desire to enable 2AWRs out of 4 (ie: Master and Slave2), what needs to be done in AWR config Bsp_Ar12xxConfigObj? 2. Will there be changes required in configuring the 4 onboard FPGA (ie: in ChainsCommon_fpgaPowerUp() and ChainsCommon_fpgaStart())? 3. Currently when all 4AWRs are enable each with 4RX channels, there is a total of 16RX channel data feeding the 4EVEs for Range and Doppler FFT processing. If only 2 AWRs are enabled, there will essentially be only 8 RX channels going into the 4EVEs, how are the 8 channels divided amongst the 4EVEs? My guess is that only EVE1 and EVE2 will be actively processing the ADC data while EVE3 and EVE4 will be idled. 4. If only 2AWRs are enabled, will the links in a processing chain be required to be changed? Would it be smart enough to pick that up and automatically scale based on the number of available RX channels? Thank You,

We have provision to allow use case to define how many radars are used. /**
 * \brief Structure which holds the AR12xx configuration parameters.
 */
typedef struct {

    UInt32 numRadars;
    /**< Number of Radars being connected */
    ChainsCommon_RadarParams radarParams[CHAINS_MAX_NUM_RADARS];
    /**< Parameters per Radar */
    UInt32 frameType;
    /**< 0 - Normal Frame, 1 - Advanced Frame */
    UInt32 fusionEnabled;
    /**< Flag to show if Fusion is enabled or not */
    UInt32 enableTestSource;
    /**< Flag to enable synthetic input from Radar */
} ChainsCommon_Ar12xxConfigOut; However, we have only validated the full cascade radar processing chain with 4 radars configuration.

Hi Stanley, I know there is such a data structure to tell the AWR how many Radars we would like to use. Would you please spend a few minutes understanding the 4 questions I outlined above and give some feedback to each. Thanks, --Khai

Ticket Name: PROCESSOR-SDK-TDAX: Is there a way to program the user Programmable LEDs in TIDEP-01017?

Part Number: PROCESSOR-SDK-TDAX Hi, I'm using MMWCAS_DSP_EVM with Processor SDK Radar 3.08 and according to the User guide of the board, these LEDs(in Table) are user-programmable. I was wondering if I can get guidance on how to program these LEDs from the Radar SDK. I would greatly appreciate it.

Hi, These LEDs are connected to GPIO expander output. The same GPIO expander is also configured in Bsp_boardTda2xxCascadeEnableSdAndEth() under ~\ti_components\drivers\pdk\packages\ti\drv\vps\src\boards\src\bsp_boardTda2xx.c. You can refer to that function to see how to configure the specific output of the GPIO Expander via I2C command. Regards, Stanley

Hi Stanley, Thank you for the response. We were able to run this example located in ~\ti_components\drivers\pdk_01_10_04_05\packages\ti\csl\example\i2c\i2c_led_blink\main.c After modifying the slave address for the correct Port Expander (0x76 instead of 0x20), and were able to blink all those LEDs. Although we had to modify the sample code based on the datasheet(configuring the ports to become output before switching them ON/OFF).

Ticket Name: RTOS/TDA2: How to capture image and record video

Part Number: TDA2 Tool/software: TI-RTOS Hi, Using TDA2x with TI-RTOS, we can get live hdmi output. Our SDK version is 3.04 May I know 1) How to save the frame as an image to sdcard? 2) How to capture an video to sdcard? Thank you very much.

Hi, Please go through below thread e2e.ti.com/.../709062 Regards, Anuj

Ticket Name: TDA2SX: PROCESSOR_SDK_VISION_03_05 tidl_OD usecase layer limitations ?

Part Number: TDA2SX Hi I tried to use tidl_model_import.out to get bin file. I used stats_tool_out.bin and trace_dump_0_512x512.y file to check test image detection result. Test image showed model can detect object. test image detection result: But I ran on tdasx, it cannot detect any object. I suspect tdasx cannot run too many layers model. The number of layersGroupId are 157 and number of parameters are 3.5M. Do tdasx have any limitations about layers or parameters count? thanks yumei

Hi Yumei, Below are the SSD limitations listed in the TIDL datasheet : – Only Caffe-Jacinto based SSD network is validated. – Reshape, Permute layers are supported only in the context of SSD network. – “share_location” has to be true – Tested with 4 and 5 heads. – SaveOutputParameter is ignored in TIDL inference. – code_type is only tested with CENTER_SIZE. Please try the suggestions mentioned in the below thread in OD use case to get the detections in the output : https://e2e.ti.com/support/processors-group/processors/f/processors-forum/689617/tda2-how-to-run-ssd-based-tidl-od-use-case-in-vision-sdk-with-pre-trained-model Thanks, Praveen

Hi Praveen I confused about Tested with 4 and 5 heads. Did it mean about 4 and 5 anchor box result? Thanks, yumei

Yes

Ticket Name: Linux/TDA2: The main frequency of A15？

Part Number: TDA2 Tool/software: Linux i am useing tda2 evm , what is the frequency of A15？ sample_app\src\hlos\chains_common\chains_main.c in the main i move the usecase , read a img and run a cnn. There is no multithreading in CNN. In this case, is one A15 working or two A15 working at the same time? shuai

Hi, If you are running linux on A15 then it will always run 2 A15 in SMP mode. You can check the same by below command omapconf show opp Regards, Anuj

Ticket Name: CCS/TDA2EG-17: TDA2E17：How to implement one pin of GPIO5 interrupt on DSP(running BIOS),and other one pin of GPIO5 interrupt on A15（running Linux）

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2 Tool/software: Code Composer Studio Now,my board schematic is such that I need to config one pins of GPIO5 IRQ on DSP(running BIOS) , and other pins of GPIO5 from Linux on the A15, is that possible?

Hi, As on TDA2 family there is no dedicated interrupt per pin, only one per module hence such kind of implementation of interrupting 2 cores based on pins from same module of GPIO is not recommended by TI. Regards, Karan

Hi， Thank you for your reply. According to TRM, each GPIO mudule has two interrupt lines. Is it possible to map one interrupt line to A15 and another interrupt line to DSP

Hi, Yes, I think I confused the device. So you can actually route the two interrupts to A15 and DSP. Looking at the device tree in linux will help you check which one is already going to A15 running linux then you can register the other interrupt line on DSP. Regards, Karan

Hi Karan, I tried to do this, but the A15 core printed the error message "unexpected IRQ trap at vector 00" and it didn't seem to enter the interrupt function. I was wondering if anyone succeeded in this method?

Hi, Can you please share your feedback on the below for correct understanding? Does the system work correctly when you configure only the DSP side interrupt and fire the interrupt? Does the system work correctly when you configure only the Linux side interrupt and fire the interrupt? And you are saying that you face the issue only when both are enabled? And the issue is always on the A15 side and DSP works correctly? Can you please share your Linux side changes to enable the GPIO interrupt? Regards Karthik

Ticket Name: Compiler/TDA2SG: TDA2 TDA4 JTAG

Part Number: TDA2SG Tool/software: TI C/C++ Compiler hi,I want to buy debug tool like XDS110 ,XDS510, my problem is can XDS110 OR XDS510 support TDA2S & TDA4 simultaneously。 can you offer me the purchase link 。

Hello, Yes, XDS110 is supported on both devices (TDA2S and TDA4). However, I don't see XDS510 as an option, did you mean XDS560? If so that is fine too. XDS110 is an entry-level, slower speed, fewer features type of JTAG debugger. The XDS560 is the more advanced high-performance choice. Details can be found here https://processors.wiki.ti.com/index.php/XDS560 You may purchase both of them from ti store. For example: https://www.ti.com/tool/TMDSEMU560V2STM-U https://www.ti.com/tool/TMDSEMU110-U Lastly, you may read more discussion on Jtag emulators comparison here: https://e2e.ti.com/support/processors/f/791/p/704912/2598746 https://e2e.ti.com/support/j721e/f/1026/p/850250/3144383#3144383 Hope it helps, thanks, Alex

Ticket Name: RTOS/TDA2: TDA2xx: null source decode display issue

Part Number: TDA2 Tool/software: TI-RTOS Hi, I using the SDK 3.03 version now How can I get the sizeBin.exe this tool? Is it exist in SDK 3.03? BR Allen

Please find attached. Remove .txt from the executable name. /cfs-file/__key/communityserver-discussions-components-files/791/5657.sizeBin.exe.txt

hi, Prasad we can't get the executable file have other method can download it?or can you provide different resolution inData and inHeader BR Allen

Hello Allen, Can you please try below? If this doesnt work i will upload on TI dropbox and share link. Thanks /cfs-file/__key/communityserver-discussions-components-files/791/2844.sizeBin.txt

Hi, Prasad Yes I can download it but it look not like an executable file BR Allen

Hi Allen, Please rename it to sizeBin.exe (the forum engine do not allow to attach .exe files) Regards, Yordan

Ticket Name: RTOS/TDA2: Does Vision SDK has tested software dynamic function use TESSY tools?

Part Number: TDA2 Tool/software: TI-RTOS Hi Experts: My customer are trying use TESSY automatic tools test VSDK software's dynamic function. But those tools GCC can not successful compile VSDK code. Our VSDK contain Misra-c report but customer feedback that Misra-C report just contain the static function test report. Does we have experience about use TESSY tools verify VSDK? If not use TESSY, does we have used other kinds of tool test VSDK dynamic function safety? Thanks a lot! Best Regards! Han Tao (https://www.razorcat.com/en/product-tessy.html)

Hello No, vision ASK is not tested with any dynamic analysis tools regards, Shiju

Hi Shiju： Thanks for clarify it. Best Regards! Han Tao

hello，Shiju If we want to test VSDK software's dynamic function，is there any solution？Can you give us some advice？ regards，Vivian

Hi Vivian For any dynamic analysis, do it only for "core SDK" (only for "links_fw" folder) Apps and Sample_app are application/demo code. As I mentioned earlier, We have not done any dynamic analysis on Vision SDK. Vision SDK is not a safety compliant SW, it is only reference SW from TI, so we don’t do dynamic analysis on this SW. For safety compliant SW like MCAL we use LDRA tool for dynamic analysis. regards, Shiju

Hi Shiju： We use Tessy perform unit dynamic test, in order to verify software unit (function) design and fulfill the code coverage target (branch coverage, statement coverage, MCDC coverage). Now in Vision SDK component, there is some handle code (our Freetech code) need call Vision SDK core code, but there is no complier support to comply VSDK in Tessy. In other words, this Tessy tool can support our Freetech code, but can't support the code call Vision SDK. We don't try to verify VSDK code, we just need to verify the code which develop by Freetech. So do you have any solution or advice on this situation? Any solution from your customer which belongs to automotive area? Which tools did they use on unit dynamic test? Thanks Vivian

Vivian Sorry i do not have any experience with Tessy LDRA is one tool which I heard many customers used for dynamic analysis. regards, Shiju

Ticket Name: TDA4VM: Vision apps license terms

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Dear TI user, I have some questions about the license terms of TI License: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_02_00_05/exports/docs/psdk_rtos/PROCESSOR_SDK_RTOS_J721E_manifest.html * any redistribution and use of the source code, including any resulting derivative works, are licensed by TI for use only with TI Devices. * any redistribution and use of any object code compiled from the source code and any resulting derivative works, are licensed by TI for use only with TI Devices. What is a TI Device mean ? For my case, my customer want to design theirs hardware by their own, if only using TDA4VM Jacinto Processors and DS90UB960, DS90UB953 from TI. Their designed hardware, is it TI device ? If so , they want to modify and commercial distributors the TI's Vision Applications and TI's Imaging projects (the projects at the link below) , is that permitted ? If that is permitted, so they just need to keep the existing copyright notices, is it correct ? Thanks. https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/vision_apps/docs/user_guide/index.html https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/imaging/docs/user_guide/index.html

Phan Chinh said: What is a TI Device mean ? TI Device is any SoC/device that is made by Texas Instruments such as TDA2/3/4 and its variants. Phan Chinh said: TDA4VM Jacinto Processors and DS90UB960, DS90UB953 from TI. Their designed hardware, is it TI device ? Yes, these are TI devices. Phan Chinh said: If so , they want to modify and commercial distributors the TI's Vision Applications and TI's Imaging projects (the projects at the link below) , is that permitted ? If that is permitted, so they just need to keep the existing copyright notices, is it correct ? Yes, it is permitted and you retain existing notices as applicable. Regards Karthik

Ticket Name: Linux/TDA2EVM5777: DDR Configurations for VisionSDK Linux

Part Number: TDA2EVM5777 Tool/software: Linux Hello, I am running PROCESSOR_SDK_VISION_03_03_00_00 on the TDA2EVM5777 and on custom hardware that is similar to the EVM. I can successfully boot on the new hardware with the default memory that comes with Vision SDK (note there is nothing on our custom hardware's EEPROM at this time). I need to update Linux in order to utilize the 4GB of ram on the custom hardware setup, instead of default settings. Can you please help clarify exactly what is required to allow me to use all 4GB of ram on the custom hardware? Below is what I tried/my assumptions 1. Since the custom hardware does not contain any firmware for EEPROM, and is able to boot OK, I assume its using the default settings from the u-boot source just fine, however, the Linux user space only sees 600MB of ram total (found by running the command free) where there is supposed to be 1.5GB in default settings I believe, based on dra7-evm.dts file below settings: memory { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ }; How do I get access to more memory in user space with the default settings? 2. Since the custom hardware actually contains 4GB DDR, I want to change the bootloader to recognize the ram modules that I have, and so I followed this document. In the document, I was able to successfully use the EMIF configuration tool to generate the values necessary to update the u-boot source codes. When I finished filling out the EMIF configuration tool it generated LISA map register values to update evm.c with (the values for each LISA map register were very similar to the example for 2GB per EMIF settings given in evm.c). However, I haven't been able to successfully boot up using the updated source files yet. I didn't update the dra7-evm.dts to be 4GB yet, but unsure if that is the cause why it didn't boot. I didn't change anything in EEPROM either, since I have never had anything written to EEPROM and hoping I can just modify the default settings to be 4GB. Can you please help clarify exactly what is required to allow me to use all 4GB of ram on the custom hardware without writing to EEPROM? Thank you in advance, -iFer

Hi, Can you take a look at this discussion? Regards, Somnath

Hi iFer, Did you get a chance to look at the discussion? Let me know if you have any follow up question? Regards, Somnath

Do you need any other help on this topic?

Ticket Name: RTOS / TDA2：TDA2xx eve platform Run TDA3 usecase by RTOS

Part Number: TDA2 Tool/software: TI-RTOS Dear All, I have tda2xx eve platform, how to run tda3xx RTOS usecase by tda2xx?

Hi Owen, What is the SW package you are using? Regards, Rishabh

Dear Rishabh, i use sdk is PROCESSOR_SDK_VISION_03_03_00_00, i wnat to run tda3 3D avm by tda2xx eve platform

Hi Owen, TDA3 surround view is based on in built ISP whereas TDA2xx supports GPU based surround view. You can refer to Vision SDK release notes for more details on demos that are supported on each platform. Regards, Rishabh

Dear Rishabh, i know TDA2xx can support 3D AVM but its in linux base, i want to use RTOS base. Can use 3D AVM in RTOS base by tda2xx?

Hi Owen, 3D surround view is not supported on TDA2xx. There is no ISP hardware in TDA2xx. TDA2xx does have a 2D surround view that use RTOS. Please refer to PROCESSOR_SDK_VISION_03_03_00_00\vision_sdk\apps\src\rtos\usecases\lvds_vip_sv_standalone\. Regards, Rishabh

Dear Rishabh, thank your information, i have one more question : can run linux base 3D in tda2xx(4CH VIP LVDS capture + 3D SRV (SGX/A15) + DISPLAY - Only HDMI 1080p display supported)?

Yes this is correct. You can run linux based 3D surround view. Regards, Rishabh

Dear Rishabh, Thank you

Hi Owen, Kindly mark the post that answers your query as "This resolved my issue" and close the thread. Regards, Rishabh

Part Number: TDA2 hi，dear Could you tell where is this line below ？ which file？ this Line : tempoutPutList->objDesc[tempoutPutList->numObjects].objType = (label - 1); need to be changed to " (label - 1)%3 " when use case had 4 Classes change to 21 classes ? Tks

Hi, Please change in below file vision_sdk\apps\src\rtos\alg_plugins\objectdetection\objectDrawLink_algPlugin.c Regards Surya

Tks for sharing. I got the location with that line. And could you please show the location of the TIDL segmentation example ?

All Vision sdk examples are available in below folder vision_sdk\apps\src\rtos\usecases For TIDL Semantic segmentation UC -> semSeg For TIDL OD UC -> tidl_OD For TIDL File IO UC -> tidl Regards Surya

Ticket Name: TDA2EVM5777: Linux - eth0 device not found

Part Number: TDA2EVM5777 Hi. I am trying to set up an NFS shared folder using TDA2EVM5777. I'm working in a Linux environment, but the eth0 device doesn't appear. I checked the eth0 device through the "ifconfig -a" and "ls -l /sys/class/net/" commands, but the eth0 device does not exist. ================================================================================== root@dra7xx-evm:~# ifconfig -a can0 Link encap:UNSPEC HWaddr 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 NOARP MTU:16 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:10 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:98 lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1%132976/128 Scope:Host UP LOOPBACK RUNNING MTU:65536 Metric:1 RX packets:160 errors:0 dropped:0 overruns:0 frame:0 TX packets:160 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1 RX bytes:12160 (11.8 KiB) TX bytes:12160 (11.8 KiB) sit0 Link encap:IPv6-in-IPv4 NOARP MTU:1480 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) root@dra7xx-evm:~# ls -l /sys/class/net/ lrwxrwxrwx 1 root root 0 May 13 19:52 can0 -> ../../devices/platform/44000000.ocp/4ae3c000.can/net/can0 lrwxrwxrwx 1 root root 0 May 13 19:52 lo -> ../../devices/virtual/net/lo lrwxrwxrwx 1 root root 0 May 13 19:52 sit0 -> ../../devices/virtual/net/sit0 ================================================================================== However, I have confirmed that the network operates with the Ping command in U-Boot. (I have set up ipaddr, gatewayip, netmask with the setenv command.) So, there seems to be a problem with Linux settings. How can I find the eth0 device on Linux? In addition, I would like to modify the VisionSDK App and build it to update to the NFS shared folder. Do I simply change the app.out file? Or do I need more work to do? Regards, Lee.

Hi Lee, Based on the information you have provided it looks like probe of Ethernet device failed during linux boot. Can you please share linux boot logs and the dts file you are using? Thank you Regards Santhana Bharathi

Hi Santhana Bharathi, Attach my Linux boot log and dts files. 5432.boot.zip Regards, Lee.

I resolved this issue. It was a problem with the settings in my dts file. (ti_components/os_tools/linux/kernel/omap/arch/arm/boot/dts/dra7-evm.dts) The mac setting was "disabled", and after changing to "okay", the eth0 device is output normally. ============================================================================= root@dra7xx-evm:~# ifconfig eth0 Link encap:Ethernet HWaddr F0:B5:D1:0F:22:0C inet addr:192.168.1.150 Bcast:192.168.1.255 Mask:255.255.255.0 inet6 addr: fe80::f2b5:d1ff:fe0f:220c%132400/64 Scope:Link UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:12 errors:0 dropped:0 overruns:0 frame:0 TX packets:32 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:1316 (1.2 KiB) TX bytes:3132 (3.0 KiB) Interrupt:99 eth1 Link encap:Ethernet HWaddr F0:B5:D1:0F:22:0D UP BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1%132400/128 Scope:Host UP LOOPBACK RUNNING MTU:65536 Metric:1 RX packets:166 errors:0 dropped:0 overruns:0 frame:0 TX packets:166 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1 RX bytes:12688 (12.3 KiB) TX bytes:12688 (12.3 KiB) ============================================================================= Regards, Lee.

Ticket Name: TDA2: Network_RX dumping mjpeg files from network usecase

Part Number: TDA2 Hey, I have set up the capture_encode_network_rx usecase on the TDA2. All the captured frames are written into a file. I am able to open the written file with VLC but then I get only a single frame. According to the network documentation the network_rx command saves the data as mjpeg, thus I should be able to play it as a video when converting to avi or something. This does not seem to work though. How can I run that file seeing the captured video? best regards, nico

Hi Nicolas, Try playing with ffmpeg player Regards Surya

Ticket Name: J6EVM5777: RTOS / Getting Started

Part Number: Hi all. A few questions from someone new to this area. 1) The RTOS SDK supplied is of version 04.03.00.05, and SDK documentation is somewhat confusing. Nowhere could we find any references to DRA75x / TDA2x / EVM5777 devices. For example, referring here specifically to "Processor SDK RTOS 04_03_00_05" as available on the web at h t t p : // software-dl.ti.com/processor-sdk-rtos/esd/docs/04_03_00_05/rtos/index.html 2.1.6.1. Devices -- table does not list any of the above 2.2. Supported platforms and EVMs -- neither 1.1.6.2. Emulator support -- same thing 1.1.6.3. Is TDA2x is of any of the listed types? (AM335x, AM473x, AM57xx, AMIC110, C665x, C667x, C6747/OMAP-L17, C6748/OMAP-L138, and variants of K2 are listed as supported options). Similarly, at h t t p s : // training.ti.com/processor-sdk-training-series it is stated that: For more information on AM57x Sitara processors, refer to the AM57x Sitara™ Processors Training Series. For more information on TI ARM & DSP processors, refer to the KeyStone ARM & DSP Multicore Device Training Series For a high-level look at the AM57x Sitara evaluation module, view the Evaluate the New AM57x Sitara Processors with an EVM Based on the New BeagleBoard-X15 video. and we are pretty much at loss as what is the type of the TDA2x device and what sort of training should be taken for it. 2) SDK Getting Started manual refers to pre-built SD cards shipped with SDK located at [SDK Install Path]\processor_sdk_rtos_<platform>_<version>\prebuilt-sdcards\<evm>\sd_card_img\ but for our fresh install (CCS followed by SDK) this folder is empty. We have tried to "gmake all", which completed successfully, but it is still empty. Are there prebuild RTOS images? 3) Due to circumstances beyond our immediate control, we do not have access to JTAG emulator for the time being. Is there a way to configure CCS/SDK so that a compiled program is exported as an "app" that can be written to SD card along with MLO and ran (booted) from SD card? If yes, is there any tutorial available? Ideally, stdin/stdout in such deployment should be bound to UART. We totally understand all inconveniences and impossibilities associated with not having JTAG access to board. Thanks.

Hi Ramani, Your post seems to indicate that you are using a J6 EVM but I want to be sure. Could you please provide me with the following information so that we can check further on how to help you? Are you using a TI EVM for your development? If yes, which EVM is this? If no, please clarify the SoC on your custom board. Please provide the exact version of the SDK that you are using - if you downloaded it from ti.com, please provide link to be sure. If you are not using the latest version of the installer, please indicate why you chose that version. Logs and/or screenshots will be useful to describe some of the problems above, please considering expanding your post. Regards Karthik

Hello Karthik, 1. Above the original post there is a line "Part Number: J6EVM5777", in case you missed it. 2. The original message says "The RTOS SDK supplied is of version 04.03.00.05", in case you missed it. 3. N/A. The SDK was obtained by: -- googling for EVM5777 and landing at h t t p : // www.ti.com/tool/J6EVM5777 (I can not paste the URL intact as it gets expanded into a large icon immediately for some reason) -- following "Processor Software Development Kit for DRA7x Jacinto Processors -- Linux, Android, and RTOS" link at the very bottom of the page to arrive at h t t p : // www.ti.com/tool/PROCESSOR-SDK-DRA7X -- clicking on "Get Software" in "PROCESSOR-SDR-RTOS-AUTOMOTIVE-DRA7X" row to get to h t t p : // software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-rtos-automotive/latest/index_FDS.html -- and downloading ti-processor-sdk-rtos-automotive-dra7xx-evm-04.03.00.05-Windows-x86-Install.exe from that web page. No logs or screenshots are available, as no actual development have had been happened yet. Thank you.

Bump

Hi Ramani, Thanks, I checked further and it seems like our download page needs to be corrected. If your requirement is a RTOS SDK for TDA2 then you need to be looking at the following - http://www.ti.com/tool/PROCESSOR-SDK-TDAX, please download the PROCESSOR-SDK-VISION 3.08 and also the please look at the documents that this offers. If you have any further questions, please create a new thread if you have questions on this version of the SDK. Regards Karthik

Ticket Name: Linux/TDA2PXEVM: Implicit Declaration error while creating new usecase

Part Number: TDA2PXEVM Tool/software: Linux "/home/ubuntuadmin/visionSDK/visionSDK/vision_sdk/apps/src/rtos/common/chains_main_bios_misc.c", line 278: error: function "Chains_network_copy" declared implicitly 1 error detected in the compilation of "/home/ubuntuadmin/visionSDK/visionSDK/vision_sdk/apps/src/rtos/common/chains_main_bios_misc.c". >> Compilation failure /home/ubuntuadmin/visionSDK/visionSDK/vision_sdk/build/rtos/makerules/rules_m4.mk:178: recipe for target '/home/ubuntuadmin/visionSDK/visionSDK/vision_sdk/binaries/apps/tda2px_evm_bios_all/obj/app_libs/tda2px-evm/ipu1_0/release/chains_main_bios_misc.oem4' failed make[5]: *** [/home/ubuntuadmin/visionSDK/visionSDK/vision_sdk/binaries/apps/tda2px_evm_bios_all/obj/app_libs/tda2px-evm/ipu1_0/release/chains_main_bios_misc.oem4] Error 1 /home/ubuntuadmin/visionSDK/visionSDK/vision_sdk/build/rtos/makerules/common.mk:235: recipe for target 'ipu1_0' failed make[4]: *** [ipu1_0] Error 2 MAKEFILE.MK:277: recipe for target 'app_libs' failed make[3]: *** [app_libs] Error 2 Makefile:140: recipe for target 'apps_libs' failed make[2]: *** [apps_libs] Error 2 Makefile:38: recipe for target 'apps' failed make[1]: *** [apps] Error 2 --- Attempted and unsuccessful fixes: 1. Followed all steps mentioned in Vision_SDK_LinuxUserGuide - 2.4.2.1.4 - 'Download and untar filesystem'. 2. Followed Jacinda's solution with reference to https://e2e.ti.com/support/processors/f/791/t/706851?Linux-TDA2-Facing-issue-while-building-Vision-SDK-3-03 but I could not find the file named "install-extra.tar.gz" anywhere in TI's VisionSDK installation folder or on their Downloads page. I'm using Vision SDK Version 3.06 on Ubuntu 16.04 LTS and Spectrum Digital's TDA2PX EVM.

Hi Pallavi, 1. Is "Chains_network_copy" API added by you ? 2. Looking like you are building for MAKECONFIG=tda2px_evm_bios_all, but following Vision_SDK_LinuxUserGuide You should follow the steps mentioned in VisionSDK_UserGuide_TDA2px.pdf 3. For vision sdk 3.6 release, you don't need "install-extra.tar.gz" tar ball, it is part of file system now Regards Surya

HI Suryamani Jena, thank you for the clarification about install-extra.tar.gz. "Chains_network_copy" is added by me. issue was resolved by adding declaration in chains.h

Ticket Name: TDA2: Is it possible to implement tangent function in EVE?

Part Number: TDA2 Hi, I am porting an algorithm in plain C on EVE using kernel C which has 'tan' function into it. Is there a function or way to get the tan value in kernel C? Can it be implemented in VCOP? Regards, Shruti

Hi Shruti, You can use table lookup to implement tan function in kernelC on VCOP. You can store a 32KB table lookup in EVE memory. So if you want 16-bits fixed-point precision, you can store 16K elements. Would the loss of precision acceptable ? You could interpolate the results if you need more precision. regards, Victor

Ticket Name: Linux/TDA2: GPIO NUMBER

Part Number: TDA2 Tool/software: Linux Hi, How can i find the gpio number of a particular pin say gpio3_26 in tda2xx. I want to make that particular pin high from userspace (/sys/class/gpio). Kindly help me on this.

Hi Blessy, can you check if the following can help: e2e.ti.com/.../2605087 processors.wiki.ti.com/.../Linux_PSP_GPIO_Driver_Guide Regards, Yordan

As a side note to what Yordan suggests, you can also check the pinmux tool: It will help you identify the pins and gpios on them. thanks, Alex

Hi, Thankyou. Got it, by verifying with /sys/kernel/debug/gpio.

Ticket Name: RTOS/TDA2: How to driver UART2 to communication with PC?

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, As title. I don't know how to driver UART2 on TDA2 EVM. Could you please give me some advise? Many thanks.

Hi Prince, Are you using TDA2 EVM or custom board? Regards, Rishabh

Hi Rishabh, Both have.(TDA2x EVM and custom board)

Hi Prince, On TDA2 EVM you cannot use UART2 for communication as there is no connection between UART2 pins and FTDI chip. On custom board you have to check the schematics and find out if there is a route available for UART2. You also need to set the pin mux, IO expanders, etc depending on board schematics. Regards, Rishabh

Hi Regards, Thanks for your advise. I has setting UART2 TX, RX pin. TX = D26(UART2_TXD_0) RX = D28(UART2_RXD_4) But I don't know how to enable UART2 engine? have any example or API can use?

Hi Prince, The simplest method will be to modify and run CSL uart test present here: PROCESSOR_SDK_VISION_03_04_00_00\ti_components\drivers\pdk_01_10_00_08\packages\ti\csl\example\uart\uart_test. Regards, Rishabh

Hi Regards, Apologies to my late response. I set Y1,V2 pin mux to UART3 function. Y1 => UART3_TXD (uart3txd[0x00020000]) V2 => UART3_RXD (uart3rxd[0x00040000]) I has read register to confirm pin mux setting. I call UARTConfigInit() to initial UART3 engine after pin mux setting finish. but system get stuck problem when I call UARTConfigInit() API; Could you please give me some advise? Many thanks.

Hi Prince, In order to select UART3 you also need to set UART_SEL1_3 and SEL_UART3_SPI2. For more details please refer to board schematics. Regards, Rishabh

Hi Rishabh, Now I have't TDA2 EVM board can verify. I just only have custom board that direct connection out UART3_TXD(Y1) , UART3_RXD(V2) to using. We also pull up for UART3 TX, RX pin. Have any library can use if "PROCESSOR_SDK_VISION_03_04_00_00\ti_components\drivers\pdk_01_10_00_08\packages\ti\csl\example\uart\uart_test. " can't driver UART3 engine?

Hi Rishabh, Below schematic is UART part of coustom boart. For you reference.

Hi Prince, Mistakenly I assumed you want to enable UART3 in my previous response. As I had replied earlier there is no connection for UART2. For custom board you need to see full schematics and FTDI chip present in the board to see if UART2 connection is possible. This should be similar to "SH58 - FTDI UART" page present in TDA2 EVM schematics. Regards, Rishabh

Hi Rishabh, Now I will focus at UART3 of UART2 TX can transmit data that mean oscillator will capture waveform at TX pin. I has setting pin mux for UART3. But I can't find useful library or API to initial UART3. Because "PROCESSOR_SDK_VISION_03_04_00_00\ti_components\drivers\pdk_01_10_00_08\packages\ti\csl\example\uart\uart_test" library can't driver UART3 engine. Have other library can use? Thanks.

Hi Prince, You can't source UART3 from UART2 pins. You can use UART CSL driver for UART3 as well. UART test is an example written for testing different UART serial terminal configurations. You can modify this example to program appropriate board muxes for UART3 and then test UART3 as well. Hope this clarifies. Regards, Rishabh

Hi Rishabh, I will try to implement UART3 by UART CSL driver. Will create new ticket if I have concern. Appreciate your support.

Ticket Name: TDA2: TIDL import tensorflow model issue

Part Number: TDA2 hi，dear The same question with " https://e2e.ti.com/support/arm/automotive_processors/f/1021/t/692723 The detailed infor lists as following: I referred the section 3.6.5, optimized frozen graphs for MobileNet and tried to run the generated .pb but it's also showing error in tidl_log.txt file as : " TF Model File : ..\..\test\testvecs\config\tensorflow_models\mobilenet\mobilenet_v1_1.0_224_final.pb Could not find the requested input Data : MobilenetV1/MobilenetV1/Conv2d_0/Relu6 !! " It seems TIDL does not support the layer "MobilenetV1/MobilenetV1/Conv2d_0/Relu6" , right? Looking forward to your reply!

Yes, we may not have support in import tools, but TIDL library has support for Rlu6. So, you can modify import tool to import this Relu6 layer. Thanks, Praveen

Ticket Name: DRA75P: Need direct connect CSI2 Camera Module for J6 EVM, J6+ EVEM

Part Number: DRA75P Other Parts Discussed in Thread: TDA2, TVP5158 Is there an off-the-shelf CSI2 output camera module available for the J6/J6+/TDA2/TDA2+ EVM that mates directly to the CSI2 connector (J8 on J6+ EVM, J5 on J6 EVM)? That is, need a direct CSI2 connection without SERDES for development purposes.

Hi David, J6 does not support CSI interface, but you could connect LI based camera to LI input interface on TDA2x+ EVM. Rgds, Brijesh

Oh, right, I forgot that J6 did not have CSI2 and those ports I mentioned are for leopard imaging parallel output sensors. TDA2x+ and J6+ EVMs do have CSI2 expansion connectors (P15/J15). Do you mean that LI has a CSI2 output camera module that mates directly to the TDA2+ EVM?

Hi David, I dont remember exactly connectors. Is this J15 MIPI connector or LI connector? We can connect OV10640 LI based sensor on LI connector and OV2775 on MIPI connector. Rgds, Brijesh

Brijesh, According to the Processor SDK Linux Automotive Developer Guide we support the following: Supported cameras Camera Adapter Layer is used to capture video from CSI Camera. Currently the CAL driver supports following features. Processor SDK Linux Automotive release supports following sensors/cameras/video inputs:- OV10635 sensor - YUYV sensor on Vision board OV10635 sensor - YUYV sensor connected through LVDS OV10633 sensor - YUYV sensor connected on J6 EVM TVP5158 decoder - Support for decoding single channel analog video OV10640/OV490 - 720p CSI2 raw camera connected to OV490 ISP in YUYV format Processor SDK supports following sensors/cameras

My reply above got truncated... The OV2775 and OV10640 are both RAW output. We want YUV. Do you have experience with the OV10640/OV490 combo? Is it sold as a kit from LI? Do we have a sample configuration which sets up basic YUV output through the ISP or would customer have to figure all that out? Again, we were looking for a reference camera (CSI2, YUV, no SERDES) without needing to use the Vision SDK. Thanks,

Hi David, It is not supported on Vision SDK. It might be supported on Linux Let me check with the Linux team. Rgds, Brijesh

I checked with Leopard Imaging and they apparently do not offer a OV10640+OV490 combination with 36 pin connector to fit our EVM. Is someone on the Linux team familiar with the configuration mentioned in the SW Dev Guide?

The Linux team explained that the OV10640 + OV490 was custom made for TI and not available to customers.

Ticket Name: DRA76P: can ti RTOS support cache flush for a certain address for tda2/dra76x

Part Number: DRA76P Other Parts Discussed in Thread: TDA2 customer have video processing issues on DRA762/TDA2, when use VPE to process video data, vide data in buffer will be cached, after using hardware accelerate feature，parts of data in the cache is not flushed to data buffer, question: 1. is there any API in PDK to flush data cache by manual, when there has new data update in cache, flush it to data buffer by manual 2. if vide data in data buffer is cached, VPE enable HW acceleration function, is it possible that data update in CACHE not flush to DDR? if yes, is there any method to avoid Thanks

this is customer issue, please help check it and give solution, thanks

Hi Semon, VPE doesn’t have cache. Data is moved to DDR via VPDMA. TI-RTOS provide APIs for cache operations on M4 or C66x DSP. Regards, Stanley

Ticket Name: RTOS/TDA2: issue with generated tidl_net_jdetNet_ssd.bin and tidl_param_jdetNet_ssd.bin

Part Number: TDA2 Tool/software: TI-RTOS Hi, While using generated tidl_net_jdetNet_ssd.bin and tidl_param_jdetNet_ssd.bin files for TIDL usecase in TDA2X, video gets stuck after first frame. The tidl_net_jdetNet_ssd.bin and tidl_param_jdetNet_ssd.bin are generated using import tool which is available in PROCESSOR_SDK_VISION_03_06_00_00 in UBUNTU 16.04. Note: 1. I have used wine to execute import _tool.exe in UBUNTU 16.04 2. Default tidl_net_jdetNet_ssd.bin and tidl_param_jdetNet_ssd.bin available in SDK works fine. 3. After referring the link I understood default bin files available in SDK was generated using corresponding prototxt and caffemodel. so using those caffemodel and prototxt I generated the bin files . Is there any problem with my bin file generation? Kindly share your comments.

refer below thread for this e2e.ti.com/.../689617

Ticket Name: RTOS/TDA2: how does the four eve cores compute in parallel? and what does the link Alg_tidl_Dsp doing?

Part Number: TDA2 Tool/software: TI-RTOS

Each EVE core is running TIDL inference of SSD based objectedtion CNN network (expect the detection output layer). 4 images in parallel The last layer in the network ( detection output) layer is executed by DSP. For 4 images in sequentail.

Thank you, Kumer, I have trained a small CNN network (based on JacintoNet, with less layers and channels), which can run in 40ms on a EVE core. As you recommended, the DetectionOut layer should run on the DSP, My use case is as follows, is it right? Thank you, Jianjun.

Yes. This looks right

Ticket Name: TDA2EVM5777: TDA2X UART Speed

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello What is the max speed of UART in TDA2? I read in Spec that the speed is up to 12Mbps? so if we use 20MHz functional clock,uart speed will be 1.25M?

Hi, Theoretically yes - 1.25 Mbps, but you must be aware that 48 Mhz and 192 MHz clocks are also used for many other peripherals in the SoC which makes it almost impossible to set one of that clocks to 20Mhz. Regards, Stan PS See Figure 3-45. CM_CORE_AON Overview (b) in the TDA2 TRM document.

Ticket Name: TDA2EVM5777: Comparison between Sparse and Dense Model ?

Part Number: TDA2EVM5777 Hi, I have copied object detection trained models from caffe-jacinto-models github repo ( github.com/.../ssd512x512_ds_PSP_dsFac_32_fc_0_hdDS8_1_kerMbox_3_1stHdSameOpCh_1) And i am trying to compare the execustion time for Dense Model and Sparse Model. As per the datasheet, Sparse model execution must be faster than dense model. But, I am getting different result. Setup : 1. TDA2x EVM Board is connected to CCS using XDS560 JTAG. 2. Build and generated eve_test_dl_algo.out (release mode) for test app (in tidl folder) 3. Using CCS Load Program eve_test_dl_algo.out executed on EVE Output: 1. Sparse Model: TEST_REPORT_INIT_PROFILE_DATA : TSC cycles = 2117750600, SCTM VCOP BUSY cycles = 0, SCTM VCOP Overhead = 0 I/O Bytes : 0 ( 0 + 0 ) : 0 ( 0 + 0 ) Processing Frame Number : 0 TEST_REPORT_PROCESS_PROFILE_DATA : TSC cycles = 69244619476, SCTM VCOP BUSY cycles = 108141852, SCTM VCOP Overhead = 0 I/O Bytes : 0 ( 0 + 0 ) : 0 ( 0 + 0 ) - Execution Time = TSC cycles / EVE Frequncy - Considering only PROCESS PROFILE DATA - Execution Time: 129.4291953 seconds (EVE Frequncy: 535 MHz) 2. Dense Model: TEST_REPORT_INIT_PROFILE_DATA : TSC cycles = 3165035504, SCTM VCOP BUSY cycles = 0, SCTM VCOP Overhead = 0 I/O Bytes : 0 ( 0 + 0 ) : 0 ( 0 + 0 ) Processing Frame Number : 0 TEST_REPORT_PROCESS_PROFILE_DATA : TSC cycles = 62898624182, SCTM VCOP BUSY cycles = 275218342, SCTM VCOP Overhead = 0 I/O Bytes : 0 ( 0 + 0 ) : 0 ( 0 + 0 ) - Execution Time = TSC cycles / EVE Frequncy - Considering only PROCESS PROFILE DATA - Execution Time: 117.5675218 seconds (EVE Frequncy: 535 MHz) Whether this setup is correct ? Sparse Model execution time is more that Dense Model ? Regards, Sagar Attached Log: tidl_object_detection_eve_JTAG_emulation_log.zip

Hi Sagar, >>As per the datasheet, Sparse model execution must be faster than dense model. But, I am getting different result. Yes, but this not true for small image sizes as we optimised the dense convolution kernels (1x1 and 3x3) for small ROI processing. Please refer to FAQ 8 in the user guide for more information on these. Thanks, Praveen

Hi Praveen, If i want to reproduce the same result that TI has provided in the datasheet, Which models shall i compare and what should be procedure? Can you please provide me the link for Initial Model and Sparse Model ? And whether my setup (with JTAG) is correct to validate the same? Regards, Sagar

Hi Sagar, Please use the segmentation model bin files (jsegnet21) available in the release package to reproduce the profile numbers in datasheet. Link for models is github.com/.../caffe-jacinto-models. Yes, your setup looks fine. Thanks, Praveen

Hi I will check segmentation model files. But, I am specifically interested in object detection model comparison. Can you please share the link for that ? And I also While Importing, We get GigaMacs requirement for the model. Can we calculate the execution time for that model on EVE/DSP ? Assume that for a model GigaMacs requirement is 1.6 GMacs. And according to EVE datasheet , EVE can process 16 MACs per Cycle. So, Considering EVE Freq = 535MHz Execution Time = (Total Macs required / 16 ) * (1 / 535MHz) secs = 1.6 G /( 16 * 535 M) = 0.18 seconds Whether the above calculation is correct and Can we assume we will get actual execution time on board same or nearby to this value? Regards, Sagar

>> I am specifically interested in object detection model comparison. Can you please share the link for that ? Github link that I shared has both segmentation and SSD models. >> Whether the above calculation is correct and Can we assume we will get actual execution time on board same or nearby to this value? Yes, the calculation is correct, but considering the 16 MACs per Cycle is not correct, please refer to datasheet for actual MACs/cycle for different layers with different configuration. Do consider those values for calculating the execution time. Thanks, Praveen

Ticket Name: CCS/TDA2: if i install the SDK linux under the Linux Ubuntu then how i will open the ccsV8.0 in window.?

Part Number: TDA2 Tool/software: Code Composer Studio Hi i read the Vision SDK Linux User Guide. so now i understand that now i need to install the Linux Ubuntu in my laptop.so my question is that i need to install the CCSv8.0 on Linux or i already install the CCS on the window . so it mean i have to install the separate installation for linux and window . thank you

Hi Vijender, CCS has to separately installed in Windows and Linux. In case you are using virtual linux environment on Windows, you can work with mapped Windows drive and won't need separate CCS. Regards, Rishabh

Ticket Name: CCS/TDA2: How to find the target name in "Modify Build Target" window

Part Number: TDA2 Tool/software: Code Composer Studio Hi, i want to compile the u-boot in CCS linux plate form . i ref. that training link "training.ti.com/linux-board-porting-series-module-6-building-u-boot-ccs but i not able to find the Target name . please suggest the target name for TDA2x device. during build i found that error "10:52:24 **** Build of configuration Default for project u-boot **** make ARCH= arm CROSS_COMPILE=arm-linux-gnueabihf- tda2xx_evm_linux_all scripts/kconfig/conf --silentoldconfig Kconfig *** scripts/kconfig/Makefile:46: recipe for target 'silentoldconfig' failed *** Configuration file ".config" not found! Makefile:477: recipe for target 'silentoldconfig' failed *** *** Please run some configurator (e.g. "make oldconfig" or *** "make menuconfig" or "make xconfig"). *** make[2]: *** [silentoldconfig] Error 1 make[1]: *** [silentoldconfig] Error 2 make: *** No rule to make target 'arm'. Stop. 10:52:25 Build Finished (took 769ms)"

Hi Vijender, I am not sure how to compile u-boot in CCS, but in VisdionSDK for u-boot defconfig for TDA2x is used 'dra7xx_evm_vision_config' . Regards, Yordan

Hi Vijender, I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

thanks Yordan, Now this is working fine.

Ticket Name: CCS/TDA2EVM5777: I Can't not access a link on TIDeepLearningLibrary_UserGuide.pdf. Can I get a TIDL example project ?

Part Number: TDA2EVM5777 Tool/software: Code Composer Studio Hello, I trying to use TIDL. so I refer TIDeepLearningLibrary_UserGuide.pdf. But I can't access the link https://cdds.ext.ti.com/ematrix/common/emxNavigator.jsp?objectId=28670.42872.62652.37497 in 3.3.3 DMA utility Library the Error said below I'm just an individual(student). so I don't have team manager, program manager... How can I get CDDS account? or DMA utility Library? and I continued the UserGuide for "Building Sample Test Application" except 3.3.3 so I load "dsp_test_dl_algo.out" file. this is the result but I stopped step 9). there are no files in \test\testvecs\output sub-directory a file in \test\testvecs\referennce type is .bin so I can't check it Can I get a TIDL example project .zip file by email? reference [ˈrefrəns] Eng 1.reference [명사] ~ (to sb/sth) (… 에 대해) 말하기, 언급; 언급 대상, 언급한 것 2.reference book [명사] 참고 도서 3.with reference …을 참고로 하여 4.cross reference [명사] ~ (to sth) 상호 참조 (표시) 5.reference point [명사] (판단·비교용) 기준 6.참고 參考 reference, refer (to), consult 7.참조 參照 reference, consultation, refer (to), consult 8.언급 言及 reference, mention, refer (to), mention, make reference (to), make mention of 9.자료 資料 material(s), data (on); (참고 자료) reference 10.추천서 推薦書 (letter of) reference, (letter of) recommendation {"mean":["reference<br/><br/>[명사]\n\t\t ~ (to sb/sth)\n\t\t \t\t(… 에 대해) 말하기, 언급; 언급 대상, 언급한 것","reference book<br/><br/>[명사]\n\t\t \t\t참고 도서","with reference<br/><br/>…을 참고로 하여","cross reference<br/><br/>[명사]\n\t\t ~ (to sth)\n\t\t \t\t상호 참조 (표시)","reference point<br/><br/>[명사]\n\t\t \t\t(판단·비교용) 기준","참고\n \t\t\t參考<br/><br/>reference, refer (to), consult","참조\n \t\t\t參照<br/><br/>reference, consultation, refer (to), consult","언급\n \t\t\t言及<br/><br/>reference, mention, refer (to), mention, make reference (to), make mention of","자료\n \t\t\t資料<br/><br/>material(s), data (on); (참고 자료) reference","추천서\n \t\t\t推薦書<br/><br/>(letter of) reference, (letter of) recommendation"],"word":"\n\t\t\t\t\t\treference\n \t\t\t\n\t \t\n\t ","soundUrl":" dict-dn.pstatic.net/v

the first image is this and the second

Hi, DMAUTILS library is already included in VisionSDK and is located in <VSDK_DIR>\ti_components\algorithms\REL.DMAUTILS.00.08.00.02. Can you try to point DMAUTILS_PATH variable to this directory and give a try? Regards, Yordan

I retry step-by-step, and I got a new error in step 4, I got this error, and It said "cannot find the path specified" did I miss something?

Hi, Did you update the paths correctly in "makerules\config.mk" file? Thanks, Praveen

Ticket Name: TDA2EVM5777: TDA2EVM5777

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello I'm building a ADAS with TDA2 the OV10640 is in the TDA2 AVL but I want to use OV10642 the only difference between them is the optical filter so can I use OV10642 in TDA2? if yes is now TDA2 support parallel interface to OV10642? or when could TDA2 support parallel interface to OV10642? thank you

Hi, TDA2x supports only parallel interface as input interface. So you need to connect OV10642, which outputs over parallel interface. Please note that there is no ISP on TDA2x, so you could capture Bayer data, but there is no HW module to convert it into YUV format. Regards, Brijesh

Hi So TDA2x support OV10642 ,although it is not in AVL? thank you~

Again, only capture can be supported over parallel interface. you will require to add all other processing for this sensor on TDA2x Regards, Brijesh

I understand , OV10642 support parallel output is there OV10640 or OV10642 booting file for reference? thank you~

Hi, What is booting file? we have some register settings for OV10640 in folder VSDK_3_2\vision_sdk\apps\src\rtos\iss\src\sensor\ov10640. Rgds, Brijesh

Hello the difference between OV10642 & OV10640 is only RCCC & RGGB filter so we can use OV10642 by using the register settings for OV10640 in the SDK folder? thank you~

You need to check with omnivision, i am not sure what changes are required for OV10642.. Rgds, Brijesh

Hello OmniVision told us that OV10642 & OV10640 are same in register setting so could we use OV10642 by using OV10640 settings in SDK? thank you~

Yes, if omnivision says so. Rgds, Brijesh

Ticket Name: TDA2E: How I can access CDDS for necessary doc to learn how to program TDA2 ?

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Hi Sir Is any one can provide us a way to access CDDS for nessary docs? BR Jack

Hi Jack, Which document are you looking for? Most of TDA2 documents are on ti.com under the product folder. Regards, Stanley

Hi Stanley I need many docs from CDDS. But, I need these docs for now. Thanks BR Jack

Hi Jack, I will close this ticket and follow up with you offline. Regards, Stanley

ok, thx

Ticket Name: RTOS/TDA2PXEVM: How to use 2 ethernet mac port at same time in TI-RTOS(TDA2Px)?

Part Number: TDA2PXEVM Tool/software: TI-RTOS How to use 2 ethernet mac port at same time in TI-RTOS(TDA2Px)? Has TI got 2 ethernet mac port support in latest SDK? Our board is TDA2Px on TI-RTOS and SDK is [PROCESSOR_SDK_VISION_03_03_00_00] with one mac port(RMII1), but in chip manual it says there are 2 mac ports can be support, so we want to know how to use the two ethernet mac port at the same time and the download link for new SDK? document TDA2Px SoC for Advanced Driver Assistance Systems (ADAS) Silicon Revision 1.0 26.11.4.2 GMAC_SW Ports Ethernet Subsystem has three Ports. Port 0 is the Host port (internal to the Subsystem). Ports 1 and 2 are the external ports connected to G/MII, RGMII, or RMII interfaces as per the interface selected. Naming conventions followed in this chapter: • Port0 is referred to the Host Port • Port1 is referred to the interfaces GMII0/RGMII0/RMII0 • Port2 is referred to the interfaces GMII1/RGMII1/RMII1

Hi Mi Zhou, The dual Ethernet port facility will be made available in a subsequent release of PROCESSOR_SDK_VISION. In the mean time, can you please let me know what exactly will be the usage of dual Ethernet ports in your application? If it turns out to be a solvable issue with the current setup, I might be able to help you. In that case, you wouldn't have to wait for the release. Regards, Anand M

Hi Anand When could you release the PROCESSOR_SDK? We need to use both the two mac port, one for video data and another for debug data, both of two cost large data transparent. also they need full IP-Stack support(both UDP and TCP) It seems [PROCESSOR_SDK_VISION_03_03_00_00] can not support the request, so I need your new SDK.

Hi Mi Zhou, The dual Ethernet Port feature will be made available on the next release of PROCESSOR_SDK_VISION. It will be released by mid January. Is there anything more I can help with? Regards, Anand

OK Thanks.

Ticket Name: CCS/TDA2: i installed Ubuntu 16.0 instead of Ubuntu 14.0 . will i face any problem in future?

Part Number: TDA2 Tool/software: Code Composer Studio Hi i want to work on the open GL on TDA2x. so i need to install the linux on my machine but i installed ubuntu 16.0 instead of Ubuntu 14.0. because in SDK linux user manual clearly mention that installed 14.0. please suggest me what should i do now ? continue with the 16.o or remove with 16.0 thank you

Hi Vijender, We have done all our testing with Ubuntu 14 but Ubuntu 16 should also work. Regards, Rishabh

Hi, Is there an update on this? Regards, Rishabh

Ticket Name: TDA2XX : radar usecase.sample width=512,doppler point =512,2tx enable

Other Parts Discussed in Thread: TDA2 (1)Hi expert: vision SDK 3.8,four awr1243 + TDA2 CHAINS_CASCADE_BF_RADAR_PROFILE1_RADAR_WIDTH ( 511U ) :.sample width CHAINS_CASCADE_BF_RADAR_RADAR_HEIGHT (512 U ) doppler point =512 2tx enable: TDM-MIMO EVE can work,but DSP core can't get linkipc data. could you help me with my problem?

Ticket Name: TDA2: TIDL Simulator for DSP

Part Number: TDA2 Hi, is there the DSP/c66 equivalent of this simualtor - eve_test_dl_algo.out sim.txt
 I searched and could not find it please let me know, thank you! .luca

Hi Luca, there is "dsp_test_dl_algo.out", in ti_components\algorithms\REL.TIDL.01.01.02.00\modules\ti_dl\test\out directory. You can check chapter "3.3.4 Building the Test Application Executable through GMAKE" in TIDeepLearningLibrary_UserGuide.pdf for rebuilding steps if you need. Regards, Yordan

Hi thank you Yordan ~ this helped me a lot though I'm still not able to compile fully ~ I get this - luca@doppio test make TARGET_BUILD=debug TARGET_PLATFORM=PC all g++: error: ../../ti_dl/lib/PC/dsp/debug/tidl_algo.lib: No such file or directory /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.TIDL.01.01.02.00/makerules/rules.mk:603: recipe for target 'outfile' failed make: *** [outfile] Error 1 luca@doppio test g++ -o ./out/dsp_test_dl_algo.out /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.TIDL.01.01.02.00/out/PC/dsp/debug/modules/ti_dl/test/./src/report_utils.obj /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.TIDL.01.01.02.00/out/PC/dsp/debug/modules/ti_dl/test/./src/tidl_config.obj /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.TIDL.01.01.02.00/out/PC/dsp/debug/modules/ti_dl/test/./src/tidl_tb.obj /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.TIDL.01.01.02.00/out/PC/dsp/debug/modules/ti_dl/test/./src/tidl_image_preproc.obj /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.TIDL.01.01.02.00/out/PC/dsp/debug/modules/ti_dl/test/../../../common/configparser.obj /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.TIDL.01.01.02.00/out/PC/dsp/debug/modules/ti_dl/test/../../../common/ti_draw_utils.obj /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.TIDL.01.01.02.00/out/PC/dsp/debug/modules/ti_dl/test/../../../common/ti_mem_manager.obj /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.TIDL.01.01.02.00/out/PC/dsp/debug/modules/ti_dl/test/../../../common/cache.obj /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.TIDL.01.01.02.00/out/PC/dsp/debug/modules/ti_dl/test/../../../common/profile.obj -m32 -lstdc++ -static ""../../ti_dl"/lib/PC/dsp/debug/tidl_algo.lib" /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.DMAUTILS.00.08.00.02/dmautils/libs/PC/dsp/debug/dmautils.lib g++: error: ../../ti_dl/lib/PC/dsp/debug/tidl_algo.lib: No such file or directory -- when looking for ti_dl/lib/PC/dsp/debug/tidl_algo.lib - I cannot make it because I have no "algo" source code to build the lib -- as in here luca@doppio ti_dl pwd /home/luca/tools/PROCESSOR_SDK_VISION_03_05_00_00/ti_components/algorithms/REL.TIDL.01.01.02.00/modules/ti_dl luca@doppio ti_dl make CORE=dsp TARGET_BUILD=debug TARGET_PLATFORM=PC all . ======== tidl ALGO ================= make -C ./algo -f makefile make[1]: *** algo: No such file or directory. Stop. makefile:76: recipe for target 'all' failed make: *** [all] Error 2 luca@doppio ti_dl ls docs inc lib makefile test utils -- maybe there is a binary version I can download somewhere? also section 3.5.2 of the TIDL_UG says >> Build with below setting (in “tidl_alg_int.h” file) to build the code to run the inference faster on but I don't have that source file anywhere ~ and the doc specifically mention I need it to modify it (page 3-9) can I get help in finding a place to download those files? thank you so much! .luca

"eve_test_dl_algo.out sim.txt" May I know what is the meaning of sim.txt here. TARGET_PLATFORM=PC is suported for source release. Only objcet release is avaialble in VSDK package.

Hello! I also meet this problem that i cannot find the algo folder. Did you resolve this? Thank you !

EVE simulation will functionally match with DSP simulation. so there is no need to build the DSP version. Regarding algo folder, it is not available with object release.

Ticket Name: Linux/TDA2: A15 how to test CPU usage rate

Part Number: TDA2 Tool/software: Linux i am using SDK_VISION_03_04_00_00 i run my algorithm on a15 how to test CPU usage rate? BESTWISHES Shuai

Hi Shuai, in VisionSDK-Linux you would not be able to measure A15 by pressing 'p' as for the other cores. You can use any of the standard Linux tools (such as top, htop, vmstat ...). You can check this thread for more details: e2e.ti.com/.../709101 Regards, Yordan

Ticket Name: Linux/TDA2: TDA2XX Vision SDK

Part Number: TDA2 Tool/software: Linux Hi， TDA2XEVM board have Connectors and Transceivers，with Video output interface： one HDMI Out, one FPD-Link III, one LCD. CPU Board Block Diagram have VOUT3 interface，As shown below.but I see all of the Use case in VisionSDK_DataSheet.pdf, Display on LCD or HDMI capture and HDMI display are also supported. I want to know which Use case Video output use VOUT3 interface?and I want to Let VOUT3 be the video output interface，what should I do？ Regards, YCC

Is any display device connected on vout3? Then it would be supported in VSDK.. Rgds, Brijesh

because all use case use VOUT1 port (connect LCD) or HDMI port (Display can be on HDMI display via HDMI output port).They are not use VOUT3 port .So I want to know how to use VOUT3 port. Can it connect LCD or HDMI display device?Can you give me a use case that use VOUT 3 port ? Thank you! Regards, ycc

Please check schematic and see if anything connected to LCD3 output.. It can be enabled only if some display is connected.. It can be enabled in ChainsCommon_SetDctrlConfig in the file vision_sdk\apps\src\rtos\usecases\common\chains_common.c file.. Rgds, Brijesh

Hi，Brijesh VOUT3 connected a LVDS monitor ,The model of lvds is user-customized.Interface chip used is DS90UB940. How can I set it up？Which documents should I refer to? Regards, Ycc

Hi， VOUT3 connected a LVDS monitor ,The model of lvds is user-customized.Interface chip used is DS90UB940. How can I set it up？Which documents should I refer to? Regards, Ycc

Hi YCC, Give me some time, i will come up with the exact steps required for vout3 addition.. Rgds, Brijesh

Hi Brijesh, Thank you for providing the requested information. How the work progresses about the use of VOUT3？I urgently need the help of this questions. Thank you for your attention to this matter. I am looking forward to your reply. Regards, Ycc

Hi , I haven’t received your reply for a long time. How the work progresses about the use of VOUT3？I urgently need the help of this questions. Thank you for your attention to this matter. I am looking forward to your reply. Regards, Ycc

Hi YCC, Could not get time to check it. Will check it tomorrow and get back to you. Rgds, Brijesh

Ticket Name: 8CH 720P capture on TDA2

Other Parts Discussed in Thread: TDA2 Hi all, I want to capture 8CH 720P with YUV422 8bit discrete sync mode on TDA2. My scenario is 4CH for 3D AVM, 2CH for side view, 1CH for front camera and 1CH for rear camera. It should be no problem when run in different situation. Otherwise, the above scenario happens simultaneously. I think the ddr bandwith should be the limitation. Could you please help to comment more about it? Thanks in advance. B.R. OC

Hi, Your question has been forwarded to an expert. Best regards Lucy

Hi Lucy, Any update? B.R. OC

Hi, Just sent a reminder. Best regards Lucy

OC, Sorry for late reply. I think this is doable with VIP1 and VIP2 as far as its 8bit YUV (Port B on each slice supports only 8 bit). DDR bw would also depend upon how your algorithms are operating, you can configure bootloader in dual emif interleaved mode to get maximum DDR banwidth if you want to run all this simultaneously. But when its not all simultaneously, I don't see a problem.

Please note that if you are using discrete syncs, 2 pins for each ports are available. and if you are using embedded sync, sync codes must be in bt656 format. BT1120 codes over 8bit interface is not supported. Rgds, brijesh

Hi Yogesh, Thanks so much for your input. It's clear to me. B.R. OC

Ticket Name: TDA2SX: Memory access error when EVE read address more than 512MB DDR

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi expert, Customer used 512MB on TDA2 before while they increased DDR3 to 1GB recently. After modified EMIF and DMM configuration in gel file, we could access 0xB5000000 on DSP and ARM in CCS memory watch page. But on EVE, it reported error as below. Could you please suggest what we need to do to make EVE access correct? Thank you.

Hi, You have to update the EVE MMU mapping in GEL file. The max page size per entry in EVE MMU is only 16MB. Regards, Stanley

Ticket Name: TDA3: Presbl

Part Number: TDA3 Hi Sir, Is there any presbl code included like sbl in vision low TDA3x controller? Regards, Sagar

Hi Sagar, I did not fully understand the question. Are you talking about ROM bootloader? Regards, Rishabh

Hi Sir, Actually in TDA2x i.e vision high there is no need to initialize QSPI while copying from external SDF. But inTDA3 i.e vision low there is need to reinitialize QSPI to do the same. Why? Also there is one presbl main function in which QSPI is initialized. So why there is again initialization of QSPI? Regards, Sagar

Hi Sagar, SBL needs to initialize QSPI as per its need. And the same is done in both TDA2/TDA3 SBL. SBL will set QSPI in 4 bit memory mapped mode. It will also change the clock to max possible for best throughput. Hope this helps. Regards, Rishabh

Ticket Name: RTOS/TDA2: TDA2X: PVR:(Error): WSEGL_InitialiseDisplay: Failed to open primary device: No such file or directory [0, ]

Part Number: TDA2 Tool/software: TI-RTOS Hi We are using tda2x self-designed boad , vision sdk (PROCESSOR_SDK_VISION_03_02_00_00). First we run the demo NullSrc + Decode + Display (Only 1920x1080 H264/MJPEG Video Input Bit-Stream Supported) everythig is ok. But when we run the demo 1CH VIP capture + SGX Copy + DISPLAY , we got error log as follows: [HOST] [HOST ] Single Camera Usecases [HOST] [HOST ] ------------------------ [HOST] [HOST ] 1: 1CH VIP capture + SGX Copy + DISPLAY[liuke Removed SGX Copy] [HOST] [HOST ] 2: 1CH VIP capture + Encode + Decode + SGX Copy + DISPLAY [HOST] [HOST ] 3: 1CH VIP capture + Alg FrameCopy (EVE1) + SGX Copy + DISPLAY - (TDA2xx ONLY) [HOST] [HOST ] 5: NullSrc + Decode + Display (Only 1920x1080 H264/MJPEG Video Input Bit-Stream Supported) [HOST] [HOST ] 6: 1CH VIP capture + Alg Frame Copy (A15) + SGX Copy + DISPLAY [HOST] [HOST ] 7: 1CH VIP + Alg Frame Copy (A15) + Connetor Links (Dup, Merge, Select, Gate on A15) + SGX Copy + DISPLAY [HOST] [HOST ] [HOST] [HOST ] x: Exit [HOST] [HOST ] [HOST] [HOST ] Enter Choice: [HOST] [HOST ] 1 [HOST] [HOST ] 53.101018 s: [HOST] [IPU2 ] 53.106783 s: CAPTURE: Create in progress !!! [HOST] [IPU2 ] 53.107210 s: CAPTURE: VIP1 Slice0 PortA capture mode is [ 8-bit] !!! [HOST] [HOST ] 53.229091 s: IPC_IN_0 : Create in progress !!! [HOST] [IPU2 ] 53.227993 s: CAPTURE: Create Done !!! [HOST] [IPU2 ] 53.228512 s: IPC_OUT_0 : Create in progress !!! [HOST] [IPU2 ] 53.228817 s: IPC_OUT_0 : Create Done !!! [HOST] [HOST ] 53.229518 s: IPC_IN_0 : Create Done !!! [HOST] [HOST ] 53.229610 s: SGXFRMCPY: Create in progress for resolution: 1920x1080 !!! [HOST] [HOST ] 53.229671 s: SYSTEM_PVRSCOPE: FIFO /opt/vision_sdk/gpufifo opened successfully PVR:(Error): WSEGL_InitialiseDisplay: Failed to open primary device: No such file or directory [0, ] EGL: eglInitialize() returned 0 EGL: after eglInitialize() eglError (0x3001) ASSERT (sgxFrmcpyLink_drv.c|SgxFrmcpyLink_drvDoProcessEglInfo|219) [HOST] [HOST ] 53.484322 s: EGL: version 6.1745188 [HOST] [HOST ] 53.484322 s: EGL: eglInitialize() failed !!! highly appreciate your help, thanks. !!!

hi NullSrc + Decode + Display does not use GPU and any camera capture. Are you using TDA2x EVM? what is the camera module;e you use? did you built the VSDK Linux as per the UG - VisionSDK_Linux_UserGuide.pdf, please check again regards, Shiju

Ticket Name: TDA3MV: [TIDL]is there sematic segmentation, object detect usecase for TDA3?

Part Number: TDA3MV Other Parts Discussed in Thread: TDA2 Dear Champs, It seems there are 'segmatic segmentation' and 'object detect' usecase only for TDA2 in VisionSDK. Can these usecase be used for TDA3? Could you please provide advice how customer can modify these usecase for TDA3 in VisionSDK? Thanks and Best Regards, SI.

Hi SI, Yes these use cases can be run on TDA3. The use case needs to be updated to have only one EVE and not four EVEs. Regards, Rishabh

Rishabh, Thanks for your confirm. Then, is it possible to modify parameters of makefile or should customer modify the source to run it on IPU? When I checked the usecases, it seemed the applications will be run on A15 ARM core. Thanks and Best Regards, SI.

Hi SI, TIDL library mainly runs on C66x and EVE cores. Customer needs to modify the use case for change in number of EVEs and it seems that source code changes will be needed for Alg plugin as well. I would suggest you to wait till next week for exact changes as use case expert is OoO this week. Regards, Rishabh

Ticket Name: TDA4VM-Q1: does RTOS Processor SDK for Radar support TDA4?

Part Number: TDA4VM-Q1 Other Parts Discussed in Thread: TDA2 TI PROCESSOR-SDK-RADAR supports TDA2x & TDA3x does it support TDA4x? do you have plan to support TDA4X? we plan to design 4D imaging radar using cascaded mmWave sensor. what kind of processor is the best choice? TDA2, TDA3, or TDA4? what is the life cycle of TDA2 and TDA3? Thanks

Hi, There is no plan to create Radar SDK for TDA4. You can connect Radar to TDA4 to get object data with UART/SPI, but not raw data via CSI2. We don't have device driver support for Radar on TDA4. For TDA2 and TDA3, we are no longer making any more SDK release. However, our Radar BU is actively supporting cascade radar solution. I would recommend you to reach out to our Radar team for device selection. Regards, Stanley

Ticket Name: TDA2SG: tda2 McSPI interface

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Hi, two questions Q1： The normal McSPI MOSI data trace should be low in the leisure state. However, some small packets have been detected on the MOSI data trace. How do we optimize software? (MOSI: see green curve, CLK: see yellow curve) TDA2 internal and external interfaces are known to be pulled up to the same power source Q2：We measured the timing of McSPI with an oscilloscope and found that the specifications were not met，How do we optimize software? TDA McSPI operation mode: PHA = 0, POL = 0 The MOSI data is based on the falling edge of the CLK clock, and SM6 = 166.4ns is measured, which does not meet the requirements of SM6 = +-5ns.

Hi, Which software are you using for the McSPI? Is McSPI configured as master/slave? Are you using the TI EVM or a customer board? What is connected to the McSPI? Regards, Prasad

Hi Prasad， We use vision-sdk software version number is ROCESSOR_SDK_VISION_03_07_00_00. The McSPI interface of TDA2 is configured as the master. Tested on our own board. A level conversion chip is connected to McSPI of TDA2, and the other end of the chip is a MCU，and the waveform measured by the MCU is normal.

Hi, Is the data sent from the McSPI/SoC is received at the mcu correctly or there is any data corruption? Also Is the data sent from mcu received by the McSPI IP/software correctly? Is the signal measurement done near to the SoC (before the level shifter)? Regards, Prasad

Ticket Name: TDA2SX: TDA2 SX customer wants to know how to run-time low down the CPU speed.

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi Champs: Customer made their own TDA2 SX PCB. please see this PDF page 43. https://www.ti.com.cn/cn/lit/an/sprac22/sprac22.pdf?_ticdt=MTYwNjE5Mzc0M3wwMTc1ZjJkZGQyMzYwMGEwMTkzMTI0OTUwOWYwMDMwNzMwMDEzMDZiMDA5Nzh8R0ExLjIuNDU5MTY4NDIwLjE2MDYwOTc0MjZ8MA This customer wants to low down the CPU speed when CPU is running. They know how to low down the CPU speed while in SPL stage. However, if the CPU is over-heat during run-time, how to low down the CPU speed while in system running stage not the Booting stage? please provide the solution in detail. THanks. BR Rio

Hi Rio, Do they have CPUREQ/CPU DVFS enabled? Best Regards, Keerthy

Ticket Name: RTOS/TDA2SX: TDA2XX: enable OPENCV undefined reference ti_sysbios_family_arm_a15_Cache_wbInvAll__E

Part Number: TDA2SX Other Parts Discussed in Thread: SYSBIOS Tool/software: TI-RTOS Hi, I would like to build image the OPENCV Usecases enable AVB_INCLUDE with the latest SDK (Ver: [DEV_VISION_SDK_03_07] on TDA2XX EVM(ES 2.0/Board Rev A). So I configured OPENCV_OPENCL=yes, AVB_INCLUDE=yes, NDK_PROC_TO_USE=Ipu1_1 in the file of cfg.mk" under tda2xx_evm_bios_all folder. Then rebuild vision_sdk, it show that the error message: /home/sam/proj/TI_SDK_VISION_V03_07/ti_components/open_compute/opencl_rtos_am57xx_01_01_10_00/packages/ti/opencl/usr/lib/libOpenCL.a(shmem_rw_policy_rtos.cpp.obj shmem_rw_policy_rtos.cpp:(.text+0x23c): undefined reference to `ti_sysbios_family_arm_a15_Cache_wbInvAll__E BTW, There is a 1GB DDR_MEM on TDA2XX EVM, I would like to increase the memory size by replace DDR_MEM=DDR_MEM_512M (default) with DDR_MEM_1024M. Could you help teach me how to configure for the Usecases? Thanks. regards, Sam Hsieh opencv_cfg_n_log.rar

Hi Sam, can you set MAKECONFIG=tda2xx_evm_bios_opencx under Rules.make and see if you face any problems? Regards, Yordan

Hi Yordan, Thank you for your feedback. After change MAKECONFIG=tda2xx_evm_bios_opencx, I could rebuild image successfully [make depend;make vision_sdk;make appimage; make sbl;]. But It got the error message then system halts after boot from SD card. Putting MPU CPU1 in Off mode, Jumping to MPU CPU0 App ...0x8980514c Could you help teach me why it result in the MPU in Off mode, how to fix it? Thanks. regards, Sam. opencx_log_20190627.txt 
 TDA2xx SBL Boot
 Ver:Jun 27 2019 10:28:50

 DPLL Configuration Completed

 Clock Domain Configuration Completed

 Module Enable Configuration Completed

 TI EVM PAD Config Completed

 DDR Config Completed

 App Image Download Begins

 SD Boot - file open completed successfully

 MPU CPU0 Image Load Completed

 IPU1 CPU0 Image Load Completed

 DSP1 Image Load Completed

 App Image Download Completed

 SBLLibMPUCPU1BringUp: Enter !! Entry:0x0 mode=0x0

 Putting MPU CPU1 in Off mode

*****************************************************************

 PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles

 SBL Initial Config Cycles - 166844  (14.23 ms)
 SOC Init Cycles - 170897  (14.58 ms)
 DDR Config Clock Cycles - 43652  (3.72 ms)
 App Image Load Cycles - 36849805  (3144.51 ms)
 Slave Core Bootup Cycles - 110039  (9.38 ms)
 SBL Boot-up Cycles - 37342300  (3186.54 ms)
 Time at which SBL started IPU1_0 - 113350  (3459.16 ms)

 Jumping to MPU CPU0 App

...0x8980514c

Hi Yordan, BTW, as the answer of the question (RTOS/TDA2: A15 SMP feature conflict with OpenCX), Currently both OpenCX and A15 SMP feature not supported on Vision SDK BIOS. I traced the SBL parse & load the Applmage, it run normally before jump the entrypoint of mpuCore0EntryFuncPtr(). At the same time, I tried to dump the vision_sdk_a15_0_release.xa15fg.rprc, the address of core is OK. Why it couldn't run the AppImage normally? Could you help feedback the issue? Thanks. BRs, Sam.

Hi, We do not support opencv or opencx since past a few releases. Still first you can try without changing your DDR_MEM config. Regards, Anuj

Ticket Name: TDA2: On the optimization of tda2x

Part Number: TDA2 The tda2x platform can Implementation pipeline between multiple cores, such as capture.....algorithm1(dsp1)->algorithm2(dsp2)->algorithm3(eve1 and eve2)......dispay frame(1) frame(2) -> frame(1) frame(3) -> frame(2) -> frame(1) frame(4) -> frame(3) -> frame(2) Is my idea feasible? Thanks! Mary

Hi Mary , is it that the same frame needs to be passed to alg 1 on dsp1 , alg 2 on dsp2 , alg 3 on eve1 , alg 4 on eve 4 and then to display . ? Yes it can be done , Regards Chetan.M

Hi, Chetan.M Yes, same frame needs to be passed to alg 1 on dsp1 , alg 2 on dsp2 , alg 3 on eve1 , alg 4 on eve 4 and then to display. 1280x720*3 (RGB) size image, data transfer between different cores. such as from dsp(1) to eve(1), How long will it take? Thanks! Mary.

Hi Mary, IPC latency between cores will be less than 1 millisec Regards Chetan.M

Hi Chetan.M, Thank you very much for your reply Optimization method: 1. sparse matrix 2. floating-point to fixed-point ， Data aligned read and write 3. application instruction set 4. use DMA to external memory (SDRAM) data transmission to L2 5. single cycle, pipeline. The above is the optimization of DSP. Are there any other optimization methods besides these? How can EVE be optimized? thanks! Mary

Hi Mary , Please close this thread and start another thread for optimization , DSP and EVE experts will help you out . You can also refer the the user guide and developer guide in docs folder for more details of components Regards Chetan.M

Ticket Name: TDA2: How SPI+emda is configured and used in vision SDK

Part Number: TDA2 Suppose I'm working on SPI salve+edma under IPU2 in startware, can it work when transplant it to IPU2 （main app） under VISION SDK, but i find it cannot work for the EDMA conflict, because each core call UtilsEdma_init under VISION, how should I avoid conflict, or how to configure EDMA +spi in VISION SDK, thank you very much!

Hi, You should replace the starterware EDMA calls with EDMA LLD calls in order to use the same by the main app in Vision SDK. I hope you understand that you can't make it a use case as you don't have any link for SPI slave + edma. Regards, Rishabh

HI,Rishabh THANK you for your Reply! I want to create a always running task for spi receive ,not in link. I have some problem as follows : 1，can i use the BSP example "bsp_examples_mcspiLoopback_target" transplant it to IPU2 （main app） under VISION SDK 2，BSP example "bsp_examples_mcspiLoopback_target" why can work well in IPU1 ，but Work is not normal in IPU2，so I want to know how to set in order can work in different core。 Regards, KOKO

Hi, First you should try to port bsp_examples_mcspiLoopback_target to IPU2 and run it using gel. You might need to set up AMMU, interrupts, etc. Then you should try to run it from Vision SDK. Regards, Rishabh

Ticket Name: TDA2PXEVM: Questions regarding image processing tools and optimization of semseg on EVE's

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hi Dear TI, I have some thought provoking questions regarding tda2 and tidl. I have successfully implemented semseg with 2EVEs on tda2px. Now I have these following questions for which I need detailed answers. 1. As far as I understood, I cannot use opencv due to performance issue for image processing. Therefore, the only option I am left with is either vlib or eve_sw. I wanna ask, among them, which one is more suitable and closer to opencv. This arises another question 2. If I use eve_sw, my computational requirement is already occupied by the semseg, so I believe that I can only use vlib as it is for dsp. Please put some light on it. 3. Now, the third question is: How can I optimize the semseg so that I can use only one EVE to make it run on more than 10fps. What are the possible way which can contribute to fulfill this purpose. 4. Finally, I wanna ask, how can I check the memory consumed by tda2 while running the network or any usecase. I can calculate the theoretical value by converting it from the PC memory usage while inference and converting it for the tda2. However, I actually wanna see the practical value printed by the tda2 on the fly. Thank you once again, will be waiting for your detailed answers. With best regards, H. M. Owais

Hi Owais, 1 & 2. You can use vlib. 3. There is no further optimization possible in the Semseg use case on one EVE, you need to more EVE's in parallel to improve fps. 4, You can refer to "tidl_tb.c" for all the allocated buffers. Thanks, Praveen

Hi Praveen, Thank you for reply. Regarding your answer 3, as per my understanding the network structure contributes towards the performance on tda2. So I want to rephrase my question: The question is whether the network structure can enhance the performance (i.e. the fps), using the same usecase? If so, would you like to give any suggestions on it? If, we build another usecase, what are the things need to considered to increase the performance? Once again, my goal is achieve the highest fps on minimum number of EVEs. What are the possible choices do I have on your current platform. With best regards, H.M. Owais

Hi Owais, Yes, the network structure can enhance the performance. For that you can use example scripts for training sparse models from Caffe-jacinto github link (https://github.com/tidsp/caffe-jacinto-models) and try couple of thimgs suggested below, 1. You can try to increase sparsity in the model 2. You can try to decrease the number of layers and use more convolution layers 3. You try to reduce the resolution of feature sixe if possible use sizes multiple of 32 Thanks, Praveen

Ticket Name: TDA2: What is B15 of TDA2 relative with vision board ?

Part Number: TDA2 Hi Sir, We will design new EVM board and use Cam1 port to capture image frame(parallel to parallel). But we don't know what relative B15 of TDA2 with Cam1 ~ Cam6 of vision board. Could you please give us advice or more information? Thanks for your support.

Hi, Prince Kuo, I am not sure that I understood your question. Numerations B15, A15, etc. are the BALL NUMBERs. BALL NAMEs are mcasp2_axr0, mcasp2_axr1. For all list of the correspondence between BALL NUMBER and BALL NAME see the Table 4-2. Ball Characters in Data Manual document. Regards, Mariya

Hi Mariya B15 in EVM looks like to be use as a detection of vision board if we don't need to detect the the vision board because we put camera & SoC on the same board, the function of detecting vision board could be turned off by software? thank you

Hi, We do not use this pin. For detecting the multi deserializer board we do a probe one of the slaves in the multi deserializer board at address 0x25. You can refer the Bsp_boardGetIdTda2xx() function in <pdk_install_dir>\packages\ti\drv\vps\src\boards\src\bsp_boardTda2xx.c. Regards, Prasad

Ticket Name: TDA2: Source code of SFM

Part Number: TDA2 Recently，I have been reading the vision SDK of TDA2 ，and know TI has finished SFM（structure-from-motion）algorithm based eve and DSP，I found some core module is not open source，and some question to ask as shown below 1.Whether or not all code of SFM is open soure , and any open plan? 2.How can I get down these open source? Thank you !

SFM algorithm only available as object form (Libarary). No plans to make it open source. Regards, Kumar.D

Ticket Name: Linux/TDA2: TDA2 - 'Undefined reference Error'

Part Number: TDA2 Tool/software: Linux Hi, I am working with VisionSDK 3.1. I am trying to add a new usecase in vision_sdk/apps/src/hlos/adas/src/usecases. The main function that I have used is Void chains_lvdsVipMultiCam_opencvcanny_SgxDisplay(Chains_Ctrl *chainsCfg) which is defined in the corresponding usecase .c file. This function was called in vision_sdk/apps/src/hlos/adas/src/common/chains_main.c which includes a header #include <src/hlos/adas/include/chains.h>. The function was declared in the above mentioned header. While compiling I am getting the following error. # apps: tda2xx-evm: Creating archive apps.a # apps: tda2xx-evm: Linking /home/vkchlt0160/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/lib/tda2xx-evm/a15_0/release/apps.a(chains_main.o): In function `main': chains_main.c:(.text.startup+0x1ee): undefined reference to `chains_lvdsVipMultiCam_opencvcanny_SgxDisplay' /home/vkchlt0160/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/lib/tda2xx-evm/a15_0/release/links_a15_algorithm.a(algorithmLink_cfg.o): In function `AlgorithmLink_initAlgPlugins': algorithmLink_cfg.c:(.text+0x18): undefined reference to `AlgorithmLink_OpenCVCanny_initPlugin' collect2: error: ld returned 1 exit status make[6]: *** [exe] Error 1 make[5]: *** [demo] Error 2 make[4]: *** [apps] Error 2 make[3]: *** [apps_exe_hlos] Error 2 make[2]: *** [apps_hlos] Error 2 make[1]: *** [apps] Error 2 make: *** [vision_sdk] Error 2 How can I solve this.

Hi Blessy, Better to use tda2xx_evm_linux_opencx config while building OpenCV applications Ensure your new use-case added to uc_cfg.mk file & to LINUX_TDA2XX_UC_LIST under vision_sdk\apps\configs\cfg.mk file Regards Surya

Hi Surya, I tried compiling with tda2xx_evm_linux_opencx. I am still facing the same issue. Infact the number of errors increased. Usecase is defined in cfg.mk and uc_cfg.mk # apps: tda2xx-evm: Linking /home/vkchlt0160/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_opencx/lib/tda2xx-evm/a15_0/release/apps.a(chains_main.o): In function `main': chains_main.c:(.text.startup+0x1b6): undefined reference to `chains_lvdsVipMultiCam_opencvcanny_SgxDisplay' chains_main.c:(.text.startup+0x1fa): undefined reference to `chains_vipSingleCamOpenCVOpenCLDilationSgxDisplay' /home/vkchlt0160/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_opencx/lib/tda2xx-evm/a15_0/release/links_a15_algorithm.a(algorithmLink_cfg.o): In function `AlgorithmLink_initAlgPlugins': algorithmLink_cfg.c:(.text+0x14): undefined reference to `AlgorithmLink_FrameCopy_initPlugin' algorithmLink_cfg.c:(.text+0x18): undefined reference to `AlgorithmLink_OpenCVCanny_initPlugin' algorithmLink_cfg.c:(.text+0x1c): undefined reference to `AlgorithmLink_OpenCVOpenCLDilation_initPlugin'

Hi Blessy, You need to add "chains_lvdsVipMultiCam_opencvcanny_SgxDisplay" to MAKEFILE_adas.MK file under vision_sdk/apps/src/hlos All algorthim link init plugins are under #ifdef in algorithmLink_cfg.c file Could you share your cfg.mk file in use-case folder (need to check which all ALG enabled) ? Regards Surya

Hi Surya, The new use-case i have added is "lvds_vip_multi_cam_opencvcanny_sgx_display". I have included this use-case in MAKEFILE_adas.MK as ifeq ($(UC_lvds_vip_multi_cam_opencvcanny_sgx_display),yes) $(MAKE) -fMAKEFILE.MK -C$($(MAKEAPPNAME)_PATH)/src/hlos/adas/src/usecases/lvds_vip_multi_cam_opencvcanny_sgx_display MODNAME=$(MAKEAPPNAME) CORE=a15_0 $(TARGET) endif I am not able to attach the cfg. mk file. Below are the contents of cfg.mk ALG_dmaSwMs=yes ALG_opencvcanny=yes NEED_PROC_IPU1_0=yes NEED_PROC_A15_0=yes

Hi, 1st make sure your build system is not broken. Try a clean build without adding the new usecase. I hope after changing any cfg file you are doing a clean build. Please share the output of make showconfig. Regards, Anuj

Hi, Is the issue resolved? If yes, then please close the thread as there is no activity since a long time. Regards, Anuj

Ticket Name: TDA4VH-Q1: Performance gain when using C7x instead of C66x DSP for non-TI-optimized code

Part Number: TDA4VH-Q1 Other Parts Discussed in Thread: TDA2, Dear TI experts, we are currently using TDA2 (C66x DSP @ 1Ghz) to run C code that is not optimized w.r.t. TI intrinsics etc.The code has complex data structures and performs many operations in nested loops. We basically fully rely on the compiler optimizations (O3 level) to make best out of the DSP's capacity. We are now considering to switch to TDA4VH-Q1 (C7x DSP @ 1 GHz). In that context I have the following questions: 1) I know that C7x has a wider SIMD data path compared to C6x (512 bit vs 64 bit). Much much would we benefit from that given the same i.e. non-TI-optimized code? Meaning, will the compiler generally be able to make use of that in our case? 2) How could we take more advantage from the C7x (compared to C66x)? Would introducing the TI intrinsics etc. improve the performance a lot? What else would be helpful here?

Hi, 1) it becomes difficult to do parallelization when SIMD width is higher, so in the case of c7x. Non optimized code may not show any improvement on c7x. It may degrade as well in some cases 2) First thing for DSP optimization is that, most of the compute should happen in loops which can be software pipelined. Then on top of that using intrisics helps in optimizing it further. Hence having loops is first and foremost requirement for DSP optimization. in case of nested loops, only inner most loop will be software pipelined. There are plenty of documents available online for C66x software pipelining, and most of the concept/requirements of optimization of C66x applies to c7x. Regards Deepak Poddar

Ticket Name: TDA2PXEVM: git am ../linux-kernel-addon/earlyboot-kernel-patches/* failed

Part Number: TDA2PXEVM Hi, I want to apply the earlyboot-kernel-patches for kernel.But it apply failed.My vision SDK version is 3.07. Here's the apply log. git am ../linux-kernel-addon/earlyboot-kernel-patches/*
应用：dra7xx: Kernel Optimizations for early-use-case enablement
error: 打补丁失败：ti_config_fragments/auto.cfg:50
error: ti_config_fragments/auto.cfg：补丁未应用
打补丁失败于 0001 dra7xx: Kernel Optimizations for early-use-case enablement
失败的补丁文件副本位于：.git/rebase-apply/patch
当您解决这一问题，执行 "git am --continue"。
如果您想要跳过这一补丁，则执行 "git am --skip"。
若要复原至原始分支并停止补丁操作，执行 "git am --abort"。 Could you give some help? Regards Ll

Hi Ll, can you make sure you have checkout the right branch as described in chapter "2.4.2.1.1 Clone kernel" of VisionSDK_Linux_UserGuide.pdf. You may need to run 'git am --abort' before you can checkout the branch. (also it could be useful if you change your local setting to English so we can read the error messages) Regards, Yordan

Hi Yordan, I describe my steps below. 1.Checkout the right branch,I use a new branch name early_boot to distinguish origin branch. lyp@lyp-desktop:~/hd2/tda2/sdk_3.07/ti_components/os_tools/linux/kernel/omap$ git checkout -b early_boot tags/REL_VISION_SDK_03_07_00_00
Switched to a new branch 'early_boot' 
lyp@lyp-desktop:~/hd2/tda2/sdk_3.07/ti_components/os_tools/linux/kernel/omap$ git log
commit 0af2ab56214366ea1b8c1ea6ca0dae726dba083a
Author: Shravan Karthik <shravan.karthik@ti.com>
Date:   Tue Jun 4 18:47:56 2019 +0530

    ti_config_fragments: Add CONFIG_BLK_DEV_NVME to default config
    
    Cascade radar board has a NVME SSD card mounted on the board.
    Add NVME driver support by default in the kernel config
    
    Signed-off-by: Shravan Karthik <shravan.karthik@ti.com>

commit 9e4a96e876ff8cfffe8694f38f27635dfbc18f3f
Date:   Tue Jun 4 18:45:32 2019 +0530

    arm: dts: Change board name for cascade radar DTB
    
commit 12d7cbeff8522722c1981d49b8e07d81fdd887ce
Author: Vignesh R <vigneshr@ti.com>
Date:   Wed Nov 22 14:33:41 2017 +0530

    pci: dwc: pci-dra7xx: Improve MSI IRQ handling
    
    We need to ensure that there are no pending MSI IRQ vector set (i.e
    PCIE_MSI_INTR0_STATUS reads 0 at least once) before exiting
    dra7xx_pcie_msi_irq_handler(). Else, the dra7xx PCIe wrapper will not
    register new MSI IRQs even though PCIE_MSI_INTR0_STATUS shows IRQs are
    pending. Therefore, keep calling dra7xx_pcie_msi_irq_handler() until it
    returns IRQ_NONE, which suggests that PCIE_MSI_INTR0_STATUS is 0. 
lyp@lyp-desktop:~/hd2/tda2/sdk_3.07/ti_components/os_tools/linux/kernel/omap$ git branch
* early_boot
  infoadas-on-psdkla3.03
  kernel_dev
 2.Try to apply the patch,it still apply failed. lyp@lyp-desktop:~/hd2/tda2/sdk_3.07/ti_components/os_tools/linux/kernel/omap$ git am ../linux-kernel-addon/earlyboot-kernel-patches/*
Applying: dra7xx: Kernel Optimizations for early-use-case enablement
error: patch failed: ti_config_fragments/auto.cfg:50
error: ti_config_fragments/auto.cfg: patch does not apply
Patch failed at 0001 dra7xx: Kernel Optimizations for early-use-case enablement
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
 Regards, LI

Hi, Can you apply patch 1 by 1 and tell us which patch is giving the error and share the output of gist status and git diff when you get the error. Regards, Anuj

Hi LI, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Ticket Name: TDA2: TIDL: Using Caffe_Jacinto framework

Part Number: TDA2 I want to get the Caffe-jacinto framework and run training on out custom dataset. So train around for 100 images, Will we be needing a GPU or a simple non-GPU system will work.

You can get the caffe-jacinto framework and scrits by clonning the following two repositories: github.com/.../caffe-jacinto github.com/.../caffe-jacinto-models Please navigate to those links in your browser and read through the documentation provided to understand the usage. If you face any specific issue related to the code or scripts, you can file an issue using the github repository "issues" link in the above repositories.

Yes, I understand that. I wanted know if a system without a GPU is used, approximately how long it'll take to train for say 100 images? Is it recommended.

Training on CPU can be 30x or more slower compared to training on GPU. Exactly how much time will be needed will depend on the size of the image, complexity of the network and the problem that you are trying to solve. Why don't you try to train on CPU - that will give you an estimate of the time required. But whether you conclude to use CPU or GPU for training, I would highly recommend to more images for training. Deep learning cannot learn to generalize with just 100 images and any model or conclusion that you make using that dataset may not work outside the laboratory.

Ticket Name: Linux/TDA2SG: TDA internal pull-up/pull-down resistor

Part Number: TDA2SG Tool/software: Linux Hi, We are analyzing the state of the processor's pins after reset. In which cases do I need to use an external pull-up or pull-down resistor on the GPIO input signal? What is the specific resistance value inside the GPIO pin of the processor? What are the typical and maximum current requirements for GPIO? Thanks. Best Regards,

Hi Feng, 1. You can find buffer types, pullup capability, and default mux mode of each pin in the Datasheet, Table 4.1 Ball Characteristics. 2. It is completely dependent on your use-case. Depends on the buffer type of the external device (push-pull, open-drain) and if this device always drives 0 or 1 (e.g. will it sleep sometimes and go tri-state, or, disconnects via a PCB connector). Depends if it drives relatively static signals: 0 to few kHz, or faster. In other words: - if you expect that external driver is always online and it is a push-pull, you can disable the internal pullup to save some power. - If external device goes tri-state or disconnect - enable an internal pullup - in most cases should be enough - If your external device is some interface (for ex,. I2C, SPI) you need pullups depending on the interface needs 3. Please check the datasheet for the internal resistance. Very roughly it is somewhere 40-70 kohms. 4. Sorry, I don't understand you question for current requirements Regards, Stan

Hi Stan, Thank you very much for your reply, I am already clear. Two other questions: Q1: What is the difference between IOL and IIN? Does IIN refer to the injection current of PIN in tri-state? Q2: If the GPIO output is low, why is the driving capability of the 1.8V mode larger than 3.3V, is this normal? Regards,

Q1: Note that IOL=2mA (Output current during drive Low) is only a condition to parameter VOL. Yes, IIN should be the max leakаge current with pullups/downs disabled. Q2: Driver strength is defined as nominal value of 40-Ohm in all conditions. This, however, this will result in different values for the current in 3.3V and 1.8V modes. ~8mA and 4.5mA respectively. Note that min and max driver strength wasn't defined and may vary. Best regards, Stan

Hi Stan, We have found that two of the SOC chips in our products are overheated. The phenomenon is that the current value of one of the SOC chips fluctuates, sometimes large and sometimes small. The other SOC current value is always large. But the cores of both SOCs can run normally. One of the reasons may be that the external pull-up resistor on the given signal is not connected to the power rail that supplies the VDDSHVn domain to which the GPIO pad belongs，cause the pad to be damaged. Can we read the relevant fault point through the SOC register? How do we diagnose the point of failure? Best regards

Hi, One possible programming method could be: 1. Switch a pin to GPIO function (it is very rare a pin to be GPIO func. by default) in the Control Module padconfig register 2. In the same Control Module register, make sure that input buffer is enabled 3. From the relevant GPIO module, switch the relevant GPIO I/O to output (OE) 4. Set the GPIO I/O to drive 1 (in the output register) , read the GPIO input to see if it is 1 5. Set the GPIO I/O to drive 0 (in the output register), read the GPIO input to see if it is 0 6. IF 4. or 5. fails, THEN this pin is damaged OR it is driven by an external device 7. GOTO 1. for the NEXT pin I think you understand the idea. Note that every pin needs evaluation - is it driven by external device on PCB, or not? If yes, then the pin could be just fine, but you will possibly see the external driven value. !Avoid using it on externally driven pins (especially for long time) because they can get damaged! No issues with external pullups/downs, however. Regards, Stan P.S. You can try also searching for a short (or partial short/low resistance) with a multimeter where possible and where you suspect a failure.

Ticket Name: TDA2: How configured the message object for receive data frame

Part Number: TDA2 Hi , I used vision sdk 03.03.00.00, and I want to know how configured the message object for receive data frame. As followed the TRM chapter 24.9.4.7.3, I must set the arbitration bits (ID[28:0] and Xtd bit) before I received the frame. However, I could not know the identifier of the frame. Regards, Tianxing

Hi Tianxing, VSDK have DCAN demo available. You can enable it by 'DCAN_INCLUDE=yes' in '<install_dir>\vision_sdk\apps\configs\tda2xx_evm_bios_all\cfg.mk' This demo is available in '<install_dir>\vision_sdk\apps\src\rtos\modules\dcan'. Please refer this for more details as it contains how to configure DCAN message RAM/mailboxes. This will also have CAN messages IDs for sent and received messages. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Ticket Name: TDA2EXEVM: HDMI Output on Cascade TDA2 Board

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi, I have a need to use HDMI local display to show RDM data output of 2D-FFT. I have created a usecase and modified the PkDetect Alg to get a copy of one of the 4 EVEs' 2D-FFT output and create a VideoFrameBuffer to output the RDM data to fftHeatMap for local display. As far as I know the usecase runs without any issue but plugging the HDMI output from the TDA2 cascade board to a monitor showed no HDMI output. It didn't look like there is even sync signal detected by the monitor. Normally when monitor picks up a sync, it has a very gent click to kick the monitor active and show the content. There isn't such a thing on this cascade board. Was the HDMI connector on the board designed to be used with usecase? Thanks, --Khai

Khai, Are you using on-chip HDMI or off-chip HDMI? Rgds, Brijesh

HI Brijesh, I using the TDA2 Cascade EVM board from TI at the moment. I am not sure what you are referring to. This is not a custom board. Thanks, --Khai

Hi Khai, We didn't have any customer requirement to support HDMI output on Cascade EVM so it was not tested. I tried once to see if it worked out-of-box with SDK and it didn't. It will require some effort to bring this interface up but we don't have plan to do this. Regards, Stanley

Hi Stanley, We reply on local HDMI output to realize the working of the processing chain. As you know our processing chain will be nothing like the MIMO or TxBF usecase provided where it interacts with Matlab script to render result on PC. Ours usecase is high performance and realtime. Can this feature be considered and make available as there is an HDMI output connector on the board after all. If not this SDK version, the upcoming SDK version. Thanks, --Khai

Hi Khai, There is no plan for any more SDK release except for critical bug fixes. Main reason we descoped HDMI output was we don't have GPU support to display matlab like plot to HDMI output. Having the radar object data transferred to PC for rendering is the only option. Regards, Stanley

Hi Stanley, As of now, the Processor SDK RADAR v03.08 is not compatible with the 2243 Cascade board. If there are no plans for new releases, how is TI planning to address this issue?

In Addition, there is a GPU HW Block in the TDA2 just like the TDA3. If TDA3 can have local HDMI functionality, TDA2 is even a more powerful chip, it should be able to do the same. It's all about TI commitment to supporting it in SDK. --Khai

On TDA3, it is just drawing bitmap on DSP or M4. Same function can run on TDA2. However, HDMI functionality is not support on Cascade EVM.

So you're saying drawing bitmaps cannot be done on the Cascade DSP EVM?

Bitmap drawing functions can be called on DSP or M4 but we didn't bring up HDMI interface for display.

Ticket Name: TDA2: New version of OpenCV library (v3.4.1) for Cortex A15 in TDA2x.

Part Number: TDA2 Dear Sir, Vision SDK (and later PROCESSOR_SDK_VISION_03_03_00_00) contains OpenCV pre-built library for Cortex A15 and currently available version of OpenCV library is v3.1.0. Here are my questions: (1) There are two pre-built OpenCV v3.1.0 libraries, one is for Linux and the other is for SYS-BIOS. Does that mean thoseTI pre-built OpenCV library itself may call some OS-dependent specific software component? (2) Is there Open CV 3.4.1 pre-built library for Cortex A15 in TDA2x? If not, does TI have plan to support it? Best reagards. Mark.

Hi Mark Yes, TI has 2 separate pre-built OpenCV library, one is for Linux and the other is for SYS-BIOS. This is because on RTOS (BIOS) side we need a couple of additional patches and some OS dependent implementations. TI do not have any plans to support/migrate Open CV 3.4.1 Please use the current pre-built library of openCV. It will not be possible to support you on how to migrate/re-build it because the openCV support infrastructure is deprecated. regards, Shiju

Ticket Name: RTOS/TDA2: How to flash FW file(AppImage) to eMMC of TDA2x.

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, As title, I want to know how to flash FW file(AppImage) to eMMC of TDA2x. Could you please advice us how to achieve it. Many thanks,

If you are running RTOS on A15, the boot modes supported are SD, QSPI flash, and NOR flash. eMMC boot mode is not supported. However, eMMC boot mode is supported by uboot with Linux running on A15. Regards, Stanley

Hi Stanley, Understand and thanks.

Hi Sir, 1. RTOS doesn't support eMMC boot, but we can boot from NOR flash via QSPI and run the algorithm in eMMC (use eMMC to be storage), is it correct? 2. Could we know the detail what's limitation why RTOS doesn't support eMMC boot? Is it OS or driver or HW issue? 3. Base on item2, if it is driver issue, will TI have plan for the driver support in the future? Thank you. Sidney

Hi, Yes you can use eMMC for storage. There is no SW support for eMMC boot on RTOS side and the same is not planned for future as well. Regards, Rishabh

Hi Rishabh, On RTOS how can we storage data(or algorithm ) in eMMC ? Have any sample code or document can refer? Many thanks,

Hi, You can refer to mmc app present here: PROCESSOR_SDK_VISION_03_03_00_00\ti_components\drivers\pdk_01_09_00_17\packages\ti\csl\example\mmcsd\mmc_raw_access\. We don't have a lot of SW support for eMMC on RTOS side. I would recommend you to use QSPI or NOR flash for storing data instead of eMMC. Regards, Rishabh

Hi Rishabh, Understand , thanks for your support.

Hi Prince, If you don't have any further questions shall I close the thread? Regards, Rishabh

Hi Rishabh, I have last question . Can we separate AppImage to algorithm and application two parts and save to different memory(algorithm to eMMC, application to QSPI)? If yes how can we booting system and reload algorithm? Could you please give us some advice? Thanks for your support.

Hi, From RBL perspective you can boot only from single boot media. Then the control is with SBL. You can modify SBL to achieve what you want. Assume that you have SBL in QSPI memory. Then you can load and parse a multicore App Image present in QSPI memory first (say application). Then you can initialize another memory say eMMC and load/parse App Image present on that (say Algorithm). Following this approach will need concrete effort as you need to define read/write API library for eMMC and modify SBL. I would suggest you to rather have two app images on same boot media (QSPI or NOR) and flash them at a different locations. Then you will only need to modify SBL to parse the two images. Regards, Rishabh

Hi Rishabh, Thanks for your support.

Hi Rishabh, Many thanks.

Hi Prince, Closing this thread as query has been answered. Regards, Rishabh

Ticket Name: TDA2: EVE/VCOP/KernelC : I am new to VCOP Programming, How the VCOP Kernel-C code taking Less time than Natural-C.

Part Number: TDA2 # 2D Block Addition for Unsigned Byte Arrays : Natural C Code : -------------------------------------------------------------------------------- void vcop_vec_array_add_uns_char_cn (unsigned char a[], unsigned char b[], unsigned char c[], int blk_h, int blk_w) { int i3; int i4; for (i3=0; i3<blk_h; i3++) { for (i4=0; i4<blk_w; i4++) { c [blk_w * i3 + i4] = a [blk_w * i3 + i4] + b [blk_w * i3 + i4]; } } } # 2D Block Addition for Unsigned Byte Arrays : VCOP Kernel-C Code : ------------------------------------------------------------------- #define ELEMSZ sizeof (*in1_ptr) #define VECTORSZ (VCOP_SIMD_WIDTH * ELEMSZ) void eve_array_add_uns_char ( __vptr_uint8 in1_ptr, // input 1 data pointer __vptr_uint8 in2_ptr, // input 2 data pointer __vptr_uint8 optr, // output data ptr unsigned short width, // width of each line unsigned short height // height of each line ) { __vector Vin1; // input1 __vector Vin2; // input2 __vector Vout; // output for (int I1 = 0; I1 < height; I1++) { for (int I2 = 0; I2 < width/VCOP_SIMD_WIDTH; I2++) { __agen Addr; Addr = I1 * width * ELEMSZ + I2 * VECTORSZ; Vin1 = in1_ptr [Addr]; Vin2 = in2_ptr [Addr]; Vout = Vin1 + Vin2; optr [Addr] = Vout; } } }

Hi Akshay, Please refer to chapter 8.3 of the TRM titled 'VCOP CPU and Instruction set', in particular paragraph 8.3.5.2 'Vector Core Overview' , 8.3.5.2.1 'Nested For loop Model' Also the EVE programmer's guide gives useful information as well. If you need access to this document, please contact your nearest TI sales application engineer. Thanks. regards, Victor

You can actually download the TRM from here: www.ti.com/.../sprui29d.pdf

Ticket Name: RTOS/TDA2: TDA2 Camera AVL

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, We would like use 2M RGB-IR camera, OV2736 for TDA2 product development, but it is not in AVL. Please help me check it is available be supported by TDA2. If it is not be supported, please give me the 2M RGB-IR camera suggestion list and the latest of camera AVL for my reference. Thank you. Sidney

Hi Sidney, You could capture the camera output if it supports parallel output over discrete sync interface. But how do you process this RGB-IR output data? You will have write SW to process that data. Rgds, Brijesh

Hi Sidney, I am closing the thread, since there is no reply. You could reopen it if you are still facing the issue. Regards, Rishabh

Ticket Name: TDA2: Error while running Object Detection use case in hlos

Part Number: TDA2 Hello Everyone, I ran the use case of object detection in single camera in hlos and I got the following error: [HOST] [HOST ] 439.307417 s: [HOST] [HOST ] 439.307448 s: [HOST] [HOST ] [HOST] [HOST ] Select use-case options, [HOST] [HOST ] ------------------------ [HOST] [HOST ] 1: Enable Pedestrain Detect (PD) [HOST] [HOST ] 2: Enable Traffic Sign Regonition (TSR) [HOST] [HOST ] 3: Enable Vehicle Detect (VD) [HOST] [HOST ] 4: Enable PD+TSR+VD [HOST] [HOST ] [HOST] [HOST ] Enter Choice: [HOST] [HOST ] 1 [HOST] [IPU2 ] 450.403403 s: CAPTURE: Create in progress !!! [HOST] [IPU2 ] 450.403800 s: CAPTURE: VIP2 Slice0 PortA capture mode is [ 8-bit] !!! [HOST] [IPU2 ] 450.403952 s: captdrv/src/vpsdrv_capturePriv.c @ Line 266: [HOST] [IPU2 ] 450.404044 s: Invalid number of streams(0) - Supported max streams 8 [HOST] [IPU2 ] 450.404135 s: Assertion @ Line: 548 in captureLink_drv.c: pInst->captureVipHandle != NULL : failed !!! I request you to help me in resolving this issue. Best Regards, Vijay

Hi, Please don't create duplicate thread. I am already looking into below thread and will provide response there Please close this thread. Regards, Anuj

Hello Yordan/Anuj, I was able to resolve the issue.I added code for setting capture parameters for CHAINS_CAPTURE_SRC_OV490 in chains_common.c under vision_sdk/apps/src/hlos/common.I am able to do object detection and my use case detects pedestrian,vehicle and traffic signs in hlos. But the object detection stops after sometime with the following error messages displayed continuously in the terminal: SYSTEM: IPC:[DSP1] Notify recvfrom failed <Link has been severed,67> !!! SYSTEM: IPC:[DSP1] Notify recvfrom failed <Link has been severed,67> !!! SYSTEM: IPC:[DSP1] Notify recvfrom failed <Link has been severed,67> !!! SYSTEM: IPC:[DSP1] Notify recvfrom failed <Link has been severed,67> !!! I request you to resolve this issue. Best Regards, Vijay

Hi, After how long you observed this issue? Have you made any changes in any link or the usecase ported from RTOS. Even after getting this log whats the effect on running the usecase? I will suggest to please recheck your changes and try a clean build. Regards, Anuj

Hello Anuj, The duration was random.When the error occured the display turned green.But during my last data collection activity(I modified the chain for storage of video to a file) there was no error.We can close this thread for now.I hope I don't get this error again. Best Regards, Vijay

Hi, Thanks for the information. Please verify the answer and close the thread. Regards, Anuj

Ticket Name: TDA2HV: How to build Ti-DL with PSDK on Linux ?

Part Number: TDA2HV Other Parts Discussed in Thread: TDA2 Hi, I found Ti-DL source code in Ti-DL . and I am using PROCESSOR_SDK_LINUX for TDA2. I unzipped the PSDK package and its has following arch: cd PROCESSOR_SDK_VISION_03_07_00_00/ ls Index.html Processor_SDK_Vision_manifest.html ti_components uninstall uninstall.dat vision_sdk VisionSDK_Getting_Started_Guide.pdf When I want to build Ti-DL code on my Linux, it tell me (in tidl-api/0makefile) : # makefile for building from the tidl-api git repo # Cross-compilation requires TARGET_ROOTDIR to be set. # E.g. # PSDK_LINUX=<path to Processor Linux SDK install> # TARGET_ROOTDIR=$PSDK_LINUX/linux-devkit/sysroots/armv7ahf-neon-linux-gnueabi My questions are : 1. what is PSDK , isn't my PROCESSOR_SDK_VISION_03_07_00_00 folder? 2. how to get one "PSDK" 3. if Ti-DL is in PSDK source code , how can I build it ?

Hi @he zhan, TIDL is included as part of VisionSDK, please check the document "PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_UserGuide_TI_DeepLearning.pdf". The library itself is located in folder "PROCESSOR_SDK_VISION_03_07_00_00/ti_components/algorithms/REL.TIDL.01.01.03.00". You may need first to look at "PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/docs/UserGuides/VisionSDK_UserGuide_TDA2xx.pdf" first to get familiar how to set up and build the SDK. Regards, Yordan

Ticket Name: TDA2PXEVM: A15 Micro-Processor On the TDA2

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2, TIDEP-01017 Hi, I am using the TDA2 Cascade Processor board and have the following questions: 1. Which flavor of TDA2 chip is on that board? There seems to be 3 variant of TDA2 chipset 2. The Dual ARM A15 processor, if I am running ti-rtos, can i develop radar application (use case) using this processor same way as how IPUs or DSP cores are being used? If this is possible, this will provide even more flexibility to radar application development 3. I looked in the processor SDK source tree. There is actually build configurations for tda2xx_cascade_linux_radar & tda2xx_evm_bios_radar that use the A15 where PROC_A15_0_INCLUDE=yes. I can understand the tda2xx_cascade_linux_radar uses the A15 as the main processor. What is tda2xx_evm_bios_radar build configuration? What EVM board is this and what is the purpose of this board that uses the A15? Thanks, --Khai

There is also IPU2 on the TDA2, Can both A15 and IPU2 be used in radar use case application? My guess is yes if the memory map is configured properly. Thanks, --Khai

1) Please refer to TIDEP-01017 datasheet on ti.com. 2) Yes. 3) For bios build, A15 is not running any active task but just staying in Idle task. It is free to be used. It is for the same EVM as linux build. 4) Yes. IPU2 can also be used.

Ticket Name: Linux/TDA2EVM5777: My Custom link build error

Part Number: TDA2EVM5777 Tool/software: Linux Hi, I'm working on a project with TDA2EVM. I created three custom links and put them in myApp's "src/hlos/modules/" and assigned Link ID at system_linkId.h (links_fw). However, during the final linking process of the build, the error "MyApp.out: No soch file or directory" appeared. I checked that each custom link worked separately. and this error occurred during the process of merge. I solved this problem by modifying "src/hlos/MAKEFILE.MK" file, but I don't know why. Do I need to write down the MAKEFILE.MK content sequentially, such as a my custom Link ID? For example, when mod1 (LinkID 76), mod2 (LinkID 77) In MAKEFILE.MK order must be mod1, mod2 to prevent the above mentioned error from occur. I think MOD1 and MOD2 are not interrelated, are they interrelated in build process? I'm confused... I'd appreciate it if you could give me the answer. Regards, Lee.

Hi Lee, Depending upon where you want to run these custom links the answer will vary. Is there any custom link that is meant to be run on A15? Regards, Rishabh

Hi, Rishabh. Thanks for answer. My three custom link run on A15 core. Regards, Lee.

Hi Lee, You need to add the link under PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\links_fw\src\hlos\links_a15. Please see of the already available links on how to add the same to the make. Regards, Rishabh

Hi Lee, Have you been able to make progress on this issue? Regards, Rishabh

Ticket Name: Linux/TDA2EX17EVM: BT656 For TDA2Ex

Part Number: TDA2EX17EVM Tool/software: Linux Dear Sirs: We use latest Processor SDK Vision. We want to make sure the BT656 is really working on TDA2 so we did the following test: 1. We use J6E Board with a VAYU VISION board with the OV10635 sensor 2. When using BT601 with OV 1063x setting setting 0x4700 and 0x4708 inside the PSDK, the code working fine. 3. When using BT656 with OV 1063x setting setting 0x4700 and 0x4708 inside the PSDK and modify the related OV video setting to be a)pInstPrm->videoIfMode = SYSTEM_VIFM_SCH_ES; b)pPortCfg->syncType = SYSTEM_VIP_SYNC_TYPE_EMB_SINGLE_422_YUV; and other setting remain same as before i.e. pInstPrm->videoIfWidth = SYSTEM_VIFW_8BIT; pInprms->dataFormat = SYSTEM_DF_YUV422P; pInprms->scanFormat = SYSTEM_SF_PROGRESSIVE; ... Please refer to PROCESSOR_SDK_VISION_03_02_00_00\vision_sdk\apps\src\hlos\common\chains_common.c where captureSrc == CHAINS_CAPTURE_SRC_OV10635 The above OV BT656 setting is working in our DM81xx board, but not in J6 Entry. Do you have any idea to know what could be the problem to no VIDEO input in BT656 mode? Regards, /ckhsu

Forgot to said, the above setting we set the pixelClk to RISING, and we also test on the FALLING and both not working. And we also use another J6Entry board and attach a TVP5158 to it, with setting BT656 on it, no matter what setting on 1CH/4CH, interlace, 8 bit, none of them work in BT656 mode. Please let me know what could be my problem. Regards, /ckhsu

Hi hsu, Can you please VIP register? I am interested in in mode and data size register.. As the config looks correct, but can you also check the board muxes are set correctly.. Regards, Brijesh

Since OV 10635 is 10 bits output in VISION board, to prevent the BT656 signal from OV is in fact from D9 to D2, we also create a H/W connector to make OV D9 to D2 is connected to D7 to D0 in J6E board. However the result is still the same. We will post the register values later after we dump it. Regards, /ckhsu

The problem is solved. This problem is only in PSDK Linux version but not in BIOS version.

Ticket Name: TDA2P-ACD: Several questions for using TDA2 with radar

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2, AWR1243, TDA2PXEVM Hello team, My customer has the plans to use TDA2 to use it with AWR1243 and perform first order FFT and second order FFT using TDA2 devices and to perform it on the 2.5MB L3 RAM On-chip (without DDR2/3). 1. could you please advise if our device can use the C66x DSP without external DDR2? 2. there is a need to have at least 2.5GB throughput of output data from the device, what is the best I/F for doing that (I think the PCIe II could do the trick)? 3. what is the PN chipset that comes with TDA2PXEVM (the customer is looking for TDA2PHF-ACD chipset EVM)? 4. Could you please advise if the upcoming TDA4 comes with higher memory (on-chip) in the L3 RAM than the TDA2 (2.5MB)? Thanks in advance Shai

Hi Shai, There are couple of things to look at: What is the Radar cube you are looking at? We could have C66x code running from OCMC RAM along with rest of the radar cube, but a memory partition needs to be done on what is the code/data section requirements for C66x and then plan for a DDR less system. Are there other cores you are looking at for running code out of OCMC? PCIe would do the trick if the requirement is 2.5 Gbits per second. For the PCIe if you would like to have enumeration features, the linux PCIe drivers are more mature than bare metal PDK drivers. With Linux in the picture, it would be a challenge to fit everything in a DDR less system. The EVM comes with a pre-production part DRA77xP/DRA76xP/TDA2Px (Superset SoC) . For TDA4x specific questions please contact your TI representative. Thanks and Regards, Piyali

Ticket Name: RTOS: Which core manages IPC in TIDL?

Tool/software: TI-RTOS Hi, I'm analyzing TIDL usecase and i have 3 questions. Q1) I did read some documents for understanding IPC. As i understand, each core has message box and messages from other cores are received by that. (Is this right?) If i understand correctly, is there any main core for IPC? (I mean the core which handle the messages from each core) Q2) Does IPC1_0 executes Chains_main function? In that case, the main core of TIDL usecase is IPC1_0, is this right? Q3) In converting caffe model to TIDL by using TIDL importing tool, i saw 'LayersGroupID' parameter. Is that value existing for giving each layers of DL model to DSP/EVE? If so, where can I find the source code that provides each layer of the DL model on each core? Thanks in advance. Regards, Yoo.

Hi Yoo, VisionSDK experts will answer Q1 and Q2 soon. For Q3 please check FAQ #21 in PROCESSOR_SDK_VISION_03_06_00_00\ti_components\algorithms\REL.TIDL.01.01.03.00\modules\ti_dl\docs\TIDeepLearningLibrary_UserGuide.pdf Regards, Yordan

Hi, Please find your answer below Q1> All cores has its message box for IPC. There is no main core for this each core can communicate with any core independently. Q2> I hope you mean IPU1_0 Yes IPU1_0 is master core when we run VSDK bios. So this core runs all usecase. Regards, Anuj

LayersGroupID is set via import config file. refer TIDL users guide for more information

Thank you, I understand the way to allocate each layers into DSP/EVE core. Then, the diagram below, which shows the data flow of the TIDL OD usecase, shows only the flow of the frame. And each layer operation actually is executed by DSP or EVE according to the layer groupid? or In the diagram below, first Alg_tidl_Eve executes computation of specific layers that are allocated to EVE and Alg_tidl_Dsp executes computation of other layers?

Yes, it shows only the flow of the frame. And each layer operation actually is executed by DSP or EVE according to the layer groupid

Ticket Name: TDA2P-ACD: U-Boot isolate_io function is failed

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Hello. We made the custom board with TDA2P-ACD chip. And I tried to boot using SD CARD with MLO and u-boot.img in it. But it didn't boot. TDA2P EVM board with the same firmware boot well. When I checked the log by quickly initializing the UART in SPL, I got an error "IODELAY: Isolation of Device IOs failed" in the function __recalibrate_iodelay_end in the file dra7xx_iodelay.c. And I found out that the error occurred because the code below returned an error. ----------------------------- In dra7xx_iodelay.c ---------------------------- static int isolate_io(u32 isolate) { if (isolate) { clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ, SDCARD_PWRDNZ); clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ, SDCARD_BIAS_PWRDNZ); } /* Override control on ISOCLKIN signal to IO pad ring. */ clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, PMCTRL_ISOCLK_OVERRIDE_CTRL); if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK, (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) { return ERR_DEISOLATE_IO << isolate; <----------------- } ------------------------------------------------------------------------------ I'd like to know why this happens. ------------------------------------ Full log ------------------------------------ U-Boot SPL 2016.05-00010-g9551b3d-dirty (Apr 10 2020 - 17:10:32) DRA762-GP ES1.0 IODELAY: Isolation of Device IOs failed Leveling timeout on EMIF1 SDRAM: identified size not same as expected size identified: 4 expected: 40000000 ---------------------------------------------------------------------------------- Best Regards, Yousik Kim.

Hi Yousik, 2016.05 was about 4 years old now. There can be multiple factors for this to fail like board design, aging of the device, total power on hours of the device. Is it failing always? We had customers reporting occasional failure on some TDA2 devices in the past. Can you Kindly migrate to the latest SDK for DRA7: http://downloads.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/6_00_00_03/index_FDS.html Best Regards, Keerthy

Hi Keerthy, It always fails. This is the board we've made recently and it's first test. We are using PROCESSOR_SDK_VISION_03_07_00_00, and U-Boot received from this SDK was 2016.05. It worked fine on the EVM board, so I think this is a H/W problem. But I am not sure which part to look at about this problem. Isolation Sequence part of "20.4.6.1.7 Isolation Requirements" of TDA2Px TRM document is failing. I want expert advice. Best Regards, Yousik Kim.

Hi Yousik Kim, You are right this most certainly looks like Hardware board design issue(IO related). I am definitely not the expert in the board design front. May be you will have to share more hardware details in a different new query that could be assigned to right hardware expert. From bootloader side if you nothing else to ask for i would request you to resolve this issue and raise a new one with more hardware details so it can assigned to right expert. Best Regards, Keerthy

Ticket Name: AM5749: TIDL model type

Part Number: AM5749 Dear sir, According to TIDL web document 3.15.4.7.1, modelType "ONNX" can be set by 2. However, it seems not existing when I converted onnx file with import tools in vsdk version 3.7. Is there any version onnx can convert to TIDL? thank you, Gary

Hi Gary, can you clarify which device you use? Is it TDA2x (TIDL is not supported on AM5749). Regards, Yordan

Hi Yordan, Thank you for your reply. My testing board is VAYU EVM (ES1.1) XC5777X CPU board with a vision application board. Gary

Hi Gary, As pointed out in the original post, current TIDL 01.03 version in vsdk version 3.7 does not support importing ONNX models. We have plan to support this in next TIDL 01.04 release. Thanks, Praveen

Hi Praveen, Thank you for your information. Do you know when will TIDL 01.04 be released? Thank you, Gary

Hi Gary, TIDL 01.04 will be released along with next VSDK release 3.8. I will check internally about next VSDK release date and come back. Thanks, Praveen

Hi Praveen, The next VSDK release 3.8 is planned for December 1st week. Thanks, Praveen

Ticket Name: TDA2EXEVM: Interfacing with AWR1642BOOST EVM (Radar Sensor)

Part Number: TDA2EXEVM Other Parts Discussed in Thread: AWR1642BOOST, AWR1642, TDA2 Hi, We are looking at connecting the AWR1642BOOST EVM to the TDA2X EVM through CAN. However, we noticed that the AWR1642BOOST EVM has a single CAN-FD port while the TDA2X EVM has a single Classic CAN port. Can the AWR1642BOOST EVM be configured to send plain Classic CAN messages via the CAN-FD port? If not, what is the recommended method for interfacing the AWR1642BOOST EVM to the TDA2X EVM via CAN? Regards, Ranjith

Hi Ranjith, I'm not familiar with the AWR1642BOOST EVM. I just checked the EVM datasheet: www.ti.com/.../swrs203 There are described 2 CAN ports: one CAN-FD and one classic. Can you please check again documents and inspect your board for a second CAN? Also, what is the version of your board? Regards, Stan

Hi Stan, Thanks for quick response. The datasheet link present in your comment is of the AWR1642 Radar Sensor, not of the EVM. Datasheet of AWR1642BOOST EVM is available at www.ti.com/.../swru508a.pdf This document mentions of only one CAN-FD Connector in Topic 1.2 Key Features, as well as in Figure 1. EVM (Front). So, It looks like the EVM board is exposing only CAN-FD interface, out of the 2 CAN Interfaces provided by AWR1642 Radar Sensor. Regards, Ranjith

Hi Ranjith, Sorry, I didn't realize that I was looking at the chip datasheet. I've checked also the EVM document. It looks like classic CAN can be reached on one of the connectors (e.g. J1). CAN is muxed with SPIA_CS and SPIA_CLK internally, hence CAN must be selected in software. CAN is also available on other 2 pins: TRACE_DATA_12 and TRACE_DATA_13 which are also routed to J1. Note that you will need an external CAN PHY transceiver module/PCB, because the 2 pins are a simple, CMOS RX/TX pair. (CAN-FD has onboard PHY) Regards, Stan P.S. Now I recall that if you need only the two nodes on the network (AWR and TDA2), it could be possible to connect them PHY-less. I.e. TX ----> RX RX <------TX , provided that voltage levels match. I didn't try this however.

Ticket Name: Linux/TDA2EVM5777: Install Packages in VisionSDK Linux

Part Number: TDA2EVM5777 Tool/software: Linux Helllo, I am running PROCESSOR_SDK_VISION_03_03_00_00 Linux on TDA2x and I need to install packages like minicom or nano. Is it possible to install packages into the rootfs in the compile environment? What is the correct way to install packages into VisionSDK Linux? I attempted two different methods to install packages and was unsuccessful in both methods. Method 1: I attempted to use opkg, but when I try to use the command opkg update the command gives me wget errors: root@dra7xx-evm:~# opkg update Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Downloading lcpd.gt.design.ti.com/.../Packages.gz. wget: bad address 'lcpd.gt.design.ti.com' Collected errors: * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. * opkg_download_backend: Failed to download lcpd.gt.design.ti.com/.../Packages.gz, wget returned 1. root@dra7xx-evm:~# Method 2: When I attempt to cross compile the packages on my development computer by downloading them and using ./configure && make, I would get errors where I would need to install something like coreutils, and when I attempt to install that, I would get lower level errors. Thank you, -iFer

Hi iFer, Regarding the Method 1: although the file system supports the ability to derive from Yocto feeds and do an update like the "opkg update", you would need to point it to a relevant publicly accessible feed or a private feed that you set up. As far as I know, there is no public feed that can help you achieve the desired result in this method. Please let me know if you are aware of any public feeds that I can try. Regarding the Method 2: I need more details to comment on the errors that you are facing. but this method wouldn't be my recommendation. The easiest method would be to just add the minicom and nano packages into your Yocto filesystem image, and generate the opkg and transfer/install to the target. Regards Karthik

Ticket Name: TDA2PXEVM: How to create two vlan socket that bind same IP but different vlan-id?

Part Number: TDA2PXEVM [TDA2PX]How to create two vlan socket that bind same IP but different vlan-id? (TI-RTOS) we have already added two vlan by VLANAddDevice, the default usage for vlan is bind to different IP address, we also send data success with different vlan-id socket that bind with different IP address but we need to create two vlan socket with different vlan-id that bind same IP address and this config is failure 1. we need send RTP on vlan id 5 with IP("198.18.36.96") 2. we need send other data on vlan id 12 with IP("198.18.36.96") but the NDK seems not support the two configs working at same time, we can not create one socket(vlan5) for sending RTP while create another(vlan12) for sending data, so how to solve this?

Hi Mi, This is not supported. Todd

Ticket Name: Linux/TDA2: Can TDA2 use-case support 2D surround view & E-mirror demo on Linux SDK.

Part Number: TDA2 Tool/software: Linux Hi Sir, I am using TDA2x EVM and SDK version is 3.4. I can find 2D+3D surround view use case on BIOS only SDK, but there is no 2D surround view use case on Linux SDK. Do you have sample code or document for me to reference to move BIOS use case to Linux SDK ? BTW, Is TDA2 SDK support E-mirror demo on Linux OS ? Thanks. Ranny.

Ranny No document available for moving 2D SRV UC from Bios to Linux, but you can port the UC to Linux. No E-mirror demo available on Linux vision SDK regards, Shiju

Ticket Name: why ancillary data need ANC_SKIP_NUMPIX, ANC_SKIP_NUMLINES ?

follow:https://e2e.ti.com/support/processors/f/791/p/796261/2948349#2948349 i have last question: i had read page 2211 of TRM. why is ancillary data that it need what are ANC_SKIP_NUMPIX, ANC_SKIP_NUMLINES? i think it just video data need these.why also trimmer in ancillay data?

It is a features, you could even trim unwanted ancillary data.. Rgds, Brijesh

ok. if i need all ancillary data, How do I assign the following？ ANC_SKIP_NUMPIX ANC_ NUMLINES_USE ANC_SKIP_NUMLINES ANC_ USE_NUMPIX

ok, In that case, you don't need to enable cropping for the ancillary data.. Just set the bypass bit to 1.

hi: we have requirement that get ancillary data in vip module.

You could capture ancillary data when vsync is active high.

hi: i had know u say. but i had read page 2211 of TRM.the page wrote it need configure ANC_SKIP_NUMPIX,ANC_USE_NUMPIX,ANC_SKIP_NUMLINES,ANC_USE_NUMLINES for Vertical Ancillary. It makes me confused.these four registers used to crop field in frame.however The veritical ancillary store in bottom and top field in frame. so how to configure these?

Yes, but this registers need to be configured only if you want to enable cropping.. If you dont want ancillary data cropping, then these registers need not be configured and VIP will capture entire blanking area in the memory. Rgds, brijesh

ok,i have see vision_sdk_0306/ti_components/drivers/pdk_01_10_02_07/packages/ti/drv/vps/include/vip/vps_cfgVipParser.h follow: it choosed VPS_VIP_LINE_CAPTURE_STYLE_HSYNC can be capture Horizontal Blanking Ancillary Data. so which other choose can capture Vertical Blanking Ancillary data?

vertical blanking data depends on the size of the vsync, no change required in VIP.

Ticket Name: TDA2EXEVM: what is the limit on the number of groups in convolution

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi,Because I use group convolution and the fps is very low, what is the limit on the number of groups in convolution?

Hi, The max number of supported groups in convolution are 1024. Thanks, Praveen

Hi, Thank you for your reply. The number of group I used in each convolution is less than 1024, but my fps is still very low. I think it is the problem of tidl importTool. How to set the conv2dKernelType of tidl_import_JDetNet.txt？ Only if the size of conv is less than 32*32 is set to 1. Or are there other conditions? Thanks

Hi, Sorry for the late reply. Please set conv2dKernelType to 1 if the size of conv is upto 64*64 and try if it can improve the fps. Thanks. Praveen

Hi, Thank you for your reply. I have already tried to set conv2dKernelType to 1 if the size of conv is upto 64*64, but the fps still very low. Are there any other restrictions? Thanks.

Hi, If you are running SSD model, you may need to modify below as shown to overcome low fps, keep_top_k: 20 confidence_threshold: 0.15 More details are in the below thread. https://e2e.ti.com/support/processors/f/791/t/689617 Thanks, Praveen

Hi, Thank you for your reply. Yes, I was running SSD model. I have already tried to set keep_top_k to 20 and confidence_threshold to 0.15, but the fps still very low. Are there any other restrictions or import tool have some problems? Thanks.

Hi, >> Are there any other restrictions or import tool have some problems? No, there are no other problems in the import tool. This low fps is because of grouped convolutions will take more time for processing in TIDL, so this could be a reason for low performance. Kindly try with small grouped convolutions. Thanks, Praveen

Hi, Thank you for your reply. Normally, the use of group convolution can increase the execution speed of the model, but why does the use of group convolution in tidl make the fps drop? By the way, The total parameter amount of the ssdJacintoNetV2 I trained is 3.25693e+06, and Total Giga Macs is 3.6114. After the import tool, the executed fps is 20, but why the total parameter amount of the ssd model I additionally designed is less (253024),Total Giga Macs is 1.4182, and after the import tool, the executed fps is 15 (drop)? The settings have been set according to the user guide. Are there any additional restrictions on tidl and import tool? Thanks.

Hi, Kindly share the import config file for checking ? Thanks, Praveen

Hi, I have shared my import config file. Please test for the import tool and fps. Thanks.import_config_file.7z

Hi, Import config file looks fine, the conv2dKernelType was set correctly. The fps reduction is mainly because of uneven and small tensor sizes. The kernels are be better optimized for tensor sizes multiple of 8. I think fps you got is the final number for your model. You can try one last thing setting "nms_threshold: 0.4" in the deploy.prototxt. Thanks, Praveen

Hi, Thank you for your reply. The situation you mentioned in my model is starts from the pool3 layer, but this design is the same as ssdJacintoNet, So why my fps is lower than ssdJacintoNet? What is the principle of nms_threshold: 0.4？ I have tried setting nms_threshold to 0.4, but the fps has not changed. Thanks.

Hi, >> The situation you mentioned in my model is starts from the pool3 layer, but this design is the same as ssdJacintoNet, So why my fps is lower than ssdJacintoNet? Even though this situation started from pool3 layer, but in the earlier layers there are grouped conv layers which are not well optimized in the TDA2 (as we do SIMD across numchannels), so there is performance degradation in your model. Thanks, Praveen

Hi, Thank you for your reply. >>In the earlier layers there are grouped conv layers which are not well optimized in the TDA2 But the maximum grouped conv of each layer is only 4, which is the same as the maximum grouped conv value of the ssdJacintoNet. Or is there a limit to the number of grouped conv? If so, how much is it? Thanks.

Ticket Name: Linux/TDA2EX17EVM: I want to start system from USB like SD card,what should I do?

Part Number: TDA2EX17EVM Tool/software: Linux Hi: Now the EVM board can start from SD card normally.But I want to start from USB now,So what should I do? 1.Which usb port should I insert USB into？USB1 or USB2 port? 2.If the EVM board can detect USB,where will it be mounted after bringing up?

Hi, TDA2 ROM bootloader does not support loading SBL from an USB pen drive. Regards, Stan

Hi, But I find that it can boot linux from USB storage in the Linux Core U-Boot User's Guide P14,

Yes, this should be possible, but first you need to load SBL/u-boot from different source. Regards, Stan

Hi Stanislav: So you mean SBL/u-boot should be located in SD or emmc,and kernel can be loaded from USB device? And another question is that my custom board cannot detect USB device.After it comes into Uboot,the log is as following: => usb reset resetting USB... USB0: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus 0 for devices... Kyle:tries == MAX_TRIES error!!! cannot reset port 1!? 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found In EVM board,I find that there is a signal called DET_USB2_VBUS.Does the TDA2 will detect the signal? I also want to know how EVM board will detect USB device after I excute "usb start" ,which signals does EVM will detect? Thanks !

HI, Could you help to answer my question?

HI, Sorry,I still have some questions to ask you!

Hi, Do you observe the 5 volts on the USB connector after usb initializes?

Yes, I measure VBUS's voltage,it will become 5V from 0V

Hi, It is possible to boot direct using USB. Note there are 2 stages as described in the link: http://processors.wiki.ti.com/index.php/Linux_Core_U-Boot_User's_Guide#Using_USB_Device_Firmware_Upgrade_.28DFU.29:1230:0 . In the above method, the TDA2x EVM is configured as USB device and the PC is the USB host. As mentioned previously in the above thread, alternative to this is to boot the SBL/U-Boot using other boot mode (like SDcard), and then connect USB pen-drive to load the kernel. Here we trying to configure TDA2x EVM is configured as USB host which interacts with the device (USB pen-drive). See this link for more details: http://processors.wiki.ti.com/index.php/Linux_Core_U-Boot_User's_Guide#Booting_Linux_from_USB_storage This answers the original question of this post. The subsequent question on the " cannot detect USB device" when calling "usb reset" is being discussed here: https://e2e.ti.com/support/arm/automotive_processors/f/1021/t/711806 .

HI, Thanks for your reply!Because I realized that the question "cannot detect USB device" is different from the original question,so I create another thread.Could you help to answer my new question on e2e.ti.com/.../711806 . Kyle

Ticket Name: TDA2EXEVM: Support for LSTM and RNN to enable Speech Recognition usingTIDL

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi Kumar, We have TD2X EVM board. And till now we were working on vision side and we understood how one can use any existing Deep Learning model for object detection like face detection, car detection etc using TIDL. Now, I would like to know that if i want to add ASR (Automatic Speech Recognition) on TDA2X .What should be the approach? I understand that TIDL should support LSTM, RNN layer. Because, these layers are at core of NLP and speech recognition. Somewhere in documentation, I read that support for these layers is future scope (http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_TIDL.html) 1. Can you comment on the support for LSTM and RNN in TIDL ? 2. Is there any other existing approach of speech recognition which we can use on TDA2X ? 3. Any examples or demos available ? 4. Can you suggest any speech recognition approach other that ML or DL, for quick prototyping on TDA2X ? Regards, Sagar

Hi Sagar, 1. As of now, we don't have any plans for supporting LSTM and RNN in TIDL on TDA2. 2. No, we don’t have solution using TIDL. 3. No, we don't have any demos. 4. User can use tensorflow Lite or ARM NN in the Linux running on A15 Thanks, Praveen

Ticket Name: TDA2: Math.h and vector file advise

Part Number: TDA2 Dear TI Hi I would like to ask there since to have a few math.h and vector file in the visionsdk but i am not sure which one i should be using. Are you able to advise which math.h and vector file i am suppose to use ?

Hi, You can find these inside code generation tool paths for your sdk. Please check vision_sdk/build/tools_path.mk and check for the cg_tools, in that path you will find all the necessary header files. Regrads, Anuj

Dear Anuj Thanks for the reply but may question was there are different math.h and vector file under these folder (cg_tool/window/)but i am not sure which one i am suppose to use or these different math.h and vector file under these different. On top of these follow what does folder name referring to? Is it the processor ? folder : arp32_1.0.7 ,C6000_7.4.2, gcc-arm_none_eabi-4_9-2015q3 and ti-cgt-arm_16.9.2.LTS

Hi, arp32_1.0.7 ,C6000_7.4.2 -> Eve core C6000_7.4.2 -> DSP core gcc-arm_none_eabi-4_9-2015q3 -> A15 ti-cgt-arm_16.9.2.LTS -> M4 All the 4 toolchains are 4 different cores So it depends on which core you are adding these header files,it will be picked from restective toolchains. Regards, Anuj

Dear Anuj If i am running a new usecase but the algo is running on A15 core but require a math.h and vector, it i possible if i use math.h and vector under DSP core ?

Hi, if the algorithm link is running on DSP and uses any math or vector header file then it will able to pick up from toolchain of DSP. Regards, Anuj

Dear Anuj In another words, if i run my algorithm link on A15 ( as i am using to opencv) then i cant just simply just include the header file as shown below ? #include <C6000_7.4.2/include/math.h> #include <C6000_7.4.2/include/vector>

Hi, Have to tried to add only <math.h> ? Fir all cores this toolchain paths are already defined, so it will automatically pick from the respective toolchain. you do not need to specify the path explicitly. Regards, Anuj

Part Number: TDA2 Tool/software: TI-RTOS Hi, I'm using dcan example with tda2xx_evm_bios_all config on tda2xx evm board with Vision SDK (PROCESSOR_SDK_VISION_03_01_00_00). After turning on DCAN_INCLUDE(DCAN_INCLUDE=yes) in vision_sdk\apps\configs\tda2xx_evm_bios_all\ cfg.mk, dcan1 can be tested as expected in external loopback mode. In order to test dcan2, vision_sdk\apps\src\rtos\modules\dcan\utils_dcan.c is modified, since utils_dcan.c only support dcan1 . The modification can be seen bellow. But it seems that the dcan ISR is not entered, causing the code stuck at Utils_dcanWaitForTxComplete(). Is the modification correct? Did I miss some configuration? Thanks! --- utils_dcan_original.c       2018-06-14 18:05:18.280695070 +0800
+++ utils_dcan_modified.c       2018-06-14 18:09:01.520685249 +0800
@@ -121,7 +121,8 @@
-#define UTILS_DCAN_INST                   (SOC_DCAN1_BASE)
+#define UTILS_DCAN_INST                   (SOC_DCAN2_BASE)

@@ -553,7 +554,9 @@
     Utils_dcanWaitForIfReg(UTILS_DCAN_INST, UTILS_DCAN_TX_IF_REG);
+    Vps_printf("Utils_dcanWaitForTxComplete\n");
     Utils_dcanWaitForTxComplete(mbxIndex);
+    Vps_printf("Utils_dcanWaitForTxComplete done\n");

@@ -1088,13 +1091,19 @@
     PlatformUnlockMMR();
 
     /* Clock Configuration. */
-    PlatformDCAN1PrcmEnable();
+    if(UTILS_DCAN_INST == SOC_DCAN1_BASE)
+        PlatformDCAN1PrcmEnable();
+    else
+        PlatformDCAN2PrcmEnable();
 
     /* Perform the DCAN pinmux. */
-    PlatformDCAN1SetPinMux();
+        PlatformDCAN1SetPinMux();
+    else
+        PlatformDCAN2SetPinMux();
 
     /* Initialize the DCAN message RAM. */
-    PlatformDcanMessageRamInit(0);
+    PlatformDcanMessageRamInit(UTILS_DCAN_INST == SOC_DCAN1_BASE? 0 : 1);
 }
 
 /**
@@ -1638,7 +1647,7 @@
     UInt32 cookie = 0;
     const UInt32 intrId = dcanConfig.dcanCntrlIntrId;
 
-    IntXbar_connectIRQ(intrId, DCAN1_IRQ_INT1);
+    IntXbar_connectIRQ(intrId, UTILS_DCAN_INST == SOC_DCAN1_BASE? DCAN1_IRQ_INT1 : DCAN2_IRQ_INT1);
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
@@ -1785,6 +1794,7 @@
 
+        Vps_printf("dqy dcan: init can%d!!!\n", UTILS_DCAN_INST == SOC_DCAN1_BASE? 1 : 2);
+        PlatformDcanClkConfig(UTILS_DCAN_INST == SOC_DCAN1_BASE? 0 : 1);

         Utils_dcanPlatformInit();
         /* Register Crossbars and IRQ numbers */
         Utils_dcanConfigIntr();
 Dong

Hi Dong, Is it possible for you to take a dump of DCAN2 registers and DCAN2 message RAM? Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi Dong, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Ticket Name: RTOS/TDA2: Change IVAHD encoding method from H264 to MJPEG

Part Number: TDA2 Tool/software: TI-RTOS Hi How can i modify the IVAHD encoding parameters to enable/change encoding from H264 to mjpeg. Is there any example that shows mjpeg encoding configuration. Regards Mayank

Hi, Please refer the below file vision_sdk\apps\src\rtos\usecases\vip_single_cam_view_encdec\chains_vipSingleCam_EncDec_Display.c check chains_vipSingleCam_EncDec_Display_SetEncPrms() function. Regards, Anuj

Hi, Its been since any update on this thread. I hope the issue is resolved. Regards, Anuj

Ticket Name: TDA4VMXEVM: 32.768KHz

Other Parts Discussed in Thread: TDA2 In PROC079E2A SCH, component U152 and Y8 can be saved if we use PROC078E5 (Locationn Y8) as SOC 32.768KHz source? One is using RTC (Coin Batt) Power and The other is using SOC standby power, right?

Hi Alex, TDA4 doesn't include a RTC hardware on-chip like TDA2 did. If your design requires "real" RTC function, external RTC IC/crystal/battery must be used. The 32.768k crystal connected to the SoC is for an optional oscillator used in some low-power modes, for example, for precise clocking of timer modules. Regards, Stan

Ticket Name: TDA2SX: TIDL conversion

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi everyone, I have one model which I want to convert to be able to use it on TDA2. Model is trained in Caffe framework. Model is trained for pedestrian detection and output is represented by 100 bounding boxes where every bounding box is described by 7 attributes: 1. BBox index 2. label ID 3. confidence 4. x1/width 5. y1/height 6. x2/width 7. y2.height I did conversion with tidl_model_import.out application, model is tested with eve_test_dl_algo.out.exe application and as a result stats_tool_out.bin file is generated. What I noticed is that not all information about bounding boxes are populated. Instead of 100 bbox information, I got a lot less. For other bounding boxes, all attributes are populated with zeros instead of BBox index which have value -1. Can this be sign of not good conversion process? Output file is in attachment. stats_tool_out.7z Thanks in advance, Sasa

TIDL outputs list of object which are having probability (Score) higher than the requested in the deploy.prototxt. -1 in the list indicates the end of the valid object list.

Ticket Name: TDA2SX: TDA2s boot

Part Number: TDA2SX HI。 Ｉ　ｓｅｔ　ｂｏａｒｄ　　ｂｏｏｔ　ｆｒｏｍ　ｅｍｍｃ． ｂｕｔ　ｗｈｅｎ　I　　ｗａｎｔ　ｔｏ　ｄｖｒ　ｉｎ　ｔｈｅ　ｓｄ　ｃａｒｄ，　ｔｈｅｎ　　ｉ　ｐｌｕｇ　ｔｈｅ　ｓｄ　ｃａｒｄ　，ｔｈｅ　ｂｏａｒｄ　ｃａｎ　ｎｏｔ　ｂｏｏｔ　ｆｒｏｍ　ｅｍｍｃ，ｂｅｃａｕｓｅ　ｉｔ　ｔｈｉｎｋ　ｔｈｅ　ｓｄ　ｃａｒｄ　ｉｓ　ｂｏｏｔ　ｄｅｖｉｅｃｅ．ｈｏｗ　ｃａｎ　　ｉ　ｓｌｏｖｅ　ｉｔ．（ｓｄ　ｃａｒｄ　ｉｓ　ｅｍｐｔｙ，ｓｏ　ｔｈａｔ　ｈａｓ　ｎｏ　ｂｏｏｔ　ｆｉｌｅ　ｉｎ　ｔｈｅ　ｓｄ　ｃａｒｄ）． my boot mode is : support boot from sd ,emmc .

Hi, can you share which SYSBOOT settings you use for emmc boot? Regards, Yordan

hi ,i Set sysboot [5:0] 000010

Hi, can you try to set sysboot [5:0] to 000111. Your value sets the boot order to USB -> SD card -> eMMC, you can look at "Table 29-9. Booting Devices Order" in device's TRM: Regards, Yordan

Ticket Name: TDA3XEVM: I configured 1243 through TDA3x. The parameters are workable, but an error was reported. With the same parameters, everything was normal on DCA1000

Part Number: TDA3XEVM Other Parts Discussed in Thread: TDA2, AWR1243 Hi Team, With the same parameter configuration, TDA3x reported an error (radar-framecopy instance was used). Parameter configuration comparison: mmwavestudio： The “chains_common_sample_ar12xx_config.c” part of the TDA3x routine: Best regards, Katherine

Hi Katherine, We won't be able to support Radar with TDA2 or TDA3. Please consider moving the other radar devices based on the below link. https://www.ti.com/sensors/mmwave-radar/overview.html Regards, Stanley

Hello Stanley, How were parameters such as Idle Time of AWR1243 calculated based on the sampling rate and slope? Is there any requirement for minimum precision? Because I found that the parameters I set randomly could easily lead to false targets. Regards, Katherine

Hi Stanley, Could you please follow up on my issue? Regards, Katherine

Hi Katherine, As indicated by Stanley, we will not be able to support the Radar SDK with TDA2/TDA3. These SDK's are fairly old and there are newer/better options that exist. Kindly consider moving to the newer offerings from TI. Regards Karthik

Ticket Name: TDA2: Model import and inference on TDA2XX

Part Number: TDA2 Hi, I have designed and trained my own model which is a classifier plus Jacinto SSD to detect cats & dogs in images. Following are the model's details: 1. Input resolution: 512 x 512 2. Number of layers: 50 [I have verified that configurations to all layers are within the limits mentioned in TIDeepLearningLibrary_UserGuide.pdf ] 3. Total GMACs: 1.1497 4. Processor Vision SDK version: 03.05 5. Number of classes: 2 [Cat & Dog] I can perform Caffe inference using this model on PC and the output is as expected. However, once model is imported successfully using Import Tool; it inferences erroneously on TDA2XX using TIDL OD library. I observe too many false positives. I can only see dog is getting detected NOTE: Visualisation script experienced invalid co-ordinates for detected objects. I have attached below files from my end. Please look into these and share your inputs to rectify object detection outputs. deploy.prototxt Import Config.txt [ Import Configuration File] Import Logs.txt dog_512x512.y [Input Image] cat_dog_ssd120000.caffemodel NET_OD.BIN PRM_OD.BIN Regards, Premchand Cat_Dog_SSD.zip

Hi, To add, the model was trained using Caffe Jacinto framework. Please find additional attachments as follows: Cat_Dog_Inference_Desktop.mp4 [Model inference using Caffe on the desktop machine.] Cat_Dog_SSD_Inference.jpg [Model inference using TIDL Inference on TDA2XX ] Regards, Premchand

Please find attached folder for previous post. Cat_Dog_Inference.zip

Hi, Could you try below.. 1. Can you display only strong objects from output, that is objects with score >0.3 only and check the output display 2. Can you change "quantRoundAdd" to 50 (default value) in the import config and check Thanks, Praveen

Hi Praveen, 1. I have already been displaying strong objects i.e. score > 0.3. 2. I changed "quantRoundAdd" to 50 in import config. This did not resolve issue on TDA2X however, I observed that detected bounding boxes with visualization code are within the limit of the image of resolution. Additionally, I tried out few more combinations in import config today which are as follows: "quantRoundAdd" to 50 and "numParamBits" to 10. "quantRoundAdd" to 50 and "numParamBits" to 8. Configured layers with size less than 64 X 64 to have dense convolution. Neither of these combinations resolved my issue. Regards, Premchand

Hi, Is there any update on this? Regards, Premchand

Can you try setting below create time parameter createParams.quantMargin = 30;

Hi, It did not resolve the issue. However, I observed that earlier random false detections were for Dog and now it is for Cat. FYI, I had set parameters as follows: quantHistoryParam1 = 20 quantHistoryParam2 = 10 quantMargin = 30 Please find attached image for detection results.

Is the network produces expeted result during import step for possitive sample? Is the network produces expeted result in SDK usecase for possitive sample? Is this issue specific to false dtection in negative smaple?

Hi Kumar, 1. The network produces somewhat positive result to positive sample during the import step. Please find below output for the same. 2. Network does not produce expected result in SDKuse case for a positive sample. Please find below output for the same. 3. The issue is not specific to just negative samples on TDA2XX, issue is also regarding reasonable detections for positive samples as well.

Can you try this cat image with import step and confirm the behavior.

Hi Kumar, I tried this cat image with import step but the detection is not similar to detection for cat image on TDA2XX. Please find below image. Legend for rectangle color: Green -- Dog Red -- Cat Regards, Premchand

Refer below issue in caffe-jacinto and make sure you get expected accuray when you quantize the floating point network github.com/.../11 github.com/.../29 github.com/.../26 Ans then refer the section 3.8 in uers guide to match the result with caffe jacinto. you can aslo refer FAQ 13

Ticket Name: TDA4VMXEVM: how to control pin mux.

Part Number: TDA4VMXEVM Hi,as you konw,TDA2S set pin mux in the uboot. but i dont find in the TDA4 ,can you tell me where is the pin's mux setting. Thank you!

The pin configuration for this wave of devices (TDA4/J7) is done in the device tree files (dts). See section "3. Foundational Components » 3.2. Kernel » 3.2.1. Users Guide" in the processors SDK docs. You can also use the sysconfig tool "https://dev.ti.com/sysconfig/" to generate configuration and paste it over in the dts file and recompile. See section "Docs » 3. Foundational Components » 3.4. Tools » 3.4.2. Pin Mux Tools" in the processors SDK docs. Hope it helps, thanks, Alex

Ticket Name: TDA4VM: Is there a kernel that can mix two images?

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi TI, I want to draw an icon on an image. I use DrawIcon link to achieve this on tda2 platform. So Is there an kernel like DrawIcon on tda4? Regards， Damon.

Additionnal: I mean using CPU to do pixel-blending not GPU

Hi Damon, Do you mean to blend two images? I think there is no existing kernel, but you could use DSS, two input pipelines and overlay manager could be used to overlay/blend two images and send it out to the display. Regards, Brijesh

Hi Brijesh, Thank you and yes, I want to blend two images.If so, I will try to add an userkernel to do this job.Using DSS may not be the right choice as it will take up two channels and can't send the output image to other node. Regards, Damon

Thanks Damon, closing this ticket.

Could you please take a look at my other question? https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1096110/tda4vm-how-can-i-add-a-new-kernel-running-on-r5f

Sure, lets continue our discussion on the other ticket.

Ticket Name: TDA3: TDA3x EVE registerm map

Part Number: TDA3 Hi All. Please advise, where i can find documents which contains TDA3 EVE registers map and how i can access them. It doesn't included in TDA3x TRM. There are few EVE EDC registers mentioned in "ECC/EDC on TDAxx" document, but i can't find them in TDA3x TRM. Thanks in advance, Sergey.

Hi Sergey, The registers are given in chapter 6.1.5.2 EVE Registers. Is there a particular register that you cannot find? Regards, Rishabh

Dear Rishabh. Thanks for your reply. But there is not 6.1.5.2 EVE Registers chapter in latest "TDA3x Technical Reference Manual". Please advice where i can find proper document with mentioned chapter for TDA3x. Waiting for your reply, Best regards, Sergey.

Hi Sergey, Can you share the link of the document you are referring to? Regards, Rishabh

Please have a look at the next file: www.ti.com/.../spruie7c.pdf

EVE details are NDA only (i.e. you won't see EVE registers in the public TRM). Contact your TI representative to obtain the NDA TRM where you can find the details you need. thanks, Alex

OK, now i understand. Could you please send me document version with its Literature Number, so i could ask for proper document?

Literature Number: SPRUHQ7R Version "vR"

Hi Sergey, I am closing the thread as issue has been resolved. Regards, Rishabh

Sergey, Rishabh, We have started to expose the EVE registers publicly. The next rev of the TDA3 TRM will include the full details (not sure of planned date...). In the meantime, you can refer to the TDA2 TRM (Lit # SPRUI29F) on ti.com which already includes the full contents. The only difference is that TDA2 includes up to 4 EVEs and TDA3 only has 1. The addresses for EVE1 in the TDA2 are the same as the for the TDA3 EVE. Regards, Kyle

Ticket Name: Linux/PROCESSOR-SDK-TDAX: QLinuxFbScreen::connect: Invalid argument

Part Number: PROCESSOR-SDK-TDAX Tool/software: Linux I am trying to run QT application on PROCESSOR-SDK-TDA2-3.04 that supports VDRM controller. I am getting some errors when I am running that QT app with the command ./movable -platform linuxfb -display "LinuxFb:/dev/fb0" -qws QLinuxFbScreen::connect: Invalid argument Error reading fixed information LinuxFb: driver cannot connect Aborted (core dumped) Here is my configuration. ./configure -prefix /opt/qt-4.7.1 -embedded arm -platform qws/linux-x86_64-g++ -xplatform qws/linux-vsdk304-arm-gnueabi-g++ -depths 16,24,32 -no-mmx -no-3dnow -no-sse -no-sse2 -no-glib -no-cups -no-largefile -no-accessibility -no-openssl -no-gtkstyle -qt-mouse-pc -qt-mouse-linuxtp -qt-mouse-linuxinput -plugin-mouse-linuxtp -plugin-mouse-pc -opensource -qt-gfx-linuxfb -qt-gfx-qvfb Could you please give some inputs to resolve this issue. If I am doing some thing wrong in configuration or some where else.

Hi Raza, SDK 3.04 with vDRM support is not validated for QT applications. The filesystem provided with vision-sdk 3.04 doesn't have QT libraries. Are you trying too use linux fbdev here? This feature is no more supported, drm is the default display

Yes I am using fb0 that is linked to vdrm with soft link in this manner /dev/fb0 -> /dev/vdrm-controller-0 If this feature is no more supported so could you please help me out to run QT-4.7.1 application on it through VDRM, what is the procedure to get the display on the screen?

Ticket Name: Linux/TDA2EVM5777: calibration for 3D SV DEMO

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: Linux Dear Champs, I would like to check how Calibration can be run for 3D SV DEMO, and have 2 questions especially as below. * 4 camera image capture should be done in the target board and it should be input to calibration tool on the PC, right? How 4 camera image capture should be done in target board? * in the userguide, there should be 'TDA2x' directory on the SD/MMC card. where this directory should be created? is it on the root directory of root filesystem? or is it on the boot partition? Thanks and Best Regards, SI.

Hi SI, Can i which version of SDK are you using? also any particular reason for manual calibration? Regards, Sujith

Oh..sorry. VisionSDK v3.2. BR, SI.

Hi SI, If you are using D3 Skateboard and chart, it best to perform automatic calibration. You will have to create a folder in mmc/sd root folder itself. i.e. the folder when you have MLO/uenv.txt Regards, Sujith

Thanks Sujith, Their HW is TDA2 EVM + Vision Kit + OV10635(x 4) camera. is it possible to perform automatic calibration in this case? There is no specific reason to run manual calibration. it is OK just to run 3D SV DEMO. For directory, do you mean to create TDA2x directory in the boot partition with MLO? They failed to run automatic calibration when they create TDA2x directory in the boot partition. Thanks and Best Regards, SI.

Hi SI, For auto-calibration, customer should use the chart provided and ensure cameras are mounted as described in VisionSDK_UserGuide_2D_SurroundView_Demo.pdf, section 2.3 Mounting Cameras The lens play a significant role, please determine the lens that's being used. For some of the fish-lenses the LENS.BIN is provided in the visionsdk. We could generate the LENS.BIN by following steps listed in "VisionSDK_UserGuide_3D_SurroundView_Manual_CalibTool.pdf" Various tables required for calibration is expected to be stored in mmc/sd card. Yes, you will require create a folder named "TDA2x". Below is a snap shot of my mmc/sd Regards, Sujith

Sujith, And for directory, should there 'uenv.txt'? I'm wondering why my customer's directory was not worked. my customer created the directory in the boot partition as you mentioned and the log is below. [HOST] [HOST ] 631.756877 s: CHAINS: -------------------------------------------------- [HOST] [HOST ] 631.756877 s: CHAINS: TDA2X Folder not present in MMC/SD [HOST] [HOST ] 631.756908 s: CHAINS: Create TDA2X folder and copy the following files from [HOST] [HOST ] 631.756908 s: CHAINS: '/vision_sdk/tools/surround_vision_tools/Srv_LUTs': [HOST] [HOST ] 631.756908 s: CHAINS: 1. CHARTPOS.BIN [HOST] [HOST ] 631.756908 s: CHAINS: 2. LENS.BIN [HOST] [HOST ] 631.756908 s: CHAINS: 3. LENS_2D.BIN [HOST] [HOST ] 631.756938 s: CHAINS: -------------------------------------------------- Thanks and Best Regards, SI.

Hi SI, Can you please check "VisionSDK_Linux_UserGuide.pdf" section 4.2 Regards, Sujith

Hi Sujith, Thanks for your support. I found there was some difference in the file name and it works well after correcting file name. Thanks and Best Regards, SI.

Hi SI, Thanks for the confirmation. Regards, Sujith

Ticket Name: SK-TDA4VM: TIDLRT multiple outputs

Part Number: SK-TDA4VM Other Parts Discussed in Thread: TDA2 Hi, I'm trying to deploy a model with multiple output tensors, I noticed this similar thread, my questions are: 1. I'm not confident about how to access multiple output tensors, based on this thread, the key is changing of "j" right? 2. I remember a long time ago, when deploying models, I need to deal with the paddings (both inputs and outputs) but I didn't find anything in this tidlrt code. 3. I also remember I need to deal with de-quantization scalar, how to get this number for each output tensor? My model is in caffe format and I had a hard time converting it to onnx, so have to stick with tidlrt. I guess a standard 3 output tensor OD example would cover all these questions, can someone help? Thanks, Neal

Hi Neal, 1. You will need to allocate an output tensor and then assign a pointer that TIDL-RT can use for copying memory out from the accelerator. 2. For paddings, could you give an example to clarify? The input tensor shape needs to match the model - this can be accomplished several ways, including padding, resizing/interpolation. For the outputs, do you mean paddings from the end of one output tensor to the next one if everything is in the same area of contiguous memory? If you're assigning output memory locations like above, then padding shouldn't be an issue 3. I don't believe you need to apply a de-quantization function on the output; that should already be handled on the output of TIDL. The outputs are most likely in fp32 Link to TIDL-RT documentation (this is sometimes difficult to find or search shows old versions): software-dl.ti.com/.../index.html Best -Reese

Thank you for the detailed information, I guess point 2 and 3 are tda2 era deployment routine. I don't have questions for now, I will try to follow your instructions first.

Sure Neal. Closing this thread. Regards, Pratik

Ticket Name: TDA2 and TDA3

Other Parts Discussed in Thread: TDA2 Can you please advise regarding the customer questions below? Please see the latest update from the customer: What can you tell me about the TDA2 and TDA3x processors? Can they / do they run Linux? (I’m guessing yes) www.ti.com/.../technicaldocuments The information on the web seems a bit sketchy. Are there available evaluation boards? What cost? What are the capabilities of the evaluation board? This link has a picture of a TDA2x “evaluation board” but the ability to purchase it seems somewhat lacking. www.ti.com/.../sprt681.pdf Same document for TDA3x www.ti.com/.../sprt708a.pdf Here is a datasheet for the TDA3 but again not very detailed; www.ti.com/.../tda3.pdf We are very interested in multiple FPD (LVDS) links on a board. There is also a TI automotive camera evaluation displayed but again very little information regarding it: www.ti.com/.../PMP9351 Can I purchase this as an “evaluation module”?

We have moved your post to the appropriate forum.

Ticket Name: PROCESSOR-SDK-TDAX: when I debuged the app_tidl(vision_apps/apps/dl_demos/app_tidl), I have some questions

Part Number: PROCESSOR-SDK-TDAX Other Parts Discussed in Thread: TDA2 question1: In the file of vision_apps/utils/ipc/src/app_ipc_linux_rpmsg_char.c, I found that obj->ipc_notify_handler was a function pointer to the type of app_ipc_notify_handler_f.But,I don't know it pointer to which function when call obj->ipc_notify_handler(app_cpu_id, payload),the function show as below. typedef struct { app_ipc_init_prm_t prm; void *hw_spin_lock_addr; app_ipc_notify_handler_f ipc_notify_handler; int tx_fds[APP_IPC_CPU_MAX]; uint32_t local_endpt[APP_IPC_CPU_MAX]; rpmsg_char_dev_t *rcdev[APP_IPC_CPU_MAX]; pthread_t task; int unblockfd; } app_ipc_obj_t; static void appIpcRpmsgRxHandler(uint32_t app_cpu_id, uint32_t payload) { app_ipc_obj_t *obj = &g_app_ipc_obj; if(app_cpu_id<APP_IPC_CPU_MAX) { #ifdef APP_IPC_DEBUG appLogPrintf("IPC: RX: %s -> %s (port %d) msg = 0x%08x\n", appIpcGetCpuName(app_cpu_id), appIpcGetCpuName(appIpcGetSelfCpuId()), (uint32_t)obj->local_endpt[app_cpu_id], payload); #endif if((payload & 0xFFFF0000) == 0xDEAD0000) { /* echo message dont send to handler */ printf("IPC: RX: %s -> %s (port %d) msg = 0x%08x\n", appIpcGetCpuName(app_cpu_id), appIpcGetCpuName(appIpcGetSelfCpuId()), (uint32_t)obj->prm.tiovx_rpmsg_port_id, payload); } else { if(obj->ipc_notify_handler) { obj->ipc_notify_handler(app_cpu_id, payload); } } } } then I found a suspectable call in the function (void tivxObjDescInit(void)),detail definition showed as below , I can't confirm that,because I added some printf information("======") ,but it didn't show in the terminal. void tivxObjDescInit(void)(tiovx/source/framework/vx_obj_desc.c) { printf("=====================================\n"); tivxPlatformGetObjDescTableInfo(&g_obj_desc_table); tivxIpcRegisterHandler(tivxObjDescIpcHandler); printf("=====================================\n"); } question2: I found that there are four definitions about the function tivxInit(void), in order to determine which tivxInit() function to be called , so I added some printf information(printf("from file : %s ; from function: %s\n", __FILE__, __FUNCTION__);) in every tivxInit() function, before called the tivxInit(void) ,I added printf("++++++++++++++++++++++++++\n"); But there are nothing about from file : %s ; from function: %s\n", __FILE__, __FUNCTION__ ,Only show the "+++++++++++++++++++++++++++" in the terminal. So don't kown why?

Hi, Although there are 4 tivxInit, they are used for different purpose/platform. The one defined in vision_sdk/linux (biod)/tivx_init.c was used on TDA2/3x devices, so you could ignore them. The one defined in pc/common/tivx_init.c is used in PC emulation mode. The one defined in psdk_j7/common/tivx_init.c is actually used on TDA4x.. For the first question, yes, this is where IPC handler is registers. The call flow is tivxIpcHandler -> g_ipc_handler. Regards, Brijesh

Ticket Name: Linux/TDA2: Where is the image data memory location of camera source?

Part Number: TDA2 Tool/software: Linux Hi Sir, I am using TDA2x CPU board + Vision Board + daughter board + OV1652x sensor and SDK is PROCESSOR_SDK_VISION_03_03_00_00 with TDA2XX_EVM_LINUX_ALL define. I want to do some image change, but I didn't find the image data buffer for OV16530 image source. I use surround view use-case, there should be 4 image memory locate address? My you tell me which code structure is recoding image buffer address or which document descripts this part ? Thanks. Ranny.

Hi Ranny, What exactly do you want to change in the image buffers? The buffers are allocated in the capture VIP link and passed across links.. You could get the addresses of these buffers from the capture link. But if you would like to perform some image processing, then i would suggest you write alg plugin and process the images in your alg plugin. You could refer to frame copy alg plugin and write a new one for your algorithm. Rgds, Brijesh

Hi Sir, Thank you for reply. because of the sensor data passes through the Vision board to CPU board, I want to make sure the data in image buffer is corrected that same as I expect format from image sensor. I already checked the buffer and the image data has no problem, I will use the plugin rule to add the algorithm process next step. Thank you. Ranny.

ok thanks for the update.

Ticket Name: RTOS/TDA2: Update appimage by SD card

Part Number: TDA2 Tool/software: TI-RTOS Hi Expert, I'm running PROCESSOR SDK VISION V3.04 RTOS on xc5777x evm. Using the "Load using QSPI" to launch the board, how do I update the appimage with the sd card? Could you please give some suggestion here? Thanks in advance.

Hi, Can you look at "Load using SD card" section of VisionSDK_UserGuide_TDA2xx.pdf. Regards, Rishabh

Hi, I need the sd card to update the appimage inside the QSPI flash. "Load using SD card" section only boot? Thanks in advance.

Hi, Unfortunately we don't have any application that will read the image from SD card and flash it to QSPI. You need to write this application yourself by referring to PROCESSOR_SDK_VISION_03_04_00_00\ti_components\drivers\pdk_01_10_00_08\packages\ti\drv\stw_lld\examples\mmcsd\sd_file_io and PROCESSOR_SDK_VISION_03_04_00_00\ti_components\drivers\pdk_01_10_00_08\packages\ti\boot\sbl_auto\qspiflash\examples\qspi_flash_writer. Regards, Rishabh

Ticket Name: TDA2EX17EVM: linux

Part Number: TDA2EX17EVM I used the linux which Ti VisionSDK document (VisionSDK_Linux_UserGuide.pdf) recommended. Then I got some fail in TC8 test cases (www.opensig.org/.../9_OA_Automotive_Ethernet_ECU_TestSpecification_v1.pdf). I do not understand why there are some strange result on the ethernet test, e.g., not getting TcpFlagAck, connection illegal for this process. Whether the linux network kernel follow RFC793 which is the TC8 requirement? How can I pass these TC8 testcase? It seem to me that the ethernet protocols (e.g. tcp/ip arp icmp udp) are implemented by the linux kernel. Can anyone confirm that this linux support TC8? By the way, I knew there are some network parameter on "/proc/sys/net/ipv4/" and how could I change it ? thanks ref : TC8 test report 20200505_Report_TC8_Test_Configuration.pdf

Hello. From the logs in the test report, you are failing arp and icmp tests, which indicate a setup issue is likely. We don't explicitly test RFC793 compliance in our testing, but we do heavily use tcp/ip/arp/icmp in our system testing. Best regards, Dave

Dave Bell said: Hello. From the logs in the test report, you are failing arp and icmp tests, which indicate a setup issue is likely. We don't explicitly test RFC793 compliance in our testing, but we do heavily use tcp/ip/arp/icmp in our system testing. Best regards, Dave Hi Dave Thanks for your reply. I don't get it. setup issue? Is it hardware issue or software issue? How should I do on linux now? Should I try to change my ethernet configuration? Do you have any suggest about arp/icmp? and maybe I can try it. B/R JY Chou

JY, We let this post lock and it was missed. Are you still facing issues with your setup or have you resolved? Best regards, Dave

Ticket Name: TDA2: How to disable EMIF2?

Part Number: TDA2 Hi all, If we want to disable EMIF2, what configurations we should modify? Could you please help to describe it? Thanks~

Hi, Can you give more details on software you are using. Regards, Rishabh

Hi Rishabh, We use SDK_Vision_03_04_00_00 and rtos for the TDA2xx. Thanks!

Hi, You can set MODULEMODE field in CM_EMIF_EMIF2_CLKCTRL to 0x0 to disable EMIF2 module. Regards, Rishabh

Hi, i can't find which file has this configuration. Could you please help to tell me where is the file? And another question, does there any default setting would use EMIF2? Thanks!

Hi, What is the build configuration you are using? Default Vision SDK BIOS uses 512 MB and EMIF1. Regards, Rishabh

Hi, I need some times to double check the configuration in our code. So I will close this thread, and I will create a new one if I have another question. Thanks for your help!

Ok. Thanks for the update. Regards, Rishabh

Ticket Name: CCS/TDA2SG: [TDA2] Does an usecase contain IVA H.264 Encode & H.264 Decode Link ?

Part Number: TDA2SG Tool/software: Code Composer Studio Hi, We have an usecase to encode H.264 video output to network & sometimes receive the H.264 video from network to decode it for display. Do we need to consider anything or any limitation ( such as the encode & decode cannot work simultaneously ) No matter RTOS or Dual OS (RTOS + Linux) Thank you !! Regards, Eten

Hi, You can use encode & decode links simultaneously but the limitation is 1) Both links can support 1080P@30FPS for a single channel. 2) Both links can support 7200P@30FPS for a four-channel. You can go through the following use-case for reference.(In this use-case both links are used) "vision_sdk/apps/src/rtos/usecases/vip_single_cam_view_encdec" Thanks Gaviraju Both links can support 1080P@30FPS for a single channel.

Part Number: TDA2 I tried this but somewhere i missed things. But now its working. Thank you! Regards surbhi

Hi, surbhi kumari, It seems that this is an answer for I will close this unintentionally opened thread. Regards, Mariy

Ticket Name: TDA2EVM5777: TDA2 DDR

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello I am study TDA2 VAYU_EVM, there are two channel of ddr3 channel 1 connect to 2 "MT41K512M16HA-125 AIT:A" & 1 "MT41K512M8RH-125-AAT:E" which is for ECC fuction and channel 2 connect to 4 "MT41K512M8RH-125-AAT:E" could I design our own TDA2 system using only channel 1 with 2 "MT41K512M16HA-125 AIT:A" & 1 "MT41K512M8RH-125-AAT:E" ? and let channel 2 to be float? thank you

Hi Locust, The two DDR channels are identical and independent. I see no reason why not use only channel 1. Regards, Stan

Hi Stan Thank you for the answer. And should I change any software setting in bootloader or another place? or I can just tear down the ddr on channel 2? thank you

Yes, DDR configuration should be updated. regards, Stan

Ticket Name: Compiler/TDA2EVM5777: How can i capture specific frame in Sgx link?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi, I'm trying to connect my camera to TDA2 board. I'm using Vision_sdk ver 3.6. In lvds_single_cam_sgx_display usecase, the captured frame has invalid data format. In capture link, i set input data format as YUV_422I_YUYV and output data format as YUV_422I_YUYV also. (I don't have exact information about this camera data format) To get valid data format, i'm going to dump the frame and get valid data format using YUV player. To do that, i add the code to save specific frame as raw file. The below is what i added in sgxFrmcpy ProcessData function. if(customTmp == 10) { FILE *fp = NULL; fp = fopen("/opt/vision_sdk/FRAME.RAW", "wb"); if (fp == NULL) { Vps_printf("[DEBUG] File not opened for capturing frame"); } else { Vps_printf("[DEBUG] File write is Started"); } fwrite(pBuffer->payload, pObj->inQueInfo.chInfo[pBuffer->chNum].width * pObj->inQueInfo.chInfo[pBuffer->chNum].height*2, 1, fp); //Vps_printf("[DEBUG] %d written", pBuffer->payloadSize); fclose(fp); } customTmp++; The usecase is going well but the file that is created by this cord is now displayed normally when i use YUV player. The below images are captured images what i refered. <invalid dataformat> <saved frame using fwrite> I changed input/output data format regarding all possible combinations. However, any one was not showed normally. Any suggestion? Regards, Yoo

Hi, Which camera sensor are you using? Is it a VIP capture or CSI? Can you try out with BIOS single cam display usecase. You can modify the same usecase and add dup and null link to dump that data into file to cross verify. Regards, Anuj

Hi Anuj, I'm using VIP capture. I found the reason why the color space seems wrong. The input format of my camera is YUV422I_YVYU. However, the capture link inparams only support YUV422P, YUV444P, RGB24_888 and outparams only support YUV422I_YUYV, YUV420_SP_UV, YUV422SP_UV, RGB24_888, ARGV32_8888, RAW_VBI. And display link output only support RGB24_888, YUV422I_YUYV as following guide document. Could you suggest any solution for making possible capture link get data as YUV422I_YVYU and also output as YUV422I_YVYU in chain that is containing SgxFrmcpy, Display link? Regards, Yoo

Hi Yoo, Sorry could not get your question. You want to capture YVYU format and get it displayed.. Typically the YUV422 format is YUYV or UYVY.. In your case, it seems chroma component is swapped.. When we say input format is YUV422P to the VIP driver, we are just information the driver that input YUV422. This is not VIP module configuration.. Using this format, VIP driver comes to know if there is any need to enable CSC in the path or not.. Are you using 8bit interface? If yes, which component comes in on the first clock cycle? Could you please help me understand your input details? I could help with the format you would need to set in capture and display.. Rgds, Brijesh

Hi Brijesh, I solved my problem by shifting 2 YUYV data to make YVYU. Thanks for your reply. Regards, Yoo

Ticket Name: Is it possible to do QSPI IO ReCalibration in function [SBLUtilsScaleIODelay] ?

Other Parts Discussed in Thread: TDA2 Hi We changed QSPI to from 48MHz to 76.8MHz, also have checked code in [SBLUtilsScaleIODelay] We find [gPadDelayConfigCommon_1_0], [gPadDelayConfigGpmcPadOther_1_0], the list seems too many IO pins for us, and some pins in the list drive off some modules such as I2C, So we remove the list [gPadDelayConfigCommon_1_0], [gPadDelayConfigGpmcPadOther_1_0] and only do IO ReCalibration for QSPI as below [gPadDelayConfigGpmcPadQSPI], Then we want to know if it is possible for us only do the IO ReCalibration with [gPadDelayConfigGpmcPadQSPI]? static sblutilsPadDelayConfig_t gPadDelayConfigGpmcPadQSPI[] = { /* CTRL_CORE_PAD_GPMC_A3 -> QSPI1_CS2 (PIN_INPUT) MANUAL delaymode */ { 0x04C, 0x00070101, { 0x0000, 0, 0 }, { 0x0000, 0, 0 }, { 0x0218, 0, 0 } }, /* CTRL_CORE_PAD_GPMC_A4 -> QSPI1_CS3 (PIN_INPUT) MANUAL delaymode */ { 0x050, 0x00070101, { 0x0000, 0, 0 }, { 0x0000, 0, 0 }, { 0x0224, 0, 0 } }, /* CTRL_CORE_PAD_GPMC_A13 -> QSPI1_RTCLK (PIN_INPUT) MANUAL delaymode */ { 0x074, 0x00070101, { 0x0144, 0, 0 }, { 0x0000, 0, 0 }, { 0x0000, 0, 0 } }, /* CTRL_CORE_PAD_GPMC_A14 -> QSPI1_D3 (PIN_INPUT) MANUAL delaymode */ { 0x078, 0x00070101, { 0x0150, 0, 0 }, { 0x0000, 0, 0 }, { 0x0000, 0, 0 } }, /* CTRL_CORE_PAD_GPMC_A15 -> QSPI1_D2 (PIN_INPUT) MANUAL delaymode */ { 0x07C, 0x00070101, { 0x015C, 0, 0 }, { 0x0000, 0, 0 }, { 0x0000, 0, 0 } }, /* CTRL_CORE_PAD_GPMC_A16 -> QSPI1_D0 (PIN_INPUT) MANUAL delaymode */ { 0x080, 0x00070101, { 0x0168, 0, 0 }, { 0x0000, 0, 0 }, { 0x0170, 0, 0 } }, /* CTRL_CORE_PAD_GPMC_A17 -> QSPI1_D1 (PIN_INPUT) MANUAL delaymode */ { 0x084, 0x00070101, { 0x0174, 0, 0 }, { 0x0000, 0, 0 }, { 0x0000, 0, 0 } }, /* CTRL_CORE_PAD_GPMC_A18 -> QSPI1_SCLK (PIN_INPUT) MANUAL delaymode */ { 0x088, 0x00070101, { 0x0000, 0, 0 }, { 0x0000, 0, 0 }, { 0x0188, 151, 0 } }, /* CTRL_CORE_PAD_GPMC_CS2 -> QSPI1_CS0 (PIN_INPUT) MANUAL delaymode */ { 0x0B8, 0x00070101, { 0x0000, 0, 0 }, { 0x0000, 0, 0 }, { 0x0374, 0, 0 } }, /* CTRL_CORE_PAD_GPMC_CS3 -> QSPI1_CS1 (PIN_INPUT) MANUAL delaymode */ { 0x0BC, 0x00070101, { 0x0000, 0, 0 }, { 0x0000, 0, 0 }, { 0x0380, 22, 0 } }, };

Hi, You can do the io delay calibration for QSPI pins as you mentioned. But it is recommended to do the io delay recalibration for all the pins used in your use case at the boot loader at the start up. Also the split in multiple structures for different pads is done basically for the NOR boot mode. For QSPI boot mode you may create a single structure with all the pads to be used in your use case. Regards, Prasad

Hi Mi, On TDA2 devices TI strongly recommends to do all the pin mux along with IO delay re-calibration and manual/virtual delay configuration in isolation in order to guarantee IO timings. Please make sure to update IO delay re-calibration code accordingly if you create a single structure. Regards, Rishabh

Ticket Name: Compiler/TDA2PXEVM: Missing binary file for CortexA15_0

Part Number: TDA2PXEVM Tool/software: TI C/C++ Compiler Hello TI Applications Engineers, I am currently developing on the TDA2PXEVM with fusion application board using the vision SDK, and attempting to interface with the DS90UB953EVM. By loading the prebuilt binaries for version 3.04 of the SDK onto an SD card, I can reach the demo usecases menu via serial terminal. However, when I try to run Single Camera Usecases -> 1 CH UIP Capture + Display to talk to the image sensor on the DS90UB953EVM, I get the error "i2c4 transfer to slave address 0x30 failed". This is after setting up the DS90UB953EVM according to its user guide. I tried modifying the slave ID and slave ID alias registers on the DS90UB953EVM via Analog Launchpad, but that didn't seem to help. My thought was that the deserializer i2c addressing registers on the fusion application board need to be configured to match those of the serializer on the DS90UB953EVM. I attempted to gain access to these registers by loading version 3.03 of the SDK (version 3.04 failed to compile, I kept getting "system cannot find file specified" errors) from CCS (version 8.1.0) rather than booting from SD card. Following the user guide, I was able to load all the specified binaries onto their respective cores, except for "vision_sdk_a15_0_debug.xa15fg", which is supposed to go on CortexA15_0, but doesn't show up when I search for it in windows explorer. Any help with these issues would be greatly appreciated. Thanks, Richard

Hi Richard, Which version of vision sdk are you trying to build? Which config have you selected in Rules.make for building it for TDA2Px? Can you check in cfg.mk file whether you A15 core is included or not? Have you made any changes in vision sdk? if yes.then can you brief all those changes. Regards, Anuj

Hi Anuj, I am trying to build version 3.03 of the vision SDK. I am using the config "tda2xx_evm_bios_all". Yes, I have included the A15 core in the cfg.mk file. I have not made any changes in vision sdk. Thanks, Richard

Hi Richard, Can you check if you have vision_sdk_a15_0_release.xa15fg in the binary folder. Regards, Rishabh

Hi Rishabh, I do have that file in the binary folder, I will try loading it alongside the others. Thanks, Richard

Hi Richard, I would suggest you to build Vision SDK in debug mode in order to debug as it will have all symbols and compiler would not have optimized the code. You should set PROFILE in vision_sdk\apps\configs\tda2xx_evm_bios_all\cfg.mk to debug for this. Regards, Rishabh

Ticket Name: TDA2: DDR3 Routing Specifications

Part Number: TDA2 Referring to TDA2 data sheet, Table 8-52, are there typo errors in unit? Example, should the A1+A2 length in mil instead of ps? Or how to correlate the max 500ps to signal length?

Hi, The units ("ps") are correct. Determining the max signal length (in mils) will be dependent on the material of the PCB and whether the signals are routed as microstrip or stripline. Best regards, Kevin

Ticket Name: TDA2: TIDL Normalize Layer

Part Number: TDA2 Hello, I am trying to convert Caffe-Jacinto model with TIDL convert tool. Problem that I have is that Normalize Layer (from Caffe-Jacinto) is not supported with current version of TIDL (1.1). My question is will it be supported in future TIDL releases and could I use some other norm layers instead? Thanks, Mladen Stupar RT-RK

TIDL supports Batch Normalization layer please use the same. As of now, no plan to support Norm Layer.

Ticket Name: Looking for a, ISP chip that can handle two 1080p60 streams

Other Parts Discussed in Thread: TDA2 Hello, I am building a stereovision setup that will use two 1080p60 camera sensors that will either use MIPI CSI-2 or (SUB) LVDS. The ISP chip should be as cheap as possible and handle the two streams so that it can give them to a main processor that will run algorithms to determine the depth. It should have these protocols: CSI-2, LVDS, USB and PCIe.

TDA2Px

I see that many of the TDA2 and TDA3 chips have multi camera interfaces, how would I know that the TDA2Px chips are the best ones? I am also planning on adding an IR pattern chip like the Panasonic Grid-EYE and the SoC should include a timestamp as well.

Hi, Both TDA3x and TDA2Px support CSI serial as well as parallel input interface. On CSI input interface, we could interleave frames from multiple camera and both of these devices can receive them and demux them.. There are multiple parallel interfaces supported and you could connect one camera to each of these parallel input paths. Rgds, Brijesh

Thank you for the asnwer. However, I see that most camera sensors that can capture 1080p at 60 fps use the SUB LVDS serial connection, for example the Sony IMX265LQR ( www.sony-semicon.co.jp/.../industry.html) We are looking to add a third camera for NIR (which will most likely be the same sensor) or an other use. Would it still be possible to use a TDA chip to capture that simultaneously?

You would require external device to convert from LVDS to CSI.. Rgds, Brijesh

Sorry, you would require external module to convert from LVDS to CSI/Parallel. Three cameras are possible to capture over CSI.. Rgds, Brijesh

Thank you for the response. As seen in paragraph 6.1 from the TDA2Px datasheet "And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB." Wouldn't this mean that I don't need the LVDS to CSI/Parallel converter?

Hi, I think it says it supports multi-camera interface for LVDS based surround view systems, but it requires external device (ub960) to convert from lvds (FPD Link III) interface to CSI interface.. Rgds, Brijesh

Thank you, this clarifies a lot. This chip is exactly what I need to bridge the sensors before the ISP chip. It's difficult to find an ISP that supports such inputs simultaneously without looking at FPGAs.

Hi Petros, Please close the thread if your question is answered. Rgds, Brijesh

I do have one more question regarding to this chip. Is FPD Link III the same as LVDS? In other words, can I directly connect a LVDS camera to the ub960 chip?

Ticket Name: TDA2SX: generation temperature of the device from the total power

Part Number: TDA2SX Dear Support member The customer is considering a system using TDA2Sx. Using the Power_consumption sheet provided by TI, we calculated a total power as 7718 mW. Is it possible to calculate the generation temperature of the device from this total power? Best Regards,

Dear Support member Could you reply for this question? Best Regards,

Hello, It is not possible to accurately predict the temperature. We do provide a thermal model that can be used along with a model of the customers system to estimate the power based on the use case and thermal characteristics of the SoC and heat sink etc. TDA2x Thermal Model Regards, Kyle

Ticket Name: RTOS/TDA2EVM5777: VLIB Test Report memory design

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Dear experts, We are using TDA2 C66 VLIB for opencv replacement. When we use profile function to calculate VLIB API performance, it differs a lot with the number in test report(about 10 times more than that number). Could you please expain more about how the test report is profiled? On L1SRAM? on L2SRAM? Can we achieve the same number as the test report on target application? Thanks & Best Regards! ZM

ZM, The values in the test report are obtained when running the tests using the DSP cycle accurate simulator on CCS5.x. It is effectively the performance assuming that all code, stack, data are in L1 RAM; what we call flat memory model. It only accounts for the performance of the DSP core with NO memory hierarchy stalls. As such, this is typically a best case baseline which a real world system can only hope to get close to based on how the memory system is defined. In this way, the numbers are helpful in comparing the core performance with each other, and gives an upper bound as to the performance you can get close to based on memory model optimizations, such as cache configuration or using DMA to bring in data into L2SRAM or L1D SRAM. I have attached a spreadsheet which summarizes the test performance, when run in on VLIB 3.3.0.1 release, on a sample of different memory models, to give you a better idea of what to expect based on the memory model you are using. The memory configuration number in the spreadsheet corresponds to the following legend: perf_vlib_3_3_0_1_C66_tda2.xlsx Memory configuration of test

1. Simulator - flat memory modoel. Cycles assume all of data/code accesses are in L1 memories.  This is to serve as a baseline which indicates the best possible performance on the particular DSP.

2. L2 Cache = 256kB, all code and data in DDR - pure cache memory model.

3. L2 Cache = 128kB, all code in DDR, data buffers in L2RAM - on TDA2x, this means 128k+32k RAM for buffers. 

4. L2 Cache = 64kB, all code in DDR, data buffers in L2RAM - on TDA2x, this means 192k+32k RAM for buffers.  

5. L2 Cache = 32kB, all code in L2RAM, data buffers in L2RAM -  on TDA2x, this means 224k+32k minus size of code RAM for buffers, .  I presume you are using the option 2 by default: All code and data in DDR with cache. As you can see from the spreadsheet, this is typically the worst performance (unless you have cache turned off). Options 3-5 are meant to reflect if DMA is used to move data from DDR into L2SRAM, so the processing can happen on data already in L2SRAM. This removes the expensive L2 data cache miss penalty on the data access, and leaves only the L1 cache miss penalty. Hopefully, this spreadsheet can help you determine if it is worthwhile for you to make memory movement optimizations such as using DMA to move data to L2 or L1 data. If you are still seeing a significant delta, you may want to consider the system and DDR clocks you are using, as this performance is measuring DSP clock cycles. If DDR clock is set to lower, then the number of DSP clocks may go up due to the additional memory system stall cycles imposed by lower DDR clock. I am using the default clock settings from the CCS gel file for TDA2x. Best Regards, Jesse

Thanks Jesse. This statistic helps a lot.

Ticket Name: Compiler/TDA2: Buying a TDA2x

Part Number: TDA2 Tool/software: TI C/C++ Compiler Good night! I would like to tell you where I can buy the TDA3x or TDA2x because on the site Texas instruments the sale is not available. Thank you, Hugo

Hi Hugo, please check: www.ti.com/.../samplebuy www.ti.com/.../samplebuy Regards, Yordan

HI, Yordan! I thank you for your help and I had trouble to follow It looks like we’ve encountered some resistance (Sorry, the page you’re looking for can’t be found.) Regards, Hugo.

Ticket Name: TDA2: run the user cnn model with TIDL on tda2x

Part Number: TDA2 hi, dear Now although I bought serveral tda2x boards, I have only got part service from the TI tech support in Shanghai of China. I could not get the source code of TIDL. So if I want to run my improved cnn model , I can only run it on the tda2x board not on PC simulator. I have imported the cnn model to the bin format which is suitable for TIDL. Yet the input data need to be resize to 368 X 368，and I should resize it by myself( It has to be the TI method to resize). Even worse, the configuration file (only seg , ssd detection included)on the tda2x board looks like that below: TIDL Configuration parameters ----------------------------- ################################################################################ IMP: Make sure the size of the file names (excluding extension) is not more than 8 characters. ################################################################################ inputWidth=1024 inputHeight=512 inputFile=IN.RGB outputFile=OUT.BIN netFileName=NET.BIN paramFileName=PRM.BIN My cnn net is not for detection or classifcation, but pose recognition. I do not know if I can use this demo cfg file to run my cnn model successfully on the tda2x. If not , could you please be kind enough to offer me new cfg file or make some change for me to run? I mean could you offer me a new in_Data_OD and in_header_OD sized 368 x 368 for my pose recognitation? I will replace the bin to run the video demo. tks, looking forward to your reply.

Hi, Did you check below thread where we explained how to run TIDL OD use cases? e2e.ti.com/.../689617 Thanks, Praveen

MY TIDL OD use cases ran sucessfully. Yet the new usr model not validated which is for pose recognition require the input image size 368 X368， we couldnot get the input data in the vision sdk with this size. And could you think of a method to change the OD demo cfg file to run my pose model recognition demo?

Please refer below thread for generating indata and inHeader e2e.ti.com/.../687481 Thanks, Praveen

In fact, in my case only, if I use this case called "chanis_tidl – File IO based use case to validate user model ", it is better to bring up? If so, could you offer me some tips for changing this demo to my own pose mode recog demo?This case is similar to my pose reg demo, and I want to test the performance of the mode only, not for accuracy which maybe need only one image like in.RGB, right? And how to translate my jpg image to the in.RGB format? Good luck, tks!

Beside these facts above, the output of my pose model is not the limited classification but arbitrarily float32 value. So from the link that you offer me before, I do not know if it will work successfully by just commenting the classfications.(this Line : tempoutPutList->objDesc[tempoutPutList->numObjects].objType = (label - 1); need to be changed to " (label - 1)%3 ") Any other change should be made?

Hi, We answered this in below thread, e2e.ti.com/.../723674 No need to create multiple threads for the same topic, we can discuss and follow up in the same thread. Thanks, Praveen

What about the semseg usecase of TIDL？ How to generate the indata and inHeader for semseg case？

Hi, Please refer to below thread for generating indata and inHeader for TIDL use case, e2e.ti.com/.../660676 Thanks, Praveen

Ticket Name: Linux/TDA2: The diagnostic function in TDAx

Part Number: TDA2 Tool/software: Linux We know that the EMIF1 channel can support the 2-bit ECC DDR diagnostic function. We are worried that if the DDR has a 2-bit data error, it may cause the system to run out of track. How can SOC record this information? Our hardware design supports another MCU to communicate with the SOC through the serial port. But if the program runs away, communication may fail. For other types of diagnosis, we are worried about the same result. E.g：Dual error detection (SECDED) error correcting code (ECC) diagnostic of the on-chip RAM E.g：The L3 interconnect timeout .

Hi, One suggestion is to isolate the code communicating to the MCU to reside in on-chip memory. Thus, if the primary code communicating with DDR has a 2-bit error and impacts the program operation, the code running from on-chip memory would be able to detect and report to the MCU. Best regards, Kevin

Ticket Name: TDA4VM: TDA4 processor SDK download URL

Part Number: TDA4VM Dear Sir, I am a software manager working in Longhorn Automotive Electronics Co., Ltd. at Shenzhen of China. Longhorn is Tier1 and also a TI AAA customer. We have completed 360 surround view monitor using TDA2S, but some scenarios are not handled well ,for example auto parking. Then we want to using TDA4 to doing auto parking. I find that TI has released TDA4 SDK at http://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/latest/index_FDS.html

Part Number: TDA4VM Dear Sir, TI has released TDA4 processor SDK, but I can not download it, please tell me how can I get the form to fill for downloading? Your reply will be greatly appreciated。 Best Regards, Bob Deng At software-dl.ti.com/.../index_FDS.html .

Hi, please check here: Regards, Yordan

Ticket Name: Linux/TDA2: Import Vision SDK to Visual Studio

Part Number: TDA2 Tool/software: Linux Hi, Is there any way import vision sdk to Visual Studio for linux app development use interprocess communication intarfaces?

Hi, Nobody has tried or tested such feature. And TI also does not support importing VSDK to Visual Studio. Regards, Anuj

Ticket Name: RTOS/TDA2: Can we use our model by GoogleNet + Yolo V3?

Part Number: TDA2 Tool/software: TI-RTOS Our model target is doing GoogleNet + Yolo V3, so we need TI to help us clarify the following questions. Current SDK v3.03 is using SSD model, is there any possible to replace SSD in TIDL module, for example, Yolo V3 (You Only Look Once: Unified, Real-Time Object Detection, CVPR 2016) If yes, we can replace SSD by our own model Fig.1 is TI TDA2 architecture what we supposed and the yellow block is our customized model. Q1: if TI architecture is not like above diagram, can you provide your architecture for our reference? Fig.1 Q2: How can we implement our model into TI TDA2? For TIDL input and output, can you point me two issues solution. l We need to know Input BGR input file format and seg_out.bin output file format l We need API function such as CUDA level in TI platform for hardware accelerate. 2.If not, we can NOT replace SSD by our own model and both issues of Q2 cannot be resolved Q3: when does TI platform will release Yolo algorithm? If not, how can we build our Yolo library module in TI platform? Q4: how can we apply other (Squeezent、Googlenet、Mobilent) in TI platform, any other example. If possible, can we apply yolo+(google net or VGG) in TI platform?

Refer "3.7 Input and Output Data Formats" in user guide for input and output format. Input in our use case is BGR planar. it could different in another use case. Refer Below for seg_out.bin output file format e2e.ti.com/.../685817 Regarding Object detection, We support only caffe-based SSD for complete object detection (Image to Bound boxes). Yolo is not supported and not planned. You can train Yolo based object detection network (Yolo+Squeezenet or googlenet or mobile net) using caffe / caffe-jacinto and run all the layers on TIDL except the last layer which can be executed later on DSP/EVE as a C function (Detections to Bounding boxes). Refer data sheet for supported layers. We don't provide CUDA like interface for CNN acceleration. With TIDL you run a CNN network (Series of layers, could be a portion a big CNN network) on TI device. Thanks and Regards, Kumar.D

Ticket Name: Linux/TDA2: about nullSrcLink_tsk.c

Part Number: TDA2 Tool/software: Linux I add some print it in the file of vision_sdk\links_fw\src\rtos\links_common\nullSrc\nullSrcLink_tsk.c ,then i run "make -s -j depend" and "make -s -j", and i run the apps.out on the HW environment ，But The print information I added was not printed out. It seems that the file nullSrcLink_tsk.c I changed is not compiled. it only print: [HOST] [IPU2 ] 43.077167 s: Assertion @ Line: 1500 in nullSrcLink_tsk.c: pObj->fpDataStream[chId] != SYSTEM_LINK_STATUS_EFAIL : failed !!! How can I print out the printed information on the file nullSrcLink_tsk.c?

Hi Xie, You should use Vps_printf for print logs. Regards, Rishabh

Hi Rishabh, i used Vps_printf , but it seems the change of nullSrcLink_tsk.c has no effect, It seems to be compiled and not updated. I want to know my chain (NullSource (IPU1_0) -> Decode -> Alg_FrameCopy (A15) -> VPE -> Display ) Will execute this nullSrcLink_tsk.c file? or it execute other nullSrcLink_tsk.c？ Regards Xie Baojian

Hi, Can you share the updated nullSrcLink_tsk.c. Regards, Rishabh

Hi, My change part as follows: Vps_printf("##############\n"); Vps_printf("xbj filename = %s \n", (Char *)pPrm->channelParams[chId].nameDataFile); strncpy((Char *)pPrm->channelParams[chId].nameDataFile, "./1920_1080/1280_720_1.h264", 260); UTILS_assert( (pPrm->channelParams[chId].nameDataFile[0] != (char)'\0')); pObj->fpDataStream[chId] = File_open((Char *)pPrm->channelParams[chId].nameDataFile, "r"); UTILS_assert(pObj->fpDataStream[chId] != SYSTEM_LINK_STATUS_EFAIL); the I added the first three lines In order to locate a mistake. Regards, Xie Baojian

Hi Xie, Do you have the above mentioned file ./1920_1080/1280_720_1.h264. Can you give absolute path and try. Regards, Rishabh

Hi， OK,i will try the absolute path, but It's strange that printing does not execute. thanks. Regards, Xie Baojian

Hi Xie, Agreed it is strange. Let's first try to resolve the assert issue. Regards, Rishabh

Hi Regards, the assert issue Says file open failed, Because there is no print information to locate，I don't know why the file opened failed. Regards, Xie Baojian

Hi Xie, Did you try the absolute path? Regards, Rishabh

Hi Xie , I see in the query Tool/software: Linux But you are using nullSrc in bios , Please note if you are using Linux as hlos please change the usecase and add nullSrc on A15. Please refer the following thread If you are using bios on A15, Please verify if the files are present in the drive . Regards Chetan.M

Hi Chetan.M, I am using tda2xx_evm_linux_all mode ，so i cannot use NullSource (IPU2)? Can only use NullSource (A15)？ Is that right? Regards, Xie Baojian

Yes , Fatfs and network will be in control of hlos core. Please close the thread Regards Chetan.M

Ticket Name: TDA2: EVE/VCOP s_scatter/p_scatter store

Part Number: TDA2 Hi, Could you help with s_scatter(<vector>) store option. I read that load/store option take 2 ticks. how many ticks does s_scatter store take? And how does it depend from <vector>? Also i try use p_scatter instead s_scatter, and get vcop error. Which is rules used for p_scatter? Thank you

Hi Danil, Both s_scatter and p_scatter are used to store each entry within a vector at an offset which is given by another vector. For example Lets say we have a vector (VOffset) with following entry VOffset = ( k1,k2....,k8) lets say the vector which we want to store has some entries as Vin = ( a, b,c,d,e,f,g,h) Lets say we perform the write as follows dst[addr].s_scatter(VOffset) = Vin The above store would write the value "a" at an offset of k1 bytes , "b" at an offset of k2 bytes, "c" at an offset of k3 bytes and so on, from the base pointer dst. s_scatter operation will take 8 cycles for this store but it doesnt have any restriction on k1,k2.. k8. On the other hand p_scatter would do the same in single cycle but it has a restriction the the offsets k1,k2... k8 should be chosen in such a way that all the 8 entries of the vector falls in a different memory bank Regards, Anshu

Thank you for answer, Could you answer what is the size of bank for IbufL, IbufH and Wbuf?

Each of these buffers have 8 banks with 4 bytes each. Regards, Anshu

Did you mean 4 kbytes?

I thought you asked about the size of each bank in memory which is 4 bytes per bank and there are total 8 such banks. But now it looks like you are asking about size of EVE internal buffers which are as follows: IBUFA = 32KB --> THis is further split into IBUFLA 16KB and IBUFHA 16KB IBUFB = 32KB --> THis is further split into IBUFLB 16KB and IBUFHB 16KB WBUF = 32 KB Regards, Anshu

Ticket Name: TDA2E: linux vision SDK 3.02 dra72x scaling_governor not found

Part Number: TDA2E Hi I try to run omapconf show opp,but it show scaling_governor not found. If I want to use this to chane frequency,what I need to set up? thanks Yumei

Hi Yumei, can you check in this doc how to enable the scaling governor: Regards, Yordan

Hi Yordan I had been to use menuconfig to change governor. When I use menuconfig ,then use make linux_install and copy uImage to SD card. But omapconf show opp still show no find scaling governor. thanks Yumei

HI Can you confirm if the kernel configuration used is similar to that of the Linux SDK - would help if you can mention the SDK/kernel version. You can check the kernel configuration by typing # zcat /proc/config.gz

Hi Please confirm if your issue is still open If it is still unresolved, please check the kernel configuration and report back your findings

Hi Sriam I am not sure path to run zcat /proc/config.gz. Do it run in the ti_components/os_tools/kernel? Thanks Yumei

Hi You need to run the command on the target (EVM) once the kernel boots to the shell prompt

Hi the verison is 4.4.84-00018-gd326d64-dirty I use tda2eg sdk302. thanks Yumei

HI Were you able to verify the kernel configuration by running the "# zcat /proc/config.gz" command on the target side

Hi Sriram I cannot to verify the kernel configuration by running the zcat /proc/config.gz. I even cannot find config.gz. file. thanks Yumei.

Hi Config.gz file is exported at runtime if the corresponding kernel configuration option to include it the kernel image is enabled. It is enabled by default in the TI SDK - have you modified the kernel configuration at your end. If so can you verify the changes carried out - including selection of options for CPUFREQ, governors

Ticket Name: TDA2: Use case generate tool

Part Number: TDA2 Hi, I use VSDK v3.3 + TDA2x. I want to test use case generate tool but I find vsdk.exe can't run on win7 64 bits version. I can find vsdk.exe for 64 bits version on SDK v3.2(C:\PROCESSOR_SDK_VISION_03_02_00_00\vision_sdk\build\rtos\scripts\vsdk_win32.exe(1,954 KB, 2017/12/22 19:04)) But SDK v3.3 total have 3 files they both can't run on Win7 64 bits OS. 1st : PROCESSOR_SDK_VISION_03_02_00_00\vision_sdk\build\rtos\scripts\vsdk_win32.exe(1,954 KB, 2017/12/22 19:04) 2nd : PROCESSOR_SDK_VISION_03_03_00_00\vision_sdk\apps\tools\vision_sdk_usecase_gen\bin\vsdk_win32.exe(895 KB, 2018/4/6 19:29) 3rd : PROCESSOR_SDK_VISION_03_03_00_00\vision_sdk\apps\src\rtos\usecases\vip_single_cam_display_metadata\vsdk_win32.exe(1,976 KB, 2018/4/6 19:29) Could you please check it? Thanks.

Hi, You should use the tool present in PROCESSOR_SDK_VISION_03_03_00_00\vision_sdk\apps\tools\vision_sdk_usecase_gen\ folder. As the source of the tool is present here you should rebuild the tool for 64 bit machine. Regards, Rishabh

Ticket Name: TDA2EVM5777: TDA2xx Vision SDK Build Error: CODEGEN_PATH_A15 does not exist!

Part Number: TDA2EVM5777 Hello, I am trying to install and start compiling using the PROCESSOR_SDK_VERSION_03_04_00_00 Linux. When following the Linux User Guide, I was able to compile just fine the first time (running make linux, make linux_install, make -s -j depends, make -s -j all worked just fine initially). After going away for a while and coming back to it, I get a compile error saying: /home/user01/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/apps/configs/autorules_footer_cfg.mk:69: *** CODEGEN_PATH_A15 does not exist! (/home/user01/PROCESSOR_SDK_VISION_03_04_00_00/ti_components/cg_tools/linux/gcc-arm-none-eabi-4_9-2015q3). Stop. I have another installation of PROCECSSOR_SDK_VISION_03_01_00_00 and I can compile just fine without gcc-arm-none-eabi-4_9-2015q3 in the directory /home/user01/PROCESSOR_SDK_VISION_03_01_00_00/ti_components/cg_tools/linux/. For reference, here is what the linux user guide says in section 2.2.1 A15 Compiler Linker for PROCESSOR_SDK_VISION_03_04_00_00 The Linux installer for the GCC Linaro tools should be downloaded from below link https://releases.linaro.org/components/toolchain/binaries/5.3-2016.02/arm-linux-gnueabihf/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf.tar.xz The tools need to be installed under $INSTALL_DIR/ti_components/os_tools/linux/linaro/ IMPORTANT NOTE: A15 Compiler and linker MUST be installed before initiating the build else compilation will fail. Also make sure the compiler is installed at the exact path mentioned above after installation of vision sdk. Use following steps to install the toolchain $> cd $INSTALL_DIR/ti_components/os_tools/linux/linaro $> tar –xvf gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf.tar.xz I noticed that there was no mention of the directory $INSTALL_DIR/ti_components/cg_tools/linux or the file gcc-arm-none-eabi-4_9-2015q3 anywhere in the user guide. What steps must I take to get passed this issue? Thank you, -iFer

Hello, I was successfully able to compile. The reason I had the error before was because on a new installation of PROCESSOR_SDK_VISION_03_04_00_00 the Rules.make file under $INSTALL_DIR/vision_sdk/build/ directory was defaulted to MAKECONFIG?=tda2xx_evm_bios_all. I needed it to be MAKECONFIG?=tda2xx_evm_linux_all otherwise I would run into that error. Thank you, -iFer

Hi iFer, thanks for updating the thread. Regards, Yordan

Ticket Name: DRA726: Virtual DRM

Part Number: DRA726 Other Parts Discussed in Thread: TDA2, I am working on getting our cameras supported in IPU1 and have a question on Virtual DRM I have been reading "Virtual DRM : An User Guide for Developing Usecases". It seems straightforward but doesn't address my use case. We have two possible LCD displays, one 7 inch display 800x1280 and one 12 inch display 1920x720 The board is the same except for some jumpers that choose the proper LVDS serial format. No way to know from u-boot or Linux which jumpers are populated. How would I handle that in the M4 and on Linux if I want only one u-boot and one linux kernel? I would also be nice if the 7 inch display was seen as 1280x800 so the Linux software wouldn't have to flip the LCD 90 degrees Michel Catudal ACTIA Corp

Hi Michael, I am not sure of any way to enable without having different dtb files but again how to choose dynamically change the dtb file based on jumper setting. Many other customers are also using vertical display like 720x1920. TI has suggested a edma based frame-copy algorithm running on IPU to rotate the image. Thanks RamPrasad

Hi Michael, forgot to add one more information. There is TILER2D memory available in the DRA7/TDA2 Soc which can be used for rotation, mirror etc but TILER2D is not used in visionSDK software. Thanks RamPrasad

Hi Michel, Regarding "The board is the same except for some jumpers that choose the proper LVDS serial format. No way to know from u-boot or Linux which jumpers are populated.". Have you considered connecting a GPIO pin on the DRA726 device to the same jumpers, such that u-boot or Linux kernel can determine the proper boot flow? Regarding "I would also be nice if the 7 inch display was seen as 1280x800 so the Linux software wouldn't have to flip the LCD 90 degrees", What content is going to be displayed on the 800x1280 display? Thanks, kb

Ticket Name: TDA2SG: TDA2 power supply

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Hi， We are not using the USB function of TDA2 What will happen if we turn off this power supply of TDA2 after the SOC completes the power-on sequence? VDDA33V_USB1 & VDDA33V_USB2

Hello, You should not turn off that power supply. Turning it off can damage the SoC. Regards, Kyle

Hi，Kyle Another question: The PMIC power to the MPU through SMPS1 and SMPS2. Under normal circumstances, the port SMPS should continue to output 2MHz switching waveform, but sometimes we find that the switching frequency is stagnant, as shown in the figure ： We are worried that this method will affect the RE, so I would like to consult which PMIC registers can be improved or optimized？

Hello, Where are you probing for that waveform ... can you show both SMPS1 and SMPS2 waveforms separately? Thanks, Kyle

Hi，Kyle The test points and oscilloscope waveform are as follows： Thanks,

Hello, That's expected operation. Here is a quote from the PMIC Datasheet: In dual-phase configuration the two interleaved synchronous buck regulator phases with built-in current sharing operate in opposite phase. In triple-phase configuration the three interleaved synchronous buck regulator phases with built-in current sharing operate 120° out of phase. For light loads, the converter automatically changes to 1-phase operation. Regards, Kyle

Hi，Kyle What kind of damage may occur to SOC? Is it possible that the SOC power consumption is abnormal? Which document describes this content? thanks

Hello, Can you summarize the background for your question? Are you wanting to intentionally turning off that supply and why? Or is it some type of system fault that leads to that supply turning off? Thanks, Kyle

Ticket Name: Linux/TDA2: how to send data from a15 to c66 DSP

Part Number: TDA2 Tool/software: Linux now i am VISION_03_04_00_00 i read file load cnn_model in a15 , it will use by C66 , so have can i send the model_buffer to C66 dsp ？ Now I'm passing the model over the image data through IPCOut_A15_0_DSP1_0Prm, and then taking it out of the image data, and I think that's a temporary solution. can you tell me how to do this and Describe the steps？

Hello If you need to pass this buffer only one time, then use of IPCOut_A15_0_DSP1_0 is not really required. You can do a file read and load this data to a buffer/memory on A15 from usecase, Then pass the physical pointer of this buffer to DSP as an Alg link (on DSP) create time parameter regards, Shiju

Ticket Name: TDA2: TIDL: NET_OD.bin and PRM_OD.bin are missing in SDK v3.4

Part Number: TDA2 Dear support staff, NET_OD.bin and PRM_OD.bin are required to run TIDL OD demo. They could be found in SDK v3.3 but there are missing in SDK v3.4. Could you help check? Below lists the files under \PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\apps\tools\TIDL_files IN.RGB NET.BIN NET_SEMSEG.BIN PRM.BIN PRM_SEMSEG.BIN Ref_out.bin TIDLCFG.TXT tidl_net_jdetNet_ssd.bin tidl_param_jdetNet_ssd.bin TIDL_SSD_CFG.TXT Below lists the files under \PROCESSOR_SDK_VISION_03_03_00_00\vision_sdk\apps\tools\TIDL_files IN.RGB NET.BIN NET_OD.BIN NET_SEMSEG.BIN PRM.BIN PRM_OD.BIN PRM_SEMSEG.BIN Ref_out.bin TIDLCFG.TXT

Hi Luke, TIDL OD use-case uses TIDL_SSD_CFG.TXT file to read & parse information of required input files You can specify the netFileName & paramFileName depending on which one you want to use With VSDK 3.4 release below files are used netFileName - tidl_net_jdetNet_ssd.bin paramFileName - tidl_param_jdetNet_ssd.bin Regards Surya

Surya, Thanks for the prompt reply. I'm not aware of the change in SDK v3.4, sorry.

Ticket Name: TDA4VM: How to modify TDA4VM's csi clock in SDK07_02_00_06 ?

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi, I have a deserializer MAX9286, it works well when four cameras opened. But when just two or one camera opened, then TDA4VM cannot receive csi signal. This situation occured in TDA2 also. And it can through modify csi clock to fix. In TDA4VM I try to modify uint32_t csi_ddr_clock to lower value, but it not works. So How to modify TDA4VM's csi clock in SDK07_02_00_06 ? Regards

Hi, CSI clock in TDA4VM is controlled through lane speed parameter. This parameter can be configured through 'laneBandSpeed' parameter available in Capture Node interface 'kernels_j7/include/TI/j7_capture.h'. Please refer 'j7_capture.h' for more details. Here is an example to change lane speed/CSI clock: Consider single cam app, if you want to change lane speed to 800 Mbps in this app, then just add following line before creating capture node (done @ line no. 523):     local_capture_config.instCfg[CAPT_INST_ID].laneBandSpeed = TIVX_CAPTURE_LANE_BAND_SPEED_720_TO_800_MBPS;
 Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Ticket Name: DRA746: Boundary Scan test

Part Number: DRA746 Other Parts Discussed in Thread: TDA2 Dear Sir, We're trying to run the boundary scan test on the board that is using DRA746 and DDR3 (MT41K256M16). We're using the bsdl file "vayu.23x23.bsdl". The ID of the DRA746 can be recognized properly but when testing the interconnect test and the memory test by IEEE1149.1. All the nets of the DDR3 interface has been sensed as "0". Are there any setting that will impact this? Please help to reply. Thanks, Pricilla

Pricilla, I am not aware of existing occurrences of DDR1 nets resting at 0 during bscan testing. Are DDR1 nets the only ones whose values were not sensed correctly? Can you help provide a sequence of how your tests were executed, including all the test instructions used? Moreover, please double check in the BSDL file header that the chip revision matches the chip you are using. Best Regards, Shiou Mei

Hi Pricilla, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Dear Shiou Mei, The bsdl file that we use is TDA2x_bsdl_23mm.bsdl and the IC part name is TDA2SGBRQABCRQ1 PBGA2.0. Is it the correct one? The DDR3 and Nor Flash still can't test properly. We aware that it is mentioned that "Device security features\JTAG® lock" in the TDA2 datasheet, but there is no detailed info. for it. Is it possible that this feature has been enabled? or any suggestions for boundary scan test ? Thanks, Pricilla ---------------------------------------------------------------------- -- TDA2x Boundary Scan ---------------------------------------------------------------------- -- Supported Devices: TDA2x Revision 1.0 -- -- Derived from parent device BSDL file -- -- Does NOT apply to TDA2Ex -- ---------------------------------------------------------------------- -- Created by : Texas Instruments Incorporated -- -- BSDL Revision : 1.1 -- -- -- -- BSDL Status : Preliminary -- -- Package : 23x23 -- -- Date Created : 03 September 2013 -- -- -- ----------------------------------------------------------------------

Pricilla, I tested BSDL with a TDA2x PG2.0 reference unit on my bench and was not able to reproduce the issue. Can you help provide more information on your fail mode: Is result reproducible on multiple units? What are all the nets with improper values (i.e. address, data, etc)? Can you help provide a sequence of how your tests were executed, including all the test instructions used? Thanks & Regards, Shiou Mei (pending Manoj feedback)

Ticket Name: PROCESSOR-SDK-AM62A: How to create a graphic layer for display ?

Part Number: PROCESSOR-SDK-AM62A Other Parts Discussed in Thread: TDA2 Hello !! We want to create a graphic layer, like OSD, to overlay the display, video layer, with transparency attribute. It looks like the Display_GrpxLink on the TDA2 platform. https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-edgeai/AM62AX/latest/exports/docs/common/configuration_file.html Based on the above URL, I only found the display sink(kmssink) node. Do you know how to create the gst node or to construct the overlay graphic layer ? Thank you very much ! Regards, Eten

Hello Eten, Could you please share the example that was used on the TDA2 platform? On AM62A, we do not have a graphics layer as an input to the DSS. We have two input pipelines and DSS has the following properties that it can support with two pipelines: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/09_00_00_03/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Display/DSS7.html#tidss-properties Regards, Krunal

Hi Krunal, In TDA4 SDK, the graphic initialization source code is in located in "vision_apps/utils/grpx/src/app_grpx.c". How can I perform the same function in AM62A by gstreamer? Regards, Eten

Hi Eten, I am not sure I understand the request. There is no graphics core on AM62A so the above feature would not port. Regards, Krunal

Hi Krunal, Based on your mentioned URL, https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/09_00_00_03/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Display/DSS7.html#tidss-properties I guess that the graphic layer should be the "plane" object (connector ID 31 & 40). The following image is the HDMI output screen after executing"modetest -M tidss -P 40@37:1920x1080 -w 40:zpos:1 -w 40:alpha:32768". When using plane#31, the color will be filled on screen without alpha blending. We want to draw something on the plane#40 by ARGB888 and let it display asynchronously to overlap the screen (CRTCs). So how to set the system and to construct the corresponding gstream pipeline string. Regards, Eten

Hi Eten, You can do something like this: gst-launch-1.0 videotestsrc ! video/x-raw,width=1920,height=1080 ! kmssink driver-name=tidss plane-properties="prop,zpos=1" Regards, Krunal

Hi Krunal, Do I need to assign plane number ? How to set the global alpha blending value? Thank you !! Regards, Eten

Hi Eten, You need to do gst-inspect-1.0 kmssink or waylandsink to see if those properties are exposed. Regards, Krunal

Hi Krunal, Thanks for your support !! Regards, Eten

Ticket Name: Linux/TDA2: I2C configuration for processor as SLAVE

Part Number: TDA2 Tool/software: Linux HI, How can we configure the Processor as I2C slave in TDA2x? I have I2C4 to be configured as I2Cslave . Is it possible to configure CONFIG_I2C_SLAVE?

Hi Sreerag, current version of I2C-omap driver do not support slave mode. You can check those posts for detailed description: e2e.ti.com/.../2151948 e2e.ti.com/.../2156908 Regards, Yordan

Ticket Name: TDA2: Cannot save uBoot env

Other Parts Discussed in Thread: TDA2, SYSBIOS Hi all, I want to boot TDA2 EVM with NFS. I follow the document, VisionSDK_LinuxUserGuide.pdf, and do followinf steps: setenv bootargs 'console=ttyO0,115200n8 vram=16M root=/dev/nfs rw nfsroot=172.24.170.60:/datalocal/user/abc/vision_sdk/linux/targetfs rootwait ip=dhcp mem=1024M' setenv fdt_high 0x84000000 setenv bootcmd 'load mmc 0 0x825f0000 dra7-evm-infoadas.dtb;load mmc 0 0x80300000 zImage;bootz 0x80300000 - 0x825f0000' save But it shows error message: Saving Environment to MMC... MMC init failed zImage, dra7-evm-infoadas.dtb, MLO and u-boot.img are already copied to SD card. Is there anything I missed? My environment is TDA2, Linux + sysbios, Vision SDK v2.10. Thanks. Kevin Tsai

Hi, Kevin, VSDK expert is notified for your questions. Regards, Mariya

hi, I guess you have to set your NFS server address correctly below one is for TI NFS server nfsroot=172.24.170.60:/datalocal/user/abc/vision_sdk/linux/targetfs pick the file uenv_nfs.txt, modify with your NFS server address, rename to uenv.txt and copy to SD card. regards, Shiju

Hi Shiju, Thanks for your reply. I did change NFS address and path when I typed the command in console. But I forgot to change it when I typed this post. I am sorry for that. The error message mentions "MMC init failed". So I think something like pinmux should be modified. But the document does not describe about this. By the way, your sugestion is modifying uenv.txt directly instead of typing command at uboot, right? I will try it. Thanks. Kevin Tsai

Ticket Name: RTOS/TDA2P-ACD: Video encode by IVA

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2, AM5728 Tool/software: TI-RTOS hi, AM5728 and TDA2 have a IVA accelerator to encode video, in TDA2 rtos sdk i finde out rtos based program for video encoding is it possible to use that for am5728 ?? because for am5728 TI support IVA just for Linux ?!

Hello, This thread is duplicated with this one: https://e2e.ti.com/support/processors/f/791/t/809598 Please do not open multiple threads for the same question. I am closing this one. Best Regards, Margarita

Ticket Name: RTOS/TDA2PXEVM: 2MP SV DEMO UG and HW information for TDA2PxEVM

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2, TIDA-01130 Tool/software: TI-RTOS Dear Champs, My customer want to evaluate 2MP SV DEMO using TDA2Px EVM and I found there is new update for this in VisionSDK3.02, but I could not find any UserGuide and details for this. I only find below in the Release notes and 'ProcessorSDK_Vision_IssSensor_TestMatrix.xls', but could not find any other details. Could you please let me know where I can find details for 2MP SV DEMO? And also could you please let me know HW configuration for 2MP SV DEMO? It seemed it was implemented on Fusion board. Is this right? Is it possible to run it on Vision board also? Is additional deserializer needed? Thanks and Best Regards, SI.

Hi SI, This demo is actually supported on Linux build and uses ISS drivers. It captures RAW images from the OV2775 or IMX390 sensors, uses ISS to convert RAW data into YUV and then it uses SGX to stitch the images. It uses fusion board to capture four camera input over CSI2 interface. There is a TIDA1130 module, which supports OV2775 sensor and D3 module, supporting IMX390 sensor. Let me know if you want more information. Rgds, Brijesh

Hi, Sung-IL, The query has been forwarded to the VSDK lead. Regards, Mariya

Hi Brijesh, Is it 3D SV DEMO? To run this DEMO, should they use Fusion application Daughter Board? Is it possible to use Vision application Daughter Board to run this DEMO? If not, is there any plan to release 2MP SV DEMO for Vision applicaiton Daughter Board in future releases? Is there any plan to release 2MP 2D SV DEMO running on TI-RTOS? When we will release detailed document for this 2MP DEMO? When customer buy TDA2+ EVM, can they set-up 2MP DEMO by themselves using VisionSDKv3.02? Thanks and Best Regards, SI.

Hi SI, yes, it is 3D SV demo. No This demo is not supported on Vision board, it is supported only on Fusion board and as of now, AFAIK, there is no plan to support 2MP SRV demo using vision daughter card. Vision card outputs only on parallel interface and one of the advantage of J6+ is that it support capture over CSI2 serial interface. We are using CSI interface to get 2MP 4Ch data. As such, most of the documentation should be available, Let me check what is missing in documents. yes, customer can setup 2mp demo using TDA2x+ EVM, fusion board and TIDA1130/IMX390 sensors. They need to use VSDK 3.02 release. Regards, Brijesh

Hi Brijesh, I checked it again, but I could not find any related document. It seemed the 'VisionSDK_UserGuide_2MP_3D_SurroundView.pdf' is not updated yet. the title of 'VisionSDK_UserGuide_2MP_3D_SurroundView' is a 'Vision SDK TDA2xx 2MP 3D Surround View User Guide', not TDA2Px. Thanks and Best Regards, SI.

SI VisionSDK_UserGuide_2MP_3D_SurroundView.pdf is currently for TDApx based 2MP SRV, No section added for TDA2Px 2MP SRV, where ISS is getting used. Sorry, we do not have any seperate user guide for TDA2Px 2MP 3D SRV, will add one section the same for next release. regards, Shiju

Hi Shiju, Could you please release instruction how customer can try it? my customer is willing to buy TDA2P EVM to run this 2D SV DEMO. Is it OK to buy Fusion Kit and TIDA-01130 OV2775 camera module only? or other kit will be required? Could you please explain about HW setup at least? Thanks and Best Regards, SI.

SI You need below HW to set-up 2MP SRV demo on TDA2Px 1. TDA2Px EVM - 1 2. Fusion Card/EVM - 1 3. TIDA OV2775 cameras - 4 (with Fakra cables) separate power supply is required for Fusion Card Regards, Shiju

SI please make sure you order TIDA OV2775 cameras with Fisheye lens. Sometimes, spectrum digital ship only sensor without lens module regards, Shiju

Ticket Name: TDA2: dlib on TI TDA2X

Part Number: TDA2 Dear all, Is there any example that we can cross-compile dlib on ARM and used on TDA2X? Thanks and best regards He Wei

Hi Wei, What do you mean by dlib ? Are you referring to TI deep learning library? Thanks, Praveen

Dear Praveen, I am referring to open source lib: http://dlib.net/compile.html Thanks and best regards He Wei

Hi He Wei, Sorry, we don't have any example or reference. Thanks, Praveen

Ticket Name: TDA2EVM5777: Vision SDK installation GUI

Part Number: TDA2EVM5777 Hello, I am setting up VisionSDK 3.06 on a new PC with Ubuntu 16.04. I am not able to see the installation GUI when I run the installation executable. Instead, the installation starts in the Ubuntu Terminal. Am I missing some library which enables the installation GUI? Thank you.

Hi, We tested on ubuntu 14.04 & we din't tried on 16.04. please try to run from the command line Thanks Gaviraju

Ticket Name: Linux/TDA2: VSDK/OpenCV on RTOS: Running error when imported the pre-build libopencv_objdetect.a and libopencv_highgui.a

Part Number: TDA2 Tool/software: Linux Dear TI: Building environment: VSDK3.4 and RTOS. add these 2 libs in makefile: _OPENCVAPP_LIBS_a15_0 +=$(OpenCV_PATH)/libopencv_objdetect.a _OPENCVAPP_LIBS_a15_0 +=$(OpenCV_PATH)/libopencv_highgui.a Modify the OpenCV use case and build succeeded but encounter error when runing OpenCV: [HOST ] 39.341731 s: IPC_IN_0 : Create in progress !!! [HOST ] 39.342036 s: IPC_IN_0 : Create Done !!! [HOST ] 39.342127 s: ALGORITHM: Create in progress (algId = 5) !!! [HOST ] 39.346977 s: ALGORITHM: Create Done (algId = 5) !!! [HOST ] 39.347068 s: IPC_OUT_0 : Create in progress !!! [HOST ] 39.347068 s: hewei: prevLinkQueId=0, numQue=1 [HOST ] 39.347099 s: IPC_OUT_0 : Create Done !!! [HOST ] 40.864667 s: SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1023 [HOST ] 40.864667 s: SYSTEM: Heap = LOCAL_DDR @ 0x00000000, Total size = 100663296 B (98304 KB), Free size = 100078392 B (97732 KB) [HOST ] 41.075672 s: OpenCV Error: Unspecified error (The storage is not opened) in icvGets, file /datalocal/ti_components/open_compute/opencv_src/tiopencv/modules/core/src/persistence.cpp, line 299 [HOST ] 41.075825 s: Unhandled Exception: [HOST ] 41.075855 s: Exception occurred in ThreadType_Task [HOST ] 41.075855 s: Exception occured in A15 with exception type 18 [HOST ] 41.075855 s: handle: 0x89549ac8. [HOST ] 41.075886 s: stack base: 0x89554df0. [HOST ] 41.075886 s: stack size: 0x4000. [HOST ] 41.075886 s: R0 = 0x72830b0b R8 = 0x89363734 [HOST ] 41.075916 s: R1 = 0x0000093b R9 = 0x00000000 [HOST ] 41.075916 s: R2 = 0x88ec97e6 R10 = 0x89559020 [HOST ] 41.075916 s: R3 = 0x00000000 R11 = 0x89557994 [HOST ] 41.075947 s: R4 = 0x89559ca0 R12 = 0x89547744 [HOST ] 41.075947 s: R5 = 0x893b39f8 SP(R13) = 0x88e13294 [HOST ] 41.075947 s: R6 = 0x89547710 LR(R14) = 0x8f4e2314 [HOST ] 41.075947 s: R7 = 0x8954790c PC(R15) = 0x88e13294 [HOST ] 41.075977 s: PSR = 0x00000000 [HOST ] 41.075977 s: DFSR = 0x00000206 [HOST ] 41.075977 s: IFSR = 0x00000000 [HOST ] 41.075977 s: DFAR = 0x72830b0b [HOST ] 41.076008 s: IFAR = 0x00000000 [HOST ] 41.076008 s: Terminating Execution... [HOST ] 41.076008 s: [HOST ] 41.076038 s: ### XDC ASSERT - ERROR CALLBACK START ### [HOST ] 41.076038 s: [HOST ] 41.076069 s: E_dataAbort: pc = 0x88e13294, lr = 0x8f4e2314. [HOST ] 41.076069 s: [HOST ] 41.076069 s: ### XDC ASSERT - ERROR CALLBACK END ### [HOST ] 41.076069 s: [DSP1 ] 40.864972 s: SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1023 [DSP1 ] 40.865003 s: SYSTEM: Heap = LOCAL_L2 @ 0x876ac3a4, Total size = 227264 B (221 KB), Free size = 227264 B (221 KB) [DSP1 ] 40.865064 s: SYSTEM: Heap = LOCAL_DDR @ 0x00000000, Total size = 524288 B (512 KB), Free size = 518264 B (506 KB) Any suggestion on " OpenCV Error: Unspecified error (The storage is not opened) in icvGets, file /datalocal/ti_components/open_compute/opencv_src/tiopencv/modules/core/src/persistence.cpp, line 299"? thanks and best regards He Wei

Hi He Wei, I am working with team on this to get more information. Will back to you soon Regards, Kumar.D

Dear Kumar, Thanks in advance. Just to give you more information: we had try both in linux and RTOS environment for the OpenCV, if either one is working, it is good enough for us but either one will give us some issue. We don't need the entire OpenCV libs but at least the libobjdetecion lib shall be working. I have searched around, seems the static lib (.a) need to have "proper" order when linking in makefile to avoid any dependency issue but I can't find what is this proper order. We are new to TI TDA2x and this is really crucial for our development if we can break through it. Thanks and best regards He Wei

Kumar, Please post your comments/questions on the same thread. Regards Karthik

Hi He Wei, We have limited support for openCV. We are not actively supporting addition of new openCV libraries. Please refer our Object detection demos using the TI libraries for any specific application. Regards, Kumar.D

Ticket Name: TDA2HG: About Deep learning application

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 Hi Sir we used TDA2 for development and knew SDK supports Caffe/TensorFlow training frame works. we would like to know that VGG, SSD, Yolo, Yolo v2 can be implemented in TDA2 or not? please advise and thanks BR Yimin

Object detection layers are not supported in the current release (01.00). SSD will be supported in the next release 01.01 (March end release) Regards, Kumar.D

Ticket Name: TDA4VM: [TDA4] How to disperse (assign) computing power for each core ?

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi, Expert : I'm studying TDA4 code programming for ADAS applications. follow this site, I can know the concept for IPC communication between each core. software-dl.ti.com/.../developer_notes_ipc.html but I still feel confuse this point : "How to disperse (assign) computing power for each core ?" I try to studying vision_app sample code (EX:tidl_object detection), this app use C66_1/C66_2/C7X, how to assign work for each core? software-dl.ti.com/.../group_apps_dl_demos_app_tidl_od.html same problems for main R5f core. any hit? Many Thanks.

Hi Gibbs, Need a clarification to understand your question better - how to disperse(assign) computer power for each core - the question is more about the CPU usage (MHz) rather than the power (Watt)? Is that understanding correct and can you consider expanding your question for better understanding? Regards Karthik

Hi, Karthik : My question(pint) is simple, and I may find some answers. TI OpenVX have this function : vxSetNodeTarget(n1, VX_TARGET_STRING, TIVX_TARGET_DSP1) n1 is node, 3'st parameter is core id, it includes : #define TIVX_TARGET_DSP1 "DSP-1" #define TIVX_TARGET_DSP2 "DSP-2" #define TIVX_TARGET_EVE1 "EVE-1" #define TIVX_TARGET_EVE2 "EVE-2" #define TIVX_TARGET_EVE3 "EVE-3" #define TIVX_TARGET_EVE4 "EVE-4" #define TIVX_TARGET_A15_0 "A15-0" #define TIVX_TARGET_IPU1_0 "IPU1-0" #define TIVX_TARGET_IPU1_1 "IPU1-1" #define TIVX_TARGET_IPU2 "IPU2" but I do not find define about "Core R5" . (MCU2_0, mcu2_1, mcu3_0, mcu3_1) How to assign job to MCU2_0, mcu2_1, mcu3_0, mcu3_1? Thanks

Hi Gibbs, It seems like you are looking at the TDA2 source code - can you please send me the references to this OpenVx code that you are looking at? Regards Karthik

Hi, Karthik : This file locate in psdk : path as below : psdk_rtos_auto_j7_07_00_00_11\tiovx\kernels_j7\include\TI\j7.h Gibbs

Gibbs, Ok, the previous code snippet was probably a different reference - I understand your question. Let me get back to you on this. Regards Karthik

Hi Gibbs, The MCU2_0 target is TIVX_TARGET_IPU1_0 and the MCU2_1 target is TIVX_TARGET_IPU1_1. The mcu3_0, mcu3_1 have not been enabled for OpenVX in our demos. We will be sure to have this more clearly documented in the next release. Regards, Lucas

Ticket Name: CCSTUDIO: How to compile a imported makefile project for EVE in CCS12?

Part Number: CCSTUDIO Hi Sir I imported a makefile project from EVE startware example, eve_bfswtch_arp32_error_intr. 1.I can compile it use CCS termimal with make command. 2. I got errors with the same makefile using CCS build in compile. - I do not know what it is and how to change the compiler. I attached the screen shot to show the makefile, the imported project, termimal compiled result and the compile error shows in console window. Thanks BR Jack

Hello Chung, Thank you for reaching out to Texas Instruments E2E support forum. I have taken your inputs and working on it. Please allow some time to revert back. Best Regards, Tushar

Hello Chung, Apologies for the delayed response. Can you please specify which device are you using? Regards, Tushar

Hi Looks like you are discussing this with the right product group on the following E2E https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1307552/ccstudio-compile-eve-starterware-fail-can-not-find-rts6740-lib/4969901#4969901 So will mark this one closed.

Ticket Name: TDA2: Booting from NAND, how to manage the application images

Part Number: TDA2 Hello: For the TDA2-EVM board, it boot from the sdcard with the ext2 file system, for our product which will use the nand for persistent storage. and seem little document introduce how to boot from nand. My question are: 1. For nand, should we organise the multiple app image based on file system like booting from sd card? 2. <<SBL User Guide>> under ti_components\drivers\pdk_01_09_00_17\packages\ti\boot\sbl_auto\docs\internal , introduce the tiimage file, is that based raw data or file system? 3. if boot from nand, seem the ubifs is the better, consider above, shall we make the multiple app image into an ubifs partition for u-boot to load multiple app images? 4. what's the different between connecting nand to emmc and connecting nand to GPMC? Thanks very much!

There is no support for NAND in PDK (RTOS) and there is no plan to use NAND in the future as well. The RTOS SBL supports only MMC, NOR and QSPI boot media. If you need NAND support use need to use Linux driver stack.

Hi, In addition to what Sivaraj said, NAND boot is supported for AM335x device: processors.wiki.ti.com/.../AM437x. You can use this as a reference in case you want to develop SBL for NAND boot. Kindly note that SBL and u-boot are two different boot loaders. It is not very clear from the question whether you are using linux (i.e. u-boot) or RTOS (i.e. SBL) as both are being referred in the question. Regards, Rishabh

Hello Both: As we'are new to the TDA2xx, maybe the question is not very clear. let me clarify it again. we'are using TDA2PX as our product, which will use the NAND as the boot media. the A15 will run the linux. the evem demo board use vision SDK and introduce the uboot and booting from the sdcard, so we are looking how we can boot from the NAND. 1. uboot is not SBL, if using SBL, tiimage format must be used for multiple app images? 2. uboot is for linux and SBL for RTOS? 3. for our case, we should use the uboot, and treat multiple app images like files and pack them into a filesystem? 4. the evem board boot from sdcard with ext4 filesystem, and for boot from nand, ubifs is better? BTW,what's the MLO under boot partition of the sdcard?

Hi, Yes you are correct that uboot is for linux and SBL is for RTOS. It seems that you are using Processor SDK Linux. Please let me know if this is not the case. Uboot does not claim NAND flash support for TDA2Px device. However uboot supports NAND boot for TDA2Ex. You can refer to below commits: git.ti.com/.../ git.ti.com/.../ git.ti.com/.../ You can also refer to below e2e threads on the same topic: e2e.ti.com/.../655887 e2e.ti.com/.../2165108 Regards, Rishabh

Hi, You should also note that TDA2xx, TDA2Px and TDA2Ex belong to the same SoC family but they are different SoCs. Regards, Rishabh

Hi Rishabh: we are using TDA2PHG and use NAND for boot media.

Hi, As explained above you need to implement the NAND boot for TDA2Px. Uboot does not claim NAND flash support for TDA2Px device. Regards, Rishabh

Hi Rishabh: Can give it more details about implement the NAND boot for TDA2Px. As my understanding, with the linux, only the Uboot is the only way to bring up the kernel. If the Uboot does not calin NAND flash support for TDA2Px device, should we focus on Uboot, and implement the NAND boot in Uboot?

Hi, Yes Uboot is needed to bring up Kernel. I have already shared the NAND support git patches for TDA2Ex device. You should refer to them and implement the same for TDA2Px. Regards, Rishabh

Hi Rishabh: Appreciate so much!

Hi, Glad to help. Kindly mark the post that resolved your query as "This resolved my issue". Feel free to ask any follow-up questions by creating a new thread. Regards, Rishabh

Ticket Name: TDA2SX: AM5729 (similar to the TDA2)

Part Number: TDA2SX Hi Stanley, I'm trying to solve the same issue, I need to disable the EVEs in the bootloader. I reviewed the provided VisionSDK documents but I cannot find a section that addresses this topic. Thank you Casey

Is there a way to disable the EVEs without turning off the VDD_DSP power rail to the EVE, IVU, and GPU?

As long as there is no EVE image in your multi-core AppImage, SBL (bootloader) will not load any code or boot EVE.

Ticket Name: TDA2: Platform supported by Processor SDK Linux Automotive 03.04

Part Number: TDA2 Other Parts Discussed in Thread: SYSBIOS Hi, I need information regarding PROCESSOR-SDK-LINUX-AUTOMOTIVE 03_04_00_03. Is This SDK have support for TDA2xx ? In my project, I am using TDA2xx. So, Is it good to use this SDK version? Please help to know this information. Thanks, Anand Kumar

Hi Anand, you can run Processor SDK Linux Automotive on TDA2x, also note that VisionSDK has Linux+BIOS version which runs Linux on A15 and SYSBIOS on other cores (Linux part is based on PSDKLA) - refer documents in "PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\docs\Linux". Regards, Yordan

Hi Yordan, Thanks for information. Thanks, Anand Kumar

Hi Anand, You can get this information by looking at release notes of any SW package provided by TI. Regards, Rishabh

Ticket Name: PROCESSOR-SDK-TDAX: Where I can find "algorithms\src\isp\src\isp_graph.c"?

Part Number: PROCESSOR-SDK-TDAX Hi Sir, Is any one can point me where to find "algorithms\src\isp\src\isp_graph.c" ? This is from "BA M Algorithm Framework User’s Guide". Thanks BR Jack

Hi, This is not released in the source form. Please contact your local TI support team for this. Regards, Brijesh

Hi Brijesh Thanks, I guess I found it in SDK. BR Jack Ho

Thanks, then closing this ticket.

Ticket Name: CCS/TDA2: what SL2_SRAM ？

Part Number: TDA2 Tool/software: Code Composer Studio MEMORY { L1P_SRAM : origin = 0x00E00000, len = 0x8000 L1D_SRAM : origin = 0x00F00000, len = 0x4000 /* 16 KB SRAM */ L1D_CACHE : origin = 0x00F00000, len = 0x4000 /* 16 KB cache */ L2_SRAM : origin = 0x00800000, len = 0x28000 /* SARAM in L2, = 256 + 32 - 128 = 160 KB*/ L2_CACHE : origin = 0x00828000, len = 0x20000 /* Cache for L2, which is configured as 128 KB*/ DSP2_L2_SRAM : origin = 0x40800000, len = 0x48000 SL2_SRAM : origin = 0x5B000000, len = 0x40000 EXT_MEM_CACHE : origin = 0x80000000, len = 0x08000000 /* DSP Used cachable area */ } SL2_SRAM : origin = 0x5B000000, len = 0x40000 what is SL2_SRAM mean？

Hi Shuai, This is an internal memory within the IVAHD subsystem. More details are available in the IVA Subsystem chapter in the TRM. Thanks and Regards, Piyali

Ticket Name: Linux/TDA2: TDA2xx vision_sdk Compile Error

Part Number: TDA2 Tool/software: Linux when i make -s -j to compile vision_sdk，The following error occurred： # Linking into /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/vision_sdk/bin/tda2xx-evm/vision_sdk_c66xdsp_1_release.xe66... undefined first referenced symbol in file --------- ---------------- EDMA3_semCreate /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/lib/tda2xx-evm/c66xdsp_1/release/utils_common.ae66<utils_dma_edma3cc.oe66> EDMA3_semDelete /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/lib/tda2xx-evm/c66xdsp_1/release/utils_common.ae66<utils_dma_edma3cc.oe66> edma3OsProtectEntry /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/lib/tda2xx-evm/66/release/edma3lld_drv.ae66<edma3_drv_adv.oe66> edma3OsProtectExit /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/lib/tda2xx-evm/66/release/edma3lld_drv.ae66<edma3_drv_adv.oe66> edma3OsSemGive /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/lib/tda2xx-evm/66/release/edma3lld_drv.ae66<edma3_drv_adv.oe66> edma3OsSemTake /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/lib/tda2xx-evm/66/release/edma3lld_drv.ae66<edma3_drv_adv.oe66> error: unresolved symbols remain error: errors encountered during linking; "/home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2 xx_evm_linux_all/vision_sdk/bin/tda2xx-evm/vision_sdk_c66xdsp_1_release.xe66 " not built make[7]: *** [/home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/vision_sdk/bin/tda2xx-evm/vision_sdk_c66xdsp_1_release.xe66] Error 1 make[6]: *** [c66xdsp_1] Error 2 make[5]: *** [apps_dsp1] Error 2 make[5]: *** Waiting for unfinished jobs.... # # /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_all/vision_sdk/bin/tda2xx-evm/vision_sdk_c66xdsp_2_release.xe66 created. # make[4]: *** [apps] Error 2 make[3]: *** [apps] Error 2 make[2]: *** [apps_exe] Error 2 make[1]: *** [apps] Error 2 make: *** [vision_sdk] Error 2 How can I solve this error?

Hi, Can you let us know what all other commands you run before running "make -s -j" Regards Surya

Hi, before running "make -s -j" ，i just run "make -s -j depend". Regards Xie Baojian

Hi Xie Baojian, Is there any change in SDK site or is it a plain SDK ? Regards Surya

Hi, i have no change in SDK ,but when i delete DIR/vision_sdk/binaries/$(MAKEAPPNAME)/$(MAKECONFIG) folder and compiled again，it Compiled successfully. i don't know why... Regards Xie Baojian

Hi Xie, Sometimes using -j creates a problem as one of the build targets would have failed due to dependencies, system load, etc. E.g. The error message you have shared above shows issue with EDMA LLD build. Typically you should not use -j while building for the first time, -j should be mostly used with incremental builds. Regards, Rishabh

Ticket Name: RTOS/TDA2: Linux/TDA2: I2C configuration for processor as SLAVE

Part Number: TDA2 Tool/software: TI-RTOS Hi, How can we configure the Processor as I2C slave in TDA2x? I have I2C4 to be configured as I2Cslave . Is there any sample example for Multiprocessor communication or have any example for I2C slave config?

Hi, You can refer to PDK example app: PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\drv\stw_lld\examples\i2c\i2c_slave_app Regards, Rishabh

Hi, Is there any document to know what the example is for? I tried it with connecting with an i2c master device. But the slave is not detected at master side. How the acknowledgment from slave to master is send in this example?

Hi, My suggestion will be to go through printUsage API in the application. Regards, Rishabh

Ticket Name: CCS/TDA2: TDA2X reading large data onto Memory

Part Number: TDA2 Tool/software: Code Composer Studio Hi, I'm working on TI TDA 2x and my C program requires large data file to be loaded onto memory. Originally in desktop, I loaded the required a file which is amount to 50~150MB binary data file(Most data is comprised of Integer) using fread(). But I'm afraid that the file maybe takes too long time to read in TDA board. To be simply, my C code reads arrays including innumerable Integers amount to 50~150MB. Is there a useful way to load large file? Is there someone who has experience about similar situation? Thank you.

hello Yes this can be one option - where you embedded the data file (as arrays/constants) in the executable. But this will increases the binary size. Another option - you can use CCS to load the file into memory SD card read or network read are other options - these are supported in vision SDK 3.3 release regards, Shiju

Ticket Name: Linux/TDA2: How to check availability of opencv lib/module in VSDK (Linux)?

Part Number: TDA2 Tool/software: Linux Dear TI: There are list of pre-build OpenCV libs in VSDK3.4 folder: PROCESSOR_SDK_VISION_03_04_00_00\ti_components\open_compute\opencv\opencv-3.1.0\libs_linux: libopencv_calib3d.a libopencv_objdetect.a .. I enable the opencx and build and run the OpenCV use case successfully under Linux, but I can't find any libopencv* (listed above) in targetfs. How to check which module is available inside the VSDK? ( I am trying to use openCV object detection API but failed and wonder if there is opencv objdetect lib available in VSDK Linux)? Thanks and best regards He Wei

I found it in makefile. Thanks and best regard He Wei

Hi He Wei, thanks for updating the thread! Regards, Yordan

Ticket Name: TDA2: Error in building tda2pxx vision sdk

Part Number: TDA2 Hi, I am building TDA2PXX vision sdk but i am getting the following error: Nothing to be done for tda2px a15_0 bsp_uart Nothing to be done for tda2px a15_0 bsp_mcspi /bin/echo: not found gmake[3]: *** [header] Error 127 /bin/echo: not found gmake[3]: *** [header] Error 127 /bin/echo: not found gmake[3]: *** [header] Error 127 /bin/echo: not found gmake[3]: *** [header] Error 127 /bin/echo: not found gmake[3]: *** [header] Error 127 /bin/echo: not found gmake[3]: *** [header] Error 127 /bin/echo: not found gmake[3]: *** [header] Error 127 /bin/echo: not found gmake[3]: *** [header] Error 127 gmake[2]: *** [depend] Error 2 gmake[1]: *** [links_fw_depend] Error 2 gmake: *** [depend] Error 2 C:\PROCESSOR_SDK_VISION_03_03_00_00\vision_sdk\build> I have followed each and every step in vision sdk user guide. I have tried many approaches to fix the above error but i am still getting it. Regards Mayank

Hi Mayank, Can you run build command "gmake depend" without -s & -j and share ? Note: gmake path should point to xdc path under ti_components (run where gmake & confirm) Regards Surya

Hi Surya, Thanks for your mail. Please find below the output after running the command suggested by you. C:/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/os_tools/windows/xdctools_3_32_01_22_core/bin/rm -rf C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/include/config/apps/tda2px_evm_bi gmake -fMAKEFILE.MK HeaderCORE=ipu1_0 header ; gmake -fMAKEFILE.MK HeaderCORE=ipu1_1 header ; gmake -fMAKEFILE.MK HeaderCORE=ipu2 header ; gmake -fMAKEFILE.MK HeaderCORE=a15_0 header ; gma gmake[3]: Entering directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' /bin/echo: not found gmake[3]: *** [header] Error 127 gmake[3]: Leaving directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' gmake[3]: Entering directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' /bin/echo: not found gmake[3]: *** [header] Error 127 gmake[3]: Leaving directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' gmake[3]: Entering directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' /bin/echo: not found gmake[3]: *** [header] Error 127 gmake[3]: Leaving directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' gmake[3]: Entering directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' /bin/echo: not found gmake[3]: *** [header] Error 127 gmake[3]: Leaving directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' gmake[3]: Entering directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' /bin/echo: not found gmake[3]: *** [header] Error 127 gmake[3]: Leaving directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' gmake[3]: Entering directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' /bin/echo: not found gmake[3]: *** [header] Error 127 gmake[3]: Leaving directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' gmake[3]: Entering directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' /bin/echo: not found gmake[3]: *** [header] Error 127 gmake[3]: Leaving directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' gmake[3]: Entering directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' /bin/echo: not found gmake[3]: *** [header] Error 127 gmake[3]: Leaving directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' gmake[2]: *** [depend] Error 2 gmake[2]: Leaving directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' gmake[1]: *** [links_fw_depend] Error 2 gmake[1]: Leaving directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/build' gmake: *** [depend] Error 2 C:\PROCESSOR_SDK_VISION_03_03_00_00\vision_sdk\build> Regards Mayank

Hi Mayank, There could be 2 issues 1. gmake path is incorrect 2. windows 8191 characters limitation 1. set gmake path on cmd prompt where you are building vision_sdk set PATH=C:\PROCESSOR_SDK_VISION_03_03_00_00\ti_components\os_tools\windows\xdctools_3_32_01_22_core;%PATH% 2. From logs, I can see few characters are missing, In such case try git bash to build C:/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/os_tools/windows/xdctools_3_32_01_22_core/bin/rm -rf C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/include/config/apps/tda2px_evm_bi gmake -fMAKEFILE.MK HeaderCORE=ipu1_0 header ; gmake -fMAKEFILE.MK HeaderCORE=ipu1_1 header ; gmake -fMAKEFILE.MK HeaderCORE=ipu2 header ; gmake -fMAKEFILE.MK HeaderCORE=a15_0 header ; gma gmake[3]: Entering directory `C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/src/rtos' /bin/echo: not found gmake[3]: *** [header] Error 127 Regards Surya

Hi Mayank, If the issue is resolved, Can we close this thread ? Regards Surya

Ticket Name: RTOS/TDA2EVM5777: PHY swich,(Ndk_nsp_hook.c)

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: DP83865 Tool/software: TI-RTOS Hello, everyone! Can I ask for help about switching the DP83865 phy to DP83867 on TDA2x evm board? I found there is a old question related to it. I also had a look the file "Ndk_nsp_hook.c",but I didn't find out any idea to change it, if anyone successfully switched the phy, please give me direction,thanks a lot.

Hi Yongliang, I believe this thread is a duplicate to the thread e2e.ti.com/.../798823 .Kindly close this thread. We can continue discussion on the other thread. Regards, Anand

Ticket Name: TDA4 capture output YUV420 format

Other Parts Discussed in Thread: TDA2 We use TDA4 and connect YUV422 camera. TDA2 can set capture input format YUV422 and capture output format YUV420. Can TDA4 set capture input format YUV422 and capture output format YUV420 ?

Hi, No, VIP module in TDA2x can convert YUV422 to YUV420, but CSIRX cannot convert YUV422 to YUV420. You will require to use some other module like LDC or DSS for this conversion. Regards, Brijesh

Ticket Name: TDA2: Compatible automotive gigabit ethernet phy

Part Number: TDA2 Other Parts Discussed in Thread: DP83848Q-Q1 Does TI have any compatible automotive gigabit ethernet phy that works with TDA2SG? What I find in TI with automotive grade is DP83848Q-Q1 but is 100Mbps.

Hello Lim, Please give me some time. I am checking with our PHY team, will let you know once get details from them. Thanks.

Prasad Jondhale said: I am checking with our PHY team Hello Lim, Can you please let us know the timeline by which you need the auto qualified PHY?

Hi Prasad, We need it by 2nd week of Oct 2018. If it is not possible to have it by that time, we may consider to use DP83848Q-Q1 for this prototype and change it to Gigabit PHY in next design phase. Has DP83848Q-Q1 been tested with TDA2X? Regards Lim

Hello Lim, Can you please drop me a mail at a0132233@ti.com so I can share TI auto PHYavailability details? Just want to confirm the our PHY timelines and if it aligns with your schedule. Thanks for understanding.

Closing this thread as discussions ongoing on mail.

Ticket Name: Compiler/TDA2SX: PROCESSOR_SDK_RADAR

Part Number: TDA2SX Tool/software: TI C/C++ Compiler Hi， I have two questions about processor radar SDK： 1、 Why not provide CCS projects? The CCS project is easy to debug and the code structure is clear. 2、 How to check the code structure in makefile mode? How to debug? Thanks a lot.

Hi, For processor radar/vision SDK, we do not provide CCS project. Its a makefile based build system. You can export entire vision SDK folder into any editor and do code browsing its upto your choice. Using CCS you can debug. Please check userguide and check load using using CCS. There you can add breakpoints, step through the code. Even if you boot using SD card then you can connect to any core(1st remove gel files for that core) and then load symbol instead of loading the program. Regards, Anuj

Hi, Thank you for your reply,but how can code built on makefiles be ported to CCS? Is there any guidance document? The code structure built by makefile is too complicated. How to assemble a complete CCS project? Thanks a lot

Hi, As told in earlier post, CCS based build is not supported. So you have to proceed with makefile based build. What kind of complication you are facing when you build with makefile and you think that will be resolved using CCS? Entire radar sdk can be exported to any code editor for code browsing. Just the building part you have to use makefile. regards, Anuj

Ticket Name: PROCESSOR-SDK-VISION 3.7 : How to change HSYNC polarity on HDMI output

Other Parts Discussed in Thread: TDA2 Hi Expert, I am using Processor SDK Vision 3.7 (PSDKV 3.7) and trying to connect HDMI output to DLP5531 (DLPC230 used) with some modification in PSDKV 3.7. Resolution changing to 1152x576 was successful, since I conformed that 1152x576 output image was seen on HDMI monitor without any errors. However, sync error in DLP is now being faced when connecting TDA2 to DLP5531. As a result of deep investigation, it seems that HSYNC on TDA2 HDMI output needs resersal of polarity. Please see below analog waveform for HDMI output. #1: HSYNC original : #2: HSYNC reversal: Could you please tell me which source code in PSDKV 3.7 should be modified for HSYNC reversal (#2) ? Best regard, Saito

Hi Saito-san, Please refer to file PROCESSOR_SDK_VISION_03_07_00_00\ti_components\drivers\pdk_01_10_03_07\packages\ti\drv\vps\src\vpslib\hal\src\vpshal_dssHdmi.c. You can update halHdmiWpVideoFormatConfig to hard code the value as an experiment to make sure output works. Regards, Rishabh

Hi Rishabh, Thank you for prompt reply. Initilized value is set as below. Is that correct ? //vpshal_dssHdmi.c VpsHal_HdmiInfo HdmiHalInfo = {{0U,0U,0U,0U,0U,0U,0U,0U,0U,0U,0U,0U}, {0U,0U,0U,0U,VPSHAL_HDMI_PACKETMODERESERVEDVALUE}, {0U,0U,0U,0U,0U,0U,0U,0U,0U,0U,0U,0U,0U,0U,0U,0U,0U}, {0U,0U,0U}}; I will try to chage HSYNC polarity. Best regards, Saito

Hi Saito-san, I would suggest you to get these values while running the binary and then flip the one you want to modify. You can build SDK in debug mode and put a break point on halHdmiWpVideoFormatConfig API. Regards, Rishabh

Hi Saito-san, Were you able to get this working? Regards, Rishabh

Hi Rishabh, Closing this thread. Thanks. Best regards, Saito

Ticket Name: TDA2SX: Data logging on TDA...best/most developed method?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi Team, Regarding algorithm validation via data logging on TDA2 series of parts, which is the recommended/typical interface and why? (i.e. ethernet, straight to SD card, USB to PC)? Do we have any software tools on the PC side already developed to receive video data? I'm aware of example Ethernet usecase which sends one frame at a time, but wondering if we have something more advanced. Best,

Hi Lina, I have forwarded your question to VisionSDK experts to comment. Regards, Yordan

Hello Lina, In vision SDK we have 'null' link which can be used for data logging. Currently it supports Ethernet, SD card and memory write. The choice of interface depends on throughput requirement of use-case. Ethernet supports higher bandwidth (upto 600Mbps TCP/IP) where as SD(~10Mbps) and memory are limited. If you want to log only few frames you can use SD card but for large video Ethernet is recommended. You can use opensource tools like ffmpeg, yuvplayer etc. for analyzing the post processed data.

Hi Prasad, Thanks for the information. What about USB? Have you seen that implementation with a PC? Best, Lina

Hello Lina, USB/PCIE are not supported with current implementation of null link.

Ticket Name: Linux/TDA2: ALG: ERROR: No alg create function specified (algId = 39) !!!

Part Number: TDA2 Tool/software: Linux Hi : i am thy to add a new Link_algPlugin in sample_app\src\rtos\alg_plugins, i add id at bottom of AlgorithmLink_DspAlgorithmId but have some problem follow is log OST] [HOST ] 78.946776 s: IPC_OUT_0 : Create in progress !!! [HOST] [HOST ] 78.946837 s: IPC_OUT_0 : Create Done !!! [HOST] [HOST ] 78.947447 s: pObj->Alg_FrameCopy_forhandLinkID start=50331697 [HOST] [DSP1 ] 78.946928 s: IPC_IN_0 : Create in progress !!! [HOST] [DSP1 ] 78.947325 s: IPC_IN_0 : Create Done !!! [HOST] [DSP1 ] 78.947538 s: ALG: ERROR: No alg create function specified (algId = 39) !!! what is the problem? thanks shuai

Hi Shuai, please make sure you call your your AlgorithmLink_XXXXXX_initPlugin function in App_init() in file "vision_sdk/apps/src/common/app_init/app_init_dsp.c". You need to call this function in order to register you algorithm plugin. Regards, Yordan

Ticket Name: CCSTUDIO: Compile EVE starterware fail. Can not find RTS6740.lib

Part Number: CCSTUDIO Other Parts Discussed in Thread: TDA2 Hi Sir I compiled the EVE starterware example project "mailbox_eve1_to_dsp1" But, it failed and show it short of rts6740.lib. Thanks BR Jack Ho

Hello, What TI processor are you writing code for? Regards, Nick

Hi Nick It is TDA2X Jack

Hello Jack, Got it. Sending your thread other to the TDA2 team. Please note that responses may be delayed due to the holidays. Regards, Nick

If you are building SDK example from CCS project, it is not supported. You need to use makefile system with commend-line build from commend prompt. Please refer to the PDK user guide in SDK for details.

Hi Stanley Thanks, I got it work on CCS. But, I need more doc to get more inside of EVE. Please help me withe access of CDDS. Thanks BR Jack Ho

CDDS access requires signed NDA with TI. Please contact our local Sale office to assist with that.

Hi Stanley Could you provide me the contact info? BR Jack

Will share the contact offline.

Ticket Name: Linux/TDA2EVM5777: Linux/TDA2EVM5777

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hello, I cann't find pinmux file for TDA2EVM5777 evaluation board. Can you help me find it? Thanks

Hi, You should use the pinmux tool: https://dev.ti.com/pinmux/ Regards, Rishabh

Helllo, I needs a *.pinmux file (for example, " TDA2EVM5777.pinmux") for corresponding EVM module. Regards, Maxim

Hi, We don’t have sample files for TDA2 EVM. You can choose the mux mode values from tool and generate the file. You can use files for a similar device as reference: bitbucket.itg.ti.com/.../board_files Regards, Rishabh

It's pity. P.S. Developers, which made EVM did not used PinMux utility really?

Hi, Unfortunately Vision SDK does not use this tool. Every driver does pin mux before using the respective peripheral. Regards, Rishabh

Ticket Name: TDA2: TIDL new oobect

Part Number: TDA2 Hi, I have seen from the TIDL document that the following example use-case in the sdk supports only 4 objects. 1. Road 2 Pedestrian 3 Traffic Sign 4 Vehicle can it possible to add a new object to the TIDL? Is there any support from TI for getting object files/models for the requirement? What is the type of objects used in TIDL? Is this support caffe model? Please enlighten.

Hi Sreerag, yes, you can use Caffe framework to add new objects for TIDL. Look at those links: github.com/.../caffe-jacinto github.com/.../caffe-jacinto-models Also you can check the userguide: PROCESSOR_SDK_VISION_03_XX_XX\ti_components\algorithms\REL.TIDL.01.01.03.00\modules\ti_dl\docs\TIDeepLearningLibrary_UserGuide.pdf for details. Regards, Yordan

I saw some bin file is used for object detection in the TIDL user guide. how to convert the caffe model into this .bin file?

Hi Sreerag, do you refer to "tidl_net_*.bin" and "tidl_param_*.bin"? They are created with "importTestCases.bat" script. This is in step 3. and 4. in chapter "3.6.4 Importing Caffe-Jacinto-Models" of the userguide. Regards, Yordan

Ticket Name: 编译器/ TDA2SX： I have some questions about yocto compilation

Part Number: TDA2SX Tool/software: TI C / C ++编译器 Hi,I builded a Yocto file system, compiled with the version of psdkla-V3.4.However, two tasks have been unpacking, and they have not been completed for about 3 days.How should I solve it? log is here.Thanks. # ./build-core-sdk.sh dra7xx-evm [PSDKLA]> [PSDKLA]> Current Directory is /home/xiaomiao.yang/psdkla_03_04_00_03/yocto-layers [PSDKLA]> PATH is /usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/snap/bin:/opt/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/bin/ [PSDKLA]> Building on hirain-PowerEdge-R740 running Linux hirain-PowerEdge-R740 4.15.0-29-generic #31-Ubuntu SMP Tue Jul 17 15:39:52 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux [PSDKLA]> Starting Yocto build at Fri Sep 4 09:55:46 CST 2020 [PSDKLA]> [PSDKLA]> cd build [PSDKLA]> . conf/setenv [PSDKLA]> cp conf/local.conf conf/local.conf.pristine [PSDKLA]> MACHINE=dra7xx-evm bitbake -k tisdk-rootfs-image NOTE: Started PRServer with DBfile: /home/xiaomiao.yang/psdkla_03_04_00_03/yocto-layers/build/cache/prserv.sqlite3, IP: 127.0.0.1, PORT: 42837, PID: 28823 Loading cache: 100% |############################################################################################################################| ETA: 00:00:00 Loaded 2849 entries from dependency cache. NOTE: Resolving any missing task queue dependencies Build Configuration: BB_VERSION = "1.30.0" BUILD_SYS = "x86_64-linux" NATIVELSBSTRING = "Ubuntu-18.04" TARGET_SYS = "arm-linux-gnueabi" MACHINE = "dra7xx-evm" DISTRO = "arago" DISTRO_VERSION = "2016.12" TUNE_FEATURES = "arm armv7a vfp thumb neon callconvention-hard" TARGET_FPU = "hard" meta-glsdk = "HEAD:66cfd8ef55344508d6e7b306259f34c05b828194" meta-arago-distro meta-arago-extras = "HEAD:4c01410ffde8853224567fb6078d7d9f190b942f" meta-qt5 = "HEAD:f8584d7a7c90afc71484a40279aa3df651d0e04f" meta-networking meta-ruby meta-python meta-oe = "HEAD:55c8a76da5dc099a7bc3838495c672140cedb78e" meta-ti = "HEAD:5f3a1169d307fec41626f850f5c700437dedbe93" meta-linaro-toolchain meta-optee = "HEAD:2f51d38048599d9878f149d6d15539fb97603f8f" meta = "HEAD:bfa04fa71c47e8fe9528208848cfcec2e232777d" NOTE: Preparing RunQueue NOTE: Executing SetScene Tasks NOTE: Executing RunQueue Tasks ERROR: automake-1.15-r0 do_compile: oe_runmake failed ERROR: automake-1.15-r0 do_compile: Function failed: do_compile (log file is located at /home/xiaomiao.yang/psdkla_03_04_00_03/yocto-layers/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/automake/1.15-r0/temp/log.do_compile.28877) ERROR: Logfile of failure stored in: /home/xiaomiao.yang/psdkla_03_04_00_03/yocto-layers/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/automake/1.15-r0/temp/log.do_compile.28877 Log data follows: | DEBUG: SITE files ['endian-little', 'bit-32', 'arm-common', 'arm-32', 'common-linux', 'common-glibc', 'arm-linux', 'arm-linux-gnueabi', 'common'] | DEBUG: Executing shell function do_compile | NOTE: make -j 16 | : && /bin/mkdir -p doc && { PATH='/home/xiaomiao.yang/psdkla_03_04_00_03/yocto-layers/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/automake/1.15-r0/build/t/wrap:'$PATH && export PATH; } && /usr/bin/perl ../automake-1.15/doc/help2man --output=doc/automake-1.15.1 automake-1.15 | help2man: can't get `--help' info from automake-1.15 | Try `--no-discard-stderr' if option outputs to stderr | Makefile:3687: recipe for target 'doc/automake-1.15.1' failed | make: *** [doc/automake-1.15.1] Error 255 | WARNING: /home/xiaomiao.yang/psdkla_03_04_00_03/yocto-layers/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/automake/1.15-r0/temp/run.do_compile.28877:1 exit 1 from 'exit 1' | ERROR: oe_runmake failed | ERROR: Function failed: do_compile (log file is located at /home/xiaomiao.yang/psdkla_03_04_00_03/yocto-layers/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/automake/1.15-r0/temp/log.do_compile.28877) ERROR: Task 6172 (/home/xiaomiao.yang/psdkla_03_04_00_03/yocto-layers/sources/oe-core/meta/recipes-devtools/automake/automake_1.15.bb, do_compile) failed with exit code '1' Currently 2 running tasks (4157 of 7428): 0: ti-cgt-arm-native-16.9.2-r0 do_unpack (pid 28868) 1: ti-cgt-pru-native-2.1.4-r0 do_unpack (pid 28871)

Hi, The details on this post should help you to resolve the problem: https://e2e.ti.com/support/processors/f/791/p/712340/2625408#2625408 Regards Karthik

Hi Karthik Ramanan Thank you for the reply.Your solution is very effective.

Ticket Name: CCS/TDA2EG-17: Is it possible to run Different Network on Different core (TDA Platform)?

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2 Tool/software: Code Composer Studio Hi . We have a customer made their PCB within TDA2. Some questions: A. Is it able to run the different Deep Learning Network on different core at the same time on TDA2 Platform? B. If yes, please provide the related document. If no, which TDA platform can allow them to do this? Please comment ,thanks. BR Rio

Hi Rio, A. Yes B. We have maximum 4 EVEs, each of them can run separate nets, please refer to TIDL use cases in vision SDK Thanks, Praveen

Hi Parveen: Which Section of TIDL document to address different Network model for doing the Deep Learning? I only can find we can set 4 EVE running at the same time, but no clear instruction to address different model running on different EVE. please comment, thanks. BR Rio

Hi Rio, We don't have any document or instruction to address different model running on different EVE (because we had not tried this at our end), but it is possible to do this. Thanks, Praveen

Hi Praveen: Do you have any clear instruction or some hints for us to achieve this? Any help to let us try? BR Rio

Hi Rio, I don't know how to achieve this, may be someone from VSDK team can help. Kindly contact them offline. Thanks, Praveen

Hi Praveen: I don't know who is the right person of the VSDK team. May you send me their email to my email? Thanks. BR Rio

Hi Rio, You can contact Gaviraju for VSDK questions and he will direct to someone if required. Thanks, Praveen

Ticket Name: TDA2EXEVM: How to use remote service on TDA2

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 The customer would like to get serializer and deserializer‘s register information in usecase code, but that information is on another core, so he intends to use remote service to get the information which is on another core. The customer would like to know how to use remote service function on TDA2, and could you you please offer an example? Thanks. Best Regards, Cherry Zhou

Hi, The latest update as follows: The customer also would like to have an example about how to use remote service function based on TDA2 SDK. Thanks again! Best Regards, Cherry Zhou

Hi, May I know is there any update? Thanks! Best Regards, Cherry Zhou

Hi Cherry, Could you give some details about the customer system? What OS is used on A15? Which core will have the SerDes driver? Which core does need to get the register info via remote calls? Regards, Stanley

Ticket Name: PWM control external drive buzzer on TDA2

Other Parts Discussed in Thread: TDA2 Hi all, My code base is VisionSDK_2_10 and use TDA2 custom board. I want to use PWM to control external drive buzzer. The two function pins could be choose from TDA2. One is ehrpwm and another one is timer to configure to PWM output. But I checked bsp driver (VISION_SDK_02_10_00_00\ti_components\drivers\bsp_01_06_00_11\src) that did not have the example code for ehrpwm or timer. Could you please indicate where has the example code for this function? Thanks a lot. B.R. OC

HI, Your question has been forwarded to the Vision SDK team Best regards Lucy

Hi are you looking for a timer configuration sample code or something else? regards, Shiju

PWM module is not supported in VSDK or Starterware

Hi Sivaraj, Shiju, Let move to private forum for discussion. Thanks a lot. B.R. OC

Ticket Name: TDA2HG: Vulcan support

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 Does the GPU on the TDA2 support the Vulcan API?

Hello Aaron Seibold , The TDA2x GPU is SGX544 core. On the 3rd party support page this core is listed as "not supported". Furthermore, this 3rd party API is also not listed as supported in the TRM. Here is what's supported officially: – OpenGL® - ES 1.1 and 2.0 – OpenCL™-EP 1.1 – Direct3D® Feature Level 9.3 Thanks, Alex

Ticket Name: CCS/TDA2: CCS Load test_eveMedianFilter.eve.out no response

Part Number: TDA2 Tool/software: Code Composer Studio Hi， I load the test_eveMedianFilter.eve.out in the path of \PROCESSOR_SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\apps\median_filter\test\elf_out by the windows CCS， But it is nothing printed out，and Resume Button No change to green. But My colleague's machine is able to run and print out, and his Resume Button is green after load. What is wrong with my environment?

Hi, Have you followed all steps to load and run the binary on CCS as mentioned in evesw_getting_started.pdf? Before loading the binary you should reset the EVE core, let me know if you have done this step? Regards, Anshu

Hi I have solved this problem ， I forget to modify the config file. Thanks, Xie Baojian

Ticket Name: TDA2EVM5777: Omnivision Sensors with Vision SDK

Part Number: TDA2EVM5777 Hi, From your previous response : Q1: Yes. Vision SDK supports OV10635 camera module which is connected directly to TDA2 EVM. Q2: You can connect camera module with IR filter on TDA2. You can check out this DM demo with IR camera done by our 3rd party using Vision SDK. www.youtube.com/watch In the demo video for IR camera, OV10635 camera module itself is used. But, instead of using IR Cut filter (default comes with camera) , they have used IR Pass filter on camera lens? Is my understanding correct? Regards, Sagar

Sagar, Youtube link seems to be incorrect. Well it can work.. but it is better first to bring up new camera with the simple example in PDK. Rgds, Brijesh

Hi Brijesh, This is proper link: www.youtube.com/watch I have tda2x evm board which comes with OV10635 camera module by default. I am able to build camera display usecase and i can see camera output on hdmi display. My main question is whether the camera used in youtube demo is OV10635 ? Because, in OV10635 datasheet it is mentioned that it can be used for night vision. Regards, Sagar

Sagar, I am trying to get this details, will get back to you on this. Rgds, Brijesh

Sagar, Still have not the details, will update you as soon as i get it. Rgds, Brijesh

Sagar, This demo uses Sony IMX290 2MP sensor. This sensor board is build by D3. Regards, Brijesh

Ticket Name: TDA2EX17EVM: TDA2 EX - RTOS , customer needs to know how to set / config to their own GPIO

Part Number: TDA2EX17EVM Hi Champs: If customer wants to make their own purpose on the GPIO and test it on the TDA2 EX17 EVM, How to give them the GPIO example to work? I trace the code of this: ultrasonicCaptureLink_hw.c Can the ultrasonic code be able to re-modify for their own purpose GPIO? If no, how to set the other GPIO to make their own purpose? BR Rio

Hi Rio, can you check if PDK standalone GPIO examples can help you: Regards, Yordan

Hi Yordan: May we know where is the GPIO example path? This is TDA, not Sitara... BR Rio

Hi Rio, please check in <VSDK_dir>\ti_components\drivers\pdk_01_10_04_05\packages\ti\csl\example\gpio Regards, Yordan

Ticket Name: CCS/TDA2: Create an RTSC project in ccs, where the cfg file calls other .cfg files. How do you do this?

Part Number: TDA2 Tool/software: Code Composer Studio Create an RTSC project in ccs, where the cfg file calls other .cfg files, how to do this. For example, there is xdc.loadCapsule("bspCommonBIOS.cfg") in captureVip.cfg; I put both cfg files in the project directory at the same time, or how do I need to deal with them?

Hi, can you check it that can help you: processors.wiki.ti.com/.../Files_in_CCS_Projects Regards, Yordan

Ticket Name: TMDSEVM572X: floating output after importing model

Part Number: TMDSEVM572X Other Parts Discussed in Thread: AM5728, TDA2 SDK: 06_03_00_106 Hello, TI! I read Victor Cheng's answer in this thread https://e2e.ti.com/support/processors-group/processors/f/processors-forum/892591/tda4vm-tidl-how-can-i-get-out-q-values-scale-factors-of-layers-after-model-import/3300978?tisearch=e2e-sitesearch&keymatch=dataq#3300978. The answer said the floating output is (integer output) / (dataQ factor) / (2^quantized bit, like Q8 format, 256). Just want to make sure if this formula is also applicable to the TIDL library in the processor sdk for AM5728? Thanks!

Hi, yes, AM57x is a similar device as TDA2. So you can use Victor's answer for TDA2 Thank you, Paula

Thank you very much Paula.

Ticket Name: TDA2SA: Why the D2 and D3 of DSS Vout1 can't output signals?

Part Number: TDA2SA Other Parts Discussed in Thread: TDA2 Dear TI, We made a new TDA2 board, and found the D2 and D3 pin of DSS Vout1 are broken on some board. 1. We measured the impedance of those pins. The impedance value of good one is about 6.7K, the impedance value of bad one is about 2R. 2. We tried to config the D2 and D3 to GPIO, they can't be controlled to switch to high level or low level. 3. The D2 and D3 pins are only connected to DS933 chip. 4. The D4~D9 are good, not be broken. Could you please help to analyze this issue? Why the D2 and D3 are broken, other pins are ok? wade

Wade, Can you summarize how many boards you've tested - how many pass vs fail? Is it always D2 and D3 that fail at the same time? Is the schematic for D2 and D3 the same as the other D4-D9 IOs? How are you testing the PCBs during manufacturing? Do you perform ICT or BSDL style testing? Thanks, Kyle

Hi Kyle, We made four boards at the first time. Two of them are OK. Two of them are NG. The case of NG boards are same, only D2 and D3 are abnormal. There is no difference of the connection of D2~D9. About the NG board, we remembered it is ok before. But we can't understand why they become abnormal. The connection of D2~D9 as below: TDA2X Dx ----> 22ohm resistor -----> D90UB933 Dx wade

Hello Wade, Can you elaborate on what is "abnormal" about those IOs? Are they wiggling at all? Can you put those pins (and neighbors) into GPIO mode, and test if you can see them go high and low? If it was working before and is no longer working I would guess that some form of damage has occurred. Is there any cable or outside influence that can be mistreated? Thanks, Kyle

Hi Kyle， Yes, in GPIO mode, the pin also can't go high and low. We will plan to make more new boards to check. Thanks a lot! wade

Ticket Name: RTOS/TDA2EVM5777: which os systems are supported on this platfrom?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2, SYSBIOS Tool/software: TI-RTOS Dear, Now We want to use TDA2EVM5777 platform to develope project. Because there are 2-cortexA15 arm cores,2-C66X DSP cores. 2x Dual Cortex-M4. I want to know if the whole platfrom is supported by SYS/BIOS? if so,we can debug project for every cores in SYS/BIOS by emulator? by the way, if there are some others OS systems for this platform,such linux,IOS,and so on? BRS, Meng

Hi Meng, Are you using Vision SDK for this platform? It does support SYS/BIOS for all the cores. Please refer to Vision SDK White paper, figure 4 for the software stack diagram ( www.ti.com/.../spry260.pdf). Regarding the question about emulator support and other OSes support, we would have to move this thread to the device forum for a faster response from the TDA2 platform experts. Vikram

Dear Vikram, Thank you for your reply. I shall browse through the document mentioned by you. BRS, Meng

Dear Vikram, Thank you for your reply. There are some others questions about this platfrom,could you give me help? Thank you in advance. The following picture is TI vision SDK software frame. I want to know which ccs version is used for TI vision SDK software? which sysbios version is used for TI vision SDK software? The software use IPC3.0 for Inter-core communiation,where I can download this IPC version? It is suggested for sysbios version,IPC version and XDCtools from the following website: software-dl.ti.com/.../index.html For IPC3.0, which sysbios version and Xdctools and ccs version are suggested? by the way,my current OS is WIN7. CCS6.0 version and above can be installed in WIn7 OS? T Thanks a lot! BRS, Meng

Hi Meng you do not need to download each components like Sys-bios, IPC, XDC separately, VSDK is a single installer contain all these packages, just download VSDK and follow the User guide to build and test. CCS version 6.0.1.00040 or higher should be used along with vision SDK 2.10 or 2.11 release. Regards, Shiju

Ticket Name: Linux/TDA2EVM5777: Latest Linux Kernel available?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hello! I've got a problem using linux on DRA7xxx (XC5777X Board): The "remoteproc" is not usable in SDK "Vision_SDK_2_12_02_00". The Kernel used in this SDK is a special patched linux-4.4.45 without generating the "sys/class/remoteproc" - control stuff! The mainline Kernel 4.13.0 is far away from the kernel used in the SDK, so backporting will not be as easy... but remoteproc is fully integrated. (Without any kind of TDA2 ipu or dsp support...? At least I can not not find any usable dts-file, or any supporting code... ) Do you have a newer linux kernel than 4.4 dealing with TDA2 subcores and fully suppored remoteproc? I have to work with M4 and DSP in TDA2 bare metal, so controlling the subcores with remoteproc (start, stop, etc...) is needed. Thank you... Marco.

The solution: patchwork.kernel.org/.../

Hi Marco, it's great you solved the issue and thanks for sharing the solution. Regards, Yordan

Ticket Name: TDA2: Max objects count using AWR1243.

Part Number: TDA2 Other Parts Discussed in Thread: AWR1243 Hi, We are working on AWR1243 with TDA2px board. We just want to know what is the maximum number of objects, can be detected by AWR1243.

Hi Vasantha, The maximum number of objects is a function of the memory and processing power. It is usually an application defined requirement. You can use the Radar System planner available in the Processor SDK Radar release package to analyze the processing power and memory bandwidth requirement for the number of objects you are looking at. Thanks and Regards, Piyali

Ticket Name: TDA2P-ACD: DRA7x: How to boot from eMMC Boot Partitions (e.g. mmcblk1boot0/)?

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Hello *! I'm not able to boot DRA7x (TDAX) from special eMMC bootloader partitions. I can create a vfat formatted partition on user-area of the eMMC, but this is suboptimal. Is there any possibility to boot from e.g. mmcblk1boot0 ?

Hi Marco, which SDK you use? Regards, Yordan

Sorry, but what has the SDK to do with my question? We do not use any TI-SDK, because it's too far away from our requirements. My question was: Is it possible on DRA7x to boot from mmcblk1boot0 ? => First, this is a question of the ROM-Code capabilities in the Chip. Let me ask my question more clearly: Is the ROM-Code of DRA7x able to boot from the special "boot" partitions on an eMMC?

Hi Marco, TDA2 supports these eMMC modes by ROM: • Raw (Boot): The booting image is read from one of the selectable partitions in raw mode (this mode is also called Alternative Boot Operation mode and applies to eMMC only). • Raw (UDA): The booting image is read from the user data area (eMMC and SD). • File system (FAT12/16/32 with or without master boot record): The image data is read from a booting file within a file system in the user data area (eMMC and SD). NOTE: File system mode is only supported when booting in the eMMC user area. It is not supported in the eMMC boot area. Regards, Stan

Ticket Name: Compiler/TDA2: gmake gmake[5]: *** No rule to make target `;'. Stop.

Part Number: TDA2 Tool/software: TI C/C++ Compiler Dear TI, During the VSDK3.4 compile in RTOS windows mode, gmake give me this error: gmake[5]: Entering directory `D:/TI_VSDK_03_04/vision_sdk/links_fw/src/rtos/links_common/algorithm' gmake[5]: *** No rule to make target `;'. Stop. gmake[5]: Leaving directory `D:/TI_VSDK_03_04/vision_sdk/links_fw/src/rtos/links_common/algorithm' gmake[4]: *** [links_common_algorithm] Error 2 gmake[4]: Leaving directory `D:/TI_VSDK_03_04/vision_sdk/links_fw/src/rtos' gmake[3]: *** [libs] Error 2 gmake[3]: Leaving directory `D:/TI_VSDK_03_04/vision_sdk/links_fw/src/rtos' gmake[2]: *** [links_fw_libs] Error 2 gmake[2]: Leaving directory `D:/TI_VSDK_03_04/vision_sdk/build' gmake[1]: *** [apps] Error 2 gmake[1]: Leaving directory `D:/TI_VSDK_03_04/vision_sdk/build' gmake: *** [vision_sdk] Error 2 Actually it is working successfully before but failed to due to the above error. Can you advise how to debug on it? Thanks and best regards He Wei

Hi, He wei, I am not familiar with the SDK, but It seems that the problem is the same as described in: %20Error%202:1230:0] Please, also check the following threads: https://e2e.ti.com/support/arm/automotive_processors/f/1021/t/636297?tisearch=e2e-sitesearch&amp;keymatch=No%20rule%20to%20make%20target%20`;%27.%20Stop. Regards, Mariya

Hi, Can you check if you are using gmake from xdctools. Regards, Rishabh

Dear Rishabh, yes. the path is correct: D:\TI_VSDK_03_04\vision_sdk\build>where gmake D:\TI_VSDK_03_04\ti_components\os_tools\windows\xdctools_3_32_01_22_core\gmake.exe

Hi, Can you specify what all build commands you are running. Regards, Rishabh

Dear Rishabh, I am using " gmake -s -j depend" cmd. In addition, I use the git bash too based on one thread information, it doesn't have this " *** No rule to make target `;'. Stop." error but got the "Permission" error. Thanks and best regards He Wei

Hi, Can you try only "make -s depend". Also please share the permissions error you are getting. Regards, Rishabh

Dear Rishabh, 1. In windows cmd, I still get same error when run "gmake -s depend". 2. It is ok now in git bash after running as admin. But Window cmd still got the issue. and don't what is the cause? Thanks and best regards He Wei

Hi, Glad that the issue is resolved. Can you try running from command prompt in admin mode. Also are you trying a clean build when you are facing this issue? Regards, Rishabh

Ticket Name: Linux/TDA2: TDA2x Pin Muxing for Linux

Part Number: TDA2 Other Parts Discussed in Thread: DRA742 Tool/software: Linux Hello every one, I am trying to connect a custom camera board to TDA2x board. How can I change the pin muxing for linux ? I want to connect the cameras in vin1a,vin2a,vin6a and vin1b port. How can i do the pinmuxing for the same ? Regards, Renjith

Hello, One way to do so is to use the pinmux tool: https://dev.ti.com/pinmux/ . You can then dump register setting to a file and use that configuration in the SDK driver (I believe it's a .dts file actually). thanks, Alex

Hi Alex, Thank you very much for your quick reply. I want to know one more thing , Can i use PDK for developing the same ? or PDK is only for RTOS ? Regards, Renjith

Renjith Mohan said: I want to know one more thing , Can i use PDK for developing the same ? or PDK is only for RTOS ? Let me ping PDK experts as this is slightly out of my expertise. They will reply here soon. thanks, Alex

Helllo, TI recommends to perform all the pinmux from u-boot first stage (MLO) You should describe the required pinmux settings in the board/ti/dra7xx/mux_data.h If you are using vision SDK, you are already using PDK for basic drivers. When running with Linux, some devices are controlled from A15 Linux while other are controlled from M4 RTOS. In this case, pinmux is controllled by A15 u-boot. PDK code for pinmux should not be used since it runs on M4. Regards, Nikhil D

Hello Nikhil, Thank you verymuch for your valuable reply.. I am working on Vision SDK in DRA74x EVM REV H.0 board, which all are the PDK drivers working with Linux ? In my case i want to connect 4 cameras , Can i use the serializer & deserializer drivers in PDK ? Do i need to configure all the things in linux ? What all are the things controlled by A15 U-boot ? Regards, Renjith

Hii Nikhil, Could you Help me on this ? Actually my use case is connect four camera with TDA2xx in Linux , VisionSDK version 3.04. CAM1 -> VIN1A 8bit mode. CAM2-> VIN2A 8bit mode. CAM3 -> VIN6A 8bit mode. CAM4 -> VIN1B 8bit mode. I have already tried everything within my knowledge.But dont work for me. I Set the pimux changes as in file attached. What all are the changes need to do in SDK side and Kernel Side ? Could u help to solve this problem.. 6840.pin_mux.pdf

Hi, For the camera capture, you can use the PDK drivers, it should work well. None of the cameras are controlled by Linux/Uboot so there isn't any conflict. I assume, If you are using TI EVM, then all the cameras are connected to i2c5. In this case, PDK drivers will also control the i2c ONLY pinmux and boardmux is setup by the u-boot first stage. Apart from that, everythin is controlled by PDK drivers. Regards, Nikhil D

I reviewed your pinmux document. You should describe the required pinmux settings in the board/ti/dra7xx/mux_data.h There are macros to describe the PAD registers and muxmodes. Nikhil D

Hi Nikhil , I am using DRA74x EVM REV H.0 board. I configured values for "dra74x_core_padconf_array, dra742_es2_0_iodelay_cfg_array" in the board/ti/dra7xx/mux_data.h But i couldn't find delay values for "dra742_es1_1_iodelay_cfg_array" in TRM/DataSheet etc. Where can i get these ioDelay values ? Regards, Renjith

Hi, You can find the iodelay values from the data sheet. Also, you can utilize the python tool which generates the iodelay values for the pad config that is done already. https://git.ti.com/glsdk/iodelay-config I hope this is helpful Regards, Nikhil D

Hi Nikhil, I have some more doubts regarding this, pin muxing done in board/ti/dra7xx/mux_data.h file. Where i can set the instances/port for VIP as per the requirement ? I want to change the SerDes config (linux) , Can i follow the "Video Driver Porting Guide for TDA2xx, TDA2Ex and TDA3xx" ? It would be greateful if you share an example ( how to set vin1b port instance/capture) . Regards, Renjith

Hi Ranjit, I would suggest to close this thread and open another for VIP camera configuration. The appropriate owner shall respond on that. Regards, Nikhil D

Ticket Name: TDA2EVM5777: Where and how to get the demo input clips?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Dear Sirs: We are using PROCESSOR SDK VISION 03_07_00_00. We build the TDA2 RTOS demo and run the code to test on the EVM. We want to test the case Single Camera Usecases 1CH VIP capture (HDMI) + FrontCam Analytics 2 (PD+TSR+VD+LD+TLR+SFM) (DSPx, EVEx) + Display (HDMI) After execute, we play the input vide in NB and output to the HDMI which is connect to EVM HDMI input, however the result is not good. We know that TI has demo clips of this case, I just want to know where and how we can get it? Regards, /ckhsu

Hi Hsu, The demo clips are here: https://cdds.ext.ti.com/ematrix/common/emxNavigator.jsp?objectId=28670.42872.30602.25095 Thanks and Regards Piyali

Hi Piyali: Thank you very much. Regards, /ckhsu

Ticket Name: TDA2: TDA2X

Part Number: TDA2 Hi, I want a boot print message for a TDA2X EVM board.Could you give me a complete Boot print log？Please send me a document.Thank you! Best regards , Ycc

Hi Ycc, Are you running RTOS or Linux? Regards, Rishabh

linux

Hi, I use SD only boot,when Create SD card boot and insert it into EVM micro SD slot.Turning on the power of TDA2XEVM，then give me a complete print log.Thank you! Best regards , Ycc

Hi, Please find attached the logs for the application (Vision-SDK) as well the kernel logs on boot-up. Regards Shravan VSDKLinux boot logs.txt

Hi, I have already seen your VSDKLinux boot logs.txt.I have a question.when you Log in as root on the UART console,you can run ./apps.out directly. I compiled VisionSDK according to VisionSDK_Linux_UserGuide to create SD card boot.The instructions for running the demo are as follows： I have to run load_ocl_kos.sh、opencl_env.sh、vision_sdk_load.sh first,then run apps.out.Otherwise it will give an error.As shown below root@dra7xx-evm:/opt/vision_sdk# ./apps.out ASSERT (osa_mem.c|OSA_memInit|595) Why can you run apps.out directly?What are the effects of these three documents?Finally, I attached the log record of my operation. Regards， Yccmy log.log

Hi， I am sorry that the picture above is wrong.The instructions for running the demo in VisionSDK_Linux_UserGuide are as follows: I am looking forward to your reply. Regards, Ycc

Hi, You have to run the vision_sdk_load.sh script before running apps.out as it loads the memcache kernel module which is used by the Vision-SDK application. If you have any further questions, please create a new thread, we will support you. Issue pertaining to the Vision-SDK logs is resolved. Thank you. Regards Shravan EDIT: You need to run the script vision-sdk-load.sh, not source it. please go to /opt/vision_sdk folder and run ./vision-sdk-load.sh.

Hi Ycc, Even in the log shared with you, ./vision_sdk_load.sh is called. Other two scripts are needed for for opencl. The scripts are present here: PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\build\hlos\scripts\linux. I would suggest you to go through them to understand what each one is doing. Regards, Rishabh

Ticket Name: TDA2HF: Program on M4 auto start when i load program by CCS

Part Number: TDA2HF Processor :TDA2X SDK: VISION_SDK_3.8 According to the <<VisionSDK_UserGuide_TDA2Ex.pdf>> ,i load the progarm : On ARP32_EVE_4, load the binary, “vision_sdk_arp32_4_release.xearp32F”. On ARP32_EVE_3, load the binary, “vision_sdk_arp32_3_release.xearp32F”. On ARP32_EVE_2, load the binary, “vision_sdk_arp32_2_release.xearp32F”. On ARP32_EVE_1, load the binary, “vision_sdk_arp32_1_release.xearp32F”. On C66xx_DSP2, load the binary, “vision_sdk_c66xdsp_2_release.xe66”. On C66xx_DSP1, load the binary, “vision_sdk_c66xdsp_1_release.xe66”. On Cortex_M4_IPU1_C0, load the binary, “vision_sdk_ipu1_0_release.xem4”. On Cortex_M4_IPU1_C1, load the binary, “vision_sdk_ipu1_1_release.xem4”. On CortexA15_0, load the binary, "vision_sdk_a15_0_debug.xa15fg”. But there is something worng. I can see main() on DSP,and do start or set break point.CCS‘s screenshot was shown below: I cant start or set break point on M4,the porgram start automaticly., there is console message: Cortex_M4_IPU1_C0: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.4.0.00006) I want to set break point on M4 ,and start it from main(),what should i do?

Hi, It appears that IPU1_0 M4 has crashed. If you loaded the binaries from your build, there might be something wrong with them. Maybe build configurations were not set correctly. I suggest you to try again with pre-built binary first and see if it works correctly. You can download the binary from SDK download page. Regards, Stanley

Ticket Name: TDA2EG: System_linkControl_local/System_sendLinkCmd_local Issue

Part Number: TDA2EG Hi I am studying on the Link. In the "vision_sdk\links_fw\src\rtos\links_common\system\system_linkApi_local.c", the System_linkControl_local/System_sendLinkCmd_local are all implemented by mailbox. Here, "local" should means communication on the same processor, but according to the technical reference manual of TDA2, mailbox is designed for two processors communication. So why VSDK use mailbox to do the local communication? Thanks xuanbo

Hi xuanbo, This mail box is implemented using simple queue and semaphores, it does not use hardware mail box. For inter processor communication, it uses IPC. Regards, Brijesh

Hi Brijesh So the software mailbox is totally different with hardware mailbox. As a Link is a OS thread, could i treat the mailbox implemented with semaphore as the way to do the inner thread communication? By the way, where can i find the implement or definition code of mailbox in the VSDK? Thanks xuanbo

Queue related: Utils_mbxCreate function at "\vision_sdk\links_fw\src\rtos\utils_common\src\utils_mbx.c"; semaphores related: Utils_queCreate function at "vision_sdk\links_fw\src\rtos\utils_common\src\utils_que.c" right? Thanks xuanbo

xuanbo, Well, yes, utils_mbx.c uses queue and semaphores to implement mail/message box. Rgds, Brijesh

Hi xuanbo, Yes, it is different from hardware mailbox. Yes, it is used for inter-link communications.. Regards, Brijesh

Hi Brijesh OK, i got it, Thank you~ Regards xuanbo

Ticket Name: TDA4VM-Q1: bootmode for auto select primary boot device

Part Number: TDA4VM-Q1 Other Parts Discussed in Thread: TDA2 Hi : The TDA2 have the BOOTMODE。for example ,The first device is SD ,the second is EMMC ,it is convenient to use . however .The tda4 , I need to change bootmode every time for different primary boot device .(SD /EMMC ) So does the tda4 have the same bootmode function as the tda2.? and how to set the bootmode

Hi, On TDA4 as well there is a way to select secondary and primary boot mode with a single set of dip switches. So if ROM code is not able to find a valid bootloader from Primary boot media, it will attempt to boot from secondary boot mode. Now that being said, the options for primary boot mode are limited and Section 4.3.2.2 Backup Boot Mode Selection When MCU Only = 0 of the TRM lists them. From the table above, eMMC as backup boot mode is not supported however MMC/SD is. Regards Karan

thanks for your reply. so i understand i can not use a bootmode to achive my idea "the primary boot mode is MMC/SD, the second boot mode is EMMC " it must use a dip switches to change different bootmode . Regards kong

Hi Kong, xiangxu kong said: so i understand i can not use a bootmode to achive my idea "the primary boot mode is MMC/SD, the second boot mode is EMMC " That is correct. The SoC doesn't support booting from a backup boot media of eMMC boot partition. Regards Karan

Ticket Name: RTOS/TDA2: PROCESSOR_SDK_VISION_03_04_00_00 link error

Part Number: TDA2 Tool/software: TI-RTOS Hi, Recently found a problem with PROCESSOR VISION_SDK_V03_04 That is, in EVE_sw_01_19_00_00_00/apps_nonmam, I base on evelib_fir_filter_2d.c, add a few new eve programs, use eve_algo_dma_auto_incr.c It contains the following functions, and packaged into libeveapps.eve.lib EVELIB_getBestBlockDimensions, EVELIB_algoDMAAutoIncrInit, EVELIB_algoDMAAutoIncrDeInit, EVELIB_algoDMAAutoIncrConcurrent,EVELIB_algoDMAAutoIncrSequential, EVELIB_algoDMAAutoIncrProcess When you make, you find the following problem. It seems that libeveapps_opticalflow.eve.lib also includes these programs of the same name, and it does not have source code, but it is needed in the alg-_plugins algorithm. How can I solve it?! Now I just disable denseopticalflow all function .

Hi Casper, Dense optical flow is not release as part of EVE SW and it turns out that denseopticalflow library has same name for some of the functions which are used in apps_nonbam. If you are trying to link both the libraries together you will have this issue. Can you just rename the names of the function in any one of them so that there is no conflict. Regards, Anshu

Anshu, For short term solution , it's good suggest. But next EVE version , TI must corrected. Regards, Casper

Casper, The functions present in apps_nonbam folder are example functions and are there mostly for reference. Please refer other applets outside apps_nonbam folder to develop any new applets. These API's will not have conflicts with any existing applets. We don't have any plan to fix this in future. Regards, Anshu

I don't think so. This TI release SOP ? Our own function is base on this development. One a little bug still bug. IT's TI ? IT's TI? NO SOP ?

These Dense optical flow applet already conflicts with MY applets. These Dense optical flow applet already conflicts with MY applets.

These Dense optical flow applet already conflicts with MY applets.

Dear Casper, Thanks for identifying the behavior. Can you help me understand your usage: 1. Do you want to use dense optical flow library in your product? Please note that from TI it is delivered as a reference demo library from our partner network. If you are using it in your product, you should make sure that we get you in touch with that partner. 2a. If the answer to above question is yes, then while you work with the partner for productization of the library, you can also work on making sure that the symbols being used by dense optical flow library don't conflict 2b. If the answer to above question is NO, then I understand that the issue doesn't impact you now. Thanks, With Regards, Pramod

The conflicting program is placed in the EVE function library, and the library of the optical flow function uses the same name as the previous appnonbam. The correct method should use the original function instead of adding one. 2b. If the answer to above question is NO, then I understand that the issue doesn't impact you now. NO, But dense optical flow library impact my own applet. Please "NOTE" 2a and 2b you question is same "NOT IMPACT"

2A and 2B is same question.

TI expert, When you understand that this is wrong, not to fix this problem, but to dig a hole to solve, the next time you will be dig another hole. Is your TI SOP ? And TI demo source code just for demo , can't production and need to find tune or create our own algorithm and applet . I have question , how about TI SW release SOP ? For example , I use TI vision sdk 4 years. I found same place variable in each different version, have uppercase or lowercase issue. Why change ? I think, it's NOT need to change. It is depend on you programmer like or not. It is not right. It is my personal suggest and ask my own. By the way, may be other TI customer will as same question to you when them use app_nonbam. Casper Tu

Pramod, Please post your comments/questions on the same thread. Regards Karthik

Hi Caser, We will fix in DOF library the usage of symbols in upcoming SDK release. Thanks, With Regards, Pramod

Hi Casper, Processor SDK-Vision (aka Vision SDK) v3.06 addresses this issue www.ti.com/.../processor-sdk-tdax Thanks, With Regards, Pramod

Ticket Name: TDA2: Some issues about the usage of TIDL

Part Number: TDA2 Hello, I met some problems when using TIDL, 1. Convolution Layer 1.1 Can numGroups support from 1 to size of kernel(eg, kernel size is 3*3*32, numGroups can support from 1 to 32) ? 1.2 The dilation is the same thing to rate of atrous convolution? (eg, in the flowing case, dilation should be 1, 2, 4 ) 2 Spatial Pooling layer 2.1 In TIDL user guide, pooling can support with strideW 4, but in the spatial_pooling.cpp, strideW 4 is not supported. If I modify the cpp code to supporting strideW 4(similar to strideH), is it OK? 3 In tidl_ModelImport tool, it can generate the trace_dump file ,such as trace_dump_0_32x32.y. Then how can I get the similar file in TIDL(tidl_tb.c)? For I get the different result between tidl_ModelImport tool and TIDL, I want to do some checks. Thanks~

Hi, 1.1 TIDL can support numGroups from 1 to 32, but we did not tested with larger number of groups. 1.2 TIDL can support dilation values 1, 2, 4 2.1 Pooling can support with stride 4. Please try modifying the code though we did not tested, it should work. 3. Change #define ENABLE_TRACE_DUMP (0) to #define ENABLE_TRACE_DUMP (1) at line no 40 in tidl_alg.c file to dump traces from TIDL. Thanks, Praveen

Hi, Do you use the CCS in using TIDL?

Can I ask where do find the spatial_pooling.cpp file, is it in the PROCESSOR_SDK_VISION_03_04_00_00?

Hi, Source files will not be released as part of VISION SDK. For source file access you should get the source releases of each component from TI, for that please contact your local TI FAE. Thanks, Praveen

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi, We are having following queries for sensors/lenses with Vision SDK: Query 1: We understand from that Vision board only one sensor can be connected to TDA2x. We plan to use the Omnivision sensors / lenses to connect to Vision board. (Not using multides) Can you please confirm that capture link from VisionSDK would be able to capture video frame from camera connected to directly to VisionSDK ? Query 2: Has TI used IR camera for any of the test cases ? Do you see any compatibility issues in using IR camera sensor with VisionSDK, capture link ? Please provide your views. Thanks, Abhishek

Hi Abhishek, Q1: Yes. Vision SDK supports OV10635 camera module which is connected directly to TDA2 EVM. Q2: You can connect camera module with IR filter on TDA2. You can check out this DM demo with IR camera done by our 3rd party using Vision SDK. www.youtube.com/watch Regards, Stanley

Ticket Name: Linux/TDA2: what is OCMC memory?

Part Number: TDA2 Tool/software: Linux in VisionSDK_DevelopmentGuide.pdf tell me. Algorithm might need some memory for its operation, which is internal to the algorithm. This memory might be present in DDR / OCMC / L2. Such memory requests for the algorithm needs to be catered to in create plug in function. but what is OCMC memory?

Hi OCMC is an On Chip Memory Controller, its an internal memory accessible from all CPUs regards, Shiju

Hi :Shiju is there any DOC talk about OCMC? BESTWISHES SHUAI

Hi SHUAI sorry, what is DOC? regards, Shiju

Hi: Shiju document pdf， for exmample CorePac_guide talk about C66 core and memery! BESTWISHES SHUAI

Hi SHUAI please refer the TRM (technical reference Manuel) of the TDA device for all SoC related details regards, Shiju

Ticket Name: RTOS/TDA2: Can't find schematic of LVDS MCV board (6 channel FPD-Link III FMC SV600964 Daughter Board) .

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, We are tracing LVDS setting from VPS of SDK v3.3 and need LVDS MCV schematic to refer. HW is TDA2 + vision board + FMC SV600964 Daughter Board. But we can't find FMC SV600964 Daughter Board schematic. Could you please tell us how to get it? Thanks.

Hi Sir, Seem like below link. support.spectrumdigital.com/.../Schematic Prints.PDF Could you please confirm for us? Thanks.

Hi Prince, The schematics look correct. Regards, Rishabh

Ticket Name: TDA2SX: TDA2S USB related issues

Part Number: TDA2SX Hi，Ti We want to transplant ADB function in TDA2S. Does TDA2S support OTG? If supported, how do we need to modify the driver? Regards Kong

Hello Kong, What is the TI SDK being used for the TDA2S project you are using for the above query? Thanks.

Hi Praveen, The version we are using is V3.6. Thanks

Hello Kong, Thanks for the version, but was checking the SDK being used. Is it PROCESSOR-SDK-RADAR or PROCESSOR-SDK-VISION - We are assuming you are using PROCESSOR-SDK-VISION. Note that TDA2S does "not" support OTG, but it does support "dual-role" mode. Please note that "OTG" is an often misused term. By "OTG", if you meant the OTG protocols, such as HNP or SRP, those are not supported. But if you meant the "dual-role" mode, in which the USB port can work in either device mode or host mode based on the USB cable connection, this is supported. For more details, refer to chapter 23.6 in the TRM https://www.ti.com/lit/pdf/sprui29 Regarding ADB support, this is not supported in the PROCESSOR-SDK-VISION. Thanks.

Hello Praveen, We are using PROCESS SDK VISION.How should we set up the USB OTG interface and gadget driver in the kernel, in addition to setting dr_mode on the device tree. Thanks.

Hello Kong. Support of the USB "dual-role" is already enabled in the Linux kernel that is provided with PROCESS SDK VISION. The device tree's dr_mode = "otg" is sufficient for this. Thanks.

Ticket Name: TDA2SX: Is it impossible to boot from the SD card with NDK on Vayu board?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi, I am using vayu board with visionSDK2.8. On line 617 of the file C: \ VISION_SDK_ 02_ 08 _ 00 _ 00 \ vision_sdk \ Rules.make is written # When NDK is enabled, FATFS can not be used to to MMCSD conflict Dose it mean that it is impossible to boot from the SD card with NDK on Vayu board? Regards, Kenshow

Hi kenshow, Vision SDK experts have been notified to comment here. Thanks, Alex

Hello Kenshow, This only applies to TDA3xx due to pin mux conflicts for using port1. But if it is necessary on TDA3xx as well we can enable FATFS and NDK together with the help of daughter board. For TDA2/2ex you should be able to use both FATFS and NDK together.

Ticket Name: RTOS/TDA2: NDK 2_24_02_31 TCP slow start

Part Number: TDA2 Tool/software: TI-RTOS Hello everyone! We are wondering about slow start conditions, within the source file: VISION_SDK_02_12_01_00\ti_components\networking\ndk_2_24_02_31\packages\ti\ndk\stack\tcp\tcpout.c We have probably understood the meaning of the first slow start condition: pt->snd_una==pt->snd_max so, that means that the sequence number within the lastly sent TCP header (within the segment that is not acknowledged) is equal to the sequence number of the last segment of the current window. Please, correct me if I am not right about this. Another contition is the following: pt->t_tidle > (pt->t_trtx<<2) We are wondering about these tick counts: t_tidle and t_trtx, what exactly thay represent. We have observed the snd_cwnd value and it holds the maximum value (65535) during the whole time of the communication. After we had decreased the bandwidth on the router, we have noticed that snd_cwnd sometimes decreases. Also, we have added some prints within the slow start IF statement and we have not noticed any occurence of the true slow start condition. We hawe also noticed that this TCP does not perform the slow start at the beginning of the data transfer, but it immediately sets the maximum 16-bit window size. What would be the best way to trigger the slow start? Thanks in advance, Marko

Hello Marko, Kindly give us some time to come back on your issue. I have asked our NDK expert to comment, he will check possible issue and let you know. Sorry for the inconvenience.

Hi Marko, There are no configuration for the slow start mechanism in the stack. Unfortunately, we simply don't have the staff to go into the implementation details. If you are seeing an issue with the feature (from a black box perspective), please include a test case (with description). Todd

Thank you Todd, During the long testing time we have noticed that the slow start condition never gets satisfied, so we have suspected that there is some missfunction involving this mechanism. Nevertheless, after another couple of experiments, we have succeeded to trigger the slow start. We observed the cwnd value and indeed it gets set to one MSS, thus proving its functionality. Best regards, Marko Gostovic

Ticket Name: TDA2SX: Linux : How to increase TDA2 memory on f Dual OS (Linux & RTOS) from 1GB to 2GB ?

Part Number: TDA2SX Our system need more memory to do more algorithm, so our new platforms contain 2GB DDR memory. (M4 does not need to manage the memory area whose memory address is over 512MB) After reading the URL http://processors.wiki.ti.com/index.php/VSDK/VisionSDK_UserGuide_MemoryMap#Memory_Map_of_the_Application, our adjustments are still fail. Our testing code on EVE can access at 0xC0000000 ~ 0xD0000000 ( by modify "/vision_sdk/links_fw/src/rtos/bios_app_common/tda2xx/eve_common/tlb_config_eve_common.c" ) But the same testing code on DSP1/DSP2 cannot work. ( Note : the testing code is to access the memory address directly ) There are some error message about omap-iommu fault.... Could you help us ? Thank you very much. Regards, Eten

Hi, By default, DSP will have access to only those sections which are defined in the below memory map file. vision_sdk\apps\build\tdaxxx\mem_segment_definition_linux.xs So if you want to access a memory section beyond C0000000 then please add a dummy section in the above file so that it will automatically get accessed from DSP. For adding a new section please refer section 6.3 of the below doc vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_UserGuide_MemoryMap.pdf Regards, Gaviraju

Hi Gaviraju, It works. Thanks for your help. Regards, Eten

Ticket Name: TDA2: ABC package height after soldering

Part Number: TDA2 Hello, The customer would like to know the min/max height of TDA2 ABC package after soldering. They want to know exact thickness of TDA2 ABC to attach thermal pad. In TDA2 ABC data manual, min/max height is 2.62/2.96 and seating plane is 0.15. Hence, the min/max height after soldering TDA2 should be 2.47/2.81. correct? Thanks, Lloyd

The min/max height after soldering is 2.47 to 2.96. The logic is that the min height may be reduced by the maximum height of the seating plane (2.62-0.15) whereas the max height may be reduced by the minimum height of the seating plane (2.96-0). Regards, Kyle

Ticket Name: Linux/TDA2: Build first Linux set make –s –j have error

Part Number: TDA2 Tool/software: Linux Dear All, When I set make -s have this question how can solve? SDK: PROCESSOR_SDK_VISION_03_03_00_00_setuplinux 2742.Rules.make.txt # file name: Rules.make
# set up the build environment

ifeq ($(vision_sdk_PATH), )

#
# Application to build for
#
# Supported Applications are:
#	sample_app
#	apps

MAKEAPPNAME?=apps

#
# Config to use
#
# Selecting a config selects the system config and modules to include
# in the build
#
# Edit the detailed config in file
# $(vision_sdk_PATH)/$(MAKEAPPNAME)/configs/$(MAKECONFIG)/cfg.mk
#
# Supported "out of box" configs are listed below
# - TDA2x Configs,
#    tda2xx_evm_bios_all
#    tda2xx_evm_bios_opencx
#    tda2xx_evm_bios_radar
#    tda2xx_evm_linux_all
#    tda2xx_rvp_linux_all
#    tda2xx_evm_linux_infoadas
#    tda2xx_evm_linux_opencl
#    tda2xx_evm_linux_opencx
#    tda2xx_evm_robust_rvc
#
# - TDA3x Configs,
#    tda3xx_alps_bios_radar
#    tda3xx_evm_bios_all
#    tda3xx_evm_bios_radar
#    tda3xx_rvp_bios_all
#    tda3xx_evm_bios_iss
#    tda3xx_rvp_bios_iss
#
# - TDA2Ex Configs,
#    tda2ex_17x17_evm_linux_all
#    tda2ex_evm_bios_all
#    tda2ex_evm_linux_all
#    tda2ex_evm_linux_infoadas
#    tda2ex_evm_robust_rvc
#
# - TDA2Px Configs,
#    tda2px_evm_bios_all
#    tda2px_evm_bios_radar
#    tda2px_evm_linux_all
#    tda2px_evm_linux_infoadas
#    tda2px_evm_bios_iss
#
#
MAKECONFIG?=tda2xx_evm_linux_all

# Default build environment
# Options: Windows_NT or Linux
BUILD_OS ?= Linux
ifeq ($(OS),Windows_NT)
    BUILD_OS=Windows_NT
endif

#
# Set BUILD_MACHINE to 32BIT as required, this is needed only
# if A15_TARGET_OS is going to be Linux
#
# Options: 32BIT or 64BIT
BUILD_MACHINE ?= 64BIT

vision_sdk_RELPATH = vision_sdk
vision_sdk_PATH  := $(abspath ..)

# Application paths
$(MAKEAPPNAME)_PATH := $(vision_sdk_PATH)/$(MAKEAPPNAME)

include $($(MAKEAPPNAME)_PATH)/configs/defaults.mk
include $($(MAKEAPPNAME)_PATH)/configs/cfg.mk
include $($(MAKEAPPNAME)_PATH)/configs/autorules_header_cfg.mk
include $(vision_sdk_PATH)/build/tools_path.mk
include $($(MAKEAPPNAME)_PATH)/configs/autorules_footer_cfg.mk

endif

include $(MAKERULEDIR)/build_config.mk
include $(MAKERULEDIR)/platform.mk
include $(MAKERULEDIR)/env.mk
include $(MAKERULEDIR)/component.mk

export MAKEAPPNAME
export $(MAKEAPPNAME)_PATH
export MAKECONFIG

refer linux user guide 2.4.2.1.4 File system patch for Vision SDK Copy “install-extra.tar.gz” from $INSTALL_DIR/ti_components/os_tools/linux/kernel/linux-kernel-addon/fs-patches into $ INSTALL_DIR/ti_components/os_tools/linux/targetfs and untar tar –xvzf install-extra.tar.gz

Hi Owen, thanks for updating the thread. Regards, Yordan

Ticket Name: Linux/TDA2: pass buffer_site for A15 to c66

Part Number: TDA2 Tool/software: Linux now i am VISION_03_04_00_00 char * model_fr = (char*)OSA_memAllocSR(OSA_HEAPID_DDR_CACHED_SR1, length_fr, 32); i read model file to model_fr buffer in a15 , it will use by C66 , so have can i send the model_frto C66 dsp ？ how can i pass the physical pointer of this buffer to DSP as an Alg link (on DSP) create time parameter? i am run SDK_VISION_03_04_00_00\vision_sdk\sample_app\src\hlos\usecases\nullSrc_display , could you please illustrate how to add code take this usecase as an example . Shuai

Hi, You can send any structure to any link from A15 from your usecase using System_linkControl api with a command to a link provided that link supports that command. You can also provide your model_fr to a link in its create param, provided that links create param has that member to take model. Regards, Anuj

Hi Anuj in sample_app\src\hlos\usecases\nullSrc_display\Chains_nullSrc_display this file get mem and read model then char * model_fr = (char*)OSA_memAllocSR(OSA_HEAPID_DDR_CACHED_SR1, length_fr, 32); gUcObj.Alg_FrameCopyPrm.mybuf = (void*)model_fr; i print model_fr bufsite and model data here is right. in sample_app\src\rtos\alg_plugins\framecopy\frameCopyAlgoLocalDma.c Alg_FrameCopyCreate i get the bufsite is the same, but model_data is 0 is wrong. float *model_fr = (float *)pCreateParams->mybuf; Vps_printf("rtos_model_frsite=%x,model_fr_0=%f,model_fr_1=%f \n", model_fr,model_fr[0], model_fr[1]); i donot know why ?

Hi, Its because you are allocating the buffer from A15 which runs linux and has a virtual memory but DSP uses physical memory. So you need to get the physical address of that buffer and pass that DSP. You can use something like below buffer.payload = (void *) OSA_memVirt2Phys((UInt32)buffer.payload, OSA_MEM_REGION_TYPE_SR1); Regards, Anuj

HI: Anuj char * model_fr = (char*)OSA_memAllocSR(OSA_HEAPID_DDR_CACHED_SR1, length_fr, 32); fread(model_fr, sizeof(char), length_fr, fp_fr); gUcObj.Alg_FrameCopyPrm.mybuf = (void*)OSA_memVirt2Phys((UInt32)model_fr ,OSA_HEAPID_DDR_CACHED_SR1); you mean like this ? Regards, SHUAI

HI: Anuj its right now! thanks SHUAI

Ticket Name: Linux/TDA2: PCI configuration for TDA2x

Part Number: TDA2 Tool/software: Linux Hi, I want to know about how the PCI lines of TDA2x can be configured in linux? I have a custom board developed based on TDA2x. I have to configure PCI as two 1X1 pci .How the configurations can be done in linux?

Hi Sreerag, can you check those documents and see if they can give you some directions: processors.wiki.ti.com/.../Linux_Core_PCIe_EP_User's_Guide processors.wiki.ti.com/.../PCIe_Debugging Regards, Yordan

Hi Sreerag, I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Ticket Name: TDA2EXEVM: QSPI usage

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi, I am using TDA2Ex SoC. As mentioned in TRM, there are two QSPI parts: QSPI_ADDRSP0 (Config port) and QSPI_ADDRSP1(memeory mapped port). My understanding is QSPI_ADDRSP0 can be used to configure, write to flash. but I am unable to understand the use of QSPI_ADDRSP1. How does it help memory mapping, etc. Looking forward for the response. Thanks in advance, Priyanka Zadge

Hi Priyanka, QSPI_ADDRSP1 allows to view a QSPI flash contents in a CPU address space similarly to NAND or NOR flash memories. This address space is located at: QSPI_ADDRSP1 | 0x5C00_0000-0x5FFF_FFFF | 64 MiB | QSPI CS0/CS1/CS2/CS3 space (Maddrspace 1) I don't have much experience with that though. Regards, Stan

Hi Stan, [QSPI_ADDRSP1 allows to view a QSPI flash contents in a CPU address space similarly to NAND or NOR flash memories.]: meaning, this part of QSPI is useful to see the contents of external flash only, correct? Regards, Priyanka

Yes, but QSPI is most useful with flash memories. If you need SPI as a control interface, better option is the MCSPI peripherals of TDA2. Regards, Stan

Hi Priyanka, In additional to what Stan said QSPI can operate in two modes: Memory mapped Mode and Config mode. QSPI_ADDRSP0 is used while operating in config mode and QSPI_ADDRSP1 in memory mapped mode. Memory mapped mode allows user to read QSPI as a flat memory similar to DDR/OCMC. You can search for SOC_QSPI_ADDRSP1_BASE and SOC_QSPI_ADDRSP0_BASE in <pdk>\packages\ti\boot\ folder to see how both spaces are used. Regards, Rishabh

Ticket Name: TDA2: where can i get vsdk_win64

Part Number: TDA2 I'm trying to generate usecase by using generator I installed the lastest version of vision sdk(ver3.30) though, I can't find vsdk_win64.exe The only thing I can find is vsdk_win32.exe, and it does not compitible with my OS... where can i get vsdk_win64.exe ?

Hi Habit, You may refer below post. Currently vsdk_win64.exe is not included in the SDK, but you can build it from source code on your own. Below I attached mine for your convenience. I built it on my own using Cygwin. vsdk_win64_v3.3.zip (Update) Somehow the exe generated by cygwin can not recognize Windows' path. JPG won't be generated because "dot.exe" (included in graphvz) can not be called. The solution is to input "dot -Tjpg xxx_img.txt -o xxx.jpg" to generate JPG manually.

Thanks a lot (quick answer also)

Ticket Name: Linux/TDA2: Vision SDK 3.04 framework and examples build fail

Part Number: TDA2 Other Parts Discussed in Thread: SYSCONFIG Tool/software: Linux Hi, I got similar error while executing build command for SDK. command: make -s Error: dispDistSrcLink_tsk.c:81:45: fatal error: vdrm_controller/v_controller_if.h: No such file or directory compilation terminated. make[6]: *** [depend] Error 1 make[5]: *** [links_a15_dispDistSrc] Error 2 make[4]: *** [vision_sdk_linux_lib] Error 2 make[3]: *** [links_fw_libs_hlos] Error 2 make[2]: *** [apps_hlos] Error 2 make[1]: *** [apps] Error 2 make: *** [vision_sdk] Error 2 I checked git commit also for kernel, u-boot, sgx u-boot: 839f3f2 (HEAD, origin/ti_2.12_release, ti_2.12_release) updated library and binaries added 2e3691d debug renamed to debug 35e203d Makefile and header files added 002bee1 itsapp.mk added d9bc44b nwmanager initial version added 6619725 Debug renamed to debug , and Ipc renamed to ipc 34b4ac8 Debug renamed to debug , and Ipc renamed to ipc 21d98c8 controlapp initial version version added fad591e json,ffmpeg Dependency added 764c7cb its directory added in rootfs file sytsem 3713f24 itsapp new directory added cd424bd makefile renamed to datalogger.mk de8a247 its renamed to datalogger in rootfs 003ce5f . 429efbf read failed error fixed for wifi_reader Kernel: 839f3f2 (HEAD, origin/ti_2.12_release, ti_2.12_release) updated library and binaries added 2e3691d debug renamed to debug 35e203d Makefile and header files added 002bee1 itsapp.mk added d9bc44b nwmanager initial version added 6619725 Debug renamed to debug , and Ipc renamed to ipc 34b4ac8 Debug renamed to debug , and Ipc renamed to ipc 21d98c8 controlapp initial version version added fad591e json,ffmpeg Dependency added 764c7cb its directory added in rootfs file sytsem 3713f24 itsapp new directory added cd424bd makefile renamed to datalogger.mk de8a247 its renamed to datalogger in rootfs SGX: fd47e44 (HEAD, origin/ti-img-sgx/1.14.3699939/k4.4, sgx_dev) Revert "km: build: remove dependency on user-mode builds" 8d5305b km: remove update of sysconfig register in driver bc31285 km: fix error in calculating size of page array e68719b km: build: remove dependency on user-mode builds a5a0fe1 km: Resolve Linux build warnings c13efb7 km: disable active power management c8d280c km : use CONFIG_ZONE_DMA for LPAE 106ddd5 km: use platform specific reset APIs only for AM3/AM4 platform fed0756 (origin/ti-img-sgx/1.14.3699939/k4.1) KM: Make kernel configuration variable SUPPORT_LISR_MISR_SYNC conditional 3d5e9c9 KM: Enhance OMAP-based platform code to support AM3/4/5 devices 2d4a2cf KM: Invoke platform-specific reset API calls if available Is all source code have old version/tags?? Have i taken any wrong process? Please help to solve my problem? Thanks, Anand Kumar

Hi Anand, from the git log it seems that your kernel and u-boot are old versions (SGX seems to be on the right commit). Which version is you VisionSDK? Can you look at chapter "2.4.2 Install Linux Components" in VisionSDK_Linux_UserGuide.pdf how to clone and checkout the right tag of u-boot and kernel. Regards, Yordan

Hi Yordan, i am using Vision SDK_03_04. Now, i changed to updated kernel version with help of UserGuide pdf file. Now, It is compiling successfully. Thanks, Anand Kumar

Ticket Name: Compiler/TDA2PXEVM: Error while installing and building Vision SDK

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi, While installing the vision sdk in the Ubuntu 16.04 PC, I got following error. Please suggest what is the step that I have missed. error: symbol "HSMMCSDEdmaTransfer" redefined: first defined in "/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2 px_evm_linux_all/lib/tda2px-evm/ipu2/release/utils_common.aem4<file_api_dma. oem4>"; redefined in "/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/ti_components/drivers/pdk_01_ 10_03_07/packages/ti/drv/vps/lib/tda2px-evm/m4/release/vps_examples_utility. aem4<bsputils_fileio.oem4>" error: symbol "HSMMCSDEdmaClose" redefined: first defined in "/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2 px_evm_linux_all/lib/tda2px-evm/ipu2/release/utils_common.aem4<file_api_dma. oem4>"; redefined in "/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/ti_components/drivers/pdk_01_ 10_03_07/packages/ti/drv/vps/lib/tda2px-evm/m4/release/vps_examples_utility. aem4<bsputils_fileio.oem4>" error: symbol "HSMMCSDUARTPutNum" redefined: first defined in "/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2 px_evm_linux_all/lib/tda2px-evm/ipu2/release/utils_common.aem4<file_api_dma. oem4>"; redefined in "/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/ti_components/drivers/pdk_01_ 10_03_07/packages/ti/drv/vps/lib/tda2px-evm/m4/release/vps_examples_utility. aem4<bsputils_fileio.oem4>" error: symbol "HSMMCSDUartPuts" redefined: first defined in "/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2 px_evm_linux_all/lib/tda2px-evm/ipu2/release/utils_common.aem4<file_api_dma. oem4>"; redefined in "/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/ti_components/drivers/pdk_01_ 10_03_07/packages/ti/drv/vps/lib/tda2px-evm/m4/release/vps_examples_utility. aem4<bsputils_fileio.oem4>" error: symbol "HSMMCSDEdmaWaitTransfer" redefined: first defined in "/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2 px_evm_linux_all/lib/tda2px-evm/ipu2/release/utils_common.aem4<file_api_dma. oem4>"; redefined in "/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/ti_components/drivers/pdk_01_ 10_03_07/packages/ti/drv/vps/lib/tda2px-evm/m4/release/vps_examples_utility. aem4<bsputils_fileio.oem4>" # # /home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2px_evm_linux_all/vision_sdk/bin/tda2px-evm/vision_sdk_ipu1_0_release.xem4 created. # error: errors encountered during linking; "/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2 px_evm_linux_all/vision_sdk/bin/tda2px-evm/vision_sdk_ipu2_release.xem4" not built /home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/build/rtos/makerules/rules_m4.mk:312: recipe for target '/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2px_evm_linux_all/vision_sdk/bin/tda2px-evm/vision_sdk_ipu2_release.xem4' failed make[7]: *** [/home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2px_evm_linux_all/vision_sdk/bin/tda2px-evm/vision_sdk_ipu2_release.xem4] Error 1 /home/teuser/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/build/rtos/makerules/common.mk:271: recipe for target 'ipu2' failed make[6]: *** [ipu2] Error 2 MAKEFILE.MK:162: recipe for target 'apps_ipu2' failed make[5]: *** [apps_ipu2] Error 2 MAKEFILE.MK:31: recipe for target 'apps' failed make[4]: *** [apps] Error 2 MAKEFILE.MK:314: recipe for target 'apps' failed make[3]: *** [apps] Error 2 Makefile:175: recipe for target 'apps_exe' failed make[2]: *** [apps_exe] Error 2 Makefile:38: recipe for target 'apps' failed make[1]: *** [apps] Error 2 Makefile:12: recipe for target 'vision_sdk' failed make: *** [vision_sdk] Error 2

Hi Revathi, do you have any modifications in the SDK? Can you try clean build: make clean make linux_clean make linux make linux_install make -s -j depend make -s -j Regards, Yordan

Ticket Name: Porting application code from TDA2x to TDA3x

Other Parts Discussed in Thread: MATHLIB, TDA2 Hi, I am working on porting the application from tda2x to tda3x. Currently the application runs fine on tda2x.The application uses bios,xdc,ipc,bsp,edma,ivahd,eve,vlib,mathlib packages from vision sdk. On tda2 physical master is a15 that launches the secondary bootloader.The sbl will load and start the code from m4. On tda3 what will be the scenario since tda3 does not support a15. a) How the secondary bootloader launches on TDA3x b)Is it fine to port the software modules running on a15 in TDA2 on m4 in TDA3x. c)Does disabling a15 support from whole application,compiling the ti packages with TDA3 and then generating the application image is right procedure. d)How should i proceed for porting application from tda2x to tda3x. Regards Mayank

a - secondary bootloader is launched from M4 on TDA3x b - Yes it is fine, which peripherals / subsystems are these modules on A15 working on? It also depends on that. You need to see if you have driver on M4 + bios for the same. c- Yes, in vision_sdk when you select platfor as TDA3XX_EVM in Rules.make, this happens automatically. d - Please give details of your usecase and peripherals you are using on TDA2X so we can discuss further.

Hi Yogesh, Kindly can you guide me, where can I find source code for vision sdk for TDA3x ? What I got is http://software-dl.ti.com/processor-sdk-vision/esd/TDAx/latest/index_FDS.html, but it only contains the prebuilt binaries. I do have NDA and license for CCS. Regards, Waleed

Ticket Name: TDA2: Running a model on multiple cores

Part Number: TDA2 Need more clarification on this: From Previous Conversation: Yes, we can do that by assigning unique layersGroupId for each of the cores, let's say 1 for EVE1, 2 for EVE2, 3 for EVE3 and 4 for DSP. Note that this layersGroupIds 1 for EVE and 2 for DSP is just an example, you can assign any unique layersGroupId and same mapping should used in running inference. Query: How to map it? Where i need to define it 1 for EVE1, 2 for EVE2, 3 for EVE3, 4 for EVE4, 5 for DSP1 and 6 for DSP2. Regards, Sagar

Hi Sagar, We had explained about this in the user guide of TIDL latest release (REL.TIDL.01.01.01.00). Refer to FAQ 21 and 22 in the user guide, where the example considered only two cores but it can be applicable to any number of cores. Thanks, Praveen

No. It is not explained in the UserGuide, not the case which i am referring. I am quoting your reply from previous conversation https://e2e.ti.com/support/arm/automotive_processors/f/1021/t/685827 : "Yes, we can do that by assigning unique layersGroupId for each of the cores, let's say 1 for EVE1, 2 for EVE2, 3 for EVE3 and 4 for DSP. Note that this layersGroupIds 1 for EVE and 2 for DSP is just an example, you can assign any unique layersGroupId and same mapping should used in running inference." Please Consider following Example (first few layers on EVE1 and next few layers on EVE2 and last layer on DSP1): Layer 1 : EVE1 Layer 2: EVE1 Layer 3: EVE2 Layer 4: EVE2 Layer 5: DSP So, while importing this model I will update import config file layersGroupId = 1 1 2 2 4 Is this right ? How 4 will be identified as to use DSP. Because, in the current version of TIDL layersGroupId 1 means EVE and layersGroupId 2 means DSP. Regards, Sagar

>> So, while importing this model I will update import config file >> layersGroupId = 1 1 2 2 4 >> Is this right ? Yes. This is right. >> How 4 will be identified as to use DSP. Because, in the current version of TIDL layersGroupId 1 means EVE and layersGroupId 2 means DSP This is not correct, that is just an example. We need to mention in infer config as below to run on EVE1, EVE2 and DSP to run above configuration, 1. Set layersGroupId = 1, runFullNet = 0 in the infer config file for EVE1, this will execute only layer1 and layer2 on this core. 2. Set layersGroupId = 2, runFullNet = 0 in the infer config file for EVE2, this will execute only layer3 and layer4 on this core. 3. Set layersGroupId = 4, runFullNet = 0 in the infer config file for DSP, this will execute only layer5 on this core. So, this layersGroupId is just a number to map between import and inference. So, number used in import for specific layers will run together on that specified core. Thanks, Praveen

Ticket Name: BEAGLE-3P-BBONE-AI: BEAGLE-3P-BBONE-AI,Processor Name :AM5729

Part Number: BEAGLE-3P-BBONE-AI AM5729 I am working with Beaglebone AI, which has its CLOUD 9 IDE, and the software tool is TIDL with OpenCL and c++ wrappers. My question is - In the neural network models implemented using TIDL, How do measure the host and co-processor runtime/execution time separately? Using what concept? In general OpenCL code like vecadd (vector addition) , I was able to make used profiling events to measure the runtime, but I have no idea how to do the same with imagenet or ssd_multibx codes. Please help...

Hi Kavya, checking inside Linux PSDK filesystem /usr/share/ti/tidl/ I see there are some TImeStamps, and a GetProcessTimeMiliSeconds() functions in utils.cpp. I haven't personally use them, but I see there is a test TIDL example which use ReportTime(). Please take a look as probably you could use them for your purpose. thank you, Paula

As you can see in the figure, I couldn't find the utils.cpp file in tidl folder. How do I get the Linux PSDK file system, by the way, I am using Windows OS should I shift to LINUX OS?

Hi Kavya, I gave you the upper level folder, utils.cpp is actually inside tidl_api/src/ thank you, Paula

Yes i understand, but the src folder under tidl_Api itself doesnt exit..

Hi Kavya, I am not familiar with Debian image for BBAI. One option is to get Linux PSDK image/SDK from below link (at least as a reference): http://software-dl.ti.com/processor-sdk-linux/esd/AM57X/latest/index_FDS.html hope this helps, Paula

Thank You.

Ticket Name: TDA2: fish eye lens holder for SV demo

Part Number: TDA2 Dear Champs, Could you please let me know exact lens holder part name we used in our SV DEMO of Vision SDK? From the web site of DSL219D, there were 2 holders recommended to use with DSL219D lens as below and these holders have different size. do you think any holders in below can show similar DEMO quality? Thanks and Best Regards, SI.

Hi SI, It seems like the second part number is a recent addition, I am trying to check on this. I will reply as soon as its clarified. Regards, Sujith

Hi Sujith, Have you checked this? Thanks and Best Regards, SI.

Can you please give more details of the demo setup you are using? SoC name Sensor name Camera module version It will help if you can attach a picture.

They are using our SV DEMO on TDA2 using TDA2 EVM as below. SoC name : Vision28 CPU EVM and Vision Apps Board Sensor name : omnivision image sensor board(Multides Surround View Kit, OV10635-EAAE-AA0A) Camera module version : OV10635-EAAE-AA0A www.spectrumdigital.com/.../ Thanks and Best Regards, SI.

This is a Spectrum Digital product. Please contact Spectrum Digital.

Hi, I'm asking about DEMO configuration in VisionSDK, not about product. which lens holder have been used in SV DEMO of VisionSDK? I believe all other configurations should be same in the DEMO described in the VisionSDK, but there was no information about Lens holder. Thanks and Best Regards, SI.

Lens holder is not a part of Vision SDK. This is a part of the camera module sold by Spectrum Digital.

Do you mean Lens holder will not be impact on the DEMO quality? Thanks and Best Regards, SI.

Please contact Spectrum Digital for lens holder details.

Ticket Name: TDA2: EVM footprint library file

Part Number: TDA2 Could TI share with me the EVM footprint library file to ease my development with time saving by re-use the footprint?

Hi, You can find EVM's Design files (PCB drawings, assembly drawing, schematic, etc.) here: www.ti.com/.../tda2evm5777 Regards, Yordan

Ticket Name: TDA2EVM5777: I want to use Qt on TDA2EVM5777, what should I do?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi， I want to use Qt on TDA2EVM5777 because of project needs, what should I do? I have read other posts and said that it is possible to use ti-processor-sdk-linux-am57xx-evm, how do I deploy it on my board？ Thank you.

Leon, The full fledged filesystem supports Qt on the TDA2. Have you read through the User Guide to understand how to generate the full filesystem? Could you please give me more details on the difficulty and also let us know which release you are using? Regards Karthik

Karthik， The development environment I use is ti-processor-sdk-linux-am57xx-evm-06.02.00.81. But I did not find a user guide on how to generate a complete file system for TDA2. Can you provide links to related materials? Thank you

Hi Leon, Ok, are you using a TI EVM or your own custom board? If its TI EVM which EVM are you using? If you are using the TI EVM then there are different starting points depending on the board you have - can you please answer the above question so that I can guide you further. Regards Karthik

Hi Karthik, The hardware I use is TI evm, not customized, specifically TDA2x Vision EVM Kit.（www.ti.com/.../TDA2EVM5777） I think I found the information I needed on the TI website: Processor SDK Linux Automotive Software Developers Guide. I want to confirm that these two are compatible? Thank you

Leon, Thanks for confirming and I think from your description it seems like you have found the right material. Try it out and let us know if you have further questions. Regards Karthik

Ticket Name: TDA2: CDDS link about TIDL ON TDA2X

Part Number: TDA2 hi, I could not open the link "cdds.ext.ti.com/.../emxNavigator.jsp 30602.25095 " from the user guide paper, could you please send the CDDS link to me? Or could you please send me the video to my email 530294114@qq.com? I want to bring up the tda2x board with the TIDL. Looking forward to your reply! BR

Hi, TIDL Object release is part of TI’s processor software development (SDK) for vision. You can download this from below link, www.ti.com/.../PROCESSOR-SDK-TDAX In the vision SDK, you’ll find TIDL with documents at \ti_components\algorithms\. Source release of TIDL is available as standalone release via CDDS. Please work with your local TI representative to get access to the same. Thanks, Praveen

Ticket Name: CCS/TDA3LA: Software/tools required to develop radar software

Part Number: TDA3LA Other Parts Discussed in Thread: TDA2, AWR1243 Tool/software: Code Composer Studio Dear experts! I recently joined new automotive radar project in which we are trying to use AWR1243 + TDA2/TDA3. Because I'm not still familiar with TI's MCU series, I would like to ask you some simple question. To develope the software of radar using AWR 1243+TDAx, which softwares and tools are required. I mean to develop the software, we need to compile source codes, write a binary onto MCU and debug them. So we might need a compiler and tools, etc. for example, "code composer" and "Trace32". Could you anyone list up which softwares and tools are required to develop the radar software for TI radar? We need to prepare a budget for the new project and our project is the radar

Hello coolguy , For the compiler and debugger tool certainly use the Code Coposer Studio, free download here: processors.wiki.ti.com/.../Download_CCS For the binary that you need to compile, there is entire Radar (and Vision) SDK with use cases, documentation, examples, and lots of help in this forum, free download: www.ti.com/.../processor-sdk-vision Start from there, study the docs and come back for help if you need any. Hope it helps Thanks, Alex

Thanks for the answer. Then, how can a TI radar system be connected to a PC with the code composer installed? USB? UART?, etc.?

coolguy , You will need a JTAG for that. For TDA3x connection you can use various Blackhawk, Spectrum Digital, and TI XDS emulators. Thanks, Alex

Thank Alex. Sorry for bothering you. It might be a dumb question to you, but could you let me which one among 4 (Blackhawk, Spectrum Digital, and TI XDS emulators) is the best from your perspective?

Hello, Not a dumb question at all actually. You need to define what's best for you. Is it if it's cheap and supported, or is it if it more expensive but faster and with additional features? It all depends. For complex projects, it's always good to have a couple different ones to cross-check drifts in the results. I personally use the Blackhawk, it fast enough for me and well supported, never had issues with it. See more comments on the topic from the community over at the CCS forum: Hope it helps, Alex

Thanks for your answer. All my wonder cleared.

Ticket Name: Linux: gst-launch-1.0 filesrc location=testvideo.mpg ! tsdemux ! video/x-h264 ! h264parse ! avdec_h264 ! autovideosink sync=false

Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hello, I want to play *.mpg video file on TDA2, I'm using gstreamer now, I don't know how to write pipeline, Can you ask next, thank! Below is the pipeline I tried to play, but it doesn't work properly. ********************************************************************************************************************************** root@dra7xx-evm:/opt/vision_sdk# gst-launch-1.0 filesrc location=testvideo.mpg ! tsdemux ! video/x-h264 ! h264parse ! avdec_h264 ! autovideosink sync=false Setting pipeline to PAUSED ... Pipeline is PREROLLING ... ERROR: from element /GstPipeline:pipeline0/GstTSDemux:tsdemux0: Internal data stream error. Additional debug info: ../../../git/gst/mpegtsdemux/mpegtsbase.c(1347): mpegts_base_loop (): /GstPipeline:pipeline0/GstTSDemux:tsdemux0: stream stopped, reason error ERROR: pipeline doesn't want to preroll. Setting pipeline to NULL ... Freeing pipeline ... root@dra7xx-evm:/opt/vision_sdk# root@dra7xx-evm:/opt/vision_sdk#

Hi What is the vision-sdk version used? VISION_SDK v3.06 has support for video playback and display on waylandsink . What you are trying is an explicit pipeline and you need to know the format of the stream(h264, mpeg4 mpeg2, vc1 etc). Using playbin to playback will choose the correct parser and decoder. You can try gst-launch-1.0 playbin uri=file:///home/root/testvideo.mp4 video-sink=waylandsink or gst-play-1.0 --videosink waylandsink testvideo.mp4 will work. This will choose hardware based decoder instead of software decoders(avdec). Thanks Ramprasad

Ticket Name: TDA3XEVM: Need help on using L3 firewall to protect memory between M4 cores.

Part Number: TDA3XEVM Hi, We are using TDA3X SOC. Needed help regarding L3 firewall. We are running task on both M4 core's, IPU_C0 and IPU_C1. We have a requirement where the task running on IPU_C1 should not access IPU_C0 memory buffers. We have memory buffer of 40MB allocated on IPU_C0 which should not be accessed by IPU_C1. The solution to this as per technical reference manual is L3 firewall. So as per L3 firewall we can protect certain memory of IPU core which cannot be accessed by other IPU core. I also looked into l3fw_app.c example code in vision SDK which protects SOC_OCMC_RAM1_BASE memory from being accessed by other M4 core. In the example the module instance is being given as L3FW_OCMC_RAM1_INST and target address is SOC_OCMC_RAM1_BASE. So I had few confusion as below, 1) Does L3 firewall works for IPU only on OCMC RAM. 2) Can I create L3 firewall for 40MB of buffer which should not be accessed by other M4 core. 3) As per memory map of TDA3x TRM says IPU_RAM 0x5882_0000 to 0x5882_0000 64KB of RAM, can we access only this RAM ?. What is the significance of this RAM. 4) Technical reference manual says IPU MMU has 32 entries, does this mean IPU cores can access only 32 entries(pages) of the DDR ? Best Regards, A G Megharaj.

Hi Megharaj, Please find answers to your questions as: No, you can use other L3 firewalls for IPU, through which you can protect other regions on L3 space. Please refer to L3 Firewall chapter in TDa3x TRM for more details. Differentiating/protecting accesses between M4 cores through Firewalls is not possible. This is an internal memory of IPUSS which has faster accesses as compared to other memories in the system. You can access any memory in the system through MMU pages but you can configure such 32 pages only. If you are programming all 32 pages for DDR access, then answer to your question is yes, you can access only 32 pages of DDR. But you won't able to access any other memory in the system in this case since all accesses are going through MMU. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi Vivek Dhande, Thank you very much for the quick response. Just needed few clarification, 1)As per safety manual document section 4.17.3 Memory isolation on cortex M4, show one possible implementation of memory isolation for multiple tasks running on the Cortex-M4. * Define memory regions in external memory using L3 firewalls * Firewalls are reconfigured to QM mode in the following cases: QM tasks entry * Firewalls are reconfigured to ASIL mode in the following cases: QM tasks exit * Perform cache flush at entry of the QM task to remove cache entries from previous permission * Require task synchronization between both the cores; ASIL task is in one core, and the other core cannot run QM task Attaching the image as described in the document. 2) Also in the safety features manual says In case of M4, FFI between ASIL/QM can only be achieved by switching MMU tables at task-switch boundaries. So as per the above information only way to achieve FFI between M4 cores is throuh ASIL/QM task switch ? Can you please point to any examples if possible. Best Regards, A G Megharaj

Hi Megharaj, Please find answers to your questions as: Yes, that is correct. But note that these are tasks running on the same core. One M4 core cannot run the ASIL task while the other is running the QM task within the same IPUSS at the same time. Yes, it is correct. We can achieve FFI on IPU through switching MMU tables for ASIL and QM tasks as mentioned. Example for demonstrating FFI - ASIL and QM tasks is currently not available in SDK but you can refer following the link for more details about achieving FFI on IPU: http://www.ti.com/lit/an/sprac41/sprac41.pdf But, the example demonstrating FFI within DSP and A15/M4 cores is available in the SDK. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Ticket Name: CCS/TDA2: How to configure for EDMA_UTILS_TRANSFER_OUT

Part Number: TDA2 Tool/software: Code Composer Studio EDMA_UTILS_autoIncrement_initParam_v2 initParamV2; i configure for EDMA_UTILS_TRANSFER_IN and EDMA_UTILS_TRANSFER_INOUT is work, this time for EDMA_UTILS_TRANSFER_OUT status=0 but it dosenot work , No data is copied to extmem. initParamV2.initParams.numInTransfers = 0; initParamV2.initParams.numOutTransfers = 1; //parameters for ping transfer from external to internal memory and vice versa initParamV2.initParams.transferType = EDMA_UTILS_TRANSFER_OUT; //parameters for in transfer - ping //initParamV2.initParams.transferProp[0].roiWidth = width * 2; //initParamV2.initParams.transferProp[0].roiHeight = height*channels; //initParamV2.initParams.transferProp[0].roiOffset = 0; //initParamV2.initParams.transferProp[0].blkWidth = width * 2; //initParamV2.initParams.transferProp[0].blkHeight = height; //initParamV2.initParams.transferProp[0].blkOffset = 0; //initParamV2.initParams.transferProp[0].extBlkIncrementX = 0; //initParamV2.initParams.transferProp[0].extBlkIncrementY = height; //initParamV2.initParams.transferProp[0].intBlkIncrementX = 0; //initParamV2.initParams.transferProp[0].intBlkIncrementY = 0; //initParamV2.initParams.transferProp[0].extMemPtrStride = width * 4; //initParamV2.initParams.transferProp[0].interMemPtrStride = blkWidth * 4; //initParamV2.initParams.transferProp[0].extMemPtr = (uint8_t *)(inBufExt); //initParamV2.initParams.transferProp[0].interMemPtr = (uint8_t *)(inBufInt[0]); //initParamV2.initParams.transferProp[0].dmaQueNo = 0; //parameters for out transfer - ping initParamV2.initParams.transferProp[1].roiWidth = width * 2; initParamV2.initParams.transferProp[1].roiHeight = height * channels; initParamV2.initParams.transferProp[1].roiOffset = 0; initParamV2.initParams.transferProp[1].blkWidth = width * 2; initParamV2.initParams.transferProp[1].blkHeight = height; initParamV2.initParams.transferProp[1].blkOffset = 0; initParamV2.initParams.transferProp[1].extBlkIncrementX = 0; initParamV2.initParams.transferProp[1].extBlkIncrementY = height; initParamV2.initParams.transferProp[1].intBlkIncrementX = 0; initParamV2.initParams.transferProp[1].intBlkIncrementY = 0; initParamV2.initParams.transferProp[1].extMemPtrStride = width * 2; initParamV2.initParams.transferProp[1].interMemPtrStride = width * 2; initParamV2.initParams.transferProp[1].extMemPtr = (uint8_t *)(outBufExt); initParamV2.initParams.transferProp[1].interMemPtr = (uint8_t *)(outBufInt[0]); initParamV2.initParams.transferProp[1].dmaQueNo = 1; //configure EDMA for ping set both Ext -> Int and Int -> Ext EDMA_UTILS_autoIncrement_init_v2(dmaAutoContextInOut, &initParamV2); status = EDMA_UTILS_autoIncrement_configure_v2(dmaAutoContextInOut, EDMA_UTILS_TRANSFER_OUT);

Hi, Which software package you are using and which version? Regards, Prasad

Hi Shuai, When you configured OUT have you already configure IN channels? Regards, Anshu

Hi: Anshu its like this ! if in _fun1 no EDMA_UTILS_globalReset(); then call fun1 6times dmaQue is over, so i must add EDMA_UTILS_globalReset in fun1 ,but this will break dmaAutoContextOut. fun1( out,indata) { EDMA_UTILS_globalReset(); ////////////// EDMA_UTILS_autoIncrement_triggerInChannel_v2(dmaAutoContextInOut); for (j= 0; j < 16; j++) { fun2( out,indata_in[bufIdx ]); EDMA_UTILS_autoIncrement_waitInChannel_v2(dmaAutoContextIn); EDMA_UTILS_autoIncrement_triggerInChannel_v2(dmaAutoContextIn); bufIdx ^= 1; } } for (j= 0; j < 32; j++) { EDMA_UTILS_autoIncrement_waitOutChannel_v2(dmaAutoContextOut); fun1( out[bufIdx],indata); EDMA_UTILS_autoIncrement_triggerOutChannel_v2(dmaAutoContextOut); bufIdx ^= 1; } BESTWISHES SHUAI

Hi Shuai, This is looking like a different question then the original question you asked. In general following should be the flow 1. EDMA_UTILS_globalReset() -> Call this only once for your frame processing. 2. Setup(init) input channels ( EDMA_UTILS_TRANSFER_IN) 3. Setup(init) output channels ( EDMA_UTILS_TRANSFER_OUT) At this stage we have not touched the hardware 4. Configure input channels ( EDMA_UTILS_TRANSFER_IN) 5. Configure output channels ( EDMA_UTILS_TRANSFER_OUT) Step 4 and 5 are the ones which will go and configure the hardware as per the transfer properties described in the init parameters. It is important to note that number of blocks in input transfer and number of blocks in output transfer should be same. Once this setup is done then you can call trigger and wait as required. I see that in your code you are calling input and output transfers with different frequency . For this case I would suggest you to use two different dmautils context for input and output channels. Configure first context with EDMA_UTILS_TRANSFER_IN and configure second context with EDMA_UTILS_TRANSFER_INOUT and give number of input channels as 0. Then you will not need to call global reset for the output transfer. Regards, anshu

Ticket Name: Linux/TDA2SX: Memory frequency how to adjust dynamically.

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Tool/software: Linux hi ti The DDR memory model I used was w632gu6mb-12.I want to know how to set it to dynamically adjust the frequency according to the load. Can I use devfreq?What if I could change the device tree?I hope I get the answer. thaks.

Hi, It isn't recommended to update the DDR frequency dynamically. It is set as part of the bootloader and must not be modified. By default in the Linux kernel, Dynamic Voltage Frequency Scaling is enabled which modifies the frequency of the A15 depending on the system load. Regards Shravan

hi Shravan If it has to be modified, is it possible to implement it in the kernel? What are the effects of the changes?

thanks

Hi, Linux runs out of DDR, so you can't modify the DDR frequency on the fly. The DDR configuration happens from U-boot (SPL), which runs from the on-chip memory. After this no configuration of DDR happens. Regards Shravan

hi Shravan Is there a memory low power mode? thanks

Hi, TDA2 family of SoCs don't support low power memory mode. Regards Shravan

thanks

Ticket Name: TDA2: Dual partition layout for enhanced software upgrade and support rolback

Part Number: TDA2 Hello: For safety software upgrade, we expect to use two partition, partition A and B based on NAND. A and B both contain the whole image when A is active, new software is download to B,and then active B. my question: does current TI has the sample solution for this ? does the u-boot already support this to read the partitions alternatively and load image correctly? For linux image in each partition, we also expect to use dual FS partition for linux upgrade, please have look at https://wiki.yoctoproject.org/wiki/System_Update does TI already support it in SDK Any sample for share? Thanks!

Hi, Sorry for the delay in my response! Regarding software upgrade, what we support on our platform today is available at processors.wiki.ti.com/.../6AO.1.0_Application_Notes You may also take a look at the specific patch at review.omapzoom.org/ that enabled the recovery mode and ability to update firmware. It shows one way of how u-boot can decide which image to load at run time. We flash both the regular boot image and recovery image when flashing full image to EVM. I would request you to please go through the above information and let us know if you have more questions. Regards, Somnath

Ticket Name: Linux/TDA2: Linking Error. the usecase with a OpenCV alg_plugin

Part Number: TDA2 Tool/software: Linux Hi, all Refer to vip_single_cam_opencvcanny_sgx_display, I write a usecase with a OpenCV alg_plugin. I got some error in Linking. it looks like something invoked opencl, but I do not enable opencl in cfg.mk. how can I locate the problem? best regards, John ----------------------------------------------------------------- cfg.mk # # Enable below macro to enable OPENVX into Vision SDK # OPENVX_INCLUDE=yes CIO_REDIRECT=yes HS_DEVICE=no DEFAULT_UBOOT_CONFIG := dra7xx_evm_vision_config DEFAULT_KERNEL_CONFIG := omap2plus_defconfig # For TDA2x DEFAULT_DTB := dra7-evm-infoadas.dtb # add by John # Enable macro for OpenCV ENABLE_OPENCV=yes CMEM_INCLUDE=yes BUILD_OPENCV_SRC=no BUILD_LLVM=no ----------------------------------------------------------------- Err info: open_compute/opencv/opencv-3.1.0/libs_linux/libopencv_core.a(ocl.cpp.o): In function `int cv::ocl::getStringInfo<int (*)(_cl_device_id*, unsigned int, unsigned int, void*, unsigned int*), _cl_device_id*>(int (*)(_cl_device_id*, unsigned int, unsigned int, void*, unsigned int*), _cl_device_id*, unsigned int, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >&) [clone .constprop.320]': ocl.cpp:(.text._ZN2cv3ocl13getStringInfoIPFiP13_cl_device_idjjPvPjES3_EEiT_T0_jRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE.constprop.320[_ZN2cv3ocl7Context4Impl10setDefaultEv]+0x26): undefined reference to `clGetPlatformInfo' ocl.cpp:(.text._ZN2cv3ocl13getStringInfoIPFiP13_cl_device_idjjPvPjES3_EEiT_T0_jRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE.constprop.320[_ZN2cv3ocl7Context4Impl10setDefaultEv]+0x5e): undefined reference to `clGetPlatformInfo' /opt/proj/e0800/apa_r04/bsw/platform/ti/open_compute/opencv/opencv-3.1.0/libs_linux/libopencv_core.a(ocl.cpp.o): In function `cv::ocl::OpenCLBufferPoolBaseImpl<cv::ocl::OpenCLBufferPoolImpl, cv::ocl::CLBufferEntry, _cl_mem*>::freeAllReservedBuffers()': ocl.cpp:(.text._ZN2cv3ocl24OpenCLBufferPoolBaseImplINS0_20OpenCLBufferPoolImplENS0_13CLBufferEntryEP7_cl_memE22freeAllReservedBuffersEv[_ZN2cv3ocl24OpenCLBufferPoolBaseImplINS0_20OpenCLBufferPoolImplENS0_13CLBufferEntryEP7_cl_memE22freeAllReservedBuffersEv]+0x4a): undefined reference to `clReleaseMemObject'

Hi John, Could you please share some more details like which release version of SDK you are using ? Also to build Linux opencv app, refer tda2xx_evm_linux_opencx config (all required configs are already enabled) Regards Suryamani Jena

Hi Suryamani, Thanks, The version of SDK is PROCESSOR_SDK_VISION_03_00_00_00. The config refer to tda2xx_evm_linux_all. and I tried tda2xx_evm_linux_opencx. Regards, John

Hi Suryamani, another question, there are some info about IPU2( in cfg.mk) "IPU1 (core 0 & 1 are) not supported when IPU_PRIMARY_CORE=ipu2" Is that meaning ,if IPU_PRIMARY_CORE= ipu2, PROC_IPU1_0_INCLUDE=yes is conflict with PROC_IPU2_INCLUDE=yes? But in the srv usecase(Linux), IPU1_0 is used to capture and display. Why? Regards, John

Hi John we have used only on IPU subsystem when Linux is running on A15. it can be either IPU1 (with IPU1-0 & IPu1-1) or IPU2 (with IPU2-0 & IPu2-1) in SMP mode. when you select IPU_PRIMARY_CORE= ipu2, all capture, display etc. are run on IPU2. This mapping from IPU1 to IPU2 is done inside VSDK regards, Shiju

Ticket Name: TDA2HF: Set DSS parameter failed when Display_Link was creating

Part Number: TDA2HF In PROCESSOR_SDK_VISION_03_08_00_00,i builded a chain: capture->vpe->display vpe params was set as below: 
static Void chains_vipSingleCam_Enc_Dec_SgxDisplay_SetVPEPrms(
VpeLink_CreateParams *pPrm,
UInt32 numLvdsCh,
UInt32 displayWidth,
UInt32 displayHeight,
UInt32 inputWidth,
UInt32 inputHeight
)
{
UInt16 chId;

pPrm->enableOut[0] = TRUE;

for(chId = 0; chId < numLvdsCh; chId++)
{
pPrm->chParams[chId].outParams[0].numBufsPerCh =
VPE_LINK_NUM_BUFS_PER_CH_DEFAULT;

pPrm->chParams[chId].outParams[0].width = displayWidth;
pPrm->chParams[chId].outParams[0].height = displayHeight;
pPrm->chParams[chId].outParams[0].dataFormat =SYSTEM_DF_RGB24_888 ;

pPrm->chParams[chId].scCfg.bypass = FALSE;
pPrm->chParams[chId].scCfg.nonLinear = FALSE;
pPrm->chParams[chId].scCfg.stripSize = 0;

pPrm->chParams[chId].scCropCfg.cropStartX = 32;
pPrm->chParams[chId].scCropCfg.cropStartY = 24;
pPrm->chParams[chId].scCropCfg.cropWidth = inputWidth-32;
pPrm->chParams[chId].scCropCfg.cropHeight = inputHeight-24;
}
}
 then i got assert as below: [HOST] [IPU1-0]     57.923595 s: CaptureLink_drvAllocAndQueueFrames:1553:FVID2_queue: captureVipHandle=0x9f11b880, frameList.numFrames=6, streamId=0
 [HOST] [IPU1-0]     57.923961 s:  CAPTURE: Create Done !!!
 [HOST] [IPU1-0]     57.924388 s:  VPE: Create in progress !!!
 [HOST] [IPU1-0]     57.925242 s: wwlog:vpe set flag=82176,format=20
 [HOST] [IPU1-0]     58.164765 s:  VPE: Loading Down-scaling Co-effs
 [HOST] [IPU1-0]     58.164978 s:  VPE: Co-effs Loading ... DONE !!!
 [HOST] [IPU1-0]     58.165222 s:  VPE: Create Done !!!
 [HOST] [IPU1-0]     58.165649 s:  DISPLAY: Create in progress !!!
 [HOST] [IPU1-0]     58.165954 s:    wwlog: repliEnalbe is false before set!!!!!
 [HOST] [IPU1-0]     58.166046 s: wwlog: repliEnalbe set true
 [HOST] [IPU1-0]     58.166107 s: wwlog: display get flag= 82176,format=20
 [HOST] [IPU1-0]     58.166168 s: wwlog: display will create in SYSTEM_DF_RGB24_888!!!!!
 [HOST] [IPU1-0]     58.166320 s: hal/src/vpshal_dssDispcVid.c @ Line 1023:
 [HOST] [IPU1-0]     58.166412 s: Invalid Data format
 [HOST] [IPU1-0]     58.166595 s: dispdrv/src/vpsdrv_displayCore.c @ Line 304:
 [HOST] [IPU1-0]     58.166687 s: Set DSS parameter failed
 [HOST] [IPU1-0]     58.166748 s:  Assertion @ Line: 474 in displayLink_drv.c: status==SYSTEM_LINK_STATUS_SOK : failed !!! But when i use capture->vpe->sgxFmcpy(A15)->display,display_link can run normal in SYSTEM_DF_BGRA16_4444 . I want to know why dispaly_link cant be creanted in SYSTEM_DF_RGB24_888,or how to make display_link run in SYSTEM_DF_RGB24_888 .

Hi, I think DSS does not support RGB24_888 format, ie R in lower byte, followed by G, followed by B. DSS supports BGR24_888 format, So can you try changing it to system_df_BGR24_888 format? Regards, Brijesh

Thanks for your reply. Dont know why ,but display does run normal with BGR24_888,

Because it is only supported in the DSS. The other RGB packed format is not supported.

Ticket Name: TDA2EVM5777: How to optimize the build time? Want to reduce the Gmake building time

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi, I am following the guidelines given in the userguide for tda2, gmake takes too much time to build for building new package or editing code. Almost 3,4 hours at least. How can make it, since I want to edit code more often. Moreover, if there is any package specific building, like in ROS, just to put package name next to catkin_make in order build that specific package. I believe that would be more quicker than building whole thing. Is there specific guide that explains the whole makefile thing? Thank you. With best regards, H.M. Owais

Hi, You should refer to chapter 3 Fast Builds from PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_BuildSystem.pdf. Regards, Rishabh

Ticket Name: Linux/TDA2: MAKECONFIG?= tda2xx_evm_linux_opencl make fail

Part Number: TDA2 Tool/software: Linux i want try MAKECONFIG?= tda2xx_evm_linux_opencl in visionsdk but when build make -s -j have problem , cg_tools/linux/ti-cgt-c6000_8.1.0 no ti-cgt-c6000_8.1.0 exist ， The C6000 compiler installation specified by TI_OCL_CGT_INSTALL does not exist: /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/ti_components/cg_tools/linux/ti-cgt-c6000_8.1.0 make[7]: *** [copy.dsp_h] Error 1 make[6]: *** [opencl_build] Error 2 make[5]: *** [vision_sdk_linux_demo] Error 2 make[4]: *** [apps] Error 2 make[3]: *** [apps_exe_hlos] Error 2 make[2]: *** [apps_hlos] Error 2 make[1]: *** [apps] Error 2

Hi Shuai, With VSDK 3.2 release the compiler version for C6000 was 7.4.2. Can you check if you have the folder C6000_7.4.2 in path PROCESSOR_SDK_VISION_03_02_00_00\ti_components\cg_tools\linux\C6000_7.4.2. Regards, Rishabh

Hi Rishabh yes ti_components\cg_tools\linux\C6000_7.4.2 BESTWISHES shuai

Hi Shuai, Can you download the ti-cgt-c6000_8.1.0 from www.ti.com/.../8.1.0 and install it in ti_components\cg_tools\linux\ folder and then try the build. Regards, Rishabh

Ticket Name: TDA2SX: HOW TO USE THE SM OF TDA2

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi NOW i use TDA2X do ADAS product and its related safety feature.i got the safety manual from TI,but the safety manual is unclear to describe related safety mechanisms and how to use the related SM;it needs lot of time to study the technical reference manual of TDA2 and it is very diffcult for us. so could you share some experience to config TDA2 SM or do you know TI could provide the safety related software LIB? Thanks a lot!

Hi Xingchao, Please see the Safety Folder on CDDS for TDA2x. There you will find a folder (Getting started...…) with additional videos that can be reviewed. Safety: US - https://cdds.ext.ti.com/ematrix/common/emxNavigator.jsp?objectId=28670.42872.4722.40558 If you do not have access to this link, please work with you local TI contact to get access. Regards, kb

Ticket Name: BEAGLE-3P-BBONE-AI: AM5729

Part Number: BEAGLE-3P-BBONE-AI Hi, I am trying to compile and run ssd_multibox with a video clip, but I am faced with this error. Any suggestions?. I have tried installed gnome but nothing seems to work. Unable to init server: Could not connect: Connection refused (Segmentation:1401): Gtk-WARNING **: 02:30:18.466: cannot open display:

Hi Kavya, have you tried to run "/etc/init.d/weston start" before running ./ssd_multibox? If not please try and let me know. thank you, Paula

Hi, I tried that just now. The weston file is not present in the file.

Hi Kavya, you might need to get assistance from BBAI/Debian open source community. As probably this is a difference between our Linux PSDK and Debian filesystems.. One suggestion, if you don't mind, would be to create an SD card with our Linux PSDK image and give a try to OBB demos there.. Link to download PSDKL and with links to SD creation steps below: http://software-dl.ti.com/processor-sdk-linux/esd/AM57X/latest/index_FDS.html thank you, Paula

thank you, this helps.

Do you use CCS IDE itself or Cloud9, in order to use the PSDK?

Hi Kavya, neither, we use makefiles and Linux dbg capabilities... thank you, Paula

Hi Kavya, one more point... I actually also use Eclipse or VS code to debug/develop some applications. The methodology is to build in debug and then import executable. In this way, I can (for some applications) been able to step into the code, see variables, use memory browser, etc. Hope this helps, Paula

Are there any sources for that? if you did, please share.

Kavya, There should be plenty of resources - articles/videos etc if you search for debugging with Eclipse and/or VS code. I suggest that you search for it and get familiarized. Regards Karthik

Ticket Name: Linux/TDA2: can not add --debug_software_pipeline

Part Number: TDA2 Tool/software: Linux i test my code use CCS and get the cycle， then i add this code in vision sdk ,but the same code use more cycles , i may be diffrent Linker options and rules. so i thy to change rules_66.mk according CCS options, LNKFLAGS_INTERNAL_COMMON i add some options here fatal error #10000: invalid option: --symdebug:none fatal error #10000: invalid option: --debug_software_pipeline this is my CCS options -mv6600 -O3 --opt_for_speed=5 --symdebug:none --diag_warning=225 --diag_wrap=off --display_error_number --debug_software_pipeline --sat_reassoc=off --program_level_compile --auto_inline=1 --gen_opt_info=2 -z

Hi, This could happen if the toolchain use by ccs and vision are different. Please 1st make sure the toolchains are same. Regards, Anuj

Hi Anuj CCS is C6000_8.2.2 and vision SDK is cg_tools/linux/ti-cgt-c6000_8.1.0 , how can i update cg_tools/linux/ to c6000_8.2.2?? Regards, shuai

Hi, Its not recomended to change the toolchain of VSDK. So please try to change your CCS version or change the ttolchain of ccs and have the same toolchain as VSDK. And we do not recommend to build using CCS. CCS is being used only for debug purpose. Regards, Anuj

Ticket Name: TDA2: Is there an example(s) of keras segment(object detection) on TDA2 ?

Part Number: TDA2 Hi all, I have successfully run an example of keras classification on TDA2 as provided in e2e.ti.com/.../689876. Is there any example(s) of keras segmentation(object detection) on TDA2 ?

We don't have any example for Tensotflow segment and object detection models. We have caffe based eamples segment and object detection. Can be found in the below pathc github.com/.../caffe-jacinto-models

Ticket Name: Compiler/TDA2EXEVM: TDA2 - 'Undefined reference Error'

Part Number: TDA2EXEVM Tool/software: TI C/C++ Compiler Hi, How can i implement IPC communication for vision_sdk? i need to implement ipc communication for vision_sdk to receive STOP, RESUME and START command from other modules. I have used the same code ipc_init, ipc_send etc in chains_main.c and included the required header files in the chains.h file. But i am getting an undefined reference error as shown below. --------------------------------------------------------------------------------------- chains_main.c:(.text+0x208): undefined reference to `vDiagPrint' chains_main.c:(.text+0x268): undefined reference to `vDiagPrint' chains_main.c:(.text+0x294): undefined reference to `vDiagPrint' chains_main.c:(.text+0x2ba): undefined reference to `vDiagPrint' chains_main.c:(.text+0x2e6): undefined reference to `vDiagPrint' /home/username/Source/vision_sdk/binaries/tda2ex_mccdvr_all/lib/a15/release/vision_sdk_linux_demo.a(chains_main.o):chains_main.c:(.text+0x33e): more undefined references to `vDiagPrint' follow /home/username/Source/vision_sdk/binaries/tda2ex_mccdvr_all/lib/a15/release/vision_sdk_linux_demo.a(chains_main.o): In function `main': chains_main.c:(.text.startup+0xe): undefined reference to `ipc_init' chains_main.c:(.text.startup+0x88): undefined reference to `vDiagPrint' --------------------------------------------------------------------------------------- can anyone pls help me to to link libraries.? Regards Balaji T

Hi, Ipc Initialization will be automatically done for all core included in the build. You just need to send and received event using IPC. For further implementation info please check how IPC links send informations. Regards, Anuj

Ticket Name: RTOS/TDA2: How to configure VIN1A, VIN3A and VIN5A for direct use without making use of multiplexer control logic block?

Part Number: TDA2 Tool/software: TI-RTOS My colleague is now making a hardware based on TDA2x reference design. It is presumed that we can still make use VIN1A, VIN3A and VIN5A if we do not add in the multiplexer control logic block in our hardware circuitry. In this case, how do we configure VIN1A, VIN3A and VIN5A in this case? Thanks

When you say multiplexer logic, you meant the mux present in TI EVM? In this case there is no special programming required. You can connect the VIN pins directly to TDA2xx and configure the pinmux accordingly.

Hi Sivaraj, Thanks. Basically my colleague intends to remove the MUX hardware block entirely. With Vin directly connect to TDA2x directly, do we need to do any special configuration? Does this type of hardware change will impact on our use on TI SDK?

No impact. We need to just bypass the mux programming (IO expander) code in SDK board module.

Hi, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Sivaraj R

Thanks for the reply. I see your reply is to bypass the mux programming (IO expander) code in SDK board module. I can only try it out when the board being modified by my colleague, is ready for my testing

I will close this thread. You can create a new one if you have any further queries

Ticket Name: TDA2: How to disable the cores

Part Number: TDA2 Hi Sir, How can disable power state, module state and clock state of the IPU2, GPU, IVA, EMIF2? Regards, Sagar

Hi Sagar, Can you please look at www.ti.com/.../sprac22.pdf Regards, Rishabh

Hi Rishabh, Is there any other document which can explain to disable IP's power, clock, module state? Regards, Sagar

Hi Sagar, You can refer to chapter 3 of www.ti.com/.../spruic2c.pdf Regards, Rishabh

Hi Sir, As per this table, if I want to disable EMIF2 module only then which register should I have to configure? If I want to turn off all modules in the CD_EMIF module, then what should I do? Regards, Sagar

Hi Sir, What does the meaning of N/A in the in clock domain? Regards, Sagar K

Hi Sagar, You need to set CM_EMIF_EMIF2_CLKCTRL to turn off EMIF2. For clock domain turn off all modules and then turn off clock domain or put clock domain in HW_AUTO (clock will be gated automatically). Regards, Rishabh

Sagar, PRM is the PRCM module controller itself. It does not fall under any clock domain. Regards, Rishabh

As a side note, Sagar Kanade , you can download CTT for a good visualization on clock registers settings: Regards, Mariya

Thanks Mariya. Sagar please use clock tree tool as suggested by Mariya. Regards, Rishabh

Hi Rishabh, One last question. To put DSS in off state, which register I have to configure? Regards, Sagar K

Sagar, You need to disable all modules and then clock domain. Search for <module>_CLKCTRL and <domain>_CLKSTCTRL. Look at register manual for chapter 3 in TRM and you can find all registers. Start with DSS_CLKSTCTRL. Regards, Rishabh

Hi Rishabh, Thanks for your support. If I called the PMHALResetAssert(PMHAL_PRCM_RG_IVA_RST); function to disable the IVA core, all the cores are in running state. I am not able to take control over any core. All are in running state. This is happened for the second ECU. Regards, Sagar

Hi Sagar, I have already answered multiple questions in this thread. Kindly start a new thread with this specific question instead of having one generic thread with multiple questions. Please mark the posts that have answered questions as “This resolved my issue”. Thanks. Regards, Rishabh

Ticket Name: bare metal interrupt handler

Other Parts Discussed in Thread: TDA2 is there info or samples for bare metal interrupt handling? I am trying to use interrupts on the C66x DSP1 core on the TDA2 (XC5777X CPU BOARD). I have tried the timer example from the starterware and it configures the timer and interrupt functions, but I get exactly one interrupt. The timer is in auto reload mode and seems to be counting and reloading properly. I can’t make sense of the interrupt though. In previous C64xx projects I have had a vector.asm file that contained the reset, nmi and 12 vectors for the chip interrupts. On the C66x with the starterware code there is a lot added to configure the interrupt crosspoint and handlers. I’m not sure if it needs the vector.asm or not. When I add the vector.asm it is getting located at 0x00800000 and the ISTP is set to the same. When the first interrupt occurs, it branches to a vector at 0x00800220. The DSP ISR is showing a value of 0x0040 indicating vector 6. With a vector for ISR6, I would expect it to be at 0x00800060. What I can’t find documented is whether this should dispatch through some predefined function that uses the inth_handler table or whether I should just branch to my handler directly. I "think" the starterware is assuming dsp-bios is running but it is not in this case. Scott

Hi Scott, Welcome to the TI keystone E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature. We do not have Starterware package/support for C66xx (Keystone ) DSP's. The only support available for C66xx DSP's (Keystone I) is MCSDK 2.x. Please find the latest MCSDK and user guide link below my signature. is there info or samples for bare metal interrupt handling? I am trying to use interrupts on the C66x DSP1 core on the TDA2 (XC5777X CPU BOARD). We are not familiar with this platforms however i can point you to some CSL based examples for interrupt on C66xx keystone devices. By understanding that, you can be able to develop your own example. Thank you.

Ticket Name: TDA2SX: how to use Image pyramid algorithm link in vision sdk for tda2

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 I want to use Image pyramid algorithm link in vision sdk for tda2, this algorithm link is supported on M4, but the comment for this algorithm link in algorithmLink.h says: "Image pyramid algorithm link. Only valid for TDA3x" typedef enum { ALGORITHM_LINK_IPU_ALG_DMA_SWMS = 0, /**< Alg to DMA based SW Mosaic */ ALGORITHM_LINK_IPU_ALG_OBJECT_DRAW = 1, /**< Alg to draw rectangles on the image (Needed by PD) */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB = 2, /**< AEWB for ISS running on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB1 = 3, /**< AEWB for ISS running on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_HW_CRC = 4, /**< CRC for checking Frame Freeze Detect on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_IMG_PYRAMID = 5, /**< Image pyramid algorithm link. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_SCENE_OBSTRUCTION_DETECT = 6, /** < Alg to perform SCENE obstruction detection */ ALGORITHM_LINK_IPU_ALG_DEWARP = 7, /**< Plugin to that supports DeWarpping of images, depends on SIMCOP/TDA3x*/ ALGORITHM_LINK_IPU_ALG_RADAR_PROCESS = 8, /**< Alg to perform radar processing */ ALGORITHM_LINK_IPU_ALG_RVC_DIAGNOSTIC = 9, /**< Plugin to support Robust RVC diagnostics register only for TDA2xx */ ALGORITHM_LINK_IPU_ALG_OPENVX = 10, /**< Pluging to support OpenVX */ ALGORITHM_LINK_IPU_ALG_TIDLPREPROC = 11, /**< Alg to do TIDL Pre Process */ ALGORITHM_LINK_IPU_ALG_VPE_SWMS = 12, /**< Alg to VPE based SW Mosaic */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB2 = 13, /**< AEWB for ISS running on IPU1-0 in SRV demo. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_OPENVX_TIDL = 14, /**< Pluging to support OpenVX TIDL */ ALGORITHM_LINK_IPU_ALG_MAXNUM = 15, /**< Should be the last value of this enumeration. * Will be used by Link/driver for validating the input parameters. */ ALGORITHM_LINK_IPU_ALG_FORCE32BITS = 0x7FFFFFFF /**< This should be the last value after the max enumeration value. * This is to make sure enum size defaults to 32 bits always regardless * of compiler. */ } AlgorithmLink_IpuAlgorithmId; I don't know why this link is not valid for tda2x. If I want to use this LINK for tda2x , how to do ? thanks

This is duplicate of below thread, so closing this thread. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1005297/tda2sx-how-to-use-image-pyramid-algorithm-link-in-vision-sdk-for-tda2 Regards, Brijesh

Ticket Name: TDA2EVM5777: Error on eglInitialize

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Dear Experts, I am using version 03.08 Vision SDK in TDA2EVM5777 and only change the MAKECONFIG to tda2xx_evm_linux_all to enable the platform to Linux in Rules.make. I want to use GLES in this environment, but I got some error messages in below program: int main(int argc, char *argv[])
{
    EGLDisplay display = eglGetDisplay(EGL_DEFAULT_DISPLAY);
    
    if (display == EGL_NO_DISPLAY)
    {
        fprintf(stdout, "eglGetDiaply ERR\n");
    }
    
    EGLint majorVer, minorVer;
    
    eglInitialize(display, &majorVer, &minorVer); //error happened and return EGL_NOT_INITIALIZED
    
    return 0;
} Error messages: PVR:(Error): WSEGL_InitialiseDisplay: Failed to create output [0, ] The same problem is also happened on the built-in commands "eglinfo", "gles1test1", and "gles2test1". Is there any prerequisite setting for the above commands and GLES lib in the platform? Best Regards, David

Hello David, Yes, there is a distinction here between the GPU drivers. By default, we provide the Windowing System GPU drivers (WS) and by default this will usually run weston/wayland. I'm not familiar with the TDA2 Vision SDK, but I would assume that by default when you boot up the board you see weston come up on the display? Or perhaps do you see anything on the display? The program that you are trying to run would not be using the windowing system's display, but rather a native EGL display, which is not the default driver we provide. Can you please confirm what comes up on your display when you boot up the board? And the boot logs as well? Thanks, Erick

Ticket Name: RTOS/TDA2: SDK ov10635 I2C address not make sense with datasheet.

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, I find OV10635 salve device default address is 0x30. But I found SDK use 0x38 to communication with OV10635. (Vision board cam1 <-> OV10635) Why they are different?

Hi, The lower 3 bits of the i2c address is controlled by GPIO[2:0]/SID[2:0] pins. so because of them, i2c address can change. Rgds, Brijesh

Hi Brijesh, Thanks for your reply. I know you mean. But same camera module just connect to different CAM port of vision board that will change I2C address of camera module.(Seem not relative with GPIO[2:0] or SID[2:0]) FW log show SOC use 0x38 to communication with OV10635 Do you know why use 0x38 (0x70 /2) ?

These are aliased I2C address. In case of multi-deserializer board, the sensor is connected to the serializer at the remote end through the FPD link. There is no sensors directly connected to the I2C bus on the EVM end. The communication is done through the deserializer, serializer and then to the sensor. We can program a suitable I2C address in the desrializer. Once the programming is done, any read/write to this aliased address is communicated to the remote sensor via the FPD link. The addresses are chosen in a such a way that it doesn't conflict with any of the I2C address connected to this I2C bus in the EVM side. For more details go through 913/914 reference manual.

Hi Sivaraj R3681, Understand. Many thanks.

Ticket Name: TDA2/TDA3 TIDL: Pooling layer error

We use TIDL convert caffe models(*.prototxt + *.caffemodel)，the tidl_log.txt display the following information: TIDL algInit returned with error -1048! ============================= TIDL ERROR! ============================== Pooling layer error, invalid stride width! My SDK version is PROCESSOR_SDK_VISION_03_08_00_00. I refer to the documentation "TIDeepLearningLibrary_UserGuide.pdf": Spatial Pooling Layer – Average and Max Pooling are supported with stride 1, 2, 4 and kernel sizes of 2x2,3x3,4x4 etc. STOCHASTIC Pooling not supported. My *.prototxt ，the "Pooling" layer, the stride have "stride: 2" and "stride: 4", the kernel_size have "kernel_size: 3" and "kernel_size: 5", all of these accord with TIDL Limitation content "Pooling are supported with stride 1, 2, 4 and kernel sizes of 2x2,3x3,4x4 etc." So ,why appear the above error message? tidl_log_pooling_error.rar

Hi, Max Pooling are supported with stride 1, 2, 4 in Height direction, but Width wise only stride 1, 2 are supported. That is the reason you are getting this error. Sorry for the confusion, this is not clearly mentioned in the user guide. Thanks, Praveen

Ticket Name: TDA2EVM5777: TDA2 EVM DDR VTT Enable

Part Number: TDA2EVM5777 Hello Why the EVM connect the SPI1_CS1n(ball A22) to DDR VTT? is there any scenario to turn off VTT by SoC? thank you

Hi, Yes, this pin could turn off VTT during <DDR in self-refresh>, thus saving power. I'm not aware if/how it is used in software. Hope it will be answered here soon. Regards, Stan

Hi @user3829173, which SDK you use? Regards, Yordan

Hi Yordan 01.09.00.00 thanks

Hi Stan Got it! thanks

Ticket Name: Linux/TDA2P-ABZ: linux version 4.14.24 Crashes

Part Number: TDA2P-ABZ Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hi, Could you please answer a question from a customer. I try to bring up linux version 4.14.24 (ti-git repository) on our homebrew device, but it will not boot into linux kernel and crashes very early, so this way will not bring success. So there is still no Board Support Package, which captures all features of the TDA2+, right? (I tried out linux 4.4.84, out of visual sdk, before, but sadly I was missing timer12. RNG and MCAN support.) Thanks, -Needhu

Hi, I would recommend customer to use the kernel and u-boot from here Vision SDK and add selected features from the latest kernel. Latest kernel and u-boot can be found here Kernel: git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git Branch: ti-lsk-linux-4.14.y U-boot: git://git.ti.com/ti-u-boot/ti-u-boot.git Branch: ti-u-boot-2017.01 Regards, RK

Ticket Name: TDA2SX: is it suitable to port/migrate the application to TDA4VM?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2, TDA4VM, SK-TDA4VM Hi, we are working with cascade imagine radar apps and use cases in the MMWCAS-DSP (TDA2) + MMWCAS-RF and I would like to know how difficult could be the migration from my solution to a TDA4VM (SK-TDA4VM), does exist any critical risk, compatibility or requirement (hardware, software, architecture, etc) that I should take into account? Thanks

Ticket Name: TDA2PXEVM: Failed to connect display in libilmCommon

Part Number: TDA2PXEVM Hi I am trying to run Qt application on Jacinto6 plus board but it is failing with the following error. Please suggest how to solve it. Failed to connect display in libilmCommon Interpreter error: failed Failed to connect display in libilmCommon Interpreter error: failed Failed to connect display in libilmCommon Interpreter error: failed Thank you, Deepthi

Hi Deepthi, Can you please provide some more details on the issue. What SDK is being used, what is working so far?. At what point is the error seen, and what application is under test? Please be aware of the below related threads: TDA2EVM5777: I want to use Qt on TDA2EVM5777, what should I do? - Processors forum - Processors - TI E2E support forums (+) Qt App Development For Processor SDK Linux Automotive - Processors forum - Processors - TI E2E support forums (+) Linux/TDA2: build the PSDK by yocto, error:unknown type name 'ucs4_t' - Processors forum - Processors - TI E2E support forums Regards, kb

Ticket Name: RTOS/TDA2: JAMR3 Application Board Query

Part Number: TDA2 Tool/software: TI-RTOS Hello, Wanted to know if JAMR3 Application Board(EVM) supports Vision SDK version 03.05.00? Reference: (SPRUI52.pdf) Thank you! Vallabh

HI Vallabh, JAMR3 Application Board(EVM) not supported on Vision SDK version 03.05.00 However it is supported on Processor SDK 03.04.00.00 release Regards Surya

Thank you Surya! Regards, Vallabh

Ticket Name: Linux/TDA2EVM5777: System-link Buffer issue in VSDK3.04, Getting NULL pointer in "bufAddr[0]"

Part Number: TDA2EVM5777 Tool/software: Linux Hi, I’m in the process of migrating my application running on TDA2x EVM, from VSDK3.03 to VSDK3.04. In brief, I have a chain running as shown: Null_src (A15-Linux) -> ALg_link(EVE) -> Null_sink (A15-Linux) While trying to get the input buffers in Null_sink from the Alg link (EVE), using “System_getLinksFullBuffers”, I’m observing that the bufAddr[0] in the System_VideoFrameBuffer received are pointing to Null. I’m using buffers in in-place mode. The same application is working well under VSDK3.03, however when it is built under VSDK3.04, this issue is seen. Can you please provide your inputs to resolve this issue. Thanks in advance, Regards, Ranjith Bhide

Hi, Can you please check the bufType of the buffer got from System_getLinksFullBuffers in NULL_Sink link. Inside your alg link running on eve, just check the bufaddr when you receive the input and check the same when you send that buffer. Is the alg link is yours or TI? Regards, Anuj

Hi Anuj, Thanks for the response. This cause of the issue was found. There is a new member variable "hlosTranslationDisable" added to structure System_Buffer, which needs to be initialized to FALSE during init. Failing which the Physical-Virtual address translation was not happenning which was causing this issue. After setting the hlosTranslationDisable field as FALSE for all the system buffers the issue was resolved. Regards, Ranjith Bhide

Ticket Name: TDA2PXEVM: Installing ROS on TDA2PXEVM after building Yocto filesystem

Part Number: TDA2PXEVM Hello all, I have built Yocto filesystem on my TDA2Px using this guide: https://software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/6_00_00_03/exports/wiki/Processor%20SDK%20Linux%20Automotive%20Software%20Developers%20Guide%20-%20Texas%20Instruments%20Wiki.pdf I want to know how can I add ROS layer and build Yocto again with ROS installed and have ROS running on my TDA2Px-EVM. Or in other word how can I customize a ROS layer or is there any guide for that? Thank you, Best Regards, Kirollos Henry

Kirollos, It seems like you have made progress on the ROS image already: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1013431/tda2pxevm-roscore-run-error-on-my-tda2px-evm-due-to-python-version. There is no guide for integrating ROS with TDA2Px - most of our experiments with ROS were experimental and since both TI SDK and ROS were moving quite a bit we didn't snapshot a stable version and document the same. Lets continue discussion on the newer thread. Closing this one for now. Regards Karthik

Ticket Name: RTOS/TDA2: How to exchange data between IPU1_0 and IPU1_1

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, I have a global variable "Var" at IPU 1-1. How to exchange "Var" to IPU1-0 if need? Could you please give me advise? Thanks.

Hi Prince, You need to allocate the buffer from the shared memory space. This shared memory space will be accessible on all cores.. Rgds, Brijesh

Hi Brijesh, Thanks for your reply. Have any links or utils of SDK can study?

Hi Prince, Look the usage of the object gSystemLinkStatsCoreObj in the vision sdk. This object is allocated from non-cached shared section and accessed from all cores. Rgds, brijesh

Thanks for your support.

Ticket Name: TDA2EXEVM: Switching AWR Profile Config in Cascade MIMO Usecase

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi, The MIMO usecase defines an AWR configuration that uses all 4 radar sensors with single profile. Say if I would like to extend the number of profiles from 1 to 4, I would simply add 3 more statically filled profile data structures in rlProfileCfg_t gChains_cascadeRadarProfileArgs. This enhanced profile config will then be registered with Bsp_ar12xxRegisterConfig() after ChainsCommon_ar12xxInit() was called. That's fine and all. Now I would like to instruct to switch from profile 0 to profile 1, how can that we done? Thanks, --Khai

Please use the below function under ~/vision_sdk/apps/src/rtos/radar/src/common/chains_common_ar12xx.c. You can refer to the use case, radar_objectdetect_display, to see how it is used. /** ******************************************************************************* * * \brief Function to change the profile parameters at run time * * \param algId Algorithm Link ID for the FFT Heat Map * \param pAr12xxCfg Pointer to the configuration structure. * * \return retval SYSTEM_LINK_STATUS_SOK if the parameter change has happened. * ******************************************************************************* */ Int32 ChainsCommon_ar12xxChangeParameters(UInt32 algId, ChainsCommon_Ar12xxConfigOut *pCfgOut)

Resolved

Hi Stanley, Using your suggestion with some code mods allows me to switch from one chirp profile to another. However, the new profile radar cube didn't seem to automatically recognize in the processing data flow (ie: FFT Alg didn't get a new profileID). Debugging into the FFT code that sets the ProfileID in this code block below get skipped over the logic. pObj->inBufAddrOffset[chId] is never > 0. So, currProfile is always 0 due to initialization. My new chirp profile change also has numADCSamples and numLoops that are different than the the first profile. if (pObj->inBufAddrOffset[chId] > 0U) { currProfile = ((*(UInt32*)inBufAddr) >> 2U) & 0xFU; } Any thought? Can I get a zoom session with you to debug this? Thanks, --Khai

Hi Stanley, If currProfile = ((*(UInt32*)inBufAddr) >> 2U) & 0xFU; is not changing upon ProfileCfg_t change, how do I know if the AWR radar cube size actually did change? Thanks, --Khai

Did you use the data out format 6 in dataPathCfgArgs? You need that so chirp profile will be added to the beginning of input data..     .dataPathCfgArgs   = {
        .intfSel         = (rlUInt8_t) 0,
        .transferFmtPkt0 = (rlUInt8_t) 6, /**< Data out Format, \n
                                      b5:0 Packet 0 content selection\n
                                      000001 - ADC_DATA_ONLY \n
                                      000110 - CP_ADC_DATA \n
                                      001001 - ADC_CP_DATA \n
                                      110110 - CP_ADC_CQ_DATA
                                      b7:6 Packet 0 virtual channel number (valid only for CSI2)\n
                                      00 Virtual channel number 0 (Default)\n
                                      01 Virtual channel number 1\n
                                      02 Virtual channel number 2\n
                                      03 Virtual channel number 3 \n*/

Yes, when i set .transferFmtPkt0 = (rlUInt8_t) 6, profileId varies from 0 -> 15 from frame to frame. Not reliable. I would expect it to remain 0 until a new profile is changed. Thanks, --Khai

Is there another way to know when profile changes (which in turns radar cube size changes), the correct radar cube size is coming into the TDA2 processing chain? In the past, reply on setting this flag to 6 so when profile changes, a new profileId is updated in FFT Alg and thus pull the right parameters to process the incoming ADC data. Now that that is not reliable, how do I know the profile has actually been changed on the AWR? Where can i print the actual ADC radar cube size and not from the pre-populated profile info in the pRadarParam object? Thanks, --Khai

This would be a question for our radar team. Maybe you can test this with mmWave Studio first to see if it is even possible to do what you want to achieve with the radar configurations.

Ticket Name: CCS: how to move tda2 C66 to TDA4 C66

Other Parts Discussed in Thread: TDA2 Tool/software: Code Composer Studio I have run our cnn on tda2 C66 , i use v7 ccs build my code creat c66 static lib and call it by visionsdk. in the lib i used EDMA to move data between L2 and DDR. now i have to run my cnn on tda4 c66, what should i do ? just using v9 ccs rebuild it? Thanks! Shuai

Shuai, The EDMA used in TDA2 is no longer in TDA4. You can first try to compile the lib in CCS v9 without EDMA (use cache) to see that the build, link, and run are functional. I will see who can follow up on what new DMA library you can use from the PSDKRA package. Regards, Jesse

The DMA on TDA4x is called UDMA. You can reference how it can be used in following folder: PSDKRA: vision_apps/utils/udma Regards, Jesse

Ticket Name: TDA2PXEVM: Function to extract the masks from semseg usecase

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hi TI, I have few questions regarding post image processing on tda2. 1. How to use vlib within the tidl_postproclink,c? 2. Which function of vlib can be used to extract the information of individual class mask. What I am looking for is something similar to cv2.inRange function in Vlib? 3. Is there any function to find the contours as well in vlib? Thank you. With best regards, H.M. Owais

Hafiz Muhammad Owais said: 1. How to use vlib within the tidl_postproclink,c? I can't find the file tidl_posproclink.c in the SDK. Is there a typo? Also, not sure I understand the question. Assuming that this link is running on DSP, then adding vlib call is like adding any other library call. You need to call into the function you want, and make sure that the header file vlib.h is included and the makefile includes the include path for this. Hafiz Muhammad Owais said: 2. Which function of vlib can be used to extract the information of individual class mask. What I am looking for is something similar to cv2.inRange function in Vlib? There is none in vlib. Hafiz Muhammad Owais said: 3. Is there any function to find the contours as well in vlib? There is none in vlib.

Hi Jesse, Thank you for your reply. I have solved the question 1. I want to be more precise for the rest of questions. Since TI has offered a demo version for semantic segmentation which is semseg. Once we finish the semantic segmentation, let's just say for three classes bicycle, person and background. What I want to do now is to apply image processing further to extract the information regarding whether the person is sitting on the bicycle or not. I believe most of the users need such kind of post image processing for the semantic segmentation. Do you have any solution for the post processing in the vlib? With best regards, Owais

Hi Owals, Unfortunately, no we don’t have such function that would analyze the output of semantic segmentation. However you can train another deep learning network that would analyze the output of the semantic segmentation and detect regions in which there is a person sitting on a bike. Or the original semantic segmentation model could be retrained to detect 4 classes: bicvcle alone, person alone, person sit on bicycle, background. regards, Victor

Hi Victor, I have written post processing algorithm by myself on C which works pretty fine enough :-) without utilizing any vision library. Your suggestion is useful but it would require more time for labeling and training it again. I will keep this suggestion in my mind for other segmentation tasks. Thank you. With best regards, Owais

Ticket Name: TDA2SX: Emotion recognition - TIDL import

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi to all, I am trying to import emotion recognition model and I am facing some difficulties. Model have 7 output classes. For every input image I have same output index (same class) and same output for every input image. I looked at deploy.prototxt and added flatten layers before every InnerProduct layer. Also, I am using sparse convolution, so with kernel_size: 5 I think there shouldn't be a problem for convolution layers, should it? I don't see any other limitation that could affect me, but it will be useful if some expert take a look at model and import file to check if I missed something.emotion-recognition.7z I am using TIDL 01.01.01.00 with PSDK 03.04.00.00. There are model files in attachment. Thank you in advance and regards, Sasa

8637.emotion-recognition.7z

Hi Sasa, Form the "deploy.prototxt" it looks like TIDL can support all the layers, but in the deploy.prototxt, can you use different output names for different flatten layers and try? Also, Did out check that outputs correct with caffe inference on these input images and your model? Thanks, Praveen

Hi Sasa, Did you get a chance to try out above suggestions? Thanks, Praveen

Hi Pravenn, I only managed to try renaming flatten layers to have different names and there was no success. I have usually class 4 detected and for some of images class 5. layer {
  name: "flatten1"
  type: "Flatten"
  bottom: "pool_3"
  top: "flatten1"
  flatten_param {
    axis: 1
  }
}
layer {
        type: "InnerProduct"
        name: "hidden_1"
        inner_product_param {
                num_output: 200
        }
        bottom: "flatten1"
        top: "hidden_1"
} These are changes made. I did the same with different names for other flatten and innerProduct pairs of layers. Also I have a question about checking correctness. This same caffe model is tried on another platform and worked correctly (same model and same inputs) . I wanted to run it on TDA2 to have comparison, so I can confirm that model is correct.

Hi Sasa, Ideally we expect this to work properly, but not sure where the problem is. So I would suggest to check the layer level outputs from import tool against the caffe reference outputs to identify which layer is causing the issue, please refer to section 3.8 (Matching TIDL inference result) in the TIDL user guide on how to do this. Thanks, Praveen

Ticket Name: TDA2PXEVM: Is Reshape/Permute layer supported on TDA2X with CaffeImportTool?

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hi ! When convert shufflenetv2 caffemodel to tidl bin/param using REL.TIDL.01.01.03.00, it failed. EEROR LOG: TIDL returned with error code : -1100, refer to interface header file for error code details Error at line: 1578 : in file .\.\src\tidl_tb.c, of function : test_ti_dl_ivison End of config list found ! But I check that reshape layer and permute layer work well in SSD model. So how can I make separate reshape layer and permute layer work ?

Hi, Reshape, Permute layers are supported only in the context of SSD network. They are not supported as standalone layers. Thanks, Praveen

Hi Praveen Thanks for you replay. So currently, channel shuffle can not work on TIDL(both tda2 / 4). These requirements will be supported in the futures?

Hi, It can work on TDA4 TIDL but not in TDA2 TIDL, please note that both are different code bases and TDA4 can support much more netwroks and frame works compare to TIDL on TDA2 , please try with TIDL on TDA4 (https://www.ti.com/tool/download/PROCESSOR-SDK-RTOS-J721E/08.00.00.12). Thanks, Praveen

Ticket Name: CCS/TDA2: EMIF Register definitions in CCS

Part Number: TDA2 Tool/software: Code Composer Studio Hi It seems that the Register Definition of the EMIF in CCS are not only incomplete (PHY_STATUS_2-19 missing), but also wrong for the existing register definitions: So in CCS it says 0x018C for STATUS_20 but the TRM specifies 0x0190 Are there newer Register definitions available for our device? Do they ship with CCS or where could I get a update of these? Regards, Daneil

Daniel, Looks like you are using an older defective device support package (i.e the package that loads those registers). Try using the latest version (Automotive v1.0.6) Here is the wiki processors.wiki.ti.com/.../Device_support_files or you can use Help->Install New software -> select CCS update site->Select latest auto package. Thanks, Alex

Ticket Name: tda2x

hi: i have sensor ar0132 that data type is raw. we need put raw-data output to algorithm mode. i have question: 1.Whether raw-data pass through the vip module not direct output to algorithm mode? 2.if it pass through the vip,then it can pass through which vip sub-modules? eg.repacker,parser,csc1 and son.

Hi, I could not understand your question completely, RAW data can be captured via VIP. In this case, internal modules like CSC, Scalar will be bypassed.. and the captured data will directly go the memory, then you could pass it to algorithm for further processing. Rgds, Brijesh

ok,u means captured data not directly go the vpdma but go memory,didn't u?

vpdma capture data to memory. vip outputs to vpdma and vpdma writes to memory..

hi brijesh : i read page 2267 of TRM .VPDMA Data Formats just support rgb and yuv types. i don't see raw data

raw is implemented in driver using YUV422 data type. VIP ip does not support raw as a format. Rgds, Brijesh

ok.but i don't have isp? 1.is the output to vpdma also yuv422? 2.how implement raw data in driver using YUV422？where should i find these code or file？ 3.if Algorithm interface only supported raw-data，then what should i do？

It is yuv422 input and yuv422 output, so essentially no other processing, the input data straight goes to memory. Just the data format to FVID2_DF_RAW, it is supported.. It is not problem, just set the data format to RAW in the driver, driver will capture the raw data and that you could use it in the algorithm. Rgds, Brijesh

hi: i read sample code about how to set dataformat in vision_sdk_0306/ti_components/drivers/pdk_01_10_02_07/packages/ti/drv/vps/examples/vip/captureVip/src/CaptureVip_main.h 653~677 line: ar013 have 12-bit raw data type.why didn't select FVID2_DF_RAW12 but FVID2_DF_RAW16?

There is no RAW12 because VIP does not support it. it can support 8bit or 16bit or 24bit input.. You could capture RAW12 by tying upper 4 bits to low, even in this case, output will be stored 12ibt in 16bit container.. Rgds, Brijesh

Ticket Name: TDA2E: 24.10 Gigabit Ethernet Switch (GMAC_SW) in Literature Number: SPRUI29F November 2015–Revised October 2018

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 HI, We use Cortex®-A15 microprocessor unit (MPU) subsystem on TDA2x ,and we want to driver GMAC_SW on A15 (MPU) subsystem. We have PROCESSOR_SDK_VISION_03_06_00_00 soft package,and the guide document of package is attached. My question is: 1. Where is GMAC( on TDA2x) driver code in PROCESSOR_SDK_VISION_03_06_00_00 soft package? 2. How to build the GMAC driver code into .out file? Thanks Dengfei Li VisionSDK_Getting_Started_Guide.pdf

Hi, can you check in "PROCESSOR_SDK_VISION_03_06_00_00\ti_components\networking\nsp_gmacsw_4_16_00_00" Regards, Yordan

HI , PROCESSOR_SDK_VISION_03_06_00_00\ti_components\networking\nsp_gmacsw_4_16_00_00" DO NOT be built into kernel in PROCESSOR_SDK_VISION_03_06_00_00 package can you solve the second question below ? 2. How to build the GMAC driver code into .out file? Thanks Dengfei Li

There are 2 options for GMAC driver support on TDA2 running Vision SDK. - Option 1: TI RTOS GMAC driver on M4. This is provided by nsp_gmacsw_4_16_00_00 and it is pre-built. VSDK will link the libraries from NSP package. It is included by defining NDK_PROC_TO_USE=ipu1_1 under ~\vision_sdk\apps\configs\tda2xx_evm_bios_all\cfg.mk. - Option 2: Linux Ethernet driver on A15. If you build the Linux Vision SDK and run Linux on A15, the ethernet driver is provided in Linux kernel by default. Regards, Stanley

HI Stanley, Thanks for your answers firstly. There are 2 questions to need you help below: 1. We use A15 on TDA2x,and I see "NDK_PROC_TO_USE=a15_0" in ~\vision_sdk\apps\configs\tda2xx_evm_bios_all\cfg.mk. Now I want to know: what's the directory of the ethernet driver( GMAC_SW on TDA2x soc) provided in Linux kernel by default? 2. We use realtek PHY IC(RTL9000A) to connect GMAC_SW(on TDA2x),what's the directory of PHY driver for realtek in linux kernel ? if I know dir of PHY driver in liunux kernel,I can use it as base and change it according to new RTL9000A driver code. Thanks a lot Dengfei Li

1. This is still using TI RTOS driver under nsp. To build for Linux, please refer to ~/vision_sdk/docs/Linux/VisionSDK_Linux_UserGuide.pdf. 2. Once you follow the Linux User Guide, the Linux 4.4 kernel will be installed. Please refer to Linux kernel documentation for ethernet driver.

HI Stanley, Sorry for your misunderstanding my meaning. I want to know exactly "detailed directory" in in Linux kernel for Option2 below: - Option 2: Linux Ethernet driver on A15. If you build the Linux Vision SDK and run Linux on A15, the ethernet driver is provided in Linux kernel by default. Thanks Dengfei

Linux kernel documentation will provide that information.

HI , I do not find the detail directory of GMAC( on TDA2x) driver code for A15 (MPU) subsystem in linux kernel documents Could other engineer tell the directory below? What's the detailed directory of GMAC( on TDA2x) driver code for A15 (MPU) subsystem in PROCESSOR_SDK_VISION_03_06_00_00 soft package? Thanks a lot Dengfei Li

Please follow the Linux user guide first to clone Linux kernel from public repo. Vision SDK doesn't come with Linux kernel since it is open source. All Linux drivers are under ~/ti_components/os_tools/linux/kernel/omap/drivers/. Please note we don't provide training on Linux since it is open source.

Ticket Name: TDA2: TDA2SX EMIF DDR3

Part Number: TDA2 Hi. We are ging to use this IC. So can we use only one emif1 interface with DDR3 or we must use both emif1 and emif2 with DDR3? Thnks.

Hi, You can use only one EMIF as well depending on the use case requirements. Regards, Rishabh

Hi Yuri, in addition to what Rishab said: if you want to use only EMIF1 or EMIF2 you need to correctly configure the LISA_MAP registers in DMM. This is explained in section “Addressing Management with LISA” of the TDA2x TRM. Take also into account that when you use only one EMIF, the max SDRAM size is 2GB. Regards, Yordan

Hi Yordan. I have a little question. In TRM written " In this example, assume there is 1 GiB of external memory evenly spread onto two address spaces. The address range for address space 0 must start at offset 0x2000_0000 (see Table 15-19)." Summary address space is 1 GiB in table 15-19. How can I connect 2 GiB memory to EMIF1? I want to use only EMIF1 with ECC too. I want to use 2 ICs MT41K256M16 and one IC MT41K512M8 for ECC. Is that correct configuartion? Regards, Maxim.

Hi, If you want to use 2 GB DDR, you should set 0x7 as SYS_SIZE in LISA_MAP. For the question related to hardware parts please start a new thread. Regards, Rishabh

Ticket Name: [TDA4M] Removal of RTC oscilator HW

Other Parts Discussed in Thread: TDA2 Hi, WKUP_LFOSC_XO/WKUP_LFOSC_XI external oscillator is used for low power operation. RTC OSC can be shown at HW schematic of TDA4 EVM. Q1) What is the functionality of using RTC OSC instead of using WKUP_LFOSC_XO/XI ? Q2) Should WKUP_LFOSC_XO/XI be added in my customized board? Q2) Can I remove RTC OSC HW if RTC OSC functionality which you will reply for my question is not needed ? BR, Soolim

Hi Soolim, Q1) TDA4, unlike TDA2/TDA3, doesn't feature an internal RTC capability thus an external HW is required if RTC function is needed. Q2) WKUP_LFOSC_XO/XI crystal is required for some of the SoC low power modes. This crystal is needed if some Timer modules need accurate 32.768k clock for your application. I would place crystal pads if not sure. Q3) RTC IC can be skipped if software doesn't need a real-rime clock function. Regards, Stan

Ticket Name: IssCapture Input Type

Is it possible to use HDMI as an input instead of CSI2 in IssCapture. Thanks and Regards, Aneesh

Aneesh, IssCapture link support CAL module, which can receive data only from CAL, over CSI input format. For HDMI, you need to use VIP, capture link. Rgds, Brijesh

Hi Brijesh, Can you tell me a usecase where i can see the hdmi as input to vip capture. Regards, Aneesh

Hi Aneesh, You could use any object detection usecase, it uses HDMI as input port, where HDMI decoder output is connected to VIP. Rgds, Brijesh

Ticket Name: TDA2: Bsp_deviceRead8 on serializer(UB913) fails with timeout.

Part Number: TDA2 On my custom HW setup, TDA2X EVM + UB914DES <--> UB913SER + AR0132 Vision SDK 3.03 Communication with Serializer seems to be failing always: [IPU1-0] 9.936375 s: CHAINS: Sensor create in progress [IPU1-0] 9.936558 s: VIDEO_SENSOR: INST1 : I2C1 : I2C Addr = 0x10 [IPU1-0] 9.938052 s: Read8 I2C1: DEV 0x6c: RD 0x06 = 0xb0 [IPU1-0] 9.938418 s: Write8 I2C1: DEV 0x6c: WR 0x01 = 0x04 [IPU1-0] 9.939028 s: Write8 I2C1: DEV 0x6c: WR 0x03 = 0xed [IPU1-0] 9.940065 s: Write8 I2C1: DEV 0x6c: WR 0x06 = 0xb0 [IPU1-0] 9.941377 s: Write8 I2C1: DEV 0x6c: WR 0x07 = 0xe8 [IPU1-0] 9.942017 s: Write8 I2C1: DEV 0x6c: WR 0x08 = 0x30 [IPU1-0] 9.942993 s: Write8 I2C1: DEV 0x6c: WR 0x10 = 0x20 [IPU1-0] 9.944000 s: Write8 I2C1: DEV 0x6c: WR 0x1f = 0x12 [IPU1-0] 9.945068 s: Read8 I2C1: DEV 0x6c: RD 0x06 = 0xb0 [IPU1-0] 9.946501 s: Read8 I2C1: DEV 0x6c: RD 0x07 = 0xe8 [IPU1-0] 9.947081 s: Read8 I2C1: DEV 0x6c: RD 0x1c = 0x03 [IPU1-0] 10.558561 s: src/bsp_deviceI2c.c @ Line 386: [IPU1-0] 10.558683 s: I2C1: DEV 0x74: RD 0x06 ... ERROR !!! [IPU1-0] 10.558775 s: src/bsp_deviceI2c.c @ Line 412: [IPU1-0] 10.558897 s: I2C1: Error timeout 611 ms!!! [IPU1-0] 10.558988 s: src/bsputils_lvds.c @ Line 1083: [IPU1-0] 10.559080 s: device address - 74 i2c error - -21 Any reasons as to why such a timeout occurs in Bsp_deviceRead8 ? Regards, Vivek

Hi Vivek, From the log it shows that you are trying to configure the serializer1 connected on the lvds interface. the file from where the error is generated is <PDK_INSTALL_DIR>\packages\ti\drv\vps\examples\utility\src\bsputils_lvds.c This may not be connected on your custom board and check what sensors you need to configure. Can you check on this? Regards, Prasad

Hi Vivek, We have not heard back from you. Hope you were able proceed further. Regards, Prasad

Custom HW is just : UB913SER + AR0132 Tda2x evm + MULTIDES is standard hardware We are still not able to understand why the i2c reads are timing out.

Hi Vivek, Check the I2C address of the sensor, are you able to talk to UB913? Regards, Sujith

Hi Sujith, I have not been able to talk to UB913. Whan I read the 0x1C General Status of Deserializer, it indicates Signal detect bit is set for serial input. That is the closest. I tried the same with i2c_utility. Regards, Vivek

Okay, please check if the UB913 is powered up, use a scope and check please. Regards, Sujith

Sujith, Cannot use scope on the UB913 since its a closed camera housing. Another piece of information which might help is, The same camera with the same set of required code modification is working fine on Vision SDK 2.09 version. Is there any change in Camera power up / bring-up sequence in newer vision SDK, or in Pin Mux Settings? Regards, Vivek

Hi Vivek, If the sensor is working in 2.9, can you enable I2C debug flag before the sensor config and disable after that? This should print all the I2C transaction happening. You can compare this with latest version. You can enable using the API Bsp_deviceI2cDebugEnable(). Regards, Prasad

Prasad, Did that already, no difference between working and non-working set of Read/Writes to configure Deserializer. I2C Transactions are same until write to serializer to reset happens and reading the same leads to timeouts. Regards, Vivek

Any further Pointers ? Prasad Konnur / Sujith

Hi Vivek, Can you please list the changes that you had to do get it going on VSDK 2.9. Regards, Sujith

Sujith, Below is short indicator of files modified: 1. In bsputils_lvds.c a. SER & DES addressing b. gI2cExpParams c. gAR0132DesParams 2. bsp_boardTda2xx.c Not sure If I can share exact customer code. Regards, Vivek

Hi Sujith / Prasad Konnur We seem to have found the issue. It was with the way IO expander configurations on multi-deserializer are done. I think it has been cleaned up from Vision SDK 2.9 to 3.3. We were missing this Thanks and Regards, Vivek

Ticket Name: RTOS/TDA2: Bottom Part of the video cropped when running the TIDL object detection usecase

Part Number: TDA2 Tool/software: TI-RTOS Hello, I'm running the TIDL object detection usecase, and usecase is running fine only with a small problem here: My original input file is .MP4 with resolution 1920*1080, and I make it to .h264 with resolution 768*320, I played the .h264 file using VLC media player and the display is good, but when I use the file to run the object detection usecase, the bottom of the video is cropped, and I'm sure there is no resolution problem in the code or the cfg file in my SD card. I've attached my .h264 file for reference(remove the .txt before use), please pay attention the bottom left part when display it.outfile.h264.txt

Hi, I hope you have not modified anything in usecase or any links. You just have created your input and index file and modify the names in cfg file placed in sd card. can you share a snapshot/picture of your display while running this usecase? Regards, Anuj

Hello Anuj, Thanks for your reply, I'm sure I didn't modified anything in the usecase or links...I'm still getting familiar with it... Here is the snapshot, 1.png is the h264 data I generated on PC and I played it with VLC media player, 2.png is the photo I take when I run the TIDL usecase with TDA2, you can see from the bottom left some part is missing. snapshot.rar

Hi, Can you try with the default provided files. Regards, Anuj

Hi, I don't have a CDDS account so I have no default inData_OD and inHeader_OD files. Thanks.

Hi, Can you try to run the usecase NullSrc decode display(option 1->n in usecase menu) with your input files and see there you see the full video or not? Regards, Anuj

Hi, Its been a long time since any update on this thread. I hope this issue is resolved. Regards, Anuj

Ticket Name: RTOS/TDA2P-ACD: DCAN module board to board test

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hi Sir, I has test CAN TX, RX function by loopbackTest(TX send to RX of TDA2) by setting "DCAN_INCLUDE=yes" . loopbackTest setting as below: /** \brief Used for enabling board-to-board DCAN */
//#define ENABLE_B2B_DCAN_TEST             (1U)

static Void System_dcanInitCfgStruct(dcanConfig_t * dcanConfig)
{
    Int i;
    UInt8 msgData[] = {0xAA,0xEE,0xBB,0xFF,0xCC,0xDD,0x55,0xAA};

#if ENABLE_B2B_DCAN_TEST
    dcanConfig->enableLoopback     = FALSE;
#else
    dcanConfig->enableLoopback     = TRUE;
#endif
    dcanConfig->enablePeriodicTx   = TRUE;
    dcanConfig->rxMsgId            = 0xC1;
    dcanConfig->txMsgId            = 0xC2;
    dcanConfig->enableSendRxAck    = TRUE;
    dcanConfig->enableReceiveRxAck = TRUE;
    dcanConfig->txAckMsgId         = 0xC4;
    dcanConfig->rxAckMsgId         = 0xC5;
    dcanConfig->rxMsgCb            = System_dcanRxMsgHandler;
    dcanConfig->rxAckMsgCb         = System_dcanRxAckMsgHandler;
    dcanConfig->txMsgPeriod_ms     = SYSTEM_DCAN_TX_PRD_MS;
    dcanConfig->dcanCntrlIntrId    = SYSTEM_DCAN_INTR_ID;
    dcanConfig->dcanTxTskPri       = SYSTEM_DCAN_TX_TSK_PRI;
    dcanConfig->dcanRxTskPri       = SYSTEM_DCAN_RX_TSK_PRI;
    dcanConfig->dcanInputClk_hz    = SYSTEM_DCAN_INPUT_CLK;
    dcanConfig->dcanBaudRate_hz    = SYSTEM_DCAN_BIT_RATE;
    dcanConfig->enableTxMsgCycle   = TRUE;
    dcanConfig->dcanTxPrdMsg.dataLength = UTILS_ARRAYSIZE(msgData);
    for ( i = 0 ; i < UTILS_ARRAYSIZE(msgData); i++)
    {
        dcanConfig->dcanTxPrdMsg.msgData[i] = msgData[i];
    }
}
 I can log TX and RX of TDA2 communication data by PCAN-USB-FD Adaptor. I got some issue that is when I send test packet [CAN-ID=0xC2, Data = 0xAF, 0xF3, 0xC0, 0x04, 0xD1, 0XE2, 0x5A, 0xAF] to TDA2. The issue seem like TDA2 can't receive data from PCAN-USB-FD Adaptor. Could you please give me some advise? Many thanks.

Hi Prince, You need not to comment out 'ENABLE_B2B_DCAN_TEST' macro. Can you please un-comment it and try it again? From your logs, it looks like you are able to receive some messages form TDA2. Please confirm this. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi Vivek , Thanks for your feedback. I comment out 'ENABLE_B2B_DCAN_TEST' macro still get same error when send test data by PCAN-USB-FD Adaptor. Have any document or tutorial to description DCAN of TDA2?

Hi Vivek , Update information. a. External loop back test mode can transmit test data to PCAN-USB-FD Adaptor - comment out 'ENABLE_B2B_DCAN_TEST' macro. - pDcanCfgPrms->testModeEnable = TRUE - pDcanCfgPrms->testMode = DCAN_TEST_MODE_EXT_LPBACK - Tx pad is workable - Rx pad is open - Tx and Rx ISR is workable. b. Silent mode can't receive test data from PCAN-USB-FD Adaptor. - comment out 'ENABLE_B2B_DCAN_TEST' macro. - pDcanCfgPrms->testModeEnable = TRUE - Modify pDcanCfgPrms->testMode = DCAN_TEST_MODE_SILENT - Tx pad is open - Rx pad can't receive test data from PCAN-USB-FD Adaptor. - Rx ISR is not workable. c. Normal operation mode can't receive/transmit test data with PCAN-USB-FD Adaptor. - Open 'ENABLE_B2B_DCAN_TEST' macro. - pDcanCfgPrms->testModeEnable = FALSE - pDcanCfgPrms->testMode = DCAN_TEST_MODE_NONE - Tx pad can't transmit test data to PCAN-USB-FD Adaptor. - Rx pad can't receive test data from PCAN-USB-FD Adaptor. - TX and Rx ISR is not workable. I trace all DCAN code but can't find why normal mode is not workable. Could you please give me some suggestion? Many thanks.

Hi Vivek, I use SDK version is V03.04.00(04-Jul-2018).

Hi Vivek, Have any update?

Hi Prince, Looks like there is an issue with Rx pin. Since you are able to receive message on PCAN when DCAN is operating in external loopback mode which means Tx pin is OK. Can you do following: 1. In case b, can you look at PCAN error and value of 'DCAN_ES' register? 2. In case c, send only one message from PCAN, and look at PCAN error and value of 'DCAN_ES' register. 3. In case c, send only one message from TDA2P(in another run), and look at PCAN error and value of 'DCAN_ES' register. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi Vivek , Thanks for your reply. I find result why the RX pad not working. SDK pad config is different with TDA2x EVM. Need modify "platform_tda2xx_pad_config.c" setting to modify RX pin of DCAN form AD17 (Wakeup0) to G19(dcan1_rx) if use TDA2x EVM. Update for all user reference.

Ticket Name: RTOS/TDA2: Dual Emif interleave 1GiB configuration

Part Number: TDA2 Tool/software: TI-RTOS Hello, Using an MLO that configures the two EMIFs on the TDA2 Vayu EVM in interleaved mode with 1GB total (2x512MB) how is the full 1GB addressed? We know 0x8000.0000 - 0xA000.0000 is part of the DDR range and we can access it but that's only 512MB. How do would you access the other 512MB of memory? Thank you Juan

Hi Juan, You should be able to access the other 512 MB from 0xA0000000-0xC0000000. Are you facing any issues with this? Regards, Rishabh

Ticket Name: Compiler/TDA2EG-17: Mirror/Flip Displaying

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi: My target operation system is 'Linux'. My project have two requirements about image transformation before displaying it. One is flipping image horizontally in ARGB8888 mode, and the other is rotating image in specified angle. My project will generate an image frame buffer by using totally computing resource on A15 core, so I don't want to waste computing resource in flipping/rotating image on A15. However, I find an enumeration (vpsissRszFlipCtrl_t from $SDK_DIR/ti_components/drivers/pdk_01_10_03_07/packages/ti/drv/vps/include/iss/vps_cfgrsz.h) which seems to indicate the flipping image mode on other core. But the usecase system seem that the flipping image mode is not supporting for ARGB8888 data format ($SDK_DIR/vision_sdk/links_fw/include/link_api/vpeLink.h). Here is the definition from vpeLink.h /**
 *******************************************************************************
 * \brief Ouput param representation for VPE link.
 *
 *
*/
typedef struct
{
    UInt32 width;
    /**< Width of the video frame or field in pixels. */

    UInt32 height;
    /**< Height of the video frame or field in lines. */

    System_VideoDataFormat dataFormat;
    /**< Output Frame data Format.
     *   VPE link is validated only for the following output dataformats
     *   1. SYSTEM_DF_YUV422I_YUYV
     *   2. SYSTEM_DF_YUV420SP_UV
     */

    UInt32 numBufsPerCh;
    /**< Number of output buffers per channel */

    UInt32 inputFrameRate;
    /**< applicable for progressive input OR when DEI bypass is TRUE
     *   inputFrameRate + outputFrameRate should be set to control required fps
     */
    UInt32 outputFrameRate;
     */
}VpeLink_OutParams; So, I wanna ask: 1. Is Vision sdk supporting for running flipping/rotating image on other core? If yes, how to do it? 2. Is TDA2's hardware supporting for outputting flipped screen directly? Thank you

Hi, Please find answers to you questions below. 1, vsdk in itself does not support, but you could EDMA to do so. 2, EDMA Rgds, Brijesh

Hi: Would you please provide some information about EDMA? Is it an software library? or an hardware device? thank you.

Hi, EDMA is HW module in SoC. Please refer to TRM for more details on EDMA. Rgds, Brijesh

Ticket Name: Linux/TDA2: How to do neon optimization for the link on the A15 core

Part Number: TDA2 Tool/software: Linux How to do neon optimization for the link on the A15 core in SDK_VISION_03_02_00_00\ti_components\algorithms have examples of optimizes for eve and C66! on A15core some code have to do neon optimization , is there any examples for this ?

Hi In VSDK, we do not have any real Algos on A15 and hence not used any neon optimization, I have kept below compiler flag to enable neon -mfpu=neon But not sure if this is sufficient to enable neon optimization on A15. Please check with GCC documentation/tutorials regards, Shiju

Hi Shiju thankS shuai

Hi Shiju where can i get GCC documentation/tutorials and i want to add -ldl for A15 Compilation options where should i add ？ thanks shuai

Hi shuai Please search on internet for GCC related queries regards, Shiju

Ticket Name: RTOS/TDA2SX: Can i use HDMI input in EVM

Part Number: TDA2SX Tool/software: TI-RTOS Hi, I am using TI TDA2xx EVM with Vision SDK Linux Environment. I need some clarifications about HDMI. I want to use USB Camera to capture frames. Can i connect USB camera to HDMI input port of the EVM via USB-HDMI Converter ?? if, Yes means which USECASE have to use.

If it supports standard HDMI output, with the supported resolution/format, it can be used. Rgds, Brijesh

Thanks for quick response, However, We are looking to use the HDMI port present in the VIsion APP Board for receiving video input, not for sending through HDMI output port of TDA2xx EVM. We are expecting this below flow, CAMERA ---> HDMI INPUT ---> VISION SDK ---> TDA2xx Regards, ARUNKUMAR

Hi Brijesh, Sorry for interrupting you, I understood, what you had explained. But, I want a usecase for camera capture. Flow : USB Camera --> HDMI Converter --> HDMI Input to Vision SDK Board

As i said, if converter can convert to standard HDMI signal, it should be possible.

Hi Brijesh Jadav, I understood, what you had answered to my question from compatibility perspective. Now I am looking for visionsdk usecase to capture and display or capture and dump to file from HDMI. For Example : TDA2xx vision SDK usecase for multides camera capture and display using the 1) "lvds_vip_multi_cam_view_sgx_display" to capture & display. 2) "lvds_vip_multi_cam_vpe_enc_null" to capture and store in file. like this above usecases, is there any usecase there to test HDMI input from visionSDK usecase ? Thanks & Regards, ARUNKUMAR V N

Not really, but you could easily add by merging two usecases. rgds, brijesh

Closing this thread as there is no further questions..

Ticket Name: TDA2SX: TDA2SXBTQABCRQ1

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2, 1. TRM里关于DEVICE 的watchdog与DATASHEET里不一致，如下两张图红色部分 2. TDA2中watchdog一共有几个？具体是监控哪些功能模块？我司这边针对TDA2的功能模块划分参考TDA2 safety manual Chapter 3.8的下一级章节； 麻烦给个清单说明位于哪里的watchdog监控了哪些功能模块。

Hi, Could you please post the question in English? Regards Karthik

1. The state of TDA2SX in the TRM and datasheet is different. The device includes one watchdog timer in the TRM, while includes two watchdog timer in the datasheet. Why？ Can you explain?

2. How many watchdogs in TDA2SX? And which module are monitored by the watchdog? The module in TDA2SX can refer to the next level of safety manual chapter 3.8, for example, MPU subsystem, DSP subsystem, NOC L3 interconnect subsystem and OCMC subsystem etc. It would be better if you give a list of watchdog classification, and its corresponding monitoring module. Thank you!

Hi, I noticed that you already asked this question on a different thread: https://e2e.ti.com/support/processors/f/processors-forum/997911/tda2sx-tda2sxbtqabcrq1 I'm closing this duplicate post. Regards Karthik

Ticket Name: TDA2EXEVM: XDC out of memroy when running TIDLOD usecase

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi sir, I was running raw TI tidlOD usecase with 1280x720 resolution model. I got a run time error: [2020-03-10 16:41:53.578] [IPU1-0]     24.989446 s:  GRPXSRC: Create in progress !!!
[2020-03-10 16:41:53.578] [IPU1-0]     24.990453 s: 
[2020-03-10 16:41:53.578] [IPU1-0]     24.990514 s:  ### XDC ASSERT - ERROR CALLBACK START ### 
[2020-03-10 16:41:53.578] [IPU1-0]     24.990575 s: 
[2020-03-10 16:41:53.578] [IPU1-0]     24.990849 s: out of memory: handle=0x86ade77c, size=4293584896
[2020-03-10 16:41:53.578] [IPU1-0]     24.990941 s: 
[2020-03-10 16:41:53.578] [IPU1-0]     24.990971 s:  ### XDC ASSERT - ERROR CALLBACK END ### 
[2020-03-10 16:41:53.578] [IPU1-0]     24.991032 s: 
[2020-03-10 16:41:53.578] [IPU1-0]     24.991429 s: ti.sysbios.heaps.HeapMem: line 221: ti.sysbios.heaps.HeapMem: line 221: out of memory: handle=0x86ade77c, size=4293584896
[2020-03-10 16:41:53.578] [IPU1-0]     24.991581 s:  UTILS: MEM: Memory allocation failed due to  insufficient free memory, requested - -1382400 
[2020-03-10 16:41:53.593] [IPU1-0]     24.991673 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1023 
[2020-03-10 16:41:53.593] [IPU1-0]     24.991795 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 243232 B (237 KB)
[2020-03-10 16:41:53.593] [IPU1-0]     24.991947 s:  SYSTEM: Heap = SR_OCMC              @ 0x00000000, Total size = 0 B (0 KB), Free size = 0 B (0 KB)
[2020-03-10 16:41:53.593] [IPU1-0]     24.992100 s:  SYSTEM: Heap = SR_DDR_CACHED        @ 0x8a783000, Total size = 355979264 B (339 MB), Free size = 65602048 B (62 MB)
[2020-03-10 16:41:53.593] [IPU1-0]     24.992283 s:  SYSTEM: Heap = SR_DDR_NON_CACHED    @ 0xbfb00000, Total size = 127360 B (0 MB), Free size = 92800 B (0 MB)
[2020-03-10 16:41:53.593] [IPU1-0]     24.992435 s:  Assertion @ Line: 389 in C:/PROCESSOR_SDK_VISION_03_07/vision_sdk/apps/src/rtos/modules/grpxSrc/grpxSrcLink_tsk.c: status == SYSTEM_LINK_STATUS_SOK : failed !!!
[2020-03-10 16:41:53.593] [IPU1-0]     24.993198 s:  Assertion @ Line: 389 in C:/PROCESSOR_SDK_VISION_03_07/vision_sdk/apps/src/rtos/modules/grpxSrc/grpxSrcLink_tsk.c: status == SYSTEM_LINK_STATUS_SOK : failed !!! I'm wondering why it is out of memory, what is the max resolution for model can be ran on TDA2? Can you also suggest me how to fix it? Thank you, Gary

Hi, [2020-03-10 16:41:53.578] [IPU1-0] 24.990849 s: out of memory: handle=0x86ade77c, size=4293584896 From the log I noticed, The size seems to be the wrong value, So please check why this parameter is set wrong value. Thanks Gaviraju

Hi Gaviraju, Where should I check this value? Thank you, Gary

Hi, Assertion @ Line: 389 in C:/PROCESSOR_SDK_VISION_03_07/vision_sdk/apps/src/rtos/modules/grpxSrc/grpxSrcLink_tsk.c: status == SYSTEM_LINK_STATUS_SOK : failed !!! Please check in the above file. Thanks Gaviraju

Ticket Name: TDA2HV: Linux and RTOS requirements and limitations

Part Number: TDA2HV Other Parts Discussed in Thread: TDA2 Hello, We are analysing the Linux and RTOS operative system. What minimun memory (Flash, RAM) requirements we have for each Operative System? What is the minimun time for starting up for each operative system (fast boot for RTOS is 500ms, right? Is fast boot available for Linux)? Can you rate the required work for porting the project? (TDA2px)RTOS -> (TDA2px)Linux (TDA2px)Linux-> (TDA2px)RTOS (TDA2px)RTOS -> (TDA4)OpenVX (TDA2px)Linux-> (TDA4)OpenVX. Best regards, Andrés

Hi, Generally, we have 2GB RAM for all TDA2xx device family soc & 1GB is enough to boot both Linux & RTOS OS, Please refer to the TRM to know the flash memory. RTOS Fast boot is available only for the TDA3xx platform & Linux Fast boot is supported only in TDA2xx platform. Refer to the below wiki page to know about the fast boot in Linux. Refer to the TDA3xx user-guide to run the fast boot use-case on RTOS file:///C:/PROCESSOR_SDK_VISION_03_08_00_00/vision_sdk/docs/UserGuides/VisionSDK_UserGuide_TDA3xx.pdf Run the fast boot use-case according to user-guide instructions to know the time taken by the RTOS for fast boot For porting (TDA2px)RTOS -> (TDA2px)Linux (TDA2px)Linux-> (TDA2px)RTOS Can you add more details on what you are trying to port from RTOS to Linux & Linux to RTOS? Are you trying to port the vision SDK use-case from RTOS to Linux & vice versa? For porting (TDA2px)RTOS -> (TDA4)OpenVX (TDA2px)Linux-> (TDA4)OpenVX. Can you add more details? what you are trying port from TDA2px RTOS to TDA4 & TDA2px Linux to TDA4? Thanks Gaviraju

Hello Gaviraju, So, the minimun RAM memory needed would be 1GB for both cases, and the Operative System Selection does not affect the RAM size selection, right? Would be possible a smaller RAM than 1GB for some cases? We would like to fit the RAM memory size for reducing the BOM cost for our project, Can you support in that way? Only for confirm, the fast boot is only available from Linux for TDA2HV and TDA2px, right? Regarding to porting, we would like to know the possibilities for porting some AlgorithmLink_Plugins we have and the few Usecases from RTOS -> Linux and from Linux -> RTOS. For the future task, we are managing the possibility of migrate to TDA4x with OpenVX operative system and we would like to know what is the easier way from TDA2xx RTOS or TDA2xx Linux. Best regards, Andrés

Hi, Please ask the question related to RAM, Flash, any resource in this thread : The Linux fast boot is supported in all TDA2xx families of SOC but we tested only in TDA2Ex, TDA2Px, TDA2xx platforms. If you are familiar with the vision SDK framework then it's a 2 weeks effort to port the algorithm plugin from RTOS to Linux & vice versa. I'm not familiar with the OpenVX framework, so no idea about porting from TDA2px to TDA4. I will check with the team & let you know. Thanks Gaviraju

Hi, Please go through the below thread to know about the transition from tda2 - tda4 https://e2e.ti.com/support/processors/f/791/t/895725 Thanks Gaviraju

Ticket Name: RTOS/TDA2: Bit-stream input files for running NullSrc, Decode and Display UC of VSDK Linux

Part Number: TDA2 Tool/software: TI-RTOS Hello, We are using the standard TDA2 RVP image and execute the network use cases. We are able to capture and stream the RAW/YUV and MJPEG format to TDA2 RVP board. Now we would like to execute H246 format. Found the related ticket and H246 binary "streams_1920x1080/1920x1080_00.h264" at "e2e.ti.com/.../693296" We are able to see the video using VLC with H246 demux. On TDA2 RVP: Selected: " 2: Network RX + Decode + Display (TDA2x ONLY)" On PC tool side exectued command: ./network_tx.out --host_ip 192.168.1.101 --target_ip 192.168.1.201 --port 29171 --verbose --files ./streams_1920x1080/1920x1080_00.h264 We are getting following errors: [IPU1-0] 407.492954 s: DECLINK:ERROR in Declink_jpegDecodeFrame.Status[-1] [IPU1-0] 407.507350 s: DECODE: ERROR: ALGPROCESS FAILED (status=0xffffffff) !!! [IPU1-0] 407.507472 s: DECLINK:ERROR in Declink_jpegDecodeFrame.Status[-1] [IPU1-0] 407.569389 s: DECODE: ERROR: ALGPROCESS FAILED (status=0xffffffff) !!! [IPU1-0] 407.569541 s: DECLINK:ERROR in Declink_jpegDecodeFrame.Status[-1] [IPU1-0] 407.588696 s: DECODE: ERROR: ALGPROCESS FAILED (status=0xffffffff) Please let us know how to execute the H246 data steaming. Thanks, KK

KK The streams that you used is meant for below Vision SDK Linux UC 5: NullSrc + Decode + Display (Only 1920x1080 H264/MJPEG Video Input Bit-Stream Supported) for Bios based file read from SD card or Network, you need the .hdr file in binary format. so I would suggest you to first try 4: 1CH VIP Capture + Encode + Network TX (TDA2x ONLY) get the bit stream files stored on PC, use this files to run 2: Network RX + Decode + Display (TDA2x ONLY) regards, Shiju

Hello Shiju, Thanks for the information, As mentioned, I am able to work with YUV and MJPEG. Out test trials can be found in ticket: e2e.ti.com/.../707133 Is H246 support available in BIOS or only in Linux? Regards, KK

Hi KK H264 is available on both VSDK Bios and Linux regards, Shiju

Hello Shiju, Thanks for the information, Could you provide steps to test the H246 (receive and transmit) on BIOS. Thanks, KK

Hi KK please refer VisionSDK_UserGuide_NetworkTools.pdf regards, Shiju

Hello Shiju, We read through the doc vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_NetworkTools.pdf We have info about RAW/YUV/MJPEG, which we have tested okay, We were not able to find H246 (Tx and Rx)details, let us know the section or the procedure. Thanks, KK

KK please refer the UC under \vision_sdk\apps\src\rtos\usecases\network_rx_tx how run is explained in VisionSDK_UserGuide_NetworkTools.pdf regards, Shiju

Hello Shiju, UC tried under \vision_sdk\apps\src\rtos\usecases\network_rx_tx are: 1. networkRxDisplay 2. networkRxDecDisplay 3. networkTxCapture 4. networkTxEncCapture Dec and Enc uses MJPEG format. All this are working okay, please refer to link : e2e.ti.com/.../707133 We did not find H246 in doc of VisionSDK_UserGuide_NetworkTools.pdf. Could you please guide us Thanks, KK

since the discussion is in progress, it is not yet resolved.

Hi KK You are right the Network UC 2. networkRxDecDisplay only support MJPEG decode as of today. But the FW support both H264 and MJPEG, its only a matter of modifying the UC to use H264. Please modify 2. networkRxDecDisplay UC to use H264 instead of MJPEG Please refer another UC \vision_sdk\apps\src\rtos\usecases\vip_single_cam_view_encdec, file name" chains_vipSingleCam_EncDec_Display.c to know how you can configure H264 code. regards, Shiju

Ticket Name: RTOS/TDA2: vpe dei and scaling

Part Number: TDA2 Tool/software: TI-RTOS I want to use vpe's dei and scaling at the same time, but it's work. Please help me tto check it . // for Deinterlace static Void setVpe_deiPrm(
                                             VpeLink_CreateParams *pPrm,
                                             UInt32 captureOutputWidth,
                                             UInt32 captureOutputHeight)
{
    UInt32 outId, chId;
    VpeLink_ChannelParams *chPrms;

    memset(pPrm, 0, sizeof(*pPrm));

    pPrm->enableOut[VPE_LINK_OUT_QUE_ID_0] = TRUE;
    pPrm->enableOut[VPE_LINK_OUT_QUE_ID_1] = FALSE;

    for(outId=0; outId<VPE_LINK_OUT_QUE_ID_MAX; outId++)
    {
        for (chId = 0; chId < VPE_LINK_MAX_CH; chId++)
        {
            chPrms = &pPrm->chParams[chId];
            chPrms->outParams[outId].numBufsPerCh =
                                     10;//VPE_LINK_NUM_BUFS_PER_CH_DEFAULT;
            chPrms->outParams[outId].inputFrameRate  = 120;
            chPrms->outParams[outId].outputFrameRate = 120;

            chPrms->outParams[outId].width  = captureOutputWidth;
            chPrms->outParams[outId].height = captureOutputHeight;
            chPrms->outParams[outId].dataFormat = SYSTEM_DF_YUV420SP_UV;

            chPrms->deiCfg.bypass = FALSE;

            chPrms->deiCfg.inpMode = VPE_DEI_EDIMODE_LUMA_CHROMA;
            chPrms->deiCfg.tempInpEnable = TRUE;
            chPrms->deiCfg.tempInpChromaEnable = TRUE;
            chPrms->deiCfg.spatMaxBypass = TRUE;
            chPrms->deiCfg.tempMaxBypass = TRUE;

            chPrms->scCfg.bypass       = TRUE;
            chPrms->scCfg.nonLinear    = FALSE;
            chPrms->scCfg.stripSize    = 0;

            chPrms->scCropCfg.cropStartX = 0;
            chPrms->scCropCfg.cropStartY = 0;
            chPrms->scCropCfg.cropWidth  = 0;
            chPrms->scCropCfg.cropHeight = 0;
        }
    }
} // for scaling static Void setVpePrm(
                    VpeLink_CreateParams *pPrm,
					UInt32 numLvdsCh,
					UInt32 OutWidth,
					UInt32 OutHeight,
					UInt32 inCropWidth,
					UInt32 inCropHeight)
{
    UInt32 chId;
    UInt32 outId = 0;

    pPrm->enableOut[0] = TRUE;
    for (chId = 0; chId < numLvdsCh; chId++)
    {
        chPrms = &pPrm->chParams[chId];
		chPrms->outParams[outId].numBufsPerCh =
			VPE_LINK_NUM_BUFS_PER_CH_DEFAULT;

        chPrms->outParams[outId].width = OutWidth;
        chPrms->outParams[outId].height = OutHeight;
        chPrms->outParams[outId].dataFormat = SYSTEM_DF_YUV420SP_UV;

        chPrms->scCfg.bypass       = FALSE;
        chPrms->scCfg.nonLinear    = FALSE;
        chPrms->scCfg.stripSize    = 0;

        chPrms->scCropCfg.cropStartX = 0;
        chPrms->scCropCfg.cropStartY = 0;
		chPrms->scCropCfg.cropWidth  = inCropWidth;
		chPrms->scCropCfg.cropHeight = inCropHeight;
    }
}

sorry for error.: but it does not work.

the chains is : Capture -> VPE_dei -> Dup_rec -> VPE_swms -> Sync_swms -> Alg_DmaSwMs -> Encode -> Null_rec (A15)

Hi, Are you trying to create 2 different instances of VPE link and using 1 for scaling and 1 for dei? Regards, Anuj

VPE_dei and VPE.I could not understatnd your mean. Can you provided more details? My inial as below:     setVpe_deiPrm(
            &pUcObj->VPE_deiPrm,
            pObj->captureOutWidth,
            pObj->captureOutHeight);

    setVpePrm(
           &pUcObj->VPE_swmsPrm,
           pObj->chainsCfg->numLvdsCh,
            swWinWidth,
           swWinHeight,
pObj->OutWidth,
pObj->OutHight);

Hi, Please take a reference of the below file to set Vpe_dei prm vision_sdk/apps/src/rtos/alg_plugins/objectdetection/fpcompute2/vpe_resizer.c Regards, Anuj

Ticket Name: TDA2PHV-ACD: L3 Firewall

Hello All, We have a Safety goal for a Buffer which is shared between DSP1 and IPU_C0. This buffer must be verified on each frame for possible corruption. It must not be corrupted once it fixed. Verifying each bit of buffer data for every frame is costly and time consuming. We are looking for an approach that can protect the Buffer against any memory corruption Instead of verifying Buffer for every frame. We are thinking to implement L3 firewall to protect this buffer. We are using TDA2PHV. If we read the code then it seems its General purpose device. Does this device support L3 firewall? Can we implement firewall to protect the buffer? Please guide us. Please let us know if you have other approach. Best regards, Naresh

Hi Naresh, can you check this Application Note and see if it can give you some directions: Regards, Yordan

Dear Yordan, Thank you for the document. We are working on TDA2PHV. There is no any mentioned the L3 firewall support or not on TDA2P. Can you please help me to find out which L3 firewall will support or not on General purpose TDA2PHV? Here is the list of Variant for TDA2P and we are using TDA2PHV. • TDA2PHA • TDA2PHG • TDA2PHV • TDA2PSX Best regards, Naresh

Ticket Name: TDA2SX: L3 Custom Error

Part Number: TDA2SX Hi, EVM board:VAYU EVM XC5777X CPU BOARD SDK3.07 Customer uses configuration tda2xx_evm_linux_all, and he doesn't modify the sdk. The following error may appear when the device starts loading multi-core, the probability is about 10% [ 10.551985] ------------[ cut here ]------------ [ 10.551993] WARNING: CPU: 0 PID: 101 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x25c/0x368() [ 10.551997] 44000000.ocp:L3 Custom Error: MASTER DSP1_MDMA TARGET L4_PER3_P3 (Read): Data Access in User mode during Functional access [ 10.552053] Modules linked in: dwc3(+) udc_core virtio_rpmsg_bus(+) bc_example(O) extcon_usb_gpio ahci_platform libahci_platform libahci libata scsi_mod omap_sham pvrsrvkm(O) omap_des omap_aes_driver c_can_platform c_can can_dev omap_rng dwc3_omap rng_core extcon rtc_omap omap_remoteproc remoteproc virtio virtio_ring sch_fq_codel [ 10.552057] CPU: 0 PID: 101 Comm: kworker/0:2 Tainted: G W O 4.4.84-00038-g0af2ab5 #1 [ 10.552059] Hardware name: Generic DRA74X (Flattened Device Tree) [ 10.552066] Workqueue: events_freezable thermal_zone_device_check He used the SDK3.08 version before and found the same problem (the probability is much higher than SDK3.07) www.ti.com.cn/.../PROCESSOR-SDK-TDAX

Hi, Is the behavior also seen on the TDA2-EVM or a custom board? Can you please confirm that so that I can check this further on my side. Regards Karthik

Hi， He test on the VAYU EVM XC5777X CPU BOARD.

Hi, Any update?

Hi Nancy, On the older J6 releases, some firmwares were making an access to a region that it was prohibited to do so, this happened only during the boot up. This is a warning to indicate that this happened. There is no impact due to this, please treat this as a warning from the SDK binary. Regards Karthik

Ticket Name: RTOS: TDA2 Host Emulation Build for Source Package Build error

Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hello, I follow "Ti Deep learning Library User Guide April 2018" to build source in host emulation. in path：C:\PROCESSOR_SDK_VISION_03_01_00_00\ti_components\algorithms\REL.TIDL.00.08.00.00\modules\ti_dl step1 "E:\Program Files (x86)\Microsoft Visual Studio 11.0\VC\vcvarsall.bat" step2 gmake CORE=eve TARGET_BUILD=debug TARGET_PLAT=PC all then, I got error C:\PROCESSOR_SDK_VISION_03_01_00_00\ti_components\algorithms\REL.TIDL.00.08.00.0 0\modules\ti_dl>gmake CORE=eve TARGET_BUILD=debug TARGET_PLAT=PC all . ======== tidl ALGO ================= gmake -C ./algo -f makefile gmake[1]: Entering directory `C:/PROCESSOR_SDK_VISION_03_01_00_00/ti_components/ algorithms/REL.TIDL.00.08.00.00/modules/ti_dl/algo' /PROCESSOR_SDK_VISION_03_01_00_00/ti_components/algorithms/REL.TIDL.00.08.00.00/ makerules/rules.mk:383: *** multiple target patterns. Stop. gmake[1]: Leaving directory `C:/PROCESSOR_SDK_VISION_03_01_00_00/ti_components/a lgorithms/REL.TIDL.00.08.00.00/modules/ti_dl/algo' gmake: *** [all] Error 2 rules.mk:383: dir: $(OBJDIRS) How could I solve the error ? Thanks, Ting

Hello, More question Q1：Is "Ti Deep learning Library User Guide " for TDA2 RTOS or Linux ? Q2：Is Vision_SDK tidl for TDA2 RTOS or Linux ? Q3：Is tidl for RTOS and Linux ? I just build for getting net.bin and param.bin, and files for two systems to use ? Thanks, Ting

Hi Ting, There is latest TIDL release available, please download it from VSDK from http://www.ti.com/tool/PROCESSOR-SDK-TDAX Regarding build source in host emulation, for this you need access to source release of TIDL which is not part of VSDK. You may have to contact your local TI FAE to get access to it. You do not need source release of TIDL to import your models and get net.bin and param.bin files, for this refer to section "3.6 Running a Model trained by user" in the "TI Deep learning Library User Guide". This Vision_SDK tidl is for TDA2 RTOS only. Thanks, Praveen

Hi Praveen Thanks for your reply. I think I don't ask clearly, so I follow your reply and confirm that. Downloading the Vision_SDK, I can get the "usecases\tidl_OD" and "REL.TIDL.01.01.03.00", then first is for RTOS to recognize object and the other is for generate net.bin and param.bin Q1："Is C:\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\apps\src\rtos\usecases\tidl_OD" for RTOS ? Q2："Is "C:\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\algorithms\REL.TIDL.01.01.03.00\modules\ti_dl" not build source release of TIDL? is it for Linux or RTOS ? We think it is just for generate net.bin and param.bin, we don't care about it is for linux or RTOS, right ? Q3：If we want to build linux for TDA2 and run tidl, do you have some advices or documents, or I should create a new issue for this question ? Thank, Ting

Q1："Is C:\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\apps\src\rtos\usecases\tidl_OD" for RTOS ? Answer : Yes Q2："Is "C:\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\algorithms\REL.TIDL.01.01.03.00\modules\ti_dl" not build source release of TIDL? Answer : Yes is it for Linux or RTOS ? We think it is just for generate net.bin and param.bin, we don't care about it is for linux or RTOS, right ? Answer : Yes Q3：If we want to build linux for TDA2 and run tidl, do you have some advices or documents, or I should create a new issue for this question ? Answer : You can refer to this thread https://e2e.ti.com/support/processors/f/791/t/777773 Thanks, Praveen

Hi Praveen Thanks for your reply. Q1：About answer of Q3, Is it for rebuild DL model, like ".caffemodel", and convert to tidl for RTOS or Linux ? Q2：About answer of Q3, Is it for linux(make), I think it could also run from windows(gmake) ? is it anything different ? Q3：in RTOS, we can run "usecases/tidl/" to demo result of ObjectDetection, is any project for linux to demo result on TDA2 ? Thank, Ting

Hi Ting, Regarding the answer of Q3, those steps are to build only import tool in the Linux. We do not have any references to run demo in Linux. Thanks, Praveen

Hi Praveen Thanks for your reply. Thank, Ting

Ticket Name: TDA4VM-Q1: TIDL/Host Emulation performance is poor, how to improve?

Part Number: TDA4VM-Q1 Other Parts Discussed in Thread: TDA2, TDA4VM Hi, We have similar issue with https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1092091/tda4vm-psdk-rtos-j721e-tidl-inference-host-emulation-execution-time We're using SDK 7.3 but I think it's a common issue no matter which SDK is using now. Now we're running multiple images at the same time on top of multi-core CPU to accelerate but it consumes a lot of computing resources. Please help to clarify whether there are other ways to speed up host emulation. Previously in TDA2, tidl provided a special nature C operation model. This mode provides better host emulation. Customer can also get the same results as on the board. Any similar approach on TDA4VM? Thank you.

Hi, James Austrial said: We have similar issue with https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1092091/tda4vm-psdk-rtos-j721e-tidl-inference-host-emulation-execution-time The solution is same as what is mentioned in the above thread. Regards, Anshu

Ticket Name: Linux/TDA2: TDA2x ADAS data flow -LVDS surround view could not output display

Part Number: TDA2 Tool/software: Linux Hi, We would like to run the use-case via 4 LVDS cameras capture (OV10635 sensor) in Vision SDK to output display on TDA2X boards. But it outputs black screen even though burned prebuilt image(software-dl.ti.com/.../index_FDS.html) Could you help provide some suggestion to look into the problem? Thanks. BTW, my configuration: "tda2xx_evm_linux_all", why the default config (tda2xx_evm_linux_all/cfg.mk) is "no"? PROC_IPU1_0_INCLUDE=no PROC_IPU1_1_INCLUDE=no Could you also help teach me how to makeconfig for the use-case? Thanks. regards, Sam Hsieh

In case of linux we have moved code running on ipu 1_0 and ipu1_1 to ipu2 ipu2 operates in smp mode. Please check the pin settings of video conf to check why blan screen. Refer user guide Regards Chetan.M

log_app.txtHi @Chetan.M I don't understand clearly how to migrate from ipu1 dual core to ipu2, and ipu2 operated in smp mode. Could you help instruct me how to configure it in details ? Thanks. As user guide descripted : modify the tda2xx_evm_linux_all/cfg.mk , Include: PROC_IPU1_0_INCLUDE=yes PROC_IPU1_1_INCLUDE=yes PROC_IPU2_INCLUDE=yes PROC_DSP1_INCLUDE=yes PROC_DSP2_INCLUDE=yes PROC_EVE1_INCLUDE=yes PROC_EVE2_INCLUDE=yes PROC_EVE3_INCLUDE=yes PROC_EVE4_INCLUDE=yes PROC_A15_0_INCLUDE=yes but it got the compilation failure which error message as attached: At the same time, I observed that the comment in cfg.mk file # IPU1 (core 0 & 1 are) not supported when IPU_PRIMARY_CORE=ipu2 Do you think whether if I need to modify the IPU_PRIMARY_CORE & IPU_SECONDARY_CORE ? BR, Sam Hsieh >>>>> Compilation failure /home/sam/ADAS/VISION_SDKv3_3/vision_sdk/build/rtos/makerules/rules_m4.mk:172: recipe for target '/home/sam/ADAS/VISION_SDKv3_3/visi 1877 make[6]: *** [/home/sam/ADAS/VISION_SDKv3_3/vision_sdk/binaries/apps/tda2xx_evm_linux_all/obj/links_ipu_iva/tda2xx-evm/ipu2/release/ 1878 make[6]: Leaving directory '/home/sam/ADAS/VISION_SDKv3_3/vision_sdk/links_fw/src/rtos/links_ipu/iva' 1879 /home/sam/ADAS/VISION_SDKv3_3/vision_sdk/build/rtos/makerules/common.mk:235: recipe for target 'ipu2' failed 1880 make[5]: *** [ipu2] Error 2 1881 make[5]: Leaving directory '/home/sam/ADAS/VISION_SDKv3_3/vision_sdk/links_fw/src/rtos/links_ipu/iva' 1882 Makefile:19: recipe for target 'links_ipu_iva' failed >>>>

In case of linux , IPU1_0 and ipu1_1 should be disabled . IPU2 is enabled . Your device has 2 dual core ipu hence in case of linux we enable the ipu2 as SMP . User need not change any configuration . Regards Chetan.M

Hi @Chetan.M, It shows error message when configured "PROC_IPU1_0_INCLUDE=no" ERROR: IPU1_0 MUST be included in application: and I observed that "NEED_PROC_IPU1_0=yes" in vision_sdk/apps/src/rtos/usercases/lvds_vip_multi_cam_vie/cfg.mk. It seems like the configuration of use-case is conflict. Could you help correct me if there is any mistake in the configuration? Thanks. BR, Sam Hsieh

Sam, These errors can be ignored , In case of linux IPU1_0 and ipu1_1 will not be used , it is disabled . Internally there are changes in the code which will run all the links created on IPU1_0 and ipu1_1 to ipu2 Regards Chetan.M

Hi @Chetan.M, Thanks for your suggestion. I disabled IPU1_0 and IPU1_1, try to move the codes implementation from IPU1 to IPU2 then try to rebuild it. If there is any further update, I also post the result. BR, Sam Hsieh

Hi @Chetan.M, I observed that there is some package (PDK) default core "ipu1_0" which configured in cfg.mk Then revise it by CORE=ipu2 But I still got the compiling failure when make links_fw_libs: make[5]: *** [arp32_4] Error 2 make[5]: Leaving directory '/home/sam/ADAS/VISION_SDKv3_3/vision_sdk/links_fw/src/rtos/links_common/system' Makefile:19: recipe for target 'links_common_system' failed make[4]: *** [links_common_system] Error 2 Could you help solve the compiler failure ? Thanks. BR,log_app_07_05_2018.txt Sam Hsieh

Hello Sam Hsieh Can you please help me understand , You are trying to run the default usecase .? Please revert all the changes and do a build and run . Regards Chetan.M

Hi @Chetan.M, I could rebuild successfully after refresh install all packages. including tda2xx_evm_bios_all and tda2xx_evm_linux_all usecase. But I don't why the compileration failure occurred, it perhaps I made a mistake in makerules. Thanks for your instruction. :) regards, Sam.

Ticket Name: RTOS: Emulator and TDA2x has different result with TIDL(version 01.01.03).

Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hello, I have test my own model using TIDL(version 01.01.03). I recently found that the PC emulator and TDA2x generate different results. I have checked each layer dump , discovering a convolution layer gives different output. Furthermore, I checked the layer result which gives different output and found another strange phenomenon. My convolution layer has 96 input channels and 192 output channels with group = 8 and kernel size = 3. The output feature maps is different at 0th, 24th, 48th, 72th, 96th, 120th,144th, 178th. It seems that the first generated feature map in each group has different value. After that I extract the particular convolution layer to do the test which input is previous layer output.(ex: trace_dump7.y ). The result from PC emulator and TDA2x is different. I generate the TDA2x eve test and PC-emulator ,using below instruction respectively. "gmake TARGET_BUILD=release CORE=eve all" "gmake TARGET_BUILD=release TARGET_PLATFORM=PC CORE=eve all" All detail is in the appendix .rar file , including Convolution layer information , input data , PC_emulator result and TDA2x result. Thank you. TIDL_issue.rar

The PC emualtion is expected to give the same result as Target. Your build commands are right. BTW, Is the PC emualtion results matching with expected results (caffe)? Which is the first layer mismatching ?

I just check the proto file. This has only one layer. We will look in to this get back on this .

The rar does not contain, the caffe model file? Can you share the caffemodel also?

The Caffe model contains only the layer which begins to generate different output.Layer_model.rar

We have checked the output which given by PC emulator. Detection Boxes generated by PC emulator are similar to the result from Caffe.

Hi KaiNan Hsieh, We could not re-produce this issue in latest code base. Looks line one the recent fix had solved this isse as well. We will locate the right fix and share the patch soon.

Hi KaiNan Hsieh, We are not able to reproduce this issue in 01.01.03 release as well. Are you observing this issue when you the full network or with the attached single layer as well?

We found this issue when we do the detection with full network , and we dumped each layer to check which layer gives the different output. Then we test the attached single layer see if it gives the same issue which we found in full network. So this issue was found in both cases. Thank you

Hello , We have tried another case, discovering that it has different output with convolution layer on PC-simulator and TDA2x. In our test case we found the PC-simulator and TDA2x have same output when we didn't use dense convolution. Therefore , We regenerate the model by set some layer using dense convolution , and these makes the output different. Is any problem with dense convolution may cause this problem? Thank youconvolution-Issue.rar

Hi, Last thread I have mentioned that dense convolution gives different output in some case. I have built a caffe model with only 3 convolution layer and test different setting of dense convolution.(The first model import with no dense convolution and another with all dense convolution). The results are in the attached file ,including files below: import.txt , infer.txt , caffemodel , deploy.prototxrt, input data, output data from TDA2 and PC-simulator. I used the command "gmake TARGET_BUILD=release TARGET_PLATFORM=PC CORE=eve all" to generate eve_release_out.exe and generate the PC-simulation result. Use "eve_release.out" which is existed in the testcv/out folder to generate the TDA2 result. Thank you, ti_conv_issue.rar

Hi KaiNan Hsieh, Could you please provide the version of your TIDL? I can get incorrect result with your eve_test_dl_algo.out.exe, but get correct result with TIDL 1.1.3. Please provide your import tool binary to make sure I can reproduce it. So you mean that PC-simulation is not align with the inference on TDA2 target? Your prototxt has 3 conv layers, only the third layer can be configured as dense conv. All 3 layers are not aligned or only the third layer is incorrect? Thanks & Best Regards! ZM

Hi, I can reproduce it now(first channel of each group of the third layer is not aligned with PC tool). and get back to you later. Thanks & Best Regards! ZM

Thanks for your reply. The output of these 3 layers have the same result with TDA2 and PC-simulation at first and second layers.But third layer is not align with TDA2. Only the third layer is not aligned. Thank you

Thanks, Problem is solved.

Ticket Name: TDA2: Vision SDK TDA2xx v03.02.00

Part Number: TDA2 Hello everyone: Here are my environment: Hardware: 1. TDA2xx EVM 2. TDA2xx Vision Application Board 3. 6 channel FPD-Link III FMC Daughter Board 4. 2 x OV10635 Sensor SDK: Vision SDK 3.0.2 I can run use case "vip_single_cam_sgx_display" with single OV10635 connected to P1. Now, I'm trying to run use case "lvds_vip_multi_cam_view_sgx_display". BUT when I'm using daughter board that two OV10635 camera connected to, the kernel stop at "[ OK ] Started Synchronize System and HW clocks." and then reboot again and agin. I try to remove one of the camera and there is no problem at all. And I also try to use Automotive SDK, the result is the same. My question is "Can I use only two cameras? How can I do that?" Thanks in advance

Hi, Multi cam usecase uses 4 camera, the buffers get displayed on screen only when all four cameras are feeding video. This won't work with 2 camera only. Single cam usecase uses only 1 camera, connect it to the cam6 port of the multides board. This will get the single cam usecase working. Refer to the user guide for more details on camera connections Regards, Nikhil D

Ticket Name: TDA2: TDA2 CPU Selection Issues

Part Number: TDA2 Dear E2E: Project: streaming media rearview mirror project, Now it was in selection station. Due to the inconsistent camera resolution and LCD resolution,it need to do some processing. The current competitor is Renesas Iw8836 720p/iw8845 1080p, customers ask TI whether there are similar cost-effective product recommendations. Thank you. Customer needs are as follows Camera input signal 1280*800, LCD resolution is about 1280*400. The Camera image can be converted to the LCD with integrated storage. Video ICs or CPUs with integrated Video ICs are fine. thanks .

hello, You can refer to this page for guidance and additional details for your use-case http://www.ti.com/processors/automotive-processors/tdax-adas-socs/applications/mirror-replacement-system.html I would recommend TDA3x for the system you describe. regards Kedar

Ticket Name: TDA2: How to utilize 4 EVE engine for TDA2

Part Number: TDA2 Hi team, My customer is evaluating TDA2 processor for a front camera application. The customer run Object Detection Usecase from Vision SDK. From the box this use case have 4 EVE cores utilized by 50-55% and give ~10fps. The customer have modified the usecase to use 2 EVE cores. The modified example utilizes 2 EVE cores by 98-100% and give same 10fps. How we can utilize 4 EVE cores by 100% and get 20fps?

Hi, Can you tell me which usecase are you using? As there is no object detection usecase which uses 4 EVEs. Is there any modification done on any usecase? We will be able to siggest better if you lets us know the usecase path and the modification done on that usecase. Regards, Anuj

Hi, Its benn very long since any update on this issue, Is it still open? Regards, Anuj

Ticket Name: [TDA4M] EMIF avatar tool

Other Parts Discussed in Thread: TDA2 Hi~ I want to find the best register through DDR4 stress test. At tda2 there was an avatar EMIF TOOL.( www.ti.com/.../SITARA-DDR-CONFIG-TOOL TOOL&tisearch=Search-EN-everything) There was a 0.3 version of the EMIF tool, so I tested ddr4 on uboot. Do you have avator EMIF TOOL in tda4? And ask if you can provide it later. thanks Regards, kyungtae

Kyungtae, The EMIF DDR tool is available on CDDS: https://cdds.ext.ti.com/ematrix/common/emxTree.jsp?objectId=28670.42872.34616.54449&amp;fromContent=true Regards, Kyle

Hi, Kyle. As I mentioned, the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool.xlsm file already knows.(version 0.3) this EMIF TOOL extracts the register for the DDR I want. Create register with dts file and gel file. But what I want is AVARTAR EMIF TOOL which does DDR trainning like TDA2. At TDA2 (AVARTAR_EMIF_TOOL) creates a project in CCS to extract the optimal register after DDR stress test. I mean this Avartar emif tool. Thanks, Regards, kyungtae

Hi Kyungtae, The TDA2x Avatar_EMIF_Tool did contain a CCS project that swept DLL values to optimize settings and account for system level timing skews. Similarly, the TDA4M has hardware algorithms inside the PHY which perform a similar function to optimize DLL values based on skews introduced in the system, such as the PCB routing. By using the hardware algorithms, this simplifies the procedure to quickly bring up new boards, and also allows each system to have unique settings and compensate for any board-to-board skew differences. The XLS tool Kyle has referenced already has the hardware training support enabled during initialization. Thus, the parameters are being optimized each boot cycle on TDA4M. Additional details regarding which parameters are trained can be found in section 8.2.4.7.9 (Memory Controllers -> DDR Subsystem -> DDRSS Functional Description -> DDR PHY Functional Description -> Training Support) of the TRM. Since hardware algorithms are used on TDA4M, the use of software (such as the Avatar EMIF Tools) is not required or supported. Best regards, Kevin

Hi, Kevin. Thank you for the detailed explanation. Thanks. Regards, kyungtae

Ticket Name: Linux/TDA2: how to use EDMA_UTILS_autoIncrement_triggerInChannel_v2

Part Number: TDA2 Tool/software: Linux I am using TDA2 evm SDK_VISION_03_04_00_00 i am try to copy data using pingpang EDMA biasDmaAutoIncrement_Init and EDMA_UTILS_autoIncrement_triggerInChannel_v2. in L2 pOutBufInt[2] each buffer size is width =9 height=1024 outbuf in DDR size is width =216 height=1024 how can i set biasDmaAutoIncrement_Init ? channels==24 blkWidth_out==9 blkHeight_out==1024 type of data is float. follow is what i set ,it deos not work ! initParamV2.initParams.transferProp[1].roiWidth = blkWidth_out * 4 * channels; initParamV2.initParams.transferProp[1].roiHeight = blkHeight_out ; initParamV2.initParams.transferProp[1].roiOffset = 0; initParamV2.initParams.transferProp[1].blkWidth = blkWidth_out * 4; initParamV2.initParams.transferProp[1].blkHeight = blkHeight_out; initParamV2.initParams.transferProp[1].blkOffset = 0; initParamV2.initParams.transferProp[1].extBlkIncrementX = blkWidth_out * 4; initParamV2.initParams.transferProp[1].extBlkIncrementY = 0; initParamV2.initParams.transferProp[1].intBlkIncrementX = 0; initParamV2.initParams.transferProp[1].intBlkIncrementY = 0; initParamV2.initParams.transferProp[1].extMemPtrStride = blkWidth_out * 4* channels ; initParamV2.initParams.transferProp[1].interMemPtrStride = blkWidth_out * 4; initParamV2.initParams.transferProp[1].extMemPtr = (uint8_t *)(outBufExt); initParamV2.initParams.transferProp[1].interMemPtr = (uint8_t *)(outBufInt[0]); initParamV2.initParams.transferProp[1].dmaQueNo = 1; thanks! Shuai

Hi Shuai, sorry for the delayed responce. Can you check chapter "4.2.2 EDMA Utility Autoincrement V2" in PROCESSOR_SDK_VISION_03_05_00_00\ti_components\algorithms\REL.DMAUTILS.00.08.00.02\dmautils\docs\DMAUtilsLibrary_UserGuide.pdf and also the example in "ti_components\algorithms\REL.DMAUTILS.00.08.00.02\dmautils\test\edma_utils_autoincrement_test" and see if it helps? Regards, Yordan

Ticket Name: TDA2SX: Radar VSDK non-half-lambda antenna offest

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Using the TDA2 Cascade EVM, our custom front end has non-half-lambda antenna offset. In PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\docs\Radar\ProcessorSDKRadar_DataSheet.pdf - "3.9.1.6.3 Understanding Antenna Offsets in the board": *Here the antAzimOffs and the antElevOffs are given in half lambda spacing convention* How do we manage antenna offset in our front end where the offset distance divided by Lambda/2 are fractional not whole number?

Zach I would need to consult with radar experts here to help you. I will forward the question and get back to you. Thanks and Regards, Piyali

Hi Zach I haven't heard back from the expert yet. I will continue to follow up internally on your behalf. Thanks and Regards Piyali

Thank you Piyali, This is an open question for us still. Best, -Zach

Hello Zach, For non lambda/2 by two spacing the processing would have to be very customized based on the exact antenna configuration you have. Could you provide the reasoning for using non lambda/2 multiple spacing? Also can you provide the exact antenna pattern? regards, vivek

Hello Zach, any update on this? regards, Vivek

Ticket Name: TDA2HV: ASIL compliance for each TDA2 core

Part Number: TDA2HV Hello, Can you provide me more information about the ASIL compliance for each core into TDA2HS? Can you provide me the safety manual for TDA2HS? Best regards,

Hi User6448690, Please start by referencing www.ti.com/.../sprui16a.pdf. For ASIL compliancy of the TDA, please see this thread https://e2e.ti.com/support/processors/f/791/t/726849?Functional-Safety-ADAS. Regards, kb

Regarding ASIL compliancy of the TDA parts, please also be aware that the list of TDA products on ti.com, has a "Features" column which shows the parts ASIL rating. https://www.ti.com/processors/automotive-processors/tdax-adas-socs/products.html. Regards, kb

Ticket Name: AM5708: Video DPLL SSC support

Part Number: AM5708 Other Parts Discussed in Thread: TDA2 Hi, My customer is working om AM5708 design and has done some EMC measurements and some radiated emission levels of the display interface are to high. He looked at the DPLL_VIDEO Registers and found in table 11-48 PLL_SSC_CONFIGURATION1 a reference to the SSC feature, with a note that the SSC feature is not supported. His questions: 1) Is this going to be supported in the future? 2) Is the feature available but not tested/supported? 3) can customer use this function? Thanks in advance, Best regards, Patrick ps: why is this non supported feature part of the documentation? (On e2e i found other references to this feature in TDA2 and DRA72X devices, but also not supported. quit confusing)

Hi Patrick, SSC feature is available, but not tested, thus not verified by TI. See the below e2e threads for more info: e2e.ti.com/.../565566 e2e.ti.com/.../1964650 e2e.ti.com/.../604515 e2e.ti.com/.../633615 Regards, Pavel

Patrick Verkennis said: 1) Is this going to be supported in the future? I can not confirm. You should check in any new version of the AM57x documents regarding the status of SSC. Patrick Verkennis said: 2) Is the feature available but not tested/supported? Yes Patrick Verkennis said: 3) can customer use this function? The customer can use it, but at his own risk. The customer should fully test and validate that feature on his custom board. TI do not recommend that feature usage, if possible you should avoid it. Regards, Pavel

Ticket Name: Please anybody suggestion best algorithm to detect the algorithm like only Pedestrians, Vehicles, Traffic Signs

Hi , Please anybody suggestion or link to best way detect the algorithm like only Pedestrians, Vehicles, Traffic Signs . Regards , Sunil

Hello Sunil, Can you provide some additional detail on this request, please? Is this a vehicle-mounted sensor? One sensor or multiple sensors? What type of sensor? Any additional information you can provide will be very helpful to determine a solution. At your service, ~Leonard

Hello Sunil, you can run your algorithms very efficiently in terms of computational performance and in respect to power on TDA2x and TDA3x device families. Please check https://e2e.ti.com/blogs_/b/behind_the_wheel/archive/2017/01/05/tda-adas-solutions-enable-a-safer-driver-experience

Its vehicle mounted sensor ( camera ) , type of sensor is camera .. we mounted camera in car bumper for forward collision warning . presently we are using open cv to find pedestrian , vehicles Using C++ ..I am curious about best algorithm suitable for above case using C in TDA2x

Hi Sunil, you can check here: <VISIONSDK_03_00_inst_dir>\ti_components\algorithms\REL.200.V.OD.C66X.00.06.00.00\200.V.OD.C66X.00.06 to find object detection module for DSP. In the subdirectories you can find documentation and test examples. Regards, Yordan

Thank You Yordan

Ticket Name: TDA2: Running a different model using TIDL_OD usecase

Part Number: TDA2 Hi, I am trying run our model using TIDL_OD usecase. I have generated inHeader_OD,inData_OD, NET_OD.BIN and PRM_OD.BIN for our network and copied to the SD card.The model is not yet trained completely. The network takes input of size 512x512. In the chains_tidlOD.c I have modified some parameters as follows. #define TIDL_OD_INPUT_WIDTH (512) #define TIDL_OD_INPUT_HEIGHT (512) #define DEC_OUT_WIDTH (512) #define DEC_OUT_HEIGHT (512) For display resolution, I am maintaining the same as for default model 768x320(scaled by 2 for display). #define TIDL_OD_DISPLAY_WIDTH (1536) #define TIDL_OD_DISPLAY_HEIGHT (640) When I run the model, there are no errors, but the video is black. Even if the model contains dummy parameters, I believe we should be able to see the input video(with wrong or no detection boxes). Am I right? Do any more parameters need to be set? Thanks in advance, Navinprashath.R.R

Hi Navin, you are correct you should see something on the video , Can you run print statics "p" options and share the logs , You need to find where the frames are dropped . Regards Chetan.M

Hi Chethan, Please find the teraterm logs and the inHeader_OD.(Renamed to inHeader_OD.123 for sharing). Regards, Navinprashath.R.R inHeader_OD.123 1884.teraterm.log

Hi NavinPrashant, Can you reduce the READ fps to 5 and try , looks the frames are dropped in processing . Also change the threshold according to the performance Regards Chetan.M

Ticket Name: TDA2SX: Possibility evaluation of TDA2x + 1080p surrounded view cameras + ADAS

Part Number: TDA2SX We known multi-channel cameras based on TDA2P MIPI interface via TI official website: TDA2P + DS90UB960 or DS90UB953; but we are familiar with TDA2S platform, we developed 720p(1280*720) surrounded view cameras and ADAS function. We want to evaluate possibility of TDA2S + 1080p(1920*1080) surrounded view cameras + ADAS: 1. Surrounded view cameras: 4pcs 1080 camera raw data; 2. Please recommend serializer and deserializer:

Hi, Only the TDA2Px devices have the integrated ISP needed for processing RAW data. The TDA2xx (Including TDA2Sx) devices do not have the ISP. Is there a reason why you don't want to use the TDA2Px device for this usecase? Shashank

Because we are familiar with TDA2S plaftform and we developed mature product, TDA2S is cheaper than TDA2P, as we know TDA2P supports few CMOS sensors. if we give up integrated ISP, does TDA2S support 2 Mega surrounded view cameras ?

Please see response in teh other thread.

Ticket Name: TDA2: TDA2X: monitor can't display any signal. can't install PROCESSOR_SDK_VISION program.

Part Number: TDA2 To TI suporter: How to install SDK VISION program. I can't understand from docs. What is install and build Vision SDK, MLO and AppImage? We would like to have your fully support to setup TDA2X system. Looking forward to hearing from you soon. Thank you. Regards, Ken Huang

Hi Ken, This query is already supported in another thread. Kindly don't start new threads on same topic. Regards, Rishabh

Hi, Ok, sorry. I worried about another thread is be resovled and not notice. you can delete it. Regards, Ken Huang

Hi Ken, Ok I am closing this thread. Regards, Rishabh

Ticket Name: TDA2SX: Max Ethernet bitrate

Part Number: TDA2SX Hi, I am running the TDA2SX board with an AWR1243 attached for cascade radar imaging with the processor SDK radar (RTOS). I'm looking for the maximum bitrate that the TDA2SX is able to output through an ethernet connection to my PC. Thanks, Stefan

Hi Stefan, Sorry for late reply. The TDA2xx throughput numbers are part of NSP data sheet. You can access data sheet @PROCESSOR_SDK_VISION_xx_xx_xx\ti_components\networking\nsp_gmacsw_4_15_00_00\docs\nsp_vayu_datasheet.pdf Regards, Prasad

Ticket Name: TDA2: How to run pose model based TIDL SEG use case in Vision SDK with pre-trained model

Part Number: TDA2 hi, dear 1， Is there any tips about changing the seg configuration files to run user model like my pose reg model? 2， Beside these facts above, the output of my pose model is not the limited classification but arbitrarily float32 value. So from the link that you offer me before, I do not know if it will work successfully by just commenting the classfications.(this Line : tempoutPutList->objDesc[tempoutPutList->numObjects].objType = (label - 1); need to be changed to " (label - 1)%3 ") Any other change should be made? 3，In fact, in my case only, if I use this case called "chanis_tidl – File IO based use case to validate user model ", it is better to bring up? If so, could you offer me some tips for changing this demo to my own pose mode recog demo?This case is similar to my pose reg demo, and I want to test the performance of the mode only, not for accuracy which maybe need only one image like in.RGB, right? And how to translate my jpg image to the in.RGB format? Good luck, tks!

Hi, 1. I will check and come back on this. 2. Line : tempoutPutList->objDesc[tempoutPutList->numObjects].objType = (label - 1)%3; This modulo 3 is because, currently VSDK supports only four colour codes for display. This means it can display all the 21 objects but can use only 4 colours as below, Class 0, 4 , 8... uses first colour Class 1, 5, 9... uses second colour Class 2, 6, 10..uses third colour Class 3, 7, 11... uses the fourth colour coding. 3. I recommend standalone setup (using CCS and TIDL .out file) to validate your model first, once you confirm that it is working on standalone then you can run it on VSDK use case. Thanks, Praveen

Tks for sharing. 1. The key point that I care is which file contains the line “tempoutPutList->objDesc[tempoutPutList->numObjects].objType = (label - 1)%3”？ 2. I think running on the ccs with the simulator may be useful and convenient to validate, yet I said many times, I can not get the source code of TIDL from the representative in shanghai. If I have not got that code, could I just use the limited tools for debugging on CCS? I had better get the source code for building the tools and debugging on CCS ? Right?

1. File location is shared in this thread e2e.ti.com/.../723749 2. For running on the ccs with the simulator and validation, source code may not required. It may be required if you want to add new layers and debugging. Thanks, Praveen

Ticket Name: Realtime clock (RTC) subsystem time and calendar register not writeable?

We are trying the TDA2xx RTC subsystem for time and calendar (TC) use. There appear to be problems writing to the TC registers. At the same time I can write to the a SCRATCH register and later read the correct value from it. I cannot do this for the TC registers, even the SECONDS register does not store the values. In addition the seconds is not counting since reading from that register is always '0'. Are there differences between setting up the TC registers and SCRATCH registers? We are configuring using the internal clock source. Thanks

Hi Dan, Do you use func clock from the PRCM or from the external rtc_osc_xi_clkin32 pin? What values you have in the below two registers? CM_RTC_CLKSTCTRL CM_RTC_RTCSS_CLKCTRL Make sure you follow the below TDA2x TRM sections: 23.4.1 Clock Source 23.4.3.3 OCP MMR Spurious Write Protection 23.4.3.5 Modifying the TC Registers 23.5.1.2 RTC Module Global Initialization Regards, Pavel

Hi Pavel, Yes, first we are using the PRCM and wanted to pull the rtc_osc_xi_clkin32 pin low as suggested, however cannot find the actual pin pad location. It is not in the TRM. I am checking the other items you suggest, I have looked at those things. First is the RTC_STATUS_REG returns 0x0, which I was thinking it should be 0x2, which indicates the RTC is running. Am checking further. Thanks, Dan

Dan, Dan Zulaica said: Yes, first we are using the PRCM and wanted to pull the rtc_osc_xi_clkin32 pin low as suggested, however cannot find the actual pin pad location. It is not in the TRM. Pad locations are documented in DM (data manual), not TRM. For TDA2Hx-17 (SPRS952A), rtc_osc_xi_clkin32 is at AA13. Regards, Pavel

Hi Dan, I would like to highlight some spots that Pavel already pointed to. 1. Make sure RTC is enabled in PRCM - CM_RTC_CLKSTCTRL[1:0] CLKTRCTRL = 0x3 - CM_RTC_RTCSS_CLKCTRL[1:0] MODULEMODE = 0x2 2. Make sure RTC Register protection is turned off - RTC_KICK0_REG = 0x83E70B13 - RTC_KICK1_REG = 0x95A4F1E0 3. Select internal clock - RTC_OSC_REG[3] 32KCLK_SEL = 0 4. Enable clock -RTC_OSC_REG[6] 32KCLK_EN = 1 5. Start RTC runnig - RTC_CTRL_REG[0] STOP_RTC =1 6. Check RTC is running - RTC_STATUS_REG[1] RUN == 1 OR - See if seconds are updating Please be aware that internal 32-k clock is made of SYS_CLK1 div 610 and will be close to 32,768kHz only if you use SYS_CLK1 @20MHz. Best regards, Stan

Ticket Name: RTOS/TDA2: ERROR in convert caffe model to bin format

Part Number: TDA2 Tool/software: TI-RTOS Hi I use import tool to convert caffe model to bin format. I use the sample model from "github.com/.../sparse ", The config file as follow randParams = 0 modelType = 0 quantizationStyle = 1 quantRoundAdd = 25 numParamBits = 8 inputNetFile = "A.prototxt" inputParamsFile = "A.caffemodel" outputNetFile = "NET_OD.BIN" outputParamsFile = "PRM_OD.BIN" conv2dKernelType = 1 rawSampleInData = 1 sampleInData = "000100_1024x512_bgr.y" tidlStatsTool = "tidl_model_import.out.exe", However, I got the error as shown in the following figure. Could you point me how to fix this error? Thanks. BR Allen

Hi Allen, Please refer to first post in below thread and it also has import config file to use.. e2e.ti.com/.../689617 Thanks, Praveen

Hi, Praveen We fixed the error and NET and PRM files was been generateed . but why the logs still show "Couldn't open inputNetFile file" ? BR Allen

Hi Allen, Please attach import config file and log file to check the problem. Thanks, Praveen

Hi, Praveen we find something wrong and already solve and we have some post which doesn't receive respond form E2E the link as below can you help us? thanks a lot Allen

Ticket Name: Is The ancillary data have code words or head in memory?

are there have code words or head in ancillary data after send to memory? similar "0x00,0xff,0xff"

Not really, the captured ancillary data will be exactly what is sent from the sensor.. Rgds, Brijesh

Ticket Name: Linux: TDA2 new-usecase function

Tool/software: Linux Hi I use "PROCESSOR_SDK_VISION_03_07_00_00"and, I wanted to build a new usecase. I could read and show image by opencv and did the same things by draw2d.c. I followed VisionSDK_UserGuide_BuildSystem.pdf to build usecase. But I did't know what function or program could do that things. Q1：Is any document for building new-usecase, or about read and show ? Q2：Could someone show a brief process for this case ?

Hi, Can you refer to PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_DevelopmentGuide.pdf Regards, Rishabh

Ticket Name: TDA2SX: TDA2S DDR3 interface Performance

Part Number: TDA2SX Hi, As we known, TDA2S includes 2 DDR0 and DDR1 controllers, each DDR3 interface can connect with 2pcs 16bit DDR3 RAM, so TDA2S can connect 4pcs 16bit DDR3 RAM; Based on above understanding, although TDA2S supports 2 DDR3 controller, DDR3 controller work under 32bit data bus, if we connect 4pcs 16bit 512M bytes DDR3 with 2 DDR3 controller, is it equivalent to 2pcs 16bit 1G Bytes DDR3 with 1 DDR3 controller ? Thanks

Hi, If you connect 2x 16-bit 1GB (or 8Gb) DDR memories to 1x DDR controller, you would have the same amount of memory available as connecting 4x 16-bit 512MB (or 4Gb) DDR memories to 2x DDR controllers. The system performance would vary when using 1x controller vs. 2x controllers, as using two controllers effectively provides a 64-bit data bus to the system. As an example, the two controllers can be interleaved such that system memory alternates between the two controllers every 128 bytes, utilizing both controllers in parallel. Best regards, Kevin

Ticket Name: TDA2: [Vision_SDK 03.03.00.00] TIDL OD usecese input video

Part Number: TDA2 Hi, To run TIDL OD usecase, followinfg 4 files are required. TIDL OD Network file (NET_OD.bin) TIDL OD Parameter file (PRM_OD.bin) TIDL OD Usece input data file (inData_OD) TIDL OD Usecase input header file (inHeader_OD) SDK already contains NET_OD.bin & PRM_OD.bin in ./vision_sdk/apps/tools/TIDL_files. Those network is for 768x320 input image size. How do we get 768x320 video file to translate to inData_OD / inHeader_OD ? I am referring follwing e2e. However, FullHD or 4K files are only seen in http://jell.yfish.us/ . https://e2e.ti.com/support/arm/automotive_processors/f/1021/t/689617 e2e.ti.com/.../687481 Best regards, Saito

Hi Saito The TI trained (default) files will be part of cdds . Vision SDK demo clips are available at cdds.ext.ti.com/.../emxNavigator.jsp Regards Chetan.M

HI Cheta.M, Thanks. TI OD usecase is running well. Best regards, Saito

Ticket Name: TDA2SG: Can TDA2S Support to Output Same resolution two different video sources on the same vout port?

Part Number: TDA2SG Hello Sir/Madam, We have one project (surround view application) using TDA2x as video processor. GPU stitched surround view images (25FPS, 1440*900) output via DS90UB933 (TI Serializer) in YUV422 8bit format. Now we have new requirement, we want to output (25+1) frames, that means for every 25-Frame stitched images, there is 1 additional frame image (four raw surround view images in MOSAIC), this may be from different sources, GPU, A15, or DSP, but in same resolution 1440*900. We would like to know if this is achievable in TDA2SG and it would be appreciated that you can provide more implementation details. thanks. Jeffrey Yu

Hi Jeffrey, If i understand correctly, resolution and format remains same, so no change needed in the DSS. I believe main changes are in the application. You need to merge two channels, one from GPU and other may be from DSP.. You could probably use merge link, but this would require some changes to exactly control fps. Rgds, Brijesh

thank you, Brijesh. We will try. Jeffrey Yu.

Ticket Name: Linux/TDA2: Linux OpenCV Canny no video out

Part Number: TDA2 Tool/software: Linux Hi, SDK 3.04. Build tda2xx_evm_linux_opencx Compilation OK. Run Single camera usecase OV10635 1CH VIP capture and display to HDMI output. OK. No problem. But when run OpenCV Canny usecase got error and no video out. Any idea? [HOST] [HOST ] OpenCV Usecases [HOST] [HOST ] ---------------------------- [HOST] [HOST ] 1: 1CH VIP capture + OpenCV Canny (A15) + SGX Copy + DISPLAY [HOST] [HOST ] 2: 1CH VIP capture + OpenCV OpenCL Dilation (A15 + DSP) + SGX Copy + DISPLAY [HOST] [HOST ] [HOST] [HOST ] x: Exit [HOST] [HOST ] [HOST] [HOST ] Enter Choice: [HOST] [HOST ] 1 [HOST] [HOST ] 73.112304 s: [HOST] [IPU2 ] 73.112487 s: CHAINS: Sensor create in progress [HOST] [IPU2 ] 73.113036 s: VIDEO_SENSOR: INST0 : I2C1 : I2C Addr = 0x30 [HOST] [IPU2 ] 73.210364 s: VIDEO_SENSOR: VIP 0: DRV ID 1203 (I2C ADDR 0x30): a635:0000:7fa2 [HOST] [IPU2 ] 73.210699 s: CHAINS: Sensor create ... DONE !!! [HOST] [IPU2 ] 73.217104 s: CAPTURE: Create in progress !!! [HOST] [IPU2 ] 73.217470 s: CAPTURE: VIP1 Slice0 PortA capture mode is [ 8-bit] !!! ASSERT (chains_vipSingleCamOpenCVCannySgxDisplay_priv.c|chains_vipSingleCamOpenCVCannySgxDisplay_Create|166) [HOST] [HOST ] 73.339931 s: IPC_IN_0 : Create in progress !!! [HOST] [HOST ] 73.340328 s: IPC_IN_0 : Create Done !!! [HOST] [HOST ] 73.340389 s: ALG: ERROR: No alg create function specified (algId = 5) !!! [HOST] [IPU2 ] 73.338894 s: CAPTURE: Create Done !!! [HOST] [IPU2 ] 73.339291 s: IPC_OUT_0 : Create in progress !!! [HOST] [IPU2 ] 73.339687 s: IPC_OUT_0 : Create Done !!!

Hi Chee Peng, Due to CMEM dependency, this issue is observed & same has been reported & documented in release note of VSDK 3.4 release ADASVISION-1894 : [TDA2xx Linux] OpenCL UC, Cmem initialization fails However if you don't have any dependency on Linux, then you can try BIOS config for openCV (working fine with 3.4 release) Otherwise you can try on old VSDK release (3.1 release) where it is working fine Regards Surya

Hi Surya, May I have VSDK release 3.1 download link? Thank you very much regards chee peng

I found vsdk 3.01. software-dl.ti.com/.../index_FDS.html I try first. thank you

Hi Surya I tried VSDK 3.01 Strange, i can compile successful for tda2xx_evm_linux_all But compile fail for tda2xx_evm_linux_opencx Do you have any idea? Best regards Chee Peng cheepeng@ubuntu:~/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/build$ make -s -j # Invoking configuro... # Configuro done! # Making tda2xx-evm:ipu2:release:vision_sdk_lib... # Linking into /home/cheepeng/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_opencx/vision_sdk/bin/tda2xx-evm/vision_sdk_ipu2_release.xem4... # # # /home/cheepeng/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_opencx/vision_sdk/bin/tda2xx-evm/vision_sdk_ipu2_release.xem4 created. # ‘/home/cheepeng/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/binaries/apps/tda2xx_evm_linux_opencx/obj/vision_sdk/tda2xx-evm/ipu2/release/vision_sdk_configuro/osa_mem_map.h’ -> ‘/home/cheepeng/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/links_fw/src/hlos/osa/include/osa_mem_map.h’ # system: tda2xx-evm: Compiling system_ipc.c # osa: tda2xx-evm: Compiling osa_mem.c # osa: tda2xx-evm: Compiling osa_remote_log_client.c # osa: tda2xx-evm: Compiling osa_remote_log_server.c # system: tda2xx-evm: Creating archive system.a # osa: tda2xx-evm: Creating archive osa.a In file included from /home/cheepeng/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/apps/src/include/chains_common_osal.h:86:0, from /home/cheepeng/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/apps/src/include/chains_common_surround_view.h:83, from /home/cheepeng/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/apps/src/hlos/common/chains_common.h:147, from /home/cheepeng/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/apps/src/hlos/adas/include/chains.h:101, from chains_vipSingleCamOpenCLFrameCopySgxDisplay.c:99: /home/cheepeng/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/links_fw/src/hlos/system/system_priv_ipc.h:100:30: fatal error: ti/ipc/MultiProc.h: No such file or directory compilation terminated.

Hi Chee Peng, Did you install all components with 3.1 release or not ? Could you please check "MultiProc.h" file is present in below folder or not ? ti_components\os_tools\ipc_3_45_00_00\packages\ti\ipc Regards Surya

Hi Chee Peng, The issue "ASSERT (chains_vipSingleCamOpenCVCannySgxDisplay_priv.c|chains_vipSingleCamOpenCVCannySgxDisplay_Create|166)" has been resolved & will be available with next vision sdk release Regards Surya

Ticket Name: TDA2SG: recommended pcb pad size of TDA2 bga

Part Number: TDA2SG Hello team, My customer would like to know if the PCB pad size(land pattern size of BGA) is acceptable. The ball size of TDA2x ABC (23mmx23mm) looks typ. 0.50Φ according to data manual as following. The customer is designing the PCB pad size with 0.40Φ. 0.40Φ pad size is acceptable? . What would be the recommended pad size for BGA? regards, Lloyd

Refer to the following appnote for background: www.ti.com/.../spraa99b.pdf The solder ball dia that the POD shows is not the key parameter that should be used in determining the PCB’s ball land diameter. The package’s Solder Mask Opening (SMO) for each ball is the parameter that drives PCB ball land dia. Optimally SMO = Ball Land for best mechanical robustness, see Table 1 of attached. It recommends 0.4mm ball land dia for 0.8mm pitch BGAs assuming the standard package side SMO = 0.4mm. For TDA2x and DRA74x/75x we recommend 0.4mm ball land dia. Regards, Kyle

Ticket Name: TDA2: TDA2x

Part Number: TDA2 Dear TI, We are working on TIDL now, refer to: VisionSDK_UserGuide_TI_DeepLearning.pdf, I can't access the link: https://cdds.ext.ti.com/ematrix/common/emxNavigator.jsp?objectId=28670.42872.30602.25095 stated inside this doc. due to lack of "CDDS user account". Can you advise us how to get the CDDS account? Thanks and best regards He Wei Team leader for System Architectures and Deep Learning

Dear TI, In addition, to try on the TIDL use case in the VSDK, it require the configure file, network file, parameter file and usecase input file, Where can I get these files? He Wei Team leader for System Architectures and Deep Learning

Hi He Wei, you need to contact your local TI FAE to get access to CDDS (it requires NDA to be signed). The example files for TIDL Usecase can be found in "PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\apps\tools\TIDL_files". Regards, Yordan

Ticket Name: Compiler/TDA2: Gmake optimization and language options

Part Number: TDA2 Tool/software: TI C/C++ Compiler Hi, I use vision sdk 3.04 for ubuntu. How could I enable optimization and c99/c11 options for gmake? Or where can I read about it? Thanks for answers.

Hi, You can add c flags in vision_sdk/build/rtos/makerules/ Please follow the below doc \PROCESSOR_SDK_VISION_03_03_00_00\vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_BuildSystem.pdf Regards, Anuj

Hi, For example, For A15 add "CFLAGS_INTERNAL+= -std=c99 " enable c99 option, is it right?

Hi, You can not do like that coz if you modify CFLAGS_INTERNAL it will be same for c and cpp file and for cpp files -std=c99 is not a valid flag. So add it where it compiling c files only like below $(OBJ_PATHS): $(OBJDIR)/%.$(OBJEXT): %.c $(ECHO) \# Compiling $(PLATFORM):$(CORE):$(PROFILE_$(CORE)):$(APP_NAME)$(MODULE_NAME): $< $(CC) -MD -MF $(DEPDIR)/$(basename $(notdir $<)).P -std=c99 $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -o $(OBJDIR)/$(basename $(notdir $<)).$(OBJEXT) $< Regards, Anuj

Thank you

Ticket Name: RTOS/TDA2: RTOS/TDA2

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, I has Vayu EVM board (Rev.H) + SDK 03_03_00_00 and will drive GPIO_5[8] to output high or low. I refer PDK document "API_Documentation.html" to know how to program it. -------------------------------------------------------------------------------------- Programming sequence of gpio module is: Enable the functional clocks for the required GPIO instance. Perform a pin multiplexing for the required GPIO pin. Enable the GPIO module using the API GPIOModuleEnable. Perform a module reset of the GPIO module using the API GPIOModuleReset. When GPIO is input pin, following configuration is used Enable/disable debouncing feature for the specified input GPIO pin if required, using the API GPIODebounceFuncControl. Program the debouncing time, if required using the API GPIODebounceTimeConfig. Interrupt trigger conditions need to be configured using the API GPIOIntTypeSet. Enable GPIO to generate interrupts on detection of the specified transitions on the decided GPIO pin using the API GPIOPinIntEnable. When GPIO is output pin, following configuration is used A logic HIGH or a logic LOW could be driven on the specified GPIO pin by invoking the API GPIOPinWrite. -------------------------------------------------------------------------------------- my sample code as below: // a. Enable the functional clocks for the required GPIO instance. /* Set the access to the GPMC registers - Enable GPMC Clock */ HW_WR_REG32(SOC_L4PER_CM_CORE_BASE + CM_L4PER_GPIO5_CLKCTRL, 0x101); while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE + CM_L4PER_GPIO5_CLKCTRL) & (0x00030000U)) != 0x0) { ; } // b. Perform a pin multiplexing for the required GPIO pin. HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_MCASP1_AXR6, (0x60000U | CTRL_CORE_PAD_MCASP1_AXR6_MCASP1_AXR6_MUXMODE_GPIO5_8_14)); //C12 GPIODirModeSet(SOC_GPIO5_BASE, 8, GPIO_DIR_OUTPUT); //C12 // c. Enable the GPIO module using the API GPIOModuleEnable. GPIOModuleEnable(SOC_GPIO5_BASE); // d. Perform a module reset of the GPIO module using the API GPIOModuleReset. GPIOModuleReset(SOC_GPIO5_BASE); // Set C12 to high. GPIOPinWrite(SOC_GPIO5_BASE, 8, GPIO_PIN_HIGH); //C12 The sample code still can't drive GPIO_5[8], could you please give me some suggestion. Thanks.

Hi, You should refer to gpio app in <pdk>\packages\ti\csl\example\gpio folder. Regards, Rishabh

Hi Rishabh, I refer gpio sample code and get Luke.Lin (TI technical support of Taiwan ) support. Now GPIO control is workable. Thanks.

Ticket Name: Linux/TDA2: how to creat vcop_median3x3_kernel.c and vcop_median3x3_kernel.h from vcop_median3x3_kernel.k

Part Number: TDA2 Tool/software: Linux in SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\kernels\imgsiglib\vcop_median3x3 have vcop_median3x3_kernel.k how can i creat vcop_median3x3_kernel.h? thanks shuai

Shuai, We have already discussed this in the following thread : e2e.ti.com/.../2676382 Is it still not clear? Regards, Anshu

Hi Anshu yes ,i cannot generate vcop_median3x3_kernel.h from vcop_median3x3_kernel.k i compile SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\kernels\imgsiglib\vcop_median3x3 by gmake also cannot generate vcop_median3x3_kernel.h. BESTWISHES shuai

Are you using makefiles which comes as part of EVESW? Can you explain how are you building? Regards, Anshu

Hi Anshu cmd to D:\ti_SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\kernels\imgsiglib\vcop_median3x3\test then run gmake target, in D:\ti_SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\kernels\imgsiglib\vcop_median3x3\test\elf_out creat vcop_median3x3_kernelC.out. follow is the log ! D:\ti_SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\kernels\imgsiglib\vcop_median3x3\test>gmake target D:\ti_ccsv7\ccsv7\utils\cygwin\mkdir -p ".\elf_out" || cd ".\elf_out" "D:\ti_SDK_VISION_03_02_00_00\ti_components\cg_tools\windows\arp32_1.0.7"\bin\cl-arp32 -O3 --opt_for_speed=5 -kh --silicon_version=v210 -lu --display_error_number --diag_suppress=26066 --diag_suppress=10063 -I"D:\ti_SDK_VISION_03_02_00_00\ti_components\cg_tools\windows\arp32_1.0.7"\include -I"D:\ti_SDK_VISION_03_02_00_00\ti_components\cg_tools\windows\arp32_1.0.7"\include\vcop -I . -I"..\..\..\..\common" -I"..\..\..\common" -I"..\..\..\..\starterware\inc" -I"..\..\..\..\star terware\inc\baseaddress\vayu\eve" -I"..\..\..\inc" -I"..\inc" vcop_median3x3_config.c vcop_median3x3_tb.c "..\..\..\..\common\configparser.c" "..\..\..\..\common\eve_profile.c" "..\..\..\..\common\curve_fitting.c" "..\..\..\..\common\ti_stats_collector.c" ..\..\..\common\boot_arp32.obj -z -l ..\src_kernelC\vcop_median3x3_kernel.obj -l..\..\..\lib\release\libevenatckernels.eve.lib -l"..\..\..\common\linker_boot_cama.cmd" -l"D:\ti_SDK_VISION_03_02_00_00\ti_components\cg_tools\ windows\arp32_1.0.7"/lib/rtsarp32_v200.lib -l"..\..\..\..\starterware\libs\vayu\eve\release\libevestarterware_eve.lib" -m ".\elf_out"\vcop_median3x3_kernelC.map -o ".\elf_out"/vcop_median3x3_kernelC.out [vcop_median3x3_config.c] [vcop_median3x3_tb.c] [configparser.c] [eve_profile.c] [curve_fitting.c] [ti_stats_collector.c] <Linking> BESTWISHES shuai

Shuai, The header vcop_median3x3_kernelC.h will be generated inside <EVESW>/kernels/inc directory. Please check if you can find it there. Regards, Anshu

Hi Anshu befor i compile in D:\ti_SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\kernels\inc have vcop_median3x3_kernelc.h and vcop_median3x3_kernelc.c , i move them and rebuild generate vcop_median3x3_kernel.h. so this thread is over! thanks ! shuai

Can we close this thread? Regards, Anshu

Hi: Anshu Of course! Regards, shuai

Ticket Name: TDA2EVM5777: How to Delay SPI Slave to Master Response in Vision SDK

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi , Please guide me how to delay slave to master response in Vision SDK by one clock ? I am missing MSB in MISO and wave form shows that when clock starts first bit is already passed so it starts reading from second MSB. Thanks,

Hi, Have you configured the TDA2 in master or slave mode? In case of slave mode, the TDA2 device does not control the clock. It only responds to the clock sent by the external master. Regards, Prasad

Rajesh, Are both master and slave operating in the same SPI mode 0/1/2/3?

Hi, Sorry for the delay in reply. TDA2x is configured in slave mode and both are using SPI mode 3. I have attached a screen shot for the slave to master communication for data 0111 0000 and the problem is our MSB gets lost because delay in clock signal and we are receiving 1110 0000 on MCU side. We are using SPI mode 3 for this communication and using GIO_issue and GIO_reclaim API's given by Vision SDK. Could you please guide us here how we can sync clock signal so that we will not loose first bit (MSB) while doing communication from slave to MCU. MCU to slave no issue. Thanks,

Hi Rajesh, Can you post or send by email the part of schematic diagram related to SPI? Stan

Hi, Please check your email for the SPI related schematic diagram. Thanks

Hi Rajesh, did you resolved your issue? If you have further question please write here or send mail to Stan. Regards, Yordan

Ticket Name: TDA2HG: How can TDA2HG configure O917A133 on DVFS mode

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 Hi, My board use TDA2HG as processor, O917A133 as PMIC. And external MCU set POWERON and POWERHold to let O917A133 output power to TDA2HG. Please refer diagram below: TDA2HG output signal to O917A133 's nRESWARM, and O917A133 output Rest_out signal to TDA2HG's RESETn. The problem: is everytime when TDA2HG configure O917A133 in "warm reset sequences", TDA2HG will reset by O917A133. But actually TDA2HG only want O917A133 change it's output voltage not reset TDA2HG. Or it may called DVFS mode. But from O917A133 datasheet, it only have OFF2ACT, ACT2OFF, ACT2SLP and Warm Reset Sequences. So is DVFS mode available on this design? Thanks a lot!

Tim, DVFS is a software concept where application code would change the Voltage and Frequency to a new OPP to increase performance (and increase power) or decrease power (and decrease performance) at run-time. However, DVFS is not supported in the SDK for the TDA2 devices. Regards, Kyle

Thanks Kyle! I finger out this problem already. Actaully SOC rest_out singal is because I configure SMPS4 on a wronge voltage then cause SOC rest. And I think if I leave SMPS4 along which is only for DDR supply, is OK for my system to work property. Anyway, thanks for your reply!

Ticket Name: TDA2HV: Customize TI-RTOS HWI_Disable()/HWI_Restore() APIs to toggle GPIO

Part Number: TDA2HV Other Parts Discussed in Thread: TDA2, SYSBIOS Hello TI RTOS experts, TI RTOS runs on TDA2 on a custom board. Code base is custom and loosely based on an older Vision SDK release. A missed interrupt issue on A15 core is being debugged. One theory is that interrupts are globally disabled for too long via HWI_Disable()/HWI_Restore() APIs. Since JTAG access is not available on the board, the approach is to measure time between interrupts disabled/reenabled by toggling GPIO. The current implementation modifies low level code and adds low level GPIO register access code in multiple locations (where hwi disable is defined): in hwi.c ( "bios_6_46_04_53\packages\ti\sysbios\hal"), in file Core__epilog.h ( "bios_6_46_04_53\packages\ti\sysbios\hal"), and in ( "C:\ti\ford\bios_6_46_04_53\packages\ti\sysbios\family\arm\gic") . Is it necessary to "hit" all three locations with modifications? Are there more locations? Is there a cleaner way to implement this functionality? Basically customize HWI_Disable()/Restore() APIs to toggle a specific GPIO. Thanks in advance, Jelena

Jelena, User code will invoke the Hwi_disableFxn()/enableFxn/restoreFxn implementations in src/ti/sysbios/family/arm/gic/Hwi.c. When the custom SYSBIOS library is built, -Dti_sysbios_Build_useHwiMacros is added to the compile line for each source file pulled into the custom library. Defining that symbol invokes inlined versions of Hwi_enable/disable/restore to be used rather than the versions in Hwi.c. The optimized versions of those APIs are implemented in ti/sysbios/family/arm/gic/Hwi__epilogue.h and in ti/sysbios/hal/Hwi__epilogue.h. if you simply change the #ifndef ti_sysbios_Build_useHwiMacros statement in those header files to #ifdef ti_sysbios_Build_useHwiMacros Then the implementations of Hwi_enableFxn/disableFxn/restoreFxn found in ti/sysbios/family/arm/gic/Hwi.c should always be invoked. Alan

Part Number: TDA2 Tool/software: TI-RTOS Hi Ti, I'd like to run tidl use case "Semantic Segmentation" in PROCESSOR_SDK_VISION_03_05_00_00 on tda2xevm. I refer to VisionSDK_UserGuide_TI_DeepLearning.pdf: page6 It needs to prepare these 6 files. Make sure the following files are present in the MMC/SD card: o TIDLCFG.TXT (TIDL use case configuration file) o Input file o TIDL Semseg Network file (NET_Semseg.bin) o TIDL Semseg Parameter file(PRM_Semseg.bin) o TIDL Semseg Usecase input data file (inData_semSeg) o TIDL Semseg Usecase input header file (inHeader_semSeg) I put these 5 files to SD card except "input file". inData and inHeader are from https://e2e.ti.com/support/processors/f/791/p/687481/2534375?keyMatch=inHeader_OD&tisearch=Search-EN-Everything tidl_net_jsegnet21v2.bin and tidl_param_jsegnet21v2.bin are from PROCESSOR_SDK_VISION_03_05_00_00/vision_sdk/apps/tools/TIDL_files What is "input file"? Where can I get it? Can you also check my TIDLCFG.txt file? It was modified from TIDL_SSD_CFG.TXT. TIDL Configuration parameters ----------------------------- ################################################################################ IMP: Make sure the size of the file names (excluding extension) is not more than 8 characters. ################################################################################ inputWidth=768 inputHeight=320 inputFile=inData.h264 inputHDRFile=inHeader netFileName=tidl_net_jsegnet21v2.bin paramFileName=tidl_param_jsegnet21v2.bin Thank you.

Hi Eric, input file refer to "IN.RGB" file present inside vision_sdk/apps/tools/TIDL_files However you don't need any input file or cfg.txt file for semseg UC As in UC, the file names are hard coded, Please refer the UC file shared in below path -> vision_sdk\apps\src\rtos\usecases\semSeg\chains_semSeg.c so please rename the files accordingly For Semantic Segmentation UC, these below listed 4 files need to be present in the SD card o TIDL Semseg Network file (NET_Semseg.bin) o TIDL Semseg Parameter file(PRM_Semseg.bin) o TIDL Semseg Usecase input data file (inData_semSeg) o TIDL Semseg Usecase input header file (inHeader_semSeg) Regards Surya

Hi Surya, What size of video do I prepare for "TIDL Semseg Usecase input data file (inData_semSeg)"?

Hi Eric, Ensure input video width & height should be 1024x512 as in UC, it is defined as #define SEMSEG_INPUT_WIDTH (1024) #define SEMSEG_INPUT_HEIGHT (512) PSB for details of the test video We used for testing Regards Surya

Ticket Name: CCS/TDA2SX: NDK helloWorld example

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Tool/software: Code Composer Studio Hi, TI experts! I want to run NDK helloWorld example on TDA2 custom board. I found the example on path: PROCESSOR_SDK_RADAR_03_08_00_00\ti_components\networking\nsp_gmacsw_4_16_01_01\packages\ti\ndk\tda3xx\examples_ipu1\helloWorld. I sucessfully builded this example and tried to run it on TDA2 custom board on IPU1_0 core. Example was run but in ccs console i can't found any messages with ip adress, mac or any error. What could be my mistake? How can i change correctly this example for my custom board?

Also I tried another example from: PROCESSOR_SDK_RADAR_03_08_00_00\ti_components\networking\nsp_gmacsw_4_16_01_01\packages\ti\ndk\vayu\examples_ipu1\helloWorld I run it on EVM5777 board and still nothing on the ccs console.

Ticket Name: RTOS/TDA2: Configuring MLO for TDA2x

Part Number: TDA2 Tool/software: TI-RTOS Hi, By using TDA2x to do some development work, there is a need for me to make changes for configurations in MLO. The requirements are:- MLO must be built with OPP_HIGH and dual ddr interleaved mode How do I make changes on MLO for this purpose? Thanks

Hi, Can you refer to SBL user guide: processors.wiki.ti.com/.../TDA_SBL_UserGuide.pdf Regards, Rishabh

Aware about this SBL user guide. it is not mentioned how to configure dual ddr interleaved mode

Hi, You should refer to chapter 8 EMIFMODE. Option to use is SBLLIB_DUAL_EMIF_2X512MB. Regards, Rishabh

Hi, Is this issue resolved? Regards, Rishabh

Ticket Name: Compiler/TDA2SG: TDA4 UBOOT is compatibility the TDA2S UBOOT

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi, can I use TDA4 UBOOT replace the TDA2S UBOOT

Hi Zhangsc, The UBOOT for TDA2S will not have support for TDA4 SoCs. Regards, Karan

Hi Zhangsc, TDA2 had just MLO(SPL) & u-boot.img both running on A15. TDA4 has tiboot3.bin which contains R5 SPL followed by tispl.bin which is the A72 SPL and finally u-boot.img which is A72 u-boot. So as Karan responded they are entirely different. Best Regards, Keerthy

what is the version of the uboot thanks.

Ticket Name: TDA2EVM5777: TDA2 QSPI flash size support

Part Number: TDA2EVM5777 Hello I found the QSPI flash on the EVM is S25FL256SAGMFV001 what is the max qspi size TDA support? could I replace to "1 Gbit (128 Mbyte) S79FL01GS Dual-Quad SPI NOR Flash" ? thank you

Hi, You can access 128 MB QSPI flash in CFG mode. From L3's view only 64 MB is available to QSPI (0x5c00_0000 to 0x5fff_ffff) so the maximum QSPI memory that you can access in memory mapped mode at given point of time is 64 MB only. In case you want to connect 128 MB flash part and access the second 64 MB region then you need to configure the flash so that all accesses go to the second section of the flash. These settings are provided in the flash's datasheet. Regards, Rishabh

Ticket Name: TDA2: Is Vector to scalar switching possible?

Part Number: TDA2 Hi, Is it possible to switch from vector to scalar in VCOP kernel C? I want to make decisions based on the individual element value, will it be possible? Regards, Shruti

Hi Shruti, Can you provide some example of what you want to do? VCOP only works with vector instructions but if we know what you are trying to do we may provide some alternatives. Regards, Anshu

Hi Anshu, I have a use case wherein, depending on the value of the element I have to set a flag. This flag can range from 0 to 7. Depending on the flag's value, I have to perform some operations. In normal C this is easy, the flag can be set for a single element, and normal if-else conditions take care of the rest. But, when using kernel C, 8 elements are processed at a time, and the flag is also a vector. So, all the elements of the flag will be in the range of 0 to 7. And for each element the operation should be different. Is there a way to handle this? Regards, Shruti Joshi

Shruti, Can you look into select instruction of VCOP and see it helps? Regards, Anshu

Hi Shruti, We haven't heard back on this from you. Were you able to make progress? If yes please close this thread. If not then let us know. Regards, Anshu

Hi Anshu, We tried to use select instruction, but that does not solve the purpose. So we decided to change the code logic itself. So that we do not have to take such complex decisions. Anyways thanks for your help. Regards, Shruti

Ticket Name: Linux/TDA2SX: How to control gpio in linux?

Part Number: TDA2SX Tool/software: Linux Hi, We use gpio7_27 to enable the CAN interface in hardware, so before using the CAN interface, we need to set the GPIO7_27 pin to low level. How do I use gpio in Linux? I am using the hardware TDA2SX, using the VSDK version of 03-06-00-00. Regards Kepei

Hi, You can use the GPIO hog device tree entry so that the GPIO line is driven low. Refer to Linux kernel documentation on GPIO-hog https://www.kernel.org/doc/Documentation/devicetree/bindings/gpio/gpio.txt NIKHIL d

Hi NIKHIL, Thank you for you reply! So i can used this code to set the gpio to 0? gpio_enable <&gpio7 27 GPIO_ACTIVE_HIGH> Regards Kepei

Hi NIKHIL I have tried this code in dcan node. gpio_enable <&gpio7 27 GPIO_ACTIVE_HIGH> but it is not work and i tried this code in gpio7 node line_b { gpio-hog; gpios = <27 0>; output-low line-name = "dcan-standby"; }; It is not work too. The out put of gpio7_27 is high.

You should be getting compiler error since you are missing a ; after output-low Maybe the DTB is not updated and that's why no effect. Otherwise, the code change is almost correct Nikhil D

Ticket Name: TDA2: Pytorch network implementation on TDA2x/4x

Part Number: TDA2 I am going to implement deep learning network ESPNet on TDA2x and TDA4x(in future). ESPNet source was implemented in Pytorch framework. I found there are Caffe/Tensorflow contents in TIDL document. I have two questions. 1. how to use pytorch outputs in TIDL. Should I export pytorch outputs in ONNX format and import it to Tensoflow or Caffe, after then follow the TIDL guid? Is there any related documents? 2. If some core operations are not supported in TIDL because of TIDL limitations, Should I implement it by myself? ex)Convolution Dialition 1,2,4 only tested / Deconvolution only supported stride value is 2 / ... Then where should I start? Thanks.

1. ONNX mdoels are not supported in TDA2x/3x TIDL. 2. We can split caffe/tensorflow in to multiple sub TIDL models. Use TIDL for processing these mdoels and user can implements unsuported models and run them between the sub models. Please get in touch with TI representative for TDA4x related questions.

Thanks for your answer! Then will ONNX be supported in TDA4x? Currently, What approach should I follow for using pytorch framework in TDA2x? Thanks.

Please get in touch with your local TI support for TDA4x related questions. For TDA2x, you may try to convert the model to caffe format.

Ticket Name: TDA2: 2D SRV Calibration issue in TDA2X

Part Number: TDA2 I followed "VisionSDK_UserGuide_SurroundView_Calibration_TDA2xx.pdf" , and updated CHARTPOS.BIN for actual dimensions of the chart used for calibration by using "3d_calibration_tool". The result of Auto Calibration for 3D SRV was good after I replaced CHARTPOS.BIN in Micro SD card. However, the result of Auto Calibration for 2D SRV was worse than before the default CHARTPOS.BIN was replaced. 3D SRV ran on HLOS while 2D SRV ran on RTOS. What should I do next? Regards, Daniel

Hi Daniel, The usecase will work if you follow everything described on the document. Please contact the respective TI field agent assigned to your account. Regards Shashank

Hi Shashank All right, Thanks for your reply. Regards Daniel

Ticket Name: Linux/TDA2: OV490 video output issue in VSDK 3.04.

Part Number: TDA2 Tool/software: Linux Hi , I am using a custom Board and running VSDK 3.04 with Linux usecase. In VSDK 3.04 ,the ov490 video output via chains like this: IPU capture -> split ->IPC -> A15 -> SGX -> IPU display. and in IPC Link , the Video BufAddr export to dmaFd ,mapped to tex[]. THE ISSUE is that SPLIT LINK using address manipulation only , the stitched two video exported to the same dmaFd, so it cannot split the video frame. Any clues to help me split the stitched video buf ? Best regards, John

Hi, Split link splits vertically the incoming video data to multiple channel in its output queue by changing the buffer address. Can you tell me exactly what you want to do so that i can help you properly. Regards, Anuj

i think it splits the frame horizontally. Essentially, for same input buffer, it gives out two buffer pointer, one for the start address and other middle of the line.. It does not really do any buffer copy, just buffer pointer manipulation What exactly your requirement? Regards, Brijesh

thanks for reply. I tested the srv linux usecase with ov490 ISP. But the 4 textures displayed 2 camera videos with 2 duplicated ones. as below. I checked the code, the tex[0], tex[1] mapped the same dmaFd. So did the tex[2], tex[3]. I want 4 camera videos to displayed. regards, John

Hi, Can you explain your complete setup. As the above usecase has been designed by Ti for a specific customer which uses 4 cameras capturing at 1280*720 and 2 cameras going to OV490 which gives a total of 2 output of 2560*720 for 4 cameras input. So if you have similar kind of setup then only use the above usecase. Regards, Anuj

Hi, Anuj Thanks for reply. It is the same kind of setup . A total of 2 output of 2560*720 for 4 cameras input. I check the code about vmem and egl. And print out the address before dma-export. But I cannot find how to print out the address after dma-export in egl function. How can I check the exported YUV address ? For comparing the different? Regards, John

Hi, For debugging purpose can you try to run the similar usecase which is provided for bios for OV490 Regards, Anuj

Hi, Why not Linux usecase? Have ti tested for linux usecase? It runs ok in Vision SDK 2.xx Regards, John

Hi, Yes, you can go ahead with linux usecase also. For better debugging can you modifying your usecase and add merge after the 2 splits link and then display and dynamically display all channels alternatively. Above approach will be easier in debugging. Regards, Anuj

Hi, Thanks for your suggest. I will try it. Any suggest for debugging Linux usecase? Regards, John

Hi, You can modify your linux usecase only, no need to move to bios. Regards, Anuj

Hi Anuj, In my board, the YUV output from OV490 like this: cam1 addr 1 | cam2 addr 2 Y1 Y2 ... Y1280 | Y1281 .... Y2560 Y2 .... ... Y720 ........ U1, V1, ... ... Now my problem is that the DMABUF export the data which 4K page aligned as a dmafd. Any offset in this page are masked. So how can I pass two address within this page to GPU? Here is my other question thread: e2e.ti.com/.../737370 Regards, John

Close the thread as there is a new one. Regards, Yordan

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi sir, I would like to get a single frame frame camera. How can I do this in a usecase? Thank you, Gary

Gary, I did not get you, you want to capture single frame from camera? You could start the capture module, once first frame is captured, you could stop the capture device/camera. Rgds, Brijesh

Gary, You can run app_single_cam demo. Once the preview is running press 's' to save RAW and YUV images to the SD card. Regards, Mayank

Hi Mayank, I couldn't find app_single_cam in TDA2 usecase. Can you advise where to find it? Thank you, Gary

Hi Brijesh, My goal is to get a frame into a buffer and doing further processes. eg. I have added a camera capture link in tidlOD usecase. Now, I would like to create a new buffer and put a camera frame into it. Can I do this? If yes, how should I do? Thank you, Gary

Hi Gary, Which capture link you are using? There are two capture links, VIP Capture link and ISS capture link. I think VIP capture link does not support dumping a frame into a specific buffer. But ISS capture link supports this feature. You would require to port this feature from ISS capture link to VIP capture link.. Rgds, Brijesh

Hi Brijesh, I'm using the VIP way to capture image. Is it possible to do this: I'll set a flag. When the flag is false, the camera will drop all the frames. When the flag is true, a function will get frames until flag is set to false. If above case is possible, how can I do this via VIP capture link. Thank you, Gary

Hi Gary, Unfortunately no. there is no feature like flag based capture in the VIP link. You would have to add it. Another way is, you could register an application callback, start the capture and after you get this capture, dump the frame and stop the capture. Rgds, Brijesh

Ticket Name: Linux/TDA2EVM5777: The rstoutn function of TDAx

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: Linux The following is a section of the TDA2 manual. Why does the manual recommend using an AND gate instead of an OR gate? We measure the waveform as shown below: The rstoutn signal we designed is used to reset to other devices connected to the SOC without any gates.When the SOC is powered up, RSTOUTn (green) is reset after PORz (yellow) and there is a glitch during PORz reset. So I think if we choose an OR gate, we can keep other SOC devices with a longer reset time.

Hi, user3378603, IF I understand you correctly - the signals RSTOUTn and PORn are active-low signals. That's why they must be ANDed, not ORed. Regards, Mariya

As Mariya said, Reset signals are active-low. That's why we have an 'inverted logic', and we need an AND gate for an active reset output until both resets release. 1 AND 1 = 1 Regards, Stan

Ticket Name: TDA2P-ABZ: ISP difference to TDA3

Part Number: TDA2P-ABZ Other Parts Discussed in Thread: TDA2 Hi Experts, can you confirm if the TDA2 plus and the TDA3 have the same ISP? Or are there changes necessary if you want to reuse the software? BR Simon

Hi Simon, From the ISP design perspective, there is no difference between TDA2p and TDA3.

Ticket Name: Linux/TDA2: Facing issue while building Vision SDK 3.03

Part Number: TDA2 Tool/software: Linux While I trying to build vision SDK 3.03, we were getting the following errors, after following the steps of installation provided : system_gbm_allocator.c: In function 'gbm_wrap_native_buffers': system_gbm_allocator.c:175:9: error: implicit declaration of function 'gbm_surface_import' [-Werror=implicit-function-declaration] surf = gbm_surface_import(dev, ^ system_gbm_allocator.c:175:7: error: assignment makes pointer from integer without a cast [-Werror=int-conversion] surf = gbm_surface_import(dev, why? I have already tar the " install-extra.tar.gz” into $ INSTALL_DIR/ti_components/os_tools/linux/targetfs . using tar –xvzf install-extra.tar.gz Thanks and regards. ^

Hi Jacinda, Can you send me this file from your targetfs? /usr/include/gbm/gbm.h Regards Surya

Hi Surya I have solve this problem. Thanks and Regards Jacinda

Good to hear that issue is resolved Could you please post how you solved the issue ? It will help others Regards Surya

Ticket Name: RTOS/TDA2: Encode link latency variations

Part Number: TDA2 Tool/software: TI-RTOS Hello everyone! We have two issues regarding Encode link latencies. Issue 1: We have created two use cases with the excerpts given in the images attached below. Namely, in the case of the first image, we use one instance of Select link, that forms the output consisting of one queue comprising four channels. This output is fed into the Encode link instance, that performs H.264 encoding on all of the four input channels. We have set the following intra-frame interval (between two I-frames): pLinkDynPrm->intraFrameInterval    = 10; The Encode link feeds one instance of Null link. The latency measured by the "Print statistics" option (P key) outputs the value of ~36 ms for the Encode link. In the case of the second image, instead of using one instance of Null link for all of the 4 channels, we use 4 instances of Null link (one Null link per channel). Hence, the output from the Encode link (1 Q, 4 CHs) is firstly fed into a Select link that forms 4 Qs, each comprising 1 CH. The latency measured by the "Print statistics" option (P key) outputs the value of ~86 ms for the Encode link. Issue 2: In the case we set the intra-frame interval to the value 1 (every output frame is an I-frame): pLinkDynPrm->intraFrameInterval    = 1; the latency of the Encode link is ~18 ms when encoding one Q with 4 CHs. Hence, we can notice that the encoding latency is greater when generating P-frames. Is there any explanation of these two issues and is there any configuration that might be performed on the Encode link to decrease these latencies below 20 ms when generating P-frames? Best regards, Marko

Hi Issue <1> I expect encode latency to be the same in both cases. BTW, what are you doing in Null link, just a termination or some File write etc.? If the output buffers are not fed back to encode link the latency numbers might shows high Please use single null link with 4ch. Issue <2> Yes, this is expected, encoding with P and B frames will take more processing cycles compared with I frame only encode. with P and B frames we can achieve lower bit-rates (higher compression) and hence more processing cycles regards, Shiju

Hi, Shiju! Thanks for your reply. We use multiple Null links to transmit four video streams to four individual devices. So, in our case, the Null link(s) perform outputs on the Ethernet. If I understand well, there is some kind of bufferbloat between the Encode link and Null links since the Null links are not able to output buffers to the Ethernet opportunely? If this is the case, it is possible to occur in our environment. Regarding the second issue, I have to note that we are not allowed to generate B frames, so we generate only I and P frames. Is there any solution to reduce this latency when generating frames of these two types only? Best regards, Marko

Hi Marko <1> yes, if the null links are not able to fee-up the output buffers of encoder link, you might see higher latency numbers. <2> Not powerful options, but you can try below encode option change pLinkChPrm->encodingPreset = SYSTEM_XDM_MED_SPEED_HIGH_QUALITY; to SYSTEM_XDM_HIGH_SPEED or SYSTEM_XDM_HIGH_SPEED_MED_QUALITY But please note that this will not give any big boost. regards, Shiju

Hi, Shiju, Thank you for your response. We will perform the observation of the free buffer get function results from the Encode link to get aware of free buffers availability during the execution. Also, we will set the proposed "encodingPreset" parameter flags and compare the statistical data with our current set-up. Best regards, Marko

Hi, Shiju! We have set the "encodingPreset" parameter SYSTEM_XDM_HIGH_SPEED and we have succeeded to speed up the encoding process, thus decreasing the latency from 88ms to 16ms. Best regards, Marko

Ticket Name: RTOS/TDA2: TDA2xx record video in mp4 (original is yuv)

Part Number: TDA2 Tool/software: TI-RTOS Hi, we want to record video and save in SDcard in mp4 format. does there any utils\link can be used? SDK vision is 03_04 Thanks~~

Hi, .mp4 is a container format. You can save the video in .h264 format after encoding but you need to convert that and that support is not available with VSDK. Regards, Anuj

Part Number: TDA2 Hi, As per my understanding in the config file, we have option to select EVE or DSP core by selecting layersGroupId(1 for EVE and 2 for DSP). In case, if the model is to be run on multiple EVE cores, say EVE1 and EVE2(first few layers on EVE1 and next few layers on EVE2), is there any way to mention this from the config file? Thanks in advance, Navinprashath.R.R

Yes, we can do that by assigning unique layersGroupId for each of the cores, let's say 1 for EVE1, 2 for EVE2, 3 for EVE3 and 4 for DSP. Note that this layersGroupIds 1 for EVE and 2 for DSP is just an example, you can assign any unique layersGroupId and same mapping should used in running inference. Thanks, Praveen

Ticket Name: TDA2SX: Detailed model number of DSP (C66x)

Part Number: TDA2SX Other Parts Discussed in Thread: TDA3MV Please tell me the detailed model number of DSP (C66x) of TDA2SX. Does this DSP support LAPACK? Also, do I have to port LACACK myself?

Hi, Go through the below link & let me know if you have any questions, I will check with the DSP expert & let you know. Thanks Gaviraju

This link does not provide a detailed model number for the TDA3MV DSP (C66x). Therefore, I don't know if this DSP supports LAPACK.

This link does not provide a detailed model number for the TDA2SX DSP (C66x). Therefore, I don't know if this DSP supports LAPACK.

All TDA2x/TDA3x family of SoCs have TMS320C66x DSPs. You can find more information in the TRM.

Hello, Does TMS320C66xDSP support LAPACK? Also, do I have to port LACACK myself?

First of all, what is the detailed model number of the TDA2SX DSP (C66x)?

Hi, You can get the detailed model number of the DSP by checking the datasheet: https://www.ti.com/lit/ds/symlink/tda2sx.pdf?ts=1602829994367&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTDA2SX And there is a Linear Algebra package that is supported for this DSP https://www.ti.com/processors/digital-signal-processors/libraries/linear-algebra.html#:~:text=The%20LAPACK%20library%20built%20using,optimized%20BLAS%20library%20for%20acceleration. Please refer to this information for details. Regards Karthik

Hello, I checked the datasheet, but I couldn't find the model number of the TDA2SX DSP(C66x). I want to know the "x" part of C66x. Please tell me the detailed model number of the TDA2SX DSP(C66x).

Hello, I checked the datasheet, but I couldn't find the model number of the TDA2SXI checked the datasheet, but I couldn't find the model number of the TDA2SX DSP(C66x). I want to know the "x" part of C66x. Please tell me the detailed model number of the TDA2SX DSP(C66x).

Hello, I couldn't find the model number of the TDA2SX DSP(C66x) & TDA3MV DSP(C66x). I want to know the "x" part of C66x. Please tell me the detailed model number of the TDA2SX DSP(C66x) & TDA3MV DSP(C66x).

Dear user, The x in TMS320C66x does not have any number. Its just meant to represent C66 DSP core pack which is present in different SoC's To the differences in C66 DSP between TDA2SX and TDA3MV please refer to its respective device specifications. They might very in the clock (MHz) or in L2 SRAM size. But will mostly be identical. Is there anything you are looking for other than just the value for x? Because the x really has no value. Regards, Shyam

Ticket Name: Linux/TDA2: what's format the video data (yuv420sp_uv) in buffer?

Part Number: TDA2 Tool/software: Linux i write a algorithm plugin , and it had run. but my algorithm not work. so i want save one frame data to debug in algorithmLink_process function. there is a problem i occured . the slice of my code as follow, the data is YUV420SP_UV format , but i can't play it use yuv player on pc for(bufCntr = 0; bufCntr < numBuffs; bufCntr++) { OSA_memCacheInv((unsigned int) pSysVideoFrameBufferInput->bufAddr[bufCntr], (unsigned int) bufSize[bufCntr]); } frame_count--; if(frame_count == 0) { fp_out = fopen("/home/30.yuv", "wb"); fwrite(pSysVideoFrameBufferInput->bufAddr[0], pInputChInfo->width*pInputChInfo->height, 1, fp_out); fwrite(pSysVideoFrameBufferInput->bufAddr[1], pInputChInfo->width*pInputChInfo->height/2, 1, fp_out); fflush(fp_out); fclose(fp_out); } so , i guess the data storage format in memory is not linear . is right ? can you explain the details to me ? thanks a lot

and i run the algorithm plugin on A15

Hi, The data is linear format only. But typically none of the YUV player support YUV420SP format. Can you please confirm if your player support it? Also can you check if luma only looks correct? Rgds, Brijesh

the file is dum_yuv.txt , it seems like that stroge format is tile .dump_yuv.txt

there is the pictures.

Hi, Can you please check the pitch/line offset of the luma and chroma portion of the image? it seems it is different. Also if possible, can you share this dumped image? Rgds, Brijesh

i had upload the dumped file , it is dump_yuv.txt . res is 1280*800. the pitch should equal the width, but i will check it . the chains is NullSource (A15) -> Decode -> Alg_dms (A15) -> Display i dumped the data at Alg_dms Link, before the alg called .

May be decoder output is not correct, can you check before decoder if nullSource output is correct? Rgds, Brijesh

thanks , i solved this problem , the pitch value is not equal 1280 , it is 2048 .

Ticket Name: TDA2E: A pin cannot be used as a normal GPIO

Part Number: TDA2E TDA's software driver has affected the SD card power supply to remain at 3.3V, because our current hardware design: Y9 pin (sdwp) on the TDA chip is used as the SD card power driver Our software engineers feedback that sdwp has been occupied by the mmc1 software driver, and the Y9 pin cannot be used as a normal GPIO to control the power of the SD card. How do we solve this problem? PS: Our SD card only needs 3.3V running mode

Hi Feng, Can you please post a diagram of your hardware setup for better understanding? Also, one question in advance - is your PCB layout forzen? I.e. you are no longer allowed to make changes to the design? Thanks, Stan

Hi，Stan Yes, we are not going to change the PCB layout The hardware diagram is as follows

The pin mux is typically done outside any driver - in the SBL bootloader. Therefore, you should be able to change Y9 to GPIO w/o driver even knows it. This can be done in the device tree (.dts) file which SBL will reflect in the CTRL_CORE_PAD_MMC1_SDWP SoC register. There are many articles on TI.com and posts in this forum how to do this. On the other hand, the MMC driver will continue (if was enabled) to monitor the Write-Protect (WP) pin, thus this functionality may need to be disabled in the driver. I'm a hardware engineer and I don't know how MMC driver was implemented, but since WP is an optional feature, this should be possible in the driver. Regards, Stan

We has tried the following steps: Configure the kernel's pinmux output to pull up by default, but after the file system is running, we check the status of the gpio and find that this pin attribute becomes the input drop-down. Then the next step, when we tries to manually change the direction property of the gpio, the mmc software driver will report some errors.(As shown below) We analyze the mmc driver and the gpio driver is occupied. How to solve this problem in software?

Hi, Please check your device tree. Most likely, only the cd-gpio is described. wp-gpio is not described. You should be able to use the MMC1_SDWP pad in the GPIO mode 0x14 which will make it connect to the GPIO6_28 line. Refer TRM (CTRL_CORE_PAD_MMC1_SDWP) By default, both CD and WP pads are configured by u-boot to be in the muxmode 0x14 which will be the GPIO mode. Also, If my understanding is correct, GPIO6_28 should be registered as 32 * 6 + 28 = 220 in the /sys/class/gpio subsystem. So you should try to change that. Regards, Nikhil D

Ticket Name: TDA2: About 3D Surround View Issue

Part Number: TDA2 Hi SIr We could preview 4 CHs camera streaming with our AR0140 sensor board on TV via HDMI by using TDA2 EVM with latest linux vision SDK. But we met a 3D surround view (SUR) issue which the stitched images are not acceptable after car rotated around. As the guide of “SurroundView_demo” described: Even though without calibration parameters on TDA2 board, SUR would stitches them together to provide a realistic image of the surroundings to the driver. It should be related to the camera calibration parameters. Do you have any suggestion what we should do in next step ? BR Yimin

Hi Yimin, I cannot provide any more feedback based on the input you have provided. We have tried surround-view on TDA2 board with multiple views and have not faced any issue. Can you provide some more details with images etc? REgards Shashank

Ticket Name: TDA2-17: TDA2 Linux Link from TI.com is not working

Part Number: TDA2-17 http://software-dl.ti.com/processor-sdk-vision/esd/TDAx/vision-sdk/latest/index_FDS.html Hi. I try to download the rootfs / Linux Bin, those 2 links are broken. Can someone fix it? Otherwise, we cannot support the customer. THanks. BR Rio

Hi Rio, I have asked moderators to look at this issue. I have shared an internal link via mail from which you can download rootfs and linux bin. Regards, Rishabh

Thank you very much, Rishabh.

Ticket Name: Linux/TDA2: modify bootpart, mmcdev with uEnv.txt

Part Number: TDA2 Tool/software: Linux Hi Expert, I'm running Linux Vision SDK v03.02.00(4.4.84) on TDA2Ex. To eMMC start, In the boot mode: => setenv bootpart 1:2 => setenv mmcdev 1 => saveenv The result is shown in Figure 1. To SD card start, In the boot mode: => setenv bootpart 0:2 => setenv mmcdev 0 => saveenv The result is shown in Figure 2. Fig1. eMMC start. Fig2. SD card start. I hope to modify bootpart, mmcdev with uEnv.txt. Do not need to enter the boot mode to manually modify. The contents of uEnv.txt are as follows: fdtfile=dra72-evm-infoadas.dtb args_mmc=part uuid mmc 0:2 uuid; setenv bootargs "console=ttyO0,115200n8 vram=16M root=PARTUUID=${uuid} rw rootwait ip=none mem=1024M" bootcmd=bootpart 0:2; mmcdev 0; uenvcmd=boot Orange is new add but it has not changed. Could you please give some suggestion here? Thanks in advance.

Hi, If i understand correctly, you are trying to automate booting either from eMMC or SD card, using the script uEnv.txt. Is that right? What priority/order do you want to set? Regards, Somnath

Hi, Yes, using the uEnv.txt. sd card first, eMMC second. Thanks in advance.

Hi, Please refer include/configs/ti_omap5_common.h 1. Modify the CONFIG_EXTRA_ENV_SETTINGS to include "emmc_linux_boot" as follows: "emmc_linux_boot=" \ "echo Trying to boot Linux from eMMC ...; " \ "setenv mmcdev 1; " \ "setenv bootpart 1:2; " \ "setenv mmcroot /dev/mmcblk0p2 rw; " \ You can add the above after the definition of "emmc_android_boot=" \ 2. And then, do the following: Change definition of CONFIG_BOOTCOMMAND: replace the following line "run emmc_android_boot; " \ by "run emmc_linux_boot; " \ This should solve your problem. Let me know if you have any further query on this? Regards, Somnath

Ticket Name: CCS/TDA2EXEVM: Un supported data format (FVID2_DF_BAYER_RGGB)

Part Number: TDA2EXEVM Tool/software: Code Composer Studio Hi, I use TDA2EX_EVB connect to a camera. The sensor output is Bayer RGGB 12 bit RAW data. I am making a new chain IssCapture -> (Bayer RGGB 12bit -> RGB888 or YUV420 )-> Display_video I set : pPrm->videoIfMode = SYSTEM_VIFM_SCH_CSI2; pPrm->videoIfWidth = SYSTEM_VIFW_4LANES; pPrm->bufCaptMode = SYSTEM_CAPT_BCM_LAST_FRM_REPEAT; pPrm->outParams[0].dataFormat = SYSTEM_DF_BAYER_RGGB; pPrm->outParams[0].inCsi2DataFormat = SYSTEM_CSI2_RAW12 than I get a error meaasge [IPU1-0] 27.676538 s: dispcore/src/vpscore_dss.c @ Line 1111 [IPU1-0] 27.676599 s: Un supported data format [IPU1-0] 27.676691 s: dispdrv/src/vpsdrv_displayCore.c @ Line 304: [IPU1-0] 27.676752 s: Set DSS parameter failed [IPU1-0] 27.676813 s: Assertion @ Line: 459 in displayLink_drv.c: status==SYSTEM_LINK_STATUS_SOK : failed !!! The error message is from static Int32 VpsCore_dssGetRowInc() because the dataFormate = 0x0056 is FVID2_DF_BAYER_RGGB Is the setting correct? Is TDA2EX supported this color convert?

Hi, Display does not support Bayer format. You will need to convert Bayer format into RGB or YUV to get it displayed. Rgds, Brijesh

Hi, Brijesh, Could you show me the sample code to convert Bayer RGGB to YUV? Best Regards, Jay

Hi Jay, We don't have SW example for this conversion. There is a HW module, ISP, on TDA3x and TDA2Px, which can do this conversion.. Rgds, Brijesh

Ticket Name: Linux/TDA2: PROCESSOR_SDK_VISION_03_03_00_00 when i do : make linux , it ouucr /autorules_footer_cfg.mk:69: *** CODEGEN_PATH_M4 does not exist!

Part Number: TDA2 Tool/software: Linux Afterr i install the PROCESSOR as the VisionSDK_Linux_UserGuide.pdf write , I find that i don't have the directory : $INSTALL_DIR/ti_components/codecs . and when i build as chapter 3.1 make linux ,it oucur this error blow : /home/fee/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/apps/configs/autorules_footer_cfg.mk:69: *** CODEGEN_PATH_M4 does not exist! (/home/fee/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/cg_tools/linux/ti-cgt-arm_16.9.2.LTS). Stop. thanks!

Hi Jacinda, It looks like some issue during installation. Can you please download the installer again and retry. Regards, Rishabh

Hi Jacinda, Can we close the thread if this issue is resolved. Regards, Rishabh

Ticket Name: TDA2: Power Estimation software

Part Number: TDA2 Other Parts Discussed in Thread: TPS65917-Q1, TPS659039-Q1 Hi, I'm trying to estimate power consumption of TDA2SX and found multiple mentions of power estimation tool spreadsheed for TDA2xx (Vayu_Power_Spreadsheet_v1p5), where i can find this tool? If its possible i would like to have have some advice on PMIC selection TDA2SX, TPS659039-Q1 from EVM looks rather unattractive due to BGA package and additional power routing "complications", but I'm unsure if single TPS65917-Q1 will suffice under heavy load, so i'm drawn toward TDA2Pxx recomended combination LP87565C-Q1 + TPS65917-Q1?

Alexander, Let's take this question to direct chat. I'll contact you via your e2e account. Thanks, Kyle

Ticket Name: TDA2: High performance array transposition for EVE core

Part Number: TDA2 Hi, I have to transpose array for EVE next way: data1[y * width + y] to data2[y + x * height]. I try reales thes throw EDMA, but it is slow way. DMA doesn't work with TILER. What is the most efficient way to realise this procedure?

Hi Danil, Using EDMA to do the transpose will not be efficient. You can use VCOP to do the transpose ( look for p_scatter store instruction in VCOP). If you are doing just transpose then DMA will become bottleneck so it would be advisable if you can combine the transpose with some more processing to utilize EVE optimally. Regards, Anshu

Ticket Name: CCS/TDA2: step of EVE Optimized

Part Number: TDA2 Tool/software: Code Composer Studio i have function have to do EVE Optimized, could you tell the step how can i do the work?

HI, You can refer some examples in EVE software librray released by TI to get some idea. Also please refer the TRM for EVE architecture, instruction set to corelate the software examples with the hardware architecture Thanks, With Regards, Pramod

Hi :Pramod could you guide some pdf about TRM for EVE architecture?

EVE is documented in the TRM in Ch 8: www.ti.com/.../sprui29e.pdf Thanks, With Regards, Pramod

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi Everyone, Could any one please help me in understanding what is the Machine learning framework used by the Linux TIDL image classification demo.

Hi, The image classification models in the demo are trained using Caffe-Jacinto framework and they are available in the below GitHub repository. https://github.com/tidsp/caffe-jacinto-models/tree/caffe-0.16/trained/image_classification/imagenet_jacintonet11v2 Thanks, Praveen

Hi Praveen, Currently I am using psdk_rtos_auto_j7_06_02_00_21 package, Could you please located the where to refer image classification demo using cafe jacinto and also provide me a documentation link to understand it better if you have some.

Hi, Do you want demos for TDA2 or TDA4 device because thread subject says TDA2 but you are using J7 (TDA4) package ? Thanks, Praveen

Hi Praveen, Thanks for the reply. I want a TIDL image classification demo for TDA4 J7, Did you have any demo source and build instructions available with you? Currently I could not able to understand the demo source structure but only be able to run the image classification demo over Linux boot and invoking the demo using a the script. But could not able to understand what is the deep learning framework model used i.e; caffe jacinto or tensor flow, how it is getting imported etc. The main requirement of mine to develop and train a deep learning model using TIDL which senses numbers from 0 to 100.

Hi, You can refer following documentation : http://downloads.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/psdk_rtos_auto/docs/user_guide/developer_notes_tidl.html?highlight=demo Regards, Anshu

Ticket Name: Linux/AM5728: TIDL application note

Part Number: AM5728 Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hi. I found this document talking about TDA2 Deep Learning. https://usermanual.wiki/Document/TIDeepLearningLibraryUserGuide.1793363394.pdf My question: A. Can I follow this to test the TI Deep Learning on the AM57xx? B. If no, Why AM57xx has no this kind of APP note? BR Rio

Rio Chan said: A. Can I follow this to test the TI Deep Learning on the AM57xx? No, you can't follow the document that you shared above to program TIDL on AM57x. That is applicable for SDKs for TDAx. Rio Chan said: B. If no, Why AM57xx has no this kind of APP note? Please follow below documentation to program on AM57x.

This kind of user guide cannot be easily to let customer faster get into the TIDL. Also, if you compare the TDA2 DL document, it's more clear than the AM5 User guide. At least, the TDA2 document is more specific to clearly all the steps that AM5 user guide not do so.

Hi Manisha: If you read the TDAx2 documentation, you will find this kind of chapter: in this section: Building Sample Test Application it will tell us those useful information: DSP Code Generation Tool version 7.4.2 EVE/ARP32 Code Generation Tool version 1.0.7 XDAIS version 7.22.00.03 DMA utility Library Version 00.08.00.00 MATH LIB for C66x version 3_1_0_0 But, in the AM57 user guide, there is no such clear instruction we can follow up. With this kind of situation, how do we educate our customers? Please specify. Thanks. BR Rio

Hi Rio, The TIDL on vision SDK is different than on Sitara Processor SDK Linux. On Sitara processor side, TIDL library is a black box. The source code on DSP or EVE side is not opened, and hence they do not need to learn about the tool chain, compiler information etc. On Sitara Processor SDK Linux, TIDL library is accessed using TIDL API (underneath uses OpenCL to offload the acceleration on DSP/EVE) and runs on host A15 side. Hope that clarifies. If you have any other concern with current document, I will be happy to learn that and feedback to my team to improve the document. Regards, Manisha

Hi Manisha: I have read the entire TIDL several times. I have some questions, Please see the posted picture. A. There is the TIDL Import tool I can download? ( I ever sent you an email, but got no reply yet.) B. What's the OpenCV / OpenCL version that we support? C. Regarding the grey part " ML application", what's the example of it? Where we can find it? D. Component off " TIDL SW stack", what is this? I'm preparing a Training slide to our customers, and I need to have 2~3 working examples (beside the TI DL demos) runs from steps by steps clearly. Do we have a training slide for letting customers feel better than just to see a DL demo? BR Rio

Ticket Name: CCS/TDA2: None of the currently selected products s...try using a pre-3.30 version of XDCtools.

Part Number: TDA2 Tool/software: Code Composer Studio i make a new eve project use this SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\kernels\imgsiglib\vcop_median3x3 if i add testvecs\config this file in to the project, IDE tips it need the XDC tools , i sellect yes! then the project cannot compile. this is the probelm xdc.tools.configuro: Error: no target named: please use -t, -b, or --cb .xdchelp /eve_exmple1 line 52 C/C++ Problem None of the currently selected products s...try using a pre-3.30 version of XDCtools. in my v7 there are 2 xdctools ti_ccsv7\xdctools_3_32_02_25_core ti_ccsv7\xdctools_3_50_04_43_core

Shuai, What do you mean by "if i add testvecs\config this file in to the project". This folder contains various testcases config and none of the files inside it needs to be included in the build. These are only used when you try to execute the testcase. Regards, Anshu

Hi Anshu IDE tips it need the XDC tools , i sellect no! then it is ok ! NOW ccs and vc both ok! thanks! shuai

Hi Shuai, If your issue is resolved, can we close this thread? Regards, Anshu

Ticket Name: TDA2-17: Internal Temperature sensor Accuracy

Part Number: TDA2-17 Hello Is the internal temperature sensor accuracy guaranteed to +/- 2 deg C over the entire temp range (-40degC to 125degC) ? The DM(TDA2x_AAS_SR2.0_DM_vB) does not state explicitly this. Thanks ! Regards, Cristian.

Christian, Yes our testing shows a +/- 2 degC accuracy over the full temperature range. Regards, Kyle

Ticket Name: TDA3XEVM: DCAN Assertion issue..

Part Number: TDA3XEVM Other Parts Discussed in Thread: TDA2, SYSBIOS Hello team, One of my customer who are using TDA2/TDA3x is facing issue for DCAN assertion. The issue is similar to the below e2e issue. But they are not resolved after modified that below post recommended. Here're the logs below. [IPU1-1] 30.071188 s: Id[0x739] [IPU1-1] 30.071646 s: Id[0x73A] [IPU1-1] 30.073110 s: Id[0x73B] [IPU1-1] 30.101201 s: Id[0x73C] [IPU1-1] 30.101659 s: Id[0x73D] [IPU1-1] 30.103123 s: Id[0x73E] [IPU1-1] 30.131184 s: Id[0x73F] [IPU1-1] 30.171201 s: Id[0x739] [IPU1-1] 30.171628 s: Id[0x73A] [IPU1-1] 30.173122 s: Id[0x73B] [IPU1-1] 30.201213 s: Id[0x73C] [IPU1-1] 30.202403 s: Id[0x73D] [IPU1-1] 31.102360 s: Assertion @ Line: 400 in C:/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/apps/src/rtos/modules/dcan/utils_dcan.c: status == 0 : failed !!! [IPU1-1] 31.102574 s: [IPU1-1] 31.102635 s: ### XDC ASSERT - ERROR CALLBACK START ### [IPU1-1] 31.102696 s: [IPU1-1] 31.102848 s: assertion failure: A_badContext: bad calling context. See GateMutex API doc for details. [IPU1-1] 31.102940 s: [IPU1-1] 31.102970 s: ### XDC ASSERT - ERROR CALLBACK END ### [IPU1-1] 31.103062 s: [IPU1-1] 31.103367 s: ti.sysbios.gates.GateMutex: line 99: ti.sysbios.gates.GateMutex: line 99: assertion failure: A_badContext: bad calling context. See GateMutex API doc for details. [IPU1-1] 31.103580 s: xdc.runtime.Error.raise: terminating execution Could you please to guide how to fix it? Best Regards, Ernest

Hi Ernest, Can you please ask the customer to step through the code and see where exactly it is failing? Also ask them to increase 'freeQ' and 'rxMsgQ' size to 50 and try it. Please let me know their observation after this. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

H Ernest, I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi Vivek, Sorry for late response and thank you for your consideration. They already did your guides but the issue still happened. But they solved this issue by modifying below. - SDK reference CAN source use 1 mailbox and receive 1 message, so they modified it to use 8 mailbox and changed msgIdentifierMask. Thank you. Best Regards, Ernest

Ticket Name: TDA2: TIDL-1.1 SSD model test application in host emulation mode encountered memory leak

Part Number: TDA2 Dear all: Recently we use TIDL01.01.00.00 doing vehicle detect, we trained a ssd model. We have an input video, using the ssd model detect vehicles in the video, on the target platform the program runs successfully, but in host emulation mode, with the program running, the PC memory usage increasingly, then after some frames, the program dies. After our analysis, we found the memory leak happing in "tidl_conv2d_base.c" file at line 2370 as follow graph: hope your answers, thanks.

Hi, Could you please try with TIDL latest release TIDL01.01.01.00 ? If you still face the issue with new release also, please share your model and prototxt to replicate the issue. Thanks, Praveen

Dear Praveen: Now we don't have TIDL01.01.01.00 sources, so we couldn't build tidl_alg.lib for pc.

Hi, Could you please download it from the same CDDS link and try? It is good to have latest release as fixed couple of bugs. Thanks, Praveen

thanks, i have solved the problem.

Ticket Name: RTOS/TDA2SG: DDR usage

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS May I know how to get the DDR usage in percentage? Thank you

Hi, You can see DDR usage by using print statistics “p” option on UART console when you are running Processor SDK Vision. You can see TDA2 performance app note to see theoretical max bandwidth and actual max, then calculate the percentage. Regards, Rishabh

Hi TDA2 performance app note. Could you please pass me the url? Thank you for quick reply:)

Hi, Here is the link: www.ti.com/.../sprac21.pdf Regards, Rishabh

Ticket Name: Linux/TDA2: DDR memory partition

Part Number: TDA2 Tool/software: Linux Is there a recommendation for address division between the two channels of EMIF1 and EMIF2? When using two-channel DDR, can the software be designed to run the system only in the DDR of the EMIF1 channel?

Hi, If possible for your application, the recommendation is to interleave the two EMIFs to improve bandwidth . Please see section 18 of the following application note for more details: www.ti.com/.../SPRAC21 However, you can partition the memory such that the lower half (or upper half) of memory is all on EMIF1 or EMIF2. The application note mentioned above should give an example of how to set the EMIFs in interleaved or non-interleaved modes. If you have additional questions related to this, please let us know. Best regards, Kevin

Ticket Name: RTOS/TDA2: Does visionSDK support <opencv2/objdetect> ?????

Part Number: TDA2 Tool/software: TI-RTOS Hi, I'm trying to compile the code which is using the cascadeClassifier in <opencv2/objdetect>. However when refering to <opencv2/objdetect>.structure or whatever it is in, the compile error occurs So, my question is Does visionSDK support <opencv2/objdetect> ?????

duplicate question. refer to post with subject Compiler/TDA2: Fail to linking openCV file (objdetect) e2e.ti.com/.../688944 Thanks, Pramod

Ticket Name: Linux/TDA2: Measure execution time in A15 link on TDA2xx

Part Number: TDA2 Tool/software: Linux Hello, I am using TDA2xx and Vision SDK 3.02, build machine is Ubuntu 16.04 with kernel 4.16.7. I have a VSDK link running on A15 core with Linux and would like to find out the execution time of one of the functions. This link used to run on RTOS before and Utils_getCurTimeInUsec() was used. However, I cannot find equivalent function to use with HLOS. Thank you in advance. Regards, Nick

Hi Nick, on HLOS there is "OSA_getCurTimeInMsec" (defined in vision_sdk/links_fw/src/hlos/osa/src/osa.c). If you need microseconds, I think you can use also standard gettimeofday() from "sys/time.h" (OSA_getCurTimeInMsec is implemented using gettimeofday). Regards, Yordan

Ticket Name: CCS/TMS320C6748: TMS320C6748 NOR Writer Failing OMPL-138 Nor Flash Writer ?

Part Number: TMS320C6748 Other Parts Discussed in Thread: OMAP-L138, OMAPL138 Tool/software: Code Composer Studio Hai Sir, I am using TMS320C6748 processor with MT28EW512ABA1HPN NOR flash using before we used MT28EW256ABA properly working but in 512Mb problem occurring through OMAPL-138 AISGen software. Below error displayed. Starting OMAP-L138 NORWriter. CFI Query...passed. NOR Initialization: Command Set: AMD Manufacturer: INTEL Size: 0x40 MB Enter the binary AIS application file name (enter 'none' to skip): ASPB_Monitor.bin INFO: File read complete. Erasing the NOR Flash Erased through 0x60020000 Erase Completed Writing the NOR Flash Data verify failed. We are selected below method in AIS Gen Software: Device Type: d800k006 DSP Boot mode : NOR FLASH Clock Source: CRYSTAL 25MHz FLASH DATA WIDTH:16-bit CS2 setup: 0x3FFFFFFC Thanking You, Regards, Ramachandra

Hi, Ramachandra, Could you let us know which SDK (RTOS or Linux) you are using, and its release version? Thanks! Rex

Hi Rex, I am using OMAPL-138 starterware not using any OS through this AISGen software i am downloaded? for 256Mb Micron previos i am worked but 512Mb first time? I am able to read Manufacture ID and Device ID while loading File L2 RAM to Flash failure occurs not writing? could you give me the any suggestions, Thanking you, Regards, Ramachandra.

Ramachandra, If you are able to read the manufacturer ID and Device ID, can you also confirm if you can read the first 32 KB of the NOR flash ? Can you also confirm that the EMIF NOR connection with OMAPL138 matches the guidelines provided in Appendix B of the guidelines provided in the schematic review guide : Are there any code changes to the NOR flash writer that we provided. Each CS on EMIF only has 32 KB of direct address mapped in the memory map, so how are you accessing > 32KB data. Regards, Rahul

hai sir, Based on above pdf(NOR HardwareConnectionfor 32 M x 16 Device) we have same thing used but only single chip select (CS2) used in below diagram. For us only 32MB is enough other apart not required please check in above schematic diagram then i'm able to read the device ID and size proper way but write failure occurring. Could you give me some suggestion, Thanking you, Are there any code changes to the NOR flash writer that we provided. Each CS on EMIF only has 32 KB of direct address mapped in the memory map, so how are you accessing > 32KB data.? I am not changed in nor writer code Regards, Ramachandra

Hai sir, When i am writing to nor flash properly writing and poweron reset time it's showing 0xFFFFFFFF after soft reset data showing original data showing i checked in memory browser window of ccs. May be it's the problem of reset not occring on power on time or any problem sir. Thanking you, Reagards, Ramachandra

Part Number: TDA2 hi, dear Now although I bought serveral tda2x boards, I have only got part service from the TI tech support in Shanghai of China. I could not get the source code of TIDL. So if I want to run my improved cnn model , I can only run it on the tda2x board not on PC simulator. I have imported the cnn model to the bin format which is suitable for TIDL. Yet the input data need to be resize to 368 X 368，and I should resize it by myself( It has to be the TI method to resize). Even worse, the configuration file (only seg , ssd detection included)on the tda2x board looks like that below: TIDL Configuration parameters ----------------------------- ################################################################################ IMP: Make sure the size of the file names (excluding extension) is not more than 8 characters. ################################################################################ inputWidth=1024 inputHeight=512 inputFile=IN.RGB outputFile=OUT.BIN netFileName=NET.BIN paramFileName=PRM.BIN My cnn net is not for detection or classifcation, but pose recognition. I do not know if I can use this demo cfg file to run my cnn model successfully on the tda2x. If not , could you please be kind enough to offer me new cfg file or make some change for me to run? tks, looking forward to your reply.

Hi, It looks like duplicate thread to below thread, hence closing this thread e2e.ti.com/.../723315 Thanks, Praveen

Ticket Name: RTOS/TDA2P-ACD: RGB888 or YUV420_SP conversion to BGR565 format

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hi, I'm working on VisionSdk 3.5 and TDA2P-ACD board. My input is in RGB888 or YUV420_SP. I want to convert it BGR565 format. Whether is it possible to convert it to BGR565 format using VPE or dss_m2mwb link or any other link? Regards, Megha

Hi Megha, You can do this using DSS M2MWB. Regards, Rishabh

Hi Rishabh, Thank you for the reply. Dss M2MWB supports all formats of Fvid2_dataformats. I checked that there is supported format named FVID2_DF_BGR16_565_A8. But I want only BGR16 565 (16 bit)and not A8 part. What should I do ? Regards, Megha

Megha, FVID2_DF_BGR16_565 is supported for all TDA2/TDA3 devices. Please see <pdk>\packages\ti\drv\vps\include\dss\vps_m2mDss.h. Regards, Rishabh

Hi Rishabh, Thank you for the reply. It really helped a lot. Regards, Megha

Hi Megha, Glad that your issue is resolved. Please mark relevant posts as "This resolved my issue" and close the thread. Regards, Rishabh

Ticket Name: RTOS/TDA2: ERROR of TIDL_OD usecase

Part Number: TDA2 Tool/software: TI-RTOS Hi we want to run TIDL_OD use case but I got an ERROR below Can you tell anything to us? How do we do? Can you provide guide for our reference? And we create another thread below https://e2e.ti.com/support/arm/automotive_processors/f/1021/t/689655 but we got the reply never Can you answer these two thread for us?

Hello what is the vision SDK version you use, try to use 3.3 version and TDA2x EVM. refer guide \vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_TI_DeepLearning.pdf to build and run TIDL demos from VSDK regards, Shiju

Hi, I use the SDK v3.03 version and TDA2x EVM And the other thread has any reply?

OK, please refer guide \vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_TI_DeepLearning.pdf to build and run TIDL demos from VSDK regards, Shiju

OK please help me to resolve the other thread question

Ticket Name: TDA2: Disable the unused cores

Part Number: TDA2 Hi Sir, In my project we are not using the EVE3, EVE4 and some other cores. So how can I disable them completely to save the power? Do I need to disable only power state or also need to disable the clock state and need to disable the module also? Best Regards, Sagar

Hi Sagar, Are you using TI SBL? If yes then the SBL will put unused cores (those which are not there in Multi core image) to low power state. Regards, Rishabh

Also you could remove the unused/not required cores from vision_sdk/apps/config/select_config/cfg.mk file. Rgds, Brijesh

Hi Brijesh, Is this vision_sdk is applied for Lauterbach also. Because I am not using CCS tool of TI. Regards, Sagar

Hi Sagar, Not really, i was just talking from vision sdk. for CCS, you could remove unused cores in target configuration. But this is all on host side. On target side, as Rishabh mentioned, SBL, Boot loader, should know what cores required and power on and enable only them. Regards, Brijesh

Hi Sagar, As this question is followed up in another thread e2e.ti.com/.../760829, I am closing this. Regards, Rishabh

Ticket Name: CCS/TDA3XEVM: TDA2/3 EVE tool - ARP32 cannot download?

Part Number: TDA3XEVM Other Parts Discussed in Thread: TDA2 Tool/software: Code Composer Studio Hi Champs: By reading this doc: /ti_components/algorithms/eve_sw_01_19_00_00/docs/eve_sw_getting_started.pdf, section 3.2.1, there is an ARP tool needs to download from this link: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_ccstudio/codegen/Updates/p2win32 However, this link is missed. Anyone can fix this? BR Rio

Hi Rio, This not a html link. You have to follow the steps as mentioned in eve_sw_getting_started.pdf to understand the installation instructions. ARP32 compiler also comes as part of SDK release and can be found at following location inside SDK : ti_components/cg_tools/arp32_1.0.7 Regards, Anshu

Hi Anshu: Thanks, I already install the EVE compiler. 1 more question: By reading this: file:///C:/PROCESSOR_SDK_VISION_03_07_01_00/ti_components/algorithms/eve_sw_01_20_00_00/docs/eve_sw_getting_started.pdf There is only the TDA2 EVE building. Will the TDA3 EVE buidlign procedure the same with TDA2's EVE? BR Rio

BTW, how to create / import a TDA3 project?

Hi Rio, Both TDA2 and TDA3 have same EVE IP and hence same EVE binaries can be used for both. Regards, Anshu

What do you mean by create/import a TDA3 project? Regards, Anshu

Hi Anshu: Thanks for your helping. Originally, I'm the SW for Wireless + Sitara. I thought the PSDK of TDA2/3 is the same with Sitara. So, does it have the "create_project.bat" for creating the TDA2/3 proejcts? So that we can import and build the EVE? In short, my question is: once I set up the CCS5.4.0.91, how to import an existing / created project to build for EVE? The PDF didnot tell us how to import / create a project of EVE. Thanks. BR Rio BR Rio

Hi Rio, Do you mean CCS project when you say create/import project to TDA3? Regards, Anshu

Yes, your understanding is correct.

Rio, We don't support CCS project as we use make based build. You can build the EVE library/test bench using the gettingStarted guide of EVE. The same can be loaded to CSS for running. If you want to create a project you can refer the makefile used for the build and create. Regards, Anshu

Ticket Name: TDA2: What is purpose of VPE in TDA2x Superset?

Part Number: TDA2 Other Parts Discussed in Thread: DM505, Is VPE in TDA2 similar to ISS in DM505? Can live video processing be achieved using VPE module? If yes, would it be purely hardware?

Amer, VPE is difference module on TDA2x and is not similar to ISS.. VPE can be used for the scaling and color conversion operation, whereas ISS can be used for Bayer to YUV conversion and scaling.. Rgds, Brijesh

Hi, Amer Naseem, In addition to Brijesh's answer, please download the Technical Reference Manual books for both devices and go through chapter 7 Imaging Subsystem (for TDA2) in and Chapter 10 Video Processing Engine (for DM505) in Regards, Mariya

Ticket Name: RTOS/TDA2: CAN bus protocol sample code

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, TI have any CAN bus protocol sample code for reference? (CANopen, SAE J1939 or etc)

Hi Prince, SAE J1939 standard is supported by MCAN module which is available on TDA2Px only. MCAN sample example is available at: '<vsdk_install_dir>\ti_components\drivers\pdk_xx\packages\ti\csl\example\mcan'. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi Mr.Vivek, Understand and thank for your support.

Ticket Name: Compiler/TDA2: TDA2

Part Number: TDA2 Tool/software: TI C/C++ Compiler Hi, I made new usecase one. But, the log shows below. [HOST] [EVE1 ] 77.188769 s: IPC_IN_0 : Create in progress !!! [HOST] [EVE1 ] 77.189867 s: IPC_IN_0 : Create Done !!! [HOST] [EVE1 ] 77.190752 s: ALG: ERROR: No alg create function specified (algId = 6) !!! [HOST] [IPU2 ] 77.187915 s: IPC_OUT_0 : Create in progress !!! [HOST] [IPU2 ] 77.188251 s: IPC_OUT_0 : Create Done !!! The algID 6 is census algorithm. In cfg.mk, I added ALG_census = yes. So, In App_init(), AlgorithmLink_census_initPlugin() will be called. What is problem? Thanks, Best regards, Heechang

Hi Heechang, Please use the below command to check whether your algorithm is getting build or not? make showconfig Please follow the below doc to know how to build or integrate an algorithm link. vision_sdk\docs\FeatureSpecificUserGuides (section 4)

Hi Anuj >make showconfig ....... ....... # Alg plugins included in build, # ALG_autocalibration ALG_census ALG_disparityhamdist ALG_dmaSwMs ALG_framecopy ALG_remapmerge ALG_sceneobstruction ALG_stereo_postprocessing ALG_surroundview ALG_iss_aewb # # Use-cases included in build, # UC_iss_capture_isp_simcop_display UC_srv_calibration UC_iss_multi_capture_isp_simcop_stereo UC_lvds_vip_multi_cam_3d_srv UC_csi2Cal_multi_cam_3d_srv UC_csi2Cal_multi_cam_view UC_lvds_vip_multi_cam_view_sgx_display UC_vip_single_cam_connectorLinksA15_sgx_display UC_vip_single_cam_enc_dec_sgx_display UC_vip_single_cam_framecopy_sgx_display UC_vip_single_cam_framecopyEve_sgx_display UC_vip_single_cam_sgx_display UC_iss_multi_cam_isp_sgx_3d_srv_display UC_iss_multi_cam_isp_sgx_2mp_3d_srv UC_iss_multi_cam_isp_sgx_2mp_3d_srv_adaptive Algorithms is getting build(ALG_census) and my use-case is getting build too. The status return value is -7 when the census algorithm link is created. And, the census algorithm parameters are below. [HOST] [HOST ] 126.605319 s: imDim->disparityInputImageWidth:720, imDim->disparityInputImageHeight:376 [HOST] [HOST ] 126.605319 s: imDim->disparityInputLeftImageStartX:68, imDim->disparityInputLeftImageStartY:5 [HOST] [HOST ] 126.605319 s: imDim->disparityInputRightImageStartX:5, imDim->disparityInputRightImageStartY:5 [HOST] [HOST ] 126.605349 s: imDim->censusOutputRoiWidth:720, imDim->censusOutputRoiHeight:376 [HOST] [HOST ] 126.605349 s: imDim->censusInputImageWidth:800, imDim->censusInputImageHeight:384 [HOST] [HOST ] 126.605349 s: imDim->censusInputImageStartX:4, imDim->censusInputImageStartY:4 [HOST] [HOST ] 126.605349 s: imDim->remapImageWidth:800, imDim->remapImageHeight:384 [HOST] [HOST ] 126.605349 s: imDim->origRoiStartX:72, imDim->origRoiStartY:9 Thanks, Best regards, Heechang

Hi, This error will come when it do not find the create function of the algorithm. Can you make sure by adding some logs inside AlgorithmLink_census_initPlugin() whether the create function is null or not? Please make sure you have added the algorithm as yes in usecase cfg.mk Regards, Anuj

Hi, I cannot see log though I inserted the print log in App_init(). I have a question. The Census Algorithm run on EVE. In case of A15(Linux) <-> IPU(BIOS) <->EVE(BIOS), should I modify makefile for this case(using EVE and linux build)? Thanks, Best regards, Heechang

Hi, To run linux on A15 please follow the below doc vision_sdk\docs\Linux\VisionSDK_Linux_UserGuide.pdf And please add log inside AlgorithmLink_census_initPlugin() to verify whether create is called or not. Regards, Anuj

Hi, I resolved this issue by uploading EVE firmware which is modified. Thanks, Best regards, Heechang

Ticket Name: TDA3MV: Dual memory controller PCB tracing (with ECC)

Part Number: TDA3MV Other Parts Discussed in Thread: TDA2, Hello, we making designs of some ADAS devices on TDA2, TDA3. Sure we have NDA. We want use dual memory controller configuration. But all that we seen before (EVM and other designs) using only one memory controller. Where can we get PCB tracing (design or recommendations) for dual controller + ECC? Recommendation about tracing of FCBGA 784 (ABZ package) will be useful too.

Hi, TDA3MV does not support a dual memory controller configuration. For TDA2, you can check under the "Technical Documents" on the product page for the reference design files as shown below. Please let us know if this does not answer your question; thanks! Best regards, Kevin

Ticket Name: RTOS/TDA2: TDA2 Network stereo on IPU1_1

Part Number: TDA2 Tool/software: TI-RTOS Hello Team, Having trust in the support team, I believe, some mistake could have happened in the previous posting, Since there was no reply for a long time. Could you please check the details in the post (730834): e2e.ti.com/.../730834 We are looking forward to your answers and suggestions. Regards, KK

Sorry for delay, we have replied on original thread. Kindly please close this thread.

Ticket Name: RTOS/TDA2EVM5777: Setting for SV DEMO on TDA2 EVM

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Dear Champs, My customer is trying to run SV DEMO on TDA2 EVM using pre-built image included in VisionSDK v3.02 and successfully to run DEMO display, but there is only 1 camera displayed in SV DEMO. Could you please let me know settings of Vision daughter board and deserialize board to run SV DEMO? in my customer's display, camera1 and 3 - blank. camera2 - green(only green color displayed) camera4 - display When I changed cameras each other, same situation occurred as above.(only camera4 was displayed and camera2 was green) customer's SW3 of Vision board is as below. and deserializer board is as below. Thanks and Best Regards, SI.

Hi SI, I have forwarded your question to VisionSDK experts. Regards, Yordan

SI the SW3 switch setting in SW3 on TDA2xx Vision Application Board is not correct refer \vision_sdk\docs\UserGuides\VisionSDK_UserGuide_TDA2xx.pdf. section : 2.3.2 LVDS MCV Use-case Hardware Setup and 2.3.3 Capture Pin Settings SW3 should be set as below for 4ch LVDS setting (used in SRV) LVDS OFF OFF ON OFF OFF ON OFF ON regards, Shiju

Hi Shiju, After changing SW3 setting, I found DEMO ran well. Thanks for your support. I have a question for de-serializer board setting. I found DEMO worked well with below default setting. Is this normal? Is there any detailed document for de-serializer board? I could not find any document for de-serializer board in the Spectrum Digital's web. Thanks and Best Regards, SI.

SI The default jumper setting would work as of today we do not have any document for this, will plan to add a picture of the same regards, Shiju

Ticket Name: TDA2P-ABZ: Does this board support Deep learning accelaration (TIDL)?

Part Number: TDA2P-ABZ Other Parts Discussed in Thread: TDA2 I'm trying to figure out if our boards will get any speedup from going through the TIDL conversion, on one hand https://training.ti.com/overview-ti-deep-learning-tda2-and-tda3-adas-platforms this link this claim accleration, on the other hand in the TIDL userguide , https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/07_00_00_11/exports/docs/tidl_j7_01_02_00_09/ti_dl/docs/user_guide_html/md_tidl_overview.html, it lists only TD4 as deep learning accelerated. Can anyone shed some info?

Hi Joseph, TDA2 and TDA3 are old generation boards which can do TIDL conversion, but on these boards there is no active TIDL development and limited support. TDA4 is our new generation more capable device with active TIDL development and also supports huge variety of DL networks with different frameworks. We would suggest to evaluate TDA4 for DL acceleration. Thanks, Praveen

Ticket Name: Linux/TDA2: TDA2X BSP DRIVER UNIT/SYSTEM TESTING SAMPLE PROGRAMS

Part Number: TDA2 Tool/software: Linux Hello, how to test all TDA2x BSP driver ?

Hi, Can you refer to processors.wiki.ti.com/.../PDK_TDA_VPS_User_Guide and processors.wiki.ti.com/.../PDK_TDA_BSPLLD_User_Guide Regards, Rishabh

Ticket Name: TDA2: The resolution limited of TDA2X

Part Number: TDA2 Hi We need to use two LCD(LCD1 & LCD2) to output two different videos. The resolution of the two videos if 1920*1080@30fps & 1280*720@30fps. We want to confirm that , dId it has the limitation of the resolution & fps of the DSS module ? And what's the MAX resolution & fps can the DSS support? Please take a look. Thanks.

Hi, Can you please refer chapter 1 of TDA2xx TRM. Thanks. Regards, Rishabh

Three LCD outputs, each one with dedicated overlay manager, for support of active matrix color displays (up to 24-bit interface). Maximum listed resolutions are not supported concurrently on all outputs. • First main LCD output delivered on MIPI® DPI 1.0 LCD pixel interface, supporting up to WUXGA (1920 x 1200) with reduced blanking periods. • Second and third LCD outputs delivered on MIPI DPI 2.0 LCD pixel interfaces, supporting up to WUXGA (1920 x 1200) with reduced blanking periods. I saw this description , we just want to confirm that does it will has diference when we use two LCD at the same time ? Or , it can support 1920*1200 no matter how many LCDs we used, right?

Hi User, Yes, DSS can output two independent resolutions ie 1920x1080@30fps and 1280x720@30fps on LCD1 and LCD2 outputs.. it is possible. Regards, Brijesh

Ticket Name: Linux/TDA2: #pragma DATA_SECTION to UTILS_HEAPID_DDR_CACHED_SR

Part Number: TDA2 Tool/software: Linux Hi: i am useing SDK_VISION_03_04_00_00\vision_sdk in a dsp1 link i want put my model to UTILS_HEAPID_DDR_CACHED_SR, #pragma DATA_SECTION (model,UTILS_HEAPID_DDR_CACHED_SR ); MInt32 model[] = { 177, 301, 176, 321, 176, 340, 177, 359, 180, 379, 184, 398, 189, 417, 195, 435, 202, 453, 212, 471, 223, 487, 235, 502, 249, 516, 263, 529, 278, 541, 294, 553, 311, 562, 331, 568, 352, 569, 374, 566, 396, 558, 414, 547, 431, 533, 446, 519, 460, 504, 473, 488, 484, 470, 493, 451, 499, 431, 503, 412, 506, 392, 507, 373, 508, 353, 507, 334, 506, 314, 504, 294, 501, 275, 199, 272, 215, 257, 235, 253, 256, 255, 276, 260, 290, 274, 272, 273, 254, 270, 236, 268, 218, 269, 356, 267, 370, 251, 392, 243, 415, 238, 438, 238, 459, 250, 438, 252, 417, 255, 396, 260, 376, 265, 223, 308, 232, 302, 242, 298, 254, 297, 266, 299, 276, 305, 282, 314, 273, 316, 263, 318, 253, 319, 242, 317, 232, 314, 373, 305, 381, 294, 391, 287, 404, 284, 417, 284, 428, 286, 438, 293, 429, 300, 419, 304, 408, 307, 396, 307, 384, 306, 307, 302, 309, 337, 306, 373, 289, 391, 298, 412, 327, 415, 347, 413, 377, 406, 382, 384, 363, 368, 355, 333, 352, 298, 280, 461, 300, 451, 324, 443, 343, 444, 362, 438, 388, 440, 413, 445, 396, 463, 375, 476, 349, 483, 322, 482, 299, 475, 286, 462, 315, 460, 345, 458, 376, 452, 407, 447, 377, 455, 346, 461, 315, 462, 253, 309, 406, 296, 328, 301, 330, 332, 332, 362, 334, 391, 337, 414, 253, 307, 409, 294, }; can i ? Shuai

Hi, You can give it a try but i guess initialization of that array is not possible. Regards, Anuj

Hi Anuj the model is too big ! i am try to read it in A15 and send it to c66. but in ccs i use nitialization of that array is ok! shuai

Hi, Please initialize your array inside your usecase or from where it gets called or inside link init if you are using it inside a link. Do not do it globally. Regards, Anuj

Ticket Name: TDA2SX: TDA2x: VISION SDK OPENVX Support

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi, Expert, I want to confirm if VISION SDK support OPENVX or not ? Do we have any guide for reference.? Thanks. Regards, Fredy Zhang

Hi Fredy, Yes, but it was just support for OpenVX framework and some OpenVX standard kernels running on C66x. Most of the other modules were supported only in vision sdk. So i really doubt framework along would be useful. Regards, Brijesh

Brijesh, Thanks. Do we support OpenCV on TDA2? any guide ?Thanks. Regards, Fredy Zhang

Hi Fredy, Please check vision sdk release notes/user guide. As far as i recollect, we did not support OpenCV on TDA2. Regards, Brijesh

Brijesh, I check the release notes : 1. VISION SDK support OPENCV : https://software-dl.ti.com/processor-sdk-vision/esd/TDAx/vision-sdk/03_07_00_00/exports/VisionSDK_ReleaseNotes.pdf 2. OpenCV support on kernel 4.4. and didn't support on 4.19. https://processors.wiki.ti.com/index.php/Processor_SDK_Linux_Automotive_Release_Notes Regards, Fredy Zhang

Ticket Name: Compiler/TDA2: Vision SDK TDA2xx (v03.03.00)

Part Number: TDA2 Tool/software: TI C/C++ Compiler Hello, I am referring to Vision SDK TDA2xx (v03.03.00) User Guide 2 System Requirements 2.1 Windows Installation 2.1.2.1 A15 Compiler, Linker The windows installer for the GCC ARM tools should be downloaded from below link launchpad.net/.../4.9-2015-q3-update The tools need to be installed under “<install dir>/ti_components/cg_tools/windows/”. IMPORTANT NOTE: A15 Compiler and linker MUST be installed before proceeding else compile will fail. Also make sure the compiler is installed at the exact path mentioned above Observing error while creating dependencies as shown in log: --- $ gmake -s -j depend # makeconfig: Config is [ tda2xx_evm_bios_all ] # makeconfig: Output file is @ C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/include/config/sample_app/tda2xx_evm_bios_all/system_cfg.h # makeconfig: Input file is @ C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/build/configs/tda2xx_evm_bios_all/cfg.mk # makeconfig: Generating header ... # makeconfig: Generating alg plugin config ... # makeconfig: Generating usecase config ... # makeconfig: Generating footer ... # makeconfig: Done !!! # # CPUs that are NOT required but included in config [ tda2xx_evm_bios_all ], # # WARNING: IPU1_1 can be excluded from application # WARNING: A15_0 can be excluded from application # # CPUs that are required but not included in config [ tda2xx_evm_bios_all ], # # # Edit C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/build/configs/tda2xx_evm_bios_all/cfg.mk to include or exclude CPUs in an application # # Compiling tda2xx-evm:a15_0:release:edma3lld_drv: src/edma3_drv_init.c # Compiling tda2xx-evm:a15_0:release:edma3lld_drv: src/edma3_drv_basic.c process_begin: CreateProcess(NULL, C:/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/bin/arm-none-eabi-gcc -MD -MF C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/binaries/sample_app/tda2xx_evm_bios_all/obj/edma3lld_drv/tda2xx-evm/a15/release/.deps/edma3_drv_basic.P -c -mcpu=cortex-a15 -g -mfpu=neon -mfloat-abi=hard -mabi=aapcs -mapcs-frame -ffunction-sections -fdata-sections -DSYSBIOS -DCGT_GCC -DCPU_IDLE_ENABLED -O2 -s -DNDEBUG -Werror -Dxdc_target_types__=gnu/targets/arm/std.h -Dxdc_target_name__=A15F -Dxdc_bld__profile_release -Dxdc_bld__vers_1_0_4_9_3 -DBIOS_BUILD -Dfar= -D__DYNAMIC_REENT__ -DTDA2XX_BUILD -DTDA2XX_FAMILY_BUILD -DPLATFORM_EVM_SI -DVPS_VIP_BUILD -DVPS_VPE_BUILD -DVPS_DSS_BUILD -IC:/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/os_tools/bios_6_46_04_53/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/include -IC:/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/arm-none-eabi/include -I. -I../../../.. -Isrc -IC:/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/networking/ndk_2_24_02_31/packages -IC:/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/networking/nsp_gmacsw_4_15_00_00/packages -IC:/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/open_compute/opencl_rtos_am57xx_01_01_10_00/packages -I/packages -IC:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/links_fw/include/config/sample_app/tda2xx_evm_bios_all -o C:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/binaries/sample_app/tda2xx_evm_bios_all/obj/edma3lld_drv/tda2xx-evm/a15/release/edma3_drv_basic.oa15fg src/edma3_drv_basic.c, ...) failed. make (e=2): The system cannot find the file specified. --- Default installation creates a path: <install dir>/ti_components/cg_tools/windows/4_9-2015q3 But the folder 4_9-2015q3 should be renamed to "gcc-arm-none-eabi-4_9-2015q3". This creates a path as: <install dir>/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3 With this new path, the command is working okay. Could you review, if this okay? Regards, KK

Hi KK, Renaming the directory to "gcc-arm-none-eabi-4_9-2015q3" is correct solution. You can check CODEGEN_PATH_A15 variable which is set to point to this path in file "vision_sdk/build/tools_path.mk". Regards, Yordan

Hello Yordan, The information about the variable and the path is helpful. Thank you for confirming that rename is requried. Hope TI team will be info the users to rename to "gcc-arm-none-eabi-4_9-2015q3" in default user guide. Since the renaming is confirmed to be correct. I resolve the issue. Regards, KK

Ticket Name: TDA2P-ACD: MIPI CSI Internal termination

Part Number: TDA2P-ACD Hi, We need quick information with respect to TDA2Px, In SoC, there will be single 4-lane MIPI CSI and single 2 lane MIPI. But the internal termination details are not available in documents. Could you please help me for the termination, we need to take care of externally? Warm regards, Alwin Mathew

Hi Alwin, I am checking with our board design team. Looking at our board designs, it would appear termination is not required. The traces CSI-2 differential pairs do require 100ohm differential impedance. The receiver input impedance spec is found in Table 5-9. LVCMOS CSI2 DC Electrical Characteristics of the data sheet. Regards, Mike

Hi Alwin, The processor already has built-in termination, so all you need to do is implement your layout and PCB stackup to maintain the 100-ohm differential impedance. Regards, Mike

Ticket Name: Linux/TDA2SX: VIP Capture resolution changes in VisionSDK

Part Number: TDA2SX Other Parts Discussed in Thread: DRA752 Tool/software: Linux Hi. I am using DRA752 CPU on D3 TDA2x setup with OV10635 LVDS Camera. I am new to this, I tried to change the resolution from 1280x720 to 600x400, But I am getting distorted image, unable to capture & display proper image. * I got register settings from OVT for 600x400 (YUV422 & PCLK=24MHz). * Changed the register values in BSP LVDS Structure. * Changed 600x400 in Capture link and Display link. * Written usecases for 1) Capture->Display to display 2) Capture -> Null(A15) to dump. Then, I run application to capture & display as well as capture & dump, But, i am getting distorted image in display and dump both. OVT Suggested, Receiver need to set resolution (image size) properly. Please check if the resolution (image size) setting is correct or not. Is anywhere, am i missed to set the resolution in visionSDK 3.04? I am using only VIP capture Link. I am not using SGX / Encoder also, So I changed in VIP Capture Link and usecase. Is there anywhere i missed ? Thanks & Regards ARUNKUMAR V N

Hi Arun, How are you displaying VGA resolution on 1080p display? Are you enabling scaling in display or just positioning it on display? Also is pitch setup correctly? If you could set the snap of the output (in yuv format), it would helpful in understanding issue. Rgds, Brijesh

Hi Brijesh Jadav, Sorry for confusion. For capture to display, we are using the use-case lvds_vip_single_cam_view_sgx_display i.e.. [ Capture -> Sync (A15) -> SgxFrmcpy (A15) -> Display_M4 (IPU1_0) GrpxSrc -> Display_Grpx ] after changing the capture sensor width and height in use-case as well as capture link. We are assuming the said resolution change, pitch info etc are being taken care by SgxFrmcpy Link. Also, for dump use-case we have a chain [ Capture -> Encode -> NULL] and the recorded dump video is identicle to the video seen on HDMI display in former use-case. Attaching a image extracted from the dump. I can see image in background but lines are coming in foreground. With this additional information about our issue, is there any suggestions you can provide for us to move ahead. Best Regards, ARUNKUMAR V N

Hi Brijesh, I am wating for your reply. I want to downscale 1280x720 to 600x400. I get vip_capture link yuv422 hex data, but its still shows distorted data. ( i played data hexdump from ffplay) Changed capture width and height in lvds_vip_single_cam_view_sgx_display. Changed registers to 600x400 resolution. Changed width and height in capturelink drv.c and .h After All changes display is completely distorted like above image attached CAPTURE: Map Link pVIPcreate mode = 4, width = 0, mode = 0, stream =1 CAPTURE: Map Link pVIP width = 1280, Height = 720, Dataformat = 6, Scanformat = 1 CAPTURE : Outprm width = 1280, Height = 720, Dataformat = 7 CAPTURE: Width = 1280, Height = 720, pitch 1280 1280 0 CAPTURE: framesize_after = 1382400 verbose output of D3 shows below in capture link : [HOST] [IPU2 ] 56.227414 s: CAPTURE: Frame 0: FVID2 CH 0: Link CH 0: 0x84203000, 0x842e4000, 1382400 B [HOST] [IPU2 ] 56.248917 s: CAPTURE: Frame 1: FVID2 CH 0: Link CH 0: 0x84355000, 0x84436000, 1382400 B [HOST] [IPU2 ] 56.270359 s: CAPTURE: Frame 2: FVID2 CH 0: Link CH 0: 0x844a7000, 0x84588000, 1382400 B [HOST] [IPU2 ] 56.291862 s: CAPTURE: Frame 3: FVID2 CH 0: Link CH 0: 0x845f9000, 0x846da000, 1382400 B [HOST] [IPU2 ] 56.313304 s: CAPTURE: Frame 4: FVID2 CH 0: Link CH 0: 0x8474b000, 0x8482c000, 1382400 B [HOST] [HOST ] 56.337125 s: SGXFRMCPY: Create in progress for resolution: 1920x1080 !!! [HOST] [IPU2 ] 56.334838 s: CAPTURE: Frame 5: FVID2 CH 0: Link CH 0: 0x8489d000, 0x8497e000, 1382400 B is there anything i missed ? thanks & regards ARUNKUMAR V N

Hi Arunkumar, The config wise, it looks ok, but i am not sure which component is adding artifacts. It looks like pitch is wrong somewhere, but not sure. Can you dump the frames at the output of each block and check first output is correct, from capture, vpe.. If they are correct, then it is not configured correctly in the display alone. Rgds, Brijesh

Ticket Name: Vision SDK: Reading raw YUV data from NullSource link in order to avoid tidl_OD flicker problem

Hi, I am trying to run tidl_OD example, although it runs, there is a lot of flickering (not related to fps as it only makes the video faster, but does not solve flickering issue). This is valid in the default tidl_OD example. I am using 3.03 currently. I have converted tidl_OD example to use Camera source and there is no flickering. UseCase: chains_tidl_OD NullSource -> Decode -> VPE -> .......... UseCase: chains_tidl_OD_cam Capture -> VPE -> ........ So, I think this means that Decode link is what's causing the flickering. I want to remove Decode link from Txt file and give raw yuv file in SD card. How do I achieve such a thing? UseCase: chains_tidl_OD_raw NullSource -> VPE -> .......... What kind of files are required in the SD card? Is there a usecase example of this? Any guidance is well appreciated. Thanks.

Hi, Refer TIDL use-case example. vision_sdk/apps/src/rtos/usecases/tidl Here raw data(BGR format not compressed) is reading from NullSrc link & sending it to the next link. In this example these parameter are set & modify according to your requirement. pChInfo->flags = System_Link_Ch_Info_Set_Flag_Data_Format(pChInfo->flags, SYSTEM_DF_BGR24_888); strncpy(pNullSrcPrm->channelParams[0].nameDataFile, pObj->inFileName, 260); Make sure raw data should be in the SD card Thanks Gaviraju

Ticket Name: Linux/TDA2: Cross complie opencv, missing vsdk.cmake

Part Number: TDA2 Tool/software: Linux Dear officers, I am trying to cross complie opencv following the user guide "OpenCV_cross_compile_Steps_for_A15_Linux.pdf". But the cmake file "arm-gnueabi.toolchain_vsdk.cmake" can not be found. Would you please provide the file or the download address? Thank you

Hi @user5863765, please check the attachment in this post: Regards, Yordan

Hi Yordan, I have checked the post and do not find the file "arm-gnueabi.toolchain_vsdk.cmake". Do you mean "arm-gnueabi_bios.toolchain.cmake"?

Hi @user5863765 , sorry I missed that. Did you clone the tiopencv from the git and checkout the "tiopencvrelease_3.1" branch? Can you try with "tiopencv/platforms/linux/arm-gnueabi.toolchain.cmake"? Regards, Yordan

Hi Yordan, Sorry for response so late. I have compiled it successfully by using "tiopencv/platforms/linux/arm-gnueabi.toolchain.cmake". But how to add OpenCL/VXLIB/DSP? Can i refer to the settings in "arm-gnueabi_bios.toolchain.cmake"?

Hi, I have pinged OpenCL experts for further help. Regards, Yordan

Hi, please check this post: e2e.ti.com/.../2830341 Regards, Yordan

Ticket Name: TDA2E: JTAG IEEE 1149.7 and system trace (STM)

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Hi Champs, Could you help us with the system trace capability on the TDA2xp? Main question is, if there is documentation available about this topic that we did not find?

Hello Simon, Most of the usage on TDA2 I have seen has happened in conjunction with the JTAG debuggers. CCS and Lauterbach have provided message extraction and decode from internal onchip memories (TBR/ETB) or offchip (via TPIU). Both tools do have documentation on their interfaces. CCS did for a CTOOLs library which could be found on the web and Lauterbach has example projects in its 'demo' directory. Checkouts using these tools has happened on TDA2. The STM unit is a standard ARM Coresigh block so a lot of information will exist on its user level. To use this outside of a JTAG tools environment a fair amount of effort may be needed as interfacing with the hardware trace network and the protocol decoding back into a useable for is non-trivial. For number of years Linaro has been working to push framework to do this into the Linux kernel. I'm not sure what state it has reached. I have not seen anyone try and link that Linux path up for a TDA2. As I mention its has been incrementally adding features in Linux for years and the last time I checked (sometime ago) it was well behind what existing tools supported. This would be another source. That IP has been used on several TI chips and some of them would added additional documentation based on user requests. Some of the OMAPs have additional information. Regards, Richard W.

Hi Richard, Simon posted this question because I contacted him about this topic. We are not using Lauterbach products, but Blackhawk BH-USB-560v2 and Spectrum Digital‘s XDS560v2 emulators. While Blackhawk provided us some useful information, Spectrum Digital told us that this information should be provide by TI. In our TDA2XP based board we are not using Linux, but TI-RTOS. As you said, with some (old) information outside in Internet, it would be probably possible to get this working using the JTAG emulators. But the most useful functionality IMHO is to get the traces in field without the need of connecting any JTAG emulator. I could not find too much information about that and it would be good that TI helped with that, since, as I stated above, it could be useful to find issues in field. Thanks, Alexander

Hello Alexander, For TDA2 I don't believe TI has productized any self-hosted STM utilities. The supported path would be through JTAG tools and those vendors. The base design can support self-hosted usage, but from what I know, developing it from end to end would take a fair amount of time. The scope of that is well beyond an E2E forum post. For some different chips, TI did publish some libraries which could be leveraged: https://processors.wiki.ti.com/index.php/CTools. A Linux level STM driver was socialized at the same time https://processors.wiki.ti.com/index.php/STM_Linux_Device_Driver. A person could leverage that material and what exists in the Linux kernel for Coresight to get something that works for RTOS. I do agree that there are times where having a self-hosted method to select and extract HW trace data might be useful. For STM, on TDA2, I only see JTAG based STM tools available. Self-hosted logging methods in use are mostly to internal memory or out some kind of terminal/network interface. Regards, Richard W.

Ticket Name: RTOS/TDA2EVM5777: About Display link in TIDL SemSeg Usecase

Part Number: TDA2EVM5777 Tool/software: TI-RTOS Hi, I have a question about Display link in TIDL Semantic Segmentation Usecase. I saw the result of Alg_tidlpostproc in TIDL SemSeg usecase is YUV420_SP color map that is indicating each pixel of that map is contained some classes (None, Ped, Vehicle, ...). After processed in Merge/Sync link, the result of Alg_tidlpostproc is in Metadata and original input video frame is in Video Buf. So, the previous link (Alg_tidlpostproc_cpy) of Display link has the buffer that contains video frame and metadata(which is the result SemSeg Network). I refered FVID2 document and it is saying the FVID2 frame has 2 fields like bellow image. Then, in SemSeg usecase, the first field of FVID2 frame is for video frame and second field of FVID2 frame is for metadata? Could you please confirm that i understood correctly?

Hi, yes your understanding is correct but not completely. For field 1 having video buf the representation is same as attached picture but not for metadata buffer. Regards, Anuj

Hi, Thanks for answering. I checked the sync link in TIDL SemSeg usecase adding the log. The all of log message was saying the input buffer is Video Frame data. I think the result of Alg_tidlpostproc link is video frame that is indicating each pixel is belonged to some class by using different color for different class. If this is correct, i'm curious that how the result of Alg_tidlpostproc is overlaped onto each original video frame. Regards, Yoo

Hi, Yes the output of tidl_postproc is video frame. In semseg usecase we use 2 postproc link 1 for creating clut and other for copying it onto original image. Please check below params from usecase pUcObj->Alg_tidlpostprocPrm.outDataFormat = SYSTEM_DF_YUV420SP_UV; pUcObj->Alg_tidlpostprocPrm.outWidth = SEMSEG_INPUT_WIDTH; pUcObj->Alg_tidlpostprocPrm.outHeight = SEMSEG_INPUT_HEIGHT; pUcObj->Alg_tidlpostprocPrm.colPalette565 = pObj->colPalette; pUcObj->Alg_tidlpostprocPrm.inPad = TIDL_MAX_PAD_SIZE; pUcObj->Alg_tidlpostprocPrm.numInputQueues = NUM_PIPELINES; pUcObj->Alg_tidlpostprocPrm.mode = TIDLPOSTPROC_MODE_CLUT;; /* Y and UV copy */ pUcObj->Alg_tidlpostproc_cpyPrm.outDataFormat = SYSTEM_DF_YUV420SP_UV; pUcObj->Alg_tidlpostproc_cpyPrm.outWidth = SEMSEG_INPUT_WIDTH; pUcObj->Alg_tidlpostproc_cpyPrm.outHeight = SEMSEG_INPUT_HEIGHT; pUcObj->Alg_tidlpostproc_cpyPrm.numInputQueues = 1; pUcObj->Alg_tidlpostproc_cpyPrm.mode = TIDLPOSTPROC_MODE_COPY; Regards, Anuj

Ticket Name: Linux/TDA2: tda2 QSPI interface

Part Number: TDA2 Tool/software: Linux Can the tda2 QSPI interface support SDR or DDR mode communication?

Hi, QSPI is used to interface with QSPI flash. EMIF is used to interface with DDR. Regards, Rishabh

Hi，Rishabh You mean the TDA QSPI interface only supports SDR, right? Because I found some SPI Flash ICs can support the following modes: Single Data Rate (SDR) Double Data Rate (DDR)

Hi, If think you are referring to single and quad bit mode. QSPI supports both. Regards, Rishabh

I have already learned through other channels,TDA does not support SPI DDR mode。 thank you。

Hi, Can you please elaborate on the solution and “other channels “. Thanks. Regards, Rishabh

Ticket Name: Compiler/TDA2E: tda2x flash maximum

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi Expert, I'm expected running PROCESSOR SDK VISION v03.05.00 rtos on tda2x custom board. what is the NOR / QSPI flash maximum size support to tda2x? Can it be larger than 256 MByte? Could you please provide some guide on these questions? Thanks in advance.

Hi, Maximum QSPI flash size can be 64 MB. You can use a bigger NOR but TI EVM support only 32 MB NOR and so we have I haven't come across any customer who uses a bigger NOR. You will need to update the NOR timings as per the custom part. Regards, Rishabh

Hi. Please allow me to continue this E2E Thread. #1. If using TI RTOS for TDA2, the default is boot from QSPI Nor Flash, right? #2. If booting from the QSPI Nor Flash, what’s the Maximum size that QSPI Nor can be used? #3. Do we have those below items with Maximum size for TDA2/3/4? Any document? A. Boot Flash B. DDR C. EMMC? #4. To change the QSPI Nor For Booting, is there any document to let the customer follow the process for modifying the code? #5. Can we store those TIDL files on the "Booting QSPI Nor Flash" ? NET / PRM.BIN、TIDLCFG.TXT. if no, how to store them on the EMMC and what are the APIs to access those TIDL files? BR Rio

Hi Rio, Please note that this answer is in context of TDA2/TDA3 family, for TDA4 question please start a new thread. Actually there are two interfaces: GPMC NOR and QSPI NOR. Boot via GPMC NOR is called NOR boot and it supports XIP mode. Boot via QSPI NOR is called QSPI boot. 1. There is nothing like default boot mode. In case SYSBOOT[0:15] is set to 00000000 00000000, RBL does not boot via any interface. Hence this becomes debug boot mode. 2. The maximum size for QSPI is 64 MB. 3. Boot flash can be 64 MB, DDR is 4 GB but not all CPUs will support it. eMMC is not supported in RTOS so you need to ask a separate query for eMMC size. 4. Customers can refer to SBL user guide and Vision SDK user guide. 5. TIDL files are quite big in size, hence you will need SD card. Regards, Rishabh

Hi, How to program TIDL files to qspi (or NOR) flash if it is within 64MB? Could you please provide some guide on these questions? Thanks in advance.

Instead of reading the network and parameters binary files, you can convert the binary files into an array in C code and compile them into AppImage. In tidlODInit(), you will read data from the array instead of from file to fill the NetParams memory. You can find the tool to convert binary to C under ~/vision_sdk/apps/tools/misc_tools/bin2c. As for configuration txt file, you may hard-code the configuration in the use case so it doesn't need to read from file. Regards, Stanley

Ticket Name: Compiler/TDA2EG-17: EDMA on TDA2

Part Number: TDA2EG-17 Tool/software: TI C/C++ Compiler Hi: I would like to enable other core to help my system to flip/mirror/rotate image. 1. Is EDMA(mentioned from this post) support those functions? 2. Is there any tutorial about EDMA? 3. Is there any other way to implement those function on other core? Thank you

Hi, EDMA is a hardware IP and look at TRM for more information. It does not support these functions by default, you will have to configure it accordingly to achieve the desired functionality. EDMA can be run from any core. Hope this helps Regards, Rishabh

Ticket Name: RTOS/TDA2: How to use TDA3 RTOS usecase by tda2xx eve platform

Part Number: TDA2 Tool/software: TI-RTOS Dear All, i have tda2xx eve platform, How to use TDA3 RTOS usecase by tda2xx eve platform?

Hi Owen, This question is asked here as well: e2e.ti.com/.../702309 Please don't start duplicate threads. Regards, Rishabh

Ticket Name: RTOS/TDA2SX: VPE output format for TDA2

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS We need VPE output formant (YUV444p or RGB888p) for TDA2. Does TDA2 support this function ? How can I implement it ?

Yes, VPE does support RGB888 output format. Why do you require YUV444? Regards, Brijesh

Our algorithm input format must be YUV444P and scaled. We want use VPE scaled and output (YUV444P or RGB888) format. But we find vpelink.h. System_VideoDataFormat dataFormat; /**< Output Frame data Format. * VPE link is validated only for the following output dataformats * 1. SYSTEM_DF_YUV422I_YUYV * 2. SYSTEM_DF_YUV420SP_UV So, do you have any sample about VPE scaled output format(YUV444P or RGB888). Thanks

YUV444I is supported by the driver. You need to add support in the VPE link. Note: VPE outputs in YUV444 interleaved and not YUV444 planar.

Hi, Is the RGB888 planar or interleaved? Charles

RGB888 is also interleaved. Rgds, Brijesh

Sorry typo, RGB888 is also interleaved. Rgds, Brijesh

Thanks.

Ticket Name: Linux/TDA2: [VISION SDK] Running a TIDL usecase in LINUX+BIOS mode.

Part Number: TDA2 Tool/software: Linux Hi, I am trying to make very much the same thing like guys in main thread ... First, to avoid porting of tidl_preproc alg on A15, I want to run it on IPU until I have TIDL UC functional and then to port it on A15.. I am using PROCESSOR_SDK_VISON_03_03_00_00 and I am working on custom board that has TDA2xx chips on it (RT-RK Alpha board) UseCase: chains_tidlDsp NullSource (A15) -> Alg_tidlpreproc (IPU1_0) Alg_tidlpreproc (IPU1_0) -> Alg_tidl_1 (DSP1) Alg_tidl_1 (DSP1) -> Merge (IPU1_0) Merge (IPU1_0) -> Null (A15) Steps made during porting the UC are described in txt files that can be found after decompresing tar file added. Also, all changed or newadded files are placed there... Case is: -Free run option for TIDL UC forks fine, but - when runing dump out option (to dump results to the SD card) the UC never finishes... it gives the following output to the console: [HOST] [HOST ] 52.346062 s: ########## FRAME # 0, QUEUE = 0 ########### [HOST] [HOST ] 52.671384 s: ########## FRAME # 1, QUEUE = 0 ########### [HOST] [HOST ] 52.996827 s: ########## FRAME # 2, QUEUE = 0 ########### [HOST] [HOST ] 53.322576 s: ########## FRAME # 3, QUEUE = 0 ########### [HOST] [HOST ] 53.648081 s: ########## FRAME # 4, QUEUE = 0 ########### [HOST] [HOST ] 53.973464 s: ########## FRAME # 5, QUEUE = 0 ########### [HOST] [HOST ] 54.299091 s: ########## FRAME # 6, QUEUE = 0 ########### We figured it out that it is because feof function inside nullSrcLink used for checking end of data stream file never returns TRUE value, but we cannot figure out why is this happening Hope You can help me to solve this, Gretings, Nebojsa changes_in_VSDK_03_03_00_00.zip

Hello The nullSrc on Linux side is written in such a way to always wraparound the input file, so it never stops. You can modify the Nullsrc to with commented out rewind() calls regards, Shiju

Hi Shiju, I have tryed youre suggestion to comment out rewind() calls, but still having the sam result... Just to describe my problem with little bit more details: I am using : IN.RGB NET.BIN PRM.BIN TIDLCFG.TXT those are provided with PROCESSOR_SDK_VISION_03_03_00_00 .... NullSrc did not support work with RGB/BGR files, so I added it in similar way it is done for rtos... When I try to dump out frames to SD card the UC never stops writing it ... If I limit amount of data to be written then sometimes I get good data on the SD card, but not always... Maybe those information can help you to better understand what is happening here ... So if you have still some suggestion for me I would be really grateful.. Thx, Nebojsa

Hi Nebojsa My suggestion here is, if possible please create a simpler nullSRc -> Null data chain and debug your SD card write issue. regards, Shiju

Thx, Have solved this issue... I will add modified NullSrc)tsk.c here and will start a new thread for tidl UC on hlos related questions Regards, Nebojsa 8311.nullSrcLink_tsk.c

Ticket Name: TDA2SX: TDA2 TIDL Quantization

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi, Expert, For TDA2 TIDL, Can you pls help to share the quantization ? do we support both of per layer or per channel ? How to change that ? Thanks Regards, Fredy Zhang

in TDA we support only Per Layer quantization. We do not support per-channel quantization. Only 8-bits are supported for features, 8 -12 bits are supported for weight/Parameter quantizations. Users can set the same in import config files

Ticket Name: TDA2SX: Please help in determining capture to display latency in TDA2 for automotive applications

Part Number: TDA2SX Hi, I have a question on how the latency between a camera capture and display, can be measured. I came across an article on TI wiki, that defines what i need: http://processors.wiki.ti.com/index.php/Latency_Measurement_on_Capture_Encode_Decode_Display_Demo. I would like to know if the same solutions exist for TDA2x processors and If yes, can you please share. Thank you in advance. Mahima

Hi Mahima, Are you using vision sdk? If yes, it prints latency from the capture to display when you print stats. Regards, Brijesh

Just to add.. You would see the local link level latency and the source to link latency (which is equivalent to capture to particular link latency) in these statistics printed out from Vision SDK. Example is as below: [IPU1-0] 176.749191 s: Local Link Latency : Avg = 30 us, Min = 30 us, Max = 30 us, [IPU1-0] 176.749313 s: Source to Link Latency : Avg = 32971 us, Min = 32971 us, Max = 32971 us, Regards, Piyali

Thanks Brijesh. Yes, vision sdk is used; but, in development environment. Please let me explain my set-up, with more clarity: 1. I have to measure glass to glass latency on a bench setup using 4 cameras. The camera output goes to the ECU which has a TDA2x processor. The output images from the ECU, goes over LVDS to a monitor. 2. I only have access to M4-0 and A15 core logs thru a serial board. The rest are not accessible while testing the product. 3. I went thru the vision sdk user guide and it outlines a separate hardware setup to execute the example use cases. This, I do not have. Is it possible, barring the above limitations, to capture the glass to glass latency? I’m pretty new to this. Sorry, If I’ve not asked the right question. Thank you once again -Mahima

Thanks Piyali, for taking time out to answer. I've outlined, with more clarity, the limitations associated with capturing the latency in my setup. Kindly go thru, and let me know your suggestions. Thanks again. -Mahima

Mahima, If you are using vision sdk, just press 'p' when usecase is running, it will print all statistics including latency from the capture to display. This is the latency from capture link to the display link. There will be additional 2 to 3 frames latency in capture and display, which is not counted in this stats. The other way to measure the latency is by keeping a counting clock in front of the camera and take a picture of clock and display output in single shot. The latency is difference between time in clock and display. Regards, Brijesh

Thanks Brijesh. I think the system we use is a little different. we have a renderer in between the capture and display. I think vision sdk loses the frame once it goes inside the renderer. But the second method would give us a fair estimate though. So, thanks again for the help.

Hi Mahima, It is possible even if you have rendered in between. You just need to copy srctimestamp from source frame to target frame in your rendered link. Regards, Brijesh

Thanks Brijesh. I will try this on my system and let you know if I could capture the same.

Ticket Name: Linux/TDA2SX: Surround view use case in TDA2x

Part Number: TDA2SX Tool/software: Linux Hello, We are looking to set up a demo for Surround view use case on TDA2X board. We are looking for an out of the box solution which we can showcase. We have finalized following set up to order. Please let us know your feedback if this will work out of the box with vision SDK. Also, it will be great if we are guided with the exact use case to be run from vision SDK HLOS side. Board Link for purchase (TI or Spectrum) Project tda2x http://www.spectrumdigital.com/tda2x-vision-evaluation-module-kit/ ADAS base board + vision daughter card surround view kit http://www.spectrumdigital.com/multides-surround-view-kit/ SV kit thanks, Naren K.

Hi Naren, This appears the be the correct kit, however I did want to point out that this is the TDA2x part that doesn't have the ISP integrated in the SOC. If you were interested in that then there is a separate kit that comes with the TDA2PX parts. In this setup the ISP is on the ov10635 cameras that you are purchasing with the SRV kit. Regards Shashank

Ticket Name: Regarding USB KEYBOARD/MOUSE/WEBCAM NOT DETECTING on TI J6 Dra7xx board

Hi, Keyboard/MouIse/Webcam are not getting detected on DRA7XX board. I have enabled all the required drivers like USB keyboard driver and USB mouse driver on both kernel and root file system. I have also enabled USB host side drivers in kernel and USB OTG, When I type lsusb , the command returns nothing. When I give lspci, It does not show any USB controller. Request help on this, as I m stuck, Also request to share .config file of kernel, in which USB drivers are working. Thanks n Regards Shalini KP

Hi, Your question has been forwarded to an SW expert. Additionally provide info if you are using custom board or J6 EVM and what is the kernel version. Meanwhile, for more info you can check also below link: processors.wiki.ti.com/.../USB_General_Guide_Linux_v3.8 Best regards Lucy

Thank you for the reply. The issue is sorted after enabling all the USB host side drivers.

Hi What is the release version you are using ? In general each usb port USB1, USB2 is configured to particular mode (host, peripheral, drd/otg), the dr_mode field in usb device tree node need to set appropriately. Please arch/arm/boot/dts/dra7-evm.dts, if the dr_mode for USB1 port is set as "otg", then you need to insert the gadget module. You can insert any gadget like g_zero. (modprobe g_zero). For host only configuration you can force dr_mode property of USBx node to "host" in DT(device tree). Regards Ravi

Ticket Name: TDA2: Caffe SSD model output does not match TIDL output

Part Number: TDA2 Hi, I'm running our own ssd model(not caffe-jacinto based) using the eve host emulation.The input resolution of the image is 480x270. The SSD network contains four heads. I have set keep_top_k as 5 to output only five boxes. My detection layer is as follows: layer { name: "detection_out" type: "DetectionOutput" bottom: "mbox_loc" bottom: "mbox_conf_flatten" bottom: "mbox_priorbox" top: "detection_out" include { phase: TEST } detection_output_param { num_classes: 2 share_location: true background_label_id: 0 nms_param { nms_threshold: 0.45 top_k: 100 } code_type: CENTER_SIZE keep_top_k: 5 confidence_threshold: 0.1 } } This is the python script being used to read and print the SSD output from Bin file: import numpy as np bbox = np.fromfile("trace_dump_54_140x1.y", dtype=np.float32) reshapedbox = np.reshape(bbox,[5,7]) print reshapedbox When I run the script, the output is as follows: [[0. 1. 0.9999695 0.49767017 0.86217594 0.50364757 1.0235895 ] [1. 1. 0.9999695 0.4310913 0.8820838 0.4368931 1.0036817 ] [2. 1. 0.9999695 0.36486337 0.8434374 0.36978766 0.9579961 ] [3. 1. 0.9999695 0.2893248 0.8660821 0.29530218 0.98064077] [4. 1. 0.9999695 0.24571767 0.8706877 0.25169504 0.9869671 ]] The caffe output I got from the model is: [[[[0. 1. 0.9980788 0.8675699 0.4135536 0.921327 0.5036046 ] [0. 1. 0.9775522 0.7183735 0.4759325 0.754390 0.5347565]]]] Both in tidl and caffe the last four index corresponds to the coordinates xmin, ymin, xmax and ymax. As you could see the outputs are too different. Is it expected when models are not trained using caffe-jacinto? I verified the caffe output by plotting the bounding box over the image and it's correct. Thanks in advance, Navinprashath.R.R

We have validated the models trained using caffe-jacinto only. The detection layer is implemented as per the definition of caffe-jacinto layer Use caffe-jacinto and eaxmple models in caffe-jacito-models folder to used SSD feature of TIDL

Ticket Name: PROCESSOR-SDK-TDAX: "AR12XX: FAULT: BSS CPU fault!!" seen frequently, forcing user to reboot radar

Part Number: PROCESSOR-SDK-TDAX Other Parts Discussed in Thread: MMWCAS-DSP-EVM, MMWCAS-RF-EVM, AWR2243, AWR1243, TDA2 Hello, I have an MMWCAS-RF-EVM mounted on MMWCAS-DSP-EVM. I'm using PROCESSOR_SDK_RADAR_ 3.08 and often times I'm seeing this error on my terminal window. [IPU1-0] 1300.877569 s: radar_ar12xx/src/bspdrv_ar12xxPriv.c @ Line 541: [IPU1-0] 1300.877691 s: AR12XX: FAULT: BSS CPU fault!! [IPU1-0] 1300.877783 s: radar_ar12xx/src/bspdrv_ar12xxPriv.c @ Line 545: [IPU1-0] 1300.877844 s: AR12XX: FAULT: ESM fault!! [IPU1-0] 1301.117214 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large [IPU1-0] 1301.117336 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large [IPU1-0] 1301.117458 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large [IPU1-0] 1301.150216 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large [IPU1-0] 1301.150369 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large [IPU1-0] 1301.150460 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large I am forced to reboot the radar if I want to continue working with it. The hardware version reported by the serial terminal is ES3.0. I don't seem to have this problem happen this frequently in the ES1.0 hardware that I have. Please tell me how to isolate and fix this problem? Is there a firmware update I'm missing? Thanks Asher

Hi, ES1.0 and ES2.0 have different version of radar firmware. During radar init, it should try to check the revision of radar and download the corresponding firmware. You can check the log to see if the ES version of radar was detected correctly. Regards, Stanley

Hi Stanley, We have 2 Cascade RF boards where both boards have AWR2243 transceivers. However one board has hwMajor of 1 and the other has hwMajor 3. We believe these numbers represent ES1.0 and ES3.0. Since we have 2 AWR FW binary files for AWR1243 and AWR2243, Both cascade boards are downloaded with 2243 FW disregards whether one is an ES1.0 and the other is an ES3.0. That's how we modified the TDA2 bootup code to detect and behave. Please tell us if that assumption is correct. Now back to the BSS and ESM Faults above, we've seen this error showed up very often on the ES3.0 HW version vs the ES1.0 HW version even though both are running with same 2243 FW. So we are wondering if ES3.0 HW version has an updated FW for it to be used that fixes above errors seen? Thank you, --Khai

Hi Khai, I have forwarded this question to our Radar team to comment. In Radar SDK, only AWR1243 ES1.0 and 2.0 firmware have been tested. Regards, Stanley

Hi, Unfortunately, as mentioned by Stanley the Radar Processor SDK demo is not validated with AWR2243. There are some patches available in this forum provided by some forum members but they are not validated by TI We would have to open this question to the forum community for further support thank you Cesar

Hi Khai, If you refer mmWave DFP 2.2.3.1 example, where same code works for both AWR2243 ES1.0 and ES1.1 based on HW version. You need to implement similar logic in your application C:\ti\mmwave_dfp_02_02_03_01\ti\example\mmWaveLink_SingleChip_Example\mmw_example.c retVal = rlDeviceGetMssVersion(deviceMap, &mssFwVer); /* For AWR2243 ES1.0 MSS ROM FW version '2.2.0.3' and ES1.1: '2.2.1.7' */ if ((mssFwVer.fwBuild == 1) && (mssFwVer.fwDebug == 7)) { gMmwaveSensorEs1_1 = AWR2243_ES1_1; } else { gMmwaveSensorEs1_1 = AWR2243_ES1_0; } Similar way you can check first the AWR1243 MSS ROM version which will have some definite value for ES1.0/2.0/3.0 Silicon samples and based on that select the matching FW version to download. Regards, Jitendra

Hi Jiten, So is there a ES3.0 AWR2243 FW you can send us? In the HW detection, what parameters constitute to AWR2243 ES3.0 device? Thanks, --Khai

There is no AWR2243ES 3.0, only ES 1.0 and ES 1.1 There was an AWR1243 ES3.0 Thank you Cesar

Hi Jiten, Thanks for the clarification. So we have 2 FWs built into the AppImage in TDA2. One for 1243 and one for 2243 since we have both Cascade RF board in 1243 and 2243. My questions are: 1. What is the logic to detect AWR models (1243 or 2243)? 2. If it's 1243, would the same 1243 FW be compatible with all ESx version? 3. If it's 2243, would the same 2243 FW be compatible with all ES1.0 or 1.1 version? Thanks, --Khai

The FW release are usually not compatible. The DFP release notes mention the ES supported. Thank you Cesar

Ticket Name: Linux/TDA2: cannot print inf

Part Number: TDA2 Other Parts Discussed in Thread: SYSBIOS Tool/software: Linux i add my algorithm code in (vision_sdk\sample_app\src\rtos\alg_plugins\mycode.c ) make is pass , in frameCopyAlgoLocalDma.c i add Vps_printf(" wordWidth: DMA: height CH (TCC) = %d (%d)\n", pAlgHandle->frameCopyObj.maxWidth,pAlgHandle->frameCopyObj.maxHeight ) is done, but in mycode.c i use Vps_printf never print anything!

Please add a sleep after the print and see if it appears Regards Chetan.M

Hi Chetan.M but sleep is undifined, Regards shuai

Hi, Use Task_sleep() Regards, Anuj

Hi: Anuj I use Task_sleep(),but undefined symbol Task_sleep , i have add #include <ti/sysbios/timers/dmtimer/package/internal/Timer.xdc.h> #include <ti/sysbios/timers/dmtimer/Timer.h> Regards, shuai

Hi, I did not understand your question. if you are getting any compilation error then please take a refrence of a file where TAsk_sleep has been used. Regards, Anuj

Hi:Anuj Task_sleep() is undefined , What header should be included？ Regards, Shuai

#include <include/link_api/system.h> Regards, Anuj

Ticket Name: TDA2E: How to change display resolution dynamically at run time?

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 We use TDA2. We want to change display resolution dynamically at run time. How can I do ?

Hi, Do you mean to change DSS output resolution or input resolution? Typically output resolution cannot be changed, you will need to stop display and then only it can be chagned.. Input resolution can be changed, you just need to call driver ioctl SET_DSS_PARAMS to change input resolutions.. Rgds, Brijesh

Hi Brijesh: We want to change DSS output resolution at run time. My step: 1. DisplayLink_drvStop(pObj); 2. change dssPrms->tarHeight parameter and then call FVID2_control API. FVID2_control( pObj->displayHndl, IOCTL_VPS_DISP_SET_DSS_PARAMS, &pObj->dssPrms, NULL); 3. DisplayLink_drvStart(pObj); And display will not work normally. How can I solve it? Joe

Hi Joe, This does not change output resolution from DSS, ie LCD output resolution. This just restarts the pipeline, also please note that target resolution is not the output resolution from LCD. it is output resolution of this pipeline on the overlay manager.. Rgds, Brijesh

Ticket Name: TDA2E: Dears ，What is the Speed of CNN of TDA2 ， What is the XX Tops ？ What is the reference price of TDA2 ?

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Dears ，What is the Speed of CNN of TDA2 （operational capability）， What is the XX Tops ？ What is the reference price of TDA2 ?

Hi Andrew, for the CNN performance please check TIDeepLearningLibrary_DataSheet.pdf in "PROCESSOR_SDK_VISION_03_06_00_00\ti_components\algorithms\REL.TIDL.01.01.03.00\modules\ti_dl\docs" directory. For TDA2x pricing you need to contact authorized distributor: www.ti.com/.../distributors.html Regards, Yordan

Dear Yordan Could you offer the File ,Or link , many thanks ~

Hi Andrew, you can install VisionSDK for TDAx processors which includes TIDL library as well as example usecases fir deep learning: I also attach the file for your reference. TIDeepLearningLibrary_DataSheet.pdf Regards, Yordan

Ticket Name: TDA2: TIDL SSD MODEL

Part Number: TDA2 hi， Could you please share me with the TIDL ssd model formated as text t which can be imported into caffe framework and run normally ? As you can see the picture below,there is only the binary format of the ssd model and parameter, where is the text format of these two files ? Which files at the web link "https://github.com/tidsp/caffe-jacinto/tree/caffe-0.17/models/VGGNet/coco/SSD_300x300" I mean the two files "tidl_net_jdetNet_ssd.bin tidl_param_jdetNet_ssd.bin". Could we think of tidl_param_jdetNet_ssd.bin as caffemodel format file and the tidl_net_jdetNet_ssd.bin as prototxt file which shows the structure of the ssd net model？ Best,

tidl_net_jdetNet_ssd.bin tidl_param_jdetNet_ssd.bin are avialble binary format. Caffe-jacinto models can be found here github.com/.../JDetNet

Ticket Name: TDA2EXEVM: How to divide the input and ouput image into several blocks for reaching 30fps

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi, In surround view camera system, we tried to load our own LUT and divide the input and output images into blocks according to the reference manual, and use DMA to transmit data, but the frame rate is less than 30 frames. we have some questions to ask, Q1, does the output image in DDR also need to be transferred with DMA from L2 SRAM? Q2, how to divide the image, whether the 880*1080 image is divided into small slices of 10*18 or large slices to ensure the width of each block is long enough?

Hi, I have forwarded your question to an imaging expert. Regards, Yordan

Can you please confirm your device (TDA2 or TDA3?) and SW version (BIOS or Linux)? Please mention Vision SDK version number.

Ticket Name: TDA2: TDA2P functional safety

Part Number: TDA2 As we know TDA2P-ACD pass ISO26262 ASIL B functional safety, if the product comply with ISO26262 ASIL B, which application notes for hardware and software design ? Could you please provide relevant functional safety documents to us?

Joseph, You can start with www.ti.com/.../sprui16a.pdf Thanks and Regards, Piyali

Ticket Name: TDA2EXEVM: Understanding Processor SDK TDA2 Cascade Mode

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi, I am reading the code for Cascade use case running on TDA2. I am lost on the Chirp Configuration chains_common_cascade_ar12xx_config_mimo.c file. Is there a doc that explains the chirp config? 1. What's the concept of Master and Slave? 2. On line 249, rlChirpCfg_t gChains_cascadeRadarChirpCfgArgsMaster[CHAINS_RADAR_MAX_NUM_CHIRP_CFG], where CHAINS_RADAR_MAX_NUM_CHIRP_CFG = 64, but the initialization only fills 10. Same for the slave array of this structure. 3. I don't understand why txEnable is set as such in the code Thanks, --Khai

Also, There are two #define constant that I guess might mean the same. CHAINS_CASCADE_RADAR_RADAR_HEIGHT defines in chains_common_cascade_ar12xx_config_mimo.c - This is the number of chirps per frame CHAINS_RADAR_MAX_NUM_CHIRP_CFG defines in chains_radar.h - This is used in chains_common_cascade_ar12xx_config_mimo.c to create array of structure rlChirpCfg_t gChains_cascadeRadarChirpCfgArgsMaster[CHAINS_RADAR_MAX_NUM_CHIRP_CFG] If we desire to change number of chirps in the chirp frame, I suppose we need to change CHAINS_CASCADE_RADAR_RADAR_HEIGHT and not CHAINS_RADAR_MAX_NUM_CHIRP_CFG. But does CHAINS_RADAR_MAX_NUM_CHIRP_CFG also need to be changed if we change CHAINS_CASCADE_RADAR_RADAR_HEIGHT ? Thanks, --Khai

Hi I will check with RADAR SDK expert & let you know. Thanks Gaviraju

Hi Gaviraju, I have another question. In the ProcessorSDK_Radar_dataSheet.pdf chapter 4 where it mentioned "The height of the frame is Num of TDMA Tx antenna x Doppler Dimension". I understand the TX is chirping in a TDMA fashion from TX0 -> TX11 of all 4 sensors. What's not clear is that does each TX transmit chirp for the entire chirp frame (say if I have 128 chirps per frame) before the next TX chirps the next chirp frame OR all TXes only chirps 1 chirp round robinly and then the second and third chirps and so on... Thanks, --Khai

1. Master is the AWR device providing the clock to the 3 Slave devices so the 4 AWR devices can be cascaded. 2. We just allocated the structure to accommodate the maximal number of chirp configurations as place holder. In the example, we only use 10 chirp configurations. 3. txEnable is the bit mask of which Transmitter in AWR to enable. /** * @brief Tx enable selection bit mask \n b0 Enable TX0 \n 0 Tx0 Disable \n 1 Tx0 Enable \n b1 Enable TX1 \n 0 Tx1 Disable \n 1 Tx1 Enable \n b2 Enable TX2 \n 0 Tx2 Disable \n 1 Tx2 Enable \n Note: Maximum of only 2 TX can be turned in a chirp \n */ rlUInt16_t txEnable;

Ticket Name: RTOS/TDA2: Hello World Example Blinking LEDs No Communication

Part Number: TDA2 Tool/software: TI-RTOS Hello, We're having issues running the NDK Hello World example for IPU1 that's included in NSP_GMACSW_4_15_00_00 and uses NDK_2_24_02_31. The software is running on a Vayu EVM and we're using PHY2 on the board. When we run the original example and connect the evm to a linux laptop running Ubuntu 14 the example runs correctly and we can ping it. We can also run the companion helloWorld.c client software successfully. When we connect the evm to a switch we're seeing the LEDs on the PHY2 (P5 on the board) light up and blink indefinitely until power-off. Once the LEds start blinking in this pattern ping or client software will not work even when connected back to the Ubuntu laptop. We've tried other switches as well as other embedded linux devices in place of the Ubuntu laptop and only the ubuntu laptop seems to work. What do the blinking LEDs mean? Once the LEDs start blinking only a power cycle will make them stop. Is there a way to reset something from the TDA and avoid a total power cycle? Thanks, Juan

Hello Juan, Do you have 100Mbps sticker on RJ45 connector of your EVM? If yes, please check below note for this issue in VSDK TDA2xx user guide. The workaround is to configure remote end for 100Mbps.

Hello Prasad, There are no stickers on our EVM. Also when 1Gbps link is established it seems to work the same as 100Mbps link. Thank you

Hello, Can you please share use-case logs when you run the hello world application?

Hi Jmg65, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Ticket Name: TDA2SX: TIDL SSD model setup

Part Number: TDA2SX Hi everyone, I have SSD object detection model which I want to run on SoC. During conversion eve_test_dl_algo.exe is run and I get correct results in stats_out_tool.bin file. I am running full net with eve_test_dl_algo.exe application. However, by instructions, I should run it partially on EVE and partially on DSP core. Since I don't have DSP test app, a made usecase similar to TIDL OD one where I am running 1 EVE core and 1 DSP core with TIDL algorithm link with this model. But, I am getting empty list of bounding boxes as a result. Also, I tried this model with TIDL usecase and results are the same as for the previous usecase. Does anyone know why I am getting correct results only during the conversion but only when it is not run by isntructions and on SoC not at all? Regards, Sasa

Did you get the model working with the original TIDL OD use case without any modification to the usecase? Most cases the difference result are observed if the input used for import and use cases are not the same. Check the input tensor passed to use case and make sure, it matches with the first tensor of import (trace_0*.y)

Input to import and usecases are same and identical to trace_dump_0*.y . I didn't check the model with original TIDL OD usecase yet because originali it takes video input instead of singe image so modifications are necessarry. Can I somehow get output from all layers on SoC like during the import process having trace_dump_* file for all layers?

No, generation trace on the SoC is not supported by the library.

Ticket Name: TDA2: TI Deep Learning Library on C66x DSP and EVE: Support for original TensorFlow models

Part Number: TDA2 Hello, Section 3.6.5 of the TI-DL Library User Guide from the most recent Vision SDK states that "TIDL supports slim based TensorFlow models". I am not aware of the exact difference between the TF and TF-Slim. But several Internet posts (including github.com/.../16182 suggest that the TF-Slim is now deprecated and not to be used for new development. There are two questions: 1. Do algorithm developers need to use TF-Slim API calls while creating custom models? 2. Can algorithm developers use the main/original TF API while creating custom models? Are these models supported by the model import tool? Thank you.

Slim is a high level API for tensorflow operators. As per tensorflow team, Slim will be replaced with keras hih level APIs in tensorflow 2.0 not in 1.x We have have validaed the only slim based mdoels. Even with Keras APIs based models or original TF layers based models most layes(Convolution , Inner producr, max Pool, eltwise ) would work in currentl import tool. there may some chnage needed the in impor tool for other oprators. Since source code for import ool is part of release package user can update tool for these mdoels. We are not planning to update import toll for this

Ticket Name: Linux/TDA2: a15 Multithreading

Part Number: TDA2 Tool/software: Linux i run my algorithm on A15 ,double thread time is half of Single thread. thread num is 4 or 8 time is same with double thread. Multithreading is use 2 A15 is run ?

Hi, If you're using a TDA2x then there's a dual-core A15, which enables running a thread on each core, so you should almost see a linear decrease in the time. However, when the number of threads increases, they are scheduled between the two cores, and there may not necessarily be a linear decrease in time. Regards Shravan

Hi Shravan what about TDA2Ex? a dual-core A15 also? BESTWISHES SHUAI

Hi Shuai, TDA2Ex is single core A15. Regards Shravan

Ticket Name: TDA4VM-Q1: TDA4VM : Display YUV422 BT601 Support

Part Number: TDA4VM-Q1 Other Parts Discussed in Thread: TDA2, TDA4VM Hi, Expert, As our TDA2 VOUT interface can support BT601. Can you pls let me know if we can use the same way on TDA4VM to support BT601 ？ Thanks. TDA2 Guide is here： https://www.ti.com/lit/an/spracg3/spracg3.pdf Regards, Fredy Zhang

Hi Fredy, Yes, we can use same mechanism, but there is another better way, using two video ports outputs, we can get BT601 output and this does not even require usage of DSS M2M. Regards, Brijesh

Brijesh, Thanks, That's great . Do have have reference for two video port to support BT601 ? Thanks. Regards, Fredy Zhang

Fredy, Although driver supports this interface, there is not reference example in SDK. Customers have brought up BT601 on their platform using this method. Regards, Brijesh

Ticket Name: TDA2x (ADAS) Ethernet problems

Other Parts Discussed in Thread: TDA2 Dear support, I am trying to get Ethernet working on a TDA2 SoC with a DP83848Q PHY. I have reuesed the Ethernet driver from the VISION_SDK_02_08_00_00; I think this driver should run on the Vayu board. On my board I got receive and transmit working with this driver, but I have noticed that there are packets lost on both directions (receice and transmit). On my board only D0 and D1 is connected for transmit and receive to the DP83848Q. The connection is direct with a 22Ohms series resistor and not with a multiplexer in between as on the Vayu board. For the TDA2 SoC I have reused the pad configuration from the SDK. I have verified the 50MHz clock for the DP83848Q and TDA2 (RMII0_MHZ_50_CLK) is fine, the reset and power supply of DP83848Q is stable. Do you have any idea what I could try or what could cause the packet loss on my setup? For testing I would like to try to set the PHY to loopback mode; How do we have to setup the GMACSW_Config structure to enable the loopback mode in PHY? Best regards, Erwin

Hi Erwin, First, do you have all connections in place described in TRM Figure 24-178. RMII Interface Typical Application? Also, did you setup the CPSW for RMII mode? And did you check the PHY is discoverable via MDIO? Regards, Stan

Hi Stan, Yes, all the connections are there; RMII mode is setup and the PHY is discoverable. When connecting with a PC via crossed over cable the link will be established. Data transfer works in both direction, but packets are lost in both direction. Best regards, Erwin

Ok, can you post your strap pins configuration defined in PHY datasheet, 3.8 Strap Options? You said you use a crossed-over cable. Did you try with straight cable? Both should be ok, but just in case. '22-ohm termination' Where did this requirement came from? I could find 50-ohm recommendation in the datasheet. But first you may want to capture the waveforms and compare them vs. . Section 7 RMII Interface Timing Requirements. Regards, Stan

Ticket Name: Compiler/DRA77P: Failed to boot remote proc IPU1.

Part Number: DRA77P Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi, In order to run RVC use case on IPU1 instead of IPU2 using TI SDK 03.02 And following to https://www.ti.com/lit/an/spracb6/spracb6.pdf The remote proc fail to boot with : [ 5.982483] remoteproc0: Booting fw image dra7-ipu1-fw.xem4, size 6706040 [ 6.009733] remoteproc0: bad phdr da 0x99000000 mem 0x4c8 [ 6.009737] remoteproc0: Failed to load program segments: -22 [ 6.012032] remoteproc0: failed to unmap 16777216/0 [ 6.012052] remoteproc0: failed to unmap 16777216/0 [ 6.012071] remoteproc0: failed to unmap 16777216/0 [ 6.034583] remoteproc0: rproc_boot() failed -22 dts changes : &ipu1_cma_pool { reg = <0x0 0x9e000000 0x0 0x02000000>; }; &mbox_ipu1_ipc3x { ti,no-reset-on-init; ti,no-idle-on-init; }; &mmu_ipu1 { ti,late-attach; ti,no-reset-on-init; ti,no-idle-on-init; }; &ipu1 { ti,late-attach; ti,no-reset-on-init; ti,no-idle-on-init; };

and when I flash robust dts file : Kernel hangs at "starting kernel..." uboot logs : Core 2 ELF Image is valid Configuring IOMMU Starting the remote core loading remote core IPU1 successful Core 4 ELF Image is valid Configuring IOMMU Starting the remote core loading remote core DSP1 successful . . . Booting from eMMC ... ## Booting Android Image at 0x82000000 ... Kernel load addr 0x80008000 size 8125 KiB Kernel command line: buildvariant=userdebug RAM disk load addr 0x83000000 size 2113 KiB ## Flattened Device Tree blob at 88000000 Booting using the fdt blob at 0x88000000 Loading Kernel Image ... OK Loading Ramdisk to 8fdef000, end 8ffff0b9 ... OK Loading Device Tree to 8fdd2000, end 8fdee748 ... OK Using machid 0xfe6 from environment Starting kernel ..

Hi Chokri, Just to make sure, you are using our Robust RVC Phase 6 release? It looks to me like the first issue you're seeing is that dra7-ipu1-fw.xem4 is still trying to load into the ipu2 memory region. Can you reverify all your changes through section 5 of the pdf you linked? Also, it looks like the instructions are written for TDA2 devices, not TDA2P, so please make sure you're editing the tda2px files. If possible, can you attach these files and we can double check them? PROCESSOR_SDK_VISION_03_xx/vision_sdk/build/Rules.make PROCESSOR_SDK_VISION_03_xx/vision_sdk/apps/configs/tda2px_evm_robust_rvc/cfg.mk PROCESSOR_SDK_VISION_03_xx/vision_sdk/apps/src/rtos/usecases/vip_single_rvc_ cam_view_crc/cfg.mk dra76-evm-robust-rvc.dts or dra76-evm-tfp41-0-robust-rvc.dts u-boot/include/configs/dra7xx_evm.h u-boot/common/spl/spl.c On the second issue, can I ask you to clarify what is happening? It looked like you were getting past boot in the first scenario, but after you flash the correct dtb it no longer boots? Thanks, David

Hi David, Thanks a lot, Isuue fixed by editing PROCESSOR_SDK_VISION_03_xx/vision_sdk/apps/src/rtos/usecases/vip_single_rvc_ cam_view_crc/cfg.mk like : NEED_PROC_IPU2=no NEED_PROC_IPU1_0=yes NEED_PROC_DSP1=yes Regards, Chokri

Ticket Name: TDA2P-ACD: CDDS Account for TI DMA Utility download

Part Number: TDA2P-ACD I am looking at the document titled "TI Deep learning Library on TDAx - User Guide" from TI. Within this, one of the steps to get started is to install the DMA utility Library provided by the following link: https://cdds.ext.ti.com/ematrix/common/emxNavigator.jsp?objectId=28670.42872.62652.37497 The download package through the above link requires a TI CDDS account. How can I get access to this account? Please Help.

Hi Abhishek, you need to contact your local TI representative to get access to CDDS. Regards, Yordan

Ticket Name: Linux/TDA2E: Can the kernel software support the power management of the TF card?

Part Number: TDA2E Tool/software: Linux HI， How does the kernel software do the power management of the TF card: After the TF card is removed, we need to turn off the TF card power. When the TF card is reinserted, the kernel will not recognize the TF card, and then the TF card will be powered. The kernel still cannot recognize the TF card.

Hi, Could you provide more details, Which SDK version you are using, what issue you are facing? Regards, Vishal

Hi Vishal, We are using the 2.02 SDK. The problem is ：After turning off the TF card power supply, how to let the kernel recognize the inserted TF card? The kernel does not recognize the TF card. When the SOC performs this process: Turn off the TF power supply → Insert the TF card → Turn on the TF card power supply → The kernel cannot recognize the TF card

Hi, Is the TF card connected via SD card slot using MMC interface? You can either use a dedicated GPIO for card detect or the SDCD signal of MMC. If dedicated gpio is used, then "cd-gpios" property in dts is used to specify the GPIO used for this purpose. Regards, Vishal

Hi, Are there any more questions on this? Regards, Vishal

Hi Vishal， We use the MMC1 interface to connect the TF card through the SD card slot. The SDCD signal of MMC1 has also been used. The software uses the original SDK provided. But still has not solved the problem Regards,

Could you share the full Kernel logs from boot time? removal of card and re-insertion of card?

Hi vishal , The attached file may be the file you want. dmesg_tf.rar

Hi, Correction to my previous statement. We use a separate GPIO pin for SD card detect. The omap_hsmmc driver does not support SDCD pin. Regards, Vishal

Hi, Do you have any other question on this? Regards, Vishal

Ticket Name: TDA2SX: Angle Finding radar VSDK use case?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2, AWR1243 How to customize use case with our angle finding technique for cascade TDA2 EVM? Is modifying the beam forming use case the right place to start? Is there a better choice use case for angle finding or maybe we should look at creating a new custom use case?

Hi Zach, Are you using MIMO or beamforming for getting the angle of arrival? You can create your own usecase using the TI out of box usecases as a reference. Thanks and Regards, Piyali

Hi Piyali, We are using MIMO. Thanks and Regards, -Zach

Zach We have a MIMO usecase which is part of the SDK. You can use this as a reference. Thanks and Regards Piyali

We have cascade needed as well. We are expanding the 4 AWR1243 cascade to 8 AWR1243. How do I go about identify and quantify the changes need to get to 8 AWR1243 on TDA2s with one AWR1243 master? Which it the "MIMO" use case?

***correction*** 8 AWR1243, 2 TDAs, one master AWR1243

cascade_radar_object_detect is the MIMO usecase. If each AWR1243 would have its own TDA software, you would not need to change the number of AWR1243 for each TDA. Chirp configs would only need to be in sync.

Where is the chirp config that gets used by FxObAoA? Looks like a it read from a file handle. I don't see where this file name string and directory get set. So we can review the chirp setting in the use case.

Where can I see and modify the chirp ramp scenario please?

Hi Zach, There is a default chirp config built into the code in PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\apps\src\rtos\radar\src\common\chains_common_cascade_ar12xx_config_mimo.c The one you see with the file read is searching for a folder with the below name: #define RADAR_CONFIG_PARAM_DIR_NAME "radar_test_vector/" Kindly go through the section: 3.9.1.6.3 File-based Use Case Configuration Support in the file : PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\docs\Radar\ProcessorSDKRadar_UserGuide.pdf You can change the chirp configurations from the files in radar_test_vector under PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\apps\src\rtos\radar\src\usecases\cascade_radar_object_detect and put this folder in an SD card to be plugged into the board. Thanks and Regards, Piyali

For "Control Calibration" file in 3.9.1.6.1 4 AWR1243 Capture + Radar Object Detect (DSP) (MIMO) + Null from PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\docs\Radar\ProcessorSDKRadar_UserGuide.pdf : "For Control Calibration, the Calibration is sent out over Ethernet to the Matlab tool. This is saved as a CC.mat file. Once this file is generated you need to run vision_sdk\apps\src\rtos\radar\src\usecases\cascade_radar_object_detect\create_calib_coefs.m to finally create the SD card based coefficients and then copy this over to the SD card for the next run." Where do I find more information about generating this CC.mat file and it's format?

Zach You can refer to the end of the section 4.2 Data Flow of the vision_sdk\docs\Radar\ProcessorSDKRadar_DataSheet.pdf. You can look at the MATLAB scripts for more details for the format. Thanks and Regards, Piyali

Ticket Name: TDA2: TIDL convolution layer input ,output, bias are all in ibufla, can I put the output on ibufha

Part Number: TDA2 Hi: Recently, I found in TIDL convolution layer, the input, output and bias value are all on ibufla, for sparse convolution, the weights value first transfered to DMEM of EVE, then from DMEM to ibufha, for dense convolution, the weights value directly transferd to ibufha. Now, I put the output on ibufha, but I can't detect object. Can I put the output on ibufha, and can I directly transfer the weights value of sparse convolution to ibufha. thanks.

No, Sparse convolutions nned to update the weights during kernel executions. We recommend not to update sparse convolution flow.

Ticket Name: Linux/TDA2PXEVM: Decode link output has offset

Part Number: TDA2PXEVM Tool/software: Linux Hi all, When I use decode link, there is offset problem, please see my screenshot below which is show in RTSP. My usecase is NullSource (A15) -> Decode -> Dup Dup -> Encode ->Rtsp (A15) Dup -> Null (A15) When I dump frame use Null link, it shows: pitch: 2048, height: 964, width: 1280, startx: 32, starty: 24. Then I saw decode link had added UTILS_ENCDEC_PADX and UTILS_ENCDEC_PADY. But it is useless to set them as 0. So do you have any idea about it? Thanks a lot!

Which release you are using? I see UTILS_ENCDEC_PADX is set correctly to 32 and same for UTILS_ENCDEC_PADY. Rgds, Brijesh

V3.4 And could you please tell me why Decode link add this pad? Thanks!

Hi TI implementation of H264 decoder on IVA-HD HW need some padding around the output buffer. This can not be avoided. You can either use 1. VPE to crop or 2. SW way of manipulating the buffer start address to avoid this padding If you are connecting Display after Decode, then VSDK display link support this kind of cropping SW way of Manipulating the buffer start address = buf_addr + pitch * start_Y + start_X retards, Shiju

And also codec implementation requires this padding area internally. Rgds, brijesh

Ticket Name: TDA2P-ABZ: TDIL use case or example for TDA2P

Part Number: TDA2P-ABZ Other Parts Discussed in Thread: TDA2 Hello everybody , please VSDK does not support TIDL use case ( see my other post ) . coudl you help me on how to insert example and have something similar to TDA2 ? any instruction / example ? thank you regards Carlo

Hi, You can run tidl bios example on tda2px bios cfg. You just need to modify your usecase and use 2 EVE instead of 4. Regards, Anuj

Hi Anuj, Can you please elaborate more on your answer? Since there are several files to modify (configuration files on what processors to include, use-case related files: chains_semSeg.c, chains_semSeg_priv.c). What modification should I do in order to have only 2 EVE instead of 4? Thank you Aleksander

HI, An internal thread is going on with this. From the logs shared i hope the porting tidl usecase on tda2px is done and everything is working fine. Please close this thread and raise a new one for your camera issue with tidl. Regards, Anuj

Ticket Name: CCS/TDA2: how to get EVE cmd file

Part Number: TDA2 Tool/software: Code Composer Studio i make a new EVE project i copy this cmd file to my project ,but it no do (SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\kernels\common\linker.cmd ) i am Success in c66 project i copy CMD from ti_SDK_VISION_03_02_00_00\ti_components\algorithms\vlib_c66x_3_3_0_3\packages\ti\vlib\src\common\c66 so what can i do ?

Hi Shuai, Can you explain what are you trying to do? What do you mean by success here? Are you seeing some build failures? Regards, Anshu

Hi Anshu i have to run a algorithm ON eve. I have run it on C66 success now. i have not run EVE a go so i try to do a simple project 3*3 medfilter i think if this is success i can do my work! i found in SDK sample SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\kernels\imgsiglib\Median_filter_col\src_kernelC eve code is in a .k file , if in my project have 5 kernels i have to make 5 .k file? or just 1 .k put them together?

Hi Anshu cannot find reset_handler BESTWISHES!

Shuai, You need to add boot_arp32.asm file to your build. This file is also located at SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\kernels\common\boot_arp32.asm Regards, Anshu

Ticket Name: CCS/TDA2: Can C66 use multithreading to optimize performance

Part Number: TDA2 Tool/software: Code Composer Studio Can C66 use multithreading to optimize performance and how to do ??

Hi Shuai, The C66x core is essentially a single CPU. You can use TI RTOS for multithreading tasks on the single core but essentially they will be time multiplexed. If your idea is to run threads in parallel that would not be possible on the C66x. Thanks and Regards, Piyali

Ticket Name: TDA2EVM5777: TDA2 EVM XO_OSC1

Part Number: TDA2EVM5777 Hello I read from TDA2x_SR2.0 TRM that xi_osc1 frequency should be (19.2/32)MHz, but why osc in 516582H_VAYU_EVM_13NOV2015_H is 22.5792MHz? thank you

Hi, user3829173 (3829173), (19.2 ÷ 32) MHz means range from 19.2 to 32 MHz. So 22.5792 is within the range. Regards, Mariya

Ticket Name: Linux/TDA2: TDA2xx The running effect of usecase is wrong

Part Number: TDA2 Tool/software: Linux Hi， My environment is PROCESSOR_SDK_VISION_03_02_00_00 , My configuration is tda2xx_evm_linux_all, and i run through NFS mode。 The first usecase-1 I created was： NullSource (A15) -> Decode -> Alg_FrameCopy (A15) -> VPE -> Display and it is running normally： But I modified usecase-2 based on usecase-1，the usecase-2 is: NullSource (A15) -> Decode -> Alg_FrameCopy (DSP1) -> VPE -> Display its running results are as follows: I just changed Alg_FrameCopy running on DSP1 core form A15 core. I want to running Alg_FrameCopy correct on DSP core.

Hi , Can you dump the video buffer after decoder and verify . Regards Chetan.M

Hi Chetan.M, How can i dump the video buffer after decoder？ Which interface should I operate on? Regards Xie Baojian

HI Chetan.M, Also want to ask about Which alg_plugins directory is running when i run the usecase-2？ I have add some printf info in the directory \vision_sdk\apps\src\hlos\adas\src\alg_plugins\framecopy and \vision_sdk\apps\src\rtos\alg_plugins\framecopy， But no printouts come out. Regards Xie Baojian

where is the alg created , i mean which core, If its hlos (a15) then apps\src\hlos\adas\src\alg_plugins\framecopy if in other than a15 then apps\src\rtos\alg_plugins\framecopy To dump the frame you need to use ccs and halt in process function of the alg and dump the buffer regards Chetan.M

Hi, Are you able to resolve the issue? Regards, Anuj

Ticket Name: Linux/TDA2: assembly optimization

Part Number: TDA2 Other Parts Discussed in Thread: MATHLIB Tool/software: Linux is there any examples of assembly optimization in SDK? vlib_c66x_3_3_0_3 and vxlib_c66x_1_1_1_0 there examples are use Inline instruction！ so i am thy to assembly optimization some fuction,but no sample to follow!

Hi Shuai, Since you are looking at vxlib I assume you are interested in DSP optimization. If so please check this post by Jesse for a list of DSP optimization reference guides and trainings: e2e.ti.com/.../2371691 Regards, Yordan

Hi: Yordan this is a sample function , document have give out its Linear Assembly code. c code c code i just call it , Assembly code how to call , i put Assembly code in .asm file ? int dot(short a[], short b[]) { int sum0 = 0, sum1 = 0, sum, I; for (I = 0; I < 100/2; I+= 2) { sum0 += a[i] * b[i]; sum1 += a[i + 1] * b[i + 1]; } return sum0 + sum1; } Linear Assembly for Dot Product _dot: .cproc a, b .reg sum0, sum1, I .reg val1, val2, prod1, prod2 MVK 50,i ; I = 100/2 ZERO sum0 ; multiply result = 0 ZERO sum1 ; multiply result = 0 loop: .trip 50 LDW *a++,val1 ; load a[0-1] bank0 LDW *b++,val2 ; load b[0-1] bank2 MPY val1,val2,prod1 ; a[0] * b[0] MPYH val1,val2,prod2 ; a[1] * b[1] ADD prod1,sum0,sum0 ; sum0 += a[0] * b[0] ADD prod2,sum1,sum1 ; sum1 += a[1] * b[1] [I] ADD -1,i,i ; I-- [I] B loop ; if (!I) goto loop ADD sum0,sum1,A4 ; compute final result .return A4 .endproc BESTWISHES SHUAI

Hi Shuai, you can use separate .asm file for your assembly code or include it in .c file with: asm(" Some Assembly \n\t" " Some Assembly \n\t" ... " Some Assembly \n\t" ); but this option is better suited for small fragments of assembly code. You can check for example "<VSDK>/ti_components/algorithms/mathlib_c66x_3_1_0_0/" - there are quite a lot functions implemented in .asm files. Regards, Yordan

Ticket Name: Linux/TDA2: Cannot EDMA transfer between OSA_memAllocSR() and aligned_alloc() allocated buffers

Part Number: TDA2 Tool/software: Linux Hello, I'm using Processor SDK 3.03, building for custom board with TDA2 chip. So far I have successfully transferred data between two buffers allocated using OSA_memAllocSR() in a PSDK usecase. I did this by calling OSA_memVirt2Phys() to get physical addresses of those buffers and forwarded that information to an EDMA utility driver that I've written. Now, I need to transfer data between a buffer allocated with OSA_memAllocSR() and a buffer allocated with aligned_alloc() from POSIX. However, I don't know how to get physical address of the one allocated with aligned_alloc(). I would like to know how it could be done so that the EDMA transfer can work. Thank you in advance. Regards, Nick

Hi, What you're trying to achieve isn't possible through a simple aligned_alloc() call. The aligned_alloc call provides a scattered list, which isn't continous. You need a special allocator such as a CMA which provides a continuous memory region. Please refer this link for more information. lwn.net/.../ The reason OSA_memVirt2Phys() works is because the allocation happens from M4 where the physical to virtual address mapping is 1-1, but this isn't the case on Linux. If you intend to use EDMA from Linux, then you will need to use CMA for allocation. You also need a way to inteface your application with the EDMA driver (in vision-SDK EDMA is on M4). If you intend to use EDMA from M4, I would recommend allocating from SR and passing the buffer to M4. Regards Shravan

Hi Shravan, Can you confirm that the CMA is integrated into the DMA subsystem of ARM in kernel 4.4.84 which is used in PSDK 3.03? If yes, then I suppose it is only a matter of allocating memory with dma_alloc_coherent(). Regards, Nick

Hi Nick, Sorry about the delayed response, I was on leave. Yes you can use dma_alloc_coherent, and if the device is NULL / the device doesn't have a dedicated dma pool, it will allocate from CMA. You can then use this to program the EDMA (the call as such returns a virtual address, but one of the arguments passed contains the physical address). Regards Shravan

Hi Shravan, I managed to use dma_alloc_coherent() and perform an EDMA transfer between that and the one allocated with OSA_memAllocSR() so that worked out great. The next problem that I'm having is that the buffer allocated with dma_alloc_coherent() cannot be written to a file on SSD opened with O_DIRECT flag. I have posted on a few Linux related forums since I don't think it is related to TI specifically any more but I have got no answers. Do you have any experience with this? I will post this as a new question if you have an answer. Looking forward to hearing from you. Regards, Nick

Hi Nick, I don't think this is permitted since it security flaw to allow I/O on kernel pages mapped to user-space. There will have to be a copy into kernel space which can then be written through O_DIRECT. Regards Shravan

Hi Shravan, We have tried to write to SSD directly from the dma_alloc_coherent() buffers from a kernel module but we have found that writing to disk from kernel space is not encouraged and is only available via certain hacks so we gave up on that. What I would like to know now is something else but I will make another thread and link it here if you would like to look at it, basically we would like to write to SSD directly from OSA_memAllocSR buffers (which is the original problem that drove us into this one) but more details on the thread. It can be found here: https://e2e.ti.com/support/arm/automotive_processors/f/1021/t/729926 Regards, Nick

Ticket Name: TDA2SG: TDA2 LCD2 BT656 signal

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Hi Sir : TDA2 output BT.656 signal, when converted to BT.601 signal. Hsync will output all the time. If Vsync is low and Hsync is low, how do I set it?

Hi, Do you mean, you dont want hsync to be toggling when vsync is low? If this is the case, you could treat DE signal as inverted hsync. DE will toggle only during active video portion. Regards, Brijesh

Hi Brijesh : The hardware only has Hsync and Vsync and PCLK and ATA [7:0] pins, no DE output. The image had the output I wanted.

Hi Pierre Hsieh, hsync will toggle during vsync, this cannot be changed. In this case, you need to use DE line. Regards, Brijesh

Hi Brijesh : I cannot modify the BT656 configuration of TDA2 to output the desired signal?

Hi Pierre Hsieh, Hsync is supposed to toggle even during vsync inactive period.. This behavior cannot be changed. Regards, Brijesh

Hi Brijesh : BT.656 does not have a DE Line specification. How can I convert to BT.601 with DE Line?

Hi Pierre Hsieh, BT656 does not even output hsync and vsync, so we cannot use hsync/vsync signals for BT656. We have to use discrete sync output mode in order to get sync signals. and when we enable discrete sync signals, we will also get DE signal. Regards, Brijesh

Hi Brijesh : This TDA2 hardware configuration, Display Subsystem DPI2 output BT.656, only output Data and PCLK signal lines. Analyze Bt.656, there will still be H Active in V Blanking. TDA2 can output on BT.656, the V Blanking signal is only H Blanking?

Hi Pierre Hsieh, When you say BT656, it is embedded sync output format, and in this format, DSS does not output sync signals, so there will not be any hsync or vsync signals in bt656 output. So can you check if you are configuring DSS for discrete sync output? Regards, Brijesh

Hi Brijesh : BT.605 does not have Hsync and Vsync, so I converted it to BT601 using FPGA. I used FPGA to convert TDA2 output BT.656 signal into BT.601 signal. I found that VBlanking has a HActive signal for BT.601 signal.

Hi Pierre Hsieh, ok, in this case, you need to change FPGA. FPGA should out hsync correctly. This is not DSS question. Regards, Brijesh

Ticket Name: Does TDA2 vout support bt656 8-bit mode?

Other Parts Discussed in Thread: TDA2 Hi all, My code base is VisionSDK_v2.08 and use TDA2 custom board. My vout data pin connect as "TDA2_Vout_D[0~7] -> DS90UB913Q_DIN[2~9]" and data format is "BT656, YUV422, 800x480". In VisionSDK_v2.08, I modify some settings in vision_sdk\examples\tda2xx\src\usecases\common\chains_common.c "ChainsCommon_SetDctrlConfig() " as below "RED". But nothing display on panel. ------------------------------------------------------------------------------------------------------------------------------ if(displayType == CHAINS_DISPLAY_TYPE_LCD_7_INCH) { pPrm->deviceId = DISPLAYCTRL_LINK_USE_LCD; pVInfo->vencId = SYSTEM_DCTRL_DSS_VENC_LCD1; pVInfo->outputPort = SYSTEM_DCTRL_DSS_DPI1_OUTPUT; pVInfo->vencOutputInfo.vsPolarity = SYSTEM_DCTRL_POLARITY_ACT_LOW; pVInfo->vencOutputInfo.hsPolarity = SYSTEM_DCTRL_POLARITY_ACT_LOW; /* Below are of dont care for EVM LCD */ pVInfo->vencOutputInfo.fidPolarity = SYSTEM_DCTRL_POLARITY_ACT_LOW; pVInfo->vencOutputInfo.actVidPolarity = SYSTEM_DCTRL_POLARITY_ACT_LOW; pVInfo->mInfo.standard = SYSTEM_STD_CUSTOM; pVInfo->mInfo.width = displayWidth; pVInfo->mInfo.height = displayHeight; pVInfo->mInfo.scanFormat = SYSTEM_SF_PROGRESSIVE; pVInfo->mInfo.pixelClock = 29232u; pVInfo->mInfo.fps = 60U; pVInfo->mInfo.hFrontPorch = 40u; pVInfo->mInfo.hBackPorch = 40u; pVInfo->mInfo.hSyncLen = 48u; pVInfo->mInfo.vFrontPorch = 13u; pVInfo->mInfo.vBackPorch = 29u; pVInfo->mInfo.vSyncLen = 3u; pVInfo->vencDivisorInfo.divisorLCD = 1; if(Bsp_platformIsTda3xxFamilyBuild()) { pVInfo->vencDivisorInfo.divisorPCD = 1; } else { pVInfo->vencDivisorInfo.divisorPCD = 4; } pVInfo->vencOutputInfo.dataFormat = SYSTEM_DF_YUV422I_YUYV;// SYSTEM_DF_RGB24_888; pVInfo->vencOutputInfo.dvoFormat = SYSTEM_DCTRL_DVOFMT_BT656_EMBSYNC; // SYSTEM_DCTRL_DVOFMT_GENERIC_DISCSYNC; pVInfo->vencOutputInfo.videoIfWidth = SYSTEM_VIFW_8BIT;//SYSTEM_VIFW_24BIT; pVInfo->vencOutputInfo.pixelClkPolarity = SYSTEM_DCTRL_POLARITY_ACT_HIGH; pVInfo->vencOutputInfo.aFmt = SYSTEM_DCTRL_A_OUTPUT_MAX; /* Configure overlay params */ ovlyPrms->vencId = SYSTEM_DCTRL_DSS_VENC_LCD1; } ------------------------------------------------------------------------------------------------------------------------------ I find the description in TDA2 TRM(as below), could TDA2 support 8-bit mode? Or am I missing any settings? Please give me some hints. – Displays supported: • Active matrix color: 12-, 16-, 18-, and 24-bit panel interface support (replicated or dithered encoded pixel values) Thanks in advance.

Hi Sherry, I think also pins [9:2] from TDA2 side should be used (instead of [7:0]). See the TRM note below. Regards, Stan

Hi Stan, Thank you for your reply that H/W pin design. In the SW for display setting, I set it as below: pVInfo->vencOutputInfo.dataFormat = SYSTEM_DF_YUV422I_YUYV; pVInfo->vencOutputInfo.dvoFormat = SYSTEM_DCTRL_DVOFMT_BT656_EMBSYNC; pVInfo->vencOutputInfo.videoIfWidth = SYSTEM_VIFW_8BIT; and get error message as below dispdrv/src/vpsdrv_dctrl.c @ Line 713: Core control: Set venc output failed!! Assertion @ Line: 719 in links_ipu/display_ctrl/displayCtrlLink_drv.c: retVal == SYSTEM_LINK_STATUS_SOK : failed !!! I change videoIfWidth = SYSTEM_VIFW_10BIT and get the same error message. But set videoIfWidth = SYSTEM_VIFW_12BIT is OK! How do I set display venc's parameter for BT656? Kuve

Hi Kuve, I don't have much knowledge in DSS software, therefore I cannot tell the exact settings. Regarding "But set videoIfWidth = SYSTEM_VIFW_12BIT is OK!" : there are no sub-12-bit settings available , because it reflects register bits DISPC_CONTROL1[9:8] TFTDATALINES, which in turn configures the data with in RGB mode. That is, it is irrelevant to BT656 and therefore you can leave it at default (12-bit). Because most of the other settings above are related to DSS registers, you can refer to Table 11-150. DISPC Configure BT.656 or BT.1120 Mode, and other tables in the same section of TRM. Regards, Stan

Ticket Name: TDA2: Problem in TDA2: Example to train CNN network on tensorflow and run using TIDL

Part Number: TDA2 I follow the every step in https://e2e.ti.com/support/processors/f/791/t/689876 But, I failed in the last step when I performed the command below python -m tensorflow.python.tools.optimize_for_inference --input=keras_frozen.pb --output=keras_frozen_optimized.pb --input_names=conv2d_1_input --output_name=conv2d_5/BiasAdd and get the error message below. KeyError: "The following input nodes were not found: {'conv2d_1_input'}\n" It seems that the setting of conv2d_1_input is wrong. How could I set it ?

Hi, can you check also this post: e2e.ti.com/.../733834 For TensorFlow 1.10 the argument needs to be changed. Regards, Yordan

Ticket Name: RTOS/TDA2EVM5777: Uart data missing

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hi, I register Uart ISR in IPU1, to receive data from external device. it works well when data size not more than FIFO size, but will fail when data size more than FIFO size. the FIFO trigger level is set to 1, and we tried several baud rate (230.4k / 460.8k / 921.6k), the symptoms are the same. could you give me some help. Thanks~~~

Hi, Can you set the FIFO trigger level to half the FIFO size and try? Also check with baudrate of 115.2K. Regards, Prasad

Hi, sorry to reply late. baud 115200 also not works. I found some symptoms. I register ISR in one task. when ISR can be processed, the data transmission seems already finished. so we always can receive less than FIFO size. does it mean ISR not be processed immediately ? and the INT priority is already set to 1. Thanks~~~

Hi Markii, Did you try setting the FIFO threshold as suggested above? Regards, Rishabh

Hi, yes, we also check FIFO threshold to 8/16/32, but it seems no much difference. Thanks~

Hi Markii, I did not get from your previous reply what you mean by - "I register ISR in one task. when ISR can be processed, the data transmission seems already finished. so we always can receive less than FIFO size." Are you receiving the data from external device before the UART in SoC is configured? Regards, Prasad

Hi, Uart config and ISR register in task's drvcreate function, before receiving the data from external device. if external device send more than 64 bytes to TDA2, I always can receive only the first 64 bytes data. that is why I think the data transmission had already finished when ISR was called. Thanks~~

Hi, Can you tell what version of software you are using? Also share the sequence of APIs you are using to configure UART? Regards, Prasad

Hi, SDK version is 03_04 UART configure flow as below ***************************************************************************************************** HW_WR_REG32(SOC_L4PER_CM_CORE_BASE + CM_L4PER_UART2_CLKCTRL,0x2); PlatformUnlockMMR(); PlatformUART2SetPinMux(); UARTConfigInit(SOC_UART2_BASE, 921600, UART_WORD_LENGTH_8, UART_STOP_BIT_1, UART_NO_PARITY, UART13x_OPER_MODE); UARTRegConfigModeEnable(SOC_UART2_BASE, UART_REG_CONFIG_MODE_B); HW_WR_REG32(SOC_UART2_BASE+UART_TLR, 0x0); UARTRegConfigModeEnable(SOC_UART2_BASE, UART_REG_OPERATIONAL_MODE); HW_WR_REG32(SOC_UART2_BASE+UART_FCR, 0x41); HW_WR_REG32(SOC_UART2_BASE+UART_LCR, 0x3); HW_WR_REG32(SOC_UART2_BASE+UART_SCR, 0x81); BspOsal_irqXbarConnect(CSL_XBAR_INST_IPU1_IRQ_60, CSL_XBAR_UART2_IRQ); BspOsal_registerIntr(CSL_XBAR_INST_IPU1_IRQ_60, (BspOsal_IntrFuncPtr)UARTIsr, NULL); Hwi_enableInterrupt(CSL_XBAR_INST_IPU1_IRQ_60); UARTIntEnable(SOC_UART2_BASE, UART_INT_RHR_CTI); ***************************************************************************************************** Thanks~~

Hi, Can you try to use the UART driver and check if you can receive the data? Driver handles the interrupts and fifo etc properly and its tested in multiple use cases. The uart driver is present in "<pdk_install_dir>\packages\ti\drv\bsp_lld\uart". You can refer the example provided. Regards, Prasad

Hi, I am trying to understand this UART driver and use it. I have 2 questions. 1. Does this UART driver can be used in TI RTOS? 2. What's wrong of my flow and configuration? why it can not work? Thanks~~~

Hi Markii, This driver can be used in RTOS. The issue here is that you are trying to use CSL based UART code in Vision SDK context. Regards, Rishabh

Hi, I found the problem of my configuration. It can work now. Thanks~~

Hi Markii, Glad that your issue is resolved. Can you please post the solution for future references. Regards, Rishabh

Ticket Name: TDA2SX: TDA2Eco and TDA2x be pin-compatible

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi We have plans to create the TDA2x Board for AVM Applications. And TDA2x Board will be shared with TDA2x and TDA2Eco. Can TDA2Eco and TDA2x be pin-compatible? Regards, JP Park

Hi JP Park, TDA2x and TDA2Eco are pin-for-pin compatible, you can check the note in the bottom of the table here: www.ti.com/.../overview.page Regards, Yordan

Hi, I want to add that the note can be somewhat misleading. The two devices are NOT pin-to-pin equivalent, but it IS possible that PCB is designed so it can accommodate the one or the other SoC. For example, TDA2 has no CSI2 interface, that is, those pins are acting as other interface pins (I think VIN pins).

Hi, Thank you for your quick reply. the problem is solved thanks to you. Regards, JP Park

Ticket Name: TDA2SX: TDA2 EVE computing power issue

Part Number: TDA2SX in this problem 's response in e2e.ti.com/.../615108 "Let me first define the terminology (at least used by me in my response) FLOPS: Single precision Floating point operations MAC: Multiply + Accumulate operation. 1 MAC is equivalent to 2 operations DLOPS: In Deep learning, as you said half float or even 8-bit fixed point data type is sufficient. So in the above slide DLOPS refers to 8-bit arithmetic or conditional operation (Multiply/Add/Compare). So you can assume 1 MAC = 2 DLOPS" But, I think that (MAC: Multiply + Accumulate operation) means 2 floating operations, DLOPS: if using 8-bit fixed point data type, 1 MAC = 2 DLOPS floating operations=2 DLOPS *4 8-bit fixed point data type operations so 4EVE @900 MHz = 4*16*900 GMACS = 57.6 GMACS should be = 57.6*8=460.8Glops is that right?

Hi, 57.6 GMACS is already accounting for 4 EVE's, why did you again multiplied by 4 in the below calculation : DLOPS floating operations=2 DLOPS *4 Regards, Anshu

Hi, Is this query still open? Regards, Anshu

Ticket Name: TDA2E: Multiple VLANs use the same IP address,how to configure?

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 There is such a problem in the customer's project requirements. Multiple VLANs need to be configured on TDA2EX SOC , but they all use the same IP address. What kind of configuration do you have here. If I configure the IP address directly, there will be conflicts and ARP will not work.

Hi, Which SDK are you using ? CPSW does support VLAN Can you provide more details about your setup ? Regards Vineet

I'm using vsdk version 3.6. Well, I mean: I use the vconfig command to configure VLAN, and the results are as follows: eth0.2 and eth0.4 sub nodes. Then I configure this node to the same IP address 172.16.2.92, so that the network function is not working. I try to Ping other 192.16.2.xxx networks. If I want several VLAN nodes to set the same IP address and the network can be connected, how can I modify it? root@dra7xx-evm:~# ifconfig eth0 Link encap:Ethernet HWaddr F8:36:9B:C2:12:64 inet addr:172.16.2.92 Bcast:172.16.255.255 Mask:255.255.0.0 UP BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:97 eth0.2 Link encap:Ethernet HWaddr 02:47:57:4D:00:92 inet addr:172.16.2.92 Bcast:172.16.2.255 Mask:255.255.255.0 inet6 addr: fe80::47:57ff:fe4d:92%131824/64 Scope:Link UP BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) eth0.4 Link encap:Ethernet HWaddr 02:47:57:4D:00:92 inet addr:172.16.2.92 Bcast:172.16.255.255 Mask:255.255.0.0 inet6 addr: fe80::47:57ff:fe4d:92%131824/64 Scope:Link UP BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1%131824/128 Scope:Host UP LOOPBACK RUNNING MTU:65536 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) root@dra7xx-evm:~# ping 172.16.2.XXX

Hi, I tried to add VLAN to CPSW interface eth1 on AM57 (same CPSW) using the commands 1. vconfig add eth1 5 (adding VLAN 5 to eth1 interface) 2. ip addr add 192.168.0.3/24 dev eth1.5 3. ip link set eth1.5 up With this I was able to configure VLAN ID of 5 for the virtual interface eth1.5 When I ping from eth1.5 using "ping -I eth1.5" I can see that outgoing ARP has VLAN ID=5. I think this confirms that VLAN interface is working. Regarding the ping issue, I think this is a generic network configuration issue on Linux and nothing to do with CPSW driver. You can take a look at these threads Regards Vineet

Yes, this should be a Linux system problem, We just want to ask you, if you modify the configuration of Linux system according to the requirements of customers, can you achieve such functional requirements? Or is this kind of customer demand theoretically unreasonable?

OK, we know that VLAN function on tda2 is good. We just want to know how to realize the function of external network communication of multiple VLANs

Hi, The network configuration will depend on the actual system that customer is using. I haven't done it myself but I am guessing that it would require setting up IP routing, enabling VLAN, trunking multiple virtual interfaces. I am sorry, but I cannot help you further with this as it does not relate to the HW or TI software. Regards Vineet

Ticket Name: Linux/TDA2: TDA2SG

Part Number: TDA2 Tool/software: Linux Does TDA2 support hypervisor? Or any kind of container technology?

HI TI supports bootloader, kernel changes required for enabling interworking with a hypervisor. Hypervsior enablement is done by our 3 party ecosystem. A number of hypervisor vendors like Greenhills(integrity), OpenSynergy, Qnx and GlobalLogic(Xen) provide support for hypervisor enablement on TDA2

Ticket Name: TDA2EVM5777: GPIO list of TDA2EVM5777

Part Number: TDA2EVM5777 Hello Is there GPIO list of TDA2EVM5777 for design reference? thank you~

Hi, You should check the device datasheet www.ti.com/.../tda2.pdf for GPIO list. Regards, Rishabh

Ticket Name: TDA2: Inquiry TDA2 feature : 2 or 3 camera signal input and process in the same time performance

Part Number: TDA2 Dear Sir/Madam I have an inquiry on this TDA2. I would like to check with you is this TDA2 able to support 2 to 3 camera signal input and is it able to process is all at the same time?

Yes, Have look into the SRV usecase, it processes 4 1MP cameras. Rgds, Brijesh

Dear Brijesh So another you able to do computer vision processing on to 4 x 1MP cameras as the same time ?

Hi Wilson, Well, it depends on what algorithms you are using and what processing requires your algorithm? Rgds, Brijesh

Ticket Name: TDA4 data padding question

Other Parts Discussed in Thread: TDA2 Hi, I'm confused about the data padding. In the previous TDA2 version TIDL has all 4 padding in all directions and it's easy to understand. According to the documents "ti_dl/docs/user_guide_html/md_tidl_fsg_io_tensors_format.html" , it indicates that input and output will have pad{T , L ,R ,B}. But when I' m checking some value in custom layer example, it uses padH and padW. Here's the first question: Is padH = pad Top , pad Bot? Is padW = pad Left , pad Right? Also I check the value of some variables in the custom layer I made, founding that variables have different value when running quantools(TIDL Process with REF_ONLY FLOW) and inference phase. For example : In the quantools phase: A inData has width and height with 128 ,96 respectively , and its padW and padH equal to 1. InData pitch equal to 12771 (Channel Pitch) and 129(Line Pitch). (12771 = 129 x 99). Why the Channel Pitch is 129 x 99? In inference phase : InData has {w , h , padW , padH } = {128, 96 ,0 ,0 }. InData pitch equal to 12416 (Channel Pitch) and 128(Line Pitch). (12416 = 128 x 97). Why the Channel Pitch is 128 x 97 not 128 x 96? There is a same question about outData. The outData dims should be 64x48. outData channel pitch is 3840 and line pitch is 72. 3840 isn't divisible by 72. Could you please explain how the padding method works in TIDL or some customer layer import setting I probably miss to cause this problem. Thank you, Kevin

Hi Kevin, Is padH = pad Top , pad Bot? Anshu >>> Yes. We assume symmetric padding in both direction so same padding is used for top and bottom of feature map. Is padW = pad Left , pad Right? Anshu >>> This padding is only in one direction ( pad left) as during computation the same padding value (of next line) is used for the right side also. This requires one extra pixel towards the end of feature map and for allocation of input/output buffers to the network we consider full line for the same. So size of a feature map is (( W + PW ) * ( H + 2PH ) )+ PW. Where W and H are width and height of the feature map, PW = padW and PH = padH. Regards, Anshu

Thanks for your reply. Could you please elaborate in detail with some illustrations or examples? The padW part is a little sophisticated. In my case : tidlLayer->outData[0].padH , padW == 2 , 8. Output width and height are 64 and 48. outData channel pitch is 3840 and line pitch is 72. I got these pitch value from outDataParams->pitch[1] and outDataParams->pitch[2] respectively. Somehow the channel pitch is not divisible by Line pitch. I wonder if I have missed for some parameters setting in the import phase. Thank you, Kevin.

Hi Kevin, Channel pitch need not be a multiple of line pitch. The reason is that sometimes we align channel pitch in such a way that it is more efficient from DMA/kernel access point of view. But the minimum channel pitch should be as mentioned in my previous response (( W + PW ) * ( H + 2PH )) + PW ( I just noticed that one of the bracket was in correct in my previous response, I have corrected it now). Regards, Anshu

Ticket Name: TIDEP-01017: An error occurred when the number of sample points was set to 512 [ cascade_radar_beam_form]

Part Number: TIDEP-01017 In the example of Cascade_radar_beam_form, the following error occurred when modifying the Chirp parameter to set the sample points to 512 [IPU1-0] 14.243518 S: CAPTDRv/SRC/VPSDRV_capturecore.c@line 643: [IPU1-0] 14.243610 s: Core control: Set Max Frame Size failed [IPU1-0] 14.243701 S: Line: 395 in capturelink_drV. C: Status == FVID2_SOK: Failed!! The setting of sample points to 511 can be set successfully, I have read the documentation and forums and mentioned that the maximum number of sample points is 512, and why the example of Cascade_radar_beam_Form sets the sample points to 255 instead of 256, and The example of Cascade_radar_object_detect to 256 However, with the same configuration parameters, I used mmWavestduio to configure successfully and collect ADC data

Hello, As you mentioned the maximum number of sample points is 512, i.e starting from 0 to 511 (Total count = 512). Similar is the case with 256 sample points as well. The parameters start from 0 and hence end at 255 or 511, making the count as 256 or 512 respectively. Let us know if you have more questions. Thanks! Regards, Ishita

Hi Ishita , First of all, thank you for your answer. But I'm a little confused by your answers and the comments on the code, which are as follows： It is explained in the annotation that the maximum number of sampling points for Chirp is 1024. If the number of sampling points is 1024, the actual configuration should also be 1024. Due to the limitation of FPGA in TDA2-DSP, the maximum width is 512, so the maximum can only be configured with 512. In addition, Bsp_ar12xxGetWidthHeight(UInt32 deviceId, UInt32 *width, UInt32 *height) is calculated with metaDataLen included when calculating the width size. The length of metaDataLen is exactly equal to a sampling point (metaDataLen = 2U * numRxAntenna), the metaData data is CP (Chirp Parameter information), if so, it can be understood that the maximum number of points can only be 511.But using mmWavestudio is configurable to 512 points and frame data may not contain CP data, so where can the example Cascade_radar_beam_form modification be without CP Thanks and Regards

Please change this code in radar\src\common\chains_common_cascade_ar12xx_config_bf.c file gAr12xx_bf_config_master{ .transferFmtPkt0 = (rlUInt8_t) 6, /* change this to '1' for ADC only instead of CP_ADC_DATA */ Same for slave configuration (gAr12xx_bf_config_slave_DevIdxMap2) Regards, Jitendra

hi Jitendra, Your answer has solved my problem, Thank you very much. Regards, CSBoy

Ticket Name: Linux/TDA2EVM5777: VPE output buffer pitch is less than width

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: Linux Dear experts, In VisoinSDK 3.6 Linux_all/Bios_all on TDA2 EVM. Capture(720P) -> VPE(600x600) -> Display(600x600 inside 1080P HDMI) I ran into a problem that VPE's output buffer size is less than the width I provided. DSS init will fail because input pitch is less than 600. I found that in VPE code: vpeLink_drvCommon.c@ line 481, function VpeLink_drvCreateOutObj,                 /*Width aligned to satisfy encoder requirement*/
-                pFormat->width = VpsUtils_floor(pFormat->width, 16U);
+                pFormat->width = VpsUtils_align(pFormat->width, 16U);
                pFormat->pitch[0] =
                    VpsUtils_align(pFormat->width, VPS_BUFFER_ALIGNMENT); Please help to confirm is it correct? by default it will get 592, after modification, it will get 608. Thanks & Best Regards! ZM

I think width is 592, but pitch will still more than width, isn't it? pitch is calculated from the aligned/floored pitch. Rgds, Brijesh

Hi Brijesh, Our customer's algorithm wants 600x600 image. If VPE outputs 592x592, it means 8 pixels data is lost/incorrect. if output data is 608x608, it is larger than 600x600, which make sense. the algorithm can only take 600x600 from it, all 600x600 is correct. From the example in the description, displayLink is configured 600x600, this is not same with VPE, which will cause assertion. Thanks & Best Regards! ZM

Ming, Can you show the display error? Ideally it should not. Display just works based on what is sent by the previous link. in this case, it will just display 592 pixels, if the pitch and width are correct. The last 8 pixels will be back ground color.. The other way to fix is, to change the code to make it ceil, instead of floor.. But then you need to enable inline scalar, or crop the buffer.. Is it possible to just comment out floor operation and check output? I am not sure why it is added.. I think width can be anything, does not necessarily required to be aligned to 16.. Rgds, Brijesh

Hi Brijesh, 1. VPE must output the exact size as we want, no matter the size is 16-aligned or not. It can provide a larger buffer for us to crop, but it shouldn't provide a smaller buffer. The patch at the beginning works for this. Please help to check if this logic is correct, since all our demo are 16-aligned. 2. DisplayLink CreateParam is set from usecase, may not align with VPE. (From my understanding, we only configure displayLink's output size, input size is from previous link. There might be some debug work to do here. After changing VPE source code, this error disappear.) The error message is as follows. [HOST] [IPU2 ] 51.171140 s: DISPLAY: Create in progress !!! [HOST] [IPU2 ] 51.171597 s: dispcore/src/vpscore_dss.c @ Line 1079: [HOST] [IPU2 ] 51.171719 s: Pitch less than Width [HOST] [IPU2 ] 51.171811 s: dispdrv/src/vpsdrv_displayCore.c @ Line 304: [HOST] [IPU2 ] 51.171902 s: Set DSS parameter failed [HOST] [IPU2 ] 51.171963 s: Assertion @ Line: 459 in displayLink_drv.c: status==SYSTEM_LINK_STATUS_SOK : failed !!! Thanks & Best Regards! ZM

Great Ming, since the issue is resolved after changing VPE link, i am closing the thread..

Ticket Name: TDA2: [TIDL] JDetNet_SSD output format

Part Number: TDA2 Hi, I ran JDetNet_SSD with tidl_config_jdetnet.txt in TIDL 01.01.00.00 and stats_tool_out_eve.bin (stats_tool_out_eve.bin.zip) was outputted in folder ./modules/ti_dl/test/out. What is data format of stats_tool_out_eve.bin ? Best regards,

Please refer to below thread.. e2e.ti.com/.../2503936

Ticket Name: Linux/TDA2: wlan0 no wireless extensions

Part Number: TDA2 Tool/software: Linux Hi Expert, I'm running Linux Vision SDK v03.02.00(4.4.84) on the custom PCBA. Check ASUS USB-N13 rev A1, kernel modules is rt2800usb. Select ralink driver. Check driver is loaded. When plug usb-N13, log is below: But, wlan0 no wireless extensions. why? wlan0 try restart, and print: IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready should I be solved "wlan0 no wireless extensions" first? Could you please give some suggestion here? Thanks in advance.

Make sure you have enabled CFG80211_WEXT configuration in your Kernel. It would be under -> Networking support -> Wireless -> cfg80211 - wireless configuration API -> cfg80211 wireless extensions compatibility

Ticket Name: TDA2EVM5777: [TIDL_OD][PROCESSOR SDK VISION] Statistics with different input fps

Part Number: TDA2EVM5777 Hi, This is regarding TIDL_OD running on TDA2x. Here are some experiment, running TIDL_OD with same indput data, differnt fps settings. Even though using the same input data, we see the different in Statistics printing between 1 fps and 60 fps. Please find below screenshot for details. What is the reason for the difference? Thanks, -Shibata

Hi DSP1(60 FPS): When the CPU load is very high(Almost close to 100%), then this will not print any statistics. IPU1(1 FPS): Some task CPU load we are not printing in our code if it's taking < 0.1 % Thanks Gaviraju

Thanks Gaviraju. Understood. Regards, -Shibata

Ticket Name: TDA2: CortexA15 exception vector base address when boot

Part Number: TDA2 Hi， I have already known the device boot from the internal 48K ROM by the master Cortex A15 when reset. My question is that if the default A15 exception vector base address is the same as base address of the internal ROM. If not, how can A15 boot from the internal ROM? Thanks & regards.

Hi Yang Wang, There is a hardware tie off in the Cortex A15 subsystem which says when the A15 generates an access to 0x0 Address, the access is directed to the ROM region. On boot, the MMU is not enabled. Hence the 0x0 generated by the A15 on the address bus is sent to the ROM as a result of the tie off. Thanks and Regards, Piyali

Hi Piyali, Thanks very much for your reply! About this tie-off, which document can I refer to? Is this tie-off configurable? If not, how should A15 access GPMC space(since GPMC space starts from 0x0)? Thanks and regards

Hi, The Tie Off is not configurable. You can set up the A15 MMU to map the 0x0 to the GPMC memory location. Thanks and Regards, Piyali

Hi Piyali, Is the tie off specific to virtual address or physical adress?

And where can I find introduction to the tie off? Thanks and regards.

Hi Yang, This information is not present in the TRM. I will take an action to inform our TRM team. The tie off is such that when ever a physical address 0x0 reaches the A15 subsystem, it will re-direct to the ROM. Thanks and Regards, Piyali

Ticket Name: TDA2: video input raw bayer(RGGB) 12bit to RGB888

Hi all, Now I'm using TDA2xx and VisionSDK 2.9. The video sensor is AR0132 whose format is RGGB 12bit parallel. But the algorithm needs RGB888 format as input. Does anyone know how to convert the raw bayer data to RGB data? The ideal solution is that TDA2xx itself has the hardware modules for format converting. Thanks.

Hi Hu, There is no HW module in TDA2x to convert Bayer to RGB888. You could use ISP module to convert from Bayer to RGB888, but it is supported on TDA3x and TDA2Px. Regards, Brijesh

Hi Brijesh, Actually, we are planning to use TDA2Px. Could you tell me more details about how to convert the data format with ISP module? It's better to give us the user manual of TDA2Px. Thanks.

Hi Rooney, You could go through the ISS based usecases on TDA2PX in VSDK. These usecases captures bayer data from sensors like OV10640 and uses ISP convert Bayer into YUV420. Regads, Brijesh

Hi Brijesh, Which version of VSDK support TDA2PX ? If there is a usecase that support the conversion from bayer to RGB888 inside VSDK?

Hi rooney, Starting from VSDK 3.2 release supports TDA2Px platform and there are ISS usecases in VSDK which uses ISP to convert Bayer to YUV420.. Regards, Brijesh

Ticket Name: TDA2EVM5777: if the board can connected with the sensors?which type of the interface this board support?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 1.TDA2/TDA2P/TDA3.What are the main differences between these three series? 2.Does the corresponding EVM product purchase include a software support package? 3.Are external sensors currently supported by camera, laser radar, ultrasonic radar and millimeter-wave radars? What is the corresponding interface type? 4.If we need to be based on the current EVM to do software adaptation and two development, TI can provide technical support? 5.Only buy CPU board can be used or must be used in conjunction with other supporting board? 6.What is the initial estimate of the cost? How long is the purchase cycle? 3ks~~~~

hi, user5786212 , 1. Check Device Comparison tables of all devices to figure out the differences. 2. Vision SDK and processor SDK you can download from ti.com. 3. Will ping an expert to answer. 4. You can relay on the forum for support. 5. will ping 6. Contact TI representative for information about cost and purchase cycle. Best regards, Mariya

Hi, Answers for other questions. There are many different EVMs or boards available for these platforms. More details of boards are at www.ti.com/.../tools-software.html Optional boards / sensors for EVM available are listed at www.ti.com/.../tda2pxevm 3. Based on the board Image sensor and TI mmWave sensors can be connected. 5. That depends on the usecase for development. If an image sensor / LCD display is needed that board needs to be used. Again please refer to the link above for details on various options.

Ticket Name: RTOS/TDA2: BIOS API function descriprion

Part Number: TDA2 Tool/software: TI-RTOS Hi, I'm new in vision sdk and TI processors. Could you tel me where I can find list and discriptions functions like: Vps_printf(), Utils_memAlloc(), ChainsCommon_Osal_fileOpen()?

Hi Danil, You can grep for these APIs in Vision SDK. E.g. Vps_printf is defined in links_fw/include/link_api/system_trace.h. For more documentation you can refer to PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\docs\VisionSDK_ApiGuide.CHM. Regards, Rishabh

Ticket Name: RTOS: Why the cores(DSP, EVE, A15) initialize for NullSource link?

Tool/software: TI-RTOS Hi, I saw the image that is showing the flow of TIDL OD chain. As the below image showing, the NullSource link is allocated to IPU1_0. However, in linksInclude_${core}.h, there are define instruction for nullsrc in EVE, DSP. For example, in linksInclude_a15_0.h, #ifndef linksInclude_a15_0 #define linksInclude_a15_0 #define links_common_algorithm #define links_common_dup #define links_common_gate #define links_common_ipcIn #define links_common_ipcOut #define links_common_merge #define links_common_null #define links_common_network_tx #define links_common_network_rx #define links_common_nullSrc #define links_common_select #define links_common_sync #define utils_common #define links_common_system #define links_a15_system #endif Could you tell me Why #define links_common_nullSrc is needed in a15 and DSP, EVE?

Hi, In TIDL_OD usecase we use NullSrc link on IPU1_0 but it is a common link which can run on any core. So we build this link for all cores but filesystem support is not available for all cores except IPU1_0 so you can not read any files using NullSrc if you run on any cores. In TIDL_OD we have to read a file so its been used on IPU1_0 cores. Regards, Anuj

Ticket Name: TDA2EVM5777: [TIDL] Queries about caffe-jacinto layers

Part Number: TDA2EVM5777 Hi, This is regarding TIDL (REL.TIDL.01.02.00.00) I’m looking caffe-jacinto model. I would like to know the details about “DetectionOutput” layer and “PriorBox” layer. - What is done in these layer? - The meaning of each parameters (min_size, aspect_ratio, share_location, code_type, etc.) I checked TIDeepLearningLibrary_UserGuide.pdf as well as API guide TIDeepLearningLibrary_API.chm, but could not find good explanation. Are there any information? Regards, -Shibata

Hi, TIDL implements Single Shot Multi Box Detector (SSD). https://arxiv.org/abs/1512.02325 The layers that you mentioned were originally developed by Wei Liu, who implemented SSD in Caffe. You can see the original implementation of SSD here: https://github.com/weiliu89/caffe/tree/ssd The original implementation of the specific layers that you mentioned are: https://github.com/weiliu89/caffe/blob/ssd/src/caffe/layers/detection_output_layer.cpp https://github.com/weiliu89/caffe/blob/ssd/src/caffe/layers/prior_box_layer.cpp You can go through these files to get a better idea. [caffe-jacinto](https://github.com/tidsp/caffe-jacinto) is derived from [nvidia-caffe](https://github.com/NVIDIA/caffe), the SSD part of which is which in turn inspired by Wei Lu's implementation. Best regards,

Hi Mathew, Thanks for sharing the information. Please close this thread. Regards, -Shibata

Ticket Name: TDA2EXEVM: How to use ACF+Adaboost related API for inference in TDA2?

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi, I have referred to "github.com/.../acf-jacinto" and trained a FaceDetection cascade model using Matlab. So next how could I used the generated model to do the reference in TDA2? Is there any usecase (.e.g using this method for object detection) provided by Vision SDK so that I could refer to it? Thank you!

Hi, I will check with TIDL team & get back. Thanks Gaviraju

Hi Gaviraju, Thank you and look forward to your reply!

Hi, Please refer to the below demo use-case for reference. vision_sdk\apps\src\rtos\usecases\tidl vision_sdk\apps\src\rtos\usecases\tidl_OD vision_sdk\apps\src\rtos\usecases\semSeg file: vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_UserGuide_TI_DeepLearning.pdf Thanks Gaviraju

Ticket Name: TDA2EXEVM: TIDL algorithm

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hello, I am new to TDA2 also TIDL. I used caffe model and the model import tool to generate two .BIN files. How to use this two .BIN files to get the model output?? I found inside the TIDL/algo/ and TIDL/inc folders,there are a lot of layers definition. But it's huge and complex for me. Is there any example or resource about this part? If there is any useful information,please share with me. Thank you in advance.

Please refer the users guide for details on the importing a model and executing the same on device. Users guide is part of release package. We also have sample test bench (Part of TIDL release package) configuring the library. By default the sample stand alone test bench runs example model (net and params bin file from testvecs folder) and generates output. Refer these for more details. Thanks and Regards, kumar.D

Hello Kumar, Thank you for your response. I have already read the user_guide for importing the model and success. also i can run the sample test bench, and get the ourput .bin files. but actually i didn't know how it works. how the test bench generate the .bin files and how i use my own files?? Thank you.

Please refer the section "3.6 Running a Model trained by user" in the users guide to generate *.bin files from your own files. Thanks and Regrads, Kumar.D

Ticket Name: TDA2EVM5777: SYSBOOT and SW5 settings for EVM Rev. H

Part Number: TDA2EVM5777 Hello, We recently purchased multiple VAYU XC5777X EVMs. The EVM revision is 'H'. As per SPRUI51 (TDA2x EVM CPU Board User's Guide), "ES2.0 is on CPU Board Rev H+". We are working with Vision SDK 3.06 and I am referring to VSDK User Guide for TDA2xx, section 3.5 (Boot Modes). This section does not contain the relevant settings for the TDA2xx ES2.0 device. Please advise. Thank you.

Hi, SYSBOOT and SW5 settings are same between TDA2xx ES1.1 and TDA2xx ES2.0. You can also refer to "Initialization" chapter from TRM. Regards, Rishabh

Ticket Name: TDA2HG: 3D GPU SGX544 SrvInit failed (24) [47, /pvrsrvinit.c]

Part Number: TDA2HG Hi, In one production fail at Client, the following errors from GPU was observed : ---------------------------------------------------------------------------------------------------- PVR_K: (FAIL) SGXInit: Unable to validate device DDK version PVR:(Error): PVRSRVInitSrvDisconnect: KM returned 24 [2638, /bridged_pvr_glue.c] PVR:(Error): PVRSRVBridgeCall: Failed to access device. Function ID:3223086861 (Bad address). [294, /pvr_bridge_u.c] PVR:(Error): SrvInit: P[ 9.127164] DMA: Module install successful, device major num = 248 VRSRVInitSrvDisconnect failed (24). See srvkm lo[ 9.137745] DRV: Module install successful g for details. [135, /srvinit.c] PVR:(Error): m[ 9.145803] DRV: Module built on Jan 23 2020 19:58:43 ain: SrvInit failed (24) [47, /pvrsrvinit.c] ------------------------------------------------------------------------------------------------- Please find attached the complete log. terminalTDA2x@RT.#1.txt Is this a GPU hw issue ? Which other hw issues can make the initialization fail ? How to debug for exact cause? Thank you. Best Regards, Mukund

Hi Mukund, The log shows there is some compatibility mismatch between sgx-km and sgx-um. Compiler options used for sgx-km and sgx-um seems different. The dmesg log says sgx-km is in debug mode. As TI releases always release-mode sgx-um binaries this could be the issue for the failure. Is the issue observed consistently or sometimes? Do you have any idea of commit-id of sgx-km and sgx-um used in the system? Please share the same if you have. Thanks RamPrasad

Hi RamPrasad, Can you please elaborate on compatibility mismatch between sgx-km and sgx-um. I could not make it out from the log. Also How does the Compiler options used for sgx-km and sgx-um seem different? Where does the log say sgx-km is in debug mode? Thanks Mukund

Hi Mukund, Default sgx-us binaries available is built with BUILD=release, but the log you shared has some PVR_K prints in sgx-km which suggests , sgx-kernel modules are built with a different options(BUILD=debug and may be some more). Please try to get information on what compiler options are used to build sgx-km. Thanks RamPrasad

Ticket Name: TDA2: EVE/VCOP internal memory usage

Part Number: TDA2 Hi, I'm newer in VCOP programming and I try understand how to organize pipeline for VCOP -> DMA. Could you explain or where to read information and examples about usage IbufL, IbufH. 1. For memory allocation I use vcop_malloc(<location>, <size>) function. In location for buffer I have to point A/B buffer is used for Ibuf. So for pipeline have I to allocate array for each A and B? 2. I have kernel Vcop function in k. file. For pipeline I should use next sequence : loop { 2.0 Wait end start_dma_(pointerA, toOutput); 2.1 kernel_k_func(pointerA); 2.2 start_dma_(pointerA, toOutput); 2.3 Wait end start_dma_(pointerB, toOutput); 2.4 kernel_k_func(pointerB); 2.5 start_dma_(pointerB, toOutput); } Is this sequency write? 3. Vcop compiler change automaticaly takes/releas A/B banks. And DMA use this option for transfer start, is it right? 4. If for 10 kB input data algorithm produce additional 1 MB ouput data, is there additional options to control A/B switch?

Hi Danil, Please find the attached presentation, which might find useful. Here are the answers to your question: 1. For memory allocation I use vcop_malloc(<location>, <size>) function. In location for buffer I have to point A/B buffer is used for Ibuf. So for pipeline have I to allocate array for each A and B? No, if you implement ping/pong buffering, you don't need to allocate your array in each A or B buffer because both VCOP and EDMA support alias view. Please refer to chapter 10.5 of the EVE programmer's guide titled 'Simple Block Copy of an Image using EVE in Alias View'. There is a register called EVE_MEMMAP, which controls which mode (alias or full view) is applied to EDMA to VCOP. Please refer to 10.3 "EVE Memory Views and Buffer Ownership". The function VCOP_SET_MEM_VIEW(VIEW) should be called with VIEW=ALIAS_128K_VIEW to set that register accordingly. Also before using vcop_malloc(), call the function vcop_setview(mode) with mode=VCOP_MEMALIASED. 2. I have kernel Vcop function in k. file. For pipeline I should use next sequence : ... Please refer to example code in the same paragraph 10.5 of the programmer's guide or in the EVE software package, refer to apps\apps_nonbam\src\common\eve_algo_dma_auto_incr.c, function EVELIB_algoDMAAutoIncrConcurrent() and EVELIB_algoDMAAutoIncrSequential(). 3. Vcop compiler change automaticaly takes/releas A/B banks. And DMA use this option for transfer start, is it right? Yes, the functions VCOP_BUF_SWITCH_TOGGLE() or VCOP_BUF_SWITCH_SET() takes care of that. 4. If for 10 kB input data algorithm produce additional 1 MB ouput data, is there additional options to control A/B switch? Since image buffer A or B is only 32 KB, you only have 22 KB to store the output of your processing so you need to find a way to break your processing in smaller chunks since you have a 100x size ratio between input and output. May be process divide your 10 KB in chunks of 200 bytes. Each chunk of 200 bytes will produce 20 KB bytes which can be transferred to DDR. regards, Victor 3_Implementation of an EVE App.pdf

Ticket Name: TDA2HV: TI support of QEMU for TDA2 APP

Part Number: TDA2HV Other Parts Discussed in Thread: TDA2 Hi there, 1. Does QEMU support TDA2 APP? I have been searching for some time but in QEMU says that if the TDA2 machine is not listed than is very unlikely to be supported. 2. Is there any emulator support to test app without a board? I need it for testing. The board can be damaged by a quick test. 3. Can I convert my Application Image back to ELF? In my opinion, it is converted to ELF -> Application Image(RPRC) using the following command. ``` out2rprc.exe <App_In_name(elf or coff)> <App_out_name> ``` Please let me know if it supported. Any guidance would be appreciated. Regards,

Hi, 1. No. We don't have QEMU support on TDA2. 2. No. We don't have emulator for TDA2. 3. No. We don't have utility to covert AppImage back to multiple Elf files. Regards, Stanley

Ticket Name: TDA2HG: TDA2HG TRM

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 Hello, Could you give us a TDA2HG TRM.pdf. We are using this device. On the other hand, for TDA2HG, can we run the visionSDK 03 05? Thanks Terence

Hi, Please refer to http://www.ti.com/lit/ug/sprui29f/sprui29f.pdf Yes you can run Vision SDK 3.05 for TDA2HG. Please note that Vision SDK is not customized for paper parts, it supports TDA2 superset part. In case customer is using a part that contains lesser number of hardware accelerators or supports lower frequency as compared to superset part, they need to modify the software accordingly. Regards, Rishabh

Hi Rishabh, I read the sprui29f.pdf. But, I can't find the information about TDA2HG. Do you have TDA2HG TRM.pdf? For example, TDA2Px TRM.pdf Thanks Terence

Hi Terence, TDA2x is the platform and has multiple paper parts. TDA2HG is one of the paper part. Separate TRM for paper parts is not there. Similarly TDA2Px is platform with multiple paper parts. Regards, Rishabh

Ticket Name: TDA2E: MMWCAS-DSP-EVM Bring up

Part Number: TDA2E Other Parts Discussed in Thread: MMWCAS-DSP-EVM, TDA2 Hello I have as MMWCAS-DSP-EVM and want to use this to run RADAR Use case under the PROCESSOR_SDK_RADAR_03_07_00_00. I have compiled the PROCESSOR_SDK_RADAR_03_07_00_00 with use case for tda2xx_cascade_bios_radar and then followed following the steps mentioned in VisionSDK_UserGuide_TDA2xx.pdf 1) section 3.6 (Load using SD card ) 2) 3.6.1 (Option 1: Steps to prepare a bootable SD card ) 3) 3.6.3 (Steps to generate MLO) 4) 3.6.4 (Steps to generate appImage) 5) 3.6.5 (SD Card setup) Now when i try to plug the SD card into the MMWCAS-DSP-EVM board doesn't boot up. If anybody can tell me what is the issue it will be really helpful for me. Br Deepak Joshi

Hi Deepak, What is the SoC present on this board? Can you share the link where you ordered it. Regards, Rishabh

Hello Rishabh, It has TDA2 Soc. we didn't ordered it online but was purchased directly via our FAE. I have the photo of the board, if this helps can post that in the forum. Br Deepak Joshi

Hi Deepak, It will be helpful if you can get the link from your FAE. Regards, Rishabh

Hello Rishabh, Just got info from our FAE that this board is not in public domain. So i will my question to further private forum. Br Deepak Joshi

Hi Deepak, Ok thanks for the update, you can post it on private forum. FYI you might be missing SYSBOOT settings or UART serial port settings might not be set correctly in case you do not see any logs at all. Regards, Rishabh

Ticket Name: TDA2: HDMI differential pairs signals routing with via

Part Number: TDA2 I would like to use micro-HDMI connector in my product design due to space constraint, vias are unavoidable in routing. However, according to table 8-16 TMDS Routing Specifications, no via is allowed on each TMDS trace. Is this a mandatory specification to follow, if not, HDMI signal will be distorted? How would you advise if to use micro-HDMI connector?

Hi, Datasheet requirements are always mandatory unless the opposite is noted. In your case, it doesn't mean necessarily hdmi will not work, but TI will not be able to support you because a requirement was not followed. Note also that such requirements often come not only from TI but also from the relevant standard specs (HDMI). I would like to recommend you to consult with HDMI specs and hdmi.org prior to proceed. Please see also this topic: Q. What testing is required? Regards, Stan

Ticket Name: RTOS/TDA2HG: 2D SRV calibration issue.

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hi Sir, I followed "VisionSDK_UserGuide_SurroundView_Calibration_TDA2xx.pdf" to using "calibration_tool.exe". This tool asks me to input a reference image, I don't know how to generate a reference image and I give the "refimg.jpg" that is from "/surround_vision_tools/docs/", is it right? I input all the image files and parameters, and then follow the document to go to next step, after I go to step that select "reference image" and click "Continue", this tool will close and no next step, But if I input the sample data (from "/2D_calbration_tool/sample_data"), this tool can work correctly. Attachment are the "refimg.jpg" and I took a calbration picture by TDA2 EVM, original .yuv file is 1.31MB, I transfer it into .jpg file. FRONT_1.rarRanny,

Hi Sir, I change the file name form .YUV to .yuv, just rename the image extension name as small letter, calibration tool can work now. Ranny.

Hi Ranny, thanks for updating the thread and sharing the solution. Regards, Yordan

Ticket Name: Linux/TDA2: Trivially reproducible hard lockup (JTAG reports pipeline stall) with RT Linux and FIO

Part Number: TDA2 Tool/software: Linux We have a Cortex-A15 based device (the TDA2) and with the RT kernel and fio 2.16-1 from Debian, I get a lockup where JTAG reports: CortexA15_0: Trouble Halting Target CPU: (Error -1323 @ 0xFFFF1044) Device failed to enter debug/halt mode because pipeline is stalled. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.903.6) 
 This typically happens within a minute of starting the test. Because it happens with a ram based block device and not actual hardware I'm assuming this can be duplicated on hardware other than our own. I'm hoping someone else can try this test on newer RT kernel versions (we're using 4.1) and report back on whether they see issues. Here is the fio test file: [global] name=fio-verify-RW filename=fio-verify-RW rw=randrw bs=4K numjobs=1 invalidate=1 iodepth=1 loops=1 verify=crc32 [file1] filename=/dev/nullb0 I chose the null_blk device driver but any block device works, such as an actual physical block device, a loopback mounted file on tmpfs, or the ramblock driver. Writing to a file does not duplicate the issue. Not verifying the data greatly decreases the likelihood of seeing the lockup. I also can't reproduce on a non-RT kernel.

Hi The SDK release does not support RT kernel patches - hence we have not validated RT support on the SDK code base. Are you trying to bring this up on a different kernel version and have integrated RT patches on your own - would be quite difficult to support in which case. Though not part of the SDK, RT patches have been integrated on TI kernel branches for kernel 4.4/4.14 - refer git.ti.com/.../ti-rt-linux-4.14.y as an example. This should serve as better baseline for RT feature development, but please be aware that not all SDK features,patches would be available on this branch Finally to re-iterate SDK release does not support RT kernel patches and there are no plans to take this up

Hi, I am not asking TI to support my specific kernel on my specific processor. I provided a test case which should be very fast to reproduce on alternate CPUs and kernels since it uses very standard software - fio - and doesn't require any specific hardware. My understanding is many TI processors are quite similar to each other, so others who are using a cortex-A15 based processor from TI, perhaps such as a Sitara 5728, and an RT kernel may want to try this test case. If so I'm hoping they will report back on what happened for them.

Hi Did check internally on the specific tests that we run In addition to running cyclic test to measure latency, we also run block IO test(read/write to block media) to measure IO throughput in case of RT kernel. We have not run FIO tests

We have not been able to reliably reproduce this with anything other than FIO, and only when writing directly to a block device. We write directly to block devices as part of our software update proces, but this does not reliably reproduce the hard lockup.

Sarah Our product test team was able to run FIO tests against 4.19 kernel(TI kernel:RT and non-RT branches) and did not see any lockups Testing was carried out on AM57x platform

Ticket Name: Linux/TDA2EVM5777: Rebuilding AVBTP package failed!

Part Number: TDA2EVM5777 Tool/software: Linux Hi, I'm trying to insert log message into AVBTP_processRxPackets function. At first, i cleaned previous linux and app and rebuild all that. However, the log message was not occured. I found and refered avbtp_0_10_00_00_user_guide.html. In that document, it says use xdc to rebuild AVBTP package in ti_components/networking/avbtp_0_10_00_00/packages/ti/avbtp directory. So, i execute xdc command in that directory but the error message was showed as below. making package.mak (because of package.bld) ... js: "./config.bld", line 77: define NDK_ROOT! gmake: *** No rule to make target `package.mak', needed by `.interfaces'. Stop. Could you suggest the cause of this error? Regards, Yoo

Additionally, i tried to find /opt/ti/ccsv6 but that is not exist. Could you also tell me how can i get this? Thanks.

Hi Yoo, can you open ti_components/networking/avbtp_0_10_00_00/Rules.mak and modify following variables according to your installation: COMPILER_DIR (this should point to <Code Composer install dit>tools/compiler) and XDC_ROOT NDK_ROOT BIOS_ROOT EDMA3_ROOT NSP_ROOT currently they are set as if those components are installed in /opt/ti directory. You need to point them to the right directories in VisionSDK tree. Regards, Yordan

Hi, Then, are you meaning the AVBTP package should rebuild by CCS compiler? Regards, Yoo

Hi Yoo, I think you can point those variables: TIARMCGT_ROOT GCC_ROOT CGT6X_ROOT to the corresponding tools installed in ti_components/cg_tools/ Regards, Yordan

Ticket Name: TDA2: Load program failed for TestAppEncoder.out file for TDA2PX device

Part Number: TDA2 Hi, I am getting the following error on loading the TestAppEncoder.out file from h264enc\app\build\TestAppDM816x\out in ti ivahd_h264 encoder package. CortexA15_0: File Loader: Verification failed: Values at address 0x00000000 do not match Please verify target memory and memory map. Code Composer Studio Version Used 8.0 Target configuration file TDA2PX device Please help me to resolve this error. Regards Mayank

Hi Mayank, Data Verification errors are described here: software-dl.ti.com/.../troubleshooting-data_verification_errors.html Can you check if you can find any directions for resolving your issue in this document? Regards, Yordan

Hi Mayank, I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Ticket Name: TDA2SX: TDA2 Quantization Mobilenetv2 Models

Part Number: TDA2SX I use ptyorch to train the UNet model. The backbone network is mobilenetv2. The pytorch model was transferred to the onnx model, and the onnx model was transferred to the caffe model and quantified. However,the quantification failed. What is the reason?modles.zip

TDA2x devices support only a limited set of models fo development. Please refer to the user guide for supported/Validated models. Could you please share more details about your project and application requirements to suggest one of our latest devices? BTW, Please refer below for more details the TDA4x and AM62 github.com/.../edgeai-tidl-tools

Ticket Name: CCS/TDA2: EVE and DSP Utilization to run Network Layers in TDA2x/TdA3x

Part Number: TDA2 Tool/software: Code Composer Studio Hello Sir, I need to know, how to split the models across the EVEs and DSPs. Example how to utilize the 2 EVEs sequentially, utilizing 2 EVEs in parallel, EVE followed by DSP and other such configurations. I have deployed Caffe_Jacinto_SSD model on TDA2x by following TIDL_LIBRARY_USER_GUIDE.pdf to split Network layers through making some small changes in "LayergroupId" to run the model across EVE's and DSP's. Kindly suggest some important documents to understand all the configurations, their Implementations and gain Expertism in splitting Networks across EVE's and DSP's. Thanks and Regards, Vyom Mishra

Hi Vyom, can you check FAQ #21 and #22 in TIDeepLearningLibrary_UserGuide.pdf and see if they can help you? Regards, Yordan

Hello Sir, I have mentioned above that, I have already deployed SSD by splitting it across the EVE and DSP, by following the FAQ 21 and 22 only. So, I am requesting you to provide more on it, If there are some more documents available, to explore. Thanks and Regards' Vyom Mishra

Hi Viyom, Can you clarify you question further. You mentioned that you could deploy network by setting layer group ID. Is your your question specific to uses case development for the network or optimally setting layer group ID

Hello Sir, Basic splitting of the SSD model across EVE and DSP is done by refering the User Guide(FAQ 21 and 22). Now I need your suggestions for below queries. How to utilize the 2 EVEs sequentially, utilizing 2 EVEs in parallel, EVE followed by DSP and other such configurations. Kindly suggest some important documents to understand all the configurations, their Implementations and gain Expertism in splitting Networks across EVE's and DSP's. Thanks and Regards, Vyom Mishra

Dear Sir, I have the following queries with respect to my question above. 1. If model is floating point, In TIDL is the model converted to fixed point for inference on DSP as well? 2. Can the intermediate output of DSP be given to EVE? May not be if DSP output is floating point. Pl confirm. ex: If I have model designed and grouped to run as EVE->DSP->EVE->DSP 3. Any limitations allocation of layerGroupId in import Config 4. Is there a standard way of optimally setting layerGroupId, other than what we know from used guide. Any other doc/experiments Thanks and Regards Vyom Mishra

1. yes. 2. Yse you can pass output of DSP to EVE. DSP also computes CNN layer in fixed point 3.No 4. Try to run all the convolution layers in EVE and Detectionoutput layer in DSP. Other layers you can either run DSP or EVE.

Ticket Name: TDA2P-ACD: SoC Sleep mode realization

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Hello, We are using TDA2Px in our project, we are facing some issues related to boot time optimization and sleep mode implementation with TDA2Px. We need to implement a sleep mode with TDA2Px and need to wake up the SoC using CAN signals. Is this possible for power better power management. Is there any readily available solution for this kind of implementation? The second thing is like we need to optimize the boot time to 4 seconds using Linux, Could you please suggest a way to optimize the boot time. And also please help with a readily available solution? Warm regards, Alwin Mathew

Hi Alwin, 1) No such implementation is available. It depends on what and how you want to implement. We only support dynamic power management: http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components/Kernel/Kernel_Drivers/Power_Management.html i believe you are looking at idle low power modes which are not supported. 2) http://www.ti.com/lit/an/sprac82/sprac82.pdf Describes multiple steps to optimize boot time optimization on DRA7/TDA2 devices. Regards, Keerthy

Ticket Name: TDA2HV: CLANG and LLVM build support

Part Number: TDA2HV Other Parts Discussed in Thread: TDA2 Hello Does the tda processor support "clang" builds? If applying, where should I edit it?

Hi, Not supported and no plans to add it for TDA2. Note : There is a plan to add support for TDA4 devices in next release Regards Vineet

Ticket Name: TDA2EG-17： How to modify crystal input source

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2 Hi At present, the input source of crystal oscillator used in our board is Xi_ Osc0, can the input source of crystal oscillator be changed to Xi_ osc1？ I test disconnect Xi_ Osc0 and connect Xi_ Osc1 finds that uboot cannot be started. Do I need to modify anything in uboot? The input source of Xi_osc1 is a 20MHz active crystal oscillator.

I will let SDK experts comment from SW perspective, but just as a side note, you can check the Clock Tree Tool (CTT, free to download here: https://www.ti.com/tool/CLOCKTREETOOL ). You can use the tool to study the device clock/crystal/OSC sources and their associated register configuration. This could also guide you to the answer to your question. thanks, Alex

Hi, Unfortunately OSC0 is the mandatory oscillator for TDA2. All DPLLs needed to clock the processor(s) are running from OSC0 (SYS_CLK1) Regards, Stan

Ticket Name: TDA2: tda2x

Part Number: TDA2 Other Parts Discussed in Thread: AWR1642, AWR1243, Dear officer, We are developing both tda2x and mmWave sensor module AWR1642, and I notice that the tda2x support radar input module AWR1243 from the tda2x doc. So What is main difference between AWR1642 and AWR1243? It is true that AWR1642 will do all the data process such as range, velocity and angle etc by itself while AWR1243 will only output raw data to tda2x and let tda2x to perform the data processing? Thanks and best regards He Wei Team leader for System architectures and Deep learning.

Hi He Wei, The nut shell description is correct. The AWR16 does the processing in the integrated C67x DSP and can send processed data output to TDA2 via CAN/SPI. AWR12 would sendout raw data out through CSI. You would need to convert the CSI format to VIP to capture on TDA2, or directly connect to the CSI interface on TDA3x/TDA2px. A high level comparisson between AWR16 and AWR12 is as below: www.ti.com/.../compare.html Thanks and Regards, Piyali

Dear Piyali, Thanks a lot for the clear explanation. Thanks and best regards He Wei Team leader for System architectures and Deep learning LiteOn Singapore Automotive Electronics

Hi He wei, Glad your query is resolved. Please feel free to mark the post which answered your question for the benefit of others and post any new questions in a separate post. Thanks and Regards, Piyali

Ticket Name: TDA2EVM5777: Interfacing with vehicle CAN

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello, TI TDA2 EVM has two CAN interfaces: DCAN1 and DCAN2. I want to receive information from vehicle CAN on one of these two interfaces, and use that information in an algorithm running on the DSP core. I have the following questions: 1. How can I physically connect these interfaces (DCAN1/DCAN2) to the vehicle CAN? Is there any reference which explains how to do this? 2. Are there any use-cases in Vision SDK that show how to receive/transmit CAN data? Thank you.

Hi Sagar, Answers to your questions are as: 1. Please refer to http://processors.wiki.ti.com/index.php/PDK/PDK_FAQ#CAN_Controller.28DCAN.2FMCAN.29 for more details. This page will tell you careabouts CAN connection. 2. Vision SDK do have the use-case to demonstrate the usage of DCAN. To enable this use-case you have to set 'DCAN_INCLUDE' to 'yes' in respective 'cfg.mk' file. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hello Vivek, The link you shared provides some information about the DCAN and MCAN, but it does not say anything about the physical connectors. For instance, some boards have a DB9 port to receive CAN. The TDA2x EVM has no such facility. So I am wondering if I need to solder or glue the CAN+ and CAN- wires on the DCAN terminals of TDA2x. In that regard, where can I get the board schematics for TDA2x EVM to know the positive and negative terminals of each DCAN? I found the usage for 'DCAN_INCLUDE' in Vision SDK, but it just seems to build the 'dcan' module under vision_sdk/apps/src/rtos/modules. I could not locate any application use-case(s) employing CAN information. Can you point out the same to me? FYI, we are using Vision SDK 3.06. Thank you.

Hi Sagar, I am not sure which version of EVM are you using, but you can find EVM related documents here: http://www.ti.com/tool/TDA2EVM5777#technicaldocuments TDA2 EVM does not have DB9 connector for DCAN but it does have 3 pin header for CAN_H, CAN_L and GND. For DCAN use-case, you don't need to select any specific option, it runs with all use-cases. It periodically sends out a message and on reception, it prints the message details on the console. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Ticket Name: TDA2SX: Video data conversion

Part Number: TDA2SX Hi TI Expert, 1.HDMI interface: We known HDMI output display video stream in YUV422/YUV420/RGB565/RGB666/RGB888 format from TDA2x datasheet. we do not see HDMI transfer raw data stream, please confirm whether HDMI can not transfer raw data ? or TDA2S video processing engine can not make raw data packets in raw data 8bit/12bit format ? 2.MIPI DSI/MIPI CSI: we want MIPI DSI as video source simulator, what is the difference between MIPI DSI and MIPI CSI ? Are these difference physical layer, data packet protocol, or others? please confirm whether MIPI CSI can receive video source from MIPI DSI ? Thanks

Hi Wang, Please find answers to your questions. Jiacai Wang said: we do not see HDMI transfer raw data stream, please confirm whether HDMI can not transfer raw data ? or TDA2S video processing engine can not make raw data packets in raw data 8bit/12bit format ? No, typically, raw data is not transmitter over HDMI. In fact, DSS, from where HDMI gets its input, does not support raw data.. Jiacai Wang said: 2.MIPI DSI/MIPI CSI: we want MIPI DSI as video source simulator, what is the difference between MIPI DSI and MIPI CSI ? Are these difference physical layer, data packet protocol, or others? please confirm whether MIPI CSI can receive video source from MIPI DSI ? No, Please refer to DSI and CSI specs for more details. Regards, Brijesh

Ticket Name: RTOS/TDA2EVM5777: How to detect SD card insert/remove event in VisionSDK

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Dear Expert, I'm helping to provide a method to detect SD card(MMC1) insert/remove in VisionSDK bios_all. I'm using original VisionSDK 03.06 with TDA2XEVM5777. Here is my test: Build the original VisionSDK 3.6 bios_all, and boot to menu, dump the MMC register, then unplug sdcard, dump the MMC register. Nothing changed between before and after. Since the register is no change, I tried to call HSMMCSDIsCardInserted API, and get incorrect result. Could you please help provide some guideline to detect a SD card event on bios_all. Thanks & Best Regards! ZM

Hi Ming, I am not sure if we have tested the functionality for card insert/remove in RTOS. Let me check with MMC Linux experts and get back to you. Regards, Rishabh

Hi Ming, I checked and confirmed that there is no internal card detect. Linux drivers have muxed the card detect pin as a GPIO and software uses that to detect whether a card is inserted or not. You can implement something similar in the RTOS software. Hope this helps. Regards, Rishabh

Hi Rishabh: At PDK package just can raw read MMC2 interface eMMC card. Try to modified those project support MMC1 interface but failed at my side. We did not find MMC1 card insert detect and fat system mount example at BIOS system. Customer want to use TDA2x pin W7 (MMC1_SDCD) probe the card exist or not. Best Regards! Han Tao PDK example folder \PROCESSOR_SDK_VISION_03_05_00_00\ti_components\drivers\pdk_01_10_01_06\packages\ti\csl\example\mmcsd

Hi Tao, MMC1 is used at multiple places in PDK for TDA2x. You can use any of these for referring to MMC1 code. 1. TDA2 SBL uses MMC1 for SD boot. 2. stw_lld has one example for MMC1 present here: PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\drv\stw_lld\examples\mmcsd\sd_file_io\main.c Fatlib code is present here: PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\drv\stw_lld\fatlib Regards, Rishabh

Hi Rishabh: You can close this item now. If customer have updated information, I will create new request for it. Best Regards! Han Tao

Hi Tao, Thanks for the confirmation. Regards, Rishabh

Ticket Name: PROCESSOR-SDK-TDAX: [TDA4M] What need files for running apps?

Part Number: PROCESSOR-SDK-TDAX Other Parts Discussed in Thread: TDA2, SYSBIOS Hi, In TDA2, in order to run the apps, apps.out and firmware files(dra7-dsp1-fw, dsp-f2, ipu2-fw) are needed in Linux. And, in RTOS, the appimage and MLO files are needed. In TDA4M, if I build the PSDK, the out files are generated. If I'd like to run the app, just out file is needed? BR, Heechang

In targetfs/lib/firmware, there are many files. What need the file for running the apps in "firmware" directory?

hi Mr Kim, After doing "make vision_apps" the .out files to load on R5F, C6x, C7x and A72 are stored here, vision_apps/out/J7/A72/LINUX/$PROFILE vision_apps/out/J7/R5F/SYSBIOS/$PROFILE vision_apps/out/J7/C66/SYSBIOS/$PROFILE vision_apps/out/J7/C71/SYSBIOS/$PROFILE The *.out files get loaded on respective CPUs. See vision_apps/docs/user_guide/BUILD_INSTRUCTIONS.html To copy to SD card do below make linux_fs_install_sd This copies the R5F, C6x, C7x .out from /lib/firmware folder in the SD card. Before copying they are renamed as shown below, ifeq ($(BUILD_CPU_MCU2_1),yes) # copy remote firmware files for mcu2_1 cp $(VISION_APPS_PATH)/out/J7/R5F/SYSBIOS/$(LINUX_APP_PROFILE)/vx_app_tirtos_linux_mcu2_1.out $(LINUX_FS_PATH)/lib/firmware/j7-main-r5f0_1-fw endif ifeq ($(BUILD_CPU_C6x_1),yes) # copy remote firmware files for c6x_1 cp $(VISION_APPS_PATH)/out/J7/C66/SYSBIOS/$(LINUX_APP_PROFILE)/vx_app_tirtos_linux_c6x_1.out $(LINUX_FS_PATH)/lib/firmware/j7-c66_0-fw endif ifeq ($(BUILD_CPU_C6x_2),yes) # copy remote firmware files for c6x_2 cp $(VISION_APPS_PATH)/out/J7/C66/SYSBIOS/$(LINUX_APP_PROFILE)/vx_app_tirtos_linux_c6x_2.out $(LINUX_FS_PATH)/lib/firmware/j7-c66_1-fw endif ifeq ($(BUILD_CPU_C7x_1),yes) # copy remote firmware files for c7x_1 cp $(VISION_APPS_PATH)/out/J7/C71/SYSBIOS/$(LINUX_APP_PROFILE)/vx_app_tirtos_linux_c7x_1.out $(LINUX_FS_PATH)/lib/firmware/j7-c71_0-fw endif The also copies A72 .out files to /opt/vision_apps. cp $(VISION_APPS_PATH)/out/J7/A72/LINUX/$(LINUX_APP_PROFILE)/*.out $(LINUX_FS_PATH)/opt/vision_apps cp $(VISION_APPS_PATH)/apps/basic_demos/app_linux_fs_files/* $(LINUX_FS_PATH)/opt/vision_apps In general see vision_apps/makerules/makefile_linux_arm.mak for more details on how things are copied from local folder/files to linux filesystem. To boot EVM additional bootloader files are needed these need to be copied as shown in below file vision_apps/docs/user_guide/RUN_INSTRUCTIONS.html During boot, uboot loads these binaries to respective CPUs. This is different from TDA2x where the linux kernel would load the binaries. Let me know if you need further information regards Kedar

Ticket Name: TDA2SX: TDA2XSBTQABCRQ1 Display output YUV422 hardware schematic review

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Dear experts, Our customer want to output YUV422 but not sure whether this connection correct according to TDA2 TRM. Can you help review this?

Hi Dong, It really depends on the output interface that they are going to use. If output interface is going to be BT656, then you could use 10bit output lines, ie D0 to D9 or 8bit output data lines D9 to D2. If output interface is going to be discrete sync (BT601, yuv22 discrete sync), then 8bit data would be on D7-D0 data lines.. Regards, Brijesh

Hi Brijesh, Thanks for your reply. It's very helpful to me. They have another question is how to configure BT656 or BT601 output in the SDK code.

Hi Dong, Unfortunately, EVM does not support BT656 or BT601 output interface, so SDK does not support or have any usease to demonstrate it. Regards, Brijesh

Ticket Name: TDA2HG: tda2 rtos i2c enable issue

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 Hi team, Here's an issue from the customer may need your help: Regarding TDA2 M4 I2C, bsp_device.c / bsp_deviceI2c.c / bsp_boardTda2xx.c has been modified. The interrupt is in the system_bsp_init.c file according to the chip manual. The customer tries to enable 12C2 on rtos, and the problem is as follows: [HOST] [IPU1-0] 4.918440 s: [HOST] [IPU1-0] 4.918471 s: ### XDC ASSERT - ERROR CALLBACK START ### [HOST] [IPU1-0] 4.918562 s: [HOST] [IPU1-0] 4.918684 s: E_notFound: i2c2 name not found [HOST] [IPU1-0] 4.918745 s: [HOST] [IPU1-0] 4.918776 s: ### XDC ASSERT - ERROR CALLBACK END ### SDK: 03.08.00. PDK: pdk_01_10_04_05. Under the bsp_boardTda2xx.c file, modify as follows: static Bsp_BoardI2cData gBoardTda2xxI2cData = { /* numI2c */ (sizeof (gBoardTda2xxI2cInstData) / sizeof (Bsp_BoardI2cInstData)), /* i2cData */ gBoardTda2xxI2cInstData, /* probeInstId */ #if defined (SOC_TDA2PX) BSP_DEVICE_I2C_INST_ID_4, #else BSP_DEVICE_I2C_INST_ID_2, #endif }; Changing BSP_DEVICE_I2C_INST_ID_1 into BSP_DEVICE_I2C_INST_ID_2 Interrupt configuration: system_bsp_init.c is modified as follows： * XBAR I2C5_IRQ to IPU1_42 - I2C5_IRQ (55 or 0x37) */ BspOsal_irqXbarConnect(XBAR_INST_IPU1_IRQ_41, 51); BspOsal_irqXbarConnect(XBAR_INST_IPU1_IRQ_42, 52); BspOsal_irqXbarConnect(XBAR_INST_IPU1_IRQ_42, 55); #endif /* XBAR I2C4_IRQ (57) to IPU1_48 */ Added BspOsal_irqXbarConnect(XBAR_INST_IPU1_IRQ_42, 52); Could you help check this case? Thanks. Best Regards, Cherry

Hi, May I know is there any update? Thanks and regards, Cherry

Ticket Name: RTOS/TDA2: YUV422 for discrete sync

Part Number: TDA2 Tool/software: TI-RTOS We want to display YUV422 Discrete Sync. Discrete sync Valid pixel in D[7:0]. But Our HW layout Data pin is connected to D[9:2]. How can I set SW to display YUV422 Discrete Sync?

Hi, In DSS, there is no way to shift the output. Rgds, Brijesh

Ticket Name: Linux/TDA2: Can camera data input pins be changed from D2~D9 to D0 ~D7 with UB913/UB914 ?

Part Number: TDA2 Tool/software: Linux Hi Sir, I am using TDA2x CPU board + Vision Board + daughter board + OV1652x sensor and SDK is PROCESSOR_SDK_VISION_03_03_00_00 with TDA2XX_EVM_LINUX_ALL define. I changed the sensor from "OV1653x" to "AR0140+AP0102", then I add a new driver to initial the new sensor. Using the Muti-cam -< surround view use-case, I can see the camera image on monitor, but the color is wrong, all image is close to green color. I checked the schematic of OV10635 sensor board and found that the data pins are connecting to UB913 D2 ~ D9. My design for AR0140+AP0102 is connected D0 ~ D7, I am not sure if that's the reason cause the image shows green. My I set the VIP port input pins form D2 ~ D9 to D0 ~ D7 ?

Hi User, Please note that there is board mux between sensor and vip port, which shifts data lines by 2 bits. If you have direct connect, you need to disable this shifting in the board mux. Regards, Brijesh

Hi Brijesh, I change the sensor data output form 8 bits to 10 bits format and the problem is solved. By the way, how to disable the data shifting of board mux. Thanks. Ranny.

Hi Ranny, There is a CPLD between sensor and VIP, we will have to change CPLD firmware to remove this shifting.. Rgds, Brijesh

Ticket Name: Linux/TDA2SX: Need support for TDA2XX EVM boot from NAND

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hi All, We are using VISION_SDK_03_04 source(TDA2xx). Nand support is not enabled in default u-boot source. We enabled Nand support in below paths. We added #define CONFIG_NAND 1 in include/configs/dra7xx_evm.h and modify #define CONFIG_CMD_NAND to #define CONFIG_CMD_NAND 1 in include/configs/ti_armv7_omap.h . After compiled and flash new images to EVM. We got mtdparts in u-boot. But in u-boot it shows below logs.log_NAND.txt NAND: 0 MiB And kernel log it shows "[ 1.788753] nand: No NAND device found" and "[ 2.010108] evm_3v3_sw: supplied by sysen1"No NAND device found". Please help us to solve this issue. For your reference,please find the attachment. Thanks & Regards, Sankar.

Hi Sankar, this topic is discussed here: e2e.ti.com/.../788250 I will close this thread. Regards, Yordan

Hi Yordan, Thanks for quick reply. In u-boot we given mtdparts command,we got below logs. mtdparts variable not set,see 'help mtdparts' Device nand0 not found. In which files we need to modify for enable nand0. Thanks & Regards, Sankar.

Hi Sankar, As mentioned in other thread TDA2 EVM does not have NAND flash. Regards, Rishabh

Sorry, corrected a typo in my previous reply. Regards, Rishabh

Hi Rishabh, You mean to say S/W support? Regards, Sankar.

Hi Sankar, I mean the HW support. You can check the board schematics for the same. Regards, Rishabh

0160.sprr212.pdf3107.CPU_Schematic.pdfHi Rishabh, Please find the attached schematic and layout. In schematic U6 NAND IC present in out EVM. Could you please confirm,whether we are referring correct schemtic and Source code? Regards, Sankar.

Hi Sankar, You have a duplicate thread here: e2e.ti.com/support/processors/f/791/p/788250/2932772#2932772 Please post your queries there, I am closing this thread. Regards, Rishabh

Ticket Name: TDA2: Flexray Controller?

Part Number: TDA2 Hi Our system design requires TDA2 to connect to Flexray communication network. From Datasheet and Technical Reference Manunal, TDA2 itself does not contain Flexray Controller. Do TI have a proven solution? Thank you.

Hi Chen, One potential solution is www.fujitsu.com/.../um-mb88121-am15-11201-1e.pdf which converts SPI to Flexray. Thanks and Regards, Piyali

Ticket Name: TDA2: tda2 TIDL SSD

Part Number: TDA2 Dear TI， A strange bug comes， I find that after I run the TIDL demo ， the output detection ROI coordinate is not correct！ As you see below，I printed the detected rectangle coordinate ，then check the output value of the rectangle coordinate，nearly all of those are not accurate location . Is there any constant value needed be substracted from the variable pObjectDateDesc->ypos and pObjectDateDesc->xpos ,even pObjectDateDesc->objHeight and pObjectDateDesc->objWith needed be multiplied a constan coefficient? In fact， this page that you answer me is not the right information I want。 Could you please chech the file "vision_sdk\apps\src\rtos\alg_plugins\objectdetection\objectDrawLink_algPlugin.c" ? In this file, I print the variable pObjectDateDesc->ypos and pObjectDateDesc->xpos ,even pObjectDateDesc->objHeight and pObjectDateDesc->objWith when detecting the vehicle, yet the result rectangle is far from the real vehicle objects in the image. Is there any math relation of the results coordinate？ Looking forward to your kind reply, tks dear.

Hi, There is no other math required on this Draw link code, the pObjectDateDesc->ypos and pObjectDateDesc->xpos should give the detected object positions. Are you running TIDL demo as it is without any changes and getting wrong detection's? Thanks, Praveen

Hi，Praveen If what you said is true，then I think it maybe the frame number match or synchronization problem. Is there any synchrone mechanism to match every frame's detection result？ I mean that when I saved the current frame's result， it may be running the other frame not the current one. There is a frame synchronization problem？ Is it right？ Thanks， Chenglin

Hi, There is already a sync link in the usecase before object draw link which will take care of synchronizing of input yuv data and metadata(output of tidl) . Please 1st check with ti provided model files and check whether are you getting the proper values or not. Regards, Anuj

Hi, I have changed the origal TIDL configuration file as following: TIDL Configuration parameters ----------------------------- inputWidth=768 inputHeight=320 inputFile=inData_OD inputHDRFile=inHeader_OD netFileName=tidl_net_jdetNet_ssd.bin paramFileName=tidl_param_jdetNet_ssd.bin fps=10 (fps = 30 changed) threshold=0.3 I guess if the change of fps cause the detected results does not match the response frame？ Is there any bug about printing the detected result ？

Anybody who can help me？

Hi, Is the detections working with standalone TIDL application?

Since we haven't heard back, we hope you could find solution. Closing the thread.

Part Number: TDA2 Tool/software: TI-RTOS Dears, I see the data flow of File Input/Output TI Deep Learning (TIDL) use case on TDA2XX Did you have the data flow of TIDL Object detect use case on TDA2XX ? thanks for the reply. Allen

Hello , Data Flow for the TIDL Object Detect is not documented in datasheet , Its data flow can be obtained in the usecase folder , vision_sdk\apps\src\rtos\usecases\tidl_OD\chains_tidlOD.jpg Regards Chetan.M

Hi OK, I see the pic. but it should be contained Lane Departure warning (LDW)、Vehicle Detection (VD)、Pedestrian, Bi-cyclist and Powered Two Wheeler Detection etc... Does't it? but I doesn't see them in the flow. Can you tell me where they going?

It is trained for Pedestrians also. Regards, Kumar.D

so, TIDL algorithm can classify the road ,Right? But TIDL_OD use case does't contain Lane Departure warning (LDW) I'm right ?

The default usecase doesn't Regards Chetan.M

Ticket Name: TDA2: TDA2x SD BOOT :

Part Number: TDA2 How does the video display and ALG_TIDL run asynchronously? Meaning is, the video real-time display frame rate of 25, ALG_TIDL can not be real-time frame rate of about 10.

Hi, Please press p after 2 min of running your usecase. You will get all links statistics. Regards, Anuj

Hi, Anuj Gupta You may not understand what I mean, I want the display and algorithm to be time-sharing. I don't know how to achieve it. Thanks! Mary

Hi, Can you please elaborate what you want to know. video display and ALG_TIDL are running synchronously. Means the output of ALG_TIDL will go to video display. If ALG_TIDL is running at 5 fps the video display will be running also at 5 fps. Regards, Anuj

Hi, Anuj Now the usecase run is synchronous, just like you said “video display and ALG_TIDL are running synchronously”.But I want to implement asynchronous, that is, the display of the video is not synchronized with TIDL. The video display runs separately and TIDL runs alone. Thanks! Mary

Hi, Running them asynchronous is not possible as the links are interlinked to each other i.e. the output of 1 link is connected to the input of other link. If ALG_TIDL will not give output at suppose 30 fps the display will not get data at 30 FPS so display will not be able to run at that speed. Regards, Anuj

Hi, Anuj Whether the results can be output through global variables, the result of multi-frame TIDL may be the same. That is, TIDLlink is not connected to the display link. The output of TIDL simply changes the value of a global variable. I tried it and it seems that it is not feasible. Thanks! Mary

Hi, UInt32 frameSkipMask = 0x24924924; // 20 fps Frame skipping is to skip the frame when it is displayed, or to skip the frame when it is captured.Can you tell me how to use this parameter(frameSkipMask )? Thanks! Mary

Hi, frameSkipMask is to skip the frame while capturing /**< * Frame Skip Mask (bit0..bit29) bitN = 1 Skip frame, * bitN = 0 DO NOT skip frame * Example, 0x0 for no frame skip, 0x2AAAAAAA for skipping * alternate frames. Regards, Anuj

Hi, Thank you for your answer！ Mary

Hi, If it answers your question then please close the thread. Regards, Anuj

Ticket Name: TIDEP-01017: About DSP1 memory allocation issue

Part Number: TIDEP-01017 Hi I modify the sample code of Cascade MIMO object detection of radar sdk 3.8. And I want to use MUSIC algorithm to calculation the angle of object on DSP1. Then I need to allocate memory to use SVD. The size of input data matrix of SVD is 86 * 86, and the data type is complex. I try to use "Utils_memAlloc" to allocate memory on UTILS_HEAPID_L2_LOCAL, but it failed. Can you give me some advice? Thanks. Morris

Hi, please try with this "UTILS_HEAPID_DDR_CACHED_SR" Thanks Gaviraju

Ticket Name: TDA2: Cascade Radar Host Processor Board to 20 channels

Part Number: TDA2 Other Parts Discussed in Thread: AWR1243 Cascade Radar Host Processor Board PROC055 with TDA2 mates with the AWR1243 PROC054 and has 4 chips with 4 channels each so 16 channels. We need to add another AWR1243 so we have 20 channels. In this case we will need to add a 5th FPGA to get the VIP frame for the TDA2. On the TDA2 ports VIP5 and VIP6 are only 16 bits wide not the 24 bits wide of VIP1, VIP2, VIP3 and VIP4. How should be proceed to enable 5 AWR1243 chips radar channels per TDA2?

Hi Zach, We are currently using only 16 bits in the current SDK for capturing the data on the TDA to capture each of the 4 AWR1243 data. You can use the same for the 5th AWR. BTW the software which supports cascade board is available in www.ti.com/.../processor-sdk-tdax for reference. Thanks and Regards, Piyali

Hi Piyali, If we will use 16 bit mode as you indicated here, is it the MSB 16 bits for the 24 bits for the LSB 16 bits needed? Thank you, Zach

Hi Zach, Lower 16 bits (15:0). Thanks and Regards, Piyali

Ticket Name: Linux/TDA2: Two Encoder Link For video Saving

Part Number: TDA2 Tool/software: Linux Hi Every one, I am working on a use case that could save video on SD card in TDA2xx. For that I am using Two Encode link. I have created the usecase as below :- Capture -> VPE -> Dup_vpe -> SgxFrmcpy (A15) ->Dup_sgx Dup_vpe -> Encode_vpe -> Null_vpe (A15) Dup_sgx -> DssM2mWb - > Encode_sgx -> Null_sgx (A15) Dup_sgx -> Display_M4 (IPU1_0) GrpxSrc -> Display_Grpx while compiling , it show an error : 'SYSTEM_LINK_ID_VENC_1' undeclared 1) How can i solve this problem ? 2) Can i define SYSTEM_LINK_ID_VENC_1 and how ? Regards, Renjith

Hi, You can use only 1 instance of encoder link. Multiple instances are not supported for encoder link. Regards, Anuj

Hi Anuj, Thank you for your reply.. Is there any other option for this ? Can i use one Encoder link instead of using two ? How its possible ?

Hi, Please modify usecase as below Capture -> VPE -> Dup_vpe -> SgxFrmcpy (A15) ->Dup_sgx Dup_vpe -> Merge Dup_sgx -> DssM2mWb - > Merge Merge -> Encode -> Select -> Null_vpe (A15) Select -> Null_sgx (A15) Dup_sgx -> Display_M4 (IPU1_0) GrpxSrc -> Display_Grpx Regards, Anuj

Hi Anuj, 1) By using this usecase can i save both videos at the same time ? 2) How to configure the 'Select' ?

Hi, Please take reference of the usecase where select link is used. Regards, Anuj

Hi Anuj, Sorry for the late reply, While running i got this error Assertion @ Line: 700 in iva_enc/encLink_common.c: 0 : failed !!!

Hi, Have you set pLinkChPrm->format params? Please take a reference of encoder link params from the below usecase file. vision_sdk\apps\src\rtos\usecases\vip_single_cam_view_encdec\chains_vipSingleCam_EncDec_Display.c Regards, Anuj

Ticket Name: RTOS/TDA2: Vision SDK 3.03 DDR test resets the board

Part Number: TDA2 Tool/software: TI-RTOS Hello all, When I run Vision SDK 3.03 PDK example for DDR test on TDA2px board, and when test gets to particular address on EMIF1 (0x9BFF1000) or EMIF2 (0xBDFF1000), it restarts the board and starts executing the test again. When I run DDR test example from Vision SDK 2.12. it executes with no problems. Do you maybe know why that happens, is there a problem with SBL or with the test? Best regards, Bosko

Hi, This looks like a watchdog timer reset. Can you check if watchdog timer is disabled. Regards, Rishabh

Ticket Name: CCS/TDA2EVM5777: CCS/TDAEVM577 suspend/ wakeup

Part Number: TDA2EVM5777 Tool/software: Code Composer Studio Hi export: My production is base on battery power. I had see the https://e2e.ti.com/support/processors/f/791/t/682517?TDA2-Power-management-LPM-standby-and-wakeup-support-for-TDA2XX docutment, But I am not clear to merge the code into my code. Could you more clear to implement the function. I am use PROCESSOR_SDK_VISION_03_08_00_00/vision_sdk. Thanks, Jemy

Jemy, CPU Idle is enabled by default in Vision SDK. In the idle task, CPU clock will be idled. This is power management provided in Vision SDK. Regards, Stanley

Stanley: I can not find how to into suspend & wakeup programing point. Could more detail for this. prefer have a same code. Thanks,

We don't have the support for suspend / wakeup in PM SW in Vision SDK. The lowest power state we support is CPU idle. For CPU idle, you can refer to ~/ti_components/drivers/pdk_xx_xx_xx/packages/ti/drv/pm/examples/cpuidle. Regards, Stanley

Ticket Name: Linux/TDA2: error: #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h

Part Number: TDA2 Tool/software: Linux /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/ti_components/os_tools/linux/linaro/gcc-linaro-5.4.1-2017.05-x86_64_arm-linux-gnueabihf/lib/gcc/arm-linux-gnueabihf/5.4.1/include/arm_neon.h:31:2: error: #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h this is my option CC_OPTS=-c -Wall -Warray-bounds -fPIC -pie -fPIE -march=armv7-a -mcpu=cortex-a15 -mfloat-abi=hard -mfpu=neon-vfpv4 how to solve this problem

Hi Shuai, As mentioned in the below e2e.ti.com/.../698674 Please look for compiler support As the required flags are passed to the compiler for SDK Regards Chetan.M

Hi Chetan.M ok thanks! shuai

Ticket Name: PROCESSOR-SDK-DRA7X: 4ch mix in/BT.1120 16bit to VIP Capture

Part Number: PROCESSOR-SDK-DRA7X Other Parts Discussed in Thread: TDA2 Dear Sir, I have a 4 Channel video sensor input to one video decoder. This decoder will output one channel YUV422 BT.1120 16bit 74.25MHz to VIP captuer in TDA2. use line mixed method I need to confirm this kind application had verified, and the performace is fine. And, please let me know how to cahnge the VIP setting on PROCESSOR_SDK_VISION_03_05_00_00. Are these parameter coorrect? SYSTEM_VIFM_MCH_LINE_MUX_ES SYSTEM_VIFW_16BIT Thanks!

Hi Chen, Any specific reason for using line mux mode? You could connect multiple input to different input port. Rgds, Brijesh

Hi, Becasue the source is form MIPI, so only line mux mode. Why do you suggest to connect multiple input to different input port?

But which device is converting from MIPI to parallel output? Rgds, Brijesh

Hi, we use FPGA to convert MIPI to BT.1120x1

Hi, Can you use pixel mux mode? Regards, Rishabh

Hi, Can it output to multiple output ports? Regards, Brijesh

Hi, Firstly, please let me know why can't use line mux mode, then tell me the better solution.

Hi Chen, Line mux mode is not really recommended.. The other option is to use pixel mux mode. Is it possible to get the output in pixel mux mode? Regards, Brijesh

Hi, We refer the doc - TDA2x_Tech_Reference_Manual http://www.ti.com/lit/ug/sprui29f/sprui29f.pdf In 9.4.5.8.4 Line Multiplexing, there is descibed the Line Mux mode is supported. It's impossible to change to pixel mux mode on current board schematic design. Please confirm line mux mode is verified, and performance is fine. We only use pixel mux mode in mass production, so this information is verry important for us.

Hi Chen, Line mux is not much tested. I am not sure there could be challenges in bringing up line mux mode.. Since you are already considering pixel mux mode for mass production, why dont you use it for the bringup also? Rgds, Brijesh

Hi Chen, Current driver does not support line mux so please use pixel mux as suggested previously. Regards, Rishabh

Hi, Thanks for your comment.

Ticket Name: Linux/TDA2SX: About the TDA2 memory adjustment on Dual OS (Linux & RTOS)

Part Number: TDA2SX Tool/software: Linux Our system does not have enough shared memory to do more algorithm, So we want to adjust the memory block position & size for increasing the SR1 size. After reading the URL http://processors.wiki.ti.com/index.php/VSDK/VisionSDK_UserGuide_MemoryMap#Memory_Map_of_the_Application, our adjustments are still fail. Even we only move the IPU1 & IPU2 position & size. ( not out of 0xA0000000 ) Could you help us ? Thank you very much. Regards, Eten

Hi Eten, If you don't intend M4 to perform a CPU access and all operations happen using DMA, you can add a carveout between 0xA0000000 - 0xC0000000 and use this as shared memory (refer the dra7-evm-infoadas.dts in kernel on how to add a reserved memory node). You then need to add the corresponding entry OSA_memInit to mmap this reserved region to userspace. Regards Shravan

Ticket Name: TDA2: Classification model on TDA2X

Part Number: TDA2 Hi, I am trying to run the classification model using object detection usecase. I replaced the NET_OD.BIN and PRM_OD.BIN with classification network and parameter. Based on the classification output from the model, I will change the position of box being drawn on the image. I am getting the pointer to the output of softmax buffer on ObjectDrawPlugin as follows: metaDataAddr = pCompositeBuffer->bufAddr[0][1]; //ChId 0 contains the image. bufferOffset = ((44+8)*4) + 4; // Due to the padding of 4 on the borders classPtr = ((UInt8 *)((char *)metaDataAddr)) + bufferOffset; But the classid I'm getting is not proper. How to get the classification output at the next layer? When I tried to run the model using TIDL FILE IO Usecase it dumped 2304 bytes instead of 44bytes(44 class model). Regards, Navinprashath.R.R

Hi, Are you getting proper Classid in the standalone setup? If not first we will try to fix this issue in the standalone. Thanks, Praveen

Hi Praveen, I was able to run in the standalone mode in TIDL and the output dumped was proper. I am getting correct classid and only 44 bytes have been dumped. Regards, Navinprashath.R.R

Hi Navinprashath, If you are getting proper output on standalone and not in VSDK, then I need to check this issue with VSDK team. Meanwhile can you check if you can see these 44 bytes of proper output anywhere in the VSDK dumped 2304 bytes. Thanks, Praveen

Hi Praveen, I am able to resolve the issue in TIDL OD usecase. It seems to be a buffer handling issue from my side. I will check in TIDL FILE I/O usecase once again and update here. Regards, Navinprashath.R.R

Ticket Name: RTOS/TDA2: VIP, Monochrome Sensor Capture and Display

Part Number: TDA2 Tool/software: TI-RTOS Dear Champs, My customer is developing DMS (driver monitoring system) on TDA2x. A monochrome sensor will be used for this application. The output format of this sensor is 12-bit raw (luma-only) with discrete sync. 1. My customer did below settings on VIP to capture the output. Could you help check if the setting can work or not? SDK: PPROCESSOR_SDK_VISION_03_04_00_00. File: \vision_sdk\apps\src\rtos\usecases\common\chains_common_vision.c Original:

	pInstPrm->videoIfMode   =   SYSTEM_VIFM_SCH_DS_HSYNC_VSYNC;
	pInstPrm->videoIfWidth  =   SYSTEM_VIFW_8BIT;
	pInstPrm->bufCaptMode   =   SYSTEM_CAPT_BCM_FRM_DROP;
	pInstPrm->numStream     =   1;
	
	pInprms->width      =   captureInWidth;
	pInprms->height     =   captureInHeight;
	pInprms->dataFormat =   SYSTEM_DF_YUV422P;
	pInprms->scanFormat =   SYSTEM_SF_PROGRESSIVE;
	
	pOutprms->width         =   captureOutWidth;
	pOutprms->height        =   captureOutHeight;
	pOutprms->dataFormat    =   SYSTEM_DF_YUV420SP_UV;
	pOutprms->maxWidth      =   pOutprms->width;
	pOutprms->maxHeight     =   pOutprms->height;
	
	pPortCfg->syncType          =   SYSTEM_VIP_SYNC_TYPE_DIS_SINGLE_YUV;
	pPortCfg->ancCropEnable     =   FALSE;
	pPortCfg->intfCfg.clipActive    =   FALSE;
	pPortCfg->intfCfg.clipBlank     =   FALSE;
	pPortCfg->intfCfg.intfWidth     =   SYSTEM_VIFW_16BIT;

Modified:

	pInstPrm->videoIfWidth  =   SYSTEM_VIFW_12BIT; // modified for 12-bit
	
	pInprms->dataFormat =   SYSTEM_DF_RAW12; // modified for 12-bit RAW
	
	pOutprms->dataFormat    =   SYSTEM_DF_RAW12; //modified to prevent VIP from processing data
	
	pPortCfg->syncType          =   SYSTEM_VIP_SYNC_TYPE_DIS_SINGLE_YUV; // should this be changed too?
	pPortCfg->intfCfg.intfWidth     =   SYSTEM_VIFW_16BIT; // should this be changed too?

 I attached original and modified files for your convenience to compare. chains_common_vision.zip 2. The captured 12-bit raw data will not only be proceed in DSP but also be sent to Display. Unfortunately the display controller supports only RGB or YUV input. Is there any hardware (like VPE) can be used to convert 12-bit raw to YUV/RGB? Thanks.

The VIP natively doesn't support 12-bit capture. Kindly configure VIP for 16-bit capture. In this case the upper 4-bit MSB will be set to zero in the buffer. Kindly use below settings. Also there is no other HW block in the system that can convert 12-bit to 16-bit or 8-bit         pInstPrm->videoIfMode   =   SYSTEM_VIFM_SCH_DS_HSYNC_VSYNC;
	pInstPrm->videoIfWidth  =   SYSTEM_VIFW_16BIT; 	pInstPrm->bufCaptMode   =   SYSTEM_CAPT_BCM_FRM_DROP;
	
	pInprms->dataFormat =   SYSTEM_DF_RAW16;
	
	pOutprms->dataFormat    =   SYSTEM_DF_RAW16; 
	
	pPortCfg->syncType          =   SYSTEM_VIP_SYNC_TYPE_DIS_SINGLE_YUV; 

Ticket Name: TDA2: network speed problem

Part Number: TDA2 HI， i am using tda2x/PROCESSOR_SDK_VISION_03_06_00_00.After install and build,starting run the usecase--"1CH VIP Capture + Network TX". oh,my evm board ip address is static --192.168.1.200,and pc side is 192.168.1.201.And network cable was connected to EVM board side P5 port. And then,running the command in windows cmd terminal. "network_rx --ipaddr --target_ip 192.168.1.200 --host_ip 192.168.1.201 --port 29172 -usetfdtp --files 20190214_001.yuv" my problem is the speed of network.Less than 1280*720 30fps.just about 10fps. How to improve the speed of network?thank you.

Hi @user3792633 , from VisionSDK_UserGuide_NetworkTools.pdf: IMPORTANT NOTE: When sending RAW/YUV frames When NDK runs on M4 CPU, one can achieve a data rate of about 2 MB/s (16Mbps) When NDK runs on A15 CPU (TDA2x or TDA2px), one can achieve a data rate of about 60 MB/s (480Mbps) Can you make sure NDK runs on A15 core? You should have NDK_PROC_TO_USE=a15_0 in the build config you use. Regards, Yordan

hi Yordan, I am sure Ndk runs on A15 core now.Here have two pics about config. Jer

Hi, While the transmission is going on, please check your network speed in system monitor. To match your requirement, approximately 422 Mbps network speed is required. This is theoretically possible, but this can depend on your network bandwidth. But since you are using static IP, and you're connected to the PC directly from the EVM, I wonder what could go wrong. Please let me know if the network speed you observe is sufficient for the required data transfer. Meanwhile I'll try to replicate this on my side. Regards, Anand

Hi Anand, Network speed is 64Mbps when the usecase in running.Not able to achieve 422Mbps. Jer.

Hi Anand, Do you have any update about this issue? Regards, Jeremy

Hi Jeremy, I suspect that you won't be getting the desired FPS since you're working with raw data. You can try with encoding and see if you're getting the desired FPS. Since you're using static IP, network speed issues shouldn't come up. Just to get a closure on that, please check the UART console log of vision sdk and see if your connection is 1000Mbps. Regards, Anand

Ticket Name: TDA2EXEVM: TDA2 DSP2 XDC ASSERT

Part Number: TDA2EXEVM Other Parts Discussed in Thread: SYSBIOS We run our algorithm on DSP2. Sometimes DSP2 will have XDC Assert message and then DSP2 will crash. How can we solve it? Log: [DSP2 ] 11173.232111 s: ### XDC ASSERT - ERROR CALLBACK START ### [DSP2 ] 11173.232141 s: [DSP2 ] 11173.232202 s: assertion failure: A_badContext: bad calling context. See GateMutex API doc for details. [DSP2 ] 11173.232233 s: [DSP2 ] 11173.232233 s: ### XDC ASSERT - ERROR CALLBACK END ###

Have any update?

Hi, Please refer to BIOS API doc for GateMutex. Or, you can find the source under ~/bios_6_46_06_00/packages/ti/sysbios/gates/GateMutex.c. You are hitting the below error where GateMutex_enter() is called in HWI or SWI context. /*
 *  ======== GateMutex_enter ========
 *  Returns FIRST_ENTER when it gets the gate, returns NESTED_ENTER
 *  on nested calls.
 *
 *  During startup, Task_self returns NULL.  So all calls to the 
 *  GateMutex_enter look like it is a nested call, so nothing done.
 *  Then the leave's will do nothing either. 
 */
IArg GateMutex_enter(GateMutex_Object *obj)
{
    Semaphore_Handle sem;

    /* make sure we're not calling from Hwi or Swi context */
    Assert_isTrue(((BIOS_getThreadType() == BIOS_ThreadType_Task) ||
                   (BIOS_getThreadType() == BIOS_ThreadType_Main)),
                   GateMutex_A_badContext);

    if (obj->owner != Task_self()) {
        sem = GateMutex_Instance_State_sem(obj);
        Semaphore_pend(sem, BIOS_WAIT_FOREVER);

        obj->owner = Task_self();

        return (FIRST_ENTER);
    }

    return (NESTED_ENTER);
} Regards, Stanley

Ticket Name: Linux/TDA2: LCD output cannot display in vdrm usecase.

Part Number: TDA2 Tool/software: Linux Hi , TI experter, I've used vision SDK 3.04.00, and I used the customed lcd display output via lcd1. I want to add custom lcd driver for vdrm usecase instead of default HDMI output. Can u suggest? Best regards, John

Hi John, Which LCD you use: is it 1280x800 LG LCD or 1920x1200 LCD? Vision SDK supports only 1280x800 LG LCD: e2e.ti.com/.../2656901 You can also check if you can find something useful in this wiki: processors.wiki.ti.com/.../Virtual_DRM_:_An_User_Guide_for_Developing_Usecases Regards, Yordan

Hi ,Yordan thx for reply. I used a custom LCD module. The Virtual DRM wiki is about HDMI output.I check it. and I have a question, if I add a new drivers for dispc output. should I change the crtc port num? (now is 26.) or add something to vdrm0 in dra7.dtsi? best regards, John

Hi John, I have pinged DSS expert to provide further help. Regards, Yordan

Hi , Yordan Vision SDK supports only 1280x800 LG LCD: e2e.ti.com/.../2656901 I check it ,and had tried it. my custom LCD output is 1920x720. So I had to add new drivers for it. and refer to suggest " You can find the code to enable 1920x1200 in /drivers/gpu/drm/omapdrm/dss/(panel-dpi.c, encoder-tc358768.c) and use it as reference" ? Right ? Regards, John

In vDRM setup, the DSS drivers run in IPU. SO you will need to add your custom LCD parameters in IPU. No change in linux kernel is required. DT should be changed to address the new resolution. No change is needed in CRTC IDs etc

Ticket Name: Linux/TDA2: CONFIG_ARM_LPAE=n

Part Number: TDA2 Tool/software: Linux am using tda2x evm i use this chain test my cnn (SDK_VISION_03_04_00_00\vision_sdk\sample_app\src\hlos\usecases\nullSrc_display) i add CONFIG_ARM_LPAE=n in auto.cfg ,make clean then make linux make linux_install make -s -j depend make -s -j but when i restar the EVM have some problem follow is the log 2.777440] VFS: Mounted root (ext4 filesystem) on device 179:50. [ 2.788399] devtmpfs: mounted [ 2.791566] Freeing unused kernel memory: 340K [ 2.796027] This architecture does not have kernel memory protection. /sbin/init: error while loading shared libraries: /usr/lib/libkmod.so.2: file too short [ 2.877469] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00007f00 [ 2.877469] [ 2.886647] CPU0: stopping [ 2.889368] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.4.84-00027-g018eb62-dirty #10 [ 2.897230] Hardware name: Generic DRA74X (Flattened Device Tree) [ 2.903348] Backtrace: [ 2.905827] [<c0013114>] (dump_backtrace) from [<c0013310>] (show_stack+0x18/0x1c) [ 2.913428] r7:c0931ef0 r6:20000193 r5:00000000 r4:c094f810 [ 2.919149] [<c00132f8>] (show_stack) from [<c02b2028>] (dump_stack+0x8c/0xa0) [ 2.926406] [<c02b1f9c>] (dump_stack) from [<c0016460>] (handle_IPI+0x184/0x198) [ 2.933829] r7:c0931ef0 r6:00000000 r5:00000000 r4:c092c424 [ 2.939545] [<c00162dc>] (handle_IPI) from [<c00094c4>] (gic_handle_irq+0x78/0x7c) [ 2.947143] r7:fa212000 r6:c0931ef0 r5:fa21200c r4:c09328ec [ 2.952857] [<c000944c>] (gic_handle_irq) from [<c0013e00>] (__irq_svc+0x40/0x74) [ 2.960370] Exception stack(0xc0931ef0 to 0xc0931f38) [ 2.965442] 1ee0: 00000001 00000000 fe600000 00000000 [ 2.973655] 1f00: c0930000 c0686294 00000000 c081eb3c 00000000 c0931f60 c093250c c0931f4c [ 2.981867] 1f20: c0931f2c c0931f40 c0027f6c c0010540 60000013 ffffffff [ 2.988504] r9:c0931f60 r8:00000000 r7:c0931f24 r6:ffffffff r5:60000013 r4:c0010540 [ 2.996327] [<c0010518>] (arch_cpu_idle) from [<c00713b8>] (default_idle_call+0x28/0x34) [ 3.004454] [<c0071390>] (default_idle_call) from [<c0071620>] (cpu_startup_entry+0x208/0x264) [ 3.013107] [<c0071418>] (cpu_startup_entry) from [<c067d520>] (rest_init+0x90/0x94) [ 3.020878] r7:00000000 [ 3.023433] [<c067d490>] (rest_init) from [<c08dbd88>] (start_kernel+0x400/0x40c) [ 3.030944] r5:c0982000 r4:c0982040 [ 3.034550] [<c08db988>] (start_kernel) from [<80008090>] (0x80008090) [ 3.041110] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00007f00 [ 3.041110] Regards Shuai

Hi Shuai, can you check the file /usr/lib/libkmod.so.2 on the rootfs? It is probably a symlink to a file which might be missing or corrupt. can you try to recreate the SD card following the Linux userguide and confirm it was created without errors. Regards, Yordan

Ticket Name: Linux/TDA2EVM5777: How to enable 4 channels in NullSource link?

Part Number: TDA2EVM5777 Tool/software: Linux I want NullSource link to output 4 channels video frames, who can tell me how to do it?

Hi, can you try to change the value of NULL_SRC_LINK_NUM_CHANNELS_DEFAULT in vision_sdk/links_fw/include/link_api/nullSrcLink.h Regards, Yordan

/* * Validating the create params * TODO: Extend to validate width, height and pitch params also */ /* Only one channel is supported as of now */ OSA_assert(pPrm->outQueInfo.numCh == 1U); OSA_assert(pPrm->timerPeriodMilliSecs != 0); /* No support for Network RX Mode */ OSA_assert(pPrm->dataRxMode == NULLSRC_LINK_DATA_RX_MODE_FILE); it can't work. thanks.

Hi, if you use Linux on A15, core, than you can remove this assert and it should work, please check this thread: e2e.ti.com/.../2650316 Regards, Yordan

Ticket Name: Linux/TDA2: HOW us vision_sdk\links_fw\src\rtos\links_common\nullSrc

Part Number: TDA2 Tool/software: Linux i have run this case (vision_sdk\apps\src\hlos\adas\src\usecases\null_src_decode_display ) successul ! this case have 6 links pObj->NullSourceLinkID = A15_0_LINK (SYSTEM_LINK_ID_NULL_SRC_0); pObj->IPCOut_A15_0_IPU1_0_0LinkID = A15_0_LINK (SYSTEM_LINK_ID_IPC_OUT_0); pObj->IPCIn_IPU1_0_A15_0_0LinkID = IPU1_0_LINK (SYSTEM_LINK_ID_IPC_IN_0); pObj->DecodeLinkID = SYSTEM_LINK_ID_VDEC_0; pObj->VPELinkID = SYSTEM_LINK_ID_VPE_0; pObj->DisplayLinkID = SYSTEM_LINK_ID_DISPLAY_0; A15_0_LINK (SYSTEM_LINK_ID_NULL_SRC_0); is use this (vision_sdk\links_fw\src\hlos\links_a15\nullSrc) link i found in vision_sdk\links_fw\src\rtos\links_common\nullSrc is also a nullSrc link , can i use this nullsrc_link replace？

Hi Shuai, You can use the null src of the core where you are running the null src link. If you are reading from the file then it has to be in hlos only as file system is controlled by hlos, If you are running bios then it can be either A15 or M4 , depending you need to change the cfg file. vision_sdk\apps\configs\<sellected cfg> Regards Chetan.M

Hi Chetan.M i want to run null src link on M4 I am use LINUX system by hlos . BESTWISHES shuai

shuai when you run Linux on A15, both SD card and network will be controlled from A15 linux, so the NullSRc on M4 can not access these devices. regards, Shiju

Ticket Name: Compiler/TDA2SG: how XDS110 connect to jtag

Part Number: TDA2SG Tool/software: TI C/C++ Compiler hi, i use CCS7 & xds110 and try to debug tda2s , but not success 。 How can I connect the pin。

Hi Zhangsc, can you check if this guide can give you something useful: Regards, Yordan

Ticket Name: TDA2EG-17: GPU to support "Frame Sequential 3D"?

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2 Hi Champs: Customer is using the TI TDA2 products for MP now. They are asking the "Frame Sequential 3D" feature from their end customer. Please see this : https://www.youtube.com/watch?v=5jv0HbhCuXI We have 2 questions: 1. How to use QT 3D studio to output the “Frame 3D Sequential” to the LCD output by using TDA2 GPU?? Any 3rd party or TI Document to address this support need? 2. Does our TDA2 EG parts supporting the 3D sequential output format? Please comment, thanks. BR Rio

Hi Rio, From the video link it appears that the left-right sequential content once generated are consumed by two displays (alternate frames going to each display). If the GPU is programmed to generate the alternate content it should be able to and this appears to be more of implementation details. Is there something specific that is needed here like support for an extension, specific format or etc. Thanks, Gowtham

Hi Gowtham: The customer is willing to have this: https://www.youtube.com/watch?v=wZZ-KfNFG-I Does our TDA2 product is able to do this? If yes, how to implement? BR Rio

https://github.com/dvdhrm/docs/blob/master/drm-howto/modeset-double-buffered.c hi Gowtham: please review the DRM on the above link. Customer can ser this buffer (dev->bufs[0]) as the left frame. And set this buffer: dev->bufs[1] as the right right frame Thus, they are capable to make a 3D Side by Side. Now, they want to have a 3D sequential frame (that mean: L/R frame will be viewed as a full screen. How to modify this code snippet as a 3D sequential frame? BR Rio

Hi Rio, The mentioned buffers are ping-pong buffers used for display - one buffer is on the display and the other is used to ready the next frame and these roles keeps switching on every vsync. Here as there are two buffers for one frame, they would need four buffers to achieve ping-pong. Aside from above, the bulk of the changes needs to happen on the display side on how these left and right frames are submitted to the 3D display. What kind of display are they using and is this panel support been integrated to the driver. Thanks, Gowtham

Ticket Name: TDA2: Multiple outputs display in single frame

Part Number: TDA2 Hi, I have different vision algorithms(kernels) running on different EVE cores. Is it possible to display the output of each on a single display simultaneously in a single frame? Will the merge link work in this case? Also, is there any example available for this? Regards, Shruti

Hi Shruti Yes, this is possible with vision SDK. Connect all Alg links (of different kernels) output to a merge link and then connect to a Display. If all these alg links output video frames, then you can directly display them with display link. But if these Alg links output some meta data, then a draw link which create the necessary overly can be fed to display links please refer below demos \vision_sdk\apps\src\rtos\usecases\tidl_OD \vision_sdk\apps\src\rtos\usecases\vip_single_cam_dense_optical_flow regards, Shiju

Thank you for the clarification Shiju. Regards, Shruti

Hello Shiju, I and Shruti working together. I have following query, If all these alg links output video frames, then you can directly display them with display link. >> We have output as video frames, but Merge link output with System_VideoFrameCompositeBuffer buffer type. Then how can we directly display them ?? As Display link support video frames. Regards, Kajal

Hi Kajal Merge link output is System_Buffer, payload of this can be either System_VideoFrameCompositeBuffer or System_VideoFrameBuffer. If its System_VideoFrameCompositeBuffer, then just add this support in Display Link, its just getting the actual buffer pointer from System_VideoFrameCompositeBuffer. Only Sync link output System_VideoFrameCompositeBuffer format and if you do not have Sync Link in the data path, I assume your merge link output would be System_VideoFrameBuffer regards, Shiju

Hello Shiju, Thank you for the information. I had idea about merge link output is System_Buffer but display link only supports System_VideoFrameBuffer type, that's why queried! We have to use sync link, so output will be System_VideoFrameCompositeBuffer type, will try to add this support in display link. Regards, Kajal

Ticket Name: TDA2SX: RadarSDK Usecase modifying to use other cores

Part Number: TDA2SX Hi Experts, I am trying to figure out the processing flow of usecase below "radar_read_objectdetect_write" in Processor-SDK-Radar 3.6. I assume that each Alg_RadarProcess_fft / Alg_RadarProcess_pkDetects / Alg_RadarProcess_BeamForms uses WorkQ mechanism and all the 3 Work Threads run on EVE. Q1) How should I find out if the Alg_RadarProcess_xx uses WorkQ mechanism or not ? Do we need to check source code directly ? Q2) When we need to change the Host Thread of those to IPU1_0, is it possible ? (case-1) Q3) If Q2 can be done, is it possible to change the part of Work Thread to DSP1 ? (case-2) original: NullSource Alg_RadarProcess_fft (A15) -->[WorkQ]--> fft (EVE1) Alg_RadarProcess_pkDetect -->[WorkQ]--> peak_detect (EVE1) Alg_RadarProcess_beamForm (DSP1) -->[WorkQ]--> beam_forming (EVE1) Dup_0 (DSP1) Null case-1: NullSource Alg_RadarProcess_fft (IPU1_0) -->[WorkQ]--> fft (EVE1) Alg_RadarProcess_pkDetect (IPU1_0) -->[WorkQ]--> peak_detect (EVE1) Alg_RadarProcess_beamForm (IPU1_0) -->[WorkQ]--> beam_forming (EVE1) Dup_0 (IPU1_0) Null case-2: NullSource Alg_RadarProcess_fft (IPU1_0) -->[WorkQ]--> fft (EVE1) Alg_RadarProcess_pkDetect (IPU1_0) -->[WorkQ]--> peak_detect (DSP1) Alg_RadarProcess_beamForm (IPU1_0) -->[WorkQ]--> beam_forming (DSP1) Dup_0 (IPU1_0) Null Best regards, Saito

Hi, Q1) How should I find out if the Alg_RadarProcess_xx uses WorkQ mechanism or not ? Do we need to check source code directly ? Source code is available with SDK, you can find it in below location vision_sdk\apps\src\rtos\radar\src\alg_plugins\alg_fxns Q2) When we need to change the Host Thread of those to IPU1_0, is it possible ? (case-1) In the above path for each link you will find SRC_FILES.MK file. Inside that you can check for which all core you can run this. Q3) If Q2 can be done, is it possible to change the part of Work Thread to DSP1 ? (case-2) This will not be possible. Regards, Anuj

Hi Anuj, Thanks for the prompt rely. > Q3) If Q2 can be done, is it possible to change the part of Work Thread to DSP1 ? (case-2) > > This will not be possible. Why is the case-2 not possible ? Because peak_detect & beam_forming for DSP is not availabe or any other reason ? So let me ask further questions to clarify. Q4) Can we add frameCopy to IPU1_0 (Host thread) and to EVE1 (Work thread) as below ? (case-3) case-3: NullSource Alg_RadarProcess_fft (IPU1_0) -->[WorkQ]--> fft (EVE1) Alg_RadarProcess_pkDetect (IPU1_0) -->[WorkQ]--> peak_detect (EVE1) Alg_RadarProcess_beamForm (IPU1_0) -->[WorkQ]--> beam_forming (EVE1) Alg_RadarProcess_frameCopy (IPU1_0) -->[WorkQ]--> frame_copy (EVE1) Dup_0 (IPU1_0) Null Q5) In the original data flow for beam forming below, after DSP1 dispatches to EVE Work thread in Alg_RadarProcess_beamform, DSP1 needs to wait until Work thread beam_forming finishes with poling mechanism. Is my understanding correct ? Alg_RadarProcess_beamForm (DSP1) -->[WorkQ]--> beam_forming (EVE1) Best regards, Saito

Hi, Basically you can not build a part of a link in1 core and other part in other core. Entire link is work as a single module and it should be build for a single core. If you want a part of any link to run on any other core then create a separate link in that core and implement your workQ in that link. Regards, Anuj

Hi, Its been very long since any update on this thread. I hope the issue is resolved. if not then please reply below or create a new thread for different issue. Regards, Anuj

Hi, Apologies being long time. I would like to confirm your explanation.. Is the Case-3 possible ? Host threads are moved to IPU1_0 and Alg_RadarProcess_framecopy is just added. framecopy is doing after beamForm. Thanks. Best regards, Saito

Hi, For case 3 can you tell us which all link you want to run on which cores. Remember Host thread and work thread of a same link can not be in the different core. If you have different link then you can run that on different cores provided that core supports that link requirement. Regards, Anuj

Hi, Case-3 is similar to chains_radarobjectnull usecase in Radar SDK. (.\vision_sdk\apps\src\rtos\radar\src\usecases\radar_objectdetect_null) The difference from the chains_radarobjectnull usecase above are: - Host thread runs on IPU1_0, instead of DSP. - Alg_RadarProces_frameCopy is inserted after Alg_RadarProcess_beamForm. Best regards, Saito

Hi, Please follow below userguide. Apologies for the delayed response vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_WorkQ.pdf Regards, Anuj

Ticket Name: RTOS/TDA2PXEVM: Not able to compile Network tool which is provided with SDK

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hello Experts, I wanted to use the network tool provided by latest SDK. network tool is not getting compiled I have updated the RUELS.MK and COMMON_HEADER.MK file with appropriate toolchain path But still network tool is not compiling Below are the errors I am getting workspace/SDK_VISION_03_06_00_00/vision_sdk/apps/tools/network_tools/build/../common/inc/tfdtp_api.h:80:24: fatal error: sys/socket.h: No such file or directory #include <sys/socket.h> ^ compilation terminated. In file included from tfdtp_api.c:73:0: ../inc/tfdtp_api.h:80:24: fatal error: sys/socket.h: No such file or directory #include <sys/socket.h> ^ compilation terminated. make[3]: *** [depend] Error 1 make[3]: Leaving directory `/data/work/rveer/workspace/SDK_VISION_03_06_00_00/vision_sdk/apps/tools/network_tools/common/src' make[2]: *** [libs] Error 2 make[2]: Leaving directory `/data/work/rveer/workspace/SDK_VISION_03_06_00_00/vision_sdk/apps/tools/network_tools/build' make[1]: *** [depend] Error 2 make[1]: Leaving directory `/data/work/rveer/workspace/SDK_VISION_03_06_00_00/vision_sdk/apps/tools/network_tools/build' Please let me know the solution for compiling network tool Regards, Chaitra

Hi Chaitra, can you check if you have installed all packages listed in "2.2.3 Other mandatory software packages for build" of the VisionSDK_Linux_UserGuide.pdf. (I am concerned that libc-dev package might be missing on your PC). Regards, Yordan

Hi Yordan, All the manadtory packages are installed. Please let me know is there any other steps to compile the network tool. Regards, Chaitra

Hi Chaitra, can you check if you have '/usr/include/sys/socket.h' file on your PC? Regards, Yordan

HI Yordan, /usr/include/sys/socket.h is present in my system it is a system file we need to build network tool against below toolchain/pacakage sdk/ti/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/networking/nsp_gmacsw_4_15_00_00/packages or sdk/ti/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/networking/ndk_2_24_02_31/packages we have edited the source/vision/platform/ti/tda2/apps/tools/network_tools/build/RULES.MK file as mentioned below BUILD_OS=Linux ifeq ($(BUILD_OS),Linux) MAKE = make CGTOOLS_PATH=/home/chreddy/workspace/FFC_ADAS/FFC/FFC_WORKSPACE/sdk/ti/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/cg_tools/linux/gcc-arm-none-eabi-4_9-2015q3 NSP_INCLUDE_PATH=/home/chreddy/workspace/FFC_ADAS/FFC/FFC_WORKSPACE/sdk/ti/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/networking/ndk_2_24_02_31/packages/ti/ndk endif please let me know if any changes are required Regards,

Hi Chaitra, Network Tool is a PC side tool, so for CGTOOLS_PATH you need to use path to your native gcc compiler, usually you should have: CGTOOLS_PATH=/usr/ (build system later uses CC = $(CGTOOLS_PATH)/bin/gcc , thus calling /usr/bin/gcc). For NSP_INCLUDE_PATH you need to use <VSDK_DIR>/ti_components/networking/nsp_gmacsw_4_15_00_00/packages, can you try with: NSP_INCLUDE_PATH=/home/chreddy/workspace/FFC_ADAS/FFC/FFC_WORKSPACE/sdk/ti/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/networking/nsp_gmacsw_4_15_00_00/packages Also you can check network_tools/docs/VisionSDK_UserGuide_NetworkTools.docx Regards, Yordan

Ticket Name: Linux/TDA2PXEVM: Regarding the accuracy of the Pedestrian Detection algorithm

Part Number: TDA2PXEVM Tool/software: Linux Hi, I'm testing Object Detection of your algorithm. The detection of vehicle is good for test but the detection of the pedestrian is not good. It detects the trees like pedestrian. How can I tune the parameters value? I adjust the below value but the result is not good. pObj->inArgs.pdConfig.softCascadeThPD = 0; pObj->inArgs.pdConfig.strongCascadeThPD = 1; // pObj->inArgs.pdConfig.strongCascadeThPD = -1; // pObj->inArgs.pdConfig.strongCascadeThPD = 0; Regards, Heechang

Hi, There is no universal adaboost descrptor that works in all images / scenarios. May be you need to train the detector for your dataset. You can use the following training to tool train your own adaboost descriptor for the detector. https://github.com/tidsp/acf-jacinto Best regards,

Ticket Name: TDA2: the temperature of SOC core

Part Number: TDA2 Dear all. when I download the same program to the SOC and then after working 12 hours, we uesd PC to get the temperature of SOC CORE, and we find that two SOC have a 10℃ diffirence. I want to know what are the reasons causing this diffirence? PS: In my opinion, I think that the SOC CORE should have the same CORE temperature when they have the same program. the soc model is TDA2S. Looking forward your reply.

The junction temperature is related to the power dissipated, the thermal resistance from the silicon to the ambient, and the ambient temperature. Your question assumes that the ambient and thermal-resistance are equal between the two setups. And so, you, rightfully, consider why the power dissipation is also not the same between the two setups. The power dissipated is dependent upon the applied voltage. Are the CORE domains at the same voltage? The power (at a given voltage) can be broken into a dynamic part which is related to the code you are running and a leakage part which is a function of the device, its temperature (and its voltage) The leakage current of individual devices varies. This variation is a possible cause for your part-to-part variation. As identified in the description above, the voltage or differences in how the code actually runs on the parts could also contribute to the temperature difference. Kevin Lavery

Ticket Name: video input port(VIP) : connect camera number

Other Parts Discussed in Thread: TDA2 Hi， I have a question about the vip. the tda2x soc have some video input port, for example tda2xx have 3 video input port modules, and support for up to 10 multiplexed input ports, that means we can connect 10 cameras simultaneously? I want to be sure the max camera number we can connect. Thanks, Tianxing

You many not be able to connect all 10 comera to TDA2 because of pinmux limitations. For example some of the VIP pins are muxed with DSS pins. So kindly go through the device datasheet to check feasibility based on your board layout or usecase.

Ticket Name: Linux/TDA2: tidl_OD Usecase on Linux platform

Part Number: TDA2 Tool/software: Linux Hi Everyone , I like to know whether it is possible to run tidl_OD use case in TDA2xx EVM linux platform . If we could run , I like to know if there is anything we need to modify in the Usecase level to achieve this Regards , Surendar

Hi, Support for tidl_OD usecase is not been integrated in linux. You have run this on bios. Regards, Anuj

Ticket Name: TDA2: TIDL Eltwise Layer output not matching with caffe output

Part Number: TDA2 Hi, I have Convolutional layers, InnerProduct and Eltwise layers in my model. The caffe ouput and tidl outputs of the convolutional layer and innerproduct layers are matching. But in the elwise layer, some of the elements of the tidl matrix vary too much with the elements of caffe output. For example, let's say Eltwise layer adds two blobs of size 1x5. Here is how the caffe and tidl output looks like: Caffe output: [22.24 -2.33 -15.85 -14.89 -11.05] TIDL output: [21.29 59.05 -15.00 -14.03 -10.16] As you could see the [1] element vary too much. To convert the data to floating point, I am dividing the output data by the OutQ in the logs as mentioned in this thread(e2e.ti.com/.../2370081 Regards, Navinprashath.R.R

Please find the prototxt and caffe model file. The tidl and caffe outputs of the second Eltwise layer are not matching. Also the logs during the import and the input files(lenet_48_48.y) are also attached. PS: The weights here not used in the actual model. But the similar error can be reproduced with this network. Regards, Navinprashath.R.R Not able to upload file because of size attaching drive link. https://drive.google.com/file/d/19Zt7PlV5-yIpD-inALszIwhuxHDUwrPz/view?usp=sharing

Hi, The problem occurs when the input to the Eltwise layer is of opposite signs. Regards, Navinprashath.R.R

Hi Naveen, We don't support this combination. Thanks, Praveen

Hi Praveen, Thanks Praveen. Could we expect this combination support in future release? It is for the same network I am not able to increase the numParamBits to 12. Is it related to this issue? Regards, Navinprashath.R.R

There is no plan to add support for this combination now.

Ticket Name: TDA2SX: emmc firmware burning problem

Part Number: TDA2SX Hi，I got a tda2sx board and do product development on it. The sdk package version is processor_sdk_vision_03_07_00_00. My firmware has been compiled and passed, and the system can be started via sd. But I don’t know how to burn the firmware to emmc and start from emmc.I didn’t find any documentation about this. Can you tell me how to flash the firmware to emmc? Thank you！

Hi, Run the below script from the target in SD boot mode 7345.mk-eMMC-boot.zip Thanks Gaviraju

Hi Gaviraju Using this script, I have successfully burned the firmware into emmc and started it, thank you very much. I saw the USB flashing method, in the link you posted above,used usbboot tool. I want to know the implementation mechanism of usbboot tool, can the source code be developed? Thanks！

HI, No one responded to my question, why?

Hi, Those steps are not tested in vision SDK Linux, so can I know your requirement? based on the requirement, we can give some suggestions. Thanks Gaviraju

Hi, I want to modify the source code of usbboot tool to make a win system burning tool. Thanks.

Thanks Gaviraju

Thanks Gaviraju！

Hi, Why can't I access this link?

Hi Yan, The link got accidentally deleted, please find a snapshot of the link that you are trying to access, we will have it restored shortly. Regards Karthik /cfs-file/__key/communityserver-discussions-components-files/791/Processor-SDK-Linux-Automotive-Software-Developers-Guide.pdf

Ticket Name: RTOS/TDA2: [TIDL_OD + LD] We get wrong result

Part Number: TDA2 Tool/software: TI-RTOS Hi,experts We use TDA2xx and combine the TIDL_OD usecase and Lane detectation usecase as our custom usecase the flow as below chains_tidlOD_P.txt UseCase: chains_tidlOD_Primax

Capture -> VPE -> Dup_capture -> Merge_alg
 
//Dup_capture -> VPE  

//TIDL_OD

Dup_capture -> Alg_tidlpreproc (A15)

Alg_tidlpreproc (A15) -> Alg_tidl_Eve1 (EVE1)
Alg_tidlpreproc (A15) -> Alg_tidl_Eve2 (EVE2)
Alg_tidlpreproc (A15) -> Alg_tidl_Eve3 (EVE3)
//Alg_tidlpreproc (A15) -> Alg_tidl_Eve4 (EVE4)

Alg_tidl_Eve1 (EVE1) -> Merge_OD (DSP1)
Alg_tidl_Eve2 (EVE2) -> Merge_OD (DSP1)
Alg_tidl_Eve3 (EVE3) -> Merge_OD (DSP1)
//Alg_tidl_Eve4 (EVE4) -> Merge_OD (DSP1)
Merge_OD (DSP1) -> Alg_tidl_Dsp (DSP1) -> Merge_alg 

//Display
//Merge_alg -> Sync -> Alg_ObjectDraw -> Display

//LD
Dup_capture -> VPE_LD -> Alg_ImagePreProcess (EVE4) -> Alg_ImgPyramid -> Alg_LaneDetect (DSP1) -> Merge_alg

//Display
Merge_alg -> Sync -> Alg_ObjectDraw -> Display

//GrpxSrc -> Display_Grpx
 and the log as below session_20181015.log We have a video record about the result result.rar From the record, the object detection seen looking like working right in first frame Can you tell us why ? where is the wrong in our flow?

Can you share the behaviour of second frame. Is the output wrong or crash?

Hi, kumar it looks like wrong output the result of lane detection keep working after second frame but object detection is same as first frame no new object had detected Regard Allen

Hi, any update? Regard Allen

Hii Allen, Is the output generated by the import tool is matching with the expected output.? Regards, Kumar.D

Ticket Name: Linux/TDA2: RVP Linux usecase for OpenCV

Part Number: TDA2 Tool/software: Linux Is OpenCV support in TDA2X RVP board? example as in TDA2 EVM OpenCV Canny example?

Hi Krishnakumar, We haven't validate OpenCV in TDA2X RVP board, We validated on TDA2X EVM I am checking with team what all validated on TDA2X RVP board & will get back to you ? Regards Suryamani Jena

Hi Krishnakumar, Are you facing any issues on running OpenCV on TDA2X RVP board ?

Hi OpenCV is not supported on TDA2x RVP board regards, Shiju

Hello Shiju, Thank for the information, We need to run standard VisionSDK OpenCV usecases on RVP board. What is the best approach? Regards, KK

Hello, While there are no usecases built for OpenCV out of the box, it is possible to add OpenCV to RVP usecases. The biggest difference between RVP and EVM in this regard is all capture on RVP is via FPD Link III. OpenCV usecases must be modified to use the multichannel lvds capture initialization instead of the single camera VIP initialization. Basically, look at a usecase that works with RVP and use the same camera setup initialization in the openCV usecases. Hopefully that is all you need to change, but I have not tested these exact steps here. Cheers, Ben

Hello Ben, Thanks for your inputs, Considering that we have link-and-chains, is it sufficient that I set capture mode to be "Camera", so that data comes to my Algorithm module? Alternatively, I have ethernet based input, which can receive YUV or RGB data. Capture of data is of less conern. My concern is, 1. Do we need build OpenCV libraries? or the libraries built for EVM A15 core, can be used as it is for RVP A15 core.? 2. We need to change the .cfg, makefile, etc, so that libraries can be linked to algorithm to run the OpenCV example on RVP, in this context tutorial/guidance will be helpful. Regards, KK

Hi you do not need to rebuild the OpenCV libs, But VSDK apps needs to be rebuild after making below changes 1. Add Open CV UC in TDA2x RVP config (D:\PROCESSOR_SDK_VISION_03_03_00_00\vision_sdk\apps\configs\tda2xx_rvp_linux_all) 2. Modify the OpenCV UC to use FPD link cameras as Ben suggetsed How to build and run OpenCV is documemted in VisionSDK_UserGuide_opencx.pdf regards, Shiju

Ticket Name: RTOS: TDA2 string font setting

Tool/software: TI-RTOS Hello, We want to create a string font for Chinese. We trace code from draw2d_fontxx.c, and get some information, like width, height, num. They have created a array, and put value of 2 bytes each of col and row. Q1：What's the Font_CharNum mean ? Q2：How does it choose value to draw pixel of 'A' or another ? Q3：Can we create a array for new font ? Q4：Can we create a array for Chinese word to draw ? Thank, Ting

Hi Yes, you can create a new array for new fonts, and this can be Chinese letters too. Just follow the code of any existing font array to do the same regards, Shiju

Hi Shiju Thanks for your reply. if I have chinese letters, I can follow the code to do. before that, We have to find truetype to bmp of chinese letters. Q：Do you have advices for truetype to bmp, or someone do that once ? Thanks, Ting

Hi Ting Sorry, I do not have any utility to convert truetype to bmp. Please check on internet. regards, Shiju

Ticket Name: TDA2EVM5777: how to improve latency on TIDL(SSD) application?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi experts: I developed my application by using tidl(SSD) to detect object on image and followed the default TIDL use-case for SSD application on RTOS. After dumping message from TDA2-evm-board, i noticed that the TDA2-evm-board was running on 27-fps but the latency was up to 173ms (average latency time from capture to display link). Full log from TDA2-board is here:latency-log.txt i'm wondering: 1. why does the 27-fps speed have 173 ms latency? why the latency is not 1000/27=37 ms? 2. how to improve latency down to 1000/30=33 ms? Please comment, Thank you. Best / regards wxchen

Hi, .1) why does the 27-fps speed have 173 ms latency? why the latency is not 1000/27=37 ms? In VSDK all links are running parallel & because of this, you are able to achieve 27FPS. suppose if all the links are running sequentially then FPS = 1000/173 FPS = 5 2) how to improve latency down to 1000/30=33 ms? it's not possible because the TIDL link itself taking around 130ms to process Thanks Gaviraju

Hi, Thanks for your response. I'm curious about the 130ms you mentioned. How does the 130ms come? Is it limit of SSD-model running on TDA2 platform? Thanks Best / regards wxchen

Hi, The time is taken by the TIDL algorithm is 130ms to process one frame In order to reduce the latency, you should optimize the TIDL algorithm & the source code of these algorithms is not available in the vision SDK(We used library in vision SDK). Please check with the TI sales team to get the source code. Thanks Gaviraju

Hi, I believe that the TIDL algorithm had been optimized by TI's RnD team. Is there another idea to reduce latency? Thanks, Best / Regards Wxchen

No other way to reduce the latency.

Hi, Thanks for your response. In addition, you said "optimize the TIDL algorithm" in your previous post. I'm wondering what should I optimize? In my intuition, I should optimize the tidl on EVE to process convolution-like operations. Is it correct? Or you mean that I should optimize the SSD's network architecture or others? Thanks. Best / Regards Wxchen

Hi Wxchen, The tidl on EVE is already fully optimized, you can try optimizing your SSD network architecture. Thanks, Praveen

Hi, Thanks for your response. I'm using jacintoV2 network currently. Do you have any suggestion/experience for optimizing SSD network architecture? Thanks. Best / Regards Wxchen

Hi Wxchen, You can either reduce the resolution or train your SSD network with less complex backbone networks like mobile net v1 with a depth multiplier 0.25 Currently, we do not have a pre-trained network example for such models in SDK. Regards, Kumar.D

Hi: Thanks for your response. I will try to decrease SSD network architecture according to your advises. However, I wanna ask for tda2's hardware: 1: Is it possible to boost the clock rate in EVE-core to improve latency? if yes, how to do that? any suggestion for doing that? 2: On the other hand, as far I know, ti's tda4 platform is going to release, 2-1: is that platform capable to reach 1000/30=33ms latency time in jacintoSSD network application? 2.2: is that platform using the same VSDK to tda2's plaform? Thanks, Best / Regards Wxchen

Hi Wxchen, 1. No, as EVE core already clocked at max capacity so no further increase is possible. 2. Yes, but tda4 comes with new sdk, please read more about tidl in tda4 here https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/tidl_j7_01_02_00_09/ti_dl/docs/user_guide_html/md_tidl_models_info.html Thanks, Praveen

Ticket Name: TDA2SX: pressure test script / software

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi At present, we are preparing to do tda2sx ddr3l pressure test,Do you have tda2 ddr3l pressure test script / software? If there is no script, what should I do for stress testing?If we want to develop stress testing software, how to raise the corresponding software requirements? Please help me give some advice. Thank you!

Hi, There is nothing provided outside of what may exist in the SDKs. What operating system does your application use? Thanks, Kevin

Ticket Name: TDA2: source ./vision_sdk_load.sh error report

Part Number: TDA2 Hi , when i try to run examples, following sdk guild document, firstly do "source ./vision_sdk_load.sh", there is some error as below, however sample app can also run. root@dra7xx-evm:/opt/vision_sdk# source ./vision_sdk_load.sh insmod: ERROR: could not load module ./bin/cmemk.ko: No such file or directory ./disableDssInterruptsOnA15.sh: line 11: @0x4A002AC4:: command not found ./disableDssInterruptsOnA15.sh: line 12: @0x4A002AC4:: command not found ./disableDssInterruptsOnA15.sh: line 13: @0x4A002AC4:: command not found ./disableDssInterruptsOnA15.sh: line 14: @0x4A002AC4:: command not found ./disableDssInterruptsOnA15.sh: line 15: @0x4A002AC4:: command not found ./disableDssInterruptsOnA15.sh: line 16: @0x4A002AC4:: command not found ./disableDssInterruptsOnA15.sh: line 17: @0x4A002AC4:: command not found ./disableDssInterruptsOnA15.sh: line 18: @0x4A002AC4:: command not found ./disableDssInterruptsOnA15.sh: line 19: @0x4A002AC4:: command not found updated 0x4A002AC4 value is 00930000 Best regards HUI

Hello HUI , These need to be ignored , this is non fatal error and mentioned in FAQ doc . Regards Chetan.M

Ticket Name: [TDA4M] memory map & EMIF Tool

Other Parts Discussed in Thread: TDA2 Hi I have two questions. I am preparing for a TDA4M bringup. We use RTOS and Linux. We probably to prepare two OS version(RTOS and RTOS-Linux) First, I can't find the location of the memory map source. In TDA2, we modified the *.xs files in the following location vision_sdk/apps/build/tda2px/mem_segment_definition_bios.xs --> RTOS vision_sdk/apps/build/tda2px/mem_segment_definition_linux.xs --> Linux Please provide the location of the same file as the *.xs files in the TDA4 source. Second, I want to get the EMIF TOOL of TDA4.(DDR) We are designing a customer board. So, I want to receive the TDA4 EMIF tool. I wonder if in the future provide guidance that is provided When will be. Thanks

hello, .xs file is no longer supported. A equivalent method is to modify in a .py file, located here vision_apps/apps/basic_demos/app_tirtos/tirtos_linux/gen_linker_mem_map.py To use this you need to do below once, 1. install python3 and pip3. use 'sudo apt install python3-pip' to install pip, see google on how to install python3, mostly likely python3 should already be installed. 2. cd vision_apps/tools/PyTI_PSDK_RTOS pip install -e . You should see something like below, kedar@ubuntu:/ti/j7presi/workarea/vision_apps/tools/PyTI_PSDK_RTOS$ pip3 install -e . Obtaining file:///ti/j7presi/workarea/vision_apps/tools/PyTI_PSDK_RTOS Installing collected packages: ti-psdk-rtos-tools Running setup.py develop for ti-psdk-rtos-tools Successfully installed ti-psdk-rtos-tools Now goto below folder and run he python file, cd vision_apps/apps/basic_demos/app_tirtos/tirtos_linux ./gen_linker_mem_map.py (you may need to edit the first line of this file depending on the python version installed on your machine) This generates linker command files, .h files and Linux dts snippets based on memory map defined in gen_linker_mem_map.py It also outputs a system_memory_map.html in the same folder, open this file to see the memory map. You can update the .py files and generate a new memory map. After this step, some manual steps are still needed to copy the dts file snippets to Linux kernel dts files. Also some tweaking of MCU2-1 memory map is needed in the file vision_apps/apps/basic_demos/app_tirtos/tirtos_linux/mcu2_1/r5_mpu.xs See this note in above file /* make APP_LOG_MEM_ADDR, TIOVX_OBJ_DESC_MEM_ADDR, IPC_VRING_MEM_ADDR as non-cache */ We will document this in detail in next release update. How much DDR memory will be available in your system ? We assume atleast 2GB DDR is available, if you have 2GB DDR then no need to modify memory map. regards Kedar

Kyungtae, I will contact you via the private message tab to help with your EMIF tool question. Thanks, Kyle

Hello, Thank you for your answer. I check the .py file and find the memory file. I will test It. We will use 4GiB as the reference schematic. regards kyungtae

Ticket Name: TDA4VM: some question about tda4

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi: I was using TDA2 platform to develop object detection(ssd-jacinto) application, but by my testing (link), the model latency run on TDA2 platform will be above 130 ms (27-fps) which not satisfied my requirement (less than 1000/30 ms). However, my boss ask me evaluating the TDA4 platform, so a few question below: 1. Did anyone test/verify ssd-jacinto model on TDA4 platform? 2. How about ssd-jacinto model latency time running on TDA4 platform? 3. Is TDA4 platform capable of running ssd-jacinto model above 30-fps? 4. What is SDK supporting the TDA4 platform? Thanks Best / Regards

You can find a lot of TDA4 resources here: https://www.ti.com/product/TDA4VM (Including specifications, application notes and information about software). Specifically, information about SDK is here: https://www.ti.com/tool/PROCESSOR-SDK-DRA8X-TDA4X Information about training Deep Learning Models (including Semantic Segmentation, Object Detection etc) is here: https://github.com/TexasInstruments/jacinto-ai-devkit We provide training examples and scripts for training SSD and RetinaNet object detectors using the repository pytorch-mmdetection. We also have scripts to export the model into a format (.onnx and .prototxt) that TIDL can understand. I hope this information helps you to get started.

Ticket Name: TDA2SX: system DMA and EDMA

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi Waht's different between System DMA and EDMA of TDA2 Thanks a lot!

Hi, Please refer to Ch 16 DMA Controllers in TDA2x Technical Reference Manual. We recommend to use EDMA. Regards, Stanley

if you don't know how to answer this question, don't answer , if let me to look for TRM, it is nomeaning.

This information is already documented very clearly in TRM. Is there anything not clear in TRM? Or, do you have some specific about your use case where you have to evaluate which DMA engine to use?

Ticket Name: TDA2: why Utils_DmaCopy1D work not ok

Part Number: TDA2 HI: I want to use mem copy with dma ,use function Utils_dmaCopy1D,but I find the dest memory is not work ok. the data is always 0. ( dma callback can be work,but the data is not right); how can i let it work right with Utils_DmaCopy1D. THANK YOU! the code as follow below: void dma_memtest() { Utils_DmaChCreateParams dmaChPrm; Utils_DmaChObj dmaobj; Utils_DmaCopy1D dmaParams; Int32 status; dmaChPrm.eventQ = 0; Utils_DmaChCreateParams_Init(&dmaChPrm); status = Utils_dmaCreateCh( &dmaobj, &dmaChPrm ); UTILS_assert(status == SYSTEM_LINK_STATUS_SOK); gspidestBUf = Utils_memAlloc ( UTILS_HEAPID_DDR_CACHED_SR, 1024, 4 ); gspisrcBUf = Utils_memAlloc ( UTILS_HEAPID_DDR_CACHED_SR, 1024, 4 ); memset(gspisrcBUf,0x77,300); dmaParams.destAddr = gspidestBUf; dmaParamsrcAddr =(Ptr)gspisrcBUf;//(Ptr)0x4809a13C; dmaParams.length =32; Utils_dmaCopy1D(&dmaobj, &dmaParams); Utils_dmaDeleteCh(&dmaobj); HexToStr(tmp,gspisrcBUf,32); Vps_printf("\r\nsrc:"); Vps_printf((const char*)tmp); Vps_printf("\r\n"); HexToStr(tmp,gspidestBUf,32); Vps_printf("\r\ndst:"); Vps_printf((const char*)tmp); Vps_printf("\r\n"); }

Hi , Can you disable cache and try this out , i.e alloc the buffer from non cached region . Regards Chetan.M

thank you! i try it! I have a question as follow: when i use edma ,cpu can access memory until edma complete？or it can work during this time？

Hi , Yes CPU can access memory but not advisable to write to the same memory which dma is been performed . Cpu is not blocked till dma complete . Regards Chetan.M

thank you! it is mean cpu can write if i write the different memory when edma is not complete？ and the last your reply means cpu is blocked? but if cpu is blocked,how it can access memory.or you means cpu is not blocked？i think cpu may not blocked your mean.

Cpu is not blocked till dma complete i mentioned NOT Blocked Regards Chetan.M

Part Number: TDA2 Tool/software: TI-RTOS Hi We fallow the user guide and want to create an new use case but We got an error below Can you tell us what's wrong with the error? How can we fix this error? Allen

Hi Allen, is this "Chains_tidlODPrimax" function added by you in the new usecase? Can you check how function "Chains_tidlOD" is defined in "vision_sdk/apps/src/rtos/usecases/tidl_OD/chains_tidlOD.c" and declared as prototype in "vision_sdk/apps/src/include/chains.h" and do similar thing with your function? (I guess you already has it defined in your usecase and just need to add it to "vision_sdk/apps/src/include/chains.h") Regards, Yordan

OK, we resolve this question. And, we have another thread and have not received a response for two days can you help us to resolve the thread below? e2e.ti.com/.../689655 Thanks Allen

Hi Allen, thanks for confirming. I will ping the experts to comment on the other thread. Regards, Yordan

Ticket Name: Linux/TDA2: c66 how to save file

Part Number: TDA2 Tool/software: Linux i am use PROCESSOR_SDK_VISION_03_02_00_00 ,in DSP link i want to save imgdata in a file FILE * landmarks_data = fopen("./handdata_dsp.txt", "wb"); but i cannot find the file , how to save file in DSP link?

Hi Shuai , As filesystem is in A15 , you will have to get the buffer to write to A15 using null in A15 and write the buffer. DSP Link | | DUP Link | | | | Orig path | | Null (a15) ( do file write here) Regards Chetan.M

Ticket Name: RTOS/TDA2: TDA2x MonsterCam

Part Number: TDA2 Other Parts Discussed in Thread: DM388, TVP5158 Tool/software: TI-RTOS From log and code, i can see TDA2x MonsterCam, What is MonsterCam? Capture Source "Sensor OV10635 1280x720 @ 30fps - VIP, YUV422", "HDMI RX 1280x720 @ 60fps - VIP, YUV422", "HDMI RX 1920x1080 @ 60fps - VIP, YUV422", "Sensor AR0132 1280x720 @ 30fps - VIP, RCCC (TDA2x MonsterCam ONLY)", "Sensor AR0132 1280x720 @ 60fps - VIP, Bayer, Ext. ISP (TDA2x MonsterCam ONLY)", "Sensor OV10640 1280x720 @ 30fps - ISS CSI2, Bayer (TDA3x EVM ONLY)", "Sensor OV10640 1280x720 @ 30fps - ISS CPI , Bayer (TDA3x EVM ONLY)", "Sensor AR0132 1280x720 @ 60fps - ISS CPI , Bayer (TDA3x EVM ONLY)", "Sensor AR0132 1280x720 @ 60fps - ISS CPI , Monochrome (TDA3x EVM ONLY)", "Sensor AR0140 1280x800 @ 30fps - ISS CPI , Bayer (TDA3x EVM ONLY)", "Sensor IMX224 1280x960 @ 30fps - ISS CSI2, Bayer (TDA3x EVM ONLY)", "Sensor AR0132 DM388 1280x720 @ 60fps - VIP, YUV422 (TDA2x MonsterCam ONLY)", "Sensor AR0140 TIDA00262 1280x720 @ 30fps - ISS CSI2, Bayer (TDA3x EVM ONLY)", "Sensor OV10635 1280x720 @ 60fps - LVDS (TDA3x EVM ONLY)", "Sensor OV10640 IMI 1280x720 @ 30fps - ISS CSI2, Bayer (TDA3x EVM ONLY)", "Sensor SAT0088 (OV10635) @ 30fps - CAL CSI2, YUV422 (TDA2Ex EVM ONLY)", "CHAINS_CAPTURE_SRC_VIDDEC_TVP5158 , THIS ENTRY WAS MISSING BECAUSE OF A BUG)", "Sensor OV2775 1920x1080 @ 30fps - ISS CSI2, Bayer (TDA3x EVM ONLY)", "Sensor AR0143 MARS 1280x800 @ 30fps - ISS CSI2, Bayer (TDA3x EVM ONLY)", "Sensor IMX290", "Ethernet AVB Cam 1280x720 @ 30fps - (TDA2Ex ETH SRV BOARD ONLY)",

Hi, Chee Peng Tham, After a search in web and in E2E FORUM, I believe this is the company producer of the camera connected to TDA2x. Make a search and also see the thread: Regards, Mariya

Ticket Name: RTOS/TDA2E-17: TDA2E-17 OSD

Part Number: TDA2E-17 Tool/software: TI-RTOS Dear Sirs: In the DM81xx platform, there is a link SWOSD for the osd drawing inside the video. And specifically there is a library in M3 which can be used for OSD drawing inside the video with alphablending. According to this article: e2e.ti.com/.../893557 SWOSD in M3 is using a VCOP library to control it. Just want to ask: Is there any similiar library that can be called to draw osd in the video frame in TDA platform? Regards, /ckhsu

Hi hsu, There is no VCOP library on TDA platform. Rgds, Brijesh

Hi Brijesh: Thank you for the reply. If there is no VCOP library in the TDA platform, is there any approach than can reach the same DMA copy with a specific transparent color/value as in the DM81xx platform? Or you can suggest me any approach that can achieve the same effect. Regards, /ckhsu

Hi hsu, You could use display pipelines to do blending and transparency between two pipelines. Regards, Brijesh

Hi Brijesh: Pipeline is only for display, what we want is not on the display screen, but in the captured video which would be then send to encode. Regards, /ckhsu

Hi Hsu, You could use DSS Mem2mem path to get back the blended output from DSS into memory. This path need not be connected to the actual display. I think TDA2Ex has 4 pipelines, so you could use 2 for the actual display and other 2 with the WB pipelines to blend to video.. Regards, Brijesh

Hi Brijesh: Thank you very much for pointing out this approach. This idea is quite fantasitic, and I think this is the best approach for us to do the same effect as in DM81xx. Sincerely, /ckhsu

Ticket Name: Compiler/TDA2HG: TIDL custom layer support on TDA2

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler I have a requirement to add a custom layer to TIDL library on TDA2 Is adding custom layer in any version of TIDL library supported on TDA2, If yes can you please specify the version of library from which adding a custom layer is supported?

in TDA2X TIDL custom layer is not supported. You can split the network into multiple small networks to add a custom layer in between sub networks

Hi, Thanks for the such a quick response. I am already aware that provision for adding a custom layer is already available in the newer releases of TDA4 TIDL lib. Similarly,I would also like to know if there is any plan to add custom layer support capability to the TIDL library on TDA2 in the future release?

Hi, We don't have any plans to add custom layer support capability to the TIDL library on TDA2. Thanks, Praveen

Ticket Name: PROCESSOR-SDK-TDAX: Update on Processor SDK Radar Version for AWR2243

Part Number: PROCESSOR-SDK-TDAX Other Parts Discussed in Thread: TIDEP-01012, AWR2243, TDA2 Hi, I have posted about this in the past, but I am wondering when there will be a Processor SDK Radar release that supports AWR2243. I have been trying to work with the newest version of the TIDEP-01012 device w/ AWR2243 sensors for months now and have had to resort to makeshift patches provided on here by TI representatives/other forum members. These patches get the board returning data, but I have no clue just how reliable it is or what functionalities are missing. Last time I asked about a new version, I was told to "stay tuned" or "keep an eye out", but it has been months since then with no support for the 2G radar chips yet. I'm starting to wish you guys had just sent me the older version of the cascaded radar board. Please have someone that is directly working on this release version respond to this post, as last time I had a wide range of conflicting responses. Thanks, Jake

Jake, There is currently no update planned for the Radar SDK package for TDA2 with AWR2243 so we do not have a target date. There is support for the 2G radar devices with mmWave Studio - https://www.ti.com/tool/MMWAVE-STUDIO Best regards, Dave

Ticket Name: Compiler/TDA2PXEVM: Need Information/clarity on compiling Linux applications for TI using Vision SDK framework

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi , I have got couple of qeries regarding porting Linux Application on to Vision SDK framework for which I request you to provide your inputs on it. We have got an Linux application say Sample(which is designed and working for Linux platform) which is not complete POSIX compliant but has got support for most of the POSIX features in it. Namely Pthread, Semphores, Sockets, FileSystem calls File(OPEN …), Directory(MKDIR…) and Link(UNLINK..) operations Basic(CHMOD,UMASK…) file attributes File descriptor(FCNTL..) manipulations Read/Write(READ,WIRTE..) operations Synchronized(SYNC,FSYNC..), Asynchronous(IO_SETUP,IO_DESTROY..) and Multiplexed(SELECT,EPOLL…) I/O Monitoring(INOTIFY_INIT) file events and FIFO(mkfifo..) operations IPC communications(Shared memory). As SYBIOS provides pthread support for A15 core and also NDK(Yet to explore) is built for A15 we were trying to compile/build our Linux application(Sample) for A15 core alone on Vision SDK framework. Are we on the right direction? Do you foresee any issues with it? Recent conversation with TI Engineer states we need to Port Linux on to A15 core? Does it mean porting complete Linux platform on to A15 core and post to which we should start porting our Sample on to A15? As mentioned Linux application Sample has got FileSystem calls in place. Do we have support for FileSystem on SYSBIOS? If So, how could we make use of it or do we need to look for corresponding alternatives in it? And Sample being the server component, there are the other application which communicates to Sample via Sockets or through PIPES or any file based operations. Being Sample built for A15 core, does the other applications which has to communicate to Sample should also be built for A15? Request you to pour in your inputs/thoughts on it.

Hi Ramesh, VisionSDK has Linux + BIOS mode on which A15 core runs Linux, while all other cores run RTOS. You can check UserGuide and DevelopmentGuide in PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\docs\Linux. Can you check if that works for you? Regards, Yordan

Hi Yordan, Thanks, definitely I will have a look at it, will get back to you ASAP, in case if I face any issue with it. Btw when I try to compile the sources for "tda2px_evm_linux_all" I do face the below mentioned compiler issues? /tda2/apps/src/rtos/iss/src/sensor/ar0220/iss_sensor_ar0220.c "/opt/V_SDK/FFC/FFC_WORKSPACE/source/vision/platform/ti/tda2/apps/src/rtos/iss/src/sensor/ar0220/iss_sensor_ar0220.c", line 66: error: excess initializers are ignored "/opt/V_SDK/FFC/FFC_WORKSPACE/source/vision/platform/ti/tda2/apps/src/rtos/iss/src/sensor/ar0220/iss_sensor_ar0220.c", line 86: error: excess initializers are ignored 2 errors detected in the compilation of "/opt/V_SDK/FFC/FFC_WORKSPACE/source/vision/platform/ti/tda2/apps/src/rtos/iss/src/sensor/ar0220/iss_sensor_ar0220.c". >> Compilation failure make[5]: *** [/opt/V_SDK/FFC/FFC_WORKSPACE/source/vision/platform/ti/tda2/binaries/apps/tda2px_evm_linux_all/obj/iss_libs/tda2px-evm/ipu2/release/iss_sensor_ar0220.oem4] Error 1 make[5]: Leaving directory `/opt/V_SDK/FFC/FFC_WORKSPACE/source/vision/platform/ti/tda2/apps/src/rtos/iss' More over as mentioned earlier, my Sample application being Server component if it is build for A15 core which runs on Linux, the other use cases/applications which was built for other cores runs on RTOS is it still possible to establish the communication channel among other cores to A15 core?

Hi Ramesh, Already 1 thread is running on this issue. So please do not create duplicate threads. I will provide answers on your running thread. Please close this one . Regards, Anuj

Hi Anuj, I was asked to create the new thread for other topics, assuming I will not the response to it, I have started a new thread. Sure, I will close this loop and will continue to ask the queries on the thread which you have responded. Closing this all the queries will be asked under " e2e.ti.com/.../761254" Pradeep

Ticket Name: Linux/TDA2EVM5777: Power consumption of TDA2X

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hello Why in the TDA2EVM5777 the total power output of the PMIC(SMPS1.2.3+SMPS4.5+SMPS6...etc) is larger than the input power(3V3_EVM)? is there power consumption test report in SDK for reference? thank you~

Hello Which exact 3.3 V rail are you observing? There are multiple 3.3 V lines on the board. How are you measuring the power? Is it through the on board INAs? Regards, Piyali

Hello I didn't measure the power. I study from the document "J6 EVM Power Integrity Analysis" Only VDD_MPU+VDD_DSPEVE will be 10.814W the source of PMIC "PS_EVM_3V3" is feed from TPS43351 buckA which has the maximum 3A output it can only provide 3Ax3.3V=9.9W that is smaller than PMIC output

Hello Could you provide the power consumption of TDA2 when just running a usecase? Maybe like LDWS,FCW,or TSR Thank you~

Hi, Unfortunately, we would not be able to share the power measurements for the SDK usecases. The measured power is usually dependent on the sample type, device junction temperature, type of usecase being run etc. If you would like to know about the worst case power for the device for a particular usecase you have in mind, you can get in touch with your TI representative with the details regarding the CPU Core loading and interfaces being used. If you would like to perform the measurements yourself you can also run the Processor SDK Vision Usecases on the TI EVM and measure the power using the shunt resistors and INAs provided on the TI EVM. Could you please share what activity are you involved in at the moment? Are you working towards creating your own board based on the TI reference? If yes, I can try and get the EVM experts to help you here. Thanks and Regards, Piyali

Hello Yes,I am now designing our own board based on TI's reference. But the power consumption is unknown, and the total power output of PMIC is larger than inputs shown on the reference. Our TI representative told us the output of PMIC in reference is the maximum value ,the output should not exceed the input in actual using. But if there is no information of real using power consumption, how could I make sure that our power design is ok? thank you

Hello, There is a power estimation sheet which for a given application and temperature can allow you to estimate the worst case power consumed. You should get in touch with your TI representative to have access to the output of this excel sheet. Thanks and Regards, Piyali

Hello Thank you for your information , I got the power estimation sheet form our TI representative but I have another question here. Do you know what value should I fit to the sheet if I use just only LDWS function? thank you~

Hello, For the CPU loading information regarding LDW and other related algorithms, you can refer to the Processor SDK Vision software package. This contains the document vision_sdk\docs\VisionSDK_DataSheet.pdf which gives detailed analysis of the device loading for different usecase scenarios. In particular you can look at the "Single Channel Analytics2 on TDA2xx & TDA3xx - EUNCAP usecase" section to get the values for fitting into the sheet. Thanks and Regards, Piyali

Ticket Name: RTOS/TDA2EXEVM: ssd mdoel in tidl have high latency

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hi: Now, we use SSD model in TIDL to do object detection tasks. But the latency in one eve is about 190ms, how I can refine the code to improve the processing speed, in order to decrease the latency. hope your advise.

Hi, Yes, this 190 ms latency is expected for running SSD model on EVE, I do not think we can reduce it further by simply refining the code. I will confirm. Thanks, Praveen

Hi Praveen: thanks for your reply, I want to know when the model is fixed, what can I do to decrease the latency. hope your further answer.

With a given network configuration, the current latency that you are observing is for one EVE. In TDA2 we have four EVEs. The latency can be reduced by partitioning the computation across all 4xEVEs. For, a dense model is it is recommended to split processing spatially (Feature/Activation in height wise). For sparse model also the same logic can be used. When the feature vector size is small, the overheads will be high for sparse flow. So when feature width /height is small, it is recommended to split the processing channels wise. The current VSDK demos are not using this partitioning, this can be done with current TIDL library. Thanks and Regards, Kumar.D

Hi, I don't completely understand your idea. For example, we have trained the model with size of 640x320, in your opinion, i can use one eve to calculate the top half image 640x160, with another eve calculating the bottom half image 640x160? Is there any example I can refer? thanks.

Hi, Yes, your understanding is correct if feature sizes are large. For small feature sizes, split the channels instead of height and use one eve to process some channels, and another eve process remaining channels. We don't have any code to refer for this implementation. Thanks, Praveen

Ticket Name: Linux/TDA2: EVE: Where can I get the original C functions of alg kernel functions?

Part Number: TDA2 Tool/software: Linux I have contact our local TI representative, and they asked me why I needed a full EVE's SDK(eve_sw_01_19_00_00); We needed a full EVE's SDK, There are two reasons: 1、We found some apps function that were different from what our algorithms required, and would like to modify it based on your original version. For example, we need that input size and output size of Median Filter is same, but original version isn't same; 2、We want to develop some new algorithms with referring to your original version. In eve_sw_01_19_00_00\docs\eve_sw_manifest.pdf, can you give us full EVE's SDK( include "Limited Source, Binary and documents" ) ?

Hi, Can you discuss this with your local TI representative and work with him/her to get the source release. This process cannot be done via e2e so you need to discuss with your local TI representative. Regards, Anshu

Ticket Name: TDA2xx: SD-Card booting: Jumping to MPU CPU0 Application (BIOS)

Hello, I had created two Algplugin and integrated them in my Usecase . I tried to boot from an SD card. The TDA2xx only works until "Jumping to MPU CPU0 Application..." appears in the Terminal.

Hi Jagadish, can you check those threads with the same issue and see if they can give you any directions: e2e.ti.com/.../576746 e2e.ti.com/.../774364 Regards, Yordan

Hi Yordan , I had already gone through the threads and tried them, But it was not helpful. Can you give me another solution ?

Hi, Can you put a break point inside the init function of your alg_plugin and check what is going wrong? I hope the alg_id you have created , its value is less than the max alg_id for that core. Regards, Anuj

Hi Anuj, Thanks for ur reply , its working. The alg_id i have created is greater than the max value, i rectified it and its working...

Ticket Name: TDA2E: Drivers imigrate

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 I have a camera AR0143 and I want to send its datas directly to the CPU.The camera's data flow has 12 data bits,one flame_valid bit , one line_valid bit and one sys_check bit.Whether the TDA2xx chip can support this design?And can I find driver models to modify for this design?The follow is hardware design.

Yes, it looks fine. One suggestion, if you use line valid as DE signal, it would be better. Rgds, Brijesh

The camera'data flow is RAW/Bayer.I find the capture Driver in the SDK dosen't support this kind data flow.Should I add an encode chip or modify the capture driver to convert the data flow?

Please note that processing Bayer images requires an ISP which is not available in TDA2E SoC. This is why the SDK does not support this format. It is possible to modify the capture driver for 12b RAW format. But how will you consume the raw image sent by AR0143?

I want to modify the driver to convert RAW to RGB or YUV．if this way wil add CPU much burden?Can you recommend several ISP chips for TDA2xx? I am thinking to choose software encoding or hardware encoding ,do you have saome advice?Thank you!

Yes, doing it in software would cause very high CPU load. I would recommend TDA2PX. This is a device is TDA2 family with internal ISP. It will allow you to reuse all your existing code from TDA2E.

Ticket Name: Linux/TDA2SX: u-boot & kernel device tree porting

Part Number: TDA2SX Other Parts Discussed in Thread: TPS65090 Tool/software: Linux Dear TI, I am now trying to porting linux to my custom board and stucking in device tree porting. Please help me with these questions. uboot device tree: question 1: Is it nessary to use devicetree in uboot? If not, how the periferals drivers be registered? question 2: Which stage is the compiled dtb file being used in？(sbl, uboot) question 3: I have tda2x evm at hand for now. I found it so hard to get my own dts file modify from dra7x-evm-vision.dts file. Because there are so many devices , which are defined in the dtsi files, but not present on my board. So which dts file should i reference to start my own dts file? kernel device tree: question 4: Are there any rules to organize the dtsi and dts files? i.e. Which devices should be placed in dtsi file? Regards, Liu Gan

Hi Liu, Which version of Linux / U-boot are you using? 1. Yes, DTBs need to be ported on both u-boot and kernel. 2. The DTB file is used in the second stage boot loader (u-boot) 3. Please use dra7-evm.dts as the reference device-tree. This device-tree is written for the base EVM board. 4. dtsi files should have all the devices listed. DTS files includes dtsi files and modifies attributes for the devices defined in dtsi. Regards Shravan

Hi Shravan Thanks for your reply. I am working with TI VSDK v3.6 and the corresponding kernel/u-boot release tags. Do i need to disable the devices descripted in the included dtsi files, but are not uesed in my custom board if i take dra7-evm.dts as reference? dts snippet from dra7-evm.dts: What are these two nodes used for? What's more i can not find the min/max-microvolt definded here in the data manual of tps65903x. So i cannot decide how to modify or delete these nodes. Does TI have any released or traning docs/videos about the dts file ? Regards, Liu Gan

Hi Liu, It is recommended you add the status = "disabled" attribute in the final dts file for devices you aren't using. For example if you're not using uart2, please add the below in your kernel device-tree &uart2 { status = "disabled"; }; The snippet in the above post lists the voltage regulators for MMC/SD card which is adjusted depending on the mode at which the sd card operates. If you're using the tps65903x PMIC, please refer to Documentation/devicetree/bindings/regulator/tps65090.txt for the device tree bindings. Regards Shravan

Ticket Name: CCS/TDA2: Is there any way to diagnose the specific PIN on a TDA2X ?

Part Number: TDA2 Tool/software: Code Composer Studio Hello I'm facing the camera data input problem to a specific PIN of VIP on a TDA2X Is there any way to diagnose the PIN with CCS v8 whether active and getting datas or just floating ? Thank you

You can look at the input line state through the GPIO module. Configure the corresponding pin as GPIO input and then look at the GPIO input data register (GPIO_DATAIN).

Thank you for the answer

Ticket Name: Linux/TDA2: Request for minimal .config

Part Number: TDA2 Tool/software: Linux Hello, I'm using PSDK 3.03. Since the initial Linux build takes a long time, is there any .config that includes only basic features regarding TDA2xx/TDA2px SoC? Regards, Nick

Hi Nick To enable TDA2x/TDA2Px with Processor SDK Vision you need to do the dependency component build at least one time, like make -j linux make linux_install make -j depend make -j any subsequent build need only "make -j" (provided no changes in Linux Kernel/uboot and any ti-components) please refer \vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_BuildSystem.pdf for hints to optimize the build time regards, Shiju

Ticket Name: Linux/TDA2EVM5777: TDA2EVM5777 to Radar interface

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2, AWR1243 Tool/software: Linux Hello What interface is there TDA2x provide to link the mmWave Radar for sensor fusion? is there any reference circuit for connecting radar? thank you~

TDA2 has VIP port, so inorder to connect the AWR1243 to TDA2 you would need to convert the CSI to VIP port using some sort of CSI to parallel converter like an FPGA. TI has a plan to launch a TI design for cascade radar processing with TDA2x in Q3 2018. You can use this as a reference. Thanks and Regards, Piyali

Ticket Name: TDA2SX: Whether we can provided those pin's resistor and capacitor value.

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi Experts: Our customer want use Automatic test machine probe SMT TDA2x board's build failure or not. They did not provide power supply to TDA2Sx IC. just probe below pins resistor or capacitor to those power rail's Power supply or GND. Does we have those pin's resistor/capacitor value at no power supply mode? At datasheet i did not found it. Best Regards! Han TaoSoC_parameter.xlsx

Hi Tao Han, I'm sorry, it was a little bit difficult for me to understand your question. Can you please give one example with exact resistor/capactor and a power rail of TDA2.? Some diagram or sketch will be helpful too. Regards, Stan

Hi Stan: Like below picture. For example. item 1: pin AA3 connect to multi-meter + and reference test point VDDSHV 1.8V power supply connect to multi-meter -. test the resistor. item 10: pin Y18 connect to + and GND connect to - test the capacitor. Customer want to know the resistor and capacitor value to verify the PCB SMT quality. Best Regards! Han Tao

Hi, I didn't notice your attached file last time. Do you mean you want to test your boards for continuity when only SoC was mounted? There will be some resistivity and capacitance on those pins, but if also other componets are mounted (relative to those pins), then measurments will not make much sense. Also, I don't think these parameters were characterized, nor they are repeatable between two SoCs. Also, measuring resistivity and capacitance with power off, could cause damage to the SoC (depends on the measuring machine and method). Perhaps, measuring voltages on a powered board would be much safer and beneficial. This is my personal opinion, I might be missing something. Regards, Stan

Hi Stan， We will do ICT(In-Circuit-Test) after SMT. The results will be affected by the internal resistance and capacitance of SOC. If we know the range of resistors and capacitors, we can calculate the range of ICT results. Thanks!

Hi Stan: Thanks for your suggest. You are right customer want to test those pin's resistor or capacitor value when SOC mount at PCB. Will follow your suggest that SOC do not contain those no power supply mode pin to GND/VDDSHVx resistor and capacitor character values. Best Regards! Han Tao

Ticket Name: TDA2: EDMA

Part Number: TDA2 How EDMA is related to the QSPI? In my TI driver's code, RPRC image is read from the external SDF, in which EDMA is used. And EDMA is using the QSPI. I am not able to get how these two are related? Please Clarify. THanks in Advance! Regards, Sagar

Hi Sagar, There are two options for reading app Image from QSPI :CPU copy and EDMA. EDMA performs high-performance data transfers between two memories without CPU's intervention. Hence SBL uses EDMA. Hope this clarifies. Regards, Rishabh

Hi Rishabh, Thanks for reply. I want to clarify that whether EDMA uses the same pin which QSPI uses or different. In my SBL source code void QSPI_ReadSectors_edma(void *dstAddr, uint32_t srcOffsetAddr, uint32_t length, uint32_t edma_ch_num) this is the function which is used for reading from external SDF. Inside this function following function is called uint32_t EDMA3EnableTransfer(uint32_t baseAddr, uint32_t chNum,uint32_t trigMode) { uint32_t retVal = FALSE; switch (trigMode) { case EDMA3_TRIG_MODE_MANUAL: if (chNum < SOC_EDMA3_NUM_DMACH) { EDMA3SetEvt(baseAddr, chNum); retVal = (uint32_t) TRUE; } break; case EDMA3_TRIG_MODE_QDMA: if (chNum < SOC_EDMA3_NUM_QDMACH) { EDMA3EnableQdmaEvt(baseAddr, chNum); retVal = (uint32_t) TRUE; } break; case EDMA3_TRIG_MODE_EVENT: if (chNum < SOC_EDMA3_NUM_DMACH) { /*clear SECR & EMCR to clean any previous NULL request */ EDMA3ClrMissEvt(baseAddr, chNum); /* Set EESR to enable event */ EDMA3EnableDmaEvt(baseAddr, chNum); retVal = (uint32_t) TRUE; } break; default: retVal = (uint32_t) FALSE; break; } return retVal; } If you have the edma.c then please explain me how this function works. Also what is the meaning of shadow region? Thanks! Regards, Sagar

Hi Sagar, I would suggest you to go through EDMA chapter from TDA2 TRM. Regards, Rishabh

Ticket Name: CCSTUDIO: How to have the dip switch sys-boot configured for debug mode for TDA2?

Part Number: CCSTUDIO Hi Expert, https://e2e.ti.com/support/processors-group/processors/f/processors-forum/701991/ccs-tda2-ccs-7-4-tda2x-evm-jtag-connection-issue Alex say: In addition to the above suggestion, make sure you have the dip switch sys-boot configured for debug mode. See e2e.ti.com/.../2557345 but the Page Not Found. Could you help me to make sure I have the dip switch sys-boot configured for debug mode? Thanks Daniel

Hi Expert, Could you help me to set the dip switch sys-boot configured for debug mod? Thanks Daniel

It is documented in Vision SDK User guide. You can download Vision SDK package https://www.ti.com/tool/PROCESSOR-SDK-TDAX. Or, you can just download the document from the above link.

Ticket Name: TDA2SX: How to support YOLOv3 with TIDL?

Part Number: TDA2SX We want to running YOLOv3 model on TDA2SX to detect pedestrian and vehicle, but TIDL only support caffe model. Can TI provides support for YOLOV3 to caffe model, or where can I found some examples for this? Best Regards, Bob Deng

Hi Bob Deng, We haven’t validated YOLOv3, so TI can not provide support for YOLOV3 to caffe model. If the model format is caffe/tf/onnx and all the operators are supported by TIDL then they you can try importing. Thanks, Praveen

Hi, It was initially implemented using resizer, which is available on TDA3x. But could you please if it internally uses VPE driver? Then it can even be enabled on TDA2x. Regards, Brijesh

Ticket Name: TDA2EXEVM: TDA2 Processor Board + AWR RF Board Connection

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi, In the ProcessorSDKRadar_UserGuide.pdf, High Level Block Diagram on page 13, there is a UART3 connection from the Processor Board to the RF Board thru a selectable MUX. Can you tell me what the 4 UART lines into the RF board is for? I know Processor communicates with RF board over SPI and not UART. We redesign the RF board and have a device on it that we need to interface with from the Processor Board. Can we use one of these 4 UART to interface with this device? If not, please recommend an interface from the Processor Board to the RF Board we can use? Thanks, --Khai

Hi Khai, UART port is used for programming firmware to flash. One for each radar. Regards, Stanley

Hi Stanley, Can you recommend an interface to communicate with a new device on the RF board from the Processor board. Thanks, --Khai

Khai, The SoC can support up to 10 UARTs if that is the interface you would like to use for this other new device. Refer to the Data Manual for proper pin locations of UARTs. Also, there is I2C going from the TDA2 Processor Board to the AWR RF Board. So depending on what device has been added there are those options. Thanks, Alec

Alec, Please provide Data Manual. Thanks, --Khai

Khai, I edited my initial reply shortly after to include that I2C could be an option as well for communication. Just matters what your extra device is capable of. Datasheet is available at this link for reference: http://www.ti.com/product/TDA2SA?keyMatch=TDA2S&amp;tisearch=Search-EN-everything&amp;usecase=part-number Thanks, Alec

Ticket Name: TDA2HG: tda2 anti-aliasing

Part Number: TDA2HG hello: usecase: render a model, but the alias is obvious, so i need to use the anti-aliasing. when the egl chooseconfig, i add the EGL_SAMPLE_BUFFERS, 1 and EGL_SAMPLES,4 to the attribs, it works better, but not enough, so i change the EGL_SAMPLES, 8, the result is eglCreateContex failed! it seems doesn't support. do you have other methods? thanks ~

Hello, That is correct. 8 is not supported. 4 is the max value for EGL_SAMPLES. Regards Hemant

how about TDA4, the max value?

Hello, TDA4VMid also supports upto 4 - but of course, you will need to keep overall performance in mind. Regards Hemant

got it, thank you~

Ticket Name: TDA2EVM5777: Custom Camera running on TDA2 board in RTOS

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi experts: I have a project that using camera module with ISP IC which output format to 720p's YUV422 10-bits. I created an new usecase (Capture -> Alg_custom_frame_copy(DSP1) -> Display(YUV420sp_uv)) for testing this camera. I'd like to do color space transformation on Alg_custom_frame_copy node, so I assigned those following custom settings for this camera after calling ChainsCommon_SingleCam_SetCapturePrms() 1: videoIfWidth -> SYSTEM_VIFW_16BIT 2: pInprms->dataFormat -> SYSTEM_DF_YUV422I_YUYV 3: pOutprms->dataFormat -> SYSTEM_DF_RAW16 and i transform data on Alg_custom_frame_copy by the following code: 	Int32 row_idx , col_idx ;
	UInt8 *src_gray = (UInt8 *)inPtr[0];
	UInt8 *dst_gray = (UInt8 *)outPtr[0];
	UInt16 *row_ptr = 0;
	UInt16 tmp;

	for (row_idx = 0 ; row_idx < 720 ; ++row_idx, src_gray += inPitch[0], dst_gray += outPitch[0])
	{

		row_ptr = (UInt16 *)src_gray;

		for(col_idx = 0 ; col_idx < 1280 ; ++col_idx)
		{

			tmp = (row_ptr[col_idx] >> 6);
			dst_gray[col_idx] = (UInt8 )(tmp & 0xFFU);
		}
	}         memset( outPtr[1], 0x80, 1280 * 720 / 2); // try the gray channel first, so set UV channel to empty and i got those following error on the display(see figure): 1. one-fourth camera's FOV. 2. image noisy. 3. pixel-gap on x-direction of image. so, a few questions below: 1. does my settings/code wrong to transform color space? 2. I try 0 shifting on Alg_custom_frame_copy, I will get dark display. So, I wonder how the bit-ordering of input image. How to get that?(camera's data pin is connected to v1d0~v1d9 by pin-to-pin) 3. Due to there is only one-fourth camera's FOV and pixel-gaping, does VIP module output wrong size of image? 4. Or any good suggestion of my project? Best / Regard Wxchen

dst_gray[col_idx] = (UInt8 )(tmp & 0xFFU); Are you clipping 10-bit data to 8-bits? It seems like you are sacrificing 2 MSBs. This would explain image quality degradation as shown in the snapshot.

HI: Thanks for your reply. i tried to map 10-bit data to 8-bit( grayValue / 1024.0 * 255.0). It seems that the result was similar to clipping data. here is an testing snapshot. BTW, what cause the wrong FOV and pixel-gapping? wxchen

I can not figure out the issues when the image has been badly damaged by losing the MSBs. Can you please provide a file dump of an original 10-bit UYVY frame sent by the sensor?

Hi: Would you please provide the actual parameters of grabbing 10-bit UYVY frame in VIP driver? I can change parameters from ti_components\drivers\pdk_01_10_03_07\packages\ti\drv\vps\examples\vip\captureVip\src\CaptureVip_main.h. I will compile driver example and put it to TDA2 board, then the program will dump frame file to SD-card, and I will send it back to you. Best / Regard wxchen

Not sure what you mean by "actual parameters of grabbing" I am assuming you have 10-bit UYVY in inPtr. All you need to do is write to a binary file using fwrite or CCS.

Hi: I'm sorry for your misunderstanding. Because I'm not sure about what the proper parameter is for grabbing YUV422 10-bit image(720p) from camera in the VIP module. Would you please provide proper parameter for my case? I will build application of pdk that can dump that file to you. Thank you. wxchen

I believe you already have captured from VIP and that's the image you are manipulating. If that's not correct, please ignore my comments. Simply replace the clip to 0xFF by downshift of 2 and you will be able to get a good image.

Ticket Name: RTOS/TDA2: What is the performance of EVE in TDA2PX?

Part Number: TDA2 Tool/software: TI-RTOS Hi, I want to use EVE to deal with 4 720p camera HDR. After I invested, find when I use one eve to deal with 2 720p HDR, the percentage of EVE is about 90%. I think the eve should be more powerful. I use non-bam framework. If the bam framework or non-bam framework has so much effect? And if there is any formal eve performance data? Thanks a lot! Best Regards, Derek Yang

Hi, When I set block width from default value, 64, into 128, and keep the height in default value, 32, the performance improve a lot. But when I increase block width into 256, and keep height in 32, the process can't run. If anybody can help on this? Thanks! Best Regards, Derek Yang

Derek, There should not be much difference in performance of bam and non-bam applications. For performance data you can refer eve_sw_datasheet.pdf located inside docs folder of EVESW. Regards, Anshu

Derek, Typically larger the block size you process better is the performance. But these sizes cannot be increased arbitrarily as eventually these block sizes determines how much internal memory you use which is limited. Regards, Anshu

Hi Anshu, Thanks a lot! I find in apps/apps_nonbam/test/common, the MEMORY define is as below, .. IMEMLA: origin = 0x40050000 length = 0x4000 ... If it is possible to increase the size into 0x8000?. For the block size, I set it into 128x48=6k. If I increase it into 128x64=8k, system will block. But the memory size is 0x4000, 16k. And in EVE app document, the max block size is 32kb. How can I set the block size into bigger one, for example 8k or 16k? Thanks! BRs Derek Yang

Derek, For all the apps we use alias mode of EVE memory which helps in implementing ping-pong buffer scheme for processing. In this mode each of the image buffer becomes half of the total to support aliasing. So both IBUFL and IBUFH becomes 16KB each. Regards, Anshu

Ticket Name: TDA2SX: DESIGN FILE REQUEST TDA2

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2EVM5777 Hello We're Planning To Use TDA2X For Our Next Vehicular Machine Vision EVS Project. And When We Try To Look Up TI Website For Design Files Find No Results At All. The DSN File Is Really Important For Hardware Engineer To Prevent Starting Project From Scratch. The Rough Manual Work To Build Symbol For Such A Complicated Device Will Be Possible To Make Mistakes. So I'm Here Writing My Problem To Ask For Relative Files. Basically We Need You To Do Following Favors: TDA2EVM5777 (Complete Schematics / Schematics / Schematics / Schematics / Schematics DSN File)

Hi Bright, Please check this link! There is a Design Files section under EVM page that you may also want to check. Thanks, Dian

Hi Bright, Did you get what you want? I have same requirement as you. If you got it, could you tell me how to get it. Thanks, Seven

Seven I Don't Think I Get Required Support For Wanted Files. In Fact Here Are Only Non-OrCAD File Upon Product Page And I Don't Know How To Transfer It Into What I Want Import To OrCAD. And Considering Software Support And Following Code Jobs Efforts We Have Move Our Project To Use NXP S32V In Stead Of TDA2X. So As You See I Don't Follow Up The Thread And Continue To Request The Files. Bright

Ticket Name: RTOS/TDA2: PROCESSOR_SDK_RADAR_03_04_00_00_setupwin.exe

Part Number: TDA2 Tool/software: TI-RTOS 1、Using gmake to compile \ti_components\algorithms\eve_sw_01_19_00_00\starterware\examples\mailbox_eve1_to_dsp1\dsp1\src there is a fatal error: illegal attempt to place ".cinit" before ".far" in "GROUP_1" Gmake: *** [dsp_mbox_eve1_to_dsp1.out] Error 1 2、Put the ".cinit" section after the ".far" section, and use gmake to compile the project with the following error. Undefined first referenced Symbol in file --------- ---------------- TSC_enable ../objs/eden_mailbox_eve1_to_gem1_gem1.obj TSC_read ../objs/eden_mailbox_eve1_to_gem1_gem1.obj __ISR_Table ../objs/intvecs.obj 3、I changed _TSC_read to TSC_read in tsc_h.asm and changed _TSC_enable to TSC_enable. Change the __ISR_Table in intvecs.asm to _ISR_Table to compile the executable file after compiling with gmake 4、I loaded the executable file of dsp1 and eve1 to the TDA2xdemo board through ccs. The data was written in the mailbox message in eve1, MAILBOX_IRQENABLE_SET_u was 0x1, but dsp1 did not receive the interrupt, and the interrupt did not respond. What should I do?

Hi, Have you run the cross bar gel? Please refer Chapter 4 of starterware\docs\eve_starterware_userguide.pdf Regards, Anshu

Hi, Are you able to progress on this? If yes please close this thread, otherwise let us know if you followed the steps mentioned in previous thread. Regards, Anshu

Ticket Name: TDA2PXEVM: TDA2PXEVM: TIDL Host hmulation build

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello According to the TIDL guide $ make CORE=eve TARGET_PLAT FORM=PC TARGET_BUILD=release was conducted on the $TIDL_INSTALL_PATH/ti_dl during work, but the following error phrase was found. g++: error: ../../ti_dl/lib/PC/eve/release/tidl_algo.lib: No such file or directory /home/slgpu2/Mywork/TI/tda2/ti_components/algorithms/REL.TIDL.01.02.00.00/makerules/rules.mk:599: recipe for target 'outfile' failed When I looked up the official answer related to this in the TI support forums, there were the following answers. Source release of TIDL is available as standalone release via CDDS. Please work with your local TI representative to get access to the same. "First you need to sign NDA document with your TI representative and then he will create the CDDS account." How can I get a PC-related tidl_algo.lib?

Hi, TIDL host emulation build libraries are not available publicly, so you need have a NDA with TI to get access to them, so please check with local TI FAE for more details. Thanks, Praveen

Ticket Name: TDA2: GPU and EVE quantities inside TDA2H, TDA2SX and DRA756

Part Number: TDA2 Other Parts Discussed in Thread: DRA756, Please see TDA2x and DRA756 functional block diagram below: 1. We know Dual-core PowerVR SGX544 3D GPU from 1.1 Features of TDA2x datasheet, but we just see PowerVR SGX544 3D GPU from 1.4 TDA2x functional block diagram; TDA2x include 1 or 2 PowerVR SGX544 3D GPU ? 2. Does DRA756 has 2 EVEs inside it ? 3. DRA756 and TDA2x use same EVB and schematics?

Hi Joseph, Block diagram shows the GPU subsystem. Yes there are two EVEs in DRA756. You can refer to datasheet for more details: www.ti.com/.../dra75.pdf Regards, Rishabh

Hi Joseph, for question #3 you can find TDA2/DRA74 EVM board schematics (along with some other useful documents) in "Design Files" table here: www.ti.com/.../j6evm5777 Regards, Yordan

1. We have DRA756 EVB in our hands, if we program Vision_SDK030600 software into DRA756 EVB, can Vision_SDK030600 software run on this DRA756 EVB ? 2. Or we remove DRA756 for DRA756 EVB, then install TDA2X on this EVB and program Vision_SDK030600.

Hi, Vision SDK will work with both DRA756 and TDA2X but you need to make sure you update the configuration accordingly. E.g. Vision SDK BIOS all configuration assumes 4 EVEs and hence the same will not work for DRA756 part. Regards, Rishabh

Ticket Name: TDA2SX: TDA2 for MDIO "Clause 45" PHY support

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi there We are working on the TDA2 platform and we want to use 10000BASET1 automotive ethernet. Currently the phy chip we are working with is Marvell 88Q2112 but it only supports configurations through the Clause 45 register set. We are trying to implement the Clause 22 Access to Clause 45 Registers indirect access read/write on top of your MDIO_USERACCESS0 register but unable to make it work. The data we read back with correct phy addr and correct sequences always with 0xffff. We are wondering if anyone make a MDIO Clause 45 PHY work on TDA2? Thanks, Li

Hi, MDIO Clause 45 is NOT supported on TDA2. Please refer to the TRM as shown below for the support MDIO frame format. Regards, Stanley

Thanks..... but my colleagues made it work 2 months ago....

Ticket Name: TDA2: Complete TDA2 part number in TDA2Px-ACD CPU EVM Board

Part Number: TDA2 Hi, What's complete part number in TDA2Px-ACD CPU EVM Board? Where could get schematic?

Hi, the CPU on the EVM is a "superset" part that can be configured as particular TDA2Px device. You can find EVM schematics (along with other documents) here: www.ti.com/.../tda2pxevm Regards, Yordan

Ticket Name: RTOS/TDA2: Vision SDK 3.03, arp32 linker flags zero_init=on

Part Number: TDA2 Tool/software: TI-RTOS Hi, Below is what I set, diff --git a/vision_sdk/build/rtos/makerules/rules_arp32.mk b/vision_sdk/build/rtos/makerules/rules_arp32.mk index 346a0c8..6ca47ee 100755 --- a/vision_sdk/build/rtos/makerules/rules_arp32.mk +++ b/vision_sdk/build/rtos/makerules/rules_arp32.mk @@ -237,7 +237,7 @@ ifneq "$(or $(OBJ_PATHS),$(OBJ_PATHS_ASM),$(OBJ_PATHS_CPP))""" endif # Linker options and rules -LNKFLAGS_INTERNAL_COMMON = --warn_sections -q -e=_c_int00 --silicon_version=arp32 -c -x --zero_init=off --rom_model +LNKFLAGS_INTERNAL_COMMON = --warn_sections -q -e=_c_int00 --silicon_version=arp32 -c -x --zero_init=on --rom_model # Assemble Linker flags from all other LNKFLAGS definitions _LNKFLAGS = $(LNKFLAGS_INTERNAL_COMMON) $(LNKFLAGS_INTERNAL_PROFILE) $(LNKFLAGS_GLOBAL_$(CORE)) $(LNKFLAGS_LOCAL_COMMON) $(LNKFLAGS_LOCAL_$(CORE)) When I load binaries over CCS v7 onto TDA2X ES1.0 EVM for EVE cores, the core starts running by default. If I try to pause it, I see this error on CCS v7 Console: ARP32_EVE_1: Trouble Halting Target CPU: (Error -2062 @ 0x0) Unable to halt device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.27.9) SD Card boot also fails similarly, only with above patch. If I revert the above patch, sample_app usecase works fine.

Hi, Can you check if any MMU fault error is generated with this. Regards, Anshu

Hi Anshu, How would I be able to do the same ? and if it does turn out to be a MMU fault what does it convey, since I have not touched anything else. This patch works fine on Vision SDK 2.09

Can you check the value of following register from A15 after the issue. MMU_IRQSTATUS : (0x40281018 : This is for EVE 1) Regards, Anshu

The value reads 0x00000002 As shown in snapshot

Hi, Can you share the following gel file with us : <ccs_install_dir>\ccs_base\emulation\gel\TDA2x\TDA2xx_multicore_reset.gel Regards, Anshu

Attached is the files you requested: TDA2xx_multicore_reset.gel

Hello, Any thoughts on this issue?

Hello It seems like EVE CPU is crashed, BTW, are you seeing this issue only when you set zero_init=on? with zero_init=on, I have fixed a bug in VSDK and this fix will be available in next release (3.5) FYI here is the patch you need to apply this in all EVE_x.cfg files under links_fw/src/rtos/bios_app_common/tda2xx/eve1/Eve1.cfg, Eve2.cfg, Eve3.cfg & Eve4.cfg Program.sectMap["ttbSection"] = new Program.SectionSpec(); Program.sectMap["ttbSection"].loadSegment = "EVE1_DATA_MEM"; Program.sectMap["ttbSection"].type = "NOINIT"; regards, Shiju

Hi Shiju, Yes I was seeing this issue only when setting zero_init=on in rules_arp32.mk. I tried the patch you suggested and looks like it has fixed the eve crash I was noticing. Let me know if you see any risks if I plan to have this setting in all makefiles of all cores. Thanks and Regards, Vivek

Ticket Name: TDA3XEVM: How to build the TDA3 within VSDK3.7 for this folder:

Part Number: TDA3XEVM Other Parts Discussed in Thread: TDA2 Hi. I'm learning the TIDL building according this: TIDeepLearningLibrary_UserGuide.pdf however, I'm building this on the ubuntu18.04. --> /opt/PROCESSOR_SDK_VISION_03_07_01_00/ti_components/algorithms/REL.TIDL.01.01.03.00# However, this PDF has no mentioning on the TIDL building. please guide me how to build this TIDL on the ubuntu for TDA3. THanks. BR Rio

Hi, TIDL build on the ubuntu for TDA3 is not supported and hence not documented in the TIDL user guide. Thanks, Praveen

Hi. So, I can image the TDA2 TIDL is not okay to be built on the ubuntu? Am I right? Only the TDA4 TIDL can be built on the ubunutu? May you summerize those TDA2/3/4 TIDL supported on the ubunutu? Thanks. BR Rio

Hi Rio, Yes, you are right. TDA2/3 TIDL build is not supported on the Ubuntu but TDA4 TIDL build is supported on the Ubuntu. Thanks, Praveen

Ticket Name: AM5728: DSP transfer bandwidth and latencies across L3 to on-chip SRAM and DDR

Part Number: AM5728 Other Parts Discussed in Thread: TDA2 We are experiencing excessive interrupt latency on the DSP which is running a TI-RTOS application. Please help us with answers to the following questions, assuming the initiator of the transfer is one of the C66x cores: What is the maximum data transfer bandwidth and expected latency across the L3 Interconnect fabric itself (assuming L3 fabric is configured for max clock which I think is 256 MHz)? What is the maximum data transfer bandwidth and expected latency across the L3 interconnect-to-OCMC_RAM (i.e. the on-chip Level 3 memory)? What is the maximum data transfer bandwidth and expected latency across the L3 interconnect-to-DMM (Dynamic Memory Manager)-to-EMIF interface-to-external DDR3-1066 SDRAM? Thanks

Hi Rperezti, Due to a holiday in India, half of our team is currently out of office. Please expect a 1~2 day delay in responses. Apologies for the delay, and thank you for you patience. Regards, Takuma

Hello Rperezti, Please see the detailed performance document for the TDA2 which will be very similar performance for AM5728x: https://www.ti.com/lit/an/sprac21a/sprac21a.pdf Please let us know if you have any additional questions. -Josue

Thank you Josue. This document is helpful. We may need additional help to debug the interrupt latency problem in the system but we will open a separate thread for further questions.

Ticket Name: TDA2SX: How to improve the size of GPU video memory

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 We use QT in our project and find that the GPU is short of video memory. I see that the memory of PVR is about 160MB. How can I improve the memory of PVR? I tried to change the size of CMA, but it didn't work. root@dra7xx-evm:/proc/pvr# cat mem_areas Number of Linux Memory Areas: 897 At the current water mark these areas correspond to 164007936 bytes (excluding SUB areas) At the highest water mark these areas corresponded to 164007936 bytes (excluding SUB areas) root@dra7xx-evm:/proc/pvr# cat /proc/meminfo MemTotal: 599572 kB MemFree: 222012 kB MemAvailable: 267416 kB Buffers: 212 kB Cached: 94036 kB SwapCached: 0 kB Active: 95780 kB Inactive: 75624 kB Active(anon): 77160 kB Inactive(anon): 45268 kB Active(file): 18620 kB Inactive(file): 30356 kB Unevictable: 0 kB Mlocked: 0 kB HighTotal: 259072 kB HighFree: 143032 kB LowTotal: 340500 kB LowFree: 78980 kB SwapTotal: 0 kB SwapFree: 0 kB Dirty: 0 kB Writeback: 0 kB AnonPages: 77148 kB Mapped: 167872 kB Shmem: 45280 kB Slab: 15884 kB SReclaimable: 4472 kB SUnreclaim: 11412 kB KernelStack: 1424 kB PageTables: 2336 kB NFS_Unstable: 0 kB Bounce: 0 kB WritebackTmp: 0 kB CommitLimit: 299784 kB Committed_AS: 896872 kB VmallocTotal: 245760 kB VmallocUsed: 0 kB VmallocChunk: 0 kB CmaTotal: 212992 kB CmaFree: 48636 kB

Hello, TDA2 is a shared memory architecture and there is no dedicated video memory for the GPU. GPU cannot however access highmem so the amount of internal memory available to the GPU is limited by lowmem. In addition to internal memory, GPU also needs display bound buffers that are either CMA or DRM managed. But since, increasing CMA does not help in your case, you are likely running out of overall memory available in low memory regions. Regards Hemant

Ticket Name: RTOS/TDA2: EDMA3 read qspi flash

Part Number: TDA2 Tool/software: TI-RTOS on TDA2S ,run RTOS, i want to use edma read qspi flash , i remap flash to 0x5C000000, used Utils_dmaCopy1D function to read flash, but read some datas is error , all error data is 0,i use pc read（memcpy) is all right, what is wrong with this?

Hi, You can use System_qspiReadSector API present in PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\links_fw\src\rtos\utils_common\src\utils_qspi.c. Regards, Rishabh

HI thanks your reply, System_qspiReadSector is not used EDMA, i want to use edma,

Hi i found mlo use QSPI_ReadSectors_edma read qspi flash ,and i compare the QSPI_ReadSectors_edma() and Utils_dmaCopy1D, these two functions have little difference , how can i used QSPI_ReadSectors_edma in appliation level?

Hi, For EDMA you can refer to API Utils_qspiReadSectorsEdma in PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\links_fw\src\rtos\utils_common\src\tda3xx\utils_boot_slaves.c. Regards, Rishabh

Ticket Name: Linux/TDA2: HDMI connect detected

Part Number: TDA2 Other Parts Discussed in Thread: TPD12S016 Tool/software: Linux Hi Expert, I'm running Linux Vision SDK v03.02.00(4.4.84) on the custom PCBA. TDA2 can do HDMI or LCD1 output. Need to add a mechanism to judge whether there is connection to HDMI. If there is a connection then HDMI output. If not, switch to LCD display. Is it GPIO to read the TPD12S016 "HDMI_HPD_A" state? Or are there other ways to tell if HDMI is connected? Thanks in advance.

Hi, Yes, you can read GPIO to find out HDMI connected state. In linux driver, we follow this sequence write 1 to HDMI_CT_HPD sleep 500 microseconds read HDMI_HPD write 0 to HDMI_CT_HPD But I think you can skip steps 1, 2 and 4 Regards, Subhajit

Ticket Name: TDA2: whether TI has plan to do ASIL-B qualification of any TDA2/3

Part Number: TDA2 Whether TI has plan to do ASIL-B qualification of any TDA2/3? TI only mention that it pass the ISO26262 standard but not mention ASIL-B. Thanks.

Hi Terry, please check it this can help you: e2e.ti.com/.../2189966 e2e.ti.com/.../2129037 Regards, Yordan

Hi Terry, I haven't heard back from you, I'm hope your query is resolved. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Ticket Name: TDA2P-ACD: TI PinMux Tool doesn't generate devicetree.txt

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Hello, I am trying to use TI PinMux Tool to generate devicetree.txt then I can integrate these nodes inside my board dts. The issue is that what ever change I make in the pins configuration, there is no change reflected in devicetree.txt file, however I can see changes in other files (e.g. boardPadDelayInit.c and genericFileFormatPadConf.txt) How can I make the configurations reflect in devicetree.txt ? Thanks, Abdalla

Hi, A detailed application note of how to configure pinmux for TDA2 is here: https://www.ti.com/lit/an/sprac44a/sprac44a.pdf?ts=1618200162219 Please go through that. Best Regards, Keerthy

Hi Keerthy, Thank you for your reply, however I can't find anything in the document about devicetree.txt generation by TI PinMux tool. My question is: why doesn't the the PinMux tool generate devicetree.txt for my target as shown in the screenshots I attached ? I am wondering if you can generate devicetree.txt on your end for the same device target ? Best Regards, Abdalla

Hi Keerthy, According to the comment in devicetree.txt (Only MMC modes are exported here. All other pad configuration must be done by u-boot.) What is the effect if I only configure the RGMII pins in kernel dts without configuring them in uboot ? Does this affect the functionality of the mac port on SoC after kernel boot ? Thanks, Abdalla

Hi, Can you not do that in "board/ti/dra7xx/mux_data.h" under u-boot? - Keerthy

Ticket Name: TDA2: disable EMIF2 clock

Part Number: TDA2 Hi, I can disable EMIF2 clock by SW control in SBL. But when jumping to AppImage, the EMIF2 clock would be active again. 1. Is this symptom normal? 2. Does there any api can used to control this? I can not use HW_WR_REG32() in Appimage. Thanks~~

Hi, You can use PMHALModuleModeSet API to set EMIF2 to off. The symptom is not normal. Can you describe how you are getting EMIF2 active? Regards, Rishabh

Hi, I use HW_WR_REG32(0x4A008B38, 0x30000) in SBLUtilsDDR3Config(), and then check EMIF2 clock in SBL stage. The clock is off and then jump to Appimage. I check the EMIF2 clock again, it becomes active. Thanks~~

Hi, This means that EMIF2 is turned on somewhere in the application image. If this is a concern you need to check where you are enabling. If this is not a concern you can simply call PM API to turn EMIF2 module off. Regards, Rishabh

Hi , Does PMHALModuleModeSet just disable EMIF2 module, but the clock is still active? Now I disable EMIF2 module by un-define BUILDCFG_PMHAL_PRCM_MOD_EMIF2 in pmhal_prcm_modinc.h. Because our board already has 2 DDR, I can not verify is it work or not. So I use EMIF2 clock to verify it, but it seems somewhere would turn on the clock even if I disable EMIF2 module in Appimage. Does my method to disable EMIF2 module correct? (un-define BUILDCFG_PMHAL_PRCM_MOD_EMIF2) What do you recommend to verify EMIF2 module disable or not base on our board? Thanks~~

Hi Markii, What is the exact requirement you want to implement. The method to turn off EMIF2 is disable the module by calling PMHALModuleModeSet API and not commenting code. Regards, Rishabh

Hi, We want to use one DDR only.. So we want to disable EMIF2 module and use EMIF1 only. In your comment, we can use PMHALModuleModeSet API in AppImage to disable EMIF2, this can also achieve our requirement, right? Do I need to use this API in each core image? That is why I want to disable it in SBL stage. Thanks~~

Hi, Yes you can use PMHALModuleModeSet API. You should call this API from A15 or IPU (only one call is needed). Regards, Rishabh

Hi, understand! Thanks~~

Hi Markii, Kindly mark the post that answers your query as "This resolved my issue" and close the thread. Regards, Rishabh

Ticket Name: TDA2P-ACD: TIDL performance comparison between TDA2P and TDA2

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Dear Champs, Is there any benchmark data of TIDL on TDA2P and TDA2? Do you think the TIDL performance of 2x EVE of TDA2P is similar with 4x EVEs of TDA2 because the CPU clock of TDA2P EVE is 40% higher than TDA2? My customer validated their algorithm on 4x EVEs of TDA2 using TIDL and feel there is not much CPU resource remained. Now, because of internal ISP, they are thinking of TDA2P but are afraid if their algorithm can be run on 2 x EVE of TDA2P. But, because the core clock of TDA2P EVE is higher than TDA2(900Mhz vs 650Mhz), I think the TIDL performance would be similar between 2x EVE of TDA2P and 4x EVE of TDA2. Could you please let me know your idea on this total TIDL performance of TDA2P and TDA2? Thanks and Best Regards, SI.

Hi SI, TIDL experts are looking at your questions, but in meantime you can check those threads for some details of TIDL performance evaluation: Regards, Yordan

Hi, By default we are not validating TIDL_OD usecase on TDA2px so we do not have any performance number for this on TDA2px plaform. We only run this usecase on TDA2xx platform and with TI's provided input files, you can get a FPS of 22-24 of Display. As we did not run this on TDA2px so we can not comment anything related to its performance on TDA2px. But its very easy to port the usecase on TDA2px and you can check the performance yourself. Please use OPP_HIGH(Higher clock speed for cores) MLO for running this usecase for both platforms. Regards, Praveen

Ticket Name: TDA2SA: About DDR Memory change Issue

Part Number: TDA2SA Other Parts Discussed in Thread: TDA2 Hi SIr We used TDA2 for development and we change the DDR P/N and size (512MB). Where should we modify about DDR timing setting and memory size setting ? As we know , we should modify SBL first. Do we need to modify other parts to let system can boot successfully and work well. ( for example : where to modify size for app image) please advise BR Yimin

Hi, You need to modify PROCESSOR_SDK_VISION_03_07_00_00\ti_components\drivers\pdk_01_10_03_07\packages\ti\boot\sbl_auto\sbl_utils\src\tda2xx\sbl_utils_tda2xx_ddr_config.c for DDR timing settings. You don't need to modify app image and Vision SDK as 512 MB is supported by default. Regards, Rishabh

Hi Sir thanks for your reply. Do you have any suggestion why it stopped in "Jumping to MPU CPU0 App" by using SDCARD/QSPI booting. We have done the DDR test without issue. BR Yimin

Hi, Is the DDR stable? Can you check individual CPUs and see if any CPU has crashed. What are the other changes that have made in SDK application? Can you also try SBL mbx image from PROCESSOR_SDK_VISION_03_07_00_00\ti_components\drivers\pdk_01_10_03_07\packages\ti\boot\sbl_auto\prebuilt_binaries\sbl_multicore_mbx\tda2xx and see if it works. Regards, Rishabh

Hi Yimin, You can also check the below app notes: http://www.ti.com/lit/an/spraca1/spraca1.pdf http://www.ti.com/lit/an/sprac36c/sprac36c.pdf Regards, Rishabh

Hi SIr We have tried to load using CCS and it can work. The Menu can show up. But it will hang at below message by using SDCARD booting. Jumping to MPU CPU0 App Do you have any suggestion BR Yimin

Hi Yimin, Have you made any changes in the gel files when you got the custom board working? If yes you should make sure that you have made same changes in SBL DDR configuration. Also do you have any other changes in SDK? Regards, Rishabh

Ticket Name: RTOS/TDA2: Can't add log string to "bsputils_lvds.c" and display it

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, As title. I studying SerDes control from CSL of SDK v3.3. I add "Vps_printf()" at BspUtils_appConfSerDeSer() to output debug string and information to console port. (I'm sure system has run to BspUtils_appConfSerDeSer() of bsputils_lvds.c) I run the use case "2. Multi-Camera LVDS Usecases -> 1: 4CH VIP Capture + Mosaic Display -> 0: For Single channel mode". And I can see image has received from CAM1 of vision board and displayed to monitor but can't see debug string from console port. Maybe I call the wrong API. Could you give me some suggestion? Many thanks. Debug string as below: Int32 BspUtils_appConfSerDeSer(UInt32 devDrvId, UInt32 devInstId) { Int32 retVal = BSP_SOK; UInt32 serI2cDevAddr; UInt32 ovInstId; Vps_printf("Enter: %s\n", __FUNCTION__); ....Hiden..... Vps_printf("Exit: %s\n", __FUNCTION__); return (retVal); }

Hi Prince, can you check if this helps: e2e.ti.com/.../2531375 Regards, Yordan

Hi Yordan, I will check first. Many thanks.

Hi Sir, I find just call GT_xTrace() if want to output debug information from CSL layer.

Hi Prince, GT Trace can be used in VPS drivers but not in CSL. Regards, Rishabh

I see, thanks for your feedback :)

Ticket Name: RTOS/TDA2: VPE scale function

Part Number: TDA2 Tool/software: TI-RTOS We successfully used the hardware VPE on the TDA2 to scale the image. We want to simulate VPE scaling on the PC side. Can you provide me with the C code or algorithm principle for analog VPE image scaling?

We don;t have C model for VPE

Ticket Name: TDA2: About File Reading issue

Part Number: TDA2 Hi Sir We used Vision-SDK (RTOS) for TDA2 platform. we met below issue We use File_open() and File_mkdir() api and write them in vision_sdk\apps\src\rtos\common\chains_main_bios_single_cam.c. We can read the content of our file in the root of SDCARD. if we put this feature in the canny.cpp of usecases selections "OpenCV Canny (A15) + Display". It always returns 0. Does TI have any suggestion? or we miss some steps? BR Yimin

Hi SIr We ChainsCommon_Osal_fileOpen and File_open to open file. 1. In chains_main_bios_single_cam.c -> it works 2. in canny.cpp -> it failed Does it have any rule ? BR Yimin

Hi Yimin, what exactly is the return value of File_open()? It should return -1 if file could not be opened, else file handle. Regards, Yordan

Hi SIr Yes. the result is 01 when I use the api in canny.c file in Alg_OpenCVCanny stage. our final purpose is to read xml file by using cascadeClassifier of opencv. cv::CascadeClassifier face_det; status = face_det.load(std::string("file.xml")); please advise BR Yimin

Hi SIr BTW , we found some issue in file_api.c in below definitation #if ( defined(FATFS_PROC_TO_USE_IPU1_0) && defined(BUILD_M4_0) ) || \ ( defined(FATFS_PROC_TO_USE_IPU1_1) && defined(BUILD_M4_1) ) || \ ( defined(FATFS_PROC_TO_USE_IPU2) && defined(BUILD_M4_2) ) || \ ( defined(FATFS_PROC_TO_USE_A15_0) && defined(BUILD_A15)) In alg stage (while running canny.cpp), we found that all of File_XXX were defined to return SYSTEM_LINK_STATUS_EFAIL in file_api.c. we have the question why we cannot use filesystem in this stage ? please advise BR Yimin

Hi, What is value of FATFS_PROC_TO_USE is your cfg file and where are you running Alg_OpenCVCanny link? Regards, Anuj

Hi, Is there any update on this thread? Regards, Anuj

Ticket Name: RTOS/TDA2PXEVM: Global variables not initialized in IPU ( M4 )

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS When we try to run a Algolink ( VSDK 3.03) which was earlier running on A15 in IPU on TDA2P, we see the uninitialized global variables are not getting initialized to 0. Can you tell us if there is something we need to check on the compiler/linker options which might help.

Hi, By default the memory map sections for VSDK is uninitialized to reduce the boot up time. If you want initialize some global variables then you can create 1 section in cfg file under bss section and map it with IPU1_0_DATA_MEM and assign its type as "INIT". And map your global variables to this new section. Please refer to autosarIpcShm section in VSDK3.5 release onwards. Regards, Anuj

Hi Poorva FYI, there is a build option also available, but this one will apply globally to all uninitialized variables, arrays etc. and this can impact on boot time. --zero_init=on So as mentioned earlier, Zero init a specific section would be the recommended option. BTW, you do not need this logic at all, if your C code is capable of performing all the required variable initialization at run-time! regards, Shiju

Hi Shiju, I made --zero_init=on for LNKFLAGS_GLOBAL_ipu1_0 and LNKFLAGS_GLOBAL_ipu1_1 in source\vision\platform\ti\tda2\build\rtos\makerules\build_config.mk. file. After this change I checked the global variable values again but they weren't still initialized. Could you please mention the location where the change needs to happen? Also, in the same file for LNKFLAGS_GLOBAL_a15_0, no value for zero_init was set. Is that correct?

Hi Poorva Yes, your changes are correct, I doubt there may be some other make files overriding your changes Please do a grep in /vision_sdk/build folder and make appropriate changes if any cfg/make files overriding your changes regards, Shiju

I searched all the places where zero_init is off for IPU1_0 in the vision_sdk/build folder, but there is no override. Any other possibility do you suspect for it to be not working? Does zero_init has to be set with any other combination of compiler/linker options? I had explored cinit_compression option but there is no effect with it's value also.

Poorva We have used this in C66x & M4 CPUs, with TI compilers. BTW, are you trying on A15 with GCC compiler? If yes, this combination is not checked! regards, Shiju

Hi Shiju, We are also using M4 CPU with TI compiler (i.e. cg_tools), but it doesn't work for us. Regards, Poorva

Poorva This needs to be checked again. Meantime can you check the first option described in the beginning of the post? regards, Shiju

Hi Anuj, I tried the solution you had mentioned, but is there any other solution that zero initializes all the global variables automatically as it is not feasible for me to initialize each one of them individually. I also tried the Shiju's solution but it does not seem to be working for us. Regards, Poorva

Hi, I hope you are doing this for a specific section only. You can keep some value in any variable which is in that section and after boot just check that 1 variable and if that has a value of 0 then it will work for the entire session. Regards, Anuj

Hi, zero_init flag works on DSP but not on IPU core so using that you will not be initialize variables to 0. You can try out the experiment which has been suggested earlier. You can map all your wanted variables to a section like below assuming section name is "temp" and variable name "gVar" #pragma DATA_SECTION(gVar, ".bss:temp") Then open below file links_fw/src/rtos/bios_app_common/${platform}/${core}/${core}.cfg and map your temp section to data_memory section of that core like below assuming you are doing it for IPU1_0 Program.sectMap[".bss:temp"] = "IPU1_0_DATA_MEM"; Program.sectMap[".bss:temp"].type = "INIT"; Regards, Anuj

Hi Anuj, Thanks for the response. This resolves our query. But we want to understand the reason of this restriction for IPU. Could you please help us understand that? Regards, Poorva

Hi Poorva, Are you asking for IPU or MPU. As the above example should work for IPU1_0 core. Regards, Anuj

Ticket Name: PROCESSOR-SDK-DRA8X-TDA4X: Why TIDL is disabled in TIOVX tutorial?

Part Number: PROCESSOR-SDK-DRA8X-TDA4X Dear expert, I got the question: Why TIDL is disabled in TIOVX tutorial? Background: You can find the code in psdk_rtos_auto_j7_06_01_01_12/tiovx/tutorial/ch01_common/vx_tutorial.c #ifdef _DISABLE_TIDL printf("tidl tutorial disabled when compiled in 64-bits host-emulation, please compile in 32-bits\n"); #else vx_tutorial_tidl(); #endif Could you please give some more explanasion on this warning? Does it mean TIOVX/TIDL can only run in 32bit on host emulation? What about on TDA4(A72/R5F/C7x/C66)? Thanks & Best Regards! ZM

Hello ZM, The TIDL tutorial is only supported on the TDA2/3 family of devices as it uses the EVE. We will make this more clear in future releases. For TDA4, we have several TIDL apps in the vision apps project (vision_apps/apps/dl_demos) that you can reference for how to use the TIDL node. Please let us know if there is something specific that you are looking for from the tutorial. Regards, Lucas

Thanks, Lucas. I will suggest our customer not to run it on TDA4/PSDKRA.

Ticket Name: TDA4VM: Is there any node in TIOVX execute the function as Null link in TDA2 VSDK?

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi team, Is there any node in TIOVX execute the function as Null link in TDA2 VSDK? which could be used do something in A72? In TDA2 VSDK, there is Null link which could do some process at A15 core and by callback function when receiving the images from other link while there isn't any node could do the similar thing on TIOVX, so it's difficult to process the image from camera in A72. The customer would like to know how to create new node to process image such as Null link in VSDK? Or is there any other nodes in TIOVX could do the similar thing on TIOVX? Best Regards, Cherry

Hi Cherry, Cherry Zhou said: Is there any node in TIOVX execute the function as Null link in TDA2 VSDK? which could be used do something in A72? No there is no null node in TIOVX. Cherry Zhou said: In TDA2 VSDK, there is Null link which could do some process at A15 core and by callback function when receiving the images from other link while there isn't any node could do the similar thing on TIOVX, so it's difficult to process the image from camera in A72. Do you mean null-sink link? i dont recollect if null-sink was doing any processing.. It can just receive input some other link and return the input as it is back.. There is not any node like this in TIOVX, but you could have output of node unconnected or can declare it as graph parameter and can get this output in the application. The above graph could be realized by opening capture node two times, one for 4 channels and second for 1 channel. 4-channels can be for encode and mosaic and fifth channel for the dms path. Regards, Brijesh

Hello Brijesh Nice to communicate with you. I'm the one post the question. and now this issue is fixed and closed by using a select node which created by PyTIOVX tools. But I'm not sure this is the best solution for this certain question. on the other side, it seems interesting to solve this question by opening capture node twice. could you kindly give the example code ? I wanna know how to implement this. Thanks and best rgds! have a good weekend.

Hi henry o, There is only one example in sdk, where multiple instance of the capture node are created. You could find this example in the file ti-processor-sdk-rtos-j721e-evm-08_02_00_05\tiovx\kernels_j7\hwa\test\test_csitx_csirx.c. This essentially is CSITX -> CSIRX example, where separate node instance is created for each input channel.. henry o said: I'm the one post the question. and now this issue is fixed and closed by using a select node which created by PyTIOVX tools. But I'm not sure this is the best solution for this certain question. That's interesting. Could you please help me understand what this select node is? If possible, can you share this node, so that it would be helpful? Regards, Brijesh

Hello Brijesh, Thanks for your kindly help and response. For select node, the input is object array contrains image frames which comes from capture node or something else, the output the another object array consists of images. e.g. there are 5 camera, channel [0,1,2,3,4], every one produce image frames at certain rate. and the first four should send their output into encode node and the fifth one should send to process the image. then we could create two select node, both of them take the 5 cameras' output as input, and the first select node choose the first four channel frames and copy the frame to output object array. the second select node choose the fifth channel frame and copy it to output object array. this select node works as the select link in vision sdk (or processor sdk in tda2x). wish it's helpful. best rgds.

Hello henry o, Thanks for the explanation. Just one more question, how do you copy images from input to output object arrays? Are just copying buffer pointer or images using DMA? Regards, Brijesh

Hello Brijesh, since it's a little difficult to use DMA copying the image buffer data, the memcpy is used here to copy the image. furthermore, I take account of copying buffer pointer, but it seems that it will bring the coupling issue, e.g. the pipeline could be blocked or slow down when some node processes the buffer pointer slower than expected. so, at last, the memcpy is chosen. Regards, Henry

ok understood, thanks. Please close this ticket if your question is answered. Regards, Brijesh

Ticket Name: Linux/TDA2EVM5777: How to build ELF firmware working with remoteproc using GNU tools?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hello *! I'm using the XC5777x Board with TDA2 Processor. Now I have to realize a baseline concept which fullfill the following requirements: A15 Core runs Linux and wil be the "Master" of the system. (This is works great!) All other cores have to be programmed "real bare metal", which means: no proprietary tools. No TI-Compiler, BIOS, RTOS... But I am not able to create any kind of working "ELF" file, which will be loaded and started successfully by remoteproc (Linux). All I got is "write error: Cannot allocate memory". This points to the kernel driver of remoteproc and crahes, if the section ".resource_table" can not be found or is empty, filled with garbish... ? But I can see such a section using "readelf"... But it do not work at all. I can put this section whereever I want... no success at all. I used some linker script and header-files from visual_sdk to generate such a section... but withous success. The linux runs well, because a "Prebuild" (!!) example, without sourcecode... works fine! (messageq_single.xem4) Do anybody ever build a firmware successfully for C66x and M4 subcore which works fine using remoteproc? Please help me out with an example of how it work. (Linker .lds file, header files, simple main.c, startup code (*.asm), Makefile... using GCC... no CCS, no SDK, please...) Thank you: Marco

I've notified the sw team. Their feedback will be posted here. Best Regards, Yordan

Ok.. Thank you very much. Additional informations can be found HERE: e2e.ti.com/.../2288499 TNX - Marco

Ticket Name: TDA2: EVE: Buffer transfer between ARP32 kernel and VCP kernel.

Part Number: TDA2 Hi, I have an application with three kernels, out of them kernel1 & kernel3 are in the kernel-C running on EVE_VCOP and kernel2 which is fully in natural-C running on EVE_ARP32. The execution graph is as follows: Input -> kernel1 -> kernel2 ->kernel3 -> Output. While executing kernel2, 'BAM_ARP32_computeWrapper()' function is called, wherein the buffers are used in ping pong format. So, the input and output buffer addresses are switched between IBUFHB, IBUFLB and IBUFHA, IBUFLA. The output of this kernel is passed as an input to the kernel3(). But, when I debug I see that kernel3() input address does not change according to the output. BAM has the responsibility to pass these buffer addresses but seems like it retains the addresses it got during kernel3_init() function. Is there any way to pass this addresses correctly at runtime? Also, I see that the input buffer address also toggles, but the output address of kernel1 is constant. So, will kernel2 take correct data in the alternate iterations? Regards, Shruti

Hi Shruti, For kernels running on EVE_VCOP, such as kernel 1 and kernel 3, it is normal that the addresses don't change. VCOP has a special memory mapping capability called ALIAS view, in which the addresses just need to point to image buffer A. The actual physical location is eventually determined by the buffer switch. Actually the upper bits are masked out, so what counts in the offset from the base address from image buffer A. For EVE_ARP32, ALIAS view is not supported so the processor needs to pass the correct addresses when calling kernel 2. So to me, the behaviour you are describing me is normal. regards, Victor

Hi Victor, I think my problem is different. I have three Kernels running sequentially one after other. Kernel_1 (VCOP)-> O/P Buf1 ->Kernel_2 (ARP32) -> O/P Buf2 -> Kernel_3 (VCOP)-> O/P For Display Current Scenario: - Kernel_3 (VCOP) while initialization time has input as O/P Buf2 address (say Address 1). - ARP32 works in PING-PONG style. So for each block processing it toggles it's O/P buffer O/P Buf2(Say Address1 and Address2). Now my problem is - As Kernel_3 holds only single address (say Address 1) as input and it can not change to Address 2 at run time. So how to change run time input addresses for Kernel_3 to get proper inputs?

Hi Shruti, Do you mean that all your kernels are called within one BAM node ? You will need to split into 3 BAM nodes. Node 1 executes kernel 1, Node 2 executes kernel 2 and Node 3 executes kernel 3. regards, Victor

Hi Victor, No, they are not present in a single node. They are in 3 different nodes. Regards, Shruti

Hi Shruti, I am affraid I don't understand the issue. Since kernel 3 is in a separate node, that executes on VCOP only, you don't need to change the address of the input since the buffer switch automatically takes care of which image buffer it accesses to, thanks to alias view. regards, Victor

Shruti, Can you respond to Victor's queries? Regards, Anshu

Shruti, Can you update us on this thread? Regards, anshu

Shruti, I am closing this thread as we haven't heard back from you. Kindly re-open this thread if you have further questions. Regards, Anshu

Ticket Name: CCS/TDA2: How I load the Big image in DDR through Emulator (*.OUT FILE)

Part Number: TDA2 Tool/software: Code Composer Studio Dear Sir, i want to Upload the Image size of almost 15MB in TDA2x DDR. so i just include the image in my Main.c file. now CCS now not able to build the file. so my question is that can we upload the image file in the DDR through the emulator or *.out file. please help me how i can upload the image in DDR. thank you

Hi, You can use loadraw command from CCS. Please refer to software-dl.ti.com/.../ccs_scripting_console.html Regards, Rishabh

thanks for your Reply Rishabh now i am trying to upload the image through the Load command but i am facing different problem like secession not start i try with the following command script = ScriptingEnvironment.instance(); script.traceBegin("dssLog.xml"); debugServer = script.getServer("DebugServer.1"); debugServer.setConfig("D:/workarea_tda2x_new/testing_1234/targetConfigs/TDA2x.ccxml"); debugSession = debugServer.openSession(".*"); and got the following response could not open session.

Hi Vijender, You don't need DSS scripting. You need to run below command in CCS scripting console loadRaw(0x80000000,PAGE_PROGRAM,"C:\\Work\\image.tigf",32,false); Regards, Rishabh

thanks Rishabh now this is working fine .

Hi Vijender, Thanks for the confirmation. Regards, Rishabh

Ticket Name: TDA2: Deep learning algorithms run very slowly on DSP(TDA2xx)

Part Number: TDA2 Hi, Deep learning algorithms run very slowly on DSP(TDA2xx) image size is 512x256. ### CPU [ DSP1], LinkID [ 49], [IPU1-0] 831.681815 s: [IPU1-0] 831.681845 s: [ ALG_TIDL ] Link Statistics, [IPU1-0] 831.681937 s: ****************************** [IPU1-0] 831.681998 s: [IPU1-0] 831.682028 s: Elapsed time = 633812 msec [IPU1-0] 831.682120 s: [IPU1-0] 831.682272 s: New data Recv = 0.2 fps [IPU1-0] 831.682364 s: [IPU1-0] 831.682394 s: Input Statistics, [IPU1-0] 831.682455 s: [IPU1-0] 831.682516 s: CH | In Recv | In Drop | In User Drop | In Process [IPU1-0] 831.682577 s: | FPS | FPS | FPS | FPS [IPU1-0] 831.682669 s: -------------------------------------------------- [IPU1-0] 831.682760 s: 0 | 0. 1 0. 0 0. 0 0. 1 Computational complexity: thanks!

Hi, can you check this post by Kumar and update "deploy.prototxt " parameters as described and see if it improves the speed: e2e.ti.com/.../689617 Regards, Yordan

Hi, deploy_512x256.rarAbout eep_top_k: 20 confidence_threshold: 0.15 1. I don't have these two variables in my file (deploy.prototxt) . 2. I want to run four networks on tda2x at the same time. 1camera (video input)---------->first network on DSP_1 2camera(video input)---------->the second network on DSP_2 3camera(video input)----------->the third network on EVE_1 4camera(video input)---------->the fourth network on EVE_2 EVE_3 EVE_4 The network is running slowly on the DSP. Is there any way to improve it? Thanks!

Refer The data sheet for performance comparision between EVE and DSP. We dont see much scope the improve the performnce of DSP

Ticket Name: Linux/TDA2: what is /home/1920x1080_00.hdr

Part Number: TDA2 Tool/software: Linux in usecases\null_src_decode_display\chains_nullSrc_Display.c strncpy(pPrm->channelParams[chId].nameDataFile, "/home/1920x1080_00.h264", 260); i think is in put src vedio strncpy(pPrm->channelParams[chId].nameIndexFile, "/home/1920x1080_00.hdr", 260); but what is this ? for what ?

Hi, .h264 file -> input src file .hdr file -> Index file (size of each frame of input src file) Regards Suryamani Jena

Hi Suryamani Jena but how can i get .hdr file ,i only have .h264 vedio Regards shuai

i think in the SDK should give some file as an example!

Hi shuai, You can generate .hdr file from .h264 file (follow below steps) Required software: FFmpeg ----------------------------------------- Creating index file from input src file ----------------------------------------- Create index file ffprobe.exe -show_packets input.h264 > index.idx On Linux machine: Extract just "Size" from above generated index file with sed command. PAT=size sed -n "/$PAT/p" index.idx | cut -d' ' -f3 >> size_extracted.txt Now generate binary file from size extracted file, with below command. Please note that " size_extracted.txt should not contain any string just numbers i.e size of frame " cat size_extracted.txt | perl -n -e 'printf("%08x\n",$_)' | sed 's/\(..\)\(..\)\(..\)\(..\)/0x\4\n0x\3\n0x\2\n0x\1/' | xxd -r -p > Size_test.bin && du -b Size_test.bin Rename Size_test.bin as input.hdr and use it as index file Regards Suryamani Jena

Ticket Name: CCS/TDA2: how to remove symbol tables from compiler Libraries

Part Number: TDA2 Tool/software: Code Composer Studio Hi : i use ccs compiler Libraries, now i want to remove symbol tables from Libraries , What compilation options should i use?

Hello, If I am understanding your question correctly, one way to do it is from the CCS build options menu. Sample screenshot below. Hope it helps, thanks, Alex

Ticket Name: PROCESSOR-SDK-DRA7X: TDA2: How to Config GPU IdleMode to Smart-idle mode

Part Number: PROCESSOR-SDK-DRA7X Hi, Because of reducing GPU power consumption, we would like to know the power consumption in smart-idle Mode, Please provide the method to config GPU idle mode to smart-idle. I use PROCESSOR_SDK_VISION_03_05_00_00. br, KS.

Hi KS, I don' think that there is anything called smart-idle mode for GPU power saving. There is one way to save GPU power is to set its frequency to OPP_NOM, but it is not dynamically supported. Thanks RamPrasad

Ticket Name: TDA2P-ABZ: How to run neural networks on this board

Part Number: TDA2P-ABZ Other Parts Discussed in Thread: TDA2 Hi, I developed a couple of neural network and I would like to run them on this board. At first I would like to run an example model with and without EVE support. I have downloaded and installed the SDK from here: https://software-dl.ti.com/processor-sdk-vision/esd/TDAx/vision-sdk/latest/index_FDS.html But I cant any real guide on how to move forward. I understand I have to use TIDL (which to my understanding is deprecated now so maybe edge Ai?). Is there a step by guide to running models on the this platform? Thanks.

Hi, You can refer to user guide mentioned in the Docs folder for the build and run steps. Also, refer to these VSDK training videos to get more details on the sdk, I would recommend to go over these videos first to get overall idea before start building the SDK, https://training.ti.com/introduction-processor-sdk-vision Thanks, Praveen

Can you please refer me to a guide to how I can convert my own models so that I will be able to run them on the TDA2 EVE?

Hi Arik, Please refer to section "3.6 Running a Model trained by user" in the TIDL user guide (TIDeepLearningLibrary_UserGuide.pdf located in ti_dl\docs folder) for more details. Thanks, Praveen

Ticket Name: TDA2SX: Tda2s SPI slave mode reception problem

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hello, expert Tda2s is SPI slave mode. If the master sends a 1MHz clock and sends 140 bytes every 20ms, it will get stuck after receiving several times. If it sends 32 bytes every time, it will not get stuck. If it sends 32 bytes every 10ms, it will still receive several times of data and it will get stuck. dmesg1.txt   146 root      0:00 [kworker/0:1H]
  148 root      0:00 cat /proc/kmsg
  149 root      0:00 ps
root@dra7xx-evm:/app# 
root@dra7xx-evm:/app# ./spi_rev_tool_32 -D  /dev/spidev1.0  -s 1000000 -b 8
[   36.808325] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0
[   36.809212] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0
[   36.810092] spidev spi1.0: setup mode 0, 8 bits/w, 1000000 Hz max --> 0
<7>[   36.808304] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal
<4>[   36.808325] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0
<7>[   36.809182] spidev spi1.0: spi mode 0
<7>[   36.809198] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal
<4>[   36.809212] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0
<7>[   36.810065] spidev spi1.0: 8 bits per word
<7>[   36.810079] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal
<4>[   36.810092] spidev spi1.0: setup mode 0, 8 bits/w, 1000000 Hz max --> 0
<7>[   36.810946] spidev spi1.0:   xfer len 32 rx tx 8bits 0 usec 1000000Hz
<7>[   36.810973] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal
RX | 4D 56 00 00 10 9A 00 00  | MV...?.
RX | 01 01 00 00 00 00 00 00  | ........
RX | 00 00 00 00 00 00 00 00  | ........
<7>[   36.826262] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal
<7>[   36.826462] spidev spi1.0:   xfer len 32 rx tx 8bits 0 usec 1000000Hz
<7>[   36.826487] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal
<7>[   36.827021] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal
<7>[   36.827126] spidev spi1.0:   xfer len 32 rx tx 8bits 0 usec 1000000Hz
<7>[   36.827149] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal
 I add printing when I can't receive hand data, it's stuck in SPI_ transfer_ one_ message()---->master-transfer_ one(). How to find the problem? The problem of the master side has been ruled out, and the measurement SPI CLK CS is normal.

Hi, Our Linux SDK doesn't support SPI slave mode. It has not been validated on TDA2 EVM. Regards, Stanley

Ticket Name: PROCESSOR-SDK-DRA8X-TDA4X: Better understanding the Processor SDK RTOS Automotive source structure

Part Number: PROCESSOR-SDK-DRA8X-TDA4X Hello, we are analyzing Processor SDK RTOS Automotive with goal of using it for software development for TDA4 SoC based platform. We have years of experience with TDA2 SoC and Vision SDK, so shifting to newer TDA4 SoC and new SDK is giving us trouble to understand how are Linux and RTOS part of SDK supposed to work together? When we make Linux SDK, what are the outputs we need for the system boot, and what are the outputs we need for the RTOS SDK, and vice versa? Also how do we build RTOS now from RTOS SDK, it has very complex build system with a lot of build targets, and we cannot quite grasp how do we distinguish what builds the use-case applications, and what builds the RTOS OS, nor what is the source structure for the system and what is the source structure for the use-case applications inside RTOS SDK? Regards. Uros

Hi Uros, Well different directories have different components, just like vision sdk. tiovx is core openvx frame implementation, whereas vision apps contains different demos, which internally uses all other components, ie tiovx, pdk, ipc etc.. Usually, we just use vision apps and build everything from vision apps. Rgds, Brijesh

Ticket Name: CCS/TDA2: Run Sample C code on DSP or EVE

Part Number: TDA2 Tool/software: Code Composer Studio Hello Sir, I have written Sample Custom layer[Relu] in C how to run on DSP or EVE. Thanks Madhav

Hi Madhav, Can you provide more information. Are lookin for help in compling the code or linkingiwth your applications etc?

Hello Sir, I am trying to Run ReLu(as custom layer example) on DSP or EVE or ARM processor. My ReLu Layer will be expecting Output from one Sub-Network and output to the next Sub-Network running on other core. Firstly, So i need to know how to run the custom layer which is written in C code on DSP/EVE/ARM core separately, then i ll try to link the subnetworks to my custom layer. Thanks, Madhav

You can compile the C code using TI compilers for DSP/EVE and then you run them standalone (refer EVE SW user guide) or in the complete system with SDK (refer SDK user guide) Refer Top Level SDK documentation to navigate to various user guides

Hello sir, I have compiled c code using TI compiler for EVE target. when i am trying to run on TDA2x board getting this error file cant able to load. whether i need to write linker file to configure with memory. ARP32_EVE_1: Trouble Reading Memory Block at 0x6100 on Page 0 of Length 0x4: (Error -1065 @ 0x6100) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.903.2) ARP32_EVE_1: File Loader: Verification failed: Target failed to read 0x00006100@Program ARP32_EVE_1: GEL: File: C:\Users\Madhav\workspace_v8\rlu\Debug\rlu.out: Load failed. Thanks , Madhav

refer below EVE doc for running code on EVE with required GEL files modules\docs\eve_sw_getting_started.pdf

Ticket Name: TDA2EXEVM: How to measure total processing time for one frame in TIDL_OD usecase

Part Number: TDA2EXEVM Hi Team, This is regarding the total processing time for one frame in TIDL_OD usecase running on TDA2x. To measure it, my customer tried following two ways: (1) To accumulate Local Link Latency (average) of each Link from Source Link to Display Link, took only one pipeline for EVE. -> 313 ms (2) Simply check Source to Link Latency (average) in Display Link -> 220 ms Please find attached log and excel sheet for calculation. As you can see, there is a gap between the number (1) and (2). log_Sparse_A-manual.txt Sparse_A-manual_latency_en.xlsx - Which one is the correct way of measuring the total processing time for one frame? - What is the reason of the gap? Thanks -Shibata

Hi, You can be calculated in both methods but 1) In the first method, you should not include "SYNCH" link latency. Thanks Gaviraju

Hi Gaviraju, Thanks for your comment. By removing SYNC Link latency from (1), I got a similar number with (2). Actually I saw a large difference between MIN number and MAX number in SYNC Link latency. That might affect the total processing time. But could you please explain why we can exclude the SYNC Link as it is also running in the chain? Thanks & Regards, -Shibata

Hi, Please refer & try to understand what sync link is doing. Source file: vision_sdk/links_fw/src/rtos/links_common/sync. But I have another best option to measure total processing time for 1 frame. Add the below lines of code in the first link( beginning of the link process function) UInt64 startTime; startTime = Utils_getCurGlobalTimeInMsec(); Vps_printf("%llu", startTime); Add the below lines of code in the last link( end of the link process function) UInt64 endTime; endTime= Utils_getCurGlobalTimeInMsec(); Vps_printf("%llu", endTime); Now you can see the output of startTime & endTime in the print console, take the difference & this is the total processing time for 1 frame. totalTime = endTime - startTime Thanks Gaviraju

Ticket Name: RTOS / TDA2EG-17： AVM Solution on TDA serial

Part Number: TDA2EG-17 Tool/software: TI-RTOS Hi TI expert I have some questions. Q1. Could i TDA2EG-17 receive 4ch 1280P or 1080P @ 30 Yuv422 (8bit) on VIP ? if can't , How about TDA2-EG or TDA2P ? Q2.Could i use D0~D7 output 1080P @30fps Yuv422 BT.601/BT.656 on the TDA2EG-17 LCD3 Port ? I implemented D0~D7 output 720P @ 30fps Yuv422 BT.601 on the TDA2EG-17 LCD 3 port. Q3.From above questions,should I use 913 and 914 to transfer data or 933 and 934 to transfer?

1. A single VIP port can capture 8-bit 1080p @ 30 FPS or 720p @ 30FPS. Kindly refer to the device/part manual to see if all the 4 VIP pins can be used. Also as long as the input to the VIP is less than 165 MHz, then it can capture 1920x1280p as well. 2. 1080p30 8-bit is not validated in DSS driver 3. Kindly refer to serializer manual to check if it supports the required pixel clock

Ticket Name: RTOS/TDA2: What IP can receive PWM signal and calculate duty percentage?

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, I need receive PWM signal from external device. Seem like timer IO can achieve it. Could you please advice me what IP can support this request? Many thanks,

Hi Prince, For some simple use-cases, I think you can use timers indeed. Otherwise you can leverage the features of a specialized module called Enhanced Capture (eCAP) Module. You can see hardware details in the TDA2x TRM document. Regards, Stan

Hi Stan, Understand, thanks.

Ticket Name: Linux/TDA2: sxgFrmcpy and Display buffer : image data modify issue

Part Number: TDA2 Tool/software: Linux Hi Sir, My HW is TDA2x CPU board + Vision Board + daughter board + OV1652x sensor and SDK is PROCESSOR_SDK_VISION_03_04_00_00 with TDA2XX_EVM_LINUX_ALL define. I select use-case "4CH VIP LVDS capture + SGX MOSAIC + DISPLAY" . I changed the code like below steps: 1. I found the image capture buffer address in "SgxFrmcpyLink_drvDoProcessFrames" function, image point is "pVideoCompositeFrame->bufAddr[0][0]" 2. I try to modify the image data or clear data buffer in this function. ex. compostive_video_buf_addr = pVideoCompositeFrame->bufAddr[0][0]; memcpy(compostive_video_buf_addr, 0x00, 115200); or for (int i=0; i<57600; i++) compostive_video_buf_addr+i = 0xBBBBBBBBBBBBBBBB; 3. compiler and select use-case, 4.TV shows a strange image, I attached the image file. The image seems noisy and mix up the original capture image. I have no idea whta's happen and how to fix it. Ranny.

Hi, If you are modifying the buffer data then the output will be noisy. Still can you check inside display link when you get the data then what the value inside that. Is it same as you changed or something else. Regards, Anuj

Hi Sir, No, I check the display link, the data isn't changed as I expect. Even I print out the data buffer in sgxFrmcpy link before I modify the data, the data is not correct either, most time is 0.

Hi, Can you please let me know why are you changing the data. Whats the purpose for it. Regards, Anuj

Hi Sir, Our customer asks us to do that, They need a simple demo with some image modify. I am looking for a faster way to reach the request for their demo. Thanks. Ranny.

Hi, Can you modify the data inside display link only. Just for experiment modify the data in capture link also and check whats coming in your display link. It will be hard to identify that your changes are coming into display or not. As after modification you will get a strange image. Regards, Anuj

Hi Sir, It's working that modifying image data inside display link, but TV display becomes serious lag. Thanks. Ranny.

Hi, If you do some memory oprartion then it will increase the processing time of that link hence of the chain. Try to modify a small region only. Regards, Anuj

Hi Sir, ok, thanks. Ranny.

Ticket Name: TDA2EXEVM: the detection result of PC and tda2 is different

Part Number: TDA2EXEVM Hi, Team. I trained a SSD Caffemodel to detect the targets on the road. The test results on the PC are basically normal, as shown in Figure 1. However, when the model is converted with TDA2XX and then tested, the results are abnormal, as shown in Figure 2. In Figure 2, the red box is the ground truth, and the green box is the detection result. The result box of the class obstacle at the top right is very wide. Could you please help me with this problem? Thanks.

Did you trine the model using, Caffe-jacinto? If not please train the model using the caffe-jacinto quantization aware training to get better accuracy on target. Would it be possible for you to share details on your Project and requirements? Wanted to make sure, your target application can be supported on TDA2x/3x, or will it be better to try TDA4x devices If it helps, can you consider trying your model with our TDA4x/AM2x-based tools available here https://github.com/TexasInstruments/edgeai-tidl-tools https://www.ti.com/tool/SK-TDA4VM https://www.ti.com/tool/SK-AM62

Ticket Name: CCS/TDA2: EDMA_UTILS_globalReset(); how to use

Part Number: TDA2 Tool/software: Code Composer Studio In my project, there are 7 parts. Each part needs to move data from DDR to L2 by DMA and then do operations. I imitates the pingpang pattern in SDK_VISION_03_02_00_00\ti_components\algorithms\REL.DMAUTILS.00.08.00.02\dmautils\test\edma_utils_autoincrement_test. A EDMA_UTILS_globalReset () is called when the project is initialized; but the first two parts are normal when the int status = biasDmaAutoIncrement__Init returns a value, and the back value of the next 5 parts is a -1 description of the configuration failure. Then I call EDMA_UTILS_globalReset () once at the beginning of each part; the latter part can work, and finally I want to ask EDMA_UTILS_globalReset (); should it be called once or when you need to use it again?

Hi Shuai, Can you explain what you mean by parts? Does it mean that you have 7 transfers which you want to do for each trigger? EDMA_UTILS_globalReset () is supposed to be called only once per frame. Regards, Anshu

Hi Anshu cpu reset start main , Initialization mem , read a image , call fun1, call fun2, call fun3，call fun4，call fun5，call fun6，call fun7 return. in each fun copy data from DDR to L2 and copy data to DDR. I think EDMA_UTILS_globalReset () should call once in Initialization ?? BESTWISHES

Shuai, Basically if you call EDMA_UTILS_globalReset for each function then it will release all the resources and re-allocate for each of the fun*. So it should be ok only to call it once before fun1. In this case each of the transfer will happen on different DMA channel. Regards, Anshu

Ticket Name: Linux/TDA2: How many ethernet phy chips can be supported on TDA2X?

Part Number: TDA2 Other Parts Discussed in Thread: DP83865, DP83640 Tool/software: Linux Dear TI, We found DP83865 ethernet phy chip on EVM board. Is there another ethernet phy chip can be supported on TDA2X? Which driver is ready? Thanks a lot! waley

Hello Waley, Selection of PHY would depend on your use-case requirements. Can you please let us know your use-case? On TI TDA EVMs we are using DP83867 (http://www.ti.com/product/DP83867IR).

Dear Prasad, For our case, 10/100M baseband is enough, it seems DP83640 is ok. But I'm not sure if we need to change driver code when we replaced the phy chip to another one. waley

Waley Are you planning to use ethernet from Linux or from TI BIOS(on M4 core). Linux includes a generic phy driver that should work for most cases. Additionally there are specific PHY drivers if there needs to be PHY specific configuration. List of PHY drivers and their supported versions can be found under drivers/net/phy/Kconfig file under the kernel sources. If the specific PHY part has a driver, you need to enable the same in kernel and update the phy binding string in the device tree for the board that you are using

Ticket Name: TDA2: I want to buy a ADAS Development board

Part Number: TDA2 Dear: I want to buy a ADAS Development board. Can you give me some video of LDW,FCW,TSR,,PDS base on TDA3x and TDA2x , My Email address is welcomezyh@163.com. Zhang

Hi - You may find some CES youtube videos for these demo. https://www.youtube.com/watch?v=lBXmCEYdqio TI www also has details for EVM purchase etc. regards yashwant

Ticket Name: RTOS/TDA2: TIDL ssd result different on EVE platform and PC

Part Number: TDA2 Tool/software: TI-RTOS Hi: I trianed an ssd model, buf found that the result is different between the eve platform and PC host emulation in some video frame

Hi Can you share the make command used for building PC host emulation ?

gmake TARGET_PLATFORM=PC TARGET_BUILD=release CORE=eve all and gmake TARGET_PLATFORM=PC TARGET_BUILD=release CORE=eve RUN_REF_FOR_STATS=1 all i try both the above two command, but the result is similar.

With the below command it is expedted to match with EVE target gmake TARGET_PLATFORM=PC TARGET_BUILD=release CORE=eve all but not for the other. Can you enebale layer level trace for PC and target and locate the miamatching layer

how i can enable layer level trace , and when enable the layer level trace what Ican see?

do you mean I can enable layer level trace by enable below define? #define ENABLE_TRACE_DUMP (1) but when I enable this, on the eve platform i can not successfully build appimage on pc, when enable this define, i can get layer level trace data.

Hi how i can enable layer level trace for target. thanks.

You need to build standalone test application for EVE and run using JATG and CCS

Hi: when i load eve_test_dl_algo.out, i encountered follow problem: ARP32_EVE_1: Trouble Reading Memory Block at 0x0 on Page 0 of Length 0xad: (Error -1065 @ 0x0) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.232.0) can you help me to look at what the probelm. i can load dsp_test_dl_algo.out successfully.

i use simulator to run the standalone test, but i can not get layer level trace data. And the result between standalone test and PC differs some pixels for the detected box, is this expected.

Can you check below flag in *multicore_reset.gel for loading code in EVE #define EVE_SW_CONFIG 1 /* Applicable for EVE_SW users only * Effective only when * VISION_SDK_CONFIG == 0 */

Target execution shall mathc with host emualtion (gmake TARGET_PLATFORM=PC TARGET_BUILD=release CORE=eve all)

in which package and which directory i can find *multicore_reset.gel thanks

thanks, i find the .gel file

i still can not load program into eve with jtag. i changed the value you said.

i import the same input to platform, finally we get the result with one pixel difference compared with pc. through this, we think, with the same input image, the output from vpe and tidlpreproc link is different from pc in which we use opencv get the rgb data from the input image.

Ticket Name: RTOS/TDA2: How can I verify SSD model be used in SDK v3.03 ?

Part Number: TDA2 Tool/software: TI-RTOS 1. How can I verify SSD model be used in SDK v3.03 ? 2.Has any document can verify the algorithm add SSD model is better than old one? I can't find any document . So I want to know the answer of this question. Thanks.

Hi Allen , Are you looking for how to run the usecase or SSD model .? to run the usecase we have it documented at VisionSDK_UserGuide_TI_DeepLearning.pdf under vision_sdk\docs\FeatureSpecificUserGuides sections: 3. TIDL file I/O use case 4. Build and Run Semantic Segmentation use case 5. Build and Run TIDL Object detect use case explains how to use / verify SSD model usecase Regards Chetan.M

Hi Allen, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Hi, I Have the user guide suggested files. but I cannot run the TIDL_OD use case How can I run the TIDL_OD use case? and what configuration I must to setting?

Hi Allen, this topic will be discussed in this thread: e2e.ti.com/.../688587 Regards, Yordan

Ticket Name: TDA2P-ACD: balls AA1,AA2,AB1,AB2,AC1,AC2

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2, DRA77P Hi. (1) There is no mech.drawing of ACD(784-balls)-package in datasheet. Do I need to use ABC(760-balls)-package drawing as reference for my design? (Does it have the same size and pitch? Is ABC the same as ACD but only 24 balls are excluded?) (2) There are no any description about 6-balls in TDA2P-ACD-datasheet: AA1,AA2,AB1,AB2,AC1,AC2. Where I can find info about Pullup or Pulldown requirements for these balls if they are unused? These balls marked as MLBP-pins in SD TDA2P_EVM design (see picture). Is DRA7x TRM applicable for reference TDA2 MLBP description? But, do I need to use DRA7xxP datasheet for reference about these balls? --- best regards

Hi Arseniy, 1. As layout - yes, ACD is the same as ABC, but includes missing balls - 23 mm × 23 mm, 0.8-mm Pitch. Note that ball-mapping is different - they are not pin compatible! Please also note that ACD have different dimensions: 2. Yes, these balls are unused in TDA2P devices. You should leave them unconnected. Thanks, Dian

Ticket Name: TDA2: Unable to clone opencv source

Part Number: TDA2 Dear TI I am able to clone the opencv source from the give link from the document The given link is from page 5 pointer 1.4 of document VisionSDK_UserGuide_opencx. please advise

Hi Willson, can you try to clone from http://git.ti.com/opencv: git clone git://git.ti.com/opencv/tiopencv.git Regards, Yordan

Ticket Name: Compiler/TDA2: EVE/KernelC :- Optimization techniques

Part Number: TDA2 Tool/software: TI C/C++ Compiler Hello There, What are the EVE and/or kernel C optimization techniques ?? Do we have any document for the same?? Regards, Kajal

Hi Kajal, You can refer some examples in EVE software library released by TI to get some idea. Also please refer the TRM for EVE architecture, instruction set to correlate the software examples with the hardware architecture. Regards, Anshu

Hello Anshu, For now we don't have the TRM for EVE, once we get that we will go through it. But in meanwhile can you please tell us how to reduce the clock cycles in terms of cache & hardware memory utilization. In case of kernel C programming, we have optimized using 16 SIMD width. Do we have any further scope for optimization in Kernel C programming?? Regards, Kajal

Hi Kajal, EVE doesn't have data cache so there is nothing in terms of cache which can improve performance. Once you have optimized kernels ready then next step would be to set up DMA/ VCOP pipeline in such a way that you can find the data movement via DMA behind VCOP compute. You can refer app\morphology applet to see how it is done. Regarding kernel C optimization I would request you to go though EVE's programmers guide. To get access to this document please contact your local TI contact person. Regards, Anshu

Hi Kajal, We haven't heard back from you on this thread. Were you able to make progress? If yes please close this thread. Regards, Anshu

Ticket Name: TDA2P-ACD: Custom calibration tool for 2D SRV

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Hi all, I am trying to make a custom calibration tool for 2D surround view in Python with OpenCV that would match the existing one developed in Matlab. So far, I managed to implement the same workflow and to obtain the parameters of initial perspective metrices for 4 cameras with stitched bird view as shown in the image below. As can be seen, the bird view image is decent. However, when I provide the obtained perspective matrices (scaled to match Q11.20 format that I believe is used in GeometricAlignment and Sythesis algorithms), I get the result which is not even comparable to the one shown above, i.e., everything is distorted. This indicates that matrix parameters are wrong or incorrectly interpreted. To confirm that the perspective matrix coefficients are correct I used the same values in another framework (Octave) and I get nice bird view for each camera (I provide a view for front camera below). The question is what I am doing wrong and why I do not get (at least to some extent) correct bird view on the target? Best regards, Mladen

Just an additional note. I also tried to use perspective matrix generated by the tool for provided sample images in both Python and Octave. All I got is also distorted indicating that the TI tool does not provide the matrix coefficients expected by OpenCV warpPerspective() and Octave imperspectivewarp().

Did you compare bin files from your python with the bin files from TI tool?

Hi Do-Kyoung Kwon, I am not sure what bin files are you referring to. Currently, I am trying to get initial perspective matrices that would be comparable with the one obtained from TI tool. So far I found out that OpenCV and Octave functions returns forward mapped homographies, however, the SV algorithm is based on back-mapping. Therefore, I tried to use inverse matrices, but it seems that it does not work either. Now I suspect it has something with translating the image center to 0 instead of (width/2, height/2).

Oh.. I now realized that you are working on SRV on TDA2. I thought you are working on SRV on TDA4.

Right. It is 2D surround view running on C66.

I think image center could be a reason. There might be no issue with perspective matrices give that you got the right reconstruction for the upper part of SRV. But it seems hard to say without debugging.

Actually, I got the right reconstruction on all 4 views as you can see in the first image (this is an output from Python tool). The issue arises when I provide the obtained matrices to the usecase (GeometricAlignment link) or to the Surroundview.exe tool for further perspective matrices tuning. It seems that those initial matrices are not in the form expected by the current implementation. I will also check for the image centers, but anyway, thank you for your time.

Great to hear that you resolve the issue.

No, the issue is still unresolved. I am chasing the way to adjust the perspective matrices to match the required format.

I figured this out. Image centers are just one side of the coin. Input images relative to output view orientation should be considered as well. Obviously, a rule for feature points (corners selected in reference image and input images) correspondence I used in my custom tool is different from the one in the TI tool, so I had to add some rotations to the input images (and output results) to match them. It is very specific to my case, but it would be informative if you could share somewhere in the documentation how the corners selected in the tool on reference image corresponds to the corners selected on the input images for each camera view.

Great! Thanks for the suggestion, too!

Ticket Name: Compiler: how to run code on J7 C66 core

Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi : befor i have run my code on c66 of TDA2 evm , I use CCS to compile our algorithm into a static library of C66 and put it into the vision SDK, which is called in the framcopy link of C66。 now i have change to J7evm . I have make sdk make vision_apps and run follow app on the EVM . but i can't run app_tirtos how to compile it ? i can not find sample usecase and framcopy links in psdk_rtos_auto_j7_06_01_00_15 . how can i run my code on c66 now ./run_app_tidl.sh - Image classification demo (needs display) ./run_app_tidl_avp2.sh - Auto valet parking demo (needs display) ./run_app_dof.sh - Dense optical flow demo (needs display) ./run_app_stereo.sh - Stereo disparity demo (needs display) ./run_app_c7x.sh - C7x sample kernel demo ./run_app_srv.sh - 3D SRV 4 camera demo (needs display, Fusion1 board, 4x IMX390 camera) ./run_app_single_cam.sh - Single camera + VISS + Display demo (needs display, Fusion1 board, 1x IMX390 or compatible camera's) thanks shuai

Shuai, On TDA4x we have switched to OpenVx framework from the links-and-chains framework on TDA2x. You can take a look at one of many examples in the TIOVX library for getting a kernel executed on C66 DSP. For TIOVX tutorials please start here, psdk_rtos_auto_j7_06_01_00_docs_only/tiovx/docs/user_guide/index.html The run_app_tidl_xxx variants use a mix of underlying cores such as R5Fs, HWA, C66 and C7x DSP running multiple kernels and can be run without display as well. You can set the display_option flag to 0 to turn off display and enable file write option as well to see the outputs. Please take a look at the documentation of vision_apps here, psdk_rtos_auto_j7_06_01_00_docs_only/vision_apps/docs/user_guide/index.html Regards, Shyam

Ticket Name: RTOS/TDA2: Object detection usecase

Part Number: TDA2 Tool/software: TI-RTOS Hi Everyone, I am working on Object detection usecase with VSDK 3.1 on TDA2X , I need to add some more objects to detect . 1) i wanted to know how to train / add new object data for the usecase to run 2) I have tried tidl od usecase with some random videos I had and default bin files (NET.BIN,PRM.BIN) from the PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/apps/tools/TIDL_files path , it created the output bin file but I am not sure what to do with it ?? 3) I couldn't find any documents other than VisionSDK_UserGuide_TI_DeepLearning.pdf in feature specific guides in the docs , is there any other documents available for deep learning in tda2x processor ? Thanks & regards , V.B.Surendar

Hi, Please migrate to latest VSDK release from www.ti.com/.../PROCESSOR-SDK-TDAX 1. Please refer to the steps mentioned here ( github.com/.../caffe-jacinto-models ) 2. Refer to below e2e thread for visualisation code, use that to visualise the output. e2e.ti.com/.../2502331 3. Please refer to FAQ's in "TIDeepLearningLibrary_UserGuide.pdf " in TIDL package. Thanks, Praveen

Ticket Name: Linux/TDA2: Recommended way to use EDMA in HLOS usecase

Part Number: TDA2 Tool/software: Linux Hello, I'm using Processor SDK 3.03 on Linux with kernel 4.16.7, building for custom board with TDA2 chip. I was wondering what is the recommended way to use EDMA in a HLOS usecase. While working with RTOS I used utils_dma.c but I can't seem to find anything like that in HLOS. Thank you in advance. Regards, Nick

Nick, Can you please confirm on the Linux kernel version - have you been referring to the Processor SDK Linux Automotive releases - these are based on kernel version 4.4 Typically for HLOS use case, the DMA is programmable from within the kernel as you would be programming the Physical address es for DMA parameters and you would want this to be validated and programmed from the kernel. On linux we have dmaengine I/F www.kernel.org/.../index.html and implementation for EDMA that subscribes to this interface on TI platforms. Various device drivers inside the kernel use dmaengine I/F. There are no direct API for using DMA from userspace applications on Linux

Hi Sriram, The kernel 4.16.7 is on my build machine and the one that is built and ran on the board is the one present in PSDK 3.03 (4.4.84). Is there any good example among the device drivers where I can see how dmaengine is used? Also, the link you provided is dead. Thank you in advance. Nick

NIck For the link itself, there is an appended ")" at the end of the URL which needs to be removed. I tried fixing it on the previous post, but somehow it is not taking effect. More details on the implementation, device driver usage and testing is described under www.kernel.org/.../provider.html www.kernel.org/.../client.html www.kernel.org/.../dmatest.html

Ticket Name: CCS/TDA2: CCS simulator memory allocation and fread problem

Part Number: TDA2 Tool/software: Code Composer Studio Hi, I'm trying to handle large data using C code in CCS with DSP simulator. however I challenged with two problems. 1. Allocation of large memory (dynamic allocation) I tried to allocate heap memory using malloc(). But when I tried large size of memory(for example, more than 300,000 Integers' array) it made problem and I found that the malloc() was failed because no address value has been allocated in the target array pointer. Is there any limitation for using heap memory at one time and can I modify it? Maybe I'll need many integers amount to 20~50MB. 2. Load Memory in real board I used 'Load Memory' tool in CSS simulator to load binary data onto memory. But if the size of data is reached almost 90MB. Then, what method is needed when I load the program on the real TDA2x board? Can I use 'Load Memory' on TDA2x board? Because I'm just using CCS simulator yet. I've heard about using SD card to load data onto memory. Which manual explains well about the load data from SD card? Thank you.

Hello Dongmin Cha, For the malloc failing are you making sure the linker command file of your project has a heap size which is larger than what you are allocating. For Load Memory: Yes the TDA2x board supports CCS Load Memory. Regards, Piyali

Ticket Name: phy network card not work in tda2(dra7-evm.dts) platform

Hi, My sdk version is "Version 03.06.00", I want to use phy that type is 88q1011 of mavell, then I add some device tree config in arch/arm/boot/dts/dra7-evm.dts like this: &mac { status = "okay"; dual_emac; }; &davinci_mdio { phy3: ethernet-phy@3 { reg = <3>; }; }; &cpsw_emac0 { phy_id = <&davinci_mdio>, <2>; phy-mode = "rgmii"; dual_emac_res_vlan = <1>; fixed-link { speed = <1000>; full-duplex; }; }; &cpsw_emac1 { phy_handle = <&phy3>; phy_id = <&davinci_mdio>, <3>; phy-mode = "rgmii"; dual_emac_res_vlan = <2>; /*fixed-link { speed = <100>; full-duplex; };*/ }; But it does not work,if I use fixed-link attribute,then can use this phy. But I don't want to use fixed-link ,So what should I config something else.

Hi, nie mingwang said: But it does not work,if I use fixed-link attribute,then can use this phy. Can you elaborate what you by does not work? Is the link not up or link is up but you are unable to ping? Can you confirm what is the rx and tx delay set-up in the phy? Depending on this you might have to change the phy-mode used. Regards, Tanmay

Hi, the link is not up, it can not get the phyid by mdio interface in davinci_mdio.c file. And how do I can confirm rx and tx delay set-up?

"phy_handle = <&phy3>;" actual is "phy-handle = <&phy3>;", I copy this error

But link is still not up

Hi, Sorry for the Delay. nie mingwang said: And how do I can confirm rx and tx delay set-up? This will be bootstrapped in the hardware design. Ideally the Schematic should have this detail. There should also be some phy register with this detail. You will have to check it in its datasheet. Can you please share the linux kernel log. Regards, Tanmay

Ticket Name: Compiler/TDA2-17: How to test FPD-Link output (P1) on JACINTO 6 ENTRY EVM?

Part Number: TDA2-17 Other Parts Discussed in Thread: DS90UH926QSEVB Tool/software: TI C/C++ Compiler Hi Team, I'm testing FPD-Link output (P1) on JACINTO 6 ENTRY EVM. My Deserializer board is DS90UH926QSEVB. Which Use cases of VISION SDK can test FPD-Link output(P1) on JACINTO 6 ENTRY EVM? SDK version: PROCESSOR_SDK_VISION 03_07_00_00 (Linux)

Hi, There is no such usecase in VSDK which uses FPD link port shown by you. Regards, Anuj

Hi Anuj, Is there any other way to test it? Thanks. Will Hsu

No. We are not support this. Regards, Anuj

Ticket Name: TDA2: TDA2x EVM Camera to work with TI SDK

Part Number: TDA2 Hi, I am looking to purchase the OMNIVISION 10635 that is stated to be supported by tda2x and if i understand correctly should work right out of the box. The issue is there are many models this camera and i'm not sure which one to purchase. Can you recommend a camera that will work directly with the board? Thanks, s

Hello You can order the complete set from spectrum digital along with EVM and vision daughter card regards, Shiju

Hi, Thanks for the quick reply- but that's just it- i dont want the set, i want just one camera to connect directly to the board and work. i dont require the card...

Hi You still need a "vision daughter card" to plug an OV10635 camera directly regards, Shiju

Hi, I got the EVM board that comes with the Vision Application Board. Do i still have to have the daughter card on addition? and where can i purchase just the camera and the card if needed?

Hi If you have EVM and Vision Application Board, its good enough. You only need to buy OV10635 camera, check details on spectrum digital website. TI not selling any of these boards or camera directly Regards, Shiju

Ticket Name: TDA2E: What is maximum Image sensor resolution and frame rate

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Hi Sir, What is the maximum image sensor resolution and frame rate that TDA2E can receive, This project may use MIPI 2-lane or DVP interface, image data format is RAW data, Sensor frame rate is 30fps. Is TDA2X able to receive RAW data of image resolution 8M or higher? Thanks. Ranny.

Hi Ranny, TDA2 plus may support up to 1.5Gbps per lane, but ISP can only support image width up to 2816 pixels. Please refer to TDA2 TRM for more details.

Hi Gang Hua, I got, thanks. Ranny.

Ticket Name: Linux/TDA2: QSPI 128MB 2 instances Read/Write error

Part Number: TDA2 Tool/software: Linux Dear Experts, We are using a 1Gbit(128MB) QSPI Flash(S70FL01GS) with kernel 4.4(VisionSDK 3.2). This chip is built from 2 64MB QSPI instances with 2 chip select.(correctly connected to TDA2's CS0 and CS1) When we operate on 2 instances, read/write result is incorrect. We add 2 64MB instance in linux device tree, and 2 instances are correctly recongnized by kernel from log. Here is some of our test notes: 1. kernel detect 2 chips. we only operate on any single chip, it works well. 2. kernel detect 2 chips, we read from 1, then write data to 2, then read again from 1, the result is incorrect. Read/write CS pin works well. Thanks & Best Regards! ZM

HI On our EVM we only have a single instance of SPI ,hence we have not validated this configuration(though it should work) Can you share the device tree snippet corresponding to the QSPI configuration From you description , you have verified that on your board the right chip select is being asserted when you access the 2 chips - please confirm Also, from your description, writes to chip2, is impacting the data present in chip1 - essentially implying that the 2 regions are being aliased, right?

&qspi {
         status = "okay";

         spi-max-frequency = <76800000>;
#if 1 
         m25p80@0 {
                   compatible = "s25fl512s";
                   spi-max-frequency = <76800000>;
                   reg = <0>;
                   spi-tx-bus-width = <1>;
                   spi-rx-bus-width = <4>;
                   #address-cells = <1>;
                   #size-cells = <1>;

                   /* MTD partition table.
                   * The ROM checks the first four physical blocks
                   * for a valid file to boot and the flash here is
                   * 64KiB block size.
                   */
                   partition@0 {
                            label = "QSPI.SPL";
                            reg = <0x00000000 0x000040000>;
                   };
                   partition@1 {
                            label = "QSPI.u-boot";
                            reg = <0x00040000 0x00100000>;
                   };
                   partition@2 {
                            label = "QSPI.u-boot-spl-os";
                            reg = <0x00140000 0x00080000>;
                   };
                   partition@3 {
                            label = "QSPI.u-boot-env";
                            reg = <0x001c0000 0x00040000>;
                   };
                   
                   partition@4 {
                            label = "QSPI.kernel";
                            reg = <0x00200000 0x0500000>;
                   };
                   partition@5 {
                            label = "QSPI.file-system";
                            reg = <0x00700000 0x03900000>;
                   };
         
         };
#endif       
#if 1
         m25p80@1 {
                   reg = <1>;

                   */
                            label = "QSPI.Extern";
                            reg = <0x00000000 0x04000000>;
                   };

         };       
#endif       
};
 Chip select pin is working correctly. Data read from chip is all zero if 2 chip is accessed.

Hi Srirama, After onsite check, I found that chip select is not correct. Finally, I find a bug in Kernel QSPI driver: diff --git a/ti_components/os_tools/linux/kernel/omap/drivers/spi/spi-ti-qspi.c b/ti_components/os_tools/linux/kernel/omap/drivers/spi/spi-ti-qspi.c
index 3f225f959..89ec31848 100644
--- a/ti_components/os_tools/linux/kernel/omap/drivers/spi/spi-ti-qspi.c
+++ b/ti_components/os_tools/linux/kernel/omap/drivers/spi/spi-ti-qspi.c
@@ -495,8 +495,8 @@ static void ti_qspi_enable_memory_map(struct spi_device *spi)
 	ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
 	if (qspi->ctrl_base) {
 		regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
-				   MEM_CS_EN(spi->chip_select),
-				   MEM_CS_MASK);
+				   MEM_CS_MASK,
+				   MEM_CS_EN(spi->chip_select));
 	}
 	qspi->mmap_enabled = true;
 }
@@ -508,7 +508,7 @@ static void ti_qspi_disable_memory_map(struct spi_device *spi)
 	ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
 	if (qspi->ctrl_base)
-				   0, MEM_CS_MASK);
+				   MEM_CS_MASK, 0);
 	qspi->mmap_enabled = false;
 }
 Thanks & Best Regards! ZM

Ticket Name: TDA2: About Deep Learning Issue

Part Number: TDA2 Hi Sir we have issues about TI deep learning in PROCESSOR-SDK-VISION V3.03.00 1, Does TI have SSD design guide (design flow, what kind of framework tool?) 2, Libray can be released? 3. How to implement new model (algorithm) into use case of TI TDA2 EVM? 4.Except SSD, will TI will support Yolo v2/v3? If yes, please provide the detail information (schedule, datasheet…) thanks for the reply. BR Yimin

Hi Yimin, 1. SSD supported TIDL is trained by caffe-jacinto framework. 2. Yes. TIDL library is part vision SDK release ( software-dl.ti.com/.../index_FDS.html) 3. Refer to section 3.6 in user guide (TIDeepLearningLibrary_UserGuide.pdf) 4. Please check the supported layers by TIDL in the data sheet (TIDeepLearningLibrary_DataSheet.pdf). Thanks, Praveen

Ticket Name: TDA2EVM5777: Exploring the Vlib and other libraries for the purpose of post processing of semantic segmentation

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Dear TI experts, Currently, I am trying to do find some useful functions for the post processing of my semantic segmentation done on the tda2. I have some questions and would love to have your expertise on it. 1. How to use the Vlib at the tild_postproc link, any example will be much appreciated. 2. Is there any similar function as convex hull algorithm in Vlib or any other library for DSP which I can utilize for the same purpose? 3. What is the purpose of function connected components and how to use it? any example would help a lot. Thank you. With best regards, Owais

I have forwarded this thread to the experts that may be able to help.

Hi Owais, We dont have optimized convex hull algorithm in vlib. Connected component labelling API, gives different label to different pixel level connected object information. This API comes with sample test application in vlib package, kindly go through the provided test case there to understand the functionality in details. Regards Deepak Poddar

Ticket Name: Compiler/TDA2SG: TDA2S eth0 link is not work well

Part Number: TDA2SG Tool/software: TI C/C++ Compiler HI , I　use the rgmii1 port connect to BCM89811,and my dts is like this, DTS: &mac { status = "okay"; dual_emac; }; &davinci_mdio { status = "okay"; }; &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; phy-mode = "rgmii"; dual_emac_res_vlan = <2>; }; &cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii"; dual_emac_res_vlan = <1>; }; I set the command "ifconfig eth0 192.168.208.110 up" then look the kernel message: [ 70.109299] net eth0: initializing cpsw version 1.15 (0) [ 70.109315] net eth0: initialized cpsw ale version 1.4 [ 70.109325] net eth0: ALE Table size 1024 [ 70.116837] net eth0: phy found : id is : 0xae025022 [ 70.123702] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready why my eth0 is link is not well wrok?

[ 0.568411] ioctl DBUFIOC_EXPORT_VIRTMEM = -1072899120 [ 0.570203] libphy: Fixed MDIO Bus: probed [ 0.616776] davinci_mdio 48485000.mdio: davinci mdio revision 1.6 [ 0.616787] davinci_mdio 48485000.mdio: detected phy mask fffffffe [ 0.618852] libphy: 48485000.mdio: probed [ 0.618865] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver unknown [ 0.619440] cpsw 48484000.ethernet: Detected MACID = 38:81:d7:73:ec:6a [ 0.619536] cpsw 48484000.ethernet: cpts: overflow check period 800 [ 0.620208] cpsw 48484000.ethernet: cpsw: Detected MACID = 38:81:d7:73:ec:6b [ 0.621538] i2c /dev entries driver [ 0.626342] omap_hsmmc 480b4000.mmc: no pinctrl state for sdr25 mode [ 0.632771] omap_hsmmc 480b4000.mmc: no pinctrl state for sdr12 mode [ 0.639367] evm_1v8: supplied by smps9 [ 0.677266] omap_hsmmc 4809c000.mmc: Got CD GPIO [ 0.718626] omap-rproc 55020000.ipu: assigned reserved memory node ipu2_cma@99000000 [ 0.718678] remoteproc0: 55020000.ipu is available this is my kernel message about mdio.

Hi ，now I can link up eth1 ，how can I set the link 100Mbps/Half (now is 10Mbps) my log is : [ 17.875266] net eth1: initializing cpsw version 1.15 (0) [ 17.875299] net eth0: initialized cpsw ale version 1.4 [ 17.875309] net eth0: ALE Table size 1024 [ 17.882989] net eth1: phy found : id is : 0xae025022 [ 17.889122] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready [ 23.879044] cpsw 48484000.ethernet eth1: Link is Up - 10Mbps/Half - flow control off [ 23.879129] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready

Have you tried ethtool to change the speed/duplexity ? Regards Vineet

Ticket Name: [TDA4M] Supporting RTOS at Cortex-A in TDA4

Other Parts Discussed in Thread: TDA2 Hi, Only Linux is supported at CA72 in the latest sdk v0.9 of TDA4. But in your previous TDA2, RTOS version was the main platform at CA15. When will RTOS be supported at CA72? Regards, HJ Kim

Hi Kim, SDK v0.9 supports RTOS on CA72 with a limited set of features. TI is still discussing internally on the roadmap for RTOS support. Regards, Rishabh

Hi Rishabh, Thank you for your reply. One more question, it is same for the following SDK v1.0 in Oct? Regards, HJ Kim

Hi Kim, Yes the above will remain same for SDK v1.0 release in October. Regards, Rishabh

Ticket Name: RTOS/TDA2: NDK 2_24_02_31 debug print

Part Number: TDA2 Tool/software: TI-RTOS Hello everyone! I am trying to do some modifications within the TCP source files. I am using VISION_SDK_02_12_01_00 for Windows. In order to do some debugging, I have used "DbgPrintf" and "printf" functions. However, when one of these functions gets invoked, I cannot see an appropriate output on the serial port. At first, I have used a MicroSD card to load the AppImage and I could not see any output of these functions. After that, I have loaded the AppImage using JTAG connection and CCS and I have not noticed the output neither on the UART console nor on the CCS console. Is there any solution to debug the NDK code using debug prints that would be visible on the UART console, or as the second solution, to be visible on the CCS console? I would like that solution not to imply using any application beyond the VSDK, i.e. I would just like to run the AppImage and to get the desired print outputs. Thanks in advance, Marko

Hello Marko, The NDK debug prints (using printf and dbgprintf) are not routed to serial port and are only console prints. These will only come on CCS console. We don't support serial prints in NDK as it is independent package. There are 2 options 1. After loading appimage and before running use-case, connect CCS and load symbols. After this you should get prints on console. 2. If you are sure that your debug code won't run before initialization of VSDK, you can directly Vps_printf function of VSDK (define prototype locally & declare it as extern).

Thanks, Prasad. Linking the Vps_printf function with NDK resolved my issue.

Ticket Name: TDA2SA: PROCESSOR_SDK_RADAR_03_07_00_00 matlab collected network port data, unable to display point cloud

Part Number: TDA2SA Other Parts Discussed in Thread: MMWCAS-DSP-EVM, MMWCAS-RF-EVM As shown above, using MMWCAS-DSP-EVM + MMWCAS-RF-EVM, run the use case cascade_radar_object_detect and set the radar output to 01 0 1 0. <rangeProfile>, <rangeDopHeatMap> can be displayed smoothly in the GUI. When the radar output is set to 1 1 0 1 1, the display of the GUI is stuck, and <pointCloud> and <azimuthHeatMap> are not displayed. With Wireshark, you can see the data coming. What is the reason for this? Is there a better tool to collect and observe the network port data output by the radar? Thanks a lot.

Could you enable "pointCloud" only and see if the output is displayed correctly. If not, one reason could be you don't have the calibration data in the SD card. Please refer to the user guide for generating calibration data and put it on SD card. The "AzimuthHeatMap" runs very slowly in Matlab so when it is enabled, the display can be very slow.

Thank you for your reply.But I can not find the user guide which remind the calibration method.Could you tell me the name of the document please.

I tried to do radar calibration via HyperTerminal command"c: Control Calibration"with the parameter ：“10 1 250”.And then enable "pointCloud"only.Matlab can display point clouds, but it can only last for more than ten seconds, and then it stops there. Thank you.

Please read the VisionSDK_Getting_Started_Guide.pdf. It tells you where to find the documents including User Guide. In the User guide, you can find the instruction regarding calibration.

Ticket Name: TDA2SX: Number of GFLOPS , DLOPS? How to calculate the computing power of TDA2x

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2, 66AK2H12, Hi TI Experts, 1. We have some ADAS customers asking about the computing power of TDA2 series SoCs. I cannot find an official document listing the computing power of TDA2x in GFLOPS/ TFLOPS from TI, Where can we find or how to calculate that number? The ADAS application requires the use of deep learning algorithms, in comparison, we get to know that Mobile Eye says that the EyeQ3 delivers ~300 GFLOPS, while EyeQ4 push that number to 2.5 TFLOPS. On TI DSP overview page http://www.ti.com/processors/dsp/overview.html, I find this information, saying that the TI C66x DSP core delivers 32 GMACs and 16 GFLOPS per core at 1 GHz. And, I find the efficiency of ARM Cortex-A15 is around 6.9FLOPS/GHz/Core (https://devtalk.nvidia.com/default/topic/813318/jetson-tk1/flops-for-jetson-host/ ), So, I did the math for 66AK2H12(4* ARM Cortex-A15@1.4GHz，8* C66x @1.2GHz), the total computing power should be around 4*1.4 GHz * 6.9 GFLOPS/GHz + 8*1.2 GHz * 16 GFLOPS/GHz = 38GFLOPS + 153.6GFLOPS = 191.6 GFLOPS, which is quite close to the 200GFLOPS on the TI DSP overview page. In the very same way, we can calculate the GFLOPS of TDA2SX(2* ARM Cortex-A15@1.176GHz，2* C66x @0.75GHz ) it's 2*1.176 GHz*6.9 GFLOPS/GHz + 2*0.75 GHz*16 GFLOPS/GHz = 16+24 =40 GFLOPS In the meanwhile, I found a video from youtube (www.youtube.com/watch saying that the computing power of TDA2 is 266 Giga DLOPs 2. Can you explain what DLOPs(I'm guessing "Deep Learning Operations" ) means? what its relationship with FLOPS? 3. Since the EyeQx uses MIPS CPUs, which has a comparable efficiency to ARM Cortex-A CPU, I doubt that a 3 Watt Soc will deliver 300 GFLOPS or even 2.5 TFLOPS, while TI TDA2x only delivers 40 GFLOPS... So, Is that in deep learning field, people define FLOPS differently? I found people discussing that in deep learning algorithms, only half-precision floating point operation is needed, but regularly, when people talk about FLOPS, they mean single-precision floating point(see https://teslamotorsclub.com/tmc/threads/ap2-0-cameras-capabilities-and-limitations.86430/page-20 #396).

Hi Nestor, I have forwarded your question to Deep Learning experts. Regards, Yordan

Hi Yordan, Is there any feedback? Thanks.

Hi Yordan, Can you help to ask the Deep Learning experts for progress? Thanks.

Hi Nestor, sorry for the delay, I will ping them. Regards, Yordan

Hi Nestor, Let me first define the terminology (at least used by me in my response) FLOPS: Single precision Floating point operations MAC: Multiply + Accumulate operation. 1 MAC is equivalent to 2 operations DLOPS: In Deep learning, as you said half float or even 8-bit fixed point data type is sufficient. So in the above slide DLOPS refers to 8-bit arithmetic or conditional operation (Multiply/Add/Compare). So you can assume 1 MAC = 2 DLOPS Many researchers have suggested that 8-bit or 16-bit fixed point data type is suffice for deep learning and TI also believe that so I will focus on GMAC (or DLOPS now) in regard to the above slide TDA2x (Theoretical performance) for 8-bit or 16-bit fixed point data type 2x C6x DSP @ 1000 GHz = 2*32 GMACS = 64 GMACS 4xEVE @900 MHz = 4*16*900 MMACS = 57.6 GMACS 2xA15 @1800 MHz = 2* 8 * 1800 MMACS = 28.8 GMACS Total = 150.4 GMACs = 300 GDLOPS Now the actual throughput depends a lot on network structure, so I will not be able to comment on a single number. The slide referred by you mentions the performance of a semantic segmentation application using deep learning network. IN this we use only 4xEVE cores and that’s why the power consumption is 2.5 W!!! Now the question remains open is that the theoretical best of 4xEVE is 57.6 GMAC (115.2 GDLOPS) then how could 266 GDLOPS are achieved. And here also the point is the network property. If you look at the network and count the DLOPS, it is 266 GDLOPS but the TI Deep learning library identifies some redundant operations and avoids performing them and that’s why it can run a complex network having 266 GDLOPS on 4xEVE. Hope this clarifies… Thanks, With Regards, Pramod

Ticket Name: TDA2SX: TIDL running multiple frames

Part Number: TDA2SX Hi everyone, I am running TIDL usecase on DSP and want to use SSD model for object detection to make inference on multiple images at sequence. NullSrc is taking images one by one and sending them for preprocessing and inference. Inference on first image is correct, but for all images after the first one inference output have 26 bboxes detected and every bbox have confidence value 0.5 and values for coordinates are not as expected for any bbox. Some of them are invalid (below 0.0 and above 1.0). However, if TIDL link is restarted (System_linkStop, System_linkDelete, System_linkCreate, System_linkStart sequence of functions is called) after inference for one image and before another, results for next frame are correct. I tried same usecase with Image segmentation model and using multiple input images and there wasn't this problem. What could be the problem, why TIDL is not working correctly with my model? Regards, Sasa

Hi Sasa, Did you get import tool output correct for your model ? Thanks, Praveen

Hi Praveen, Yes, import tool output is correct. Regards, Sasa

Do you have any more suggestions? Can I at least try to have some "soft" restart for beginning? By "soft" restart I mean can I call some function at the end of AlgorithmLink_tidlProcess function to return link to initial state without taking too much time as now is the case with link restart. Thanks, Sasa

Hi Sasa, You can try that but to root cause the issue, is it possible to run TIDL inference in standalone setup using multiple images. Thanks, Praveen

Hi Praveen, you mean running it using debugger to download code to DSP? If that is the case, I can't because I don't have any debugger now. But I tried to have more frames as an input and after several frames the inference of multiple bboxes detected per frame, algorithm stabilizes itself and works OK for all of the frames. I wonder now why it has those few frames with bad inference?. Regards, Sasa

Hi Sasa, Thanks for the update. You can try changing the below quantization parameters as suggested in the section 3.8 (Matching TIDL inference result) in the TIDL user guide, and check if you can see any improvement in the output. >>Set with below parameters for running on video sequence. createParams.quantHistoryParam1 = 20; createParams.quantHistoryParam2 = 10; createParams.quantMargin = 20; Thanks, Praveen

Ticket Name: TDA2: image rotated function , how to optimize and improve efficiency?

Part Number: TDA2 Hi, I am having a problem, the 640x720 image is rotated 90 degrees, running on dsp1, the efficiency is very low, fps = 3. how to optimize and improve efficiency? Thanks!

Hi @yuling ma , do you use an algorithm, you wrote yourself? You can check if the following documents can help you: Introduction to TMS320C6000 DSP Optimization: Optimizing Loops on the C66x DSP: Hand-Tuning Loops and Control Code on the TMS320C6000: Regards, Yordan

Part Number: TDA2 Tool/software: Linux Hi , I gone through SPI driver as mention below: McSPI driver is here: PROCESSOR_SDK_VISION_03_05_00_00\ti_components\drivers\pdk_01_10_01_06\packages\ti\drv\bsp_lld\mcspi --This driver based on ti rtos driver (PDK Package) but i need spi slave driver based on linux (HLOS) side (VSDK part). could you please help me to get any SPI Slave driver code/examples/document related to this? Thanks, Anand Kumar

Hi Anand, Vision SDK package does not have spi driver for linux. If you want to use it with Vision SDK linux, you should follow approach similar to VIP and other Video peripherals (they run on M4). You should refer to linux kernel for actual SPI linux drivers. Regards, Rishabh

Ticket Name: CCS/TDA2: Where can i learn SoC programming

Part Number: TDA2 Tool/software: Code Composer Studio Hi TI, I am a newbie for SoC platform. I used to do programming on micro-controller (other brand) which i believe its a totally new platform. i need some help to get things started hope TI is able to advise me how to do some. Plus i am totally new on this CCS IDE as well Regard Willson

Hi Wilson, you can start your familiarization with CCS from here: dev.ti.com/.../ (you can find Documentation and Trainings for CCS there). You can check also "A Guide to Debugging With CCS on the DRA7x, TDA2x and TDA3x Family of Devices" here: www.ti.com/.../sprac17b.pdf You can download VisionSDK here: software-dl.ti.com/.../index_FDS.html when you install it in the "doc" directory you can find quite comprehensive documentation for the SDK, and you can also look at it's source code. Regards, Yordan

Ticket Name: Linux/TDA2: How to integrate a simple application with SDK.

Part Number: TDA2 Tool/software: Linux Hi, i want to integrate my openGL based application with SDK . please tell me how i can do that. thank you

Vijender, SDK exposes standard openGL ES 2.0 EGL libraries. As long as your application uses the standard APIs, it can be integrated to the SDK - Subhajit

Ticket Name: Toolchain for compiling Qt application for TDA2 board?

Other Parts Discussed in Thread: TDA2 Hello All, I am looking for information on how to compile a Qt application for deployment on TI's TDA2 (ARM A15 based) board. In particular which toolchain should be used? I've found Qt documentation for other boards, but nothing specific to the TDA2. Any pointers on how to get started with this board would be greatly appreciated. Regards, Eric Gilbertson ejg@peloton-tech.com

Hello, I am not aware with TDA2 but have you tried with CodeSourcery? processors.wiki.ti.com/.../Building_Qt BR Margarita

Here is the qmake.conf I used for the TDA2. Note, I'm still having a problem with GLES2 but I believe that is unrelated to the conf settings. HTH, Eric G. qmake.conf for TDA2: include(../common/linux_device_pre.conf) DISTRO_OPTS += hard-float QMAKE_INCDIR += $$[QT_SYSROOT]/usr/include QMAKE_LIBDIR += $$[QT_SYSROOT]/usr/lib \ $$[QT_SYSROOT]/lib/arm-linux-gnueabihf \ $$[QT_SYSROOT]/usr/lib/arm-linux-gnueabihf QMAKE_LFLAGS += -Wl,-rpath-link,$$[QT_SYSROOT]/usr/lib \ -Wl,-rpath-link,$$[QT_SYSROOT]/usr/lib/arm-linux-gnueabihf \ -Wl,-rpath-link,$$[QT_SYSROOT]/lib/arm-linux-gnueabihf TDA2_CFLAGS = -mtune=cortex-a15 -mfloat-abi=hard -mfpu=vfpv3-d16 QMAKE_CFLAGS += $$TDA2_CFLAGS QMAKE_CXXFLAGS += $$TDA2_CFLAGS include(../common/linux_arm_device_post.conf) load(qt_config) ~

Ticket Name: Linux/TDA2: how to enable uart2 on linux os of ti sdk

Part Number: TDA2 Tool/software: Linux Hi, I'm newbie to use TI's tda2xx evm board with Vision SDK. I am using linux os with tda2xx_evm_linux_all config. After I added PlatformUART2SetPinMux() in Bsp_boardTda2xxInit(), I am able to send strings with uart2 by typing "echo 123 > /dev/ttyS1" in uart1 terminal. The correct waveform on uart2 tx can be seen on the oscilloscope. Then I connected uart2 rx to uart2 tx, sent a string by "echo 123 > /dev/ttyS1" , then "cat /dev/ttyS1": I got nothing. Seems nothing is recieved from uart2. Did I miss anything to use uart2 on linux? Is there documents about my issue? thanks very much. Dong

Hi It is unclear where you want to control the UART instance from and the overall intent of what you are trying to implement Can you be more specific in terms of the resource usage from Linux vs BIOS

Hi, I want to verify UART2 function first in whichever method, so I take /dev/ttyS1 using Linux os. The final goal is to use LIN bus through UART2. The resource usage from Linux vs BIOS is not considered yet. Currently my problem is that UART2 data can't be received by "cat /dev/ttyS1". If TI has no support about UART2 on Linux os (tda2xx_evm_linux_all config), any other guide to quickly verify UART2 using Vision SDK(PROCESSOR_SDK_VISION_03_01_00_00) is appreciated.

It seems that the pin mux register setting of uart2 is not correct: the macro CTRL_CORE_PAD_UART2_RXD_UART2_RXD_MUXMODE_UART2_RXD_0 in PlatformUART2SetPinMux() function does not match what's described in tda2x manual about UART2_RXD_MUXMODE. (P5149, TDA2x SoC for Advanced Driver Assistance Systems (ADAS), Silicon Revision 2.0, 1.x Texas Instruments ADAS Family of Products, Technical Reference Manual) After I change CTRL_CORE_PAD_UART2_RXD_UART2_RXD_MUXMODE_UART2_RXD_0 to CTRL_CORE_PAD_UART2_RXD_UART2_RXD_MUXMODE_UART2_RXD_4, uart2 rx function is correct. Please fix this bug in TI VISION SDK in case other developers using uart2 are having the same problem. Thanks!

Ticket Name: DRA756: How deal with DRA74x/TDA2x PCIe soft reset signal?

Part Number: DRA756 Other Parts Discussed in Thread: PCF8575 According to the guide in the following link, http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_Kernel_Drivers.html?highlight=pcie#pcie-end-point There is no setting of the reset pin of PCIe (for EP nor RC). diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index eedd930..93d9f17 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -1084,7 +1084,7 @@
        vdd-supply = <&smps7_reg>;
 };

-&pcie1_rc {
+&pcie1_ep {
        status = "okay";
 }; How to deal with the PCIe software reset signal on EVM? just ignore it? How about the hardware connection to RC device?

Hi, I can only tell about hardware details of PCIe SW reset. This signal assertion, similarly to few other features on EVM, is accomplished via an external GPIO IC. IC type: PCF8575 IC ref: U58 Connected to: I2C1 of DRA75x I2C address: 40h PCI_SW_RESETn is on pin: 14 (D hex) Hope some of these helps.

Note that this reset will not propagate if PCI_RESET_SEL is high, which is selected by SW5-8 set to OFF.

Thank you for your reply. I know where the PCIe-sw-reset connects on hardware, What I want to know is, how to link it with PCIe controller, especially in Linux. in reference design shown in http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_Kernel_Drivers.html?highlight=pcie#pcie-end-point &pcie1_ep {
	status = "ok";
}; No binding of the gpio to PCIe controller.

I don't know the history for that. I hope this will get answered soon in this thread. Perhaps this wasn't implemented in Linux because Reset is not a mandatory signal for PCIe devices. Regards, Stan

Ticket Name: RTOS/TDA2-17: VSDK_03_06_00_00:enbale custom LCD

Part Number: TDA2-17 Tool/software: TI-RTOS I want to use a new LCD with FDPLINK to get vedio signals.The resolution of the custom LCD is 1280*720. In this SDK, I found that there are two resolution for LCD output directly. 800*400 and 1280*800. And there is a resolution for FPD output.1280*720. This resolution is what I need.But another TI employee told me that this SDK does not support FPD output format. Now, I have already set the FPDLINK and parameters related to displayctrl. I tried two output configurations 1.use the FPD directly in the SDK. 2.use LCD ouput and change the resolution to 1280*720. Both methods don’t seem to work.Am I missing some settings?

Hi, Have you tried change the Video Port's configuration to 720p? Regards, Rishabh

I want to achieve single channel output.I have changed the video outport in the ChainsCommon_StartDisplayCtrl funtion of chains_common.c

Hi, Can you share the changes you have made. Also are you able to turn the backlight to ON state for FPD display? If you are not able to see the back light then there is some issue with the FPD driver and we don't have support for the same in SDK. You need to use linux for FPD driver. Regards, Rishabh

Ticket Name: Provide MLBP documentation on TDA2

Other Parts Discussed in Thread: TDA2 hi Can you provide MLBP documentation on TDA2?Thank you.

Hi, Chen Melina, MLB is documented for DRA devices in the TRM book, chapter 24.12: Regards, Mariya

Hi Mariya Thank you very much for your kindly support.

Ticket Name: Linux/TDA2SX: TDA2

Part Number: TDA2SX Other Parts Discussed in Thread: OPT8241, TDA2 Tool/software: Linux Dear TI officer: I have a TDA2x development board and an OPT8241-CDK-EVM. Can I put the OPT8241-CDK-EVM 's SDK: Voxel SDK on the TDA2 development board compiler and execute the OPT8241 application? Thanks.

Dear TI Officer: Can someone answer my question? Can I add the Voxel SDK and the Point Cloud Library to the Vision SDK and compile them together? Thanks.

Hi Finley, I am not too familiar with the Voxel SDK. I believe if this is C code and library which can be compiled for the cores on TDA2 SoC and have no dependency on any specific OS functions which is not provided as part of TI RTOS, it should be okay. Thanks and Regards, Piyali

Dear Piyali: Thank you for your response Voxel SDK dependency on PCL-1.7.2, libusb-1.0-0-dev, libudev-dev, linux-libc-dev, G++ 4.8 or later on Ubuntu 14.04 Can it compile and run on TDA2 Linux ? Thanks

Dear TI Officer: Can someone answer my question? Thanks.

Hi Finley, I had tried running the PCL a long time back on the Linux on TDA2 and it was working fine. I believe you need to make sure your filesystem has the right libraries to support this. I will also let one of our Linux experts to have a look at your requirements to confirm this is indeed supported. Thanks and Regards, Piyali

Hi Finley, The latest Linux SDK release, that can be used with TDA2, is 5.00. This has support for point-cloud-dev and all other libraries that you mentioned. Please try it out and see if you can get the Voxel SDK working. If not, we will have to look at the issues and see how we can enable you from there. Regards Karthik

Dear Piyali and Karthik, Thank you for your response, i will try OPT8241 on TDA2x. thanks

Ticket Name: Linux/TDA2: TDA2xx compile opencl usecase error

Part Number: TDA2 Tool/software: Linux i wrote a usecase to use Alg_OpenClFrameCopy，the config file is： UseCase: chains_openclFrameCopy NullSource (A15) -> Decode -> Alg_OpenClFrameCopy (A15) -> VPE -> Display And the Automatically generated .h and .c files is : typedef struct { UInt32 NullSourceLinkID; UInt32 IPCOut_A15_0_IPU1_0_0LinkID; UInt32 IPCIn_IPU1_0_A15_0_0LinkID; UInt32 DecodeLinkID; UInt32 IPCOut_IPU1_0_A15_0_0LinkID; UInt32 IPCIn_A15_0_IPU1_0_0LinkID; UInt32 Alg_OpenClFrameCopyLinkID; UInt32 IPCOut_A15_0_IPU1_0_1LinkID; UInt32 IPCIn_IPU1_0_A15_0_1LinkID; UInt32 VPELinkID; UInt32 DisplayLinkID; NullSrcLink_CreateParams NullSourcePrm; IpcLink_CreateParams IPCOut_A15_0_IPU1_0_0Prm; IpcLink_CreateParams IPCIn_IPU1_0_A15_0_0Prm; DecLink_CreateParams DecodePrm; IpcLink_CreateParams IPCOut_IPU1_0_A15_0_0Prm; IpcLink_CreateParams IPCIn_A15_0_IPU1_0_0Prm; AlgorithmLink_OpenClFrameCopyCreateParams Alg_OpenClFrameCopyPrm; IpcLink_CreateParams IPCOut_A15_0_IPU1_0_1Prm; IpcLink_CreateParams IPCIn_IPU1_0_A15_0_1Prm; VpeLink_CreateParams VPEPrm; DisplayLink_CreateParams DisplayPrm; } chains_openclFrameCopyObj; When I write a complete case to compile, I get the following error： chains_openclFrameCopy_priv.h:103:8: error: unknown type name 'AlgorithmLink_OpenClFrameCopyCreateParams' AlgorithmLink_OpenClFrameCopyCreateParams Alg_OpenClFrameCopyPrm; ^ In file included from chains_openclFrameCopy_priv.c:70:0: chains_openclFrameCopy_priv.h:103:8: error: unknown type name 'AlgorithmLink_OpenClFrameCopyCreateParams' AlgorithmLink_OpenClFrameCopyCreateParams Alg_OpenClFrameCopyPrm; I have added a header file in chains_openclFrameCopy_priv.h，but it still error. #include <include/alglink_api/algorithmLink_openClframeCopy.h> How can i resolve this problem？

Hi Can you give some more information like which MAKECONFIG are you using ? & Is OPENCL_INCLUDE flag is enabled in that config ? Regards Surya

Hi my vision_sdk/build/Rules.make config mode is :MAKECONFIG?= tda2xx_evm_linux_all ; and i check that vision_sdk\apps\configs\tda2xx_evm_linux_all\cfg.mk has not define OPENCL_INCLUDE=yes. Thank you for giving me great help. Regards Xie Baojian

Hi Xie Baojian, When using OPENCL better to use MAKECONFIG= tda2xx_evm_linux_opencx Regards Surya

Hi, OK, i will try it, thanks. Regards Xie Baojian

Ticket Name: TDA2SX: Codec is master, mcasp is slave, I2S record

Part Number: TDA2SX Hi . TDA2S，sdk:PROCESSOR_SDK_VISION_03_05_00_00 linux 4.4.48 Codec is master, mcasp is slave, I2S record |------McaSP2_ACLKR ----->-| master codec |------MCASP2_FSR--------->-| tda2sx |------MCASP2_AXR0------>- | McaSP2_ Aclkr input 3.072Mhz MCASP2_FSR input 47Khz root@dra7xx-evm:~# arecord -r 48 > path_to_example_audio.wav Recording WAVE 'stdin' : Unsigned 8 bit, Rate 48000 Hz, Mono SND_SOC_DAIFMT_AC97 codec is clock and frame master path_ to_ example_ audio.wav There is only one header, 44byte， No recorded data I want to know how to check the problem, please give me some advice. thank you

Hello, sorry for the delayed response. were you able to make any progress during this time? typically we start by checking the most likely: 1. the clock master from the codec is live 2. check McASP registers to ensure it is configuration with right mode... please update the thread if the debug is ongoing. Jian

Ticket Name: Linux/TDA2: Deep learning issue

Part Number: TDA2 Tool/software: Linux Hi, My target is implement entire yolo network (at least tiny yolo) on TDA2. here is my question Q1. my current SDK vision is 3.0.0, should i use v3.03? Q2 could i implement it without TIDL, just like we create a new usecase? Q3. In TIDeepLearningLibrary_UserGuide.pdf, all step is based on windows and CCS. If we want to install it and build it on Linux and without CCS, What should we do? Thanks for your reply, Chen-Wei Lai

Hi, 1. It is always recommended to use the latest version as it could fix some issues found older versions. 2. Please post this question in a new thread as I am not expert to answer this question 3. TIDL does not build and run in Linux. Thanks, Praveen

Ticket Name: Linux/TDA2: how to save vedio by VLC

Part Number: TDA2 Tool/software: Linux i am use tda2 evm SDK_VISION_03_04_00_00 , now usecase in SDK_VISION_03_04_00_00 run is ok. then i am try to save some vedio by VLC, but i donot not how to do this. thanks Shuai

Hi, We do not support saving video using VLC. You can use null Link to save the video locally on the sd card or use network link to save it on your pc. Regards, Anuj

Hi Anuj both , can you tell me how to do this ! Regards, Shuai

Hi, Please refer below usecases vision_sdk\apps\src\rtos\usecases\null_src_dec_display vision_sdk\apps\src\rtos\usecases\network_rx_tx (check network Tx usecase) Saving the video on sd card will be easier if you do not have any specific requirement for network tx. Regards, Anuj

Hi Anuj in this case （vision_sdk\apps\src\rtos\usecases\null_src_dec_display） i think data souce is not camera. in which link have save the video locally on the sd card ? thanks! Shuai

Hi, Null Link save the video to sd card. You can modify any usecase with single camera and replace display link with null link. It will save the camera video. Regards, Anuj

Ticket Name: PROCESSOR-SDK-TDAX: Literature on the difference between opp_nom, Opp_high and opp_low when making PROCESSOR_SDK_RADAR for MMWCAS_DSP_EVM

Part Number: PROCESSOR-SDK-TDAX Hi, Can anyone point me towards the literature documenting the difference between those three folders mentioned in the title? Thank you

Please refer to ch 5.5 for detail. https://www.ti.com/lit/pdf/sprs951

Thank you.

Ticket Name: TDA2EXEVM: How to add GrpxSrcLink_drawCpuLoad() in the usecase

Part Number: TDA2EXEVM Hi sir, As your suggestion in previous thread ( e2e.ti.com/.../849828 ) to show CPU loadings by using GrpxSrcLink_drawCpuLoad(). However, there are no usecase using this function. So I have no idea how to use it. Can you provide me in more detail? I tried to add GrpxSrcLink_drawCpuLoad() into OD usecase. However, an error was occurred when compiling. It said chains_tidlODAppObj is incompatible with GrpxSrcLink_Obj. And I observed that the usecase "1CH VIP capture + Display" can show cpu load without using GrpxSrcLink_drawCpuLoad(). Can you advise me where should I add the function? Thank you, Gary

Hi, You need to update PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\apps\src\rtos\modules\grpxSrc\grpxSrcLink_tidl_od_layout.c. You can grep GrpxSrcLink_drawCpuLoad in the folder PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\apps\src\rtos\modules\grpxSrc to see how to call this API. Regards, Rishabh

Ticket Name: DRA77P: Early capture late weston usecase build error

Part Number: DRA77P Hi, I am working on DRA77P, with vision SDK v3.07, and for early initialisation of HDMI, I have been trying to build the particular usecase early capture late weston . I have done the following steps based on VisionSDK_Linux_UserGuide.pdf: EARLY_USECASE_ENABLE=yes in the apps/configs/<evm_id>_linux_all/cfg.mk make linux make linux_install make -s -j depend make -s -j On make -s -j command, I encounter the following error, gmake[1]: Leaving directory `/home/ubantu/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2px_evm_linux_all/obj/vision_sdk/tda2px-evm/ipu2/release/vision_sdk_configuro/package/cfg/MAIN_APP_ipu2_pem4.src/sysbios'
Build of libraries done.
# Configuro done!
# Making tda2px-evm:ipu2:release:vision_sdk_lib...
# Compiling tda2px-evm:ipu2:release:vision_sdk: src/main_common_ipu2.c
# Compiling tda2px-evm:ipu2:release:vision_sdk: src/eve_firmware.c
# Compiling tda2px-evm:ipu2:release:vision_sdk: src/ipu_primary.c
# Compiling tda2px-evm:ipu2:release:vision_sdk: /home/ubantu/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/apps/src/common/app_init/app_init_ipu_primary.c
# Compiling tda2px-evm:ipu2:release:vision_sdk: /home/ubantu/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/apps/src/common/main_app/tda2px/ipu2/src/main_ipu2.c
#

 undefined                     first referenced                                                                                                                                                
  symbol                           in file                                                                                                                                                     
 ---------                     ----------------                                                                                                                                                
 chains_earlyCaptureLateWeston /home/ubantu/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2px_evm_linux_all/lib/tda2px-evm/ipu2/release/app_libs.aem4<chains_early_usecase.oem4>

error: unresolved symbols remain
   built
 What am I missing here ? Regards, Padmesh

Hi Padmesh, When you have changed any flags in config file , recommendation is to clean everything and then build Please try with this make clean make -s -j depend make -s -j Thanks RamPrasad

Hi Ram, I tried the above steps. Still I get the same errors. Regards, Padmesh

Hi Padmesh, I see this usecase by default is not enabled for tda2px platform. You need to add ifeq ($(EARLY_USECASE_ENABLE),yes) UC_early_capture_late_weston=yes endif in apps/configs/tda2px_evm_linux_all/uc_cfg.mk Please refer apps/configs/tda2xx_evm_linux_all/uc_cfg.mk where all usecases are supported. Thanks Ram

Thanks Ram, I was able to resolve the issue. Doing this which firmware do i need to place in the QSPI and in what named should it be placed ? Regards, Padmesh

Refer section 3.4.1 of the visionDK_Linux_userguide.pdf You need all the three firmwares . Please refer build/hlos/scripts/linux/flash-qspi.sh Thanks Ram

Ticket Name: RTOS/TDA2: [TIDL_OD + LD]

Part Number: TDA2 Tool/software: TI-RTOS Hi, we use TDA2xx SDK03.04 and want to combine TIDL_OD and Lane detection but we have abnormal output. please teach us how to create this case our flow and logs are as following: case modification flow: we use 1280x720 camera as capture use dup for lane detection and tidl_OD use VPE transfer 1280x720 to 768x320 for tidl_OD Question 1: but we got wrong function result log is as following session_0915_1280.log can you tell us where is wrong? or tell us the right way . Question 2: Will lane detection or TIDL_OD output resolution equal to input resolution? ex. TIDL_OD use 768x320 as input , is it same as 768x320 after tidl_dsp ? Question 3: Has the merge links must need all inputs with same resolution? like this case , the merge has Q0、Q1、Q2 three inputs, they must need the input with same resolution?

Hi, TIDL_OD is not been tested with live capture. Please check the tidl_od usecase. Regards, Anuj

Hi, so we need use Nullsource link to replace Capture link? That's fine, we can change it. But the Q2 &Q3 , can you answer us? Allen

Hi, Q2: yes Q3: no Regards, Anuj

Hi, ok, and we have two question about Q1 (1) Will TI combine these two usecase (Lane detection and TIDL_OD ) ? When? (2) We try to create our custom usecase. The flow is the picture but we got the wrong result: a. object draw doesn't appear b. lane detection draw is in the left-down (wrong position) in frame Can you tell us where is wrong?

Has any response ?

Hi, (1) Will TI combine these two usecase (Lane detection and TIDL_OD ) ? When? No, TI doesnot have any plan to combine these 2 usecase. Please use the below usecase for the object detection and lane detection Z:\ADAS\vision_sdk\apps\src\rtos\usecases\vip_single_cam_analytics2 Regards, Anuj

Ticket Name: TDA2: how to set tda2x's DSP clock in uboot ?

Part Number: TDA2 Hi We are using tda2x self-designed board, the default value of dsp clock of tda2x is 750MHZ,Now we want to set the tda2x's DSP clock to 500MHZ in uboot, how to do that ? Thanks

Hi, can you try to modify the "dra7_opp_dsp_clk_rates" structure in <u-boot>/arch/arm/cpu/armv7/omap5/fdt.c with your new values. Regards, Yordan

As a side note, I suggest using the Clock Tree Tool (CTT) to understand the TDA2x clocks better. The CTT can be downloaded free of charge here: www.ti.com/.../clocktreetool thanks, Alex

Ticket Name: Linux/TDA2EX17EVM: Tiler Memory in OMAPDRM

Part Number: TDA2EX17EVM Tool/software: Linux Hello Sirs: We are using PSDK VISION 03_04_00_00, I saw that the tiler memory is implemented in omapdrm. I know that The VSDK uses vdrm rather than omapdrm, in your opnion, Is it possible to use it in VSDK? Regards, /ckhsu

It is possible to support tiler memory in VDRM, but TI does not have any plans to enable it now or in the future - Subhajit

Dear Subhajit: How we can modify the VDRM to let it support tiler memory? Regards, /ckhsu

please look at how omapdrm uses it. you can replicate the operations to get it working with vdrm. Once again, TI does not have any plans to support TILER memory from VDRM. I can say that it is doable, but I have not explored how much effort is required to accomplish this. I am closing this ticket now

Ticket Name: Linux/TDA2EVM5777: Connect KSZ989x to cpsw_emac1 ....?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hello *! Connect a single PHY to one EMAC is no problem: &cpsw_emac0 {
  status = "okay";
  phy_id = <&davinci_mdio>, <9>;
  phy-mode = "rgmii-id";
  dual_emac_res_vlan = <1>;
}; This is working fine. But now we have to use a switch behind the cspw... therefor the "port 0" (from Linux view) of the KSZ9893 have been set to "PHY Mode" and I can see the 3 ports over MDIO: [ 1.951119] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver unknown [ 1.959219] davinci_mdio 48485000.mdio: phy[1]: device 48485000.mdio:01, driver unknown [ 1.967329] davinci_mdio 48485000.mdio: phy[2]: device 48485000.mdio:02, driver unknown (Driver unknown: If a use a simple homebrew driver on base of KSZ9031, it will be probed... BUT: Port0 will get something like a PHY ID: 004040FE...? The other will be shown as 221637 as expected...? Okay, only sidekick information. I go on:) There is a driver for KSZ9893 (in our case) I took from mainline Linux and backported it to our 4.4.84 Kernel. Microchip placed it to "DSA"-part of network driver. I never used a switched like this with DSA... I tried some silly first hook: &cpsw_emac1 {
         switch@0  {
                compatible = "microchip,ksz9897";
                port@2 {
                        reg = <2>;
                        label = "lan6";
                };

                port@1 {
                        reg = <1>;
                        label = "lan3";
                };

                port@0 {
                        reg = <0>;
                        label = "cpu";
                        fixed-link {
                           speed = <1000>;
                           full-duplex;
                        };
                };
        };
 Of course... it do not work. Is somebody able to tell me, how it works using a switch behind the cpsw_emac... Maybe somebody used KSZ9897 (or similar?) behind TDA2+ and would tell little secrets? I'm running out of ideas right now... an out of time, too. So: Thank you! Every help is welcome....

Hi With the native CPSW driver the connection to the external switch will need to appear as a FIxed-PHY connection (no cable connect , disconnect), operating at a fixed speed and duplexity. The device tree parameters need to be modified as such. Any additional Switch configuration is outside the scope of the CPSW driver - it would treat it as external PHY only To the ethernet device node in the device tree file, you need to add a sub device node describing the fixed link to the PHY For more details refer description in Documentation/devicetree/bindings/net/cpsw.txt, Documentation/devicetree/bindings/net/fixed-link.txt

Ticket Name: TDA2PXEVM: Connect TDAPx-EVM to the internet

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello all, I have TDAPx-EVM board and I was able to build Yocto file system and boot the board using the built yocto file system. I want to connect it to the internet, after connecting it to an Ethernet cable there is still no internet connection, so I want to know is anything I have to configure or what should I do to have and internet connection on my TDAPx-EVM Thank You, Best regards, Kirollos Henry

Hi, Could you share the log from boot to linux kernel and the log from "ifconfig"? Did you change Linux kernel default config used by TDA2 SDK? Ethernet should be enabled already from the default config. Regards, Stanley

Ticket Name: TDA2EG-17: Does SOC support qspi interface that can output and input in both falling and rising edge?

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2 Hi, Customer they met one urgent issue, they choose a GD flash that only support the mode, from which that input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. I searched the TRM but there are only 4 modes QSPI supported(mode 1 and mode2 is not supported), all of them only support input and output either on falling edge or rising edge. Is there any methods that can enable our SOC to support output and input on different edge? This issue is urgent, please help to debug. Thanks Regards Zekun

Hi Zekun, We will have to check with the HW team, i will start email on this and will keep you posted. Regards, Brijesh

Zekun, It appears that Mode 0 matches what you're looking for? Thanks, Kyle

Zekun, Please ignore my last reply. I see you're asking about TDA2 (not J7). Regards, Kyle

Zekun, Can you share the datasheet of the selected QSPI device? Thanks, Kyle

Hi, Kyle I think we don't support the feature I asked. But now customer's issue has been closed. So close the ticket. Regards Zekun

Ticket Name: TDA2HV: Operative System Resources

Part Number: TDA2HV Other Parts Discussed in Thread: TDA2, Hello, Can you provide more information about the Operative System Resource Requirements (CPU, RAM, FLASH) for TDA2? TDA2HV: VSDK RTOS: VSDK Linux: QNX: Autosar: Best regards,

Hi, The question is not clear - are you looking for host operating system resource requirements to develop with TDA2? Please expand your question so that the team can provide an accurate response. Regards Karthik

Hello Karthik, Yes, we are looking for the minimun requirements for TDA2 for memory for each operative system. Best regards,

Hi, It is very difficult to answer the question. Can you please expand your question to include more details about your usecase? It would help by starting to experiment with the EVM with the SDK's provided by TI. And then you can estimate based on the application that you are trying to run on the TDA2. Do you have the list of application(s) that you plan to run and they will be realized in the heterogeneous core? We have realized systems with very low requirements of RAM, FLASH for very targetted usecases and we also have systems that had larger requirements. Perhaps, you can also look at the data sheet for numbers on the DRA7 (which is similar to TDA2) - processors.wiki.ti.com/.../Processor_SDK_Linux_Automotive_Data_Sheet Regards Karthik

Ticket Name: TDA2: DDR3 Interface pullup resistors of Address/Data Bus

Part Number: TDA2 Other Parts Discussed in Thread: DRA756, , , TPS51200-Q1 We study TDA2H/TDA2S/TDA2P reference schematics, we found difference between DDR3 interface schematics: 1. There are not pullup resistors with VTT on TDA2H/TDA2S reference schematics, but some technical support engineers recommend we add pullup resistors for TDA2H/TDA2S/DRA756 schematics; 2. The reference schematics of TDA2P-ACD and TDA2P-ABZ include the following pullup resistors. Would you please help us to explain following schematic usage and function ?

Hi Joseph, These resistors are terminations to VTT. If the memory type is DDR3/3L, TI has validated and supports only the fly-by topology of the C/A bus for each EMIF, with termination to VTT at the bus end. This implies that a dedicated VTT source (stand-alone regulator IC, or part of a complex DDR power solution) is employed in the design and that it is supplying the termination resistors of both EMIFs (the recommended automotive-qualified part is the TPS51200-Q1; it generates also the VREF voltage). If the ECC lane of EMIF1 has been utilized in the design, usage of the VTT-terminated fly-by topology is almost unavoidable for a 32-bit system (due to the odd number of memory chips and very difficult balancing otherwise). Regards, Stan

Ticket Name: TDA2PXEVM: How can I test the processing time of each layer on TDA

Part Number: TDA2PXEVM Hi, I am running my OD net on TDA2P and the output is fine. And it shows the fps of the whole CNN model running on EVE. Now, I want to analysis and test each layer's running time. SO, how can I get each layer's processing time?

Hi, To get each layer's running time, you need to rebuild TIDL with enabling profile in the library which needs source code access of TIDL. But, the issue here is that performance is worse because of your are running all the layers on EVE core, as detection output layer is not optimized on EVE core, so you can see that more cycles consumed on EVE. Could you please run this last detection output layer on DSP and all the remaining layers on EVE to get better performance. For that please refer to FAQ 21 and 22 in the TIDL user guide for the import and inference steps to partition layers on EVE and DSP. Thanks, Praveen

Hi, Praveen I have followed the FAQ 21 and 22 in user guide to set layerID and run detection output layer on DSP. My point is to test different convolution layer to see how does structure of convolution affect the performance. For example, testing whether setting group convolution is helpful for reducing running time, testing whether Nx1 + 1XN conv run faster than NXN conv, testing how much does sparse convolution help on different convolution layers. Those tests can help us a lot to run CNN on TIDL more efficiently. I am afraid the user guide is not enough for applying. So, is that possible to get source code to rebuild TIDL? Or, is there any testing tools for cnn testing? Thanks!

Hi, Please refer to section 1.2 Performance Summery in the TIDL data sheet where we had given "Convolution Layer Performance" for different combination of kenel sizes and sparse, dense kernels, so you can refer to that table and based on those cycles you can estimate for your network. Thanks, Praveen

Hi, Praveen Thanks for your advice. I don't have TIDL data sheet. Could you share it to me? I think it can help me a lot with estimating my network. Your replay is really helpful. Thanks again!

Hi, This TIDL data sheet (TIDeepLearningLibrary_DataSheet.pdf) also included along with TIDL user guide in the "REL.TIDL.01.01.03.00\modules\ti_dl\docs" folder. Also, attached here for your reference. Thanks, Praveen2577.TIDeepLearningLibrary_DataSheet.pdf

Ticket Name: TIDEP-01017: MLO file selection

Part Number: TIDEP-01017 Other Parts Discussed in Thread: TDA2 Hi Team, My customer just developing their own software using PROCESSOR_SDK_RADER for TIDEP-01017 When they run "gmake -s sbl" in PROCESSOR_SDK_RADER_03_08_00_00 environment, they get MLO files in 4 folders: opp_high, opp_low, opp_nom, opp_od under "vision_sdk\binaries\apps\tda2xx_cascade_bios_radar\sbl\sd" folder. which MLO file should they select for TDA2 mounted on TIDEP-01017? They think they need to select an MLO file according to OPP (Operating Performance Points). Regadrs, Takashi Onawa

Hi Team, Can I have any comments on this? Regards, Takashi Onawa

Hi Takashi, You can use any of the MLOs in the folder. I suggest that you start with OPP_NOM. Regards Karthik

Ticket Name: TDA2SX: L3 RAM issue

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi team, "Up to 2.5MB of on-chip L3 RAM" via TDA2 Datasheet", the customer would like to know where can they configure or check the "L3 RAM" part? Could you help check this case? Thanks. Best Regards, Cherry

Cherry, The TDA2 data manual Device Comparison table shows that all of the standard variants of TDA2 include 2.5 MB: The TRM Memory Map shows where those RAMs are located: Regards, Kyle

Hi Kyle, Thanks for your help. Is there any specific example or a modified case for reference? Thanks and regards, Cherry

The SDK will use this memory. Or, you can use CCS to view this memory directly. Regards, Kyle

Ticket Name: Linux/TDA2: -mfpu=neon where to add

Part Number: TDA2 Tool/software: Linux /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/ti_components/os_tools/linux/linaro/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/lib/gcc/arm-linux-gnueabihf/5.3.1/include/arm_neon.h:31:2: error: #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h -mfpu=neon where to add?

Hi Shuai , Are you getting this error while building vision sdk or linux . ? What build stage you have this error . ? Regards Chetan.M

Hi Chetan.M make -s -j i add some code use neon so error ! so -mfpu=neon where to add?

if its in bios cores i.e ipu , dsp , eve then add it in corresponding make rules vision_sdk\build\rtos\makerules for hlos cores vision_sdk\build\hlos\makerules\linux Regards Chetan.M

Hi Chetan.M for hlos cores PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/build/hlos/makerules/linux$ common_header_a15.mk ？？ How can it ，please specific? BESTWISHES SHUAI

Hi Shuai , CC_OPTS=-c -Wall -Warray-bounds -fPIC -mfpu=neon Regards Chetan.M

i find in SDK_VISION_03_02_00_00\vision_sdk\apps\src\hlos\MAKEFILE_adam_car.MK have -mfpu=neon and i add -mfloat-abi=softfp here ,but still error /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/ti_components/os_tools/linux/linaro/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/lib/gcc/arm-linux-gnueabihf/5.3.1/include/arm_neon.h:31:2: error: #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h how to solve this ? BESTWISHES SHUAI

Hi Chetan.M this (-mfloat-abi=softfp ) is not need?? thanks shuai

Hi Chetan.M i add like this CC_OPTS=-c -Wall -Warray-bounds -fPIC -mfpu=neon stille error, neon is not support? /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/ti_components/os_tools/linux/linaro/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/lib/gcc/arm-linux-gnueabihf/5.3.1/include/arm_neon.h:31:2: error: #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h BESTWISHES SHUAI

Shuai , CC_OPTS is the compiler c flags location . if you add the flags required here it is used while compilation . if you build without -s option you can see the expansion of all compiler option and macro . Regards Chetan.M

HI Chetan.M help me please /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/ti_components/os_tools/linux/linaro/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/lib/gcc/arm-linux-gnueabihf/5.3.1/include/arm_neon.h:31:2: error: #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h i add CC_OPTS=-c -Wall -Warray-bounds -fPIC -mfloat-abi=softfp -mfpu=neon but no done! how can i solve it? BESTWISHES SHUAI

Hi Shuai , i am not sure if its looking for flags in linking stage , you can add the flags at LD_OPTS=-lpthread and try , Else please look at arm compiler documentation Regards Chetan.M

"CC_OPTS="-c -Wall -Warray-bounds -fPIC -mfloat-abi=hard -mfpu=neon -w "CC_OPTS="-c -Wall -Warray-bounds -fPIC -mfloat-abi=hard -mfpu=neon -w In file included from conv11.h:2:0, from Arcsoft_AHD_Config.h:68, from Arcsoft_AHD_Utils.h:13, from Arcsoft_AHD_Net.h:4, from Arcsoft_AHD_Net.c:1: /home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/ti_components/os_tools/linux/linaro/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/lib/gcc/arm-linux-gnueabihf/5.3.1/include/arm_neon.h:31:2: error: #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h #error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h

Ticket Name: PROCESSOR-SDK-DRA8X-TDA4X: Importing mobilenet v1 (tensorflow) into TIDL for the TDA4

Part Number: PROCESSOR-SDK-DRA8X-TDA4X I tried importing mobilenet v1 224 starting from this tutorial for the TDA2: https://e2e.ti.com/support/processors/f/791/p/735984/2717341 I had to adjust many file names and many paths. In the end I've been able to convert mobilenet v1 into TIDL format. However, when I run the inference simulation, I get the following error: Processing config file #0 : testvecs/config/infer/public/tensorflow/tidl_infer_mobileNetv1.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 948.16 ... A : 896, 0.0000, 0.0000, 670 .... ..... # 1 . .. T 908.94 ... A : 558, 0.0000, 0.0000, 420 .... ..... # 2 . .. T 901.69 ... A : 443, 0.0000, 0.0000, 420 .... ..... # 3 . .. T 897.74 ... A : 499, 0.0000, 0.0000, 420 .... ..... # 4 . .. T 909.30 ... A : 539, 0.0000, 0.0000, 420 .... ..... # 5 . .. T 896.48 ... A : 539, 0.0000, 0.0000, 420 .... ..... # 6Error in reading �̽��, �̽�� Can anyone point me in the right direction ? Is there any tutorial about importing tensorflow mobilenet models for the TDA4 ? I tried searching the forums but found nothing clear. Thanks

Hi, You need to download latest SDK from http://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/index_FDS.html You should refer to TIDL user guide present here: http://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/tidl_j7_01_01_00_10/ti_dl/docs/user_guide_html/index.html Regards, Rishabh

Hello Rishabh, thank you for your quick reply. Is there any turorial ? The documentation merely lists a series of parameters and I find it very difficult to start from scratch. Any useful getting started guide ? Kind regards, Guido

Hi Guido, The same user guide has getting started tab. Please see http://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/tidl_j7_01_01_00_10/ti_dl/docs/user_guide_html/md_tidl_user_model_deployment.html Regards, Rishabh

Thank you Rishabh, thanks to your indications we were able to fix our problem !

Hi Guido, Thanks for the confirmation. I am closing the thread. Regards, Rishabh

Ticket Name: TDA4VM: PDK/MCAN - configuration for classic CAN mode

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hello, We are transmitting data over MCAN2. For the configuration of MCAN, we referred to the Gateway demo and MCAN EVM Loopback example from PDK. Our current configuration sets the mode of MCAN to CAN-FD with nominal bit rate of 1 Mbps. We wish to change this to classic CAN operating at 500 kbps. First, we simply tested the following change, but it did not work out. In the second attempt, we configured the following values, but these changes are also not working. Are these bit timings correct? Do we need to make any other changes to the MCAN configuration? Thank you.

Hi, Can you please make the following changes and check - bit.Times.nomRatePrescalar = 0xFU; bit.Times.nomTimeSeg1 = 0x5U; bit.Times.nomTimeSeg2 = 0x2U; You can find how to calculate bit rate in - https://processors.wiki.ti.com/index.php/PDK/PDK_FAQ#How_is_bit-rate_calculated.3F Regards, Karan

Hello Karan, We made your suggested changes, switched the mode to Classic CAN, and tested our vision app. The app loads and processes camera frames for 1 to 4 minutes, and after that, it freezes/hangs. We were able to reproduce this behavior 4 different times. We are able to see some CAN signals, but we did not validate whether those were correct, because that is irrelevant if the app hangs. Later, we reverted all changes, and the same application runs fine in CAN-FD mode with 1 Mbps data rate configuration. Your suggested changing one value for the MCAN_NBTP register. Do we need to make any more changes? Also, are there any changes required for the MCAN_DBTP register? Thank you.

Hi Sagar, I suspect this to an SW timing issue. Can you please check by adding inter packet delay's. i.e. transmit every 3rd or 4th frame. 500 Kbps has been used in many usecases without any issues. Regards, Sujith

Hello Sujith, The J7 TRM states that for MCAN functional clock (MCAN2_FCLK) frequency of 8 MHz, setting the MCAN_NBTP register to its reset value configures it to work at 500 kbps. Accordingly, we set 'fdMode' to (0x0U) and modified the bitTimes values in our vision app. But the vision app is not able to start. We will try out your suggestion and reply with our observations on this thread. In the meantime, I have two questions: 1. What is the nominal value of MCAN2 Functional Clock (FCLK) frequency? 2. Is this frequency being modified in the K3 MCAN EVM Loopback example? Thank you.

Hello Sujith, Sujith said: Can you please check by adding inter packet delay's. i.e. transmit every 3rd or 4th frame. We tested this, first for every 3rd frame, and then for every alternate (2nd) frame. In both tests, the vision app worked fine without any hang/freeze problem. We concluded both tests at the end of around 30000 frames, but I am assuming that the app would work fine for longer durations as well. So the MCAN settings shared by Karan are working for J7 MCAN 500 kbps operation. However, we are not able to transmit our CAN packets after every frame (33 ms). How can we resolve this issue? Note that on TDA2, we were able to transmit even larger CAN packets at every 30 ms or so. The difference is we used System_LinkControl on TDA2, and we are using Remote Service API on TDA4. Since my core issue is resolved, I can close this thread and open another one for further discussion. Kindly let me know. Thank you.

Hi Sagar, Yes, please close this thread and open a new one. Regards, Karan

Closing this thread. Thank you.

Ticket Name: Compiler/TDA2: Embed TIDL model bin into IPU image to run without SD card ?

Part Number: TDA2 Tool/software: TI C/C++ Compiler Hi, Is it possible to convert TIDL or SemSeg example to run from flash, without SD card ? i can change the input link to take video from a camera or HDMI, but I still need to supply NET.BIN and PRM.BIN model files to TIDL somehow without SD card. Model parsing functions can be changed to read net and prm from arrays in memory instead of files, but what would be the easiest way to place them into memory (flash) ? i.e. maybe link with IPU 1-0 code somehow? I am reading documentation for ti-cgt-arm_16.9.2.LTS tools, but cannot figure out how to join the code with model data. Total size of model bin files is about 3Mb. Thanks, Mikhail

I understand how to do that through conversion of the binary file to a C-array, but that means converting 3Mb bin to approximately 15Mb c-file. It would be nice if there is an option to do that through linker directly. Mikhail

Hi Mikhail , i can change the input link to take video from a camera or HDMI, but I still need to supply NET.BIN and PRM.BIN model files to TIDL somehow without SD card. Model parsing functions can be changed to read net and prm from arrays in memory instead of files, but what would be the easiest way to place them into memory (flash) ? You can always place it into QSPI flash . API for the same can be found in src/rtos/utils_common/include/utils_qspi.h Its used to dump the calib tables in following file for reference vision_sdk\apps\src\rtos\common_srv\chains_common_surround_view.c Regards Chetan.M

Hi Chetan, Thank you for the advice. I will try QSPI flash soon. Do you know if there are any code examples that use eMMC flash (with FAT FS) instead of SD card? I guess the difference between emmc and sdcard should be very small. Mikhail

Hi Mikhail , Can we close the thread , I am not sure if we have a pdk driver to access emmc . Regards Chetan.M

Yes. Thanks!

Ticket Name: Packet loss

Hello, Here's the description of the issue - Application/Usecase : HDMI display & Video streaming using RTP(real Time Protocol) with single camera at 30fps & Bit Rate: 10Mbps Processor & Framework : TDA2Px - Vision SDK 3.3 with ndk_2_25_01_11 & nsp_gmacsw_4_15_00_00 version Pipeline : Usecase : RTP - UDP - IP - NDK2NSP - GMAC (This is processed A15 core) NDK settings : Modified "NdkConfigGlobal.memRawPageSize = 64*1024;" from in NDK_config.cfg Modified "NDK_DATA_SIZE = 16*MB" from 4KB in file mem_segment_definition_bios.xs Modified "#define MMALLOC_MAXSIZE ((64 * 1024) - 4)" from 3KB in file pbm.c Implementation of RTP was a requirement from our customer. RTP protocol has been implemented and integrated in the VSDK. RTP implementation is simple, for bitrates of 5mbps & 10mbps - 15 packets/slices & 17 packets/slices with a size of ~7K(<8k) are sent sequentially in a burst. Socket options/parametes : AF_INET, SOCK_DGRAM, ipTTL=15, maxBufLen=65500U The video streaming works fine with 5 Mbps(bit rate) at 30fps. But in the case of 10mbps(bit rate) with 30 fps. We have observed last 2 IDR slices are lost on the wireshark i.e. last 2 sequence numbers are missing. After adding a delay of 2 ms just before sending the packets to cpdma driver, observed there are no slices lost on the wireshark but the frame rate drops to 17fps. Also noticed the delta is high and skew is also increased downwards from the wireshark logs. Do let us know if you need more information and any insights will be highly appreciated. Could you help us with network stack benchmarking information for the Tx ? Thanks.

Hi, I will check with an NDK expert then let you know. Thanks Gaviraju

Hi Gaviraju, Kidnly let us know if you have any updates. Thanks, Pramod

Hi, You can try to increase number of packets allocated for TX to if that helps. In nsp_xx_xx_xx_xx\packages\ti\nsp\drv\ndk2nsp\ndk2nsp.h, /*
 * Packet count of packets given to the hardware. We should use twice this number
 * for the number of packets maintained
 */
/*RX packets to be kept 128 to account for DUAL MAC and TFDTP enabled case*/
#define NDK2NSP_RX_PACKETS   (128U)
#define NDK2NSP_TX_PACKETS   (64U)

#define NDK_RX_PACKETS (NDK2NSP_RX_PACKETS * (uint32_t)2U)
 You can increase NDK2NSP_TX_PACKETS from 64 to 128.

Ticket Name: TDA2: Can DCAN1 run simultaneously with capture and display links?

Part Number: TDA2 The problem is similar to this “e2e.ti.com/.../716329 [IPU1-1] 97.623528 s: Assertion @ Line: 505 in D:/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/apps/src/rtos/modules/dcan/utils_dcan.c: status == 0 : failed !!! [IPU1-1] 97.623741 s: [IPU1-1] 97.623802 s: ### XDC ASSERT - ERROR CALLBACK START ### [IPU1-1] 97.623863 s: [IPU1-1] 97.624016 s: assertion failure: A_badContext: bad calling context. See GateMutex API doc for details. [IPU1-1] 97.624107 s: [IPU1-1] 97.624168 s: ### XDC ASSERT - ERROR CALLBACK END ### static Void Utils_dcanQuePut(Utils_QueHandle * handle, struct dcanQueMsgs_s *msg, dcanQueMsgState_e state) { Int32 status; msg->state = state; status = Utils_quePut(handle,msg,BIOS_NO_WAIT); UTILS_assert(status == 0);// this assert status == 0 : failed !!! }

Hi Yuling, DCAN can run along with capture and display links. In previous threads, user was able to get some message before seeing this error. Is your observation same? If yes, can you try doing changes suggested in attached thread(in your previous reply). Please let know your results. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Ticket Name: RTOS/TDA2: TDA2 utils_dcan question

Part Number: TDA2 Tool/software: TI-RTOS Hi, we use utils_dcan in SDK_VISION_03_04 and found something strange. we connect our device to the car with OBD connector, we want to read the velocity. the symptom is sometimes we can read the velocity and sometimes we can not read the velocity. and when we can not read, we need to restart the device and re-connect to the car. after some tests, we found the period call function still post event, but this event seems not trigger Utils_dcanTxTsk to send the read command. could you please help to give some hints or possibility to cause this symptom Thanks~~~

Hi Markii, I have few questions of this sentence 'after some tests, we found the period call function still post event, but this event seems not trigger Utils_dcanTxTsk to send the read command.' 1. Are these number of successful tests before seeing failure point same for each run? 2. This send command is actual a CAN message, right? So you seeing failure with CAN message transmission. Can you explain about the transactions happening in your CAN network? Like general flow of messages. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi Vivek, we enable periodic Tx and set txMsgPeriod_ms as 500 in dcanConfig. normally, we can get velocity every 500ms (Utils_dcanPrdCalloutFcn would do Event_post every 500ms, after event post we can read velocity from RxTsk) but sometimes we can not read the velocity suddenly (previous 500ms is ok), and if this symptom happened, we need to restart our device and re-connect to the car (unplug the connector and plug) we trace the source code and found the Utils_dcanPrdCalloutFcn still post event every 500ms, but the Utils_dcanTxMsg did not finish. and hang on Utils_dcanWaitForTxComplete. this symptom happen very often, we do not know why, could you please help to give us some advisement. Thanks~~

Hi Markii, By default automatic re-transmission is disabled in the DCAN demo. Can you please 'pDcanCfgPrms->autoRetransmitDisable' change from 'TRUE' to 'FALSE' in 'utils_dcan.c' file and re-try this application? Looks like your transmission is failing and transmission failing condition is not handled in the app. By enabling re-transmission, CAN controller will keep sending failed message until it succeeds. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Ticket Name: Compiler/TDA2EVM5777: How to bring up C6xx on TDA2 outside SDK using remoteproc

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hello *! I need to bring up the DSPs of the TDA2 using firmware mechanism of linux (remoteproc) outside the SDK, without using CCS and SYS/BIOS/RTOS. What Do I need and where do I find it in the visual-sdk provided by TI? (Of course, the cl6x will be needed to build the ELF, a custom mapping table for the remoteproc, something like a "startup code" setting IRQ-vector-table and jump to "main" of the C-Code... ) Are there any example available?

Hi Marco, I have forwarded your question to an expert for comment. Regards, Yordan

You can find information on remoteproc here: lwn.net/.../ The image needs to have a resource table for remoteproc to load the DSP ELF image. For example images that use SYS/BIOS and load with remoteproc, you can check the IPC3.x code: gitorious.ti.com/.../ipcdev processors.wiki.ti.com/.../IPC_Users_Guide You might find this other similar e2e query useful as well e2e.ti.com/.../948787 Thanks, Angela

Hello Angela, Thank you for the links, but this is not exactly what I need to getting started. A few weeks ago I took the things I thought I need to bring up the DSP: The resource table have almost been linked into the ELF file, I took the "interrupt.c" and "intvecs.asm" as something like a "startup code" and I wrote a very simple "main.c" containing a counting infinity loop... At a first look, there is no reason why it shouldn't work, but all I got is a "MMU fault" from the DSPs MMU. I think, the L3-preparation of the carveout memory works, but the stuff I took off the "visual SDK" is not adapted correctly and until now I try to find, what I did wrong. So I need help, but all I get in Forum or my FAE at TI are links to "IPCxxx" and I can't believe that there is no very simple example available, which do not use SYS/BIOS, RTOS-fragments... complex build environments to use dozens of SOCs over XDC... most code is designed to run without MMU... and of course the CL6X toolchain is very powerful, a lot of possibility... and, again: No idea what went wrong. So I need help to bring up the DSP realy bare metal, using only the TI toolchain and remoteproc. INTENTIONS: The requirements of my use-case are embedded in the need of very safe code (DSP, IPU and EVE - Linux only used a comfortable gateway...). So I have to implement only code, which is really needed. A universal BIOS or Bootloader in the DSPs and Subcores is forbidden. I did this for IPU successfully, but now I cut my teeth doing the same with the DSP... so I need help... urgently. Thank you for your dedication: Marco

Hi Marco, you can also check this E2E thread with discussion of similar topic: e2e.ti.com/.../640064 Regards, Yordan

Hi Yordan... *LOL* It's a little bit funny: Needhu is my "direct" contact at TI ;-)

PROBLEM SOLVED: After reviewing the whole code without finding any kind of mistakes, I took a look to the CALL of the CL6X and its linker-options: I read the ELF with readelf -a and saw, that the ENTRY-POINT points to symbol which don't make sense. I'm wondering about the decision of the CL6X setting this address... so I read the manual again: downloads.ti.com/.../linker_description.html I can set the entry point manually: --entry_point=... and the code I took out of the SDK, the DSP have to jump into "_vector0" to boot. This solved the problem, the DSP boot.

Ticket Name: TDA2SG: How can output yuv422 format in the display

Part Number: TDA2SG Hi ,expert: My system has three overlay in the display,like this : 1,VID1: BGRA32_8888 2.VID2: YUV420SP 3.GFX: BGRA32_8888 general, TDA2s use the rgb888 output to display, and my system is work ok,Now I want to use the yuv422( YUYV) to the display, I see the "dssm2mwb" link ,I found this link may need "sync" link and then use buftype of "SYSTEM_BUFFER_TYPE_VIDEO_FRAME_CONTAINER". I have the question as follow: 1,sync need 3 overlay framerate is same,but my system is not satisfy and overlay has different display framesrate, so i think this solution may not very well . 2,Is There other solution to yuv422 display output thanks!

Hi, do you mean yuv422 over embedded sync output interface? Rgds, Brijesh

no, I mean if i use sync link ,if one of queue has no video ,sync will no send cmd to process ,so I think this solution is not suit. Now I want to checkout the problem: 1,VID1: BGRA32_8888 ->YUYV 2.VID2: YUV420SP 3.GFX: BGRA32_8888 ->YUYV overlay like this,the display can work? 2) Is there some usecase of yuv422 output I can refer

hi, #1, in this case, you would require to change sync link to support this feature. Currently it is not supported. sync link does not output if one of the input is not available. #2, do you mean to use 3 video pipelines, each with different data type? yes, display will work with this combination #3, where yuv422 do you require? Is it at the output of capture link or input to the display link? Regards, Brijesh

output in the dispaly link , if i dont want to use "sync",I will do as follow: change RGBA328888 to YUYV format and it will make 3 video pipeline dataformat to 1,VID1: YUYV 2.VID2: YUV420SP 3.GFX: YUYV is the display link support "YUYV" and "YUV420sp" format output.

Yes, display link supports both of these formats. Rgds, Brijesh

I use capture_dsswb link ,and set vout format BT656 and DISPC_VP1_CONTROL.TDMENABLE = 0x1: TDM enabled DISPC_VP1_CONTROL. TDMPARALLELMODE = 0x0: 8-bit parallel output interface selected DISPC_VP1_CONTROL. TDMCYCLEFORMAT = 0x2: 2 cycles for 1 pixel DISPC_DATA1_CYCLE1 = 0x8 DISPC_DATA1_CYCLE2 = 0x8 DISPC_DATA1_CYCLE3 = 0x0 but my capture_dsswb has no video data,so I think writeback pipeline do not well work. how can I use writeback?

Hi, these two things are different and independent. could you help me with what exactly you are trying to enable? - are the three input video pipelines enabled? - why are you enabling TDM for BT656 output? - why are you enabling dss wb path? Regards, Brijesh

Ticket Name: RTOS/TDA2: tild_od usecase build error with MobileNet

Part Number: TDA2 Tool/software: TI-RTOS Hi All, I am building vsdk3.3.0 to test the proven the mobilenet in TIDL and get an error like below. It look like this error is related to "GRAPHICS_HEIGHT" size. # Compiling tda2px-evm:ipu1_0:release:app_libs: c:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/apps/src/rtos/useca ses/tidl_OD/chains_tidlOD.c "c:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/apps/src/rtos/usecases/tidl_OD/chains_tidlOD.c", line 439: error: integer conversion resulted in a change of sign "c:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/apps/src/rtos/usecases/tidl_OD/chains_tidlOD.c", line 447: error: integer conversion resulted in a change of sign 2 errors detected in the compilation of "c:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/apps/src/rtos/usecases/tid l_OD/chains_tidlOD.c". >> Compilation failure gmake[5]: *** [c:/PROCESSOR_SDK_VISION_03_03_00_00/vision_sdk/binaries/apps/tda2px_evm_bios_all/obj/app_libs/tda2p x-evm/ipu1_0/release/chains_tidlOD.oem4] Error 1 gmake[4]: *** [ipu1_0] Error 2 gmake[3]: *** [app_libs] Error 2 gmake[2]: *** [apps_libs] Error 2 gmake[1]: *** [apps] Error 2 gmake: *** [vision_sdk] Error 2 For reference, the test video resolution is 512x512 and the code changes are as follows. #define TIDL_OD_INPUT_WIDTH (512)//(768) #define TIDL_OD_INPUT_HEIGHT (512)//(320) #define DEC_OUT_WIDTH (512)//(768) #define DEC_OUT_HEIGHT (512)//(320) I found a similar problem in the e2e community as below but I did not get a solution. #link Please let me know what i do to fix. BR, Khethan

Hi all, There is not link-url on above so I attach the link as below. e2e.ti.com/.../721606 BR, Khethan

Hi, Can you try with any input having resolution less than 512 Regards, Anuj

Hi, have you tried with a lower resolution. Can you change TIDL_OD_DISPLAY_STARTY to 32 and try. Regards, Anuj

Ticket Name: TDA2SX: VSDK3.07

Part Number: Hi,Using mksdboot.h script to make SD card can succeed in ubuntu14, but SD card made in ubuntu18 cannot start kernel. Why? And I use the VSDK3.07. Please refer to the attached log file of unable to start the kernel and the printing process when making SD cards in different ubuntu versions.mksdboot fails the SD card.7z

Jade jiang said: Part Number: TDA2SX Hi, I use mksdboot.h script to make SD card can succeed in ubuntu14, but SD card made in ubuntu18 cannot start kernel. Why? And I use the VSDK3.07. Please refer to the attached log file of unable to start the kernel and the printing process when making SD cards in different ubuntu versions. mksdboot fails the SD card.7z

Hi, Yes, the mksdboot.sh will not work in the Ubuntu 18.04 version, because the Ubuntu 18.04 is not a stable version & it's having lot of issue. So please don't try from the Ubuntu 18.04 & we tested only in the Ubuntu 14.04. Thanks Gaviraju

Hi, If sdk3.07 is used all the time, is there any solution? Thanks Jade

Hi, Moreover, as far as I know, the SDK software of TDA4 is already available in Ubuntu 18. When will tda2 consider updating? Thanks Jade

Hi, No more development on TDA2 vision SDK & it's in support mode. Thanks Gaviraju

Ticket Name: TDA2EVM5777: how to add new sensor to TDA2

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2, TDA2PXEVM Dear TI I would like to include in new sensor to the TDA2. How or where can i create it to do that?

Hi Wilson, You can check this Application Note: processors.wiki.ti.com/.../PDK_Application_Notes_Video_Driver_Porting and also Chapter 3 in "vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_ISS_SensorFrameWork.pdf" Regards, Yordan

Hi Yordan Can i ask what is ISS stands for?

Hi Wilson, It's Imaging Sub-System. Regards, Yordan

Hi Yordan I wouls like to ask what is the follow abbreviation DCC H3A GLBCE AEWB Also is it a must for me to code them? On top of this ISS is it suitable to run in TAD2EVM5777 if i am going to add this new sensor? From the VisionSDK it seem like its for the TDA3xxEVm and TDA2PxEVM instead.

Hi Wilson, These components are used in the ISS usecase, ISS is present in TDA3x and TDA2Px It is not supported in TDA2Ex. DCC = Dynamic Camera Configuration H3A = Statistics generation module for AE and AWB. GLBCE = Global and Local Contrast and brightness Enhancement AEWB = Auto Exposure and White Balance Rgds, Brijesh

Hi Brijesh So if that the case how can i should i go about for the a new sensor then?

Wilson, You could capture from RAW Bayer data from the new sensor on TDA2x/TDA2Ex, but since there is no ISS, you will require SW solution to process and convert RAW data into YUV. The other way is, you could use YUV sensor. Rgds, Brijesh

The Brijesh in other words can i say there is no algo in the SDK to help us to process this Ray Bayer. I have to code it myself.

yes

Dear Brijesh I notice there are 2 type of yuv which format i should be convering the bayer to?

Wilson, DSS supports both YUV420 (Semi-planar) and YUV422 (Interleaved) data format. So if you could convert RAW to one of these data format, dss will be able to display it. Rgds, Brijesh

Ticket Name: RTOS/TDA2: Error in TI IVAHD H.264 Encode function

Part Number: TDA2 Tool/software: TI-RTOS Hi TI Experts, I am trying to encode a frame using ti ivahd encoder api but i am getting error that means: Active frame region dimensions are not matching with the encoding frame dimensions I am using APIs in the same sequence as suggested in H264enctest.c sample application. Also i am not giving input frm some file but some data as given below: #pragma DATA_SECTION(".input_buffer") uint8_t luma_buffer[176*144]; #pragma DATA_SECTION(".input_buffer") uint8_t chroma_buffer[176*144/2]; memset(&luma_buffer,0x22,sizeof(luma_buffer)); gInputBufDes[0].planeDesc[0].buf = (XDAS_Int8*)luma_buffer; memset(&chroma_buffer,0x22,sizeof(chroma_buffer)); gInputBufDes[0].planeDesc[1].buf = (XDAS_Int8*)chroma_buffer; result = H264ENC_encodeFrame(m_encHandle[0],&gInputBufDes[0],&gOutputBufDesc[0],&gInArgs[0],&gOutArgs[0]); real_error = status.videnc2Status.extendedError; real_error = 0,that suggests Active frame region dimensions are not matching with the encoding frame dimensions. If anybody suggest which parameter settings i am getting wrong or the sequence is not correct. Error suggests mismatch in frame dimensions,since i am currently working using qcif so everywhere i am setting width*height = 176*144. Thanks in advance Regards Mayank

Hi, Have you tried with encoder link of vision sdk? Whats your observation there? Regards, Anuj

Hi Mayank, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Ticket Name: TDA2EXEVM: How can I improve my train recognition accuracy using subclass attributes in ssdJacintoNetV2 networks?

Part Number: TDA2EXEVM Hi, There's a problem，I use the ssdJacintoNetV2 which is Ti provided Object detect net. In the identification of traffic signs, one kind of images often make mistakes, resulting in low identification errors. just show as blow. The left image is belong to the speed limit signs, which I need to recognize in my task, but the right image is very similar to the left，which not in my task. How can I strengthen my training for this situation？The right image is not marked in my sample. 1、Can I use subclass attributes to reinforce the training of the sample? 2、We want to get a good result of vehicle identification at night，For ssdJacintoNetV2 networks, I need to separate night vehicles into another one category or a subcategory，or just in the car category without subdivision？ typedef struct { uint32_t objTag; uint32_t objType; uint32_t objSubType; uint32_t xPos; uint32_t yPos; uint32_t objWidth; uint32_t objHeight; float objScore; float objScale; float reserved0; float reserved1; float reserved2; } TI_OD_objectDescriptor;

I don't think SSD is appropriate approach for identifying fine difference as you are looking for.

I'm assuming this is closed.

Ticket Name: TDA2PXEVM: TDA2: Power and reset buttons

Part Number: TDA2PXEVM Please explain the functionalities of the following buttons in TDA2P board, Attached image of what I am refring to. , 1. Power Cycle 2. CPU Reset switch 3. Power Reset switch Thanks, Sandeep

Hi Sandeep, Please refer to section 3.3 Reset Structure in https://www.ti.com/lit/ug/spruii4a/spruii4a.pdf . 1. Power Cycle - Power ON or Power OFF command to PMIC 2. CPU Reset switch - Warm reset to SoC 3. Power Reset switch - SoC cold (Power-On) (aka POR) Reset Regards, Stan

Ticket Name: Compiler/TDA2: Tda2x VisionSDK

Part Number: TDA2 Tool/software: TI C/C++ Compiler Dear Officer, Understood TI provide 2 set of build system: one is bios/rtos and another one is Linux. Can I check if I can build Linux option in windows environment by gmake? e.g. Is this below case OK? In Rules.make, set: MAKECONFIG=tda2xx_evm_linux_opencx Then go to Windows cmd prompt and run "gmake" Or all the Linux configuration must be build in native Linux host machine? Thanks and best regards He Wei Team leader for System Architectures and deep learning

Hi He Wei, you can build VisionSDK Linux only on Linux host (but you should be able to use virtual machine). You can build VisionSDK BIOS on either Linux or Windows. Regards, Yordan

Ticket Name: TDA2P-ACD: Resolution and frame rate auto-switching issue

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Dear TI Colleagues I have a question about the Display Subsystem (DSS) module. I would like to ask if the parallel video outputs can switch from 1280*720@30fps to 1980*1080@15fps multiple times to each other when the device is powered on? This kind of output switching needs to re-initialize the system? Regarding the configuration of the TI chip which initializations need to be redone and what needs to be turned off before doing so?

hi, Well, if you can stop the display, reconfigure for the new resolution and restart, it's possible. No need to restart the entire SoC. Regards, Brijesh

hi，Brijesh Jadav I have several questions. 1. How to stop/config/start DSS, which API? and how to restart the OpenVX graph？ 2. Is there a successful case to refer to in tda2, is there a demo to refer to? Look forward to your reply.

Well, you could stop the vision sdk chain, reconfigure the DSS and then restart the chain. That's one way. What do you mean by OpenVX graph? TDA2Px uses vision sdk link-chain framework, so there is no OpenVX graph. Regarding TDA2x demo, yes, you can go to settings->display settings and change the display resolution and then re-run the vision sdk usecase. Regards, Brijesh

Ticket Name: Linux/TDA2: Saving video in SD card of TDA2xx

Part Number: TDA2 Tool/software: Linux Hi Everyone , I am working on a usecase which could save display videos on the SDcard in TDA2xx , I have created a usecase as below : Capture->VPE->Sync->SGXFramecopy->dup dup -> Display dup -> Encode -> Null We wanted to save video after framecopy block , we know that SGXframecopy output results to RGB32 data and also encode block supports only yuv data . I like to know the following things : 1) How can we save video data as mpeg / h264 data format in sdcard after framecopy directly. ? 2) If not , I like to know how to convert RGB32 data to YUV to give to encoder so that we can convert YUV to mpeg ? Regards, Surendar

Hi, If you want to save encoded data then do not use SGXFramecopy. Even sync is also not required. You can use below usecase Capture->VPE->dup dup-> Display Dup -> Encoder -> Null 1) How can we save video data as mpeg / h264 data format in sdcard after framecopy directly. ? Ans- Output of framecopy is not encoded so you will not be able to save data as mpeg / h264 data format in sdcard after framecopy directly Regards, Anuj

Hi Anuj , We want to save the output of framecopy , kindly suggest me is there any way to save the video output of sgxframecopy. Is there any converter block ? . We are using 4 cameras , i like to save the video after stitching so I wanted to know whether it is possible or not Regards, Surendar

Hi, You can save the data after sgxframecopy using Null link but that will be in SYSTEM_DF_ABGR32_8888 format. Regards, Anuj

Hi Anuj , I understand that it will be in BGR format , is there any converter block to convert this to h264 /mpeg . I am not sure about this , Can we use any linux commands inside the usecase that will convert this data? . Regards , Surendar

Hi Surendar You could DSS WB M2M to convert RGB to YUV format. Rgds, Brijesh

Hi Anuj & Brijesh , It is working using DSS WB M2M block , we used following framework : Capture -> VPE -> Sync (A15) -> SgxFrmcpy (A15) -> Dup Dup -> DssM2mWb - > Encode -> Null (A15) Dup -> Display Now we can save video on sd card after framecopy .

Ticket Name: Compiler/TDA2: EVE/VCOP Question about __agen

Part Number: TDA2 Tool/software: TI C/C++ Compiler Hi, I try release next equation for agen __agen kLeft = I1 * blockW * sizeof(*img) + I2 * VCOP_SIMD_WIDTH * sizeof(*img) - I3 * sizeof(*img); There is no problems in host emulation. But eve compiler doesn't understand "-" near I3. In programming guide it is writen example with negative adress. I rewrite next way .__agen kLeft = I3 * -sizeof(*img) + I1 * blockW * sizeof(*img) + I2 * VCOP_SIMD_WIDTH * sizeof(*img); There is no compiler errors. but still result is wrong. Could your help me, whis syntax is right in this case?

Also, I try use next version of agen .__agen kLeft = I3 * sizeof(*img) *(-1) + I1 * blockW * sizeof(*img) + I2 * VCOP_SIMD_WIDTH * sizeof(*img); Compiler return next error: integer conversion resulted in a change of sign in .c file

Hi Danil, I myself have not used negative offset but following syntax should work : __agen kLeft = I3 * (- sizeof(*img) ) + I1 * blockW * sizeof(*img) + I2 * VCOP_SIMD_WIDTH * sizeof(*img); If you are seeing functional mismatch with this I would suggest you to run the kernel on EVE simulator and see if you observe the same behavior in it. If yes then you can step in and see what exactly is happening which is causing the mismatch. Regards, Anshu

Ticket Name: TDA2: Data Flow in TDA2x

Part Number: TDA2 Hello, We are trying to understand the data flow in TDA2x. We have the following queries: 1. How data and control are given from IPU0 to DSP/EVE and vice-versa? 2. How does data handling happen between DSP and EVE? 3. In which layer do these communications take place in Vision SDK? 4. Through which physical interface(hardware component) does this data transfer happen? 5. How does mailbox work? Regards, Shruti

Hi Shruti, Please refer to Vision SDK architecture documents present in PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\docs\Architecture. Regards, Rishabh

Hi Rishabh, Thank you. I found the answers to most of the questions in the documentation present. Still, I did not find out about the following: 4. Through which physical interface(hardware component) does this data transfer happen? Can you please help me find them? Regards, Shruti

Hi Shruti, There is no physical interface as this is internal to SoC, the communication is using IPC where messages contain buffer pointers. Regards, Rishabh

Thank you Rishabh. Regards, Shruti

Hi Shruti, I am closing the thread as the issue is resolved. Regards, Rishabh

Ticket Name: Cannot run use cases while TDA2 boot from eMMC

Other Parts Discussed in Thread: TDA2 Hi, If I boot TDA2 from SD card and run use cases, everything is OK. Now I boot it from eMMC and run the same code, there is something wrong with use cases. ASSERT (system_ipc.c|System_ipcInit|63) [IPU1-0] 8.081711 s: ***** IPU1_0 Firmware build time 13:26:09 Feb 9 2017 [IPU1-0] 8.081894 s: *** SYSTEM: CPU Frequency <ORG = 212800000 Hz>, <NEW = 212800000 Hz> [IPU1-0] 8.201244 s: SYSTEM: System Common Init in progress !!! [IPU1-0] 8.202128 s: SYSTEM: IPC init in progress !!! [IPU1-0] 8.202372 s: SYSTEM: Attaching to [IPU2] ... [HOST ] 11.728485 s: SYSTEM: System A15 Init in progress !!! [HOST ] 11.728546 s: SYSTEM: IPC: Init in progress !!! [HOST ] 11.728546 s: SYSTEM: IPC: Notify init in progress !!! [HOST ] 11.730804 s: SYSTEM: IPC: [IPU1-0] socket bind failed (Invalid argument, 22) !!! [HOST ] 11.730834 s: SYSTEM: IPC: [IPU1-0] Notify RX channel create failed (endpoint = 81) !!! [DSP1 ] 8.184133 s: ***** DSP1 Firmware build time 09:58:42 Jan 9 2017 [DSP1 ] 8.184194 s: *** SYSTEM: CPU Frequency <ORG = 600000000 Hz>, <NEW = 700000000 Hz> [DSP1 ] 8.200817 s: SYSTEM: System Common Init in progress !!! [DSP1 ] 8.201030 s: SYSTEM: IPC init in progress !!! [DSP1 ] 8.201091 s: SYSTEM: Attaching to [IPU1-0] ... [DSP1 ] 9.200817 s: SYSTEM: Attaching to [IPU1-0] ... [DSP1 ] 10.200847 s: SYSTEM: Attaching to [IPU1-0] ... [DSP1 ] 11.200878 s: SYSTEM: Attaching to [IPU1-0] ... [EVE1 ] 8.767248 s: ***** EVE Firmware build time 09:58:43 Jan 9 2017 [EVE1 ] 8.768834 s: *** SYSTEM: CPU Frequency <ORG = 267500000 Hz>, <NEW = 267500000 Hz> [EVE1 ] 8.771426 s: SYSTEM: System Common Init in progress !!! [EVE1 ] 8.774019 s: SYSTEM: IPC init in progress !!! [EVE1 ] 8.776123 s: SYSTEM: Attaching to [IPU1-0] ... [EVE2 ] 8.767370 s: ***** EVE Firmware build time 09:58:44 Jan 9 2017 [EVE2 ] 8.768956 s: *** SYSTEM: CPU Frequency <ORG = 267500000 Hz>, <NEW = 267500000 Hz> [EVE2 ] 8.771518 s: SYSTEM: System Common Init in progress !!! [EVE2 ] 8.774171 s: SYSTEM: IPC init in progress !!! [EVE2 ] 8.776276 s: SYSTEM: Attaching to [IPU1-0] ... [IPU2 ] 8.730464 s: [IPU2 ] EVE1 Image Load Completed [IPU2 ] 8.754376 s: [IPU2 ] EVE2 Image Load Completed [IPU2 ] 8.754498 s: [IPU2 ] EVE MMU configuration completed [IPU2 ] 8.754559 s: [IPU2 ] EVE MMU configuration completed [IPU2 ] 8.754651 s: ***** IPU2 Firmware build time 13:26:10 Feb 9 2017 [IPU2 ] 8.754773 s: *** SYSTEM: CPU Frequency <ORG = 212800000 Hz>, <NEW = 212800000 Hz> [IPU2 ] 8.756786 s: [IPU2 ] 8.756877 s: ### XDC ASSERT - ERROR CALLBACK START ### [IPU2 ] 8.756938 s: [IPU2 ] 8.757213 s: assertion failure [IPU2 ] 8.757274 s: [IPU2 ] 8.757304 s: ### XDC ASSERT - ERROR CALLBACK END ### [IPU2 ] 8.757365 s: [DSP1 ] 12.200908 s: SYSTEM: Attaching to [IPU1-0] ... [DSP1 ] 13.200939 s: SYSTEM: Attaching to [IPU1-0] ... [DSP1 ] 14.200939 s: SYSTEM: Attaching to [IPU1-0] ... [DSP1 ] 15.200969 s: SYSTEM: Attaching to [IPU1-0] ... [DSP1 ] 16.201000 s: SYSTEM: Attaching to [IPU1-0] ... Message will show "SYSTEM: Attaching to [IPU1-0]" continuously. BTW, the memory size is also different between the two booting mode. Booting from SD card: root@dra7xx-evm:~# free total used free shared buffers Mem: 634348 163636 470712 0 10260 -/+ buffers: 153376 480972 Swap: 0 0 0 Booting from eMMC: root@dra7xx-evm:~# free total used free shared buffers Mem: 2046540 143512 1903028 0 2892 -/+ buffers: 140620 1905920 Swap: 0 0 0 What is the different between SD card booting mode and eMMC booting mode? How can I run use cases while boot from eMMC? I am working on TDA2xx with VSDK v2.10. A15 OS is Linux. Thanks, Kevin Tsai

Hi, Kevin, Your question has been forwarded to VSDK expert. Regards, Mariya

ravi can you please respond? regards, Shiju

Hi Kevin, There should be no difference in memory and running usecases whether you are using SD/EMMC. This could be either related to filesystem or boot parameters. Are you using pre-built binaries or compiled? Please share boot parameters . You could print the boot environment in u-boot Stop at U-boot prompt (when it says hit any key to stop autoboot) and use command "printenv". Also did you copy the uenv.txt file to boot partition? If you modified uenv.txt, please share it. Regards, RK

Hi Ravikumar, I make a copy of uenv.txt and rename it as uenv-emmc.txt. Now, I can run usecase. Thanks for your reminding. Kevin

Hi Kevin, Thanks for updating the status of the thread. I will mark it as closed, if you have any other issues, you can write here. Regards, Yordan

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 1. The state of TDA2Sx watchdog in the TRM is, the device includes one watchdog timer. While in the datasheet of TDA2Sx, the state is that the device has two watchdog timers. Why? 2. How many watchdogs in TDA2Sx? And which modules does these watchdog monitoring? Our company used the TDA2 module classification in the safety manual Chapter 3.8. Maybe you can give a list of watchdog in TDA2SX and their corresponding monitoring module (modules refer to safety manual Chapter 3.8). thank you！

Section 4.3.6 from the TRM clarifies this: "The MPU watchdog timer (MPU_WD_TIMER) implements two channels, one per MPU core (MPU_WD_TIMER_C0 and MPU_WD_TIMER_C1, respectively" So there is "one" watchdog timer with 2 independent channels. Each one has an independent period with its own interrupts, so effectively it is like having two timers. I'm not sure what you mean by corresponding monitoring module. Could you specify what safety manual you are referring to? Regards, Zack

The safety manual is TDA2_TDA2P_DRA7_safety_manual_spruii9 Thank you!

The watchdog timers in TDA2 do not correspond to any monitoring module, so I'm not sure what your question is. As the safety manual says in section 3.8.3.2: "The watchdog is a traditional single-threshold watchdog. The user programs a reload value to the watchdog, and must provide a predetermined “pet” response to the watchdog before the timeout counter overflows. Overflow of the timeout counter triggers an error response. The watchdog can issue either an internal (warm) system reset or a CPU interrupt upon detection of a failure." So it's unrelated to the other modules in section 3.8. Let me know if you have any other questions.

the first question : how many watch dog timer and its location is at which module for TDA2SX?

There are actually 2 watchdog timers. The one I reference above is in the MCU domain, and is described in section 4.3.6 of the device TRM. The other is the system watchdog timer, and is in the PD_WKUPAON power domain.

Ticket Name: TDA2: Why crystal for xi_osc1 input is different from xi_osc0?

Part Number: TDA2 I am referring to VAYU EVM schematic, is there any special reason why xi_osc1 uses 22.5792MHz crystal but not 20MHz crystal, same as what is used at xi_osc0? Notice that the 20MHz crystal specification can fulfill the requirements stated for xi_osc1.

Hi, OSC1 is optional and only OSC0 is mandatory for the device. OSC1 is useful for on-chip audio peripherals and allows you to use an 'audio frequency', one example of such is 22.5792MHz. If you are currently designing a PCB, place a crystal footprint for OSC1 - you can decide for the crystal frequency or for no-pop at later time. Regards, Stan

Ticket Name: AM5728: _

Part Number: AM5728 Dear sir, Are there any documents can guide me how / where to modify the visualization for TIDL OD results? As attachment, I'm going to modify the category labels and the color of detected boxes. Thank you, Gary

Hi Gary, you can look at function AlgorithmLink_objectDrawRectangles() in vision_sdk/apps/src/rtos/alg_plugins/objectdetection/objectDrawLink_algPlugin.c and try to modify it according to your needs. (one note: please when creating a new thread choose TDA2x as your device - we will be able to look at your threads quicker) Regards, Yordan

Ticket Name: TDA2HG: How many eves available in TDA2HG?

Part Number: TDA2HG Hi One question puzzles me that how many eves are available in TDA2hg series? I found 4 eves availabe in TDA2xx and only 2eves availabe in TDA2hg from VisionSDK_data_sheet. However,4 eves defined when creating own usecase.when i check cpu load information,every eve's utilization over 75%. So,whether there is overclocking if there are only 2 eves?

Hi, Only 2 EVE is available in the TDA2HG. Can you share the custom use-case chain? Thanks Gaviraju

Hi here is the chain: Defination: /* TIDL on EVE1 */ pUcObj->Alg_tidl_Eve1Prm.cacheInvInBuf = 0; pUcObj->Alg_tidl_Eve1Prm.cacheWbOutBuf = 0; pUcObj->Alg_tidl_Eve1Prm.pAlgCreateParams = pObj->pAlgCreateParams; pUcObj->Alg_tidl_Eve1Prm.curCoreId = TIDL_COREID_EVE1; pUcObj->Alg_tidl_Eve1Prm.currLayersGroupId = TIDL_LAYER_GROUPID_EVE1; pUcObj->Alg_tidl_Eve1Prm.ocmcAddr = OCMC_3_BASE_ADDRESS; #endif /* TIDL on EVE2 */ pUcObj->Alg_tidl_Eve2Prm.cacheInvInBuf = 0; pUcObj->Alg_tidl_Eve2Prm.cacheWbOutBuf = 0; pUcObj->Alg_tidl_Eve2Prm.pAlgCreateParams = pObj->pAlgCreateParams; pUcObj->Alg_tidl_Eve2Prm.curCoreId = TIDL_COREID_EVE2; pUcObj->Alg_tidl_Eve2Prm.currLayersGroupId = TIDL_LAYER_GROUPID_EVE2; pUcObj->Alg_tidl_Eve2Prm.ocmcAddr = OCMC_3_BASE_ADDRESS;//OCMC_3_BASE_ADDRESS + (OCMC_3_SIZE/2); pUcObj->Alg_tidl_Eve2Prm.ocmcAddr = OCMC_3_BASE_ADDRESS + (OCMC_3_SIZE/2); /* TIDL on EVE3 */ pUcObj->Alg_tidl_Eve3Prm.cacheInvInBuf = 0; pUcObj->Alg_tidl_Eve3Prm.cacheWbOutBuf = 0; pUcObj->Alg_tidl_Eve3Prm.pAlgCreateParams = pObj->pAlgCreateParams; pUcObj->Alg_tidl_Eve3Prm.curCoreId = TIDL_COREID_EVE3; pUcObj->Alg_tidl_Eve3Prm.currLayersGroupId = TIDL_LAYER_GROUPID_EVE3; pUcObj->Alg_tidl_Eve3Prm.ocmcAddr = OCMC_1_BASE_ADDRESS; /* TIDL on EVE4 */ pUcObj->Alg_tidl_Eve4Prm.cacheInvInBuf = 0; pUcObj->Alg_tidl_Eve4Prm.cacheWbOutBuf = 0; pUcObj->Alg_tidl_Eve4Prm.pAlgCreateParams = pObj->pAlgCreateParams; pUcObj->Alg_tidl_Eve4Prm.curCoreId = TIDL_COREID_EVE4; pUcObj->Alg_tidl_Eve4Prm.currLayersGroupId = TIDL_LAYER_GROUPID_EVE4; pUcObj->Alg_tidl_Eve4Prm.ocmcAddr = OCMC_2_BASE_ADDRESS;

Hi, This is expected output & when we run default TIDL_OD use-case in TDA2XX platform having 4 EVE core, we can see the 90% of CPU Load with below configuration inputWidth=768 inputHeight=320 inputFile=inData_OD inputHDRFile=inHeader_OD netFileName=tidl_net_jdetNet_ssd.bin paramFileName=tidl_param_jdetNet_ssd.bin fps=30 threshold=0.3 Thanks Gaviraju

Hi I got it. Thaks a lot . Z.Y Wang

Ticket Name: TDA2SA: ISO21434 Compliance with TDA2 family

Part Number: TDA2SA Hi, could you share me the TDA2x documents about Security(SPRUHS7) and Cryptographic(SPRUHS8) addendums? we need to modify design to compliance with ISO21434, Thanks

Ticket Name: CCS/TDA2EVM5777: how about the EDMA in TDA4

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: Code Composer Studio i am trying TDA4EVM , how can i using EDMA move data from DDR to L2? befor in TDA2 visonsdk i find a sample about this (ti_SDK_VISION_03_04_00_00\ti_components\algorithms\REL.DMAUTILS.00.08.00.02) where can i find the same dma sample in TDA4 sdk (ti-processor-sdk-linux-automotive-j7-evm-06_01_00_05-Linux-x86-Install)? thanks! shuai

Hi Shuai There is no EDMA in the TDA4x device. Instead there is a UDMA and DRU for data routing. You can refer to the DMAUTILS in pdk/packages/ti/drv/udma/dmautils. This is part of Processor SDK RTOS Automotive. Thanks and Regards Piyali

Ticket Name: TDA2: VYUY format to YUYV or UYVY or YUV420SP Color Conversion

Part Number: TDA2 Hi, We have used the VSDK 3.04. I know converting YUYV to UYVY or YUV420SP, UYVY to YUYV or YUV420SP in VSDK. But I don't know converting VYUY to UYVY or YUV420SP, VYUY to YUYV or YUV420SP in VSDK The color format input from our Camera is VYUY. So we want to convert VYUY color format to YUYV or UYVY or YUV420SP using VPE for display. Please Let me know how to convert VYUY color format to YUYV or UYVY or YUV420SP. Regards, JP Park

As far as I know this is not possible. Let me check this again once more if by using VPDMA we can swap these bytes.

Hi Sivaraj Thank you for your quick response. Please Let us know if you can use VPDMA to swap this byte or not. I have tried to test it after modifying as below. chains_common_vision.c : pInprms->dataFormat = SYSTEM_DF_YUV422I_VYUY; : pOutprms->dataFormat = SYSTEM_DF_YUV422I_YUYV; vpscore_vip.c if (FVID2_DF_YUV422I_VYUY == pathObj->srcColorSpace) { /* Special handling for 420SP and 422SP only for UV order. * Y and UV channel swap will be done in * VpsCore_vipPathCheck422SPOut() */ if (FVID2_DF_YUV422I_YUYV == pathObj->dstColorSpace[strm]) { pathObj->dstColorSpace[strm] = FVID2_DF_YUV422I_YVYU; -> FVID2_DF_YUV422I_YUYV : modify } However, it has not been converted to the normal color format. Regards, JP Park

Can you test once again without changing any driver and just by setting output data format to FVID2_DF_YUV422I_VYUY? VIP assumes 8-bit data to come in as U0 Y0 V1 Y1. When we select FVID2_DF_YUV422I_VYUY output format, we typically get V1 Y0 U0 Y1. Since your inout is U and V swapped (V0 Y0 U1 Y1), when you do this you should get U1 Y0 V0 Y1. That is 422I_UYVY.

Hi Sivaraj I have tried to set output data format to FVID2_DF_YUV422I_VYUY but occuerrd format error in display driver. So i tried as below. if (FVID2_DF_YUV422I_YUYV == pathObj->dstColorSpace[strm]) { pathObj->dstColorSpace[strm] = FVID2_DF_YUV422I_YVYU; -> FVID2_DF_YUV422I_YUYV : modify } and i have tried to modify various format but failed. Please give me other infrom solving VYUY input format. e2e.ti.com/.../2629593 Regards, JP Park.

Park, Display does not support this format. First can you check if are you able to capture correct data with the suggested format? Then we need to modify display link to change format accordingly. Rgds, Brijesh

Hi JP, I am closing thread due to inactivity. Please open it if you have further questions. Rgds, Brijesh

Hi Brijesh, I have tested it with the following modifications, but this problem has not been solved. - chains_common_vison.c pInstPrm->videoIfMode = SYSTEM_VIFM_SCH_DS_HSYNC_VSYNC; pInstPrm->videoIfWidth = SYSTEM_VIFW_8BIT; pInstPrm->bufCaptMode = SYSTEM_CAPT_BCM_FRM_DROP; pInstPrm->numStream = 1; pInprms = &pInstPrm->inParams; pInprms->width = captureInWidth; pInprms->height = captureInHeight; pInprms->dataFormat = SYSTEM_DF_YUV422P; pInprms->scanFormat = SYSTEM_SF_PROGRESSIVE; for (streamId = 0; streamId < CAPTURE_LINK_MAX_OUTPUT_PER_INST; streamId++) { pOutprms = &pInstPrm->outParams[streamId]; pOutprms->width = pInprms->width; pOutprms->height = pInprms->height; pOutprms->dataFormat = SYSTEM_DF_YUV422I_VYUY; //modify pOutprms->maxWidth = pOutprms->width; pOutprms->maxHeight = pOutprms->height; pOutprms->scEnable = FALSE; - and modify displayLink_drv.c to avoid display format error dssPrms->inFmt.height = pInChInfo->height; dssPrms->inFmt.pitch[0u] = pInChInfo->pitch[0]; dssPrms->inFmt.pitch[1u] = pInChInfo->pitch[1]; dssPrms->inFmt.pitch[2u] = pInChInfo->pitch[2]; dssPrms->inFmt.dataFormat = SYSTEM_DF_YUV422I_UYVY; //modify //System_Link_Ch_Info_Get_Flag_Data_Format(pInChInfo->flags); if(dssPrms->inFmt.dataFormat == SYSTEM_DF_ARGB32_8888) { /* Convert to equivalent Display format */ dssPrms->inFmt.dataFormat = SYSTEM_DF_BGRA32_8888; } dssPrms->inFmt.fieldMerged[0] = FALSE; dssPrms->inFmt.scanFormat = FVID2_SF_PROGRESSIVE; if (pObj->createArgs.displayScanFormat == SYSTEM_SF_INTERLACED) { dssPrms->inFmt.fieldMerged[0] = (UInt32)TRUE; dssPrms->inFmt.scanFormat = FVID2_SF_INTERLACED; } Do you support the VYUY format ? Regards, JP Park.

Hi Park, It seems to be supported. Can you please dump one capture frame and share it across? Rgds, Brijesh

Ticket Name: Compiler/TDA2: Available memory ranges:

Part Number: TDA2 Tool/software: TI C/C++ Compiler Hi: i do not know what is the problem! vision_sdk\sample_app\src\rtos\alg_plugins\framecopy this link is use c66xdsp_1 I think ! why c66xdsp_2 have problem? and what is the problem? "/home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/sample_app/tda2xx_evm_linux_all/obj/vision_sdk/tda2xx-evm/c66xdsp_2/release/vision_sdk_configuro/linker_mod.cmd", line 247: error: program will not fit into available memory. placement with alignment fails for section ".fardata" size 0xc11ae6 . Available memory ranges: DSP2_DATA_MEM size: 0xa00000 unused: 0x9d79db max hole: 0x9d749f thanks! shuai

Hi : i load a lib is big about 26MB THANKS shuai

Hi Shuai, you may need to change DSP2_DATA_MEM in your memory map. Please refer "vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_UserGuide_MemoryMap.pdf" for details. Regards, Yordan

Ticket Name: TDA2SX: How to create Mcasp I2S driver on RTOS?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi, I follow TDA2 TRM Figure 24-126. McASP DIT- /TDM- Transmission Polling Method. And try to implement in CSL drv_stw_lld_mcasp_sinetone_app. My program stops at this stage after the second loop.

Can anyone explain the operation flow of the blocks on the flowchart?

Are there TI Audio experts who can answer?

Hi Jian: May you help to reply this E2E, it pended for > 2 weeks. BR Rio

any update?

Ticket Name: RTOS/TDA2: How to verify OV10635 raw data same as capture link setting.

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, We change video source of TIDL_OD use case from SD card to VIP(OV10635) port. And set VIP output parameter(CaptureLink) same as original VPE output parameter of TIDL_OD. We can get video display by HDMI but output video not any object be draw. First, we want to verify video raw data from memory. Could you please give some advice to me? Thanks for your support. Links chart as below

Hello TI TIDL OD lib is trained to work only with one pre-recorded clip. You might need to train the same to work with real camera capture and that is why you did not see any object be draw regards, Shiju

Hi Shiju, Thanks for your reply. Could you please advice us how to train with real camera capture? Have any document can study? Thanks.

Please refer the below for training CNN network with your dataset. github.com/.../caffe-jacinto

Thanks for Mr.Kumar advice. We will study first. Have a nice day :)

Ticket Name: RTOS/TDA2PXEVM: Video display and network transmission runtime error

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hi, I am developing with the fusion application board and SDI OV2775 camera module. My objective is to read in the video stream from the image sensor at 1080p 30 fps and simultaneously send it to the HDMI output for display and over Ethernet to be saved on my computer. Below is configuration file I have used to generate this usecase: I was running into the procId < SYSTEM_PROC_MAX error, but I was able to resolve that thanks to the previous related post. However, now I am stuck on a runtime error in which the video displayed is very dark i.e., overhead fluorescent lights appear as dim neon green strips. When I run the included 1 channel ISS usecase, the video looks normal. My bigger issue, however, is that when I run the network RX tool to save the incoming frames, then try to view the resulting YUV files, they show up as completely blank, unlike the dark images that are displayed on the monitor. Attached are the associated files for my usecase: chains_iss_Capture_NetworkTx.zip Help with either of these issues would be greatly appreciated. Thanks, Richard

Hi Richard, Please note that the capture output is in Bayer Raw format, so it might not be viewable, unless sensor has good exposure. Are you sure that adding network link is causing artifacts in the output? Can you disable network write (essentially do not connect) and see if it gives good output? Rgds, Brijesh

Hi Brijesh, I am aware that the IssCapture output is in Bayer Raw format, which is why I feed its output into the IssM2mIsp, which converts into YUV format, which can be displayed? Would I need to also add the IssM2mSimcop link to increase exposure? I am not saying that adding the network link is causing artifacts in the output, I am saying that the frames I save over the network while my usecase is running don't seem to contain viewable data. Attached is such a frame: 2318.test.zip The display output is the same when I disable the network write. Thanks, Richard

Hi Brijesh, After adding the AEWB link, the video feed looks fine now. However, now I am no longer able to save frames over the network at all, when I try to do so, the following connnection error appears: At first I thought I had neglected to enable the relevant output queue, but my app_util_iss.c settings looked fine: I know the RSZ_A and H3A queues are working because the video feed is displayed and the automatic exposure/white balance is applied. Would a data transmission rate greater than that supported by the connection cause the server connect failure? Currently both my PC and TDA2 board are on a 100 Mbps network, but streaming 1080p video at 30 fps would take up ~1 Gbps? I have tried adding in both MJPEG and H264 compression before transmission, but I get the same error. Attached are the files for my usecase: iss_capture_network_tx.zip Thanks, Richard

Richard, Yes, without AEWB, the output will not look good. Could you please check if NDK is enabled in your build? Please note that NDK and SD card both can not be enabled. Please check this. Rgds, Brijesh

Hi Brijesh, NDK was enabled in my build, and now I have disabled the FAT. However, the network error persists. Thanks, Richard

Hi Brijesh, My usecase is working now, I think my problem was a combination of missing some analagous code from the example usecases and having some unnecessary analagous code from the example usecases. Thanks, Richard

Ticket Name: TDA2: TDA4x release / MP schedule

Part Number: TDA2 Hi, Our customer plan to use TDA4x for the Automotive ADAS applicaiton. We want to know when it can release and mass production? thanks very much.

Hi Leo, Please get in touch with your TI representative for this detail. Thanks and Regards, Piyali

Ticket Name: TDA2PXEVM: Problems with the TIDL library import tool

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello, I am trying to use TIDL library on TDA2PX EVM to run DNNs on EVE and DSP cores. I am using TensorFlow as a framework. I am following the user guide with the title " TI Deep learning Library on TDAx " - November 2019. The user guide states that " TIDL supports slim based tensorflow models ". Does TIDL library supports only slim based TensorFlow models ? Does it mean that I can not import models trained in TensorFlow, not TensorFlow slim? I have tried to import MobileNet V2 from TensorFlow Keras applications using the TIDL library, but I get error mesages saying that "Pad Layer is not supported by TIDL and cannot be merged into any TIDL layer". Moreover, I need to know where I can find the file "optimize_for_inference.py". Thanks, Ahmed Anwar

Hi Ahmed, >> Does it mean that I can not import models trained in TensorFlow, not TensorFlow slim? Yes, TIDL on TDA2 can import only TensorFlow slim models. On TDA4 we support TensorFlow models also. >> but I get error mesages saying that "Pad Layer is not supported by TIDL and cannot be merged into any TIDL layer" This is because of Pad layer is not supported, refer to datasheet for all the supported layers >> I need to know where I can find the file "optimize_for_inference.py" This is available in "tensorflow/python/tools" folder Thanks, Praveen

Hello Praveen, Thank you for your reply. I have a question regarding the TensorFlow slim models. In the user guide, there is an example of a Keras/TensorFlow model which can be found here. This example uses Keras from TensorFlow, not TensorFlow slim, to build a simple CNN, which can be used as an input to the TIDL import tool. Does this mean that I can use Keras from TensorFlow, not TensorFlow slim, to build a CNN and use it as an input to the TIDL import tool ? I just need to understand this point better, as most of my development is already in Keras/TensorFlow, and the example that I mentioned also uses Keras/TensorFlow. However, based on your reply, "TIDL on TDA2 can import only TensorFlow slim models". Would you please illustrate how this example uses Keras/TensorFlow if only TensorFlow slim models are supported on TDA2 ? Thanks, Ahmed Anwar

Yes, We have limited layers support for Tesnsoflow in TDA2, where as most of the layers are supported with Caffe/Tensorflow slim models. Please refer to below comment in the user guide section 3.6.5. " We have developed/defined TIDL library layers based on the layer types Caffe framework. Most of our test cases (Layer level and network level) and demos are based caffe framework. With respect to Tensorflow, we have validated two pre-trained models from tensorflow github (Slim based Mobilenet V1 and Googlenet/inceptionetV1), this covers most of the CNN layers (Convolution, Max Pooling , Average pooling, Batch norm, Fully connected layer, softmax, Relu, Relu6, concate etc). " Thanks, Praveen

Ticket Name: Compiler/TDA2EVM5777: How can i check cd-gpios?

Part Number: TDA2EVM5777 Tool/software: TI C/C++ Compiler Hi, I'm customizing the dra7-evm.dts file to boot my custom board. In dra7-evm.dts file, the cd-gpios is set as <&gpio6 27 GPIO_ACTIVE_LOW> and the below is MMC interface part of board schematic. I want to know how can i assure that SDCD signal is hardwired to gpio6 in this schematic. Thanks and Regards, Yoo

Hi Yoo, MMC1_SDCD pinmux is configured to GPIO, code snippet from u-boot below {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)},  /* mmc1_sdcd.gpio6_27 */ Regards, Vishal

Ticket Name: TDA2SG: Consult about Type Selection and Application.

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2P-ACD Hi, I'm using TDA2SG now. Because of the problem of computing power, two DSPs and four EVEs are needed. But I saw only TDA2S series can satisfy these two conditions found on the official website. But there is no CSI input. Do you have any other suitable suggestions? In addition, the computing power of TDA2P-ACD is how much, our application need to achieve 50 G Macs. Or have any suggestion? thank.

Hi Wu Yisyuan The TDA2px may be a good option for you: 2x C6x DSP @ 1000 GHz = 2*32 GMACS = 64 GMACS 2xEVE @900 MHz = 2*16*900 MMACS = 28.8 GMACS 2xA15 @1800 MHz = 2* 8 * 1500 MMACS = 24 GMACS http://www.ti.com/lit/ds/symlink/tda2p-acd.pdf You can refer to https://e2e.ti.com/support/processors/f/791/t/615108 for the gflops calculation. Thanks and Regards, Piyali

Ticket Name: Compiler/TDA2: Fail to linking openCV file (objdetect)

Part Number: TDA2 Tool/software: TI C/C++ Compiler Dear TI So in another words if i need to use objdetect then i have to use it in linux. am i correct? In future will TI look into this area to enable bios to use objdetect?

Hi, TI does not support object detection using OPENCV and there is no such plan in future to add support for it. If you want to use object detection then you can use BIOS usecases vip_single_cam_lane_detection vip_single_cam_object_detection2 Regards, Anuj

Dear Anuj Just to verify then if we using linux instead we should be able to use objdetect.hpp in openCV

Hi, In VSDK we have a prebuilt OPENCV library. We do not support building of OPENCV library. regards, Anuj

Dear Anuj I am working in same team as Winson, I got 3 questions: 1. Because BIOS did't support object detection, so we want to build SDK in Linux host, i.e. using OpenCV in Linux version, Can I confirm if the openCV in TI Linux build will support object detection? 2. As suggested, to use openCV in TI linux build, we follow the VisionSDK_UserGuide_opencx.pdf, but this doc tell us that we need to rebuild the OpenCV from source code and also need to rebuild cmem, Do we really need to rebuild these from source code? 3. In my Linux host, I set the build config as: MAKECONFIG=tda2xx_evm_linux_opencx, The error is that it can not find the clocl cmd in the below path: home/hewei/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/../ti_components/os_tools/linux/targetfs/usr/share/ti/opencl/bin/x86/clocl: Command not found Should I install the "clocl" cmd in that path and build? Please advise Thanks and best regards He Wei

Hi, TI does not support object detection using OPENCV. Bios suppport object detection using some algorithm running on bios. Please use the above suggested usecases. Regards, Anuj

Dear Anuj So we won't get any additional openCV features support if switching from TI Bios build to TI Linux build, am I right? Based on the test report from ti_components\open_compute\opencv\opencv-3.1.0\docs: there is one sheet "objdetect" in vayu_arm_linux_opencv_test_report.xlsx but this sheet is not shown in vayu_arm_bios_opencv_test_report.xlsx. Actually this is the reason we thought objection detection is supported in Linux build . So this is not the case? Thanks and best regards He Wei

Yes, you are right. If its been supported in VSDk then a supported usecase will be there for linux. Regards, Anuj

Ticket Name: TDA2: how to recover from QSPI busy state

Part Number: TDA2 Hello, In case of TDA2x QSPI is stalling due to busy status, how to return to non-busy staus by QSPI module configuration? I tried CM_L4PER2_QSPI_CLKCTRL.MODULEMODE = 0 (disable) then CM_L4PER2_QSPI_CLKCTRL.MODULEMODE = 1, but sometimes QSPI CS looks still in active state after this operation and still stalling... If you provide the right QSPI module reset procedure it is helpful. Regards, Takeo

Hello Takeo-san, The modulemode alone would not reset the internal module state. Is this condition (stalling busy) happening always (after every SPI transaction attempt) or randomly? Regards, Stan

Also, BUSY bit is auto-clearing by hardware. Software reset of QSPI is not needed nor possible. BUSY sticked to 1 means issue with the SPI clock. One example could be missing or incorrect PCB routing of qspi1_rtclk. Kindly check the TRM chapter Quad Serial Peripheral Interface

Ticket Name: TDA2E: Git clone ipumm error for TDA2

Part Number: TDA2E Hi to whom it may conern, I'm trying to clone ipumm from git.ti.com but got the following error fatal: unable to connect to git.ti.com: git.ti.com[0: 198.47.28.207]: errno=Connecton refused I also tried to clone the linux kernel and got the same error report. Any solution for it? Regards, Ming

Hi Ming, do you work behind a proxy? Can you check this guide: Regards, Yordan

Ticket Name: TDA2: SSD based TIDL OD use case in Vision SDK with pre-trained model

Part Number: TDA2 Hi, In this thread https://e2e.ti.com/support/arm/automotive_processors/f/1021/p/689617/2542976?tisearch=e2e-sitesearch#pi320098=2 It said (original use case had only 4 classes, but this new model as 21 classes) so it need to change like below File : vision_sdk\apps\src\rtos\alg_plugins\objectdetection\objectDrawLink_algPlugin.c Line : tempoutPutList->objDesc[tempoutPutList->numObjects].objType = (label - 1)%3; How to decide which class you want to detect in TDA2x ? The original have 21 classes , TDA2x only can detect 4 classes If I don't want to detect car 、pedestrian、traffic sign How can I do to choose 4 classes in the other 17 classes ? Best Regards, Andy Dong

Hi Andy Dong, It is not that TIDL will not detect 21 classes, TIDL usecase can detect 21 classes but can only display first four classes. So, you can train a model to have your interested 4 classes or have them as first 4 classes. Thanks, Praveen

Hi, Praveen 1. Is there a way to show another 4 classes not just the first 4 classes ? 2. Line : tempoutPutList->objDesc[tempoutPutList->numObjects].objType = (label - 1)%3; the output of this line will be 0~3 ( 0~2 ? ) Is the number match classes with 0~3 or just mean it can display 4 classes ? If output be 4~7 , is it possible to display another 4 classes not the first 4 classes ? 3. How can I do to display more than 4 classes on TIDL usecase ? Thanks! Andy Dong

Hi, Is there any updates ? Thanks Andy Dong

Hi Andy, To answer your questions, let me start with explain what below line of code will do, >> Line : tempoutPutList->objDesc[tempoutPutList->numObjects].objType = (label - 1)%3; This modulo 3 is because, currently VSDK supports only four colour codes for display. This means it can display all the 21 objects but can use only 4 colours as below, Class 0, 4 , 8... uses first colour Class 1, 5, 9... uses second colour Class 2, 6, 10..uses third colour Class 3, 7, 11... uses the fourth colour coding. Hope this explanation answer all your questions. Thanks, Praveen

Ticket Name: TDA2: Cortex-A15 cores secure state after exiting from ROM Code

Part Number: TDA2 Hi, I have noticed that ROM Code provides some Secure Monitor Call interfaces to user. Why so? Is it because A15 cores enter non-secure state after exiting from ROM code?

Hi Yang, I think they are the only way to accomplish the respective functions on a non-secure, aka general-purpose (GP) device (SoC). I guess they are not needed on HS devices. I'm not an expert, just can recall some older threads in the forum. The TRM also states the following: The ROM code provides different services that can be called on GP devices for L1 and L2-cache maintenance, Enter in Low Power, etc. ... The following code example shows how the monitor ROM code functions can be accessed by an application running in public mode: .... Regards, Stan

Ticket Name: Linux/TDA2: CMEM Error: init: major version mismatch between interface and driver.

Part Number: TDA2 Tool/software: Linux Hi, When i start to run opencv sample, i got following error. CMEM Error: init: major version mismatch between interface and driver. CMEM Error: needs driver version 0x4130001, got 0x4120000 TIOCL FATAL: The cmemk kernel module is not installed. Consult the OpenCL UserGuide at http://software-dl.ti.com/mctools/esd/docs/opencl/index.html i follow the step in VisionSDK_UserGuide_opencx.pdf How can i solve this problem? Thanks, Chen-Wei

Hi Chen-Wei, Did you followed chapter "2.4.2.1.1 Clone kernel" from VisionSDK_Linux_UserGuide.pdf to clone and checkout the correct version of cmem? (from other E2E threads with the same error it looks that this might happen because the userspace library that uses cmem is build against different version of cmem.ko module) Regards, Yordan

Ticket Name: Compiler/TDA2EVM5777: Display true-color on TDA2

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi: I had an requirement for displaying true-color with transparent color(RGBA8888) in TDA2's board on Linux operation system, I tried two way to accomplish this requirement. (1) I created an new usecase and specified the link to "GrpxSrc -> Display_Grpx". I successfully run the usecase with those data format: pMyObj->GrpxSrcPrm.grpxBufInfo.dataFormat = SYSTEM_DF_BGRA16_4444;
//or
pMyObj->GrpxSrcPrm.grpxBufInfo.dataFormat = SYSTEM_DF_BGR16_565; It worked on displaying transparent color in SYSTEM_DF_BGRA16_4444. (2) I created another new usecase and specified the link to "NullSource (A15) -> Display". I setup those argument before the NullSource start: NullSrcLink_CreateParams *pNullSrcPrm = &pObj->ucObj.NullSourcePrm;
System_LinkChInfo *pChInfo = &pNullSrcPrm->outQueInfo.chInfo[0];
pChInfo->flags = System_Link_Ch_Info_Set_Flag_Data_Format(pChInfo->flags,
			 SYSTEM_DF_YUV420SP_UV
/*SYSTEM_DF_YUV422SP_UV*/); It worked on displaying specific image in SYSTEM_DF_YUV_420SP_UV. But I setup the pChInfo->flags to other format(ex: SYSTEM_DF_YUV422SP_UV), then the program will ASSERT on creating nullsource. From above two testing and I find the different data format(SYSTEM_DF_RGBA32_8888) in "system_const.h", I wanna ask: (1) Is there any way to display true-color with transparent color in Grpx(Grpx looks like supporting Half-color(RGB444))? (2) Is there any way to sending RGBA8888 data format to displaying true-color with transparent in "NullSource -> Display"? (3) Is TDA2's hardware support true-color with transparent displaying mode? wxchen

Hi, NullSource is a link which reads from a file. So there is no such format of video data file which it wont be able to read. We just have not enabled all dataformat. If you want to read any specific data format then you have to enable it in the link. Please check NullSrcLink_fillData( ) function and add your data format support. in below file links_fw/src/hlos/links_a15/nullSrc/nullSrcLink_tsk.c Similarly you can add supoort for gspx link also for your data format. And yes TDA2 hardware support true-color with transparent displaying mode Regards, Anuj

Ticket Name: TDA2: EDA2x EVM CPU Board

Part Number: TDA2 Other Parts Discussed in Thread: X5777BXGABC, Hi, I was looking into the evaluation Board TDA2x EVM CPU Board. (Literature Number: SPRUI51) The Processor in the EVM CPU Board is X5777BXGABC ( Jacinto 6) which is not TDA2x (TDA2SG or TDA2P) Can I use the Schematics and Layout reference on This EVM as Reference Design for my Hardware PCB Schematics design? Are Both Pin To Pin, drive strength, thermal Compatiable?

Hi Lee, You are free to borrow good ideas from EVMs, however keep in mind that EVMs are designed to evaluate as much of SoC functions as possible. They are full of discrete logic and muxing which normally are not needed in a field design. X5777 is a pre-production, test device, therefore drive strength and thermal are not compatible with production devices. I think they are pin-to-pin compatible, but kindly check your TDA2's silicon revision pins in the respective datasheet. Or, use an EVM schematic with your silicon revision SoC. Regards, Stan

Hi Stan, Just to verify , X5777 is a pre-production for TDA2? Presently, the system and software guys use the existing EVM CPU Board ( with X5777BXGABC) to test all the necessary features. The EVM is connected to 4 cameras. 1. If my HW is build with TDA2AG (I re- use the sDDR3 and VIP inputs as EVM ) will the system speed performance affected ? 2. The software can just port in to my TDA2AG Board without modification?

Hi, Correct, X5777 timings, thermal, and performance are not all characterized and may not meet those of TDA2. This is an early silicon for software test. 1. Speed performance - as per TDA2AG datasheet. 2. I think yes. Provided that same TDA2 pins are used on the new board. Otherwise pinmux will need to be modified as required. Regards, Stan

Ticket Name: CCS/TDA2: ddr l2 l1 Speed comparison

Part Number: TDA2 Tool/software: Code Composer Studio from spna165.pdf L1 cache 600 MHz L2 cache 300 MHz External memory~100 MHZ memory so i test this use the same function ,change site of the in put buffer and comparison use cycles this is the cmd -stack 0x4000 -heap 0x2000000 MEMORY { L1P_SRAM : origin = 0x00E00000, len = 0x8000 L1D_SRAM : origin = 0x00F00000, len = 0x8000 /* 16 KB SRAM */ // L1D_CACHE : origin = 0x00F04000, len = 0x4000 /* 16 KB cache */ // L1D_CACHE : origin = 0x00F00000, len = 0x8000 /* 16 KB cache */ L2_SRAM : origin = 0x00800000, len = 0x48000 /* SARAM in L2, = 256 + 32 - 128 = 160 KB*/ // L2_CACHE : origin = 0x00828000, len = 0x20000 /* Cache for L2, which is configured as 128 KB*/ DSP2_L2_SRAM : origin = 0x40800000, len = 0x48000 SL2_SRAM : origin = 0x5B000000, len = 0x40000 EXT_MEM_CACHE : origin = 0x80000000, len = 0x06000000 /* DSP Used cachable area */ EXT_MEM_heap : origin = 0x86000000, len = 0x02000000 /* DSP Used cachable area */ } SECTIONS { vectors :> EXT_MEM_CACHE .cio :> EXT_MEM_CACHE .bss :> EXT_MEM_CACHE ////usually reserves space for uninitialized variables .text :> EXT_MEM_CACHE //////contains executable code .cinit :> EXT_MEM_CACHE .const :> EXT_MEM_CACHE .far :> EXT_MEM_CACHE .fardata :> EXT_MEM_CACHE /////usually contains initialized data .neardata :> EXT_MEM_CACHE ///////usually contains initialized data .rodata :> EXT_MEM_CACHE .sysmem :> EXT_MEM_CACHE .switch :> EXT_MEM_CACHE .L2SramSect :> L2_SRAM .stack :> L2_SRAM .heap :> EXT_MEM_heap } input = (int *)0x00F00000; for L1 1300000 input = (int *)0x00800000; for L2 1300000 input = (int *)0x80000000; for DDR 12000000 result is L1 and L2 same DDR much more so problem is why L1 not faster than L2?

The cycles depend very much on what we are trying to do in the function. If you have to measure acutal cycles then you need to write a specific test case. For measuring L1D performance, 1. Partition L1D as SRAM and cache. 2. Declare an array of lengh (say 1KB) and pipe it to L1DSRAM using #pragma DATA_SECTION 3. Verify in .map file that array is piped to L1DSRAM section. 4. Write a function which reads the array in a loop and accumulate contents. Send the accumulated value as the return value of the funciton. 5. Profile the function. For measuring L2 performance, 1. Partition L1D and L2 as SRAM and cache. 2. Declare an array of lengh (say 1KB) and pipe it to L2SRAM using #pragma DATA_SECTION 3. Verify in .map file that array is piped to L2SRAM section. 4. Write a function which reads the array in a loop and accumulate contents. Send the accumulated value as the return value of the funciton. 5. Profile the function. For measuring DDR performance, 1. Partition L1D and L2 as SRAM and cahe. 2. Cache DDR space by setting appropriate MAR bits 3. Declare an array of lengh (say 1KB) and pipe it to L2SRAM using #pragma DATA_SECTION 4. Verify in .map file that array is piped to L2SRAM section. 5. Write a function which reads the array in a loop and accumulate contents. Send the accumulated value as the return value of the funciton. 6. Profile the function. Hope this shows the difference bettwen L1D, L2 and DDR performance. The performance can vary depending on L1D, L2 cache sizes and also if DDR cached or not.

Have you confirmed that you can properly read/write proper data in L1 and L2? The reason I ask is because access to these is dependent on the configuration. For example, at reset, the L1D is configured as full cache. The L2SRAM is configured as full RAM. So unless you change the configuration, L1D is not accessible as memory mapped RAM. If you are seeing same for L1D and L2, it might be because the L1D access is not actually reading/writing to the L1D RAM. Without seeing your code, I can only ask the question. I would also expect the L1D access to be faster than the L2 access.

Ticket Name: Linux/TDA3XEVM: Vision SDK for TDA3MA ADAS SoCs - Linux

Part Number: TDA3XEVM Other Parts Discussed in Thread: TDA3MA, TDA2 Tool/software: Linux Hi, Please help me to find guidelines to setup Yocto configuration files or Yocto set up for vision SDK for TDA3MA. Is SDK_VISION_03_06_00_00 is latest SDK for this platform Thanks and Regards Vishal Singh

Hi Vishal, Linux support is not available for TDA3 platform. On RTOS side we don't support Yocto builds. You can download latest SDK from software-dl.ti.com/.../index_FDS.html Regards, Rishabh

Hi, Sorry but I am confused when by this text "Linux not supported for TDA3" As On product page under software tab I observed that Linux Filesystem binaries are attached for this platform. and docs attached also mentions about Linux development and use cases on on this board using Linux. Please refer:- http://software-dl.ti.com/processor-sdk-vision/esd/TDAx/vision-sdk/latest/index_FDS.html Let me know if I am referring something wrong. it will be really nice if you can elaborate "not support" do you mean Yocto framework not supported for this. or there is no Linux SDK support for this platform. Thanks and Regards Vishal Singh

Hi, In addition to my last reply does in my last link SDK attached is meant for TDA2 not for TDA3. (please confirm) In this case I am sorry because same link is pointed from TDA3 product page also. Ok if this is case then can you let me know when there is possibility for TDA3 SDK and Yocto support for that. Thanks and Regards Vishal Singh

Vishal, Linux installer for Vision SDK RTOS is available. Linux OS and Yocto support is not available. Hope this helps. Regards, Rishabh

Hi Rishabh, Thanks I got the point. May i know what is probable date when Yocto build and Linux SDk for this platform will be available. Is TDA2 family is supported with Linux OS SDK. Thanks and Regards Vishal Singh

Vishal, Vision SDK Linux is already available today for TDA2 platform. We are not planning to add Linux support for TDA3. Regards, Rishabh

Hi Rishabh, Thanks for your quick reply It really helped to clarify confusion . Thanks and Regards Vishal Singh

Ticket Name: Linux/TDA2: null_src_decode_display test problem

Part Number: TDA2 Tool/software: Linux I tried to test null src test case for H.264, but it failed and showed error. 1: Single Camera Usecases 5: NullSrc + Decode + Display (Only 1920x1080 H264/MJPEG Video Input Bit-Stream Supported)\ Enter '1' for H.264 1 ASSERT (nullSrcLink_tsk.c|NullSrcLink_create|1083) The print log showed the data file is 1920x1080_00.h264 and index file is 1920x1080_00.hdr. [HOST] [HOST ] FILEREAD NOT DISABLE [HOST] [HOST ] Data file:/home/1920x1080_00.h264 [HOST] [HOST ] Index file:/home/1920x1080_00.hdr Could you please let me know where to get these test files? I had test files 1280x720, or maybe you can let me know how to change the file path? root@dra7xx-evm:/home# ls -al -rw-rw-rw- 1 1000 pulse 615343 Nov 18 2017 1280x720_00.h264 -rw-rw-rw- 1 1000 pulse 200 Nov 18 2017 1280x720_00.hdr Any help will be appreciated. Thank you. Regards, Ellen Shiu

Hi, Please check here where to get .h264 stream and how to generate corresponding index file (.hdr): e2e.ti.com/.../2551574 e2e.ti.com/.../2551636 Regards, Yordan

Ticket Name: TDA2: O9039A387IZWSRQ1 Design Specifications

Part Number: TDA2 Other Parts Discussed in Thread: TPS659039-Q1 Are you able to provide the design specifications of O9039A387IZWSRQ1, similar to what have been stated in datasheet TPS659039-Q1 as below? Thanks.

Hello CTY, The latest settings of the TPS659039-Q1 are listed in this user's guide: www.ti.com/.../swcu175 OTP 0x87 is the same as OTP 0x44 except SMPS123 (MPU) and SMPS7 (CORE) have default voltages of 1.15V. Regards, Karl

I guess you meant SMPS123 and SMPS7 voltages are changed to 1.15V, right? Thank you for the user guide, it clears my doubt.

Hi, Yes, it should be SMPS123 and SMPS7. Thanks, Nastasha

Ticket Name: TDA2E: how I find the link ID related source code？

Part Number: TDA2E (1)For example,IF I want to find the source code if ID Alg_RadarProcess_objectDetectLinkID,where I can find it. (2) I design anew set of radar parameter,how to make sure that the DSP,EVE will finish theri job in a certain time? Make the DSP a sinlge peoject test it?

Hi, (1)For example,IF I want to find the source code if ID Alg_RadarProcess_objectDetectLinkID, where I can find it. >>>> First you need to find out in which use-case this algorithm(Alg_RadarProcess_objectDetect) is used. This algorithm used in "vision_sdk/apps/src/rtos/radar/src/usecases/cascade_radar_object_detect" usecase. Here 5 Algorithm link is defined in the use-case such as Alg_RadarProcess_fft1 Alg_RadarProcess_fft2 Alg_RadarProcess_fft3 Alg_RadarProcess_fft4 Alg_RadarProcess_objectDetect For every algorithm link, the create parameter structure member is created in the use-case as below typedef struct { chains_cascadeRadarOdObj ucObj; ChainsCommon_Ar12xxConfigOut ar12xxCfg; Chains_Ctrl *chainsCfg; /* Algorithm */ AlgorithmFxn_RadarFftCreateParams radarFftParams1; AlgorithmFxn_RadarFftCreateParams radarFftParams2; AlgorithmFxn_RadarFftCreateParams radarFftParams3; AlgorithmFxn_RadarFftCreateParams radarFftParams4; AlgorithmFxn_RadarDspProcessCreateParams radarDspOdParams; } Chains_cascadeRadarOdAppObj; The next step is you have grep "AlgorithmFxn_RadarDspProcessCreateParams" in the vision SDK, then you can see where it's being used. vision_sdk\apps\src\rtos\radar\src\alg_plugins\alg_fxns\radardspprocess - This is the source code directory for the link "Alg_RadarProcess_objectDetect" 2)I design anew set of radar parameter,how to make sure that the DSP,EVE will finish theri job in a certain time? Make the DSP a sinlge peoject test it? >>> I will check with our teammates & get back

For #2, yes, you will have to run it to get the benchmark numbers for DSP algorithm.

Hi thank U （1）I didn't find the ision_sdk\apps\src\rtos\radar\src\alg_plugins\alg_fxns\radardspprocess，there is no file named radardspprocess,is it radardspcascademimo? （2）In your example, my code is /* Algorithm */ AlgorithmFxn_RadarFftCreateParams radarFftParams1; AlgorithmFxn_RadarFftCreateParams radarFftParams2; AlgorithmFxn_RadarFftCreateParams radarFftParams3; AlgorithmFxn_RadarFftCreateParams radarFftParams4; AlgorithmFxn_RadarDsp CascadeMimoCreateParams radarDspOdParams; is my software wrong?

Yup Thanks Gaviraju

hi ,please help me sovled my problem? I can't find the file you refered,and my source code is different from your

HI thanks if I need test the DSP algorithm with static test data,what should I do?use a CCS project or use a link?

（1）I didn't find the ision_sdk\apps\src\rtos\radar\src\alg_plugins\alg_fxns\radardspprocess，there is no file named radardspprocess,is it radardspcascademimo? >>>> radardspprocess was used in the older SDK version & for your SDK version "radardspcascademimo" is the source code directory of the link （2）In your example, my code is /* Algorithm */ AlgorithmFxn_RadarFftCreateParams radarFftParams1; AlgorithmFxn_RadarFftCreateParams radarFftParams2; AlgorithmFxn_RadarFftCreateParams radarFftParams3; AlgorithmFxn_RadarFftCreateParams radarFftParams4; AlgorithmFxn_RadarDspCascadeMimoCreateParams radarDspOdParams; is my software wrong? >>>> This is correct & whatever I mentioned in the above post that is used in the older SDK version Thanks Gaviraju

Ticket Name: RTOS/TDA2: IPC communication between A15 & M4 issue.

Part Number: TDA2 Tool/software: TI-RTOS Hello all, We are working on VSDK 3.04 , J6 EVK platform We are trying to implement a Heart beat mechanism, where in if Linux on A15 crashes, IPU should get notified of it and should run critical app on IPU based RTOS. To do this, we have refered HeartBeat server app from RVC - VSDK 2.12 - Utils_common directory, ported it to VSDK 3.04 and called the task from IPU_primary_core_init() in ipu_primary.c. We create a task to ping between A15 and IPU through IPC mechanism as Ideally, the heartbeat should run as a separate task from the main usecase. Issue we are facing is, when the heartbeat server starts, the use case is not getting scheduled, as Heartbeat task is getting blocked in MessageQ_get(Module.slaveQue, (MessageQ_Msg *)&msg, MessageQ_FOREVER); Please help. Thanks Naren K

Hi Naren, MessageQ_get will block only the task in which it is running, and not other tasks. Do you have your heartbeat task separate from your use case task? Also, is your usecase doing any communication between A15 and IPU outside of the MessageQ (i.e., are there any links between A15 and IPU in your usecase)? If so, these IPC methods can unfortunately not co-exist. Either only MessageQ can do A15<->IPU communication or VSDK IPC can. This is because they both use the rpmsg-proto driver, which will allow only one registered transport per remote core. Thanks, Angela

Hi Angela, Thanks for your support. That works for me. Regards, Naren k

Ticket Name: TDA2SX: Does TDA2 support pSLC for NAND?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi Expert Does TDA2 support pSLC for NAND? Thanks Daniel

Daniel, Which interface? We do support pSLC NAND for MMC modules. Best Regards, Shiou Mei

Hi Shiou Mei Could I use this? Automotive PN：FEMDMW008G-88A37 -40°C to +85°C (pSLC) Thanks Daniel

Daniel, I have received confirmation we do not support ROM code boot from pSLC NAND flash memories. Best Regards, Shiou Mei

Ticket Name: TDA2EVM5777: TDA2 with 12-bits sensor input & TIDL 12-bits input

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello, I've a question regarding using an image sensors that can output 12 bits image buffer. My questions are: (1.) Is TDA2 capable of reading buffer from a sensor that can outputs single channel 12 bits images? (2.) According to a coworker of mine, in default, TIDL takes unsigned char buffer as input. Can TIDL use other data type such as float? Thanks a lot, Wei Chih

No, TIDL can't use other data type such as float. The input should be 8-bit unsigned or signed data. Thanks, Praveen

Understood. Can TDA2 read data from a sensor that outputs 12bits single channel image? Thanks, Wei Chih

Hi Wei, 8 , 16 or 24 bit port available in VIP. so 12bit is not supported. Thanks RamPrasad

Hi Wei, 12 bit data can be supported with VIP. I got it confirmed from the expert. Thanks RamPrasad

Ticket Name: TDA2: Schematic Review

Part Number: TDA2 Does TI help to review customer's schematic?

Hi Lim, Kindly get in touch with your TI contact regarding reviewing schematics. Thanks and Regards, Piyali

Ticket Name: RTOS/TDA2EVM5777: Please tell me the reason why bboxPtr in ObjectDrawLink is calculated using this way.

Part Number: TDA2EVM5777 Tool/software: TI-RTOS Hi, I'm doing analyze the src code of Object Draw link to know what is the buffer format of result after TIOP. In objectDrawLink_algPlugin.c file, I couldn't unserstand `bboxPtr = (float *)((char *)metaDataAddr + (bufferOffset*4)+4);` (Line 1484). Could you please tell me why bboxPtr is obtained as that way? Best Regards, Yoo

Hi, Its done in this way as TIDL algorithm does some padding and the actual data starts from that address. Regards, Anuj

Hi, Anuj. If so, is there a way to know what data is in the (bufferOffset * 4) +4 space at the beginning of the metadata, including padding? I think it's too big to have only padding data in that space. Thank you & Regards, Yoo

Hi, It should be all 0 except the 1st 4 bytes where we set offset. This padding comes from TIDL algorithm only so its been done like this in SDK. Regards, Anuj

Ticket Name: TDA2: How to record VIP output data

Part Number: TDA2 Dear TI, How can i dump the data output from VIP instance. The file format i expected is YUV422 with 12bit lenght per color component. Questions: 1. Which link can be used to add the dump code, capture link callback or null link callback? 2. What APIs can help me to achieve this func? Are there any constrain of these APIs in VIP output format. Regards, Liu Gan

Hi, You have to create a usecase capture->null. Capture link will capture the vip data and null will dump the same. Regards, Anuj

Hi Anuj, Does capture link can be used to dump the vip data? How should i conifgure the DMA params for dump YUV 12 bit format file to SD card? Can you kindly providing me the example code? Regards, Liu Gan

Hi Anuj, Other questions: 1. If null link is used, what params should be used at create time? 2. How should i do to make null link dump only one frame at any time during usecase running? Regards, Liu Gan

Hi, If you want to dump any specific frame at runtime then its not supported by null link. You can use CCS to dump any specific frame from capture link. Please check any vip single cam usecase to know the create param of capture link. Regards, Anuj

Hi Anuj, Thanks for your support. Regards, Liu Gan

Ticket Name: Linux/TDA2: thansfer data from a15 to C66

Part Number: TDA2 Tool/software: Linux I am using TDA2 evm SDK_VISION_03_04_00_00 , i run a cnn in sample_app\src\rtos\alg_plugins\framecopy\frameCopyAlgoLocalDma.c my cnn have a big model 15MB about i have to read it by a15 and send buf to C66 , i read the model file in vision_sdk\sample_app\src\hlos\usecases\nullSrc_display\chains_nullSrcDisplay.c and send the address of model buffer to c66. in frameCopyAlgoLocalDma.c\Alg_FrameCopyCreate i get the address of model buffer . in frameCopyAlgoLocalDma.c\Alg_FrameCopyProcess Everything went smoothly. but i have a problem at last. when i run the program ， some times the out put of the CNN is always right ,some times front 3-5 frames is wrong but little difference, some times front 300-500 frames is wrong but little differenc So it's uncertain how many frames the results are incorrect, sometimes more, sometimes less, but after running 500 frames, they're basically correct. Later, I found that when the CNN output was incorrect, it was because the obtained model was partially incorrect. So the results are incorrect, but the gap is not big. So I think it's risky to get the CNN model in this way. It takes a while for C66 to get the correct CNN model. What causes this problem? Is there a good way to solve it? BESTWISHES Shuai!

Hi, Is the data is getting corrupted from a15 to c66. I hope you are allocating that much big memory and not modifying that data anywhere. Are you allocating from shared memory. I hope the cache operation are done properly. Regards, Anuj

Hi, Any update on this issue. Regards, Anuj

Ticket Name: TDA2EVM5777: Vision SDK usecase code tracing

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello, I'm new to the vision SDK,and now i use the version 3_01. I built the usecase and see the demo on my TDA2. Then I try to understand the usecase by tracing the source code of it inside the usecase folder. I trace to the algPlugin.c file and see the process function as below. \PROCESSOR_SDK_VISION_03_01_00_00\vision_sdk\apps\src\rtos\alg_plugins\tidl\tidlLink_algPlugin and then i try to find the algorithm but finally i find this: \PROCESSOR_SDK_VISION_03_01_00_00\ti_components\algorithms\REL.TIDL.00.08.00.00\common\ivision.h It seems like most of the algorithm of the usecase link to here. Where is the algorithm?Is it available?is it packed to another format? and is my question related to the key word - Xdais ? I have already read some documents inside the Vision SDK. The doc i read only mention that we need to build our own algorithm link and plugin function,but i don't kown what should i do clearly. If i want to build my own algorithm,is there any doc or example ? If anyone know the answer,please share with me. Thank you!

Hi Jimmy, Algorithms source is not released in Vision SDK. They are available in the library form. Please contact your local TI FAE to help you. Rgds, Brijesh

Hello Brijesh, thank you for your answer. i want to know where is the library file ? is it inside the algorithm of the TIDL?(\PROCESSOR_SDK_VISION_03_01_00_00\ti_components\algorithms\REL.TIDL.00.08.00.00\modules\ti_dl\lib\eve\debug\) Can you give me more information about how to connect our algorithm with the process as above? and what is the xdais?is it necessary? thank you! Regards, Jimmy Lai

HiJimmy, In this case, i think you could add your own algorithm link and then use it in the usecase. These algorithms are based on the xdais framework, so if you just replace function, it may not work. Rgds, Brijesh

Hi Brijesh, so i can directly code my algorithm inside a algorithm link plugin.c file without xdais,right? Regards, Jimmy Lai

Hi Jimmy, Ideally, it is preferable to create your own Alg Plugin link and use it. But for the time being, you could code your algo in one of the existing plugin link, will not require xdais. Rgds, Brijesh

Ticket Name: TDA2X-How to boot from SSD (Solid State Drive) after TDA2 is successfully compiled to generate Linux system

Other Parts Discussed in Thread: TDA2 Hi Team, The customer successfully compiled the linux system according to PROCESSOR_SDK_VISION_03_08_00_00_setuplinux.bin. Successfully boot from SD card. The mmwcas_dsp_evm development board comes with a 512GB SSD. He wants to start the linux system from the SSD, is there any relevant guidance document for operation? Best Regards, Annie Liu

Hi Annie, We do not have support for booting linux from SSD on TDA2. That is not supported on our SDK. Best Regards, Keerthy

Hi Keerthy, Customer has follow-up questions that need your help. Except booting from the SD card, is it able to boot from the SPI FLASH? If it supports SPI FLASH startup, how should it operate? Best regards, Annie

Hi Annie, https://e2e.ti.com/support/processors/f/791/p/962457/3558003#3558003 As per the above thread only SD boot is supported on 3.8 VSDK. Best Regards, Keerthy

Ticket Name: RTOS/TDA2EVM5777: Does detection output layer in TIDL Network apply NMS?

Part Number: TDA2EVM5777 Tool/software: TI-RTOS Hi, I got a one question about detection output layer in TIDL Network (JDetNet). In deploy.prototxt file, there is nms_param and keep_top_k in detection_output_param section. Does it means detection output layer apply NMS and return the output buffer which is consists of top 20 detected objects? Besides, could you let me know what is the meaning of keep_top_k? (top_k objects in order of high confidence? or just detected order) Thanks & Regards, Yoo.

Hi Yoo, 1. Detection output layer apply NMS on the "top_k" elements per class in the sorted list based on the scores. 2. "keep_top_k" are final output of top 20 objects in order of high confidence across all the classes. Thanks, Praveen

Ticket Name: Compiler/TDA2EVM5777: run QT application error in Linux System on TDA2-evm

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi: I compiled the QT library(5.13) with opengl es2 which is provided from ti's website(http://software-dl.ti.com/processor-sdk-vision/esd/TDAx/vision-sdk/latest/index_FDS.html) in rootfs image. Then, I ported the QT library on TDA2-evm board, and created an '/dev/fb0' symbol link from '/dev/vdrm-controller-0', but I got errors when running the QT application with GUI(examples/gui/rasterwindow) on board. PVR:(Error): WSEGL_InitialiseDisplay: Failed to create output [0, ]
Could not initialize egl display So, I have some questions about QT and OpenGL library: (1) Does TI not support the QT library on TDA2-evm board? (2) Does TI not support the OpenGL library on TDA2-evm board? Please help me solve this problem, thank you. Wxchen

Hi Wxchen, TI has not tested QT applications with vdrm. You have mentioned /dev/fb0, fbdev is no more supported and is replaced by drm. Please first check if you can run weston-simple-egl type of applications. Refer this link for the FAQ. http://processors.wiki.ti.com/index.php/Virtual_DRM_:_An_User_Guide_for_Developing_Usecases#FAQs Thanks RamPrasad

Hi RamPrasad: After I tried the weston-simple-egl sample program, it worked perfectly by those instructions: 1. Run the vision_sdk_load.sh from /opt/vision_sdk 2. Run the apps.out from /opt/vision_sdk 3. Choose 'single camera usecase', and select 'DispDistSrc(weston) usecase'. 4. After run the usecase, the HDMI will output an X-desktop like environment. 5. Edit powervr.ini file from /etc, and add two line at the end of file. [weston-simple-egl]
 6. Run weston-simgle-egl, the program will rotate an triangle on the X-desktop like environment. Unfortunately, I repeated the 5-6 step to run QT sample application, and I got similar error on the terminal( in desktop environment ). PVR:(Error): WSEGL_InitialiseDisplay: Failed to create DBM device: No such device [0, ]
Could not initialize egl display Is any possible to run the QT application in the TDA2 borad? Thanks Wxchen

Hi Wxchen, Did you modify your /etc/powervr.ini with this change? [qtApp-name]

Hi RamPrasad: Yes, I did modify the file with those changes: [rasterwindow]
DbmDriverName=vdrm But it not worked for me. Wxchen

Hi WxChen, What is the vision-sdk version used here? Can you check the commit-id of omap5-sgx-ddk-um-linux? If it is 32ad0237d69eb190d5b702a0bb4fac060e4995f2 as mentioned in ti_components/os_tools/linux/kernel/linux-kernel-addon/fs-patches/yocto/meta-glsdk/0003-ddk-update-libs.patch, please upgrade the commit it to bce94b557ffddd3984f8347ec41c5bfe464dff9e or you can directly download this from git.ti.com and upgrade your filesystem and give a try. http://git.ti.com/graphics/omap5-sgx-ddk-um-linux/commit/bce94b557ffddd3984f8347ec41c5bfe464dff9e Thanks RamPrasad

Ticket Name: TDA2: tda2

Part Number: TDA2 Dear TI， A strange bug comes， I find that after I run the TIDL demo ， the output detection ROI coordinate is not correct！ As you see below，I printed the detected rectangle coordinate ，then check the output value of the rectangle coordinate，nearly all of those are not accurate location . Is there any constant value needed be substracted from the variable pObjectDateDesc->ypos and pObjectDateDesc->xpos ,even pObjectDateDesc->objHeight and pObjectDateDesc->objWith needed be multiplied a constan coefficient? Looking forward to your kind reply, tks dear.

Hi, Can you specify which demo you are running and device used? Thanks, Praveen

object detection with TIDL on tda2x EVM board

Can you refer to below e2e thread to understand the format of TIDL detection output and to draw the boxes, e2e.ti.com/.../679186 Thanks, Praveen

hi，dear In fact， this page is not the right information I want。 Could you please chech the file "vision_sdk\apps\src\rtos\alg_plugins\objectdetection\objectDrawLink_algPlugin.c" ? In this file, I print the variable pObjectDateDesc->ypos and pObjectDateDesc->xpos ,even pObjectDateDesc->objHeight and pObjectDateDesc->objWith when detecting the vehicle, yet the result rectangle is far from the real vehicle objects in the image. Is there any math relation of the results coordinate？

Hi, Same question is discussed in the below thread and hence closing this thread. e2e.ti.com/.../751274 Thanks, Praveen

Yet，could anybody answer my question on that link above？

Ticket Name: TDA2: How to calculate the border pixels count for an image block.

Part Number: TDA2 Hi, I have read the pdf attached in the following thread. e2e.ti.com/.../734522 I have a doubt in that. In slide no.16, I have read the paragraph: Offset to next block is not necessarily equal to block width in order to transfer overlapping blocks. Overlapping blocks are used in case of filtering to account for the overlapping border pixels. For instance a N taps filter needs N-1 border pixels. The border width would be (N-1)/2 pixels. Example: Offset to next block= w block_width= w + N-1 I just want to know, how to calculate the block_width for a 16*16 image block, by using the mentioned formula? It means, the number of border pixels , I need to add with the original image block. Regards, Surbhi

Hi Surbhi, The overlap between blocks will depend on the overlap required for processing. For example if you are doing a 3x3 Sobel kernel then between two processing you need an overlap of 2 pixels for input blocks. If instead of 3x3 if you are doing a filtering operation with 5x5 kernel then you will need an overlap of 4 pixels between 2 input blocks ( that is what is mentioned in the ppt you refereed). Now if your output block size is 16x16 then your input block size for 3x3 filter would be (16+2)x(16+2). But the jump between two input blocks will be 16 in horizontal direction and 16 in vertical direction as there is an overlap of 2 pixels required in both direction Regards, Anshu

Part Number: TDA2 Hi Rishabh, I am from the previous post by you what doing u mean by rebuilt 64bit machine?

Hi Wilson, The executable present is for a 32 bit machine. In order to run it on 64 bit machine the tool needs to be recompiled. See e2e.ti.com/.../692787 Regards, Rishabh

Dear Rishabh I have error while generating the file

Hi Wilson, You need to install GraphViz. See requirements chapter in vision_sdk\apps\tools\vision_sdk_usecase_gen\docs\VisionSDK_UserGuide_UsecaseGen.docx. Regards, Rishabh

Hi Wilson, Try without "-img" option, without this option the image will not be generated but the usecase would be. Regards, Sujith

Dear Rishabh I have already installed the software when executing it.

Dear Rishabh Can i also ask i am suppose to use this (usecase) method to develop to algorithmic example face recognition ?

Hi Wilson, Did you try after removing "-img" as suggested by Sujith. Regards, Rishabh

Hi Rishabh I just manage to settle it by setting the PATH of GraphViz dot then after that execute with the win64.exe and it is able to generate most of the files including the img. This problem is due the GraphViz have to set the PATH pointing to "dot" . So can i ask i am suppose to follow this usecase to develop my own program? Because it quite difficult platform to understand

Hi Wilson, This is use case generation tool. This tool will not generate algorithms for you. I would suggest you to go through the documentation. Also Vision SDK does not support face recognition algorithm. Regards, Rishabh

Dear Rishabh I understand that the algorithm is not support and we have to code it in. My question was is this the place to being to write the program for my project.

Hi Wilson, Kindly go through PROCESSOR_SDK_VISION_03_03_00_00\vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_DevelopmentGuide.pdf on how to develop a new algorithm link in Vision SDK. Regards, Rishabh

Ticket Name: RTOS: Why IPC link drop the frames ?

Tool/software: TI-RTOS Hello, What are possible reasons for dropping frames by IPC link ? Specifically, in my case IPC OUT link of EVE is dropping frames. Regards, Kajal

Any update? Regards, Kajal

Which Processor are you using? Which SDK?

PROCESSOR_SDK 3.0 Regards, Kajal

And which processor are you using?

Hello Yordan, I'm able to solve this issue. Regards, Kajal

Ticket Name: TDA2EXEVM: ROS integration

Part Number: TDA2EXEVM Other Parts Discussed in Thread: MMWCAS-RF-EVM Hi, I like to integrate MMWCAS-RF-EVM with TDA2EXEVM in a ROS network. Do you have an example for TDA2EXEVM or similar boards? Thank you!

You can download the Radar SDK from the below link. https://www.ti.com/tool/PROCESSOR-SDK-TDAX Please refer to the user guide for more information. We do not have example for ROS integration. However, we do have example in Radar SDK which sends radar object data to PC over ethernet. Once on PC, you can visualize the radar object data with ROS.

Ticket Name: TIDEP-01017: Radar SDK usecases beamforming issue

Part Number: TIDEP-01017 Hello, I run the usecases "cascade_radar_beam_form", and the result is mismatched between GUI and real environment. I think the reason is calibration of TX and RX. Can i calibrate the TX and RX just like the usecsaes "cascade_radar_object_detect"? According the source code of the usecases "cascade_radar_beam_form", the parameter can be loaded from the text files. The Radar SDK only provide the MIMO parameter text files. Can TI provide the beamforming parameter text files? Thanks. Morris

Hi Morris, I am moving this to the ADAS processors forum to get you support. Thank you, -Randy

Hi, I try to calibrate the phase difference between the Rx at the beamforming mode. I put a corner reflector at 0 degree and on the static distance, and I measure the phase difference between each Rx for 10 frames. Then, i found the phase difference of each frame are different. According to my acknowledge, I think the phase difference between each Rx should be static if the corner reflector is on the static position. The result is shown below. Thanks. Morris

Hi Morris, Phase calibration datasets can be effected by local operating temperature of the devices. Most consistent data will be gathered when the device remains at the same temperature. Can you repeat this experiment, but include the following steps: 1. Allow the system to heat-up to steady state ambient operating temperature with 30 seconds of dummy chirps before taking the actual calibration data? 2. In the calibration dataset frames, discard the beginning of each frame until steady phase is observed Can you graph what phase of the target reflector vs. chirp number looks like for your setup? It may help identify if these instabilities are being caused by temperature. Thank you, -Randy

Hi Randy, I measure the Rx phase twice following these steps. step 1. I turn on the power of radar, and I let it do 60 seconds of dummy chirps. step 2. I record the data, and I turn off the power of radar. step 3. I go to step 1 after 60 second. Then, i found the phase difference of each frame are different. The result is shown below. Can you provide any advice? Thanks. Morris

Hi Morris, Can you please show me the phase stability over each chirp. What does that trend look like inside of a given frame? I agree, the assumption is that the phase delta should be pretty stable between frames. Some drift is expected depending on how much the temperature varies over time. Is the ambient temperature being controlled in any way? Is this an indoor or an outdoor measurement? Would it be possible for you to repeat this experiment in mmWave Studio using the TX-BF example project, comparing against the ProcessorsSDK code? Thank you, -Randy

Hi, Randy I try to measure the RXs phase for 1T16R, and the result is okay (<3 degree)(as shown as figure 1). I think the phase error is caused by TX beamforming in the demo. Can you have any advice? Thanks. Morris figure 1.

Ticket Name: TDA2EVM5777: How to use CAN bus in RTOS?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi, I want to use CAN bus in RTOS, is TI provide the driver(API) ? Regards

Hi, can you check if this document helps: Regards, Yordan

Hi Wall-E, please disregard my previous answer, I missed that you are using TDA2x. You can check this example and see if it works for you: Regards, Yordan

Hi Yordan, So sorry I reply so late. I have another question: How do I compile the example in sdk_3.07/ti_components/drivers/pdk_01_10_03_07/packages/ti/csl/example/mcan/mcanEvmLoopback ? Regards,

Hi Wall-E, please check here: Regards, Yordan

Hi Yordan, It seems the PDK CAN driver is independent of VisionSDK. And I have no JTAG debuger to download the binary object. Is a way to use CAN in VisionSDK? Like I can capture image from camera through IssCapute Link. I want to use CAN or other peripheral like camera. Regards.

Hi Yordan, Could you give me some idea ?

H Wall-E, I have pinged CAN experts, they will reply here soon. Regards, Yordan

Hi Wall-E, TDA2 does not have an MCAN module in it. Instead of that, it has a DCAN module that does the handling of the CAN protocol. The sample application for DCAN is available here: 'pdk\packages\ti\csl\example\dcan\dcanLoopback'. You can try this application. VSDK does have a use-case available for the DCAN module which is available at '\vision_sdk\apps\src\rtos\modules\dcan'. I think this is only available/validated for TDA3x SoC. You can port the same use-case for TDA2x. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi Dhande, Thank you for your reply. Regards.

Hi Dhande, I want to port this usecase for TDA2Px, I search the topic in forum and found this: https://e2e.ti.com/support/processors/f/791/t/726840?tisearch=e2e-sitesearch&keymatch=tda2%25252525252520dcan And I meet the same problem, I cannot receive data from a external CAN device but the external CAN device can receive the data from TDA2Px when using loopback mode. The author said he resolve this problem through Need modify "platform_tda2xx_pad_config.c" setting to modify RX pin of DCAN form AD17 (Wakeup0) to G19(dcan1_rx) if use TDA2x EVM. But I still don't know how to modify because I didn't find this configuration. Perhaps we use the different VisionSDK version. Mine is 3.07. So could you tell me How to receive data from external CAN device in VisionSDK 3.07 in TDA2Px ? Regards

Hi Wall-E, Looks like you are facing the same issue. Can you please configure DCAN-RX PAD on TDA2Px? Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Hi Wall-E, To port existing DCAN use-case from TDA3x to TDA2Px, you need to take care of the following: Module and clock enable for the DCAN module, this probably will be same for both the SoCs IO PAD (dcan_xta nd dcan_rx) configurations interrupt configurations To do the PAD configurations: You can add your own API in the file 'ti_components\drivers\pdk_xx_xx_xx_xx\packages\ti\drv\stw_lld\platform\src\tda2xx\platform_tda2xx_pad_config.c' and call it in the application OR you can modify the existing one also. Please refer to 'PlatformDCAN1PadConfig' API present in the same file for more details. Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd

Ticket Name: TDA2: System_linkControl_local function Question

Part Number: TDA2 Hi, I am using PROCESSOR_SDK_VISION_03_02_00_00, and have some confusion on function of System_linkControl_local My question is why prmSize is never been used, how receiver know the parameter size. Second, i go through all low level function, did not see any memcpy, if pPrm is a stack address, how to send? Int32 System_linkControl_local(UInt32 linkId, UInt32 cmd, Void * pPrm, UInt32 prmSize, Bool waitAck) { Int32 status; Utils_MbxHndl *pToMbx; Utils_TskHndl *pTsk; UInt32 flags = 0; linkId = SYSTEM_GET_LINK_ID(linkId); UTILS_assert(linkId < SYSTEM_LINK_ID_MAX); pTsk = (Utils_TskHndl*) gSystem_objCommon.linkObj[linkId].pTsk; if(pTsk==NULL) { Vps_printf(" SYSTEM: ERROR: No link registered at link ID [%d] !!!\n", linkId); status = SYSTEM_LINK_STATUS_EFAIL; } else { pToMbx = &pTsk->mbx; if (waitAck) { flags = UTILS_MBX_FLAG_WAIT_ACK; } status = Utils_mbxSendMsg(&gSystem_objCommon.mbx, pToMbx, cmd, pPrm, flags); } return status; } Thank you in advance BR HUI

Hi HUI, Typically control command has fixed parameter and is known to sender and receiver. So no need to use param size. Are you facing some issue because of no use of prmsize? Rgds, Brijesh

Hi Brijesh, Thank you for your reply. I try to use it for other purpose , just ask. BR HUI

Ticket Name: RTOS: Where could i find source codes for tidl preproc, EVE's computation.

Tool/software: TI-RTOS Hi, I'm trying to find source codes that are implementing tidl preprocess and Alg_tidl_EveX. Could you let me know where the source codes for them in project? Thanks in advance. Regards, Yoo.

Which SDK are you using? Regards, Manisha

Hi, You can find the source code for the above asked link in below path PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\apps\src\rtos\alg_plugins\tidl Regards, Anuj

Ticket Name: TDA2: Use vout1_fld as Vin3a_clk0

Part Number: TDA2 Hi, We will use Vin3a pin and vout1 pin like below. - Will use Display output Pin with discrete sync mode - vout1_clk (ball : D11), vout1_d0(ball : F11)...... vout1_d22(ball : B9). vout1_d23(ball : A10), vout1_de(ball : B10), vout1_hsync(ball : C11), out1_vsync(ball : E11), - We want to use vout1_fld as Vin3a_clk0 of VIN3A. - VIN3A Input : Vin3a_clk0 (ball : B11),vout3_d0(ball : M6), vout3_d1(ball : M2).... Can I use the vout1_fld pin as the Vin3a_clk0 pin of VIN3A while using the display output pin(vout1) with discrete sync mode? Regards JP Park

Hi JP, Please check the pinmux sheet, it will tell what is possible. Rgds, Brijesh

Hi Brijesh, I have checked that pinmux is possible with vout1_fld pin(MUXMODE 0) to Vin3a_clk0 pin(MUXMODE 4) : (ball : B11) I want to know if it can be used as an Vin3a_clk0 pin of VIN3A while using the display output pin(vout1) with discrete sync mode? Regards JP Park

Hi JP, The same pin cannot be used for two purpose. Rgds, Brijesh

Hi Brijesh, I think there is some confusion. The same pin is not used for two purpose. Will use the vout1_clk (ball : D11), vout1_d0(ball : F11)...... vout1_d22(ball : B9). vout1_d23(ball : A10) .... for display output except for vout1_fld pin. Will use vout1_fld pin as Vin3a_clk0 (Set to MUX MODE4 for use with Vin3a_clk0) for Vin3a. I will use vout1_fld pin as Vin3a_clk0 function for Vin3a instead of vout1_fld function for display output. Is this possible? I'm sorry, I would like to ask you again. Regards JP Park

Hi JP, Yes, it looks fine to me, if your display is progressive, there is no need for the fld output and fld pin can be used for the different purpose. Rgds, Brijesh

Hi Brijesh, Thanks for your reply. Thanks to you, the problem is solved. Regards JPPark

Hi Brijesh, We had plan to use the vin3a pins as shown below, but looking at the IOSET view of the pad conf tool, it seemed that ball B11 could not be used for the vin3a_clk0 pin function. Is it possible using differrent IOSET Pin ? Regards JP Park

Hi Park, Which SoC are you using? On TDA2x, i see there are three pins which can be used for VIN3A_CLK input. These are CTRL_CORE_PAD_GPMC_CS3, CTRL_CORE_PAD_VIN1B_CLK1 and CTRL_CORE_PAD_VOUT1_FLD. Regards, Brijesh

Hi Brijesh, Thank you for your quick reply. Yes, I am using TDA2x. I know that there are other pins for VIN3A_CLK . I want to know if it is possible using together IOSET1 (Ball M6 for vin3a_D0,Ball M2 for vin3a_D1 ) and IOSET4 (Ball B11 for vin3a_clk0) for vin3a pins. Regards,

JP Park95, Suggest you try the pin mux tool (https://dev.ti.com/pinmux). It will show you clearly with warnings/errors what's possible and what not. thanks Alex

In addition, I see from your previous post you are using our other NDA tool (the Pad Config Tool), which is fine too, but more recently we have migrated devices to the public pinmux tool I mentioned (which will give you same warnings about the ioset violation). Basically, if you violate and mix iosets you are risking to not meet the ioset's timing. The device has been characterized with these precise iosets to meet the timing requirements, switching characteristics, and iodelay manual/virtual modes. Here is the excerpt from the datasheet: CAUTION: The IO timings provided in this section are applicable for all combinations of signals for vin1. However, the timings are only valid for vin2, vin3, and vin4 if signals within a single IOSET are used. The IOSETs are defined in the Table 7- 4, Table 7-5 and Table 7-6.

Ticket Name: TDA2PXEVM: TDA2 : About Tidl_OD usecase

Part Number: TDA2PXEVM Hi Sirs, I need some advice. If my input is two-channel video, Which chain is recommended? chains_tidlOD_1 or chains_tidlOD_2? Or just use the original chains_tidlOD and run the loop twice. chains_tidlOD_1: chains_tidlOD_2: Thank you, Horace.

Hi, default TIDL_OD usecase is currently running with a single channel, So I'm not sure The TIDL algorithm will support multi-channel. So I will check with the team & get back. Thanks Gaviraju

Hi, I am looking forward to your reply. Thanks. BR. Horace

Hi, It will support multi-channel & use chains_tidlOD_1 usecase Thanks Gaviraju

Hi, If use chains_tidlOD_1 usecase Two-channel run the same SSD model, but different weight. The alg_pluging whether to add an extra tidl, and give another alg_id. Or is there another method? Thanks Horace

Ticket Name: RTOS/TDA2: how to save encoded h.264 data and play on pc ??

Part Number: TDA2 Tool/software: TI-RTOS my platform is tda2pxx , I had run the usecase "capture > encode > decode > diplay" now I want to record some frames video. so i write the usecase "capture > encode > null_save" , in null_save callback . i save the h.264 data to file . but i can't play it on pc using elecard streameye . the file code.txt is the callback func, i write , is there some wrong ?IDR.txt 0042.code.txt UInt32 idrCnt=0;
static Void capEncFrameCb(System_LinkChInfo *pChInfo, Void *pBuf, Void *arg)
{
    System_Buffer *pFrameBuf = (System_Buffer*)pBuf;
    System_BitstreamBuffer *pBitFrame;
    System_VideoFrameBuffer *pVidFrame;
    System_MetaDataBuffer *pMetFrame;
    Chains_csi2CalMultiCamAppObj *pObj = (Chains_csi2CalMultiCamAppObj*)arg;
    Int32 re=-1;
    UInt32 offset;

//    BspOsal_semWait(pObj->frameSync, BSP_OSAL_WAIT_FOREVER);

//    Vps_printf(" bufType=%d\n",pFrameBuf->bufType);
    switch(pFrameBuf->bufType)
    {
        case SYSTEM_BUFFER_TYPE_VIDEO_FRAME:
            Vps_printf(" SYSTEM_BUFFER_TYPE_VIDEO_FRAME\n");
            pVidFrame = (System_VideoFrameBuffer*)pFrameBuf->payload;
            Vps_printf(" SAVE_ENC_FRAME: Writing frame to file ...length=%d\n",pVidFrame->metaFillLength);
            break;
        case SYSTEM_BUFFER_TYPE_BITSTREAM:
//            Vps_printf(" SYSTEM_BUFFER_TYPE_BITSTREAM\n");
            pBitFrame = (System_BitstreamBuffer*)pFrameBuf->payload;
            break;
        case SYSTEM_BUFFER_TYPE_METADATA:
            Vps_printf(" SYSTEM_BUFFER_TYPE_METADATA\n");
            pMetFrame = (System_MetaDataBuffer*)pFrameBuf->payload;
            Vps_printf(" SAVE_ENC_FRAME: Writing frame to file ...length=%d\n",pMetFrame->metaFillLength);
            break;
    }

    if(TRUE == pObj->encFrame)
    {
//        Vps_printf(" firstIdrFrame=%d\n",pObj->firstIdrFrame);
        if(FALSE == pObj->firstIdrFrame)
        {
            if(1 == System_Bitstream_Buffer_Flag_Get_Is_Keyframe(pBitFrame->flags))
            {
                idrCnt++;
                Vps_printf(" First IDR frame found Cnt=%d\n",idrCnt);

//                if(idrCnt >= 2)
                {
                    pObj->firstIdrFrame = TRUE;
                }
            }
        }

        if(TRUE == pObj->firstIdrFrame)
        {
            Vps_printf(" SAVE_ENC_FRAME: Writing frame to file ...bufsize=%d,length=%d\n",pBitFrame->bufSize,pBitFrame->fillLength);
//            re = ChainsCommon_Osal_fileWrite(
//                                    pObj->fp,
//                                    (UInt8*)pBitFrame->bufAddr,
//                                    pBitFrame->fillLength);

//            re = Utils_fileWriteFile( fileName11, (UInt8*)pBitFrame->bufAddr, pBitFrame->fillLength);
            re = User_fileWrite( pObj->fp, (UInt8*)pBitFrame->bufAddr, pBitFrame->fillLength);
            offset = 5;
            Vps_printf(" offset = %d, data0-5=%x,%x,%x,%x,%x\n",
                       offset,
                       *((UInt8*)pBitFrame->bufAddr+offset),
                       *((UInt8*)pBitFrame->bufAddr+offset+1),
                       *((UInt8*)pBitFrame->bufAddr+offset+2),
                       *((UInt8*)pBitFrame->bufAddr+offset+3),
                       *((UInt8*)pBitFrame->bufAddr+offset+4));
            Vps_printf(" SAVE_ENC_FRAME: Writing Encode frame to file DONE,return = %d,Frame ID=%d\n",re,pFrameBuf->frameId);
//            pObj->encFrame = FALSE;
            BspOsal_semPost(pObj->frameSync);
        }

//        pObj->encFrame = FALSE;
    }
} the file IDR.txt is idr h264 data, can you help me to check if the data is right ? i checked many frames , the start code of each frame is 00 00 00 01 , there is no other nalu type, why?

Hi This file dump and playing with VLC media player is already validated For the Null link file write set below configuration. pUcObj->NullPrm.dumpDataType = NULL_LINK_COPY_TYPE_FILE; strcpy(pUcObj->NullPrm.nameDataFile[0], "stream.h264"); I assume you use VSDK 3.3 release regards, Shiju

Ticket Name: CCS/TDA2SG: About DDR stress test

Part Number: TDA2SG Tool/software: Code Composer Studio Hi， Can you tell me what is the difference between using the CCS tool and the memtester tool for DDR stress testing? Which test method does TI recommend? why? best regards.

Hi Feng, What is the CCS tool that you are referring here? Regards, Rishabh

Hi Rishabh， We use this tool: Code Composer Studio v8 . Refer to this document ：Avatar_EMIF_Tools_UserGuide.pdf

Hi Feng, CCS is an IDE used for loading/testing the binaries. You can also create/build projects using CCS. Similarly Memtester is the program that can be run using CCS. Hope this helps. Regards, Rishabh

Hi Rishabh， Comparing the DDR stress test results of the two tools, I want to know which test method is more comprehensive, or equivalent？ Regards,

Hi Feng, As I explained previously memtester is the utility to test the DDR stability. Hence you should use the same. In order to run mem tester you need CCS tool. Hence you need both the tools. Regards, Rishabh

Hi Rishabh， Is my statement clear enough? You mean that the test results using Avatar EMIF Tools(CCS Memory Test Tool) and Memtester (Linux Memory Test Tool) are the same. But it seems that Memteser has higher requirements on the space of the measured memory. Regards,

Hi Feng, Yes, both might have separate requirements due to difference in OS but the results are the same. Regards, Rishabh

Ticket Name: RTOS/TDA2: Dynamic changes for VPE

Part Number: TDA2 Tool/software: TI-RTOS Hi Everyone , We are working on requirement to dynamically zoom in particular region of the output we are capturing. we have a VPE link in TDA2 which will perform the cropping and resizing , I like to know whether it is possible to change the crop parameters dynamically on runtime for VPE link . If that is possible , kindly suggest me if there are another ways to crop dynamically without rebooting .

Hi Surendar, At which rate do you want to change the parameters? Regards, Brijesh

Hi Brijesh , I could not understand what you mentioned by "rate" , is it FPS or is it something else . Can you please elaborate on that. Regards, Surendar

Surendar, I meant, do you want to change it on every frame submission? Regards, Brijesh

Hi Brijesh, Yes , on every frame submission I want to change the parameters Regards , Surendar

Hi Surendar, ok, i would suggest you to have a look into the API VpeLink_drvUpdateInputRtPrm in VPE link. This will give idea for how you could change the VPE crop parameters per frame. Rgds, Brijesh

Hi Brijesh , Thank you , I will check and update you on this Regards , Surendar

Ticket Name: TDA2E: vision SDK 3.02 dsp change OPP_NOM to OPP_HIGH

Part Number: TDA2E Hi I try to change dsp frequency from OPP_NOM to OPP_HIGH or OPP_OD. I modify DRA7_CORE_OPP from OPP_NOM to OPP_HIGH in Clock.c file.(file from ti_components/os_tools/linux/u-boot/u-boot/arch/arm/include/asm/arch-omap5/Clock.c) But I use omapconf show opp to check result,it still is OPP_NOM. Do anything I miss when I want to change dsp freqency? thanks Yumei

Hi Yumei, please check if this document can help you: Regards, Yordan

Ticket Name: TDA4VM: Is there any way to control the switch of a stream in the graph?

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi TI: I integrated multiple streams in one graph: PSD/OD/SRV/DVR..Now I want to control the on/off state of one of the streams, just like the Gate link in J6（TDA2） platform. Is there a kernel like Gate link in the J7 platform? Or is there any way to achieve this? Regards, Damon

Hi TI: Supplementary Instructions: I want to dynamically control the switch of a certain stream during the running process of the app. For example： After app started: at time_1, I want run 'SemSeg' stream only; Time_2,,I want run 'PSD' stream only; Time_2,,I want run 'PSD' and 'VD' stream;

Hi Damon, No, unfortunately, there is no gate link like feature available in the OpenVX framework. You would have to add it in the framework or at the node level.. Like add a control command in the node, when you want to stop processing and then in process function, just skip processing. Again resume it again on second control command.. Regards, Brijesh

Hi Brijesh, Yep.I tried this and found that: if I just send stop cmd to pre_proc node, it dis stop. But it's downstream nodes will still execute processing instead of blocking. Form this it seems that I need to add and send stop cmd to every node in this stream(pre-proc/tidl/post-proc), right? Regards, Damon

Hi Damon, Yes, require to add this command to all downstream modules, and whenever you want to change processing, you probably need to start from the last node in that path.. Regards, Brijesh

Hi Brijesh, Thank you! And I wander will TI consider providing a convenient solution for this requirement in subsequent releases? Regards, Damon

Ticket Name: TDA2: Executing TIDL on TDA2x

Part Number: TDA2 Hi, These are the steps I'm following to run the dsp_test_dl_algo.out. 1.Open CCS. Launch Selected Configuration. 2.Select A15_0. Go to Run->Reset->System Reset. Right click-> Connect Target. Go to Scripts->TDA2xx MULTICORE Initialization->TDA2xx_MULTICORE_EnableAllCores 3.Select C6xx_DSP1. Right click->Connect Target. 4.Go to Run->Load->Load Program. Select the path of dsp_test_dl_algo.out. file and click Ok. 5.Click on Resume button. In the console I am seeing these logs. [C66xx_DSP1] Processing config file ..\testvecs\config\infer\tidl_config_jseg21.txt ! and nothing after that. Do any more configuration need to be done or is there anything wrong with the configuration I am currently setting? Thanks in advance, Navinprashath.R.R

Hi Navin, Hold on for some time, at that time input file reading is happening and will take up to an hour based on the file size. Thanks, Praveen

Ticket Name: Linux/TDA2: TDA2xx How to compile opencl

Part Number: TDA2 Tool/software: Linux I want to use opencl encapsulation in my algorithm， I added " OPENCL_INCLUDE=yes " in the configuration file (vision_sdk\apps\configs\tda2xx_evm_linux_all\cfg.mk) . But compiled failed. How can I make the “OPENCL_INCLUDE“ effective？

Hi, can you try to set MAKECONFIG to tda2xx_evm_linux_opencx in vision_sdk/build/Rules.make? (Or compare the contents of vision_sdk/apps/configs/tda2xx_evm_linux_opencx and vision_sdk/apps/configs/tda2xx_evm_linux_all/) Regards, Yordan

Ticket Name: Linux/TDA2: null_src_decode_display run problem

Part Number: TDA2 Tool/software: Linux i have build visionsdk and run ,i sellect 5: NullSrc + Decode + Display (Only 1920x1080 H264/MJPEG Video Input Bit-Stream Supported) but fail follow is print inf Single Camera Usecases [HOST] [HOST ] ------------------------ [HOST] [HOST ] 1: 1CH VIP capture + SGX Copy + DISPLAY [HOST] [HOST ] 2: 1CH VIP capture + Encode + Decode + SGX Copy + DISPLAY [HOST] [HOST ] 3: 1CH VIP capture + Alg FrameCopy (EVE1) + SGX Copy + DISPLAY - (TDA2xx ONLY) [HOST] [HOST ] 5: NullSrc + Decode + Display (Only 1920x1080 H264/MJPEG Video Input Bit-Stream Supported) [HOST] [HOST ] 6: 1CH VIP capture + Alg Frame Copy (A15) + SGX Copy + DISPLAY [HOST] [HOST ] 7: 1CH VIP + Alg Frame Copy (A15) + Connetor Links (Dup, Merge, Select, Gate on A15) + SGX Copy + DISPLAY [HOST] [HOST ] [HOST] [HOST ] x: Exit [HOST] [HOST ] [HOST] [HOST ] Enter Choice: [HOST] [HOST ] 5 [HOST] [HOST ] 902.534290 s: [HOST] [HOST ] 902.534320 s: [HOST] [HOST ] [HOST] [HOST ] ========================================= [HOST] [HOST ] Chains Run-time Codec Type Selection Menu [HOST] [HOST ] ========================================= [HOST] [HOST ] [HOST] [HOST ] Enter '0' for MJPEG [HOST] [HOST ] [HOST] [HOST ] Enter '1' for H.264 [HOST] [HOST ] [HOST] [HOST ] Enter Choice: [HOST] [HOST ] 1 ASSERT (nullSrcLink_tsk.c|NullSrcLink_create|1083)

Hi, Did you copy the input files to home folder of file system or not ? Regards Suryamani Jena

Hi Suryamani Jena 1920x1080_00.hdr 1920x1080_00.h264 where is this tow file? Regards shuai

Hi Shuai, It should be available in CDDS (refer below link) Vision SDK demo clips are available at cdds.ext.ti.com/.../emxNavigator.jsp Regards Suryamani Jena

Hi Suryamani Jena but i have no cdds , i have .h264 file for test , How to get the correspond .hdr file? BESTWISHES SHUAI

Hi shuai, I replied in below thread (Please refer) e2e.ti.com/.../2551636 Regards Suryamani Jena

Hi Suryamani Jena can the file put /opt/704X400_00/704X400_00.h264 or need to /home/704X400_00/704X400_00.h264 ? BESTWESHES SHUAI

Hi Shuai, It should be under /home of rootfs partition Refer Usecase You need to copy files to /home/704X400_00.hdr & /home/704X400_00.h264 Regards Suryamani Jena

Ticket Name: RTOS: Display link output statics

Tool/software: TI-RTOS Hello, I want to clear doubt regarding display link statics. For any use case , when we print statics for display link there no output statics. Why is it so? Regards, Kajal.

Hi Kajal, There is no output from display link and hence there is no output statistic. Regards, Rishabh

Okay. Meaning output frames are going to display drivers for displaying them. ( i. e. FVID2_Frame for that purpose) Is my understanding correct?? Regards, Kajal

Kajal, Input frame is being used by display driver for displaying data. After the frame display is complete, the driver returns the frame to the application. You can also refer to use case diagram. Regards, Rishabh

Hello Rishabh, About which use case digram you are talking? Regards, Kajal

Hi Kajal, You can look at any Vision SDK use case jpg. E.g. PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\apps\src\rtos\usecases\vip_single_cam_frame_copy\chains_vipSingleCameraFrameCopy.jpg Display link is the last block. The output does not go to any other link. Hope this clarifies. Regards, Rishabh

Okay Rishabh, thank you for clarification. Regards, Kajal

Closing the thread as issue has been resolved. Regards, Rishabh

Ticket Name: PROCESSOR-SDK-DRA8X-TDA4X: TDA2 to TDA4 transition

Part Number: PROCESSOR-SDK-DRA8X-TDA4X Hello, we are analyzing Processor SDK RTOS Automotive with goal of using it for software development for TDA4 SoC based platform. We have years of experience with TDA2 SoC and Vision SDK, so shifting to newer TDA4 SoC and new SDK is giving us trouble to understand how are Linux and RTOS part of SDK supposed to work together? In terms of which SDK has what work to do throughout the joined build? Having separate SDKs got us confusing because we got used to have all in one place in previous SDK and to do all the work from one single top level make. And in Vision SDK we head links and chains, what is the concept for creating use-cases now? Can you elaborate on these matters to help us draw parallels between these to approaches to SDKs? Regards. Uros

Hi Uros, I believe that we have some links which already capture this, and I will try to provide you a reference on this soon. Regards Karthik

hi, Here is how you can draw parallel between Vision SDK and PSDKRA. Installation and build Vision SDK Linux would look like a single installer, however there were some additional steps that were needed to make Linux and RTOS in Vision SDK like below 1. Download and install Vision SDK 2. Download a compatible Linux filesystem 3. Clone Linux kernel, uboot, graphics driver and then apply some specific patches. 4. Then build and run The above steps remain same in PSDKRA, only one needs to do below 1. Download and install PSDKRA - this is equivalent of Vision SDK 2. Download and install PSDKLA - this gives the compatible filesystem and Linux kernel, uboot and drivers. - The file system is at ${PSDKLA_PATH}/filesystem/tisdk-rootfs-image-j7-evm.tar.xz - The Linux kernel, uboot is at ${PSDKLA_PATH}/board-support 3. Now build and run vision_apps Application development Next in Vision SDK, one would goto vision_sdk folder and then do make to build everything. In PSDKRA, the equivalent is goto vision_apps folder and then do "make sdk" to build everything and then "make linux_fs_install_sd" to install everything to a Linux filesystem SD card. There are some steps to build a Linux filesystem SD card, one time, this is documented here, vision_apps/docs/user_guide/BUILD_AND_RUN.html There are scripts which help to do this. This about same as Vision SDK. Next is how to do application development using PSDKRA, I will assume you want to build analytics or camera or ADAS applications. For this refer to vision_apps once again, the "links and chain" equivalent in PSDKRA is OpenVX. To get started with OpenVX run the tutorials located here vision_apps/apps/basic_demos/app_vx_tutorial/main_vx_tutorial.c This is just the entry point to the OpenVX tutorial, actual tutorial code and documentation is here, tiovx/tutorial - code tiovx/docs/user_guide/index.html - documentation Once you familiarize your self with OpenVX you can try more specific example as listed in vision_apps/apps - code vision_apps/docs/user_guide/DEMOS.html - documentation Overall vision_apps is the equivalent of vision_sdk tiovx is the equivalent of vision_sdk/links_fw Refer to documentation in these two places, you can reach these two documentation by following the top level page ${PSDKRA_PATH}/index.html > "SDK components" See also "Developer notes" here for some additional information. Let me know if you need more information regards Kedar

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 1. How many watchdog timers in TDA2SXBTQABCRQ1 and where? 2. The MPU has its own watchdog timer that is different from watchdog timer in the PRCM? 3.IPU and DSP use the watchdog in the PRCM? If so, how to distinguish the error output by watchdog? 4. The following picture is from TDA2 technical reference manual chapter 18.4.6. When T is not within threshold low to threshold high, the output alert maybe do not be asserted to 1, like the blue arrow in the picture. Why? thank you!

1. 2 watchdog timers. 1x system watchdog and 1x MPU watchdog timer. 2. yes. 3. One watchdog timer can only be used by either IPU or DSP. You can also use GP Timer as watchdog timer. 4. Alert (Temp too high) is generated first when the temp goes above the high threshold and the next alert (Temp is safe) is generated only when the temp goes below the low threshold. In between this two events is where you have to do thermal management to lower the temp to avoid thermal shutdown.

Ticket Name: TDA2 ARM Cortex M4 Floating point support FPv4SPD16

Other Parts Discussed in Thread: TDA2 Hi, I am using Code Composer Studio 5.4.0.00091 In my project, I have enabled floating point support FPv4SPD16(ARM compiler processor option) for CortexM4 in TDA2. After i build my project, I checked .asm file. It is showing --float_support=vfplib Why compiler has not generated asm file for FPv4SPD16? Jagan

Jagan, I will FW this here to CCS experts . thanks, Alex

Jagan, The TDA2x Cortex M4 does not have a floating point hardware. Only vfplib is supported. Regards, Chaitanya

Ticket Name: Compiler/TDA2EVM5777: TIDL is slower when the input is recorded video than the input is camera captured frame

Part Number: TDA2EVM5777 Tool/software: TI C/C++ Compiler Hi, I'm testing the performance of TIDL in two case. First case is using the recorded video as input and second case is using the captured frame from camera sensor. When i compare the FPS of TIDL in above two case, the FPSs were different. The resolution of input were same in both case, moreover i used VPE link before feeding frame to TIDL. The chains of two case are below. - Video input (29.4 fps) NullSource (ch 1, 2, 3, 4) -> Merge -> Decode -> VPE -> Select -> tidlPreProc -> TIDL_EVE -> TIDL_DSP -> Merge -> NullLink - Camera input (30.3 fps) Capture (ch1, 2, 3, 4) -> VPE -> Select -> tidlPreProc -> TIDL_EVE -> TIDL_DSP -> Merge -> NullLink I removed TIDL_EVE and TIDL_DSP link in both case, to confirm whether the cause of difference is from different input link. However, the fps of both case were same as 30.x fps. Could you give me any clue to resolve this problem? Regards, Yoo

Hi, I do not understand why you use merge link for recorded frames. Please share the stats log by pressing p after running the usecase for 1 min for both cases. Regards, Anuj

Hi, Its been long since any update on this threads. I hope the issue is resolved. if not then please reply below or create a new thread for different issue. Regards, Anuj

Ticket Name: Compiler/TDA4VMXEVM: TIVXDisplayCallBack is not call

Part Number: TDA4VMXEVM Tool/software: TI C/C++ Compiler Hi, I add log in the "TivxDisplayCallBack " and i run the demo run_app_tidl.sh ok. 1.why the display callback funtion is not run ？ In TDA2s the chains & links ,The Display's callback funtion will call . 2.how can I get Capture & display run status.(In tda2s , i can see the callback of capture & display)

Hi Zhangsc, If display is running, display callback always get called. Just like TDA2x, TDA3x, there is a similar feature on TDA4x to enable periodic callback. This feature is by default enabled, so callback will always be called, whenever display is enabled.. Rgds, Brijesh

my version is 0602 ,but i cannot see rhe add log in.the display callback. can you test it.

But is your display running fine? Do you see any numbers for the entire graph? Rgds, Brijesh

Ticket Name: RTOS: How can i import TensorFlow MobileNet V1 model to TIDL model?

Tool/software: TI-RTOS Hi, I'm trying to convert TensorFlow-slim based MobileNet model(ver1) following TIDLDeepLearningLibrary.pdf section 3.6.5. I downloaded mobilenet_v1_1.0_224.ckpt.data-00000-of-00001, mobilenet_v1_1.0_224.ckpt.index, mobilenet_v1_1.0_224.ckpt.meta, mobilenet_v1_1.0_224.pb. And i ran the command to optimize mobilenet_v1_1.0_224.pb. However, these warning messages were shown. -------------------------------------------------------------------- WARNING:tensorflow:From /usr/local/lib/python3.4/dist-packages/tensorflow/python/tools/strip_unused_lib.py:86: extract_sub_graph (from tensorflow.python.framework.graph_util_impl) is deprecated and will be removed in a future version. Instructions for updating: Use tf.compat.v1.graph_util.extract_sub_graph WARNING:tensorflow:From /usr/local/lib/python3.4/dist-packages/tensorflow/python/tools/optimize_for_inference_lib.py:113: remove_training_nodes (from tensorflow.python.framework.graph_util_impl) is deprecated and will be removed in a future version. Instructions for updating: Use tf.compat.v1.graph_util.remove_training_nodes WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_1_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_2_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_3_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_4_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_5_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_6_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_7_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_8_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_9_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_10_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_11_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_12_depthwise/BatchNorm/FusedBatchNorm' WARNING:tensorflow:Didn't find expected Conv2D input to 'MobilenetV1/MobilenetV1/Conv2d_13_depthwise/BatchNorm/FusedBatchNorm' -------------------------------------------------------------------- Anyway, i ignored that messages and used result pb file to convert to TIDL model. After i executed tidl_model_import.out.exe D:\TI_TDA2x\ti_dl\test\testvecs\config\import\tidl_import_mobileNet1.txt, this error message was shown. -------------------------------------------------------------------- TF Model File : ..\..\test\testvecs\config\tensorflow_models\mobilenet\mobilenet_1_224.pb Could not find the requested input Data : MobilenetV1/MobilenetV1/Conv2d_0/Relu6 !! -------------------------------------------------------------------- Doesn't TIDL importing tool support Relu6 layer? If then, could you let me know how could you validated TF MobileNet V1 model? Thanks in advance. Yoo.

Please use TF version 1.1 for the freezing graph. We are yet to upgrade to the latest version of TF.

Thank you. It works normally after i reinstalled tensorflow 1.1.0 version. Regards Yoo.

Ticket Name: TDA2: OSA_timerCreate function question

Part Number: TDA2 Hi, For function OSA_timerCreate Int32 OSA_timerCreate(OSA_TimerHndl *hndl,OSA_TimerCb cbf,union sigval value) Is it a hardware timer, will callback function run in interrupt context? I found in the callback function of TI user case example, there is wait function inside. If it is hardware timer, it will cause disaster, could you explain about it? Also where can i find the definition of timer_create? I want to make sure it has no problem before we use it at large scale commercially. ex： inside callback func System_sendLinkCmd(pObj->tskId, SYSTEM_CMD_NEW_DATA, NULL) is used, finally it will go to OSA_msgqSend int OSA_msgqSend(OSA_MsgqHndl *hndl, OSA_MsgHndl *msg, Uint32 timeout) { int status = OSA_EFAIL; pthread_mutex_lock(&hndl->lock); while(1) { if( hndl->count < hndl->len ) { hndl->queue[hndl->curWr] = msg; hndl->curWr = (hndl->curWr+1)%hndl->len; hndl->count++; status = OSA_SOK; pthread_cond_signal(&hndl->condRd); break; } else { if(timeout == OSA_TIMEOUT_NONE) break; status = pthread_cond_wait(&hndl->condWr, &hndl->lock); } } pthread_mutex_unlock(&hndl->lock); return status; } Best regards HUI

Hi Hui, Timer_Create is standard Linux API to create based on the given clock id. It uses high resolution hrtimer. Now since the timer the callback is in application space, it isnot really running in interrupt context. Where do you see wait in the timer callback? Rgds, Brijesh

Ticket Name: TDA2EG-17: VSDK V03.08 has year 2038 issue for HLOS

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2 This thread is related follow thread (https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1071329/am3356-year-2038-problem-for-processor-linux-sdk-v7-03?tisearch=e2e-sitesearch&keymatch=rtc%202038#) Hello, We're using VSDK (v03.07/03.08) for TDA2/TDA2EG17, but the Linux kernel seems to have the same year's issue with the AM35xx SDK, Our product is a mirror with DVR feature, but the Linux date system only seems to support the past 2038 years date. Is there any patch from TI to fix this issue? Will the same problem happen with the next-gen SDK(TDA4)?

Ticket Name: TDA2: TIDL sample real-time applications

Part Number: TDA2 Hello, I have gone through most references available for TIDL on TDA2x. The TIDL Library User Guide and Datasheet are nice starting points to understand the deployment of neural networks on TDA2. But the deployment procedure described in the Guide works in a disjoint fashion, i.e., for a neural network whose layers are split between EVE and DSP cores, we have to first execute the layers on EVE, get the output, and then feed it to execute the layers on DSP. Obviously, this cannot happen in a practical scenario; I will have to set up the entire network in one go. I also went through the TIDL Library API described at this link. But this whole chapter appears to apply to TIDL for AMxx processors, and I did not find any equivalent reference for TDA2x processors. Can you point me to some sample applications which cover an end-to-end scenario, e.g., test image(s) fed to a neural network which is split across EVE and DSP, where the interlinking and I/O of the EVE and DSP is handled in real-time by the program, and then visualization of the final output? Thank you.

Hi, for the API you can check the file PROCESSOR_SDK_VISION_03_XX_XX\ti_components\algorithms\REL.TIDL.01.01.03.00\modules\ti_dl\docs\TIDeepLearningLibrary_API.chm. I will ping experts for the other questions. Regards, Yordan

The TIDL Library User Guide for TDA recommends creating TIDL applications based on XDAIS. On the other hand, the TIDL documentation for AMxx processors (refer link in first post) does not lay down any such guideline. The TIDL documentation for AMxx processors also appears to have many examples for different use-cases, along with code snippets to explain the network setup and execution. It kind of feels like the TIDL was initially built for AMxx devices, and later adapted for TDAxx. I would like to know how much of the network deployment concepts, programming guidelines, and examples from the [AMxx/Processor SDK for Linux] can be reused for [TDAxx/Processor SDK for Vision]. I would much appreciate it if the experts can also comment on this.

TIDL is stand-alone OS independent library was developed part of TDAxx SDK. TDAx SDK has example use cases developed using BIOS. The AMxx SDK provides the solution to deploy network from the host (Linux) using the same TIDL library. You can refer the network deployment and calibration related documentation from both SDKs

Ticket Name: Linux/TDA2: TDA2xx Linux make install error

Part Number: TDA2 Tool/software: Linux Dear All, I have a problem, when i set make linux_install command have error ; this is my error, sdk vision: PROCESSOR_SDK_VISION_03_03_00_00 , felllow doc : VisionSDK_Linux_UserGuide.pdf log_tda2error.txt owen@owen-VirtualBox:~/Desktop/TDA2/Linux/vision_sdk/build$ make linux | grep "error"
  WRAP    tools/lib/libfdt/fdt_strerror.c
  HOSTCC  tools/lib/libfdt/fdt_strerror.o
  CC      lib/libfdt/fdt_strerror.o
  CC      spl/lib/libfdt/fdt_strerror.o
  CC      lib/fdt_strerror.o
  CC [M]  drivers/scsi/scsi_error.o
configure: WARNING: If you wanted to set the --build type, don't use --host.
    If a cross compiler is detected then cross compile mode will be used.
owen@owen-VirtualBox:~/Desktop/TDA2/Linux/vision_sdk/build$ make linux_install | grep "error"
/bin/sh: 1: mkimage: not found
make[1]: *** [kernel_install] Error 127
make: *** [linux_install] Error 2
owen@owen-VirtualBox:~/Desktop/TDA2/Linux/vision_sdk/build$ make linux_install 
make -C ./hlos/makerules/linux -f build_kernel.mk kernel_install
make[1]: Entering directory `/home/owen/Desktop/TDA2/Linux/vision_sdk/build/hlos/makerules/linux'
make -fbuild_kernel.mk kernel_build KERNEL_TARGET=modules_install INSTALL_MOD_PATH=/home/owen/Desktop/TDA2/Linux/vision_sdk/../ti_components/os_tools/linux/targetfs
make[2]: Entering directory `/home/owen/Desktop/TDA2/Linux/vision_sdk/build/hlos/makerules/linux'
make -C /home/owen/Desktop/TDA2/Linux/vision_sdk/../ti_components/os_tools/linux/kernel/omap ARCH=arm CROSS_COMPILE=/home/owen/Desktop/TDA2/Linux/ti_components/os_tools/linux/linaro/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf- modules_install
make[3]: Entering directory `/home/owen/Desktop/TDA2/Linux/ti_components/os_tools/linux/kernel/omap'

Hi Owen, it seems that the problem was caused by missing 'mkimage' program. Please follow chapter "2.2.3 Other mandatory software packages for build" from VisionSDK_Linux_UserGuide.pdf to install additional packages needed for Linux build. Regards, Yordan

Hi Owen, The "mkimage" tool is built by "make uboot" If it still could not fix the issue, recommend you had better "make clean" and manually delete $INSTALL_DIR/vision_sdk/binaries/$(MAKEAPPNAME)/$(MAKECONFIG) then rebuilt it. BR, Sam Hsieh

Dear Sam & Yordan, thanks ur information. i'm install sudo apt-get install u-boot-tools cansolve this problem

Dear Sam & Yordan, thanks ur information. i'm install sudo apt-get install u-boot-tools cansolve this problem delete and rebuild, can ignored warning message or not?

Hi Owen, As for solved by install u-boot-tools, remind you that compile successfully, not means that run ok. you had better to build it by the cross compiler (ARM) and refer to the Vision SDK(v03.03.00) Linux User Guide. BR, Sam Hsieh

Dear Sam, I'm fellow sdk3.3.0 to build & run , thanks for your valuable suggestion.

Ticket Name: TDA2SX: GPIO Pull-Up Resistance Value

Part Number: TDA2SX Dear Support member The GPIO8 _1Pin can be set to Pull - up/Down. What is the resistance value when Pull-Up is performed? Best Regards,

The internal pull-up can vary based on process and temperature. Nominal is about 50K-ohms, but can vary from 10K-ohms to over 100K-ohms.

Ticket Name: TDA2: EVE :DIVISION OPERATION

Part Number: TDA2 Hi, I want to use division operation for unsigned short(16bit) in my code, i have checked the implemented kernels regarding division i.e (kernelslib/array_div_unsword ) & ( kernelslib/array_div_unsshort_w_TLU). Is their any other method to implement division operation? Regards Surbhi

Hi Surbhi, If its a generic division operation then you will need to use look up table based approach. Regards, Anshu

Ticket Name: Linux/TDA2: Where to find "Image data buffer address of capture source" ?

Part Number: TDA2 Tool/software: Linux Hi Sir, My HW is TDA2x CPU board + Vision Board + daughter board + LVDS sensor and SDK is PROCESSOR_SDK_VISION_03_05_00_00 with TDA2XX_EVM_LINUX_ALL define. I select use-case "4CH VIP LVDS capture + SGX MOSAIC + DISPLAY" and I want to save the source image in this ues-case. I try to check the typedef structure in this case, but I can't find the parameters for recording the image buffer address. "structure name: Chains_lvdsVipMultiCam_SgxDisplayAppObj". May you tell me where to find the image buffer location and any document about describing the structure define ? Thanks. Ranny.

Hi Ranny, Probably, you could put breakpoint on the capture callback, and once it runs FVID2_Dequeue, you could get the address of the frame captured from Fvid2_frameList.frame[0].addr[0][0] field. Rgds, Brijesh

Ticket Name: RTOS/TDA2: Rear Collision and Detection without RADAR

Part Number: TDA2 Tool/software: TI-RTOS Hi Everyone, Is there any use case available in Vision SDK for "rear collision and detection" for TDA2x EVM board without radar fusion . If not available I like to know if there is any algorithm implementation can be done for "Rear Collision and Detection " in TDA2X EVM board . I like to know if there is any possibility to execute the collision and detection without using RADAR data . Regards , Surendar

Hi, Can you check the below usecase vision_sdk\apps\src\rtos\usecases\vip_single_rvc_cam_view_crc vision_sdk\apps\src\rtos\usecases\vip_single_cam_object_detection2 Regards, Anuj

Hi Anuj, I am trying to run both the usecases on TDA2X board , object detection works fine without any issues . However I could not run the rvc_cam_view_crc usecase in tda2xx board . I have followed following steps for the same. 1) Enabled the usecase in uc_cfg.mk in tda2xx_evm_bios_all 2) Added an option for the usecase in chains common file for selecting the particular usecase 3) changed the SW3 dip switch pin#1 to 1 , previously it was 0 When I ran the usecase , I couldn't find any assertions or error in the console . In the HDMI display I am getting green lines all over the screen Kindly guide me on how to make this usecase work on TDA2xx EVM board. Regards , Surendar

Hi, You will not be able to run that usecase. You can take refrence from the above 2 usecases and create your own. Regards, Anuj

Hi, If the issue is resolved then can you close the thread. Regards, Anuj

Ticket Name: RTOS/TDA2: TDA2xx use 964 deserializers?

Part Number: TDA2 Tool/software: TI-RTOS Dear All, I have TDA2xx & 933 camera. How to use 933 serializers camera in TDA2xx? have any deserializers 964 board to TDA2xx?

Hi, This serializer is not validated on TDA2x. Also UB964 cannot be used on TDA2x, as TDA2x does not support CSI input. Rgds, Brijesh

Hi Brijesh, thank you, i have one more question. can the deserializers 914 link serializers 933 or not?

Hi Owen, At least 933 specs does not mention support for 914, so it does not look like possible. Rgds, Brijesh

Ticket Name: TDA2: Error when importing Lenet model

Part Number: TDA2 Hi, I'm importing the Caffe LeNet model and the tool crashes when processing Fully Connected Layer 1. The inputs to the fc1 layer is 9216 (64x12x12 Flattened) and num of outputs are 1024. Here is the import file. # Default - 0 randParams = 0 # 0: Caffe, 1: TensorFlow, Default - 0 modelType = 0 # 0: Fixed quantization By tarininng Framework, 1: Dyanamic quantization by TIDL, Default - 1 quantizationStyle = 1 # quantRoundAdd/100 will be added while rounding to integer, Default - 50 quantRoundAdd = 25 numParamBits = 8 # 0 : 8bit Unsigned, 1 : 8bit Signed Default - 1 inElementType = 0 inputNetFile = "..\..\test\testvecs\config\pp_lenet_model\lenet.prototxt" inputParamsFile = "..\..\test\testvecs\config\pp_lenet_model\lenet.caffemodel" outputNetFile = "..\..\test\testvecs\config\tidl_models\NET_OD.BIN" outputParamsFile = "..\..\test\testvecs\config\tidl_models\PRM_OD.BIN" rawSampleInData = 1 preProcType = 4 sampleInData = "..\..\test\testvecs\input\lenet_48_48.y" tidlStatsTool = "..\quantStatsTool\eve_test_dl_algo.out.exe" Regards, Navinprashath.R.R

Hi, Can please try with caffe jacinto model first, may be cifar10. Thanks, Praveen

Hi Praveen, In one of the documents, I found that the maximum number of input or output nodes supported for FC layer in TIDL is 4096. So I made a workaround by slicing input nodes(Instead of one FC, now I have 3 FC layers). Regards, Navinprashath.R.R

Ticket Name: RTOS / TDA2：video format RCCC to YUV420SP

Part Number: TDA2 Tool/software: TI-RTOS Hi, We using TDA2XX on our product and we have two question to confirm 1. Can we transform RCCC raw data to YUV420SP in TDA2 SOC? 2. We would like to integrate TIDL_OD and deep learning Lane Detection we develop. but if we transform the video format by using TDA2 SOC . Will it lead to has less computing power?

Cheng, I can answer part of the question. There is no hardware support for converting RCCC to YUV420, but you could have your own algorithm running on DSP/EVE to do this conversion. Rgds, Brijesh

Ticket Name: TDA2SX: Running image radar on TDA2, what's the best performance we can get?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi experts, This seems to be an obvious question that should have been frequently asked.... but I couldn't find any concrete answer in the forum. Does TI or anybody know what's the best radar-performance we can get out of TDA2sx running 4-chip cascade radar? TI has the great image radar reference design with 4-AWR2243s and TDA2sx, the reference code is good enough to get us started but left a lot to be desired. We are now able to run relatively smooth 10fps point-cloud MIMO with 256-range-bins, 64-velocity bins and 256 azimuth bins on TDA2sx, and we are trying to stretch the performance. Even though TI has a spreadsheet (ProcessorSDKRadar_SystemPlanner) that helps calculate the TDA2 resources based on radar parameters, we found it somewhat over-simplifying the calculation? We just wonder if anyone knows first hand what the TDA2 is capable of as the image radar center processor, or what's the most performance, in terms of radar specs, that the TDA2 could achieve. Thanks! Li

Ticket Name: TDA2HG: OpenVX

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 What accelerator does the OpenVX implementation supports? I know that your demos won’t be moved over to OpenVX but how stable is the OpenVX implementation if we wanted to implement our algorithms with OpenVX for the TDA2 family?

Aaron, Thanks for your questions. 1. Supported targets: As of today, all of the OpenVX kernels are implemented on C66 DSPs, so they are certainly supported as available targets. Connectivity to user kernels on EVE target has been verified using a TI extension "Harris Corners" kernel. And the ARM M4s and A15s are also supported targets. 2. OpenVX is currently in beta for TDA2x family. What we mean by this is that it passes the OpenVX conformance tests, as well as additional robustness tests, but it hasn't been internally tested in non-trivial algorithm demos/applications yet. We intend to do this internally by the time we make our end of year release, and in the mean time we also intend to continue to add features (such as graph pipelining) and support bug fixes on TDA2x platform. Algorithms which could benefit from graph pipelining will function, but not as optimally as will be the case when graph pipelinining is supported. Adding custom kernels can be done by following the pattern from existing OpenVX kernels, and one of the tutorials shows how to do this. We are also planning on adding scripts and specific app notes for this in the next few months which facilitate this effort. Please let me know if you have any more questions. Jesse

Ticket Name: Linux/TDA2: usecases\null_src_decode_display change

Part Number: TDA2 Tool/software: Linux if i change some code of usecases\null_src_decode_display , i just make -s -j ? need make -s -j depend ?

Hi Shuai, to rebuild the usecase you need just "make -s -j". You can check chapter "3.2 Building the application" of VisionSDK_UserGuide_TDA2xx.pdf for more details when "make -s -j" and "make -s -j depend" is used (in general the "make -s -j depend" command is used when some configs or something in ti_components has changed). Regards, Yordan

Ticket Name: Need memory address range for onchip and external memory of TDA2x.

Other Parts Discussed in Thread: TDA2 Hi, I want to know the memory address range for onchip and the external DDR memory of TDA2x SOC chipset. I checked in the datasheet and unfortunately I could not find that information. Thanks, Vasanth

Hi Vasanth, Can you see Memory Mapping chapter in the TDA2 TRM? Regards, Rishabh

Hi Rishabh, Thank You for your reply. We can close this ticket. Thanks and Regards, Vasanth

Ticket Name: TDA2E: Power Rail current requirements for TDA2+ and TDA2E

Part Number: TDA2E Other Parts Discussed in Thread: TDA2, Is there any documentation that i can reference that show's current requirements for each rail for TDA2+ and TDA2E.

Hi Julio, Current requirements will depend on many factors. I'm not sure we have study for those SoCs. But I'm sure the results would be very similar to these: processors.wiki.ti.com/.../AM57xx_Power_Consumption_Summary Regards, Stan

Stan, Yes this is what i was looking for. Just a power consumption summary for typical use cases with TDA nothing too specific. Best, Julio

Ticket Name: Compiler: xCAM Reference Design with TDA2

Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler I seen Mr Yogesh Marathe, He explain about the xCAM Reference Design with TDA2. I want to use the module and likely to adopt this in my concept.

Kindly reply, I want to buy immediately.

Hi Yuvaraj , Latest Vision SDK doesn't support XCAM . Last supported version was 2.11 TI Doesn't Support sales of XCAM directly. Please look at the below link to find TI supported devices www.ti.com/.../tools-software.html Regards Chetan.M

any updates on this thread , can we close the same

Ticket Name: TDA2: TDA2 DDR3 layout rule

Part Number: TDA2 Hello I read from DM that routing specification about DDR the Table 8-51 mention the length between SoC & DDR3, but the unit is in ps. How to transfer the ps to mil ? thank you

Hi, can you check the answer in this thread for the same question: e2e.ti.com/.../611865 Regards, Yordan

Ticket Name: RTOS: Image distortion correction

Part Number: TDA Tool/software: TI-RTOS Hi, I want to correct the image distortion of fisheye lens.I've got the internal parameters and distortion parameters of the lens.I don't know how to call the Remap and Merge Applet. Thanks!

To do this, you will need 2 things: 1. Convert the lens parameters to LDC look up table compatible with TI ISP format. 2. Package the LUT and other LDC parameters in a tuning plugin compatible with TI software. This can be done by TI's ISP tuning tool. If you don't have access, please request it through your TI representative.

Hi Yulin, You may refer to the link below for LDC tuning e2e.ti.com/.../2435557 tuning#2435557

Hi， Thank you very much for your reply. I can get the remap matrix of my camera, that is, the coordinate mapping matrix of the current image and the image after distortion correction.I tried to call remapmerge link, but it failed. How do I use link remapmerge to correct image distortion? Mary

Hi Mary, Which target device you want to use the remap link on ? It is tda2x or tda2+ ? The remap link was originally designed to be used for stereo-vision use-case so it expects two input queues for left and right images. Is your use-case for stereo or mono-camera ? regards, Victor

Hello Mary, Let me know if you still have any issue with that or we will close the ticket. Thanks. regards, Victor

Ticket Name: Linux/TDA2: Print Statics is not showing results about A15 core

Part Number: TDA2 Tool/software: Linux Hi Everyone, I am running linux platform VSDK 3.4 on TDA2XX ,Usecases and all are working fine without any hassles . However when I try to print performance statics after every usecase ("P" in the console) I am not getting logs usage statics on A15 core and it starts from DSP1 only . How can I get A15 core usage statics or is there any limitations in VSDK3.4 . Regards , Surendar

Hi Surendar, Linux itself provides multiple tools to display the A15 load (such as top, mpuload etc.). Thus, the print-statistics option on VSDK doesn't record the load on A15. You may find this thread useful. e2e.ti.com/.../709101 Regards Shravan

Ticket Name: RTOS/TDA2: No result for new use case

Part Number: TDA2 Tool/software: TI-RTOS Hi, we reference "vip_single_cam_lane_detection" and "null_src_dec_display" two use case and create a use case we call "null_src_lane_detection" Now, we reference "null_src_lane_detection" and "tidl_OD" two use case for our new use case I got the output below,but It looks have no result Can you tell us where is wrong? BR Allen

Hi Allen, Please verify if all the usecase and algo parameters are set . As the default usecase works there will be no issue in algo or framework, Please re verify the usecase Regards Chetan.M

Hi, I think I set all parameters I can run these two use cases separately but when I integrate these two use cases It have no result Is there anything I didn't notice? BR Allen

Can you please send the usecase flow what is all connected in the chain

Hi The below document is the use case I create chains_tidlODPrimax.txt UseCase: chains_tidlODPrimax

NullSource -> Decode -> VPE -> Dup -> Merge_alg

//TIDL_OD
Dup -> Alg_tidlpreproc (A15)

Alg_tidlpreproc (A15) -> Alg_tidl_Eve4 (EVE4)

Alg_tidl_Eve4 (EVE4) -> Merge_OD (DSP1)
Merge_OD (DSP1) -> Alg_tidl_Dsp (DSP1) -> Merge_alg

//LD
Dup -> VPE_LD -> Alg_ImagePreProcess (EVE1) -> Alg_ImgPyramid -> Alg_LaneDetect (DSP1) -> Merge_alg

//Display
Merge_alg -> Sync_alg (DSP1) -> Alg_ObjectDraw (DSP1) -> Display_alg

Can you verify the output of each algorithm , And also the alg_draw parameters Regards Chetan.M

Hi, Can you explain it in more detail? So, Is the problem occurred in the flow below? the pic below is the linking flow Is it has any problem?

Hi, Have any update? BR Allen

Allen , can you print the usecase stats 'p' and share it , Not able to suspect on the issue with the available inputs. Regards Chetan.M

Hi, It is the use case stats below 2438.session.log BR Allen

I see many times there are complete frame drops , Some times there is output but not consistent can you share the img file of the usecase . ? Regards chetan.M

Hi, It is the img file of our use case below BR Allen

Hi, Have any update? Is our flow wrong? BR Allen

Hi Allen , What is the load of each core , Is the system overloaded and dropping the frames . Do you have a local TI FAE .? So that we can arrange for a call and see how we can debug further .? Regards Chetan.M

Hi,Chetan Our FAE told to us we can't use the flow below is it really? he told us to another flow but I got errors after we try We'll post a new question for the error but, we want to know the answer about this. Is really true we can't use this flow for our customized use case?

Hi, Have any update? Is really true we can't use this flow for our customized use case? BR Allen

Allen , We will need to debug and find why the usecase is not up , There can be timing issue which is causing algo not to update . Can you try reducing the fps of read to 5 and try . Regards Chetan.M

Hi, Chetan I am not getting your answer. Can you please elaborate? BR Allen

Allen, In the usecase there are multiple paths from source (file read) to display, One of the path operates at lower fps then the frames are dropped , If you change the sync threshold to a high value then sync link will not synchronize the frames and hence it might be dropping many frames. We can debug this issue with a lower pfs , Reduce the read FPS to 5 and try running the usecase . Regards Chetan.M

Hi, Chetan We try to reduce the read FPS to 5 but we got the same result Is right what I did? It is the use case stats below 5008.session.log BR Allen

Hi, Chetan Have any update? If we change something setting wrong, please tell us BR Allen

No the settings look correct, In this usecase many links are utilized and there might be delay in some links which is causing the usecase to fail , You will have to debug this and route cause the slower link Regards Chetan.M

Hi Allen, You will have to debug each path of the usecase by adding a null terminator in each path and check the output. Then keep the entire usecase running bypassing the algo and ensure chain is up Regards Chetan.M

Hi, Did you able to resolve your issue. can you close this thread if resolved. Regards, Anuj

Ticket Name: TDA2SG: TDA2SG EMIF1 ECC

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2, AM5728 The current ECC architecture of aligned cache line writes, on EMIF1, (for TDA2SGBRQ (AM5728)) from only the core initiators (no IO initiators supported) is to limiting and not able to support the memory interface access schemes we have implemented. Is there a form, fit and function TDA2 device (pin compatible) supported by TI that would support non-aligned cache line writes from both core and IO initiators? I am getting the above information on ECC scheme for EMIF1 from Errata i922

Hi, Dean Hogle, Check this thread if it can help: Regards, Mariya

Hi Mariya- The link you gave me is my issue that Barend (FAE TI) told me to enter into this portal. Based on the link only quanta sized lines (full cache lines) can be written with ECC and only from ARM and DSP not IO. This is our issue, we want to have the ability to carry ECC on the DDR interface from all initiators and not be restricted to full cache line writes, meaning we need the capability to do read/modify/writes. Is there pin compatible TDA2 solutions that provide this solution? or other options? Thanks Dean

Hi Dean, can you check if this application report can help you: www.ti.com/.../sprac42a.pdf Regards, Yordan

Hi Dean, Read modify write with ECC enabled is not supported on TDA2xx device. You can use TDA2Px SoC which has a version that is pin compatible with TDA2xx. Regards, Rishabh

Review of the sprac42a App note confirms the short comings of the EMIF 1 ECC implementation but does not resolve or help my initial request which is a pin compatible replacement or other options. Thanks Dean

Hi Dean, As I stated in my previous reply you can see TDA2Px-ABZ which is pin compatible with TDA2xx and supports ECC with read modify write functionality. Regards, Rishabh

HI Rishabh- Can you confirm if the the TDA2Px-ABZ supports ECC with RMW from all memory sources (core and IO initiators)? Thanks Dean

Hi Dean, If the ECC referred here is EMIF ECC then the answer is yes. Regards, Rishabh

Rishabh- I did a quick comparison of the TDA2XX datasheet to the TDA2Px and it appears that secure boot and ISS are additional features and besides that the chips are identical, can you confirm? Is there a app note or white paper that documents this that you can share with me? Do you have any information on pricing, is the TDA2XX and TDA2Px on par with each other? Thanks Dean

Hi Dean, These are pin compatible chips, not identical. TDA2Px has more features/IPs. Please contact TI FAE for pricing. This information is documented in chapter 1 of TDA2Px TRM: www.ti.com/.../spruif0a.pdf. Regards, Rishabh

Hi Rishabh- The link you provided does not allow me to see the .pdf, says document not found. Can you update link. Also is there an app note that documents the ECC implementation for the TDA2Px that you can share? Thanks Dean

Hi Dean, Can you try this link: www.ti.com/.../getliterature.tsp From implementation perspective everything is same as TDA2xx. Only addition is RMW bit (REG_RMW_EN) that needs to be enabled in EMIF_ECC_CTRL_REG. Unfortunately the ECC app note is not updated for TDA2Px implementation. Regards, Rishabh

Dean, It seems that "." is getting attached to the hyperlink at the end. Kindly remove it and try: www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=SPRUIF0&fileType=pdf Regards, Rishabh

Hi Dean, I haven’t heard back from you, I’m assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out) Regards, Rishabh

Hi Rishabh- The TDA2P appears to have the ECC coverage we need. I am in the process now of understanding the production availability of the device. Thank you for your help/support on this.

Hi, Thanks for the confirmation. Regards, Rishabh

Ticket Name: TDA2SX: How to change the DDR memory size on the tda2?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2, Two DDRs are used in our own tda2 board, each of which is 2GB, with a total of 4GB. It is found that the default memory node in DTS is 1GB. After changing it to 4GB, it is found that the kernel cannot be started. How can I use all 4GB of memory?

Hi, Can you please let me know on how you confirmed on the total of 4GB? Do you have a custom board or you are using standard TI TDA2SX EVM? The max that can be supported can be upto 4GB but I believe on the TI Board it is 2GB DDR. Can you share the links on 4GB DDR? Best Regards, Keerthy

Ticket Name: Linux/TDA2E: multiple video nodes possible on usb webcam(g_webcam)?

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Tool/software: Linux Hi Guys, Scenario: If i have multiple video source with different nodes say(/dev/video0...n) and i'm using usb webcam gadget mode. 1-> Is it possible to assign multiple video node to single usb port? or Do we have to unload webcam driver for assigning different node everytime? 2-> what about switching of video nodes. is it possible and how much time it can take to switch between video nodes? regards, Ganesh

Hi Ganseh, I have forwarded your question to the expert. Regards, Yordan

Hi Yordan Kamenov , Is their any update? regards, Ganesh

Hi Ganesh, I have pinged them. Regards, Yordan

Hello, Just to clarify This question is comepletely related to V4L2 and USB It does not deal with the capture interfaces on the TDA2 platform. Now to answer your question, V4L2 USB driver would register video devices for as many webcams connected. The device numbers change only if you disconnect and reconnect cameras. You can always find the right device by-path /dev/v4l/by-path This way, you can identify a specific device without worrying about thr order of probing. I hope this helps Regards, Nikhil D

Hi Nikhil Devshatwar,  V4L2 USB driver would register video devices for as many webcams connected.
 The device numbers change only if you disconnect and reconnect cameras. What you are telling is for usb host mode right?. what i'm asking is for usb device in uvc gadget mode. Just to clarify: I'm using VISION_SDK_02_12 with kernel 4.4. I have TDA2Ex EVM board, on that board two cameras are mounted on two CSI bus. Now i want webcam gadget mode i.e EVM as device mode. As their are two camera so their will be two device node will be created(say /dev/videoX & /dev/videoY) when we load camera driver. So to make EVM as webcam gadget we load usb_f_uvc.ko it will take only one video device node right? 1-> how can we make it possible to assign multiple camera output to single usb port by using usb_f_uvc(configfs). so that host side i can access multiple video device node? 2-> If not multiple video device node on single usb port then one camera output at a time? switching using configfs? but then how can we assign different camera output every time? regards, Ganesh

Hello, your question is quiet confusing. First, the usb_f_uvc driver does not USE existing v4l2 CAPTURE device. It rather registers a NEW v4l2 OUTPUT device. Which means, application is supposed to dump buffers into it which internally sent from USB as a webcam gadget. The v4l2 device related to the USB port is a OUTPUT device. It is completely irrelevent to the v4l2 capture device registered from the CAL/CSI drivers. You need to write an application which takes data from v4l2 capture device (you can choose video1 or video2 from the CSI device) and then feed this into the v4l2 output device (video3 registered from USB driver) Application will have full control to decide and switch between the capture devices What you want is a USB gadget driver which somehow uses an existing V4L2 driver to send data over USB This sounds like application code, so I am not sure if this even exists as a kernel driver. I hope I clarified your concerns. Regards, Nikhil D

Hi Nikhil Devshatwar , Thanks for your reply, i just needed that clarification only. I was looking for any mechanism available at kernel side to switch with your answer it is clarified their is no such mechanism at kernel side. uvc-gadget is a test application which can be used for testing uvc gadget webcam for single v4l2 capture to v4l2 output. regards, Ganesh

Ticket Name: RTOS/TDA2: TDAx ADAS SOCs Forum

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, We refer the ticket http://e2e.ti.com/support/arm/automotive_processors/f/1021/t/709147 to modify DVP data width to 12 bits (original are 8 bits). But HDMI output will get black screen, could you please check for us? We data flow as below: Please find attachment to get modify code. VIP receive 12 bits image.rar We upload real output record to YouTube as below: >> TDA2 receive 12bits YUV by AVNET suggestion : https://www.youtube.com/watch?v=ntxlkS3cra4 >> TDA2 receive 8bits YUV : https://www.youtube.com/watch?v=fk_aExrFOZk Many thanks.

Hi, Note that the display doesn't support 16-bit RAW input. Since we are programming 16-bit RAW video format to VIP, the input format to the display needs to be changed to YUV422. Also did you get any error message on the UART/CCS console? Regards Sivaraj R

Hi Sivaraj, Thanks for your reply. We image sensor output format is YUV422 and DVP 12 bits. But TDA2 need separate two component to receive more than 8 bits data. (8 bits/component) Now we receive YUV422 frame by DVP 12 bits but we just see half frame from HDMI output. (Please refer before create ticket : e2e.ti.com/.../2656778 As i know VPS storage 12bits data seem like below: Component 1(data 0~7) : xxxxxxx Component 2(data 8~15) : 0000xxxx (12~15 zero pending ) but how to setting output 2 component data to HDMI? Have any use case or sample code can refer if we needs receive?

Hi, Your understanding of 16 bit storage in memory by VIP is right. Did you dump the VIP frame to a file through CCS and then analyze the image is proper with external viewer? Note that the DSS supports only 8bit YUV data. So the 16-bit YUV should be first converted to 8-bit data. If you really need 12-bit input then, you need to convert this in CPU (DSP). If not then you can configure the VIP to receive only the MSB 8-bit data. Regards Sivaraj R

Hi Sivaraj , Thanks for your reply.

Ticket Name: Linux/TDA2: Usecase problem with logs over network

Part Number: TDA2 Tool/software: Linux Hi, If somebody could help me with logs over network when linux runs on A15.. I am using PROCESSOR_SDK_VISION_03.03.00.00 on our custom board (RT-RK ALPHA board ). Trying to have logs over network (which I have now) and to run some of the Use-Cases, also over network. I have changed defaults.mk file, where now logs over network are enabled and logs over uart are disabled.. Also, there was no files like network_cons_tsk.c and network_cons_ipc.c linux, so i made them (sendig those as atachment), as proper makefile in same directory.. I looked in RTOS files and made conclusion that there are also 2 more functions that should be implemented in osa_ipc_que.c file (those are: Int32 OSA_ipcQueWriteString(OSA_IpcQueHandle * handle, const char pString[]); and Int32 OSA_ipcQueReadString(OSA_IpcQueHandle * handle, char pString[], UInt32 *strSize);) Problem appeared is that Use-Cases do not start every time i try to run them (when logs go over UART everything works fine). I have menu, but on the command to start UC nothing happends.. UC starts in one of 10 or more attempts, so, could you help me to figure out why is that happening? Thx a lot, Best regards, Nebojsa 1200.files.zip

Hello Nebojsa, Thanks for providing all details, this is useful for debug. I will check and let you know if any issues in porting the console tool. Meanwhile can you please try reducing priority of console threads instead of OSA_THR_PRI_DEFAULT? BTW can we please debug this issue on original thread? I see these two are exactly same. We can close this one.

Hey, Thx for your quick answer. I'll try your suggestion (to reduce priority of console threads) and will keep you informed about the results. Yes, we can close this thread and continue to work in original one.. Regards, Nebojsa

I'm continuing to write in the main thread e2e.ti.com/.../714772

Ticket Name: RTOS: What is SystemLink_init function for?

Tool/software: TI-RTOS Hi, I couldn't understand the role of SystemLink_init function. Is it different with some links like NullsrcLink? In the source code, the comment says 'Initializes the linkObj and creates the task for SystemLink_tskMain'. Does each core have only one linkObject? Is there any guide for this question? Regards, Yoo.

Please provide more details to help us provide appropriate guidance: 1. What device and what version of Processor SDK RTOS are you using . What HW platform are you testing on. 2. The APIs that you are referring are not commonly used by the drivers and RTOS ...Please indicate what component and what source file you are referring to. Regards, Rahul

Ticket Name: TDA2EXEVM: UTILS: MBX: Utils_mbxSendCmd(): Msg Alloc Failed (0)!!!

Part Number: TDA2EXEVM Hi sir, I ran tidlOD use case with a 1280x720 resolution model. I modified resolution relating part in tidlOD.c (such as display, grpxSrc) to fit my model. I also modify vpeLink_drvCommon.c according to this thread (). The detected process will be hung after starting detection process for a few seconds. 1. Here is the error message when detected process stops, [DSP1  ]     46.671628 s:  Assertion @ Line: 782 in tiop/tiopLink_algPlugin.c: freeId != -1 : failed !!!
[DSP1  ]    169.284572 s:  UTILS: MBX: Utils_mbxSendCmd(): Msg Alloc Failed (0)!!!
 2. Here is the inBufStats status in AlgorithmLink_tiopProcess() before error, [2020-03-12 17:29:38.765] [DSP1  ]     80.356981 s: inBufStats 0 1
[2020-03-12 17:29:38.796] [DSP1  ]     80.357042 s: inBufStats 1 1
[2020-03-12 17:29:38.796] [DSP1  ]     80.357042 s: inBufStats 2 0
[2020-03-12 17:29:38.796] [DSP1  ]     80.357073 s: inBufStats 3 0
[2020-03-12 17:29:38.796] [DSP1  ]     80.357073 s: inBufStats 4 0
[2020-03-12 17:29:38.796] [DSP1  ]     80.357073 s: inBufStats 5 0
[2020-03-12 17:29:38.796] [DSP1  ]     80.357103 s: inBufStats 6 0
[2020-03-12 17:29:38.859] [DSP1  ]     80.453760 s:  Assertion @ Line: 782 in tiop/tiopLink_algPlugin.c: freeId != -1 : failed !!! If I'm not misunderstanding, the buffer 2-6 are still available, but the error (tiop/tiopLink_algPlugin.c: freeId != -1) shows there is no free buffer can be used. 3. All things will be fine if I run with 768x320 model. Can you suggest me how to fix it? Thank you, Gary

Hi, Can you share the complete logs in text file? Thanks Gaviraju

Hi Gaviraju, Here is the debug log 4645.logs.txt I found that when the error happened, the tiop buffer couldn't be released properly. And this was due to incorrect bufferID in tiopReleaseLockedBuffer() ( tmpId = -2010018329) This error will usually happen when the capture sense changed. Please suggest me what can I do next. Thank you, Gary

Hi, Any suggestion? In my further testing , the tmpID should be positive. [2020-03-16 13:08:36.081] [DSP1  ]     33.191453 s: released tiopReleaseLockedBuffer in tmpID 2284948968
[2020-03-16 13:08:36.112] [DSP1  ]     33.191484 s: released tiopReleaseLockedBuffer out tmpID 2284948967 Thank you, Gary

Hi, You mentioned, "All things will be fine if I run with 768x320 model". So remove all your changes did for 1280x720 model then run the lowe resolution model( < 768x320) & let's see you will face the same issue or not. Thanks Gaviraju

Hi, >> ...let's see you will face the same issue or not No, it runs correctly when removing changes. Can you advise the correct way to run tidlOD usecase with a 1280x720 model? Where should I change? Thank you, Gary

Hi Gaviraju, I temporary solved this issue by lower deploy.prototxt "keep_top_k" value from 20 to 10. But 10 objects are not enough for my application. So I still need your help to find the root cause. How to deal with 20 or more objects at a time in my case? Do you have any idea? Thank you, Gary

Hi, Please share your input files with us, we will debug the issue & get back. Thanks Gaviraju

Hi Gaviraju, I've solved this issue, thank you for your help Gary

Thanks for the update!

Hi, Can you share your solutions please? I have the same problem.

Ticket Name: TDA2EVM5777: TDA2EVM5777 NAND flash & NOR flash

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello I study form the EVM schematics that data pins of nand flash & nor flash is all connected to SW2 & SW3 in page23, which will be set to pull down by 10k or pull up by 1k. why the data pin can be pull up by 1k? is there no problem when SoC is communicating with nand or nor flash? data pin can be pull low when communicating although it is strongly pull up by SW2 or SW3? thank you~

Hi, EVM has so many switches, jumpers, and muxes so that as much as possible of the SoC features can be tested or debugged. For the field design, much of the switches will not be needed, therefore much of those kind schematics will not be seen. In most of the cases, only the pull-ups, only pull-downs, or none will be on the board. Particularly for the overriding with a 1k the 10k, yes, it is neither an efficient nor good idea, but it is simple and it is working okay in practice for an EVM. Regards, Stan

Hello If we use just only eMMC & SPI flash,could we remove SW5 & U57? What is the purpose of U57? read the SW5 status by software? thank you~

Hi, Typically it is rare to need in real life design: - switches - some that are needed can be replaced with jumpers or resistor jumpers. typically that are the sysboot pin configs and some user configs if any. - muxing ICs - logic ICs - GPIO expander ICs (like U57) Please note that everything depends on design needs, peripheral needs and many other decisions that should be taken during design time. Regards, Stan

Hello We have no need of GPIO expander(U57) bu we don't know what is the purpose of U57 in EVM what is the function of U57 in EVM? for SoC to read SW5's status? thank you

For P10-P17, I think they only monitor SW5 for software. However every signal must be evaluated individually. For example, P17 (FORCE_EMU) is a signal to software only. The other 7 go directly to hardware muxes to do the job, and software can monitor them through U57. P0 (SEL_GPMC_AD_VID_S0), on the other hand, is controlled THROUGH software (output from U57) . Similar is for P3-P5, however for P3, P4, there are some notes on the diagram saying it is not supported for them in software. As I already recommended - every signal must be evaluated individually. Regards, Stan

Hi Stan I have no need to monitor the SW5 by software,and there is no need to use RU33,RU88,RU89 cause I removed them from our design. So I don't need the P0 of U57, I didn't use USB function, so I don't need P1&P2,I didn't use I2C3 ,CAN2 & Ethernet, so I don't need P3&P4. I control the MMC_PWR directly from GPIO pin, so I don't need P5. So I can remove the U57 directly,right? thank you~

Sure. I hope you will manage to remove as much as possible of those discrete muxes and logic. TDA2 contains a sophisticated internal muxing covering most of the use-cases in the field. Regards, Stan

Ticket Name: TDA2HF: Power consumption for different Ti SoC

Part Number: TDA2HF Other Parts Discussed in Thread: TDA2SX, Hi, We made TDA2Sx custom board and we ported all our use cases into TDA2Sx custom board and it consumed more power. We want to check with other Ti SoC's, So we want to know the power consumption of different Ti SoC's. please share the comparison of power consumption between below SOC in terms of percentage as compared to TDA2sx TDA2Px TDA2HF TDA3x Please share this comparison irrespective of use cases, just power on and boot with all cores in that SOC enabled. Thanks & Regards, Sankar.

Sankar, In very rough numbers ... TDA2Px is 20 to 50% higher power than TDA2x, and TDA3x is ~30 to 50% of TDA2x. TDA2HF is the same device as TDA2S with a different mix of cores enabled and different frequencies supported. Regards, Kyle

Hi Kyle, Thanks for your valuable information. Thanks & Regards, Sankar

Ticket Name: TDA4 different output between PC and platform

Other Parts Discussed in Thread: TDA2 Hi, I got the different output between PC and latform in TDA4. This model can also work normally in TDA2. The architecture is look like the figure below. The difference is begin with third layer. This layer is merged by convolution and relu. layer { name: "down2/bd" type: "Convolution" bottom: "down2/bn" top: "down2/bd" param { lr_mult: 0.0 decay_mult: 0.0 } convolution_param { num_output: 24 bias_term: false pad: 1 kernel_size: 3 group: 24 stride: 2 } } layer { name: "down2/bd_relu" type: "ReLU" bottom: "down2/bd" top: "down2/bd" } There are some files about the net and param in the last. I ask you a favor for making output become the same between PC and TDA4 platform. Thanks, Tedtidl_net.rartidl_param.rar

Usually, convolution and Relu layers are merged together. When you say PC, is it framework or TIDL host emulation? Do you see difference in layer level outputs? You can refer to section "steps to debug" in TIDL documentation to do layer level debug / difference analysis between framework and TIDL Can you please send zip files instead of rar files? - Subhajit

Hi Subhajit: The PC I said, which is meaning the TIDL host emulation. I've already see the difference in layer level outputs by setting writeTraceLevel = 3 and check the trace files. The difference is start at third layer. Thanks, Ted tidl_net.zip tidl_param.zip

Hi Ted, Can you share the deploy.prototxt, import and infer config files for me to reproduce the issue. Regards, Rishabh

Hi Rishabh: Here is the files you need. Thanks, Ted conv_issue.zip

Hi Ted, The model you have shared has a parameter called "blur_kernel" and cannot be imported with TIDL import tool I get an error message Error parsing text-format caffe.NetParameter: 181:16: Message type "caffe.ConvolutionParameter" has no field named "blur_kernel" Can you please share the model using which you are able to reproduce the mismatch issue with TIDL. Regards, Rishabh

Hi Rishabh: Sorry about the wrong files. Here is the files after fixing. Thanks and Regards, Ted conv_issue.rar

Hi Ted, TI made a new release for PSDKRA: http://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/index_FDS.html Can you confirm if you see the issue with latest release. Regards, Rishabh

Ticket Name: TDA2/TDA3: Is there any Power Consumption Spreadsheet for TDA2x and TDA3x processors?

I need to find a suitable processor for a new project and I need to know their power consumption info. But I cannot find anything tells me about it, can anyone help?

Hi, I have forwarded your question to a power expert for comment. Regards, Yordan

Same question for me...

Hello I would be interested in power figures in srandard kind of benchmarks (idel, video encode/decode, audio processing, GFX benchmark). Whom should I contact ? Thanks

Ticket Name: TDA2SX: VOUT spread spectrum feature

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hello Team, My customer asked that Spread spectrum feature is supported on VOUT1 port due to EMI issue at VOUT1 PCLK frequency. In TDA2 TRM (TDA2x_SR2.0_SR1.x_NDA_TRM_vAD.pdf), there is a register (PLL_SSC_CONFIGURATION1) which can enable SSC feature on DPLL_VIDEO1 as below. On the other hand, it is noted that "SSC feature is not supported." Customer would like to know that they can use SSC feature on DPLL_VIDEO1 by enabling "PLL_SSC_CONFIGURATION1[EN_SSC]" register. How it would work when EN_SSC is enabled?

Hi Lloyd, SSC was not tested for one reason or another. Your customer may try it and use it if everything is fine, but TI will not be able to support them. Regards, Stan

Ticket Name: RTOS/TDA2: Build VisionSDK and have the Error -1073740791

Part Number: TDA2 Tool/software: TI-RTOS Hi,team I build VisionSDK and have some errors.The building steps are as below and could you give me some suggestion?Thanks so much. == (1)I download,test 2 versions and install Vision SDK to windows PROCESSOR_SDK_VISION_03_06_00_00_setupwin.exe PROCESSOR_SDK_VISION_03_05_00_00_setupwin.exe (2)Use System administrator(cmd) or Cygwin to build TI-RTOS (3) Go inside the directory PROCESSOR_SDK_VISION_03_xx_xx_xx\vision_sdk\build (4) Open file \vision_sdk\build\Rules.make and set required config MAKECONFIG=tda2xx_evm_bios_all (5) Set environmental variables to PATH variables : PATH value : C:\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\os_tools\windows\xdctools_3_32_01_22_core;%PATH% (6) Refer to "/vision_sdk/build/tools_path.mk" and download/install A15 toolchain to C:\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\cg_tools\windows\gcc-arm-none-eabi-4_9-2015q3 C:\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\cg_tools\linux\gcc-arm-none-eabi-4_9-2015q3 than the environmental variable is set C:\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\cg_tools\linux\gcc-arm-none-eabi-4_9-2015q3\bin;C:\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\cg_tools\windows\gcc-arm-none-eabi-4_9-2015q3\bin;C:\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\os_tools\windows\xdctools_3_32_01_22_core;%PATH% (7) Build first time and run the below sequence of commands >> gmake -s -j depend (8)But there are below errors: ... ... # Archiving tda2xx:ipu1_0:release:vps_devices into C:/PROCESSOR_SDK_VISION_03_06_00_00/ti_components/drivers/pdk_01_10_02_07/packages/ti/drv/vps/lib/tda2xx/m4/release/vps_devices.aem4 ... gmake[3]: *** [vps_devices] Error -1073740791 gmake[2]: *** [pdk] Error 2 gmake[1]: *** [pdk] Error 2 gmake: *** [depend] Error 2 Best Regards, Jacob Lin

Hi Jacob, Do you get the same error with "gmake -s depend"? Regards, Rishabh

Dear Rishabh I still get the same error with "gmake -s depend".Could you have other ideas about the problem? Thanks. ... ... ... # Archiving tda2xx:ipu1_0:release:vps_devices into C:/PROCESSOR_SDK_VISION_03_06_00_00/ti_components/drivers/pdk_01_10_02_07/packages/ti/drv/vps/lib/tda2xx/m4/release/vps_devices.aem4 ... # gmake[3]: *** [vps_devices] Error -1073740791 gmake[2]: *** [pdk] Error 2 gmake[1]: *** [pdk] Error 2 gmake: *** [depend] Error 2 Best Regards, Jacob Lin

Dear Rishabh I still get the same error with "gmake -s depend".Do you have other idea about the problem?Thanks. ... ... ... # Archiving tda2xx:ipu1_0:release:vps_devices into C:/PROCESSOR_SDK_VISION_03_06_00_00/ti_components/drivers/pdk_01_10_02_07/packages/ti/drv/vps/lib/tda2xx/m4/release/vps_devices.aem4 ... # gmake[3]: *** [vps_devices] Error -1073740791 gmake[2]: *** [pdk] Error 2 gmake[1]: *** [pdk] Error 2 gmake: *** [depend] Error 2 Best Regards, Jacob Lin

Hi Jacob, Can you start cmd as an administrator and try. If you are already running as admin then try vice versa. I did some search on internet for file system error 1073740791 and suggestions pointed to issue with permissions/file system. Regards, Rishabh

Dear Rishabh Sorry for late response and I solved the issue until 5 hours ago. (1) Run as administrator for cmd and cygwin: still failing (2) Disable the read only for SDK folder : still failing (3) Release all permissions/file system : still failing (4) CHKDSK -r -f: still failing (5) Dism /Online /Cleanup-Image /CheckHealth : still failing (6) Dism /Online /Cleanup-Image /ScanHealth : still failing (7) Dism /Online /Cleanup-Image /RestoreHealth : still failing I directly change the PC and repeat the steps. The RTOS is built successfully. Maybe my HDD or file system is broken, I still don't know real reason. Thanks so much for your help. Best Regards, Jacob Lin

Hi Jacob, Glad that the issue is resolved. Thanks for the update. Regards, Rishabh

Ticket Name: Linux/TDA3XEVM: Building eve_test_dl_algo.out for X86 platform on UBUNTU 16.04LTS

Part Number: TDA3XEVM Tool/software: Linux Hello, My question refers to visionSDK tools on linux UBUNTO 16.04. We are trying to import different Caffe networks using tidl_model_import.out tool. idl_model_import.out was successfully built by us and we manage to debug this tool, but it seems that eve_test_dl_algo.out is opaque. I managed to build eve_test_dl_algo.out for eve - based on the pdf. There exists an eve_test_dl_algo.out .exe utility, which I managed to run through wine, and with that - the imported CNN network for TI works. However, the problem is that I want to build eve_test_dl_algo.out for X86 UBUNTU16.04 platform - a version that does not need wine, and that we can debug. We need to research the operation of this tool. 1-Is it possible to build and debug this tool? If so, where are the instructions? 2-Where can I find documentation regarding the functionality of this tool? Thanks you

Hi, You can find the build steps in section 3.6.3 ( Building TIDL reference executable ) in the TIDL user guide. But you need source code access to build this. Thanks, Praveen

Praveen, Thank you for your prompt response. I found this section in the pdf file - based on the reference provided by you. It seems that I followed the steps in this section - with some modifications: gmake TARGET_PLATFORM=PC TARGET_BUILD=release CORE=eve RUN_REF_FOR_STATS=1 all ARP32_TOOLS=/home/yoav/PROCESSOR_SDK_VISION_03_06_00_00/ti_components/cg_tools/linux/arp32_1.0.7 XDAIS_PATH=/home/yoav/PROCESSOR_SDK_VISION_03_06_00_00/ti_components/codecs/framework_components_3_40_02_07/fctools DMAUTILS_PATH=/home/yoav/PROCESSOR_SDK_VISION_03_06_00_00/ti_components/algorithms/REL.DMAUTILS.00.08.00.02/dmautils, But got this: /usr/bin/ld: ../../ti_dl/lib/eve/release/tidl_algo.lib(tidl_alg.obj): Relocations in generic ELF (EM: 143) /usr/bin/ld: ../../ti_dl/lib/eve/release/tidl_algo.lib(tidl_alg.obj): Relocations in generic ELF (EM: 143) /usr/bin/ld: ../../ti_dl/lib/eve/release/tidl_algo.lib(tidl_alg.obj): Relocations in generic ELF (EM: 143) /usr/bin/ld: ../../ti_dl/lib/eve/release/tidl_algo.lib(tidl_alg.obj): Relocations in generic ELF (EM: 143) /usr/bin/ld: ../../ti_dl/lib/eve/release/tidl_algo.lib(tidl_alg.obj): Relocations in generic ELF (EM: 143) /usr/bin/ld: ../../ti_dl/lib/eve/release/tidl_algo.lib(tidl_alg.obj): Relocations in generic ELF (EM: 143) /usr/bin/ld: ../../ti_dl/lib/eve/release/tidl_algo.lib(tidl_alg.obj): Relocations in generic ELF (EM: 143) /usr/bin/ld: ../../ti_dl/lib/eve/release/tidl_algo.lib(tidl_alg.obj): Relocations in generic ELF (EM: 143) /usr/bin/ld: ../../ti_dl/lib/eve/release/tidl_algo.lib(tidl_alg.obj): Relocations in generic ELF (EM: 143) /usr/bin/ld: ../../ti_dl/lib/eve/release/tidl_algo.lib(tidl_alg.obj): Relocations in generic ELF (EM: 143) So, it seems that something with my installation is missing or wrong. PROCESSOR_SDK_VISION_03_06_00_00_setuplinux.bin This is the visionSDK. Should I use some other repository or installation tool? Thanks, Yoav

Hi Yoav, As mentioned in the section 3.6.3. "The tidlStatsTool can be built using the TIDL source code". Do you have access to TIDL source code? Thanks, Praveen

Thank you Praveen, It seems that the code I have is not enough. Installing VisionSDK using PROCESSOR_SDK_VISION_03_06_00_00_setuplinux.bin - provides me with partial code base. I can create and modify algorithms and algorithm aids (for TIDL as well), build tests and build my version of AppImage. But, I can't build the utils. Trying to use BitBake to fully installed the sdk - failed because of problems with some recipes. With git://git.ti.com/tidl/tisl-utils.git - I managed to build the import tool - but I'm not sure that it is an official repository. What should we do in order to get access to the full code? Again, thank you for your prompt reply. Yoav

Hi Yoav, You may have to contact your local TI FAE to get access to full code. Thanks, Praveen

Thank you for your help Praveen. We will leave this issue in the meantime.

Ticket Name: Linux/TDA2: compile PROCESS_SDK_3_2_0_0 appimage error

Part Number: TDA2 Tool/software: Linux my host is ubuntu18.04 and I compile PROCESS_SDK_3_2_0_0 step : 1, make depend 2,make vision_sdk -s -j8 3.make appimage the step 1 and step 2 have compile finished, when i make appime is fllow err: mono VSION_SDK/ti_components/drivers/pdk_01_08_01_06/packages/ti/boot/sbl_auto/tools//out2rprc/out2rprc.exe VSION_SDK/vision_sdk/binaries/apps/tda2xx_evm_bios_met/vision_sdk/bin/tda2xx-evm/vision_sdk_a15_0_release.xa15fg VSION_SDK/vision_sdk/binaries/apps/tda2xx_evm_bios_met/vision_sdk/bin/tda2xx-evm/vision_sdk_a15_0_release.xa15fg.rprc WARNING: The runtime version supported by this application is unavailable. Using default runtime: v4.0.30319 Unhandled Exception: System.TypeInitializationException: The type initializer for 'System.Console' threw an exception. ---> System.TypeInitializationException: The type initializer for 'System.ConsoleDriver' threw an exception. ---> System.Exception: Magic number is wrong: 542 at System.TermInfoReader.ReadHeader (System.Byte[] buffer, System.Int32& position) [0x0002b] in <8f2c484307284b51944a1a13a14c0266>:0 at System.TermInfoReader..ctor (System.String term, System.String filename) [0x00065] in <8f2c484307284b51944a1a13a14c0266>:0 at System.TermInfoDriver..ctor (System.String term) [0x00058] in <8f2c484307284b51944a1a13a14c0266>:0 at System.ConsoleDriver.CreateTermInfoDriver (System.String term) [0x00000] in <8f2c484307284b51944a1a13a14c0266>:0 at System.ConsoleDriver..cctor () [0x00062] in <8f2c484307284b51944a1a13a14c0266>:0 --- End of inner exception stack trace --- at System.Console.SetupStreams (System.Text.Encoding inputEncoding, System.Text.Encoding outputEncoding) [0x0000a] in <8f2c484307284b51944a1a13a14c0266>:0 at System.Console..cctor () [0x000a8] in <8f2c484307284b51944a1a13a14c0266>:0 --- End of inner exception stack trace --- at out2rprc.Program.Main (System.String[] args) [0x00043] in <00b942d828114f90a31f2820d23dca05>:0 [ERROR] FATAL UNHANDLED EXCEPTION: System.TypeInitializationException: The type initializer for 'System.Console' threw an exception. ---> System.TypeInitializationException: The type initializer for 'System.ConsoleDriver' threw an exception. ---> System.Exception: Magic number is wrong: 542 at System.TermInfoReader.ReadHeader (System.Byte[] buffer, System.Int32& position) [0x0002b] in <8f2c484307284b51944a1a13a14c0266>:0 at System.TermInfoReader..ctor (System.String term, System.String filename) [0x00065] in <8f2c484307284b51944a1a13a14c0266>:0 at System.TermInfoDriver..ctor (System.String term) [0x00058] in <8f2c484307284b51944a1a13a14c0266>:0 at System.ConsoleDriver.CreateTermInfoDriver (System.String term) [0x00000] in <8f2c484307284b51944a1a13a14c0266>:0 at System.ConsoleDriver..cctor () [0x00062] in <8f2c484307284b51944a1a13a14c0266>:0 --- End of inner exception stack trace --- at System.Console.SetupStreams (System.Text.Encoding inputEncoding, System.Text.Encoding outputEncoding) [0x0000a] in <8f2c484307284b51944a1a13a14c0266>:0 at System.Console..cctor () [0x000a8] in <8f2c484307284b51944a1a13a14c0266>:0 --- End of inner exception stack trace --- at out2rprc.Program.Main (System.String[] args) [0x00043] in <00b942d828114f90a31f2820d23dca05>:0 make[1]: *** [build_multi_core_image_gen.mk:147: all] Error 1 make[1]: Leaving directory 'VSION_SDK/vision_sdk/build/rtos/makerules' make: *** [Makefile:249: appimage] Error 2

Hi, We have not used this tool on ubuntu 18.04. Can you try ubuntu 14.04 or ubuntu 16.04. Regards, Rishabh

Ticket Name: RTOS/TDA2: encode link whether to support two instances

Part Number: TDA2 Tool/software: TI-RTOS I want to use two encode link in one chains, Can VSDK0304 supoot this?

Hi Default VSDK support only one instance of encode link. But encode link support multiple channels (upto 8 channels). So a single instance of encode link can be used to encode multiple video streams of same or different resolutions/codec type etc. regards, Shiju

hi,Shiju Thanks for support. As you said, the encode links support multiple video streams. Now I have four camera input, I want to use MJPEG to take pictures while I want to go to h264 encoded video. How could I do? could you give some suggestions about how to use this encode link？ thanks， Widic

Hi Widic This is what I understood as your requirement, please confirm? 1. You need to H264 encode of all 4 cameras 2. At the same time MJPEG encode to take snapshots (photos) for all cameras In this case you can first perform a dup for each input cameras into 2 streams (using dup link), capture (4ch) -> Dup do a merge link after dup, This will make the number of input streams to Enc link as 8. 0 & 4 for cam1 1 & 5 for cam2 2 & 6 for cam3 3 & 7 for cam4 Now ch0 set for h264 encode ch4 set for MJPEG (snapshot encode) similar config for all reaming 3 cameras Hope this would works for you regards, Shiju

Thanks,Shiju ,this solved my issue.

Ticket Name: TDA2SX: Does TDA2S support 2 Mega surrounded view cameras ?

Part Number: TDA2SX Because we are familiar with TDA2S plaftform and we developed mature product, TDA2S is cheaper than TDA2P, as we know TDA2P supports few CMOS sensors. if we give up integrated ISP, does TDA2S support 2 Mega surrounded view cameras ?

yes Regards Shashank

Would you please describe in details ? 1. Serializer and deserializer chip type: DS90UB960 ? it is MIPI interface, TDA2S does not support MIPI; 2. Serializer and deserializer transmission data rate: we used DS90UB934/DS90UB934 for 1280*720 resolution, transmission data rate of 2 Mega pixel will 4 times for 1280*720p resolution. Thanks,

1) You can use 933 serializer and 964 deserializer which allow data through parallel port VIP. You are correct in stating that TDA2S doesn't support MIPI. For the exact data rate you will have to reach out to the SERDES group , however it may be possible to reach 2 mpix with this serdes configuration (We may have to reduce frame rate if the b/w exceeds) My suggestion would be to use the TDA2P device even if you are not using the ISP since it allows for better interfaces. Regards Shashank

Ticket Name: RTOS/TDA2: IPv6 API header file

Part Number: TDA2 Tool/software: TI-RTOS Hello, When including the IPv6 support I am getting errorfor missing prototype for IPv6 interface functions. I have included netmain.h, servers.h & console.h. # Compiling tda3xx-evm:ipu1_1:release:utils_common: ndk/ndk_nsp_hooks.c "ndk/ndk_nsp_hooks.c", line 807: error: function "IPv6InterfaceInit" declared implicitly "ndk/ndk_nsp_hooks.c", line 858: error: function "IPv6InterfaceDeInit" declared implicitly Including ti/ndk/inc/stack/inc/ip6if.h causes variable undefined errors. error: identifier "IPV6HDR" is undefined error: identifier "PSEUDOV6" is undefined Which header file contains the prototypes for IPv6 APIs?

Prasad, You need to add the following include: #include <_stack.h> Best Regards, Gerardo

Ticket Name: TDA4VM: TIDL: How can I get Out Q values(scale factors) of layers after model import ?

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi, After model import in TIDL TDA2, we can get Out Q value from part of outArgs typedef struct { IVISION_OutArgs iVisionOutArgs; int32_t numOutBufs; int32_t dataQ[TIDL_NUM_OUT_BUFS]; } TIDL_outArgs;. Here is my question: How can I get Out Q values of layers in TIDL TDA4 after import? And is there any difference(like format or meaning of value) between Out Q values of TDA4 and TDA2? Thank you! Best regards. Kuanlin

Hi Kuanlin, If you enable in the inference config file: debugTraceLevel = 1 writeTraceLevel = 3 you'll see the scale value for each tensor being displayed in float. Please refer to section Feature Map Scale Analysis of Note that on TDA4x, the definition of TIDL_outArgs is: typedef struct { /** Common outArgs for all ivision based modules */ IVISION_OutArgs iVisionOutArgs; /** Number of output buffers */ int32_t numOutBufs; /** Scale factor for each output tensor */ float32_tidl scale[TIDL_NUM_OUT_BUFS]; } TIDL_outArgs; You can use the following C pseudo-code to convert each layer's output from integer to float: for (i=0;i<layerWidth*layerHeight;i++){ floatLayer[layerIdx][i] = ((float)intLayer[layerIdx][i]) / scale[layerIdx]; } On TDA2x, the formula is different since dataQ is the scale in Q8 format: for (i=0;i<layerWidth*layerHeight;i++){ floatLayer[layerIdx][i] = ((float)intLayer[layerIdx][i]) / (dataQ[layerIdx]/256.0); } regards, Victor

Hi, Victor: Thanks for your clear answer. It solved my problem! Regards, Kuanlin

Ticket Name: TDA2EVM5777: Object Detection Algorithm

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi, I have got tda2 application board and run the sample code. It's work. My question is if I want to change the algorithm of Object Detection where should I edit. I find the file path C:\PROCESSOR_SDK_VISION_03_00_00_00\ti_components\algorithms\REL.200.V.OD.C66X.00.06.00.00\200.V.OD.C66X.00.06\common under this path I don't know which one should I edit if I want to change the algorithm of Object Detection The sample code's structure is too big to understand. Can anyone help me thanks Best Regards Andy

Hi, Andy Dong, Expert was notified about your question. Regards, Mariya

Andy The source code of the Algorithms are not included in the VSDK release package. only the lib (binary) version is included please contact your respective TI sales or field support to get the Algo in source format regards, Shiju

Hi, Shiju I install REL.200.V.OD.C66X.00.06.00.00.exe and then the documents are the same as in the path C:\PROCESSOR_SDK_VISION_03_00_00_00\ti_components\...\REL.200.V.OD.C66X.00.06.00.00 . This ( PROCESSOR_SDK_VISION_03_00_00_00 ) package , I download from Ti's website. so where can I edit the algorithm of Object Detection Thanks a lot. Regards, Andy

HI Andy, This is public forum of TI and since TI has not released the source as part of public release of vision SDK, we will not be able to help you here. There are private forums for the users of the algorithm source code and you should be asking this question in private forum. Please talk to respective TI sales or field support engineer of your region to assist you. Thanks, With Regards, Pramod

Ticket Name: Linux/TDA2: For the Development Boot Mode

Part Number: TDA2 Tool/software: Linux For the Development Boot Mode We have learned that TDA's QSPI Development Boot Mode requires the resources of MMC/SD . As the following information: Only MLO and u-boot.img are stored in QSPI flash memory. DTB & uImage are stored in MMC/SD boot parition. The rootfs is mounted from MMC/SD partition 2 Please tell us whether NorFLASH or Nandflash Development Boot Mode also needs to possess MMC/SD resources? Where can I find this information? If we do not want to use the MMC/SD hardware to store booting-related content, how can we solve it?

Hi, Can you please check the following links if you haven't checked it already? processors.wiki.ti.com/.../Processor_SDK_Linux_Automotive_Software_Developers_Guide processors.wiki.ti.com/.../Processor_SDK_Linux_Automotive_Software_Developers_Guide processors.wiki.ti.com/.../Processor_SDK_Linux_Automotive_Software_Developers_Guide processors.wiki.ti.com/.../Processor_SDK_Linux_Automotive_Software_Developers_Guide By default in our SDK, we don't support NOR boot mode on TI EVM h/w. Please refer processors.wiki.ti.com/.../Linux_Core_U-Boot_User's_Guide Also note that NAND bot mode is currently supported for DRA71x EVM. The Linux software on DRA71x EVM is portable on TDA2Ex EVM. Let me know if you have any follow-up questions? Regards, Somnath

Hi， For The Development Boot Mode, The QSPI Development Boot Mode linked on the following page mentions that boot needs to use MMC/SD. Why can't it all be stored in QSPI? We use the TDA2S series。If We can't use QSPI storage alone, do you recommend independent storage with NAND flash or NOR flash? processors.wiki.ti.com/index.php

Hi, The main reason why we use the production boot mode is when we need a faster kernel + App boot time. We get better throughput from a QSPI flash, if the kernel is stored there and also bypass the second stage of the boot process. However, this requires a bigger flash (bigger cost) depending upon the size of all the binaries you want to store in QSPI and what you want to quick start. You can store the Linux Fs in eMMC flash. And have your initial binaries (BL+ Kernel + f/w mages) stored in QSPI. Does that address your question? Regards, Somnath

Our Linux Fs and initial binaries (BL+ Kernel + f/w mages) probably only need less than 30MB capacity, so we think it would be enough to choose a 64MB QSPI FLASH. In addition, if we use TI's vision library on a SOC like Parking line detection and MOD function, will it take up more resources of FLASH?

yes, if you add more libs (like Parking line detection and MOD function) it will increases your firmware size, depends on the the code/data and const used in the libs

Ticket Name: RTOS/TDA2: Recommended RTOS for TDA2x ADAS

Part Number: TDA2 Other Parts Discussed in Thread: SYSBIOS Tool/software: TI-RTOS Dear TI I would like to check with you which OS is highly recommended to use for ADAS.

Hi Wilson, it is the VisionSDK (current ver 3.03): www.ti.com/.../processor-sdk-tdax Regards, Yordan

This is a very generic question. It is totally your choice depending on your system needs, our Sdk comes with TI SYSBIOS and Linux. These OS are not safety certified but we have customers who have built upto ASIL B system using them. You can either use them or get a OS from vendors like mentor, Windriver, QNX etc. regards yashwant

Ticket Name: RTOS/TDA2: Utils_memAlloc memory aligment

Part Number: TDA2 Tool/software: TI-RTOS Hi, I'm new in SoC and heterogen memory systems. How I should choose memory alignment parameter for Utils_memAlloc, if uint8_t, uint16_t element size is used? How does memory alignment influence?

Hi, Alignment will depend where you want to use that allocated memory. For ex if you are using it to contain the video data then it should be 32 byte aligned. Regards, Anuj

Ticket Name: TDA2: BGA Ball footprint

Part Number: TDA2 Hello expert, Customer asked a question about footprint of TDA2 BGA (TDA2_ABC 23x23mm package S-PBGA-N760). Can you send the below footprint information regarding PCB design? 1. To design PCB, how much size of ball footprint is recommended? 0.35mm ~ 0.45mm would be okay? 2. There is no description about NSMD (Non-Solder Mask Defined) or SMD (Solder Mask Defined) in data manual. Is it okay to design PCB with SMD type? Thanks, Lloyd

Recommended ball footprint is 0.35mm. If SMD, recommended opening is 0.35mm. Thanks Robert

Ticket Name: RTOS/TDA2: TIDL: How can I get DataQ value for an output tensor?

Part Number: TDA2 Tool/software: TI-RTOS Hi guys, I have been studying TIDL for a while and after getting some good understanding on it now I am adding a new object detector into TIDL_OD example. TIDL_OD implemented SSD detection method but I removed SSD from it and added a Yolo V2 like detector on the base network. So now I got the output tensor from it whose size is [1 x 40 x 18 x 32] and I need to parse those blob to come up with coordinates of bounding boxes. The real problem is that I need to convert those numbers into floating values. So I dig into some threads discussing this issues. In the end, the conclusion is two piece of information. one from User Guide of TIDL and one from this web site. Here is the answer. ---- 10. What is Q format of output? The output is 8 bit fixed point representation with the scaling factor. The 8 bit value can be divided by scaling factor to get the floating point value. The scaling factor (in Q8 format) is available in dataQ of (sTIDL_DataParams_t). Import tool also prints this information for sampledata as “Out Q : X”. Related E2E query : e2e.ti.com/.../642684 ---- But when I print out the following variables from net structure right after running TIDL algorithm. It shows all zeros on dataQ fields. (sTIDL_DataParams_t). From the source code, vision_sdk/apps/src/rtos/alg_plugins/tidl/tidlLink_algPlugin.c At the function AlgorithmLink_tidlProcess(), I added the following printing lines: i from 0 to 28 , since I have 28 layers. Vps_printf("net->TIDLLayers[%d].outData[%d].dataQ = %d\n", i, 0, net->TIDLLayers[i].outData[0].dataQ); Vps_printf("net->TIDLLayers[%d].inData[%d].dataQ = %d\n", i, 0, net->TIDLLayers[i].inData[0].dataQ); I need to know that dataQ value to calculate a scale factor to convert those 8bit quantized values into floating values. Can you help me on how I can get those dataQ values for my last convolutional layer? And if I run a statical tool called quantStatTool (exe binary), it print out the Out Q values, basically how you to print those Out Q values? Thanks in advance!

Please find the dataQ information as part of outArgs typedef struct { IVISION_OutArgs iVisionOutArgs; int32_t numOutBufs; int32_t dataQ[TIDL_NUM_OUT_BUFS]; } TIDL_outArgs;

Hi Kumar, Thanks a lot for your answer. Indeed I already checked the outArgs struct too since I guessed that it might has the dataQ values for output buffers (i.e., output tensors). I thought that it is the right answer, but when I print out dataQ[0] to dataQ[15] (since there are 16 buffers), only the first value has some output numbers all others (15) are zeros. This is fine since I have only one output buffer (convolutional layer), but dataQ[0] value begins from a value of 1402 and goes down to 42, and sometimes shows 0. 0 dataQ value is something wrong, isn't it? Anyway, thanks for confirming my hypothesis is indeed correct. What do you think about those zeros dataQ values sometimes?

1402 looks reasonable to me. DataQ ero mean almos all the tensor values are zero. Is the input image is dark r staurated during this Data zero case. Are you getting the expected output during import. If yes, try to run import with more images.

Ticket Name: TDA2: TDA2x TIDL Deep learning setup

Part Number: TDA2 Dear TI, I am trying to setup the TIDL deep learning framework. Firstly I set up the below from github in Linux Ubuntu: caffe-jacinto caffe-jacinto-models Based on the instruction, I need to build (make) for caffe-jacinto but face face different build error due to various dependency from either cuDNN or other dependncy, e.g. the current error is: CXX src/caffe/blob.cpp In file included from ./include/caffe/common.hpp:48:0, from ./include/caffe/util/cudnn.hpp:7, from src/caffe/blob.cpp:4: ./include/caffe/util/device_alternate.hpp:10:20: fatal error: nvml.h: No such file or directory #include <nvml.h> ^ compilation terminated. Can you provide a pre-build package? (So we can focus on our the DL traning and parameter generation) Thanks and best regards He Wei

Hi He Wei, TIDL prebuilt libs are part of Vision SDK release You can find in below folder <install_dir>\ti_components\algorithms\REL.TIDL.01.01.01.00 Regards Surya

Hi He Wei, Are you able to get VSDK working with TIDL prebuilt package ? Regards Surya

Dear Surya, We decide to use general Caffe and TensorFlow on PC Host for training due to some limitation on TIDL caffe-jacinto, e.g. must be in Linux and must use GPU.. Thanks and best regards He Wei

Ticket Name: Linux/TDA2: About lvds_vip_multi_cam_3d_srv Demo data dump

Part Number: TDA2 Tool/software: Linux Hi, I'm using the PROCESSOR_SDK_VISION_03_03_00_00_setuplinux.bin. I want to dump data base on the lvds_vip_multi_cam_3d_srv demo. It's link tree is as below. Questions: a.If i add my link tree（ipc -> a15 -> null）at (1)， and the demo can run and all 4 camera have image display on screen. But the callback function never being called. Even the callback only have a vps_print(), and there is nothing out. And also i add a callback for the demo's null link. It's also not called. Anyone give me some suggestions? b.If i add my link tree at (2) (same with link tree above). There is still images displayed on screen. The demo looks not work well. Is the image data can be dumped after sync_link? c.I boot system&app from MMC/SD. After i build my app. I need to plug-out my SD & write new app by host. Is there a easy way? Line ethernet?

My build choice is tda2xx_evm_linux_all. And it's configuration is default.

Add one more question, d. Is sync_link -> dup_link ->null_link OK?

Hi , a.If i add my link tree（ipc -> a15 -> null）at (1)， and the demo can run and all 4 camera have image display on screen. But the callback function never being called. Even the callback only have a vps_print(), and there is nothing out. And also i add a callback for the demo's null link. It's also not called. Anyone give me some suggestions? Ans : This needs to work , Do you have null in ipu or in A15. ? you can check printing the stats (p option) and see if null link is really receiving the frames , b.If i add my link tree at (2) (same with link tree above). There is still images displayed on screen. The demo looks not work well. Is the image data can be dumped after sync_link? Ans: Image can be dumped after sync also , but atfer sync the buffer will be composite buffer you need to properly figure out the video buffer payload and dump . c.I boot system&app from MMC/SD. After i build my app. I need to plug-out my SD & write new app by host. Is there a easy way? Line ethernet? Ans: you can use nfs boot , refer user guide. d. Is sync_link -> dup_link ->null_link OK? Ans: This data path is also Ok , Please ensure you free the buffers in all the null link else the system will slowdown . Regards Chetan.M

Hi Chetan, Thanks for you reply. I will try it and check my code. And i can dump sync data now. Like picture below. Does it make sense. Regards Zhang

Zhang, Can you view the file in yuv viewer and check the format. Regards Chetan.M

Hi Chetan, In fact it's a H264 video. I use links like this: ->sync_link->encode link-> null link I dump h264 data in null_link. Is this usage correct? Best, Zhang

I am not sure why the croma is not correct, Why do you need to dump h264 video . ? Regards Chetan.M

Hi Chetan, Because the card write speed is a little slow. If i dump YUV data. The video may drop frames. BTW. I will try to dump yuv data later. Thanks for you help. Best, Zhang

Hi Zhang , Please try to dump one frame to ensure the data is correct and later you can check the frame size when you are recording h264 and also check the play options Regards Chetan.M

Hi Chetan, Thanks. I will check my settings. I have a new question. I'm bringup D3's OV10640+OV490 camera module on TDA2x. And the demo can run and no error information output. But there is no image out on display. What's the possible reason? Regards Zhang

Hi Zhang, Please close the current thread and open a new thread for D3's OV10640 + OV490 issue , Regards Chetan.M

Ticket Name: TDA2SX: How to config DSS Vout1 output BT656 YUV422 8bit?

Part Number: TDA2SX Dear TI, On our custom board, we need to output BT656 YUV422 8-bit signal from Vout1 port. And we tried to config the software as attached file. The right signal can't be output via Vout1 port. The pixel clock seems incorrect, and the HDMI monitor no signal display. Could you please help check this issue asap? Thank you very much! Thanks & Best Regards! wxHow to config DSS output BT656 YUV422 8bit.pdf

Hi Wade, I think first you need to check why pixel clock is not correct. are you setting correctly in the application? How much is it different when you measured it? Also for which resolution, are you trying to enable BT656 output? Rgds, Brijesh

Dear Brijesh, Thanks for you quickly response. More detail info please see the attached file. Current issue is, when we set the pixel clock to 74.25MHz in BT656 mode, the dss driver will throw out error. Thanks wx

Hi Wade, But which PLL and which LCD output are you using? What error is it returning? Can you share part of code? Rgds, Brijesh

Hi Brijesh, We had fixed this issue, it is case by two reason. One is the LCD is not support 720p30 signal input. Another is the output timing is not correct. Today, we have another issue, the custom LCD need external sync signal, but now the output of DSS is embed sync signal. How to config the DSS to output YUV422 witch external sync signal? wade

Hi Brijesh, Can you receive my reply? wade

Hi Wade, Please refer to the application node: https://www.ti.com/lit/an/sprac16a/sprac16a.pdf. The same mechanism is used to get YUV over separate sync output. You could need to treat input YUV as RGB565 and get the RGB565 output over 8bit interface and that's how you could get BT601 output from TDA device. Regards, Brijesh

Ticket Name: RTOS/TDA2: Use Case generation error in VisionSDK while executing ./vsdk_linux.out

Part Number: TDA2 Tool/software: TI-RTOS Hi, I am trying to create a use case & referring the document (VisionSDK_UserGuide_UsecaseGen.pdf , present in docs folder of vision_sdk.) While executing the file "vsdk_linux.out". I followed following steps: 1.Created the simple use case file. chains_capture_display.txt (attached the file) . 2. I tried to Run the executable “vsdk_linux.out” for linux platform using following command. ./vsdk_linux.out /home/varshavanga/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/apps/src/rtos/usecases/chains_capture_display.txt -img -file -path /home/varshavanga/PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/apps/src/rtos/usecases/ I received the following errors: /usr/lib/libstdc++.so.6: version ``GLIBCXX_3.4.20' not found & /usr/lib/libstdc++.so.6: version ``GLIBCXX_3.4.21'not found Executed following commands to overcome those errors: 1. $ sudo add-apt-repository ppa:ubuntu-toolchain-r/test 2. $ sudo apt-get update 3. $ sudo apt-get install libstdc++6-4.7-dev After executing above commands encountered following error. ./vsdk_linux.out: relocation error: ./vsdk_linux.out: symbol _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EPKcRKS3_, version GLIBCXX_3.4.21 not defined in file libstdc++.so.6 with link time reference Do I need to install any other packages or dependencies to eliminate this error? -Thanks, Varsha chains_capture_display.txt UseCase: chains_capture_display
Capture -> Display

Hi Varsha, did you have installed the libs mentioned in "2.2.3 Other mandatory software packages for build" of VisionSDK_Linux_UserGuide.pdf: Ensure these packages/tools are installed on the installation machine uname, sed, mkimage, dos2unix, dtrx, mono-complete, git, lib32z1 lib32ncurses5 lib32bz2-1.0 libc6:i386 libc6-i386 libstdc++6:i386 libncurses5:i386 libz1:i386 libc6-dev-i386 device-tree-compiler mono-complete Regards, Yordan

Hi Yordan, I have installed the libs mentioned in "2.2.3". All the libs are installed successfully except "uname" & "mkimage". When i try to install them, i encounter the following errors: E: Unable to locate package uname E: Unable to locate package mkimage Working on Ubuntu 14.04 LTS (64 bit) . Is there something else I am missing to install ? And how can i overcome the above errors. Thanks & Regards, Varsha

Hi Varsha, for 'mkimage' you should install 'u-boot-tools' package and you should already have 'uname' installed. It seems that error is caused by another reason, I have pinged VisionSDK experts to provide help. Regards, Yordan

Hello Yordan, Thanks for your quick reply, I have installed u-boot-tools package & uname is already installed, but still I encounter the same errors: "relocation error" as well as "E: Unable to locate package uname & E: Unable to locate package mkimage". Yes, there might be some other reason. Waiting for the help. Thanks & regards, Varsha

Varsha Can you please follow VisionSDK_Linux_UserGuide.pdf section 2.2.3 Other mandatory software packages for build regards, Shiju

Part Number: TDA2 It has come to my attention that TI has deprecated the OpenCV infrastructure in its Vision SDK for TDA2x. My takeaway is that I cannot expect your support when I try to incorporate OpenCV functions (beyond version 3.1) in the code. But what about the OpenCV 3.1 library prebuilt into Vision SDK? Are the developers advised against depending on it too? Thanks

Hi juts for clarity , let me reiterate, From VSDK 3.2 onward OpenCV (on A15 Linux) has been completely deprecated. For VSDK 3.0 and 3.1, we support only the pre-built CV libs. So TI advice to not use open CV if you would come across to rebuilt the Open CV libs regards, Shiju

Part Number: TDA2 Hi 1.Now, when i use below configuration on pc to do ssd, I encounter memory leak problem. beause i want use pc simulate eve to do ssd, so I build the tidl_alg.lib use command: gmake TARGET_PLATFORM=PC TARGET_BUILD=release CORE=eve all 2.I track the code, finding that when comment each other the below two code slice, memory no longer leaks, (1) (2) 3. i use model within the tidl package, below is the model jdetnet.zip

configuration is as below #if defined(HOST_EMULATION) || (VCOP_HOST_EMULATION) #define ENABLE_TRACE_PROFILE (0) #define ENABLE_REF_COMPARISION (0) /* To enable the natural C-code for the optimized C66x kernels */ #define ENABLE_CN_CODE (0) #define ENABLE_PRINTFS (0)

Hi, What is the TIDL release version you are using? What kind of memory leak you are observing? Can you please share some screenshot of the memory leak ? Thanks, Praveen

i use tidl 01.01.00.00 the memory leak as follow, with the program runnig, it used memory increasingly as follows: some time later, as follows finally, the program exit.

Hi, Can you please check with latest TIDL release version tidl 01.01.01.00 ? Because we fixed similar issue in this release. Thanks, Praveen

Hi: I can not get latest tidl version, can you build a pc version lib for me. with command:gmake TARGET_PLATFORM=PC TARGET_BUILD=release CORE=eve all thanks

can you tell me what result in this memory leak, i want to solve this with tidl 01.01.00.00. because our cdds account expired, can not get 01.01.01.00.

Hi, Sorry, couple of files are modified for this fix and also we can not share source code here. Please contact your local TI FAE for getting access to CDDS as it is good to have latest releases and also we do provide releases regularly. Thanks, Praveen

Ticket Name: Compiler/TDA2SX: running usecases on custom board

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hello! I have custom board with TDA2 and custom pin configuration. I need to run usecases from radar SDK on this board. Which parameters i need to change before building AppImage for successful running? Thanks, Alex

Hi Alex, can you try to change the pimnux in in ti_components/drivers/pdk_01_10_04_05/packages/ti/drv/vps/src/platforms/src/bsp_platformTda2xx.c according to your board settings and see if it works? Regards, Yordan

Hi Yordan, I looked through this file, its almost what i need, but i didnt find ethernet pins. Is it in other .c file or i don't need configure ethernet pins? Regards, Alex

Hi Alex, Sorry for the delayed response. Can you check the patch vision_sdk/docs/Patches/0001-PAD-Mux-changes-to-enable-Dual-MAC.patch and see if it can give you any directions. Regards, Yordan

Thanks!

Ticket Name: Linux/TDA2: How to run demo program (apps.out) automatically after boot up?

Part Number: TDA2 Tool/software: Linux Dear Support, I'm running Processor SDK Vision Linux on TDA2x. The following are the steps to run demo program, 1. login as root 2. manually input below commands a. cd /opt/vision_sdk b. source ./vision_sdk_load.sh c. ./apps.out Is there any way to run the program automatically after boot up? If yes, could you provide a verified example? I'm seeing the following similar post (for AM437x) but I'm not sure if it is applicable for TDA2x.

Hi, Which VSDK version are you using? Regards, Anuj

Hi, Anuj I'm using Processor SDK Vision Linux v3.4. The steps to run demo program is the same since v3.1.

Hi, Attached a couple of files that need to be copied to the root-fs to autolaunch the VSDK app on startup (remove the .txt from the filenames from both files when adding to the file-system). Please note the logs don’t show up on UART and the VSDK app needs to be modified to select a chain by default and user input needs to be disabled (else the menu will keep printing in a loop and increase CPU load). The vsdk.service file needs to be copied to <path to target rootfs>/etc/systemd/system/multi-user.target.wants/ and the autorun.sh needs to be copied to <path to target rootfs>/opt/vision_sdk/. Ensure both files have executable permissions. The logs are redirected to /tmp/vsdk.log. Regards Shravan vsdk.service.txt [Unit]
Description=Launching Vision SDK App
After=rc.pvr

[Service]
ExecStart=/bin/sh /opt/vision_sdk/autorun.sh
Restart=always
Type=simple

[Install]
WantedBy=multi-user-target

 autorun.sh.txt echo "Inside the script" > /tmp/vsdk.log
cd /opt/vision_sdk
./vision_sdk_load.sh >> /tmp/vsdk.log
./apps.out >> /tmp/vsdk.log

Ticket Name: TDA2HV: TDA2HVBRQABCRQ1 Sleep mode/ Power down mode

Part Number: TDA2HV Other Parts Discussed in Thread: TDA2 Hi Support Team, We are used TDA2HVBRQABCRQ1 TI TDA2HV processor in our one of the automotive product. But we facing the issue that if we want to run up our system on sleep mode or power down mode to reduce the boot up time and use of battery . which pin are available in this TDA2HVBRQABCRQ1 part. Please provide any reference for that. Hope positive response from you

Hi Dhaval, Can you please tell a little more about your use case? For example when (e.g. ignition at MAR but car not started, etc.) you would like to put TDA2 in sleep mode, for how long time, etc.? Unfortunately there is no magic pin to put TDA2 in sleep (I wish it had) . It is a combination of software and hardware (SoC, PMIC, DDR) to enable low-power modes. Regards, Stan

Hi, DHAVAL SHAH, I am not quite sure what kind of issue you are facing? Please, specify. Also, what kind of pins you are trying to locate? Regards, Mariya

Hi Stan, Thanks For you valuable reply. Actually we want to give facilities in our hardware. So we want to know how it will be implement in hardware side, software side guys are at definition stage. As our discussion you said that It is a combination of software and hardware (SoC, PMIC, DDR) to enable low-power modes. In PMIC there is PMIC_SLEEP# Pin which help full to run the PMIC in sleep mode but What we do on TDA2X side & DDR3 side to run the processor in low power mode /sleep mode? Best Regards Dhaval Shah

Hi Mariya, Thanks For your reply Actually we want to give facilities in our hardware. So we want to know how it will be implement in hardware side, Software side guys are at definition stage. Best Regards Dhaval Shah

Hi Dhaval, Since I didn't knew your exact PMIC part number, I took a random PMIC. The SLEEP pin may be on another position than this one. I've highlighted the pins you need to put the SoC in RTC mode (lowest possible). RTC mode is defined as everything but RTC domain is off. DDR can be in self-refresh ( this must be double checked though) . One can exit RTC power mode through a RTC alarm or an WAKEUP pin transition. Note that it is possible to wake up through DCAN RX pin i.e. upon a CAN bus activity. I.e. DCAN RX pin is muxed with an WAKEUP pin internally. Regards, Stan

Ticket Name: RTOS/TDA2HG: HW SHORT occurred on TDA2 vision-kit and de-serializer board when 4 Cameras were connected

Part Number: TDA2HG Tool/software: TI-RTOS Dear Champs, My customer failed to run SV demo with VisionSDK_UserGuide_TDA2xx.pdf using pre-built image. When they connected 3 cameras, there was no issue to run DEMO, but they failed to run DEMO with 4 cameras. At this failure, they observed high 'current' in their power supply like HW SHORT. So, they sent de-serializer board to repair it, but they failed again even with new board. Could you please let me know your idea what should be checked in this case? SW is Vision-SDK v3.02.00.00. Thanks and Best Regards, SI.

Hi, I have forwarded your question to an expert for comment. Regards, Yordan

SI Are they tried 2D SRV on TDA2x EVM + Vision daughter card + OV10635 Camera ? or any other demo. Please check they used the right power supply (the one shipped along with EVM kit) regards, Shiju

Hi Shiju, Yes. they tried 2D SRV on TDA2x EVM + Vision daughter card + de-serializer board + OV10635 cameras. There was no power supply in the EVM package, and they used power supply. Thanks and Best Regards, SI.

SI Please check with spectrum digital on the power supply. power supply specification Input: 100-240V Output: 12V, 7A regards, Shiju

Hi Shiju, I’m checking the specification of power supply, and it seemed it’s max output is only 3A. Do you think 3A is OK? BR, SI.

SI no, I checked by power supply, it should be Output: 12V, 7A regards, Shiju

this issue was resolved after using new power supply(12V, 10A). Thanks for your support! Thanks and Best Regards, SI.

SI Thanks for the confirmation regards, Shiju

Ticket Name: TDA2EVM5777: No rule to make target

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi Team, A customer is building the vision SDK for the TDA2 EVM but is having errors below: D:\PROCESSOR_SDK_VISION_03_08_00_00\vision_sdk\build>gmake -s -j gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_common_avb_rx] Error 2 gmake[4]: *** Waiting for unfinished jobs.... gmake[5]: *** No rule to make target `;'. Stop. gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_common_avb_tx] Error 2 gmake[4]: *** [links_common_algorithm] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_common_dup] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_common_gate] Error 2 gmake[4]: *** [links_common_ipcIn] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_common_ipcOut] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_common_merge] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_common_network_rx] Error 2 gmake[4]: *** [links_common_nullSrc] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_common_null] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_common_tfdtp_rx] Error 2 gmake[4]: *** [links_common_network_tx] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_common_sync] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_ipu_display] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_common_select] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_ipu_vip_capture] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_ipu_vpe] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_ipu_dssM2mWb] Error 2 gmake[4]: *** [links_ipu_display_ctrl] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_ipu_system] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_a15_system] Error 2 gmake[4]: *** [links_dsp_system] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_eve_system] Error 2 gmake[4]: *** [links_common_system] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [links_ipu_iva] Error 2 gmake[5]: *** No rule to make target `;'. Stop. gmake[4]: *** [utils_common] Error 2 gmake[3]: *** [libs] Error 2 gmake[2]: *** [links_fw_libs] Error 2 gmake[1]: *** [apps] Error 2 gmake: *** [vision_sdk] Error 2 I am hoping you can help. Regards, Marvin

Ticket Name: TDA3: TDA2/TDA3 materials

Part Number: TDA3 Hello, Is there TDA2X, TDA3x introduction and development process information, materials like PPT, especially focusing on the basic development process, my customer has been evaluating the test platform. This matter is very important to customers, and it is also urgent, could sent to my email if available, thank you!

Hi, Multiple trainings are available on ti.com for starting TDA2/3 development: training.ti.com/tda2-and-tda3-processors-training-series Regards, Rishabh

Hi Garg, Thanks for your suggestion!

Ticket Name: Linux/TDA2PXEVM: Nullsrc read mp4 file and decode then Display. Video seems disordered

Part Number: TDA2PXEVM Tool/software: Linux Hi all, I use vision_sdk to build a usecase. And my chains picture is below: Then I saw Rtsp link shows video alright. But Display link show video seems like it disordered on timeline. My decode create parameter is below:     UInt32 chId;
    DecLink_ChCreateParams *decPrm;

    for (chId = 0; chId<MAX_NUMBER_OF_CHANNELS; chId++)
    {
        UTILS_assert (chId < DEC_LINK_MAX_CH);
        decPrm = &pPrm->chCreateParams[chId];

        decPrm->dpbBufSizeInFrames  = DEC_LINK_DPB_SIZE_IN_FRAMES_DEFAULT;
        decPrm->algCreateStatus     = DEC_LINK_ALG_CREATE_STATUS_CREATE;
        decPrm->decodeFrameType     = DEC_LINK_DECODE_ALL;

        decPrm->processCallLevel    = DEC_LINK_FRAMELEVELPROCESSCALL;
        decPrm->targetMaxWidth      = MAX_FRAME_WIDTH;
        decPrm->targetMaxHeight     = MAX_FRAME_HEIGHT;
        decPrm->numBufPerCh         = 6;
        decPrm->defaultDynamicParams.targetBitRate = 10*1000*1000;
        decPrm->defaultDynamicParams.targetFrameRate = 29;
        decPrm->fieldMergeDecodeEnable = FALSE;

        decPrm->format = SYSTEM_IVIDEO_H264HP;
        decPrm->profile = 3;
        decPrm->displayDelay = 0;
    } And my mp4 detail information is below: [STREAM]
index=0
codec_name=h264
codec_long_name=H.264 / AVC / MPEG-4 AVC / MPEG-4 part 10
profile=High
codec_type=video
codec_time_base=1/58
codec_tag_string=avc1
codec_tag=0x31637661
width=1280
height=964
coded_width=1280
coded_height=976
has_b_frames=2
sample_aspect_ratio=1:1
display_aspect_ratio=320:241
pix_fmt=yuv420p
level=32
color_range=unknown
color_space=unknown
color_transfer=unknown
color_primaries=unknown
chroma_location=left
field_order=unknown
timecode=N/A
refs=1
is_avc=true
nal_length_size=4
id=N/A
r_frame_rate=29/1
avg_frame_rate=29/1
time_base=1/14848
start_pts=0
start_time=0.000000
duration_ts=7806976
duration=525.793103
bit_rate=366088
max_bit_rate=N/A
bits_per_raw_sample=8
nb_frames=15248
nb_read_frames=N/A
nb_read_packets=N/A
DISPOSITION:default=1
DISPOSITION:dub=0
DISPOSITION:original=0
DISPOSITION:comment=0
DISPOSITION:lyrics=0
DISPOSITION:karaoke=0
DISPOSITION:forced=0
DISPOSITION:hearing_impaired=0
DISPOSITION:visual_impaired=0
DISPOSITION:clean_effects=0
DISPOSITION:attached_pic=0
DISPOSITION:timed_thumbnails=0
TAG:language=und
TAG:handler_name=VideoHandler
[/STREAM] So did I miss something? Thanks a lot!!!!

Hi, You need to provide an elementary stream to decoder. Are you able to play the stream without dup and rtsp link? Regards, Anuj

Also what is disordered? Hopefully you are removing the padding that decoder adds to the output. Rgds, Brijesh

I modified Null link, so that it can unpacked mp4 file. Then it will send to decode link. Last night I try to use "IssCapture -> Alg_SimpleIsp (A15) -> Encode -> Null" to record video as "file.h264" and "file.hdr". Then play those as "NullSource (A15) -> Decode -> Display", it displayed no disorder. But when I use "NullSource (A15) -> Null" to record h264 file, then play it on "NullSource (A15) -> Decode -> Display", it displayed disorder. So I think it may it may NullSource unpack problem. But when I played those disordered h264 file by ffplay, it looks fine. That is so wired... Did Decode link decode file on any specify way?

En... it is hard to explain what is disorder. People move seems like shake. And would you please explain how to remove the padding? I can't seem it in usecase:null_src_decode_display

Sorry this is my fault. I use ffmpeg convert avi to mp4. And it insert b frame by itself. When I setting b-frame as 0, everything goes fine. Thanks all!

Part Number: TDA2 To TI supporter, Our company bought TDA2X system that serial number is VA1 707002(TDA2X), the systematic tool has PCBA, monitor and power adaptor. Our purpose is success to run PROCESSOR_SDK_VISION program that include board test. However, we hit a dead end and need your help: The monitor is always black (no signal output) after system power on/boot up. How to let the system work and display the information on the screen?(We suspected that the system is boot up because the controller became hotter after power on. We do not know how to let the information output on the monitor.) How to install PROCESSOR_SDK_VISION program then execute board test program? We would like to have your fully support to setup TDA2X system. Looking forward to hearing from you soon. Thank you.

Hi, You can download Processor SDK Vision from: http://software-dl.ti.com/processor-sdk-vision/esd/TDAx/vision-sdk/latest/index_FDS.html Look at VisionSDK_Getting_Started_Guide.pdf and VisionSDK_UserGuide_TDA2xx.pdf on how to run Vision SDK. Regards, Rishabh

Hi Rishabh, Thanks your answer, but my monitor can't display any signal(black screen), how can i do? Regards, Ken Huang

Hi, Have you gone through the docs as suggested by Rishabh. You first need to build the sdk and prepare sd card then using that you can run the usecase ans see the same on monitor. Regards, Anuj

Hi Anuj, Ok, got it. I want to know where can find VisionSDK_Getting_Started_Guide.pdf and VisionSDK_UserGuide_TDA2xx.pdf. Thanks Regards, Ken Huang

Hi, It is in the docs folder. You need to install Vision SDK (both linux and windows versions are available in link given above). Regards, Rishabh

Hi, Ok, so i just need to install PROCESSOR_SDK_VISION_03_04_00_00.exe by sd card, then the monitor can run. is right? Regards, Ken Huang

Hi, You need to install and build Vision SDK. Then you should copy MLO and AppImage to SD card and boot TDA2 in SD boot mode. As I mentioned previously refer to docs for details. Regards, Rishabh

Hi, Sorry, can more detail? I can't understand from docs. can you teach me at here? What is install and build Vision SDK, MLO and AppImage? Thanks Regards, Ken Huang

Ken, Can you be specific what exactly you did not understand from the docs. I have clearly specified the documents you need to read. "What is install and build Vision SDK, MLO and AppImage?" You need to install PROCESSOR_SDK_VISION_03_04_00_00.exe. Then you need to build the source code. MLO and AppImage are executable generated on building SDK. Regards, Rishabh

Hi, About "Build VISION SDK" is use computer to run(folder TI components)? Then i can acquire MLO and Applmage,and copy these to SD card. Thanks Regards, Ken Huang

Hi Ken, You need to build Vision SDK from PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\build folder. Detailed instructions are given in "Chapter 3 Build and Run" of VisionSDK_UserGuide_TDA2xx.pdf. After that you need to copy MLO and AppImage to SD card and boot the EVM in SD boot mode. Regards, Rishabh

Hi Rishabh, I only have version of PROCESSOR_SDK_VISION_03_03_00_00 now, i can't found VisionSDK_UserGuide_TDA2xx.pdf from PROCESSOR_SDK_VISION_03_03_00_00_Docs_Only. And this version's install step is same ? Thanks Regaeds, Ken Huang

Hi Ken, You need to download and install PROCESSOR_SDK_VISION_03_04_00_00.exe from software-dl.ti.com/.../index_FDS.html Regards, Rishabh

Hi Ken, There has been no activity on this thread for many days. Can we close the thread? Regards, Rishabh

Ticket Name: Linux/TDA2EG-17: Cannot detect USB flash disk in host mode !

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2, PCF8575 Tool/software: Linux Hi, Now I have a problem that my custom board cannot detect USB flash disk in host mode when excuted "usb start" in Uboot mode.The log is attached. And I open debug in Uboot mode .How can I resolve it ? Uboot_with_debug2.txt

Hello, Can you confirm the USB flash disk is connected to the USB2 port on your custom board? Also can you please tell us what kind of USB flash disk is used here? Manufacture, make, speed? Is this flash disk working properly when connected to PC? Also, have you tried different USB flash disk? Looking at the u-boot log provided, the USB host driver in the u-boot got initialized properly and from you debug log, we could see that the device enumerate did not start at all. So are you seeing VBUS on the USB connection once the "usb start" is called? Thanks.

Hi, 1. Yes,USB falsh disk is connected to USB2 port.And USB flash disk can be detected on TDA2EG17 EVM board,also it can work properly on PC. So it is not that USB causes the problem 2. The differences between EVM board and our custom board is that: 2.1 First,in our custom board,TDA2 don't detect the level of USB2_VBUS; 2.2 Second,in our custom board,TDA2 detects ID pin of USB port ,but we don't use PCF8575,we use AA3 as following picture. 2.3 After I excute "USB start",I measure VBUS's voltage,it will become 5V from 0V

Hi, Good to know the VBUS voltage is proper. Since the USB mode we trying is HOST, the ID pin is not a concern. Can you share the complete schematic of USB connection b/n the TDA2 and the USB port. Also, what kind of USB receptacle is used on the board? Have you tried connecting USB flash driver after the kernel boots up? Or you still at the u-boot level? Thanks.

Hi, 1. The complete schematic of USB connection is as following: 2.The type of USB receptacle is Micro USB as following: 3. I also have tried to connect USB after kernel boots up,it also failed.So I'd like to start to resolve it from Uboot mode. I am looking forward to your reply. Thanks!

Thanks for the details and sharing the schematics. I am checking with the h/w expert to confirm the schematics are fine, especially the requirements to have choke and esd are properly taken care. Thanks

Hi, Could you give some advise?And I think it's not the hardware which causes the problem,I still doubt the detection of ID pin.

The detection of ID pin is required only if the USB is configured for OTG mode. For Host mode functionality, this pin is not used. BTW, are you still seeing the issue? As previously noted, the device was not detected by the USB2 configured as HOST. You would notice in the u-boot log that the portstatus always return value 0x101 and stayed at FULLSPEED. In case of device detection, the value returned will be 0x503 (USB_PORT_STAT_ENABLE=1) and speed will switch to HIGHSPEED. This clearly says that the device was not detected by the USB controller. Suggest you to connect the USB protocol analyzer between the USB port an the USB flash drive and provided us the protocol log to analyze the issue. Thanks.

Hi Praveen: Yes,I'm still seeing the issue.But I cannot provide the log because I don't have USB protocol analyzer.

Looking at your log, it looks like the USB goes into Full speed. We will need USB protocol logs to understand why high speed fails and full speed is entered, otherwise it limits our debug. Also I noticed you mention you are connecting to USB2 port, but your schematic s showing USB1, can you share the USB2 schematic?

Hi! I haven't heard back from you in awhile, so I am assuming you have resolved your issue. If not just post a reply (or new thread if this thread if locked) Best Regards, Yining

Ticket Name: TDA2: does ti rtos provide standard socket interface like linux

Part Number: TDA2 Hi, I am using TI Vision SDK PROCESSOR_SDK_VISION_03_02_00_00 does ti rtos provide standard socket interface like linux? BR HUI

Hi HUI, You will need to include NDK for socket support. There are already some utility function and socket being used in vision_sdk\links_fw\src\rtos\utils_common\src\network_api.c Rgds, Brijesh

Hi Brijesh, I found this below configuration, # Supported values: ipu1_0 ipu1_1 ipu2 a15_0 none NDK_PROC_TO_USE=none my question is whether dsp support socket? if yes , how to enable it. And also i read vision_sdk\links_fw\src\rtos\utils_common\src\network_api.c it is tcp socket, does TI has udp socket, alternatively, does ti rtos support all socket interface like linux? Thank you in advance. BR HUI

And also how to configure the ip address in rtos , in order to make socket work. My purpose is that A15 DSP IPU , each core has one ip , then communicate with each other through socket. Is it possible?

Hi HUI, IP Address cannot be assigned to each core. It is assigned to ethernet ip. Also i think NDK is not supported in DSP. Btw, why do you want to use socket to communicate across cores? You could use IPC. There are IPC links in the vision sdk to communicate across different cores.. Rgds, Brijesh

Hi Brijesh, I am struggling on link, based on business team, they do not want chain. Ex: there are three link in three different core, like A15, DSP , IPU. They want to send data to any core between each other at any time any place, similar to socket, if i have destination ip and port, i can send data to it rather than defining chain. I am trying to understand whether current sdk support it. Meanwhile, if each core has one ethernet ip, and also rtos support socket. I can easily do it. Please let me know your idea. Thank you. BR HUI

Hi HUI, Even in Sockets, you need to connect port on each cores. This is similar, even in links, you could have link running on each core and communicate with any core. First i think you need to come up with your data flow, we could suggest/help in creating usecase. Rgds, Brijesh

In udp socket, there is one function , sendto, if you know the destination ip and port , you can send. In receive side, just need bind to one udp port, then do recvfrom. I want the similar things in IPC. Business team did not share data flow, they said it is still in discussing. They give me an example, A B C three tasks in three cores , communicate with each other. they do not want to define any chain. They want to define three links ,then each link can talk with each other. Can current sdk support this process?

Hi Brijesh, where can i find some documents to introduce the mechanism of System_ipcMsgQSendMsg ? How does different cores send msg to each other? It looks in A15 linux using rpmsg socket, and how about rtos (Notify_sendEvent)? Thank you in advance. BR Richard

Hi Richard, we cannot use socked for this. We have support for NDK, but it can enabled only on one core and so cannot be used in this way. I think you could use shared memory and hard mail box to communicate across cores. This is what VSDK internally uses to communicate with different cores. Please have a look into System_ipcSendMessage API to understand how it works. Regards, Brijesh

Ticket Name: TDA2EVM5777: TDA2 Memory AVL

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello I'm designing our own ADAS on TDA2 platform is there memory (DDR,eMMC..etc) AVL for reference? thank you

Hi user3829173, Can you please check www.ti.com/.../sprr211 & www.ti.com/.../TDA2EVM5777 Regards, Sujith

Hi Sujith is MT41K512M8DA-107 AIT:P suitable for TDA2?

Hi, Thanks for your query! Could you please elaborate a little bit more on what exactly are you looking for? Are you looking for some DDR part numbers that you can interface with TDA2? TDA2 DDR interface is compliant with JEDEC specifications, so you can interface it with *any* DDR devices that are JEDEC compliant. The total density and number of DDR devices that can connected to TDA2 is specified in the device data manual. Please let me know if this answers your question or if you have more specific questions. Again, Thanks for writing to us. Best Regards Rajesh Veettil

Ticket Name: RTOS/TDA2: Issue with fps rate

Part Number: TDA2 Tool/software: TI-RTOS Hello There, I have below use case, Capture -> Dup Dup -> Alg1(EVE1) -> Alg11(DSP1) -> Merge Dup -> Alg2(EVE1) -> Alg22( DSP2) -> Merge Dup -> Alg3(EVE1) -> Alg33( DSP2) -> Merge -> Sync -> Alg_DmaSwMs -> Display Each algorithm links ( both EVE and DSP ) takes around 4 -6 ms to process one frame. So for sync link params are set as, syncDelta = 10 and syncThreshold = 40 Also there are no intermediate frame drops. Issue is whole chain is running at 50 fps 1080p resolution ( expected is 60+ fps same resolution) What can be the issue? ----------------------------------------------------------------------------------- [IPU1-0] 42.275605 s: [ CAPTURE ] Link Statistics, [IPU1-0] 42.275696 s: ****************************** [IPU1-0] 42.276459 s: [IPU1-0] 42.276550 s: Elapsed time = 13896 msec [IPU1-0] 42.276642 s: [IPU1-0] 42.276672 s: New data Recv = 60.23 fps [IPU1-0] 42.276947 s: Get Full Buf Cb = 50.8 fps [IPU1-0] 42.277130 s: Put Empty Buf Cb = 150.4 fps [IPU1-0] 42.277252 s: Driver/Notify Cb = 60.23 fps What can be the reason/s for less number for Get Full Buf Cb? ----------------------------------------------------------------------------------- I am using processor SDK 3.0 and TDA2x platform Attaching statistics logs for the reference. 7701.logs.txt Regards, Kajal

Hi Kajal, You are running multiple algorithms on the same core, EVE1 and DSP2, if it takes 4 to 6 ms on EVE for each algorithm, it will be too tight to run whole chain at 60fps.. Rgds, Brijesh

Ticket Name: TDA2PSX-ACD: Functional Safety FMEDA

Part Number: TDA2PSX-ACD We use the above mentioned part for our system. We had performed a FMEDA for our product and need to look more closely to the TDA2PSX-ACD. - Could you provide detail data for failure rate calculation? - Do you have an allocation of areas used for different sub-modules? - When switching to the device TDA2PHG-ACD is there anything we have to take into account from functional safety point of view? Thank you for your support. Best regards Viktor Tiederle

Hi Viktor, You would need to get in touch with your TI representative to understand the Failure Calculation using the FMEDA sheet. - When switching to the device TDA2PHG-ACD is there anything we have to take into account from functional safety point of view? This is little vague, do you have some specific device feature you have used in the past and curious if TDA2px supports this or not. Thanks and Regards, Piyali

Hi Piyali, sorry for late answering. I was quite busy. First of all I need some understanding of the FMEDA calculation of the device. In our internal documentation, we have some files, e.g. J6Entry_FMEDA_r1.xlsm All of the information is password protected. Is it possible to discuss some question with you? The change of device is due to long lead time. yes, the question, what to do is vague, but the first product is highlighting the ADAS application, and the other not. This seems for me that anything could be different, that is to be taken into account with respect to functional safety. If not - that would be great. Hopefully now it is more clear for you. Best regards Viktor

Hi Viktor, If you are moving from TDA2PSX-ACD. to TDA2PHG-ACD, there is really no change as they belong to the same family of devices. They would share the same FMEDA. Thanks and Regards, Piyali

Ticket Name: RTOS/TDA2: TDA2XX\usecase

Part Number: TDA2 Tool/software: TI-RTOS i am a newer in TDA2xx，when i Generate a usecase gen tool by vsdk_win32.exe –img –file configFile，what should i do to next？ and about these Generated file，how to compile them？ Thanks for being able to answer。

Hi, You should refer to VisionSDK_UserGuide_UsecaseGen.pdf and VisionSDK_UserGuide_BuildSystem.pdf on how to write the use case function and how to add it to build. Regards, Rishabh

Thank you for giving me great help

Part Number: TDA2 Other Parts Discussed in Thread: TPD1E05U06 Is there any special reason why HDMI differential signal pairs CPU_HDMI_TX[0-2] and CPU_HDMI_TXC do not go through companion IC TPD12S016RKTR prior to external connector?

Hi Lim, Let me check on the reason and get back to you. Regards, Sujith

The TPD12S016RKTR had too much capacitance for the TDA2 HDMI signals, and could not meet the HDMI electrical specifications. TPS12S016 data sheets states typical capacitance is 1.2pF. The ESD components used on the EVM (TPD1E05U06) has typical capacitance of 0.42pF. Additionally, the EVM implements voids in the ground plane beneath the ESD diodes to minimize the capacitance even more. Thanks Robert

Ticket Name: TDA2: TIDL Benchmarks

Part Number: TDA2 Hey, are there more benchmarks for TIDL tests that maybe also don´t only work with CNN models? Are there additional benchmakrs for TDA2x? cheers NIco

Refer the TIDL data sheet and users guide for suported layer types and their benchmarks.

yea I checked that, but it appears everything was done using CNN models. Are there other tests where non-image inputs were used?

No. We have used image based inputs only

Ticket Name: TDA2HV: How to interpolate inter video frames from 30 fps to 60 fps

Part Number: TDA2HV Dear experts, is there a way to interpolate (reconstruct or calculate) inter frames, from 30 fps to 60 fps? Similar to the way as of h.264 encoding (b-frames), by bidirectional motion estimation. Could IVAHD being (re)used for this? Or could you think of any other valid approach? Note: We do not just want to double the frames.

Hi Ewald, I have forwarded your question to an expert to comment. Regards, Yordan

This kind of interpolation can be done by a custom algorithm. IVA-HD does not support this since this is not a art of any codec specification. But you maybe able to develop an algorithm on DSP or EVE.

Ticket Name: TDA2SA: How to save multi-cam videos to files?

Part Number: TDA2SA Hi, My custom board is tda2xx and use VSDK3.07 running on linux. I want to capture 2 cameras and save the frames to SD card. The similar usecase is : lvds_vip_multi_cam_vpe_enc_null After test this usecase, I always only get one file that have frame in it. The other file is empty. I'm sure the 2nd lvds camera have data in. the multi cam usecase link is: Capture -> VPE -> Encode -> Null (A15) I got the null link in vision_sdk/links_fw/src/hlos/links_a15/null/nullLink_tsk.c if (pObj->createArgs.dumpDataType == NULL_LINK_COPY_TYPE_FILE) { /* File Write enabled for channels only from first inputQ (Q0) */ for (chId=0; chId<pObj->inQueInfo[0].numCh; chId++) { Vps_printf(" NULL LINK: Opening file for Dump \n"); pObj->fpDataStream[chId] = fopen((char *)pObj->createArgs.nameDataFile[chId], "wb"); OSA_assert(pObj->fpDataStream[chId] != NULL); Vps_printf(" NULL LINK: Opened file for Dump \n"); } } Does it mean only one camera could save to file? Please help me to store multi camera videos to files. Thanks.

Hi, Have done the proper Null link configuration in the use-case? I'm expecting the below changes in the use-case. Example: pUcObj->NullPrm.dumpDataType = NULL_LINK_COPY_TYPE_BITSTREAM_FILE; strncpy(pUcObj->NullPrm.nameDataFile[0], "/home/stream0.mpeg", 260U); strncpy(pUcObj->NullPrm.nameDataFile[1], "/home/stream1.mpeg", 260U); strncpy(pUcObj->NullPrm.nameDataFile[2], "/home/stream2.mpeg", 260U); strncpy(pUcObj->NullPrm.nameDataFile[3], "/home/stream3.mpeg", 260U); Thanks Gaviraju

Hi Gaviraju, I have check this usecase on D3 platform and it can store multi videos files. Thanks. Terry

Ticket Name: TDA4VM: TIOVX samples

Part Number: TDA4VM Other Parts Discussed in Thread: SYSBIOS, TDA2 Hi Team, Good day. Our customer has clone this repo www.google.com/url for building TIOVX and getting the following error. Building vx_framework.lib as static library [TIARM] Compiling C tivx_event.c "/home/devuser/Github_codes/tiovx/tiovx/source/platform/vision_sdk/bios/tivx_event.c", line 13: fatal error #1965: cannot open source file "xdc/std.h" 1 catastrophic error detected in the compilation of "/home/devuser/Github_codes/tiovx/tiovx/source/platform/vision_sdk/bios/tivx_event.c". Compilation terminated. >> Compilation failure concerto/finale.mak:287: recipe for target '/home/devuser/Github_codes/tiovx/tiovx/out/TDAX/M4/SYSBIOS/debug/module/source.platform.vision_sdk.bios/tivx_event.obj' failed make: *** [/home/devuser/Github_codes/tiovx/tiovx/out/TDAX/M4/SYSBIOS/debug/module/source.platform.vision_sdk.bios/tivx_event.obj] Error 1 The customer was trying to implement TIOVX samples on their linux system and in future they will trying to implement it in a TDA4X EVM development board. Do we have information regarding building TIOVX and sample implementation of Openvx? Regards, Carlo

Hello Carlo, We would recommend downloading the PSDK RTOS which includes the TIOVX project as well as all dependencies for building. The provided link is the TIOVX version intended to support TDA2/TDA3 devices, and therefore requires additional TDA2/TDA3 dependencies to build. The PSDK RTOS can be downloaded at the below link. Information in the below links is provided to show how to build the entire SDK as well as details on how to build TIOVX. Please let me know if you have further questions. Regards, Lucas

Ticket Name: TDA2EVM5777: TDA2 EVM TMDS single end 60 ohm

Part Number: TDA2EVM5777 Hello I read from GPIO_Revision 2.0 8.5.4.2 TMDS General Routing Guidelines single end impedance control should be 60 ohm, why is 60 ohm not 50 ohm? thank you

Hi, I've pinged documentation team and they said 60 ohm is correct. By the way, HDMI spec doesn't specify the single-end impedance. It only specifies the differential impedance of 100 ohms. Regards, Stan

Hello So the document says the 60 ohm, what signal should we follow the 60 ohm impedance? thank you

I'm not sure I understand enough your question. If it is related to routing, I find this guidance in the EVM schematic: DIFFERENTIAL PAIR 100 OHM DIFFERENTIAL IMPEDANCE SHORT AND STRAIGHT AS POSSIBLE, MINIMUM NUMBER OF VIAS

Hello So there is no HDMI trace need to route in 60 ohm ? Thanks

Locust, From 'HDMI Board Design and Layout Guidelines' section of the TDA2x Data Manual: "The TMDS differential signal traces must be routed to achieve 100 Ohms (+/- 10%) differential impedance and 60 ohms (+/-10%) single ended impedance. Single ended impedance control is required because differential signals can’t be closely coupled on PCBs and therefore single ended impedance becomes important." I think there is a misunderstanding between single ended impedance and differential impedance, in your original question. -Colin -Colin

Hi Locust, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Part Number: TDA2 Tool/software: Linux EVE: I only find alg kernel functions in xx\PROCESSOR_SDK_VISION_03_04_00_00\ti_components\algorithms\eve_sw_01_19_00_00\kernels. The head files of much original C functions only be found, but the implemented code can't be found. We only see alg kernel functions, and it's hard to understand alg kernel functions. Where here can I get those original C functions？

Hi @user3591944 , EVE kernels are released as "Limited Source, Binary and documents", (please check eve_sw_01_19_00_00\docs\eve_sw_manifest.pdf). For full source code release you need to contact your local TI representative. Regards, Yordan

Ticket Name: Boundary Scan file for TDA2SXBTQABCRQ1

Hi, We're using TDA2SXBTQABCRQ1 in our Hennessy Project. Could TI please share the boundary scan file for this please.

Hi Marcelino, you can find bsdl file for TDA2x here: www.ti.com/.../toolssoftware Regards, Yordan

Ticket Name: Compiler/TDA2PXEVM: Compiler issues while porting Linux application to A15(which runs on SYSBIOS)

Part Number: TDA2PXEVM Other Parts Discussed in Thread: SYSBIOS, TDA2 Tool/software: TI C/C++ Compiler Hi, As discussed under "e2e.ti.com/.../2823318 creating the new thread related to compiler issues. With the help of the patch we could compile the sources for A15 core both in module as well as in usecase. The MAKEFILE.MK file what we have at our end doesn't contain anything related to "AUTOSAR_APP". So, I haven't included those changes. ifeq ($(AUTOSAR_APP), yes) -APP_LIBS_$(IPU_SECONDARY_CORE) += $(DEST_ROOT)/lib/$(PLATFORM)/$(IPU_SECONDARY_CORE)/$(PROFILE_$(IPU_SECONDARY_CORE))/app_libs.aem4 +APP_LIBS_$(IPU_SECONDARY_CORE) += $(DEST_ROOT)/lib/$(PLATFORM)/$(IPU_SECONDARY_CORE)/$(PROFILE_a15_0)/app_libs.aa15fg endif For your reference we are using below version of SDK "PROCESSOR_SDK_VISION_03_03_00_00" You mentioned that you are running bios on A15 but your module uses linux calls...... Yeah, but can't we not overcome those compiler errors ?redefinition errors being ---------------------- /opt/V_SDK/FFC/FFC_WORKSPACE/scripts/..//sdk/ti/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/os_tools/bios_6_46_04_53/packages/ti/sysbios/posix/mqueue.h:63:0: error: "O_CREAT" redefined [-Werror] #define O_CREAT 0x200 /* TODO: sys/fcntl.h? */^ In file included from /opt/V_SDK/FFC/FFC_WORKSPACE/scripts/..//sdk/ti/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/os_tools/bios_6_46_04_53/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/include/sys/fcntl.h:4:0, from /opt/V_SDK/FFC/FFC_WORKSPACE/scripts/..//sdk/ti/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/os_tools/bios_6_46_04_53/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/include/fcntl.h:1, from /opt/V_SDK/FFC/FFC_WORKSPACE/source/vision/platform/ti/tda2/apps/src/rtos/modules/LibDLT/dlt_user.c:43: /opt/V_SDK/FFC/FFC_WORKSPACE/scripts/..//sdk/ti/PROCESSOR_SDK_VISION_03_03_00_00/ti_components/os_tools/bios_6_46_04_53/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/include/sys/_default_fcntl.h:37:0: note: this is the location of the previous definition #define O_CREAT _FCREAT ^ ----------------------------- If you are running bios on A15 then all those answer does not hold true.... Yeah, I understand the answer doesn't hold true if either SYSBIOS runs of A15. Having it in mind I would like re-iterate the set of queries to proceed further. As Pthread support is available for A15, building pthread application for SYSBIOS would still be possible? As mentioned our application had got sockets and FILESystem calls in place, Do we have support for FileSystem and sockets on SYSBIOS? If So, how could we make use of it or do we need to look for corresponding alternatives in it? And having said Sample being the server component, there are the other applications which communicates to Sample via Sockets or through PIPES or any file based operations. Being Sample built for A15 core, does the other applications which has to communicate to Sample should also be built for A15?or IPC(shared memory) mechanism suggested still holds good for communication? So you have to try with tda2px_evm_linux_all cfg.... Could please elaborate on it, what excatly should be considered from tda2px_evm_linux_all cfg.file reason being tda2px_evm_linux_all cfg.file had got A15_TARGET_OS to Linux. Pradeep

Hi Yes, you can get Pthread support on A15 Bios Socket APIs are not supported on Bios, but native FATFS file system can be supported IPC is supported in a different way and not using socket APIs, BTW, which Linux code you try to port on A15 Bios? regards, Shiju

Hi Shiju, BTW, which Linux code you try to port on A15 Bios? To be more specific we are trying to port DLT_DAEMON(which is a logging framework built for linux platform which had got most of the POSIX related calls int it) were in other components/applications use dlt interfaces to log the data to DLT-DAEMON via pipes or shared memory, and DLT-Daemon would route the data to client which runs on host machine using sockets. so, in order to acheive that we are trying to port DLT to SYSBIOS using vision SDK. ------------ Socket APIs are not supported on Bios... Then how could we communicate to external host machine(windows)? but native FATFS file system can be supported.. Could you please refer us the sample example from Vision SDK package which has got native FATFS in use? ------------ IPC is supported in a different way and not using socket APIs, .. could you please elaborate what do you mean by IPC is Supported in different way?

Hi You can use Ethernet to communicate with external host machine(windows) for FATFS, please refer \vision_sdk\apps\src\rtos\usecases\tidl UC, it read data from SD card (using FAT FS) Please refer \vision_sdk\links_fw\src\rtos\links_common\ipcOut and ipcIn modules regards, Shiju

Ticket Name: RTOS/TDA2: RTOS / TDA2： What's the entire procedure for running TIDL_OD usecase?

Part Number: TDA2 Tool/software: TI-RTOS Hi, As title, I have read VisionSDK_UserGuide_TI_DeepLearning & TIDeepLearningLibrary_UserGuide I know I have to present this four files ( NET_OD.bin、PRM_OD.bin、inData_OD、inHeader_OD ) in the SD card But, how to generate this four files ? and I read TIDeepLearningLibrary_UserGuide 3.6.5 Importing Tensorflow Models Where should I put the file which generated by doing the all steps from 3.6.5 ? Sincerely, Andy

Hi Andy , Please follow the below posts for your questions e2e.ti.com/.../687481 Regards Chetan.M

Ticket Name: TDA2: Compatibility of ISP and CMOS Image sensor

Part Number: TDA2 how we can say that this ISP is compatible with this CMOS image sensor??

Hi Harsh, ISP is not supported on TDA2x.. It is available on TDA3x and TDA2Px. Regards, Brijesh

Hi Brijesh, If i work on TDA3x then if i want to choose an ISP for my cmos sensor like OV10640, then how will i choose a perfect ISP for that. How we can say that ov490 is compatible with OV10640. how we compare different ISP's ?

Hi Harsh, ISP is HW module and is internal to TDA3x. OV490 is ISP from omnivision. Go through the details of each ISP and then you could compare.. Regards, Brijesh

Harsh, I am assuming that there are no further questions and so closing this thread. You can reopen it if you have any more questions.. Rgds, Brijesh

Hi Brijesh, As you say that TDA3x has its own internal ISP. So, do we need any external ISP for frame based functions ?

Hi Harsh, Yes, TDA3x has its own internal ISP, so you dont require external ISP for Bayer to YUV conversion.. Regards, Brijesh

Hi Brijesh, For image stablization or for noise reduction should i need external ISP?

Harsh, There is a noise filter in ISP, but for image stabilization, you need to develop algorithm. Rgds, Brijesh

Brijesh, Thank you Regards, harshgarg

Ticket Name: Linux/TDA2: VXLIB Remap Performance

Part Number: TDA2 Tool/software: Linux Hi. I'm using Vision SDK 3.4 to develop 3ch 1080p vip capture -> panorama algorithm. To make panorama image to fit 1080 width, I resized each channel to 640x360. So, 1920x360 size Y-LUT and 1920x180 size CbCr-LUT is used to make panorama image. I used VXlib function , VXLIB_remapBilinear_bc_i8u_i32f_o8u. According to VXLib Test Report, remap function takes 7.5*(dst width * dst height) + 139 cycles. In my case, remap function should take about 13ms. But, actually it takes over 40ms. LUT is allocated as belows pPanoramaObj->remapBuf = Utils_memAlloc( UTILS_HEAPID_DDR_CACHED_SR, ( 1920*360*8*2 ), MY_FRAME_ALIGN /* 32u*/ ); and below is the part of remap. VXLIB_bufParams2D_t src_addr; VXLIB_bufParams2D_t dst_addr; VXLIB_bufParams2D_t remap_addr; VXLIB_STATUS vx_status; src_addr.dim_x = 1920; src_addr.dim_y = 360; src_addr.stride_y = 1920; src_addr.data_type = VXLIB_UINT8; dst_addr.dim_x = 1920; dst_addr.dim_y = 360; dst_addr.stride_y = 1920; dst_addr.data_type = VXLIB_UINT8; remap_addr.dim_x = 1920*2; remap_addr.dim_y = 360; remap_addr.stride_y = 1920*8; remap_addr.data_type = VXLIB_FLOAT32; vx_status = VXLIB_remapBilinear_bc_i8u_i32f_o8u( (UInt8*)((UInt32)pMosaicFrameBuffer->bufAddr[0] + 1920*360), &src_addr, (UInt8*)((UInt32)pOutFrameBuffer->bufAddr[0] + 1920*360), &dst_addr, (VXLIB_F32*)((UInt8*)pPanoramaObj->remapBuf), &remap_addr, 0 ); if(vx_status!=VXLIB_SUCCESS) Vps_printf("remapY result:%d\n", vx_status); remap function itself works well, and image is normal. What should I do for better performance? Thanks in advance.

Thanks for your question. Explanation of difference you are seeing All of the performance numbers listed in the test report reflect the core DSP performance without considering memory stalls. Therefore it is a best case performance assuming all of the code and data are in L1 memory. In reality, this is not usually possible, so these numbers give an idea of what the performance should not get better than. Now I have done some testing to see what the performance is assuming all data and memory were accessed from DDR cached memory, and this kernel which used randomly generated remap table ranged from 23 to 82 cycles per output pixel on average. When I ran the same test except put the code and data in DSP L2 memory, the performance improved to range from 10 to 30 cycles per output pixel. Here is a summary of performances: 1. CPU only (no L2/DDR memory) : 7.5 cycles 2. Code/Data in L2: 10 to 30 cycles 3. Code/Data in DDR: 23 to 82 cycles The difference between case 1 and 2 is the L1 cache miss penalty. The difference between case 2 and case 3 is the L2 cache miss penalty to DDR. The cache miss rate will vary based on remap table. For example, a unity remap table will have a high cache hit rate since subsequent input pixel accesses will be on same cache line that was already fetched. Proposal for Improvement As seen above, the best thing you can do to improve performance is to process the data from L2 RAM. Since the whole input image probably does not fit into L2 RAM, DMA the input from DDR into L2 RAM prior to calling this function. This probably requires you to pipeline the processing in a ping/pong fashion across blocks of input/output. What I mean is make a loop wherein you initiate a transfer of an input block into L2 RAM, and while the DMA is happening, call VXLIB function on a previously DMA'd block in L2. When the VXLIB function is done, initiate the next transfer, and continue on until the end of the whole frame. Since you are doing a remap, which blocks you transfer and how big the transfer is depends on the remap function you are doing. Final Questions After rereading your post, I'm curious why you are using remap for whole panorama. Is most of the remap a copy, or does most every pixel get shifted/warped relative to input? If you are primarily just appending input images together, you can use a DMA for all/most of the copy and that will be the fastest.

As proposed, I copied LUT block in DDR to L2 using DMA. I didn't use pingpong buffer, but performance is double-graded. If I use ping/pong buffer, better result will be expected. To answer for your final questions, in my case, almost every pixel is warped into new position. So, I can't choose the way just copying image blocks. Thanks for response.

Ticket Name: RTOS/TDA2: Vision SDK 3.5 using multicoreimagegen tool happen Segmentation fault error.

Part Number: TDA2 Tool/software: TI-RTOS Hi expert: I am using Vision SDK 3.5 BIOS version test power consumption. I compile the SDK at linux environment. After i use #make -s allcores at /pdk_01_10_01_06/packages/ti/build/ folder generate all PM-CORE_loading application. I want to combine all image to one APPimage at SD card. If i just use 10 file i can successful generate the image. If i use 11 file Multicoreimagegen tool at /sbl_auto/tools/v1/ folder happen segmentation fault. Could you please help me check this problem? Best Regards! Han Tao /work/vsdk/sdk305/ti_components/drivers/pdk_01_10_01_06/packages/ti/binary/pm_core_loading_app/bin/tda2xx-evm$ ./MulticoreImageGen LE 55 AppImage_LE 0 pm_core_loading_app_a15_0_release.rprc 2 pm_core_loading_app_ipu1_0_release.rprc 3 pm_core_loading_app_ipu1_1_release.rprc 5 pm_core_loading_app_ipu2_0_release.rprc 6 pm_core_loading_app_ipu2_1_release.rprc 8 pm_core_loading_app_c66xdsp_1_release.rprc 9 pm_core_loading_app_c66xdsp_2_release.rprc 10 pm_core_loading_app_arp32_1_release.rprc 11 pm_core_loading_app_arp32_2_release.rprc 12 pm_core_loading_app_arp32_3_release.rprc 13 pm_core_loading_app_arp32_4_release.rprc Number of Input Files 11 Segmentation fault (core dumped)

Hi Tao, Are you running this on Ubuntu 18.04? If yes can you please try the same on Ubuntu 14 or Ubuntu 16. Regards, Rishabh

Hi Rishabh: Thanks for your quickly feedback. My PC is Ubuntu 12.04. I have copy all .rprc file to windows and use windows tools generate the 11 file's image. It did not work too. Which version of Ubuntu used at your side? I will try to install the same version of Ubuntu as you and try it again. Best Regards! Han Tao

Hi Tao, This is actually a Multicore Image Generator Tool limitation. In PROCESSOR_SDK_VISION_03_05_00_00\ti_components\drivers\pdk_01_10_01_06\packages\ti\boot\sbl_auto\tools\multicore_image_generator\v2\MulticoreImageGen.c, MAX_INPUT_FILES is defined as 10. Can you please update this macro and generate an executable for multicore image generator tool using gcc. We will fix this in next release. Regards, Rishabh

HI Rishabh: I change the macro to 12 and Delete MulticoreImageGen.c line 140 debug_printf(). Use Gcc compile this file it can use 11 rprc file. Now just A15-0/IPU1-0/IPU1-1/DSP-1/DSP-2/EVE1 working. IPU2-0/IPU2-1/EVE2/EVE3/EVE4/A15-1 can not run the simulate loading. Believe this problem can be set resolve and waiting you next release. Best Regards! han tao

Hi Tao, What change did you need for debug_printf? Regards, Rishabh

Hi Rishabh： directly compile this file have error： so I just delete this line to make the compile can work. Best Regards! han tao gcc -o MulticoreImageGen MulticoreImageGen.c MulticoreImageGen.c: In function ‘main’: MulticoreImageGen.c:140:58: error: macro "debug_print" passed 2 arguments, but takes just 1 debug_print("Number of Input Files %d\n",num_input_files); ^ MulticoreImageGen.c:140:2: error: ‘debug_print’ undeclared (first use in this function) debug_print("Number of Input Files %d\n",num_input_files); ^ MulticoreImageGen.c:140:2: note: each undeclared identifier is reported only once for each function it appears in

Hi Tao, You are referring to V1 version. V2 version already uses printf for this particular print statement. We will update this as well. Regards, Rishabh

Hi Rishabh: I use V1. at readme.txt said that V2 used for TDA3x and V1 used for TDA2x. So I use V1 generate tools. Best Regards! Han Tao

Hi Tao, I am closing the thread as issue has been resolved. Regards, Rishabh

Ticket Name: Linux/TDA2: For upgrading and booting

Part Number: TDA2 Other Parts Discussed in Thread: X5777BXGABC Tool/software: Linux Because the OTA function requires software to handle the bad block capability of NAND FLASH, Question 1:the TDA2 software supports the ability to store Linux Fs in NAND FLASH, right? Question 2: What is the flow diagram of the Ethernet OTA function on TDA2?

Hi Can you clarify the exact part number for your device. NAND flash is not supported out of the box for the Linux SDK For the Ethernet OTA function - is this being exercised from Linux? Liux SDK also does not support OTA functionality, customers typically build this on their own

part number: X5777BXGABC But why is there a NANDFLASH on the (DRA74*) DEMO board?

Hi for supporting NANDFLASH out of the box, we need to select pin mux configuration that overlaps with some of the peripherals that we would like to support out of the box from SDK perspective. Also, most customers use eMMC for their non-volatile storage needs - hence we have not enabled/validated support for NAND in our SDK releases

Ticket Name: TDA2: EVE: BAM buffer transfer

Part Number: TDA2 Hi, Are there any limitations or guidelines to buffer transfer within a kernel, or in between different kernels? Is there any document which specifies this? I am facing issues in both inter-kernel transfers as well as within kernel buffer transfers. Regards, Shruti

Hi Shruti, All the requirements are specified in the BAM user's guide. What kind of issues you are facing ? regards, Victor

Hi Victor, Yes I have gone through the BAM user guide. Following are the issues I am facing are: 1. The user guide mentions "One output of an upstream node can be connected to many inputs of a downstream node." - So I have a kernel1 which has one input and two outputs (output1 and output2) . Both of these outputs serve as an input to two different kernels kernel2 and kernel3. The code gets compiled correctly, but when I run the code, I see that one of the kernels does not get these input buffer address correctly. The addresses are zero for one of the kernel which in turn affects the output. But, when I replicate these output buffers in kernel1 (i.e. total 4 outputs given out : output1, output2, output1_1, output2_1) and give seperate outputs to respective kernels then the addresses come out correct and also the output. 2. I observe the same issue inside a kernel as well. I have a kernel1, which has multiple functions inside suppose func1(), func2() and func3(). The kernel has one input from another kernel, namely input1. If I use the same input buffer in multiple functions like func1() and func2(), then I see that func1() has the correct input data, but func2() gets some corrupted data. This thus affects the output. Again if I replicate input1 into another intermediate buffer inter1 and pass this to the next function func2() then the data is correct and the output is correct as well. Are these limitations of BAM? Or are there some bugs? Or is there any configuration to correct this behavior? Regards, Shruti

Hi Shruti, 1. Please refer to the constrain listed in Chapter 5 'Current limitations' of BAM user's guide: Specifications of edge list. If one single port of an upstream node has more than one connection, which happens in case of a fork in the graph, then all these connections must be clustered together. For instance in the below image pyramid graph, every DS_NODE’s output port BAM_BLOCKAVERAGE2x2_OUTPUT_PORT has two connections: one to the next DS_NODE and one to SINK_NODE. These connections must appear one afte the other in edge list. If there is a connection involving another node or another port between them then graph creation would be incorrect. I hope this is the issue. 2. You should be able to pass the same input buffer to multiple functions. I assume func1() runs first. Are you seeing that the input to func2() gets corrupted after func1() is executed ? Unless func1() writes into that same buffer during execution, this should not happen. regards, Victor

Hi Victor, 1. Thank you. This was the issue, I am able to see the correct addresses now. 2. Yes, func1() is getting executed first, and I am just reading the input and placing the output in a separate buffer. But still the input gets corrupted before the func2(). I can try to print the addresses, to check whether it was overlapping with any other intermediate buffer. Regards, Shruti

Hello Shruti, Did you do more investigation for 2) ? regards, Victor

I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

Ticket Name: TDA2HG: Where can I find documentation about the Device Security Features?

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2, Hello, I actually want to use the TDA2+, but the answer might be the same as for TDA2HG.(I was not able to select TDA2+ in the "Part Number" field.) Where can I find documentation about the device security features? I want to make sure that we can protect our software: Software will be stored encrypted in external eMMC Flash and will be loaded by the bootloader. Is there a way to store a key inside the SOC. I read "Secure ROM and boot" in the Data Sheet. But there is no further information about that. Best regards, Michael.

Hi, Michael K, For security documents are under NDA, and you should contact your local TI representative to get it. Regards, Mariya

Ticket Name: CCS/TDA2: How to use neon in CCS

Part Number: TDA2 Tool/software: Code Composer Studio in tda2 runs the neon code command on ccs8.2. When running to the red flag as shown in the figure, it will enter __isr_vector in single step: LDR pc [pc, #-8] @ 0x0C Prefetch Abort Set in ccs -mfloat-abi=softfp -mfpu=neon Neon initialization : MRC p15, #0, r3, c1, c0, #2 @ Read CPACR ORR r3, r3, #0x00F00000 @ Enable access toCP10 and CP11 MCR p15, #0, r3, c1, c0, #2 @ Write CPACRsobel.rar MOV r3, #0 MOV r0, #0x40000000 FMXR FPEXC, r0 @ Set FPEXC bit 30 to enable VFP MCR p15, #0, r3, c7, c5, #4 @flush prefetch buffer because of FMXR above

Hi, Can you try the below sequence and see if it works for you: MRC p15, #0, r1, c1, c0, #2        @ r1 = Access Control Register
ORR r1, r1, #(0xf << 20)           @ enable full access for p10,11
MCR p15, #0, r1, c1, c0, #2        @ Access Control Register = r1
MOV r1, #0
MCR p15, #0, r1, c7, c5, #4        @ flush prefetch buffer
MOV r0,#0x40000000
FMXR FPEXC, r0                     @ Set Neon/VFP Enable bit Regards, Rishabh

Hi, I use this sequence, run to the red flag as shown in the figure it will enter LDR pc, [pc,#-8] in single step __isr_vector: LDR pc, [pc,#24] @ 0x00 Reset LDR pc, [pc,#-8] @ 0x04 Undefined Instruction LDR pc, [pc,#24] @ 0x08 Supervisor Call LDR pc, [pc,#-8] @ 0x0C Prefetch Abort LDR pc, [pc,#-8] @ 0x10 Data Abort LDR pc, [pc,#-8] @ 0x14 Not used LDR pc, [pc,#-8] @ 0x18 IRQ interrupt LDR pc, [pc,#-8] @ 0x1C FIQ interrupt this is project 8867.sobel.rar

Hi, For me the same sequence works with "mfpu=neon -mfloat-abi=hard". Can you see if the same works for you. Regards, Rishabh

Hi, You can also refer to "Entry" definition in PROCESSOR_SDK_VISION_03_05_00_00\ti_components\drivers\pdk_01_10_01_06\packages\ti\csl\arch\a15\src\csl_a15_init.asm. Regards, Rishabh

Ticket Name: TDA2: Some question about implement deep learning algorithm by ourselves

Part Number: TDA2 Hi, I found that if we want to implement deep learning algorithm by ourselves, we must need to use TIDL. But if i implement it directly without TIDL, and just run it by CPU, it seems that i can't do this? I know that TIDL can help us accelerate the algorithm, but i just want to know that if i don't use this library and run on CPU can i implement my neural network on this board ?

Hi Chen-Wei, you can create new deep learning algorithm and integrate it in your usecase. You can check documentation at vision_sdk\docs to get idea how to add new links/chains and new usecases. But please note that if you implement your deep learning algorithm on CPU you might not get very good performance (for example TIDL runs on DSP or EVE which are better suited for such calculations). Regards, Yordan

Hi Yordan, i have this question because i modify the original usecase, replace the original function(canny) with tiny-YOLO and get the following result So, i think maybe i can't implement it on CPU. I think the best way to solve this problem is creating a new usecase rather than modifying the original usecase right? Thanks for your reply, Chen-Wei Lai

Hi Chen-Wei , I have pinged VisionSDK experts for further help. Regards, Yordan

Hi Yordan, There is no further reply for so many days, should i keep waiting or just open another thread for this issue? Thanks, Chen-Wei Lai

darket net is not suported by TIDL. You may create nw uses case with out using TIDl

Ticket Name: Linux/TDA2EX17EVM: TDA2EX Frame Capture Mode

Part Number: TDA2EX17EVM Tool/software: Linux Dear Sirs: There is a frame capture mode when the video source is interlaced video in DM81xx IPNC_RDK. I just wonder whether or not this mode is also available on TDA2 VSDK? If it is available, can you tell me where the example code snippet is? Regards, /ckhsu

Hi Hsu, Currently it is not supported for VIP. VIP driver uses different mechanism for TDA2 and DM81xx. Rgds, Brijesh

Hi Brijesh: Thank you very much. Regards, /ckhsu

Ticket Name: TDA2: EVE

Part Number: TDA2 Dear， Very thanks. I want to know whether TI DSP support caffe2 or the cnn model and algorithm in the caffe/caffe2 framework？ If not，when it can？ BR

Hi, TI ADAS SOCs (TDAx family) support the cnn models trained using caffe . Please refer the SDK from TI to get more details. www.ti.com/.../PROCESSOR-SDK-TDAX Thanks, With Regards, Pramod

Ticket Name: TDA2EVM5777: AdaBoost Training

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi, I have used Adaboost object detection training tool (Matlab based github.com/.../acf-jacinto) to generate .descriptor My dataset is download from https://goo.gl/sVtBm2 (.avi) and youtube (.mp4) I annotated my dataset by acf-jacinto-master vbbLabeler.m I only change the dataset (Boat) to train the model and convert .descriptor and use it in TDA2 But it didn't work when I run 1: Single Camera Usecases f: 1CH VIP capture (HDMI) + FrontCam Analytic 2 (PD+TSR+VD+LD+TLR+SFM) (DSPx,EVEx) + Display(HDMI) and e: 1CH VIP capture (HDMI) + Pedestrian, Traffic Sign, Vehicle Detect 2 (EVE1 + DSP1) + Display 3: Enable Vehicle Detect (VD) note: I change the VD weights with mine (boat weights) Best Regards, Andy Dong

Hi Andy, Can you play with softCascadeTh and strongCascadeTh in object_detection.cfg and see if you get any detections? Try a lower value for both. Currently for VD its set at -2. Regards, Shyam

Hi, sorry for late reply I change softCascadeTh and strongCascadeTh to -5 but it still not work when I run the usecase the sreen like below picture https://goo.gl/bbSHVa Regards, Andy Dong

Hi Andy, Even if the classifier is not detecting anything, it should atleast display the video on the screen. What happens when you replace the weights back to the original one? Can you share your descriptor file? Regards, Shyam

Hi, I had already tried to replace the weights(the original VD_weights) back and it work below is my descriptor drive.google.com/.../view Regards, Andy Dong

Hi Andy, Your descriptor file looks correct to me. Unfortunately, the maximum number of cascade trees for "VD" type is 1280. In your descriptor, the number of cascade trees is 2048. So this could be the reason. Can you try using your descriptor in place of "PD"? For "PD" type the maximum number of trees is 2048. Regards, Shyam

Hi, when I replace PD with boat weights , it works But I found something weird, it never happened before I change the weight the system become easily crashed when I do below steps 1. connect HDMI 2. start the system, choose 1: Single Camera Usecases -> f: 1CH VIP capture (HDMI) + FrontCam Analytic 2 (PD+TSR+VD+LD+TLR+SFM) (DSPx,EVEx) + Display(HDMI) the boat wieghts works depend on doing step 2 -> step 1 Regards, Andy Dong

Hi Andy, Let me connect you with one of our system experts. He might have an answer for you. Regards, Shya,

Hi Andy let me try to understand Case1: if you follow below steps it works 1. start the system, choose 1: Single Camera Usecases -> f: 1CH VIP capture (HDMI) + FrontCam Analytic 2 (PD+TSR+VD+LD+TLR+SFM) (DSPx,EVEx) + Display(HDMI) 2. connect HDMI Case2: But If you follow below steps it doesn't work for you 1. connect HDMI 2. start the system, choose 1: Single Camera Usecases -> f: 1CH VIP capture (HDMI) + FrontCam Analytic 2 (PD+TSR+VD+LD+TLR+SFM) (DSPx,EVEx) + Display(HDMI) can you please confirm my understanding is right? regards, Shiju

Hi,Shiju Yes, you are right. In Case2 the screen is like below picture https://goo.gl/bbSHVa Regards, Andy Dong

Hello Andy Dong we have not noticed any such issue, the HDMI player we used works in both cases. I would doubt one thing with the player you use as it may be try to to EDID with board and it works only if you started the demo and connect the player later. As we support only 1080p @60 capture , please check if you have a way to force the player to output 1080p (1920x1080 @60fps), then I guess both case1 and case2 will work regards, Shiju

Ticket Name: Linux/TDA2: 3D surround view Camera Calibration tool

Part Number: TDA2 Tool/software: Linux Hi, I am using TDA2X vision EVM board to develop 3D surround view function. We run the calibration using the calibration tool. We found front and rear cameras can not be calibrated perfectly. Look at the picture below. The straight line becomes curved when it passes the front camera. I think it is because the lens distortion is not completely corrected. In the lens LUT generation tool, the maximum angles are limited to below 90. Will this be a problem? In another thread, you said you can provide the calibration tool source code. Can you provide that to me so we can debug what is wrong? Thanks. 1. front camera can not be calibrated perfectly.

Another strange thing is that the birdview image generated by calibration tool is good. But the online birdview image has distortion. This picture is generated by calibration tool. The numbers in red circle has no distortion. This picture is captured online, the numbers in red circle has large distortion

Those above pictures are captured in 3d adaptive surround view function (has bowl view). I also captured some images in normal 3D surround view. There are also distortions in front and rear camera area. But the curve direction is opposite to that in 3D adaptive view. Following is the picture. Notice the curve direction in red circle. Theoretically, bird view of normal surround view should have no distortion. Why it still has distortion? Thanks.

Hi Tao, For access to SRV calibration source code, please ask the respective region TI Field representative to raise a request with me. We can pass it through the approval system and provide it to you. (I can provide the source code in public forum). This would be the source code of the embedded calibration tool. Regarding your questions Limiting the FOV to 90degrees is not an issue, this is the radial angle, so the FOV of the lens we would capture would be 180 degrees Its hard for me to debug this just looking at pictures, and I'm not sure why the calibration works fine on the offline tool but not on the device. It maybe related to the bowl shape, please make sure the bowl shape is as flat by extending the offsets to the far regions (Typically around +/-400 or so) and keep the adaptive logic turned off.Can you also mention which two usecases you tried on the device and more information on your setup (Which sensor/camera etc) Regards Shashank

Hi Shashank , I have figured out the cause of issues listed above. It is because the limitation of the max angle. After I remove that limitation. Those issue disappears. But the stitched image is still not so good. Please look at the image attached below. I am using the cameras from spectrumdigital in this link: www.spectrumdigital.com/.../. The cameras don't have lenses. We bought the that and installed by ourselves. According to your experience, will those cameras be a problem? Thanks.

Hi Tao, Typically you need machine aligned camera modules to get good calibration. Hand screwed lenses may have issues but you may be able to get better calibration than this. You can try running the lens center detection tool from the manual calibration tool prior to generating the LENS.bin. In this case, the Lens.bin will encode the centers (I am assuming the image center and lens center do not align in this case). Modifying the lens center with the tool might help. Regards Shashank

Ticket Name: RTOS/TDA2EVM5777: changing PHY DP83865 to PHY DP83867IRPAP

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: DP83865, DP83867IRPAP-EVM Tool/software: TI-RTOS Background： Hardware Platform：TDA2x EVM Board Version：ASSY 516580 REV H Software Platform：SDK Version：PROCESSOR_SDK_VISION_03_04_00_00 Explanation： Originally，there are two PHY chips (DP83865) on the EVM board. When I intended to design a new board based on the EVM board，I found it’s very hard to buy the DP83865 chip. I want to verify the DP83867 can replace the DP83865 chip, so I designed a seprate new testing board used the chip DP83867IRPAP also from TI. When I removed the connection between the TDA2x chip and DP83865 chip on the EVM board, and then connect the DP83867 testing board, didn’t change any software configuration, I found it doesn’t work, printed “NDK: Link Status: 1000Mb/s Full Duplex on PHY 3”.But it didn’t establish connection successfully with PC. I want to know what can I do, I saw some codes relative with DP83867 in SDK, But I don’t know how can I use them. Can you offer me some solution? Thank you very much!

Hi Yongliang, If there was a connection problem, you wouldn't see the link status message. So, after printing the link status message, did it print the IP address of the EVM? Also, are you using static or dynamic IP? Regards, Anand

Hi Yongliang, It's been a while since I have heard from you. Were you able to solve this issue? Regards, Anand

No, I applied a DP83867IRPAP-EVM EVM board from TI, and I recieved it, and then I had a look, I found it's not very easy to solder strap resisitor on the board, and actually I don't understand why the TI can design their EVM board in that way.

Hi Yongliang, In TDA2Ex and some other EVMs, we use the DP83867. To use this PHY, we have to specifically configure the delays for the phy. If you check inside your vision sdk folder you should find this file \ti_components\networking\nsp_gmacsw_4_15_00_00\packages\ti\ndk\j6eco\examples_ipu1\client\j6eco_init.c. You should see a function to configure delays for dp83867. You can use the same function in your existing code when you use the custom board. This is the only change in 83867 I suppose. Let me know if this helps :) Regards, Anand

Thank you very much! I will try tomorrow, and I think I get your idea. I also compared my hardware configuration with the evm board which use dp83867. I think I can solve it next. Thank you for your quick reply.

Hi Yongliang, I understand that you're still facing trouble trying to get the PHY to work. Are you facing a HW problem? Have you tried the changes I have recommended Regards, Anand

I think hardware part is OK,and I also tried according your sugesstion, but it still dosn't work.I pasted the hardware board indicator video.

Below is the log, after I insert the phy delay function into my code, but it still dosn't work. Do you have any suggestions?

Hi Yongliang, Your logs tell me that the connection with the PHY is established. When you say your code isn't working, what exactly is the error? Are you able to get an IP printed in the console? Regards, Anand

I used static IP, and after I insert the PHY delay configuration function in my code, I can't successfully ping(command) with the board(PHY is DP83867), then I used my another board running same code(PHY is DP83865), the PHY DP83865 still can run correctly, I can easily feed video by my labtop to the board, so I guess may be my inserted function dosn't work anymore. I confused. Thank you for your reply!

Hi Yongliang, I believe the configureDelays function might not be getting executed. Can you put a breakpoint inside the function and see if it is hitting? Also, make sure that if there are any SoC specific if conditionals or # defines, comment them out so that the function blindly configures the delays for you. Regards, Anand

I printed some information in the configure delay function, and I saw the information from the initialize Log. I will check the platform related compile option next, after I get the result, I will reply you. I guess may be because of some ethernet related hook, have some limitation on calling the PHY configuration function.Thank you!

Hi Yongliang, It's been a while since I've heard from you. Were you able to go forward in this? Regards, Anand

Hi Yongliang, Any updates on this? Regards, Anand

Hi Yongliang, Since I have not heard back from you in a long time, I assume you have solved this issue. Regards, Anand

Ticket Name: TDA2SX: parallel computing on eve in cascade radar usecase

Part Number: TDA2SX Hi Experts, I'm trying to understand how the parallel computing on EVE cores was implemented in the cascade radar object detect usecase, but I can not find this place in source code. I'm interesting in how datacube is split between cores before horizontal FFT and vertical FFT. How data is split for peak detection? Did you use buffer's chunks for splitting? Can you tell me where I have to looking for? Maybe some documentation is exist on this? Regards, Igor

Hi Igor, Please refer to Ch 4 "TDA2x EVM + 4 AWR12 Cascade Capture, Object Detect, display" under [Radar SDK install]/vision_sdk/docs/Radar/ProcessorSDKRadar_DataSheet.pdf. Regards, Stanley

Ticket Name: CCS/TDA2: In ccs project/RTSC TOOLS/Platform/edit/view view ti.platforms.evmDRA7XX without this platform file

Part Number: TDA2 Tool/software: Code Composer Studio Use XDCtools version:3.32.1.22_core, Targets: ti.targets.arm.elf.M4 Platforms:ti.platforms.evmDRA7XX In ccs project/RTSC TOOLS/Platform/edit/view view ti.platforms.evmDRA7XX without this platform file

Can you elaborate more what the issue here is? Is it not running with the default selection/configuration? thanks, Alex

Hello, Friendly reminder, please send more details and we can discuss this further. thanks, Alex

Ticket Name: TDA2E: Issues running caffe trained SSD model on TDA2 development board

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Hello, I've used scripts 'train_image_object_detection.sh' to train SSD for detection. However, some trained models failed to run on TDA2 development board after conversion from tidl_model_import.out, the issues are: 1. It's does run for few frames, but then the output screen/detection process froze. 2. I only changed hyper-parameters listed in the 'train_image_object_detection.sh', but no matter how I changed ssd_size, resize_width/height, and ds_fac, the converted models still showed same error behavior. I've attached a converted caffe SSD (0420_3.7z) & a .caffemodel & deploy.prototxt & lable_map.prototxt (caffeModel.7z), would you please test it and perhaps offer any suggestion that might solve the issue? Thank you, Wei Chih 0420_3.7z 6724.caffeModel.7z

Hi Wei Chih, Did you get the default use case working at your end ? Also, which Vision SDK version you are using ? Thanks, Praveen

Hi Praveen: This is wxchen who is colleague with Wei-Chin, i was trying to inspect image by this transferred model by default usecase in TIDL OD(RTOS, TDA2EVM, 4-eves, Processor VisionSDK: 3.07), here is the manifest on SDK.Processor_SDK_Vision_manifest.html but the output was same as Wei-Chin's saying. by the way, i was trying to use pre-built binary(3.08), and load the network file to board, then i got the following error: [IPU1-0]  TIDL Usecases
[IPU1-0]  ---------------
[IPU1-0]  1: TIDL File I/O Usecase
[IPU1-0]  2: Semantic Segmentation Usecase
[IPU1-0]  3: TIDL OD Usecase
[IPU1-0]
[IPU1-0]  x: Exit
[IPU1-0]
[IPU1-0]  Enter Choice:
[IPU1-0]
[IPU1-0]     17.395199 s:
[IPU1-0]     17.421734 s:  TIDL Configuration parameters
[IPU1-0]     17.421826 s:  -----------------------------
[IPU1-0]     17.421887 s:  inputWidth         = 768
[IPU1-0]     17.421978 s:  inputHeight        = 320
[IPU1-0]     17.422039 s:  inputFile          = inData_OD
[IPU1-0]     17.422100 s:  inputFile          = inHeader_OD
[IPU1-0]     17.422161 s:  netFileName        = tidl_net_jdetNet_ssd.bin
[IPU1-0]     17.422222 s:  paramFileName      = tidl_param_jdetNet_ssd.bin
[IPU1-0]     17.422283 s:  inputfps           = 8
[IPU1-0]     17.422344 s:  threshold          = 0.200000
[IPU1-0]     17.422436 s:  -----------------------------
[IPU1-0]     17.517049 s:  Assertion @ Line: 103 in /adasuser/surya/vsdk_3_8_6/vision_sdk/apps/src/rtos/usecases/common/chains_common_tidl.c: readSize == sizeof(sTIDL_Network_t) : failed !!!
[IPU1-0]     17.517873 s:  Assertion @ Line: 103 in /adasuser/surya/vsdk_3_8_6/vision_sdk/apps/src/rtos/usecases/common/chains_common_tidl.c: readSize == sizeof(sTIDL_Network_t) : failed !!!
 wxchen

Hi Praveen, It turned out, it was the conversion mistake made by one of my coworker. It does run on the board as expected now. #update: It turns out only the newly cloned caffe-jacinto-model/scripts/train_image_object_detection.sh trained SSD models worked; every parameter left unchanged, and trained with my custom dataset Once changing parameters like ds_fac and ssd_size, the trained model will only run the first few frames on the board then froze. I will verify the change of ds_fac and ssd_size does make the trained models un-runable on the board tomorrow at work with the newly cloned caffe-jacinto-models again, then report back. Thanks a lot, Wei Chih

Hi Praveen, After cloning new caffe-jacinto-models, and use 'train_image_object_detection.sh' for training, I discovered that the models that used batch normalization for training cannot be ran on TDA2 dev-borad. Thank you, Wei Chih

Hi Wei Chih, Thanks for the update. Regards, Praveen

Ticket Name: TDA4VM: How to create a new Node/kernel in openvx framework

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi guys, I'm new to openvx, and I think in TDA2 series, we have the guide to introduce for how to create a new link then combine a new function chain. So in TDA4, do we have any guide to introduce of how to create a new kernel and then package to a new node? Thanks a lot. best regard, Neo

Hello, For OpenVX in TDA4, we recommend using the PyTIOVX tool for developing new kernels. We have an introduction section within our documentation for PyTIOVX below as well as some sample scripts located at tiovx/tools/sample_kernel_wrappers as well as vision_apps/kernels/<kernel_module>/scripts. While we have a basic documentation guide below, in future releases we will have a video series walking users through basic development using the PyTIOVX tool. In the meantime, please use this forum for any specific questions on how to use this tool. https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/tiovx/docs/user_guide/PYTIOVX.html In future releases, we plan on supporting sample application development using the PyTIOVX tool. However, for now, we recommend creating a new application based on existing applications found in vision_apps/apps. Regards, Lucas

Ticket Name: Linux/TDA2: vision_sdk build failed

Part Number: TDA2 Tool/software: Linux Excuse me ： i am building vision_sdk follow VisionSDK_Linux_UserGuide 3.1 Build Linux Vision SDK for Video Capture and Display use-cases step 5. Build the sdk $>make –s –j depend $>make –s –j execute make –s –j depend For a moment, the virtual machine is automatically restarted. After restarting, the reexecution will be wrong. execute make –s –j is also have this problem , and no application’s .out file , and no respectively in ti_components/os_tools/linux/targetfs/opt/vision_sdk

Hi , The virtual machine is automatically restarted might be for some other reason. Check the permissions of the folders and size allocated . For linux you need to build the kernel , follow user guide make linux, make linux_install make -s -j depend make -s -j Regards Chetan.M

virtual machine insufficient memory

Please run all the steps after increasing the memory and then tar the filesystem Regards Chetan.M

Ticket Name: Linux/TDA2: how to use lib in alg_plugins

Part Number: TDA2 Tool/software: Linux vision_sdk\sample_app\src\rtos\alg_plugins\framecopy in framecopy link, i add my algorithm Interface function after framecopy is done， Initialization add in Alg_FrameCopyCreate . it Include 10 .c file and 8 .h file , i add .c file name in SRC_FILES.MK to Compile them. so add my souce code is success， now i first use ccs Compile my souce code create my.lib. then in vision_sdk\sample_app\MAKEFILE.MK i add APP_LIBS_c66xdsp_1 += $(ROOTDIR)/my.lib APP_LIBS_c66xdsp_2 += $(ROOTDIR)/my.lib but failed follow is the log # Making tda2xx-evm:c66xdsp_1:release:vision_sdk_lib... make[7]: *** No rule to make target `/home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/my.lib', needed by `/home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/sample_app/tda2xx_evm_linux_all/vision_sdk/bin/tda2xx-evm/vision_sdk_c66xdsp_1_release.xe66'. Stop. make[6]: *** [c66xdsp_1] Error 2 make[5]: *** [apps_dsp1] Error 2 make[5]: *** Waiting for unfinished jobs.... # Making tda2xx-evm:arp32_2:release:vision_sdk_lib... # Configuro done! # Configuro done! BESTWISHES!

Hi, What you want to do? 1> Build your lib using your .c and .h files? 2> Use the lib built by CCS in framecopy algorithm? Regards, Anuj

Hi: Anuj framecopy algorithm is a algorithm link ,now it done framecopy algorithm then add myself algorithm. so i donot have to make a new algorithm link. Now do you understand what i have to do ? then i put all my source file(10 .c file and 8 .h file) in vision_sdk\sample_app\src\rtos\alg_plugins\framecopy , i add .c file name in SRC_FILES.MK to Compile them , i add my algorithm Interface function after framecopy is done， Initialization of my algorithm add in Alg_FrameCopyCreate . this way is success, my algorithm is run ,result is correct. promblem is come in. i have to compile my source into libraries, in framecopy algorithm call the lib(i use CCS compiled it and creat my.lib, and put my.lib in vision_sdk Folder), in vision_sdk\sample_app\MAKEFILE.MK i add APP_LIBS_c66xdsp_1 += $(ROOTDIR)/my.lib APP_LIBS_c66xdsp_2 += $(ROOTDIR)/my.lib when i make the vision_sdk it have some problem follow is the LOG. # Making tda2xx-evm:c66xdsp_1:release:vision_sdk_lib... make[7]: *** No rule to make target `/home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/my.lib', needed by `/home/hancan/PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/binaries/sample_app/tda2xx_evm_linux_all/vision_sdk/bin/tda2xx-evm/vision_sdk_c66xdsp_1_release.xe66'. Stop. make[6]: *** [c66xdsp_1] Error 2 make[5]: *** [apps_dsp1] Error 2 make[5]: *** Waiting for unfinished jobs.... # Making tda2xx-evm:arp32_2:release:vision_sdk_lib... # Configuro done! # Configuro done! do you know what is my problem? BESTWISHES! shuai

Hi, 1st thing where you have added your lib in makefile thats not correct. If you add there then it will try to create that lib using your source file. Please go through the makefiles and try to undertsand how it works. 2nd thing, you said that you are building your library in ccs so that is not right way as CCS might use different toolchain than VSDK. So try to create your library using VSK toolchains only 3rd if you want to use your lib in a link then take reference of encoder module, How an encoder link uses encoder lib. You can find the path of encoder libs in build/tools_path.mk Please go through below docs vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_DevelopmentGuide.pdf vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_BuildSystem.pdf Regards, Anuj

Part Number: TDA2 Dear, Please provide safety analysis reports and FMEDAs ? Thanks

Hello Joseph, Can you please get in touch with your TI representative for these details? You would need an NDA to access this information. Thanks and Regards, Piyali

Ticket Name: TDA2HF: tda2 Resetn and PORz

Part Number: TDA2HF Other Parts Discussed in Thread: TDA2 Hello team, Acoording to the TDA2 Data manual，RESETn and PORz should be deasserted simultaneously during power-up. If no, what will be affected.The system will run unstable or not. I have a case,RESETn and PORz released not simultaneously.Will this be a problem.

Hello, It should not be a problem. Regards, Kyle

Ticket Name: TDA3XEVM: Lane Detection Algorithm Calibration

Part Number: TDA3XEVM Dear team, 1.For calibration Lane Detection algorithm we have followed User guide located in PROCESSOR_SDK_VISION_03_07_00_00\ti_components\algorithms\REL.200.V.LD.C66X.00.03.00.00\200.V.LD.C66X.00.03\modules\ti_lane_detection\docs\LaneDetection_DSP_UserGuide.pdf. Lane Detection was not smooth as we varied various parameters such as departThetaLeftMin,departThetaLeftMax,departRhoLeftMax ,etc for road with the camera holdings for different heights. Please let us know how to obtain current values (live) Theta and rho (theta1 ,theta2 ,Rho1 and Rho2) values printed on the consoles .This will help us to calibrate the road for Min and maximum values for theta1 ,theta2 ,Rho1 and Rho2 for different heights. Regards, Pradeep K

Dear team, 1. Any update ? 2. Do we have some calibration tool/ Reference tool to update the Theta and rho (theta1 ,theta2 ,Rho1 and Rho2) values for any given road? Currently we are not using CCES . Please let us know the above points how we can resolve? Regards, Pradeep K

Dear team, Please respond the above query.. The theta information is provided in terms of bin and not in degrees .How we can correlate the lane detection while setting the road map information. Regards, Pradeep K

We don't have a way to dump the running value of theta1 ,theta2 ,Rho1 and Rho2. These are not exposed by the algorithm library and we are not in a position to modify it. So, unfortunately, you need to use hit and trial to tune your parameters. Thanks, with Regards, Pramod

Ticket Name: TDA2: Can I run two kernels on EVE simultaneously?

Part Number: TDA2 Hi, I have a few questions related to EVE processing. 1. Is it possible to run two or more different kernels (vision algorithms) on the same EVE core simultaneously (not sequentially) working on the same input image? The chains will look as follows: Capture -> kernel1(EVE1) -> Display ; Capture -> kernel2(EVE1) -> Display 2. If yes, how the input and output buffers are taken care of? Regards, Shruti Joshi

Hi Joshi, Even through you have two chains, In reality the execution of kernel1 and kernel2 will be sequential on the EVE. Vision SDK takes care of the scheduling: task switching happens at buffer boundary and you don't have control over it. If the same captured image goes to kernel1 and kernel2, instead of 2 chains, I recommend a single chain with 2 branches: ------->kernel1----->display1 Capture--/------->kernel2----->display2 regards, Victor

Thanks Victor for the feedback! EVE has a scalar that runs BIOS. Isnt it? So it is posisble to run multiple kernels on the same EVE core. Right? Vision SDK framework 's links can run on the EVE Scalars and multiple such links can exist on same EVE scalar. Or on any other core DSP/MCU/A15 for that matter. isnt this understanding correct? When executing 2 kernels, what shared resources need to be carefully time shared? Is there any app note on this please? Thanks & Best Regards Feroz

Hi Feroz, Although it is possible to run multiple BIOS threads on one EVE, in practice we don't do that as it would result in very high context switch overhead. Kernels operate on per block basis. Each block of data must fit in a 16 KB memory footprint. Please refer to this post on more details about block processing: Having multiple kernels switching at a block level would be incur too much overhead. You can have task switching at each frame level but then you don't really need multi-threading on EVE itself. Your understanding is correct that the current Vision SDK framework can run have multiple links that exist on the same EVE scalar. The vision SDK would schedule each link sequentially on the same EVE scalar, with context switching happening at frame boundary. This simplifies things as so there is no resources sharing needed. regards, Victor

Thanks a lot Victor! Best Regards Feroz

Ticket Name: TDA4VM: Is there any solution for early boot?

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Is there any solution for early boot? I'm checking up TDA4VM PSDKRA and PSDKLA. I want the same as early boot solution in VISION SDK of TDA2. The below functions are that I applied in TDA2. 1. Receive video from camera. 2. Make and display surround view. 3. Start H.264 encoding and store the encoded data in DRAM during booting. 4. Run QT after booting linux and display QT gui using DispDistSrc link. The functions 1, 2 and 3 are executed in 4 or 5 seconds. Of course, these are executed in IPU before booting linux. If there are solution, patch, or guide for above functions, let me know that. Best Regards, Yousik Kim.

Hi Yousik Kim, 1 and 2 should be possible in less than 4 to 5 seconds. Let me check and get back to you on this. Regards, Brijesh

Hi Yousik Kim, 3 and 4 seems to be tough to achieve, since these features require Linux to be up.. Regards, Brijesh

Hi Brijesh, Thank you for your reply. I understood about 3 and 4. I want to apply even 1 and 2. But currently in SDK, it is possible after booting linux. I think below contents are needed. 1. mcu2_0 must be OpenVX host and has to manage shared memory before booting linux. 2. OpenVX host must be changed from mcu2_0 to mpu and mpu has to manage shared memory after booting linux. Could you provide the guide to apply that?

Hi, I think you dont really require to move OpenVX Host to R5F. If you use 1, SBL to boot Linux 2, use OSPI boot mode 3, use eMMC for filesystem storage. 4, Remove/disable unnecessary modules 5, Limit logging in Linux You should be able to achieve first frame to display in 4 seconds. I will let my colleague Keerthy J to provide more information on this. Regards, Brijesh

Ticket Name: TDA2EXEVM: Question about TDIL OD fps and input resolution of a model

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi, For my understanding, the larger input image size of a model, the lower fps on TDA2. When I test with 3 different input image size model, 768x320, 1080x635 and 1280x720, I got 22 and 5.47 and 9.65, respectively. Is this reasonable? I'm wounder what will make this happen. Thank you, Gary

Hi Gary, you can press 'p' when running the usecase to get statistics of the various links (including TIDL link) and see their input fps, output fps, processing time, etc. Can you try this and see if you can find what cause such behaviour? Regards, Yordan

Hi Yordan, Here are the statistics for two different resolution models. 1280x720.txt 1080x636.txt As I can see, 1080x636 model take more time in TIDL part. I use the same model but different resolution to train. If all settings are the same, is there any reason make this happen? Thank you, Gary

Hi Gary, >> As I can see, 1080x636 model take more time in TIDL part. Yes, this expected because this resolution is not suitable for SIMD optimization, as TIDL operates on blocks of 32x32, so you see some degradation compare to other resolutions. It is recommend to use resolutions that are multiples of 32 to get better fps. Thanks, Praveen

Ticket Name: TDA4VMXEVM: Building PSDK_RTOS_AUTO_j7_06 for TDA2pxevm

Part Number: TDA4VMXEVM Hey, is it possible to build the psdk_rtos_auto_j7_06_00_01 vision apps demos for TDA2pxevm? I like to test the singlecamera usecase on the tda2pxevm. The idea is to build instead for A72 and R5F, I build the vision apps for A15 and M4. Could that work? best regards, NIco

Hi Nico, For TDA2P you should use Processor SDK Vision package, psdk_rtos_auto_j7_06_00_01 vision apps demos are only supported for TDA4x. Regards, Rishabh

So you say it is not possible to use psdk_rtos_auto with tda2px? My aim is to debug the psdk_rtos_auto at the moment. best regards, Nico

Hi Nico, Yes it is not possible to use psdk_rtos_auto with tda2px. You should debug using TDA4 EVM. Regards, Rishabh

Hey Rishabh, so do I understand correctly that the whole concept of links and chains from psdk(for example 3.6) has been overthrown and in psdk_rtos_auto this is replaced by using tiovx? best regards, nico

Hi Nico, Links and Chains is TI proprietary API which was present on TDA2/TDA2 whereas OpenVX is an industry standard API. Hence in line with TI's strategy to move to open standards, links and chains have been replaced by TIOVX. Regards, Rishabh

Ticket Name: TDA2SX: How to implement IPv6 functionality in TDA2 before sending message data over UDP?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi team, Here's an issue from the customer may need your help: The IPv6 address protocol is used in TDA2 to send UDP message data. By creating a SOCKet, but failed, the code is as follows: static char src[] = "fd11::100"; static char dst[] = "fd11::200"; void main_Tx() { int udp6_socket, ret, ttl, on, addr_len; struct sockaddr_in6 saddr; struct sockaddr_in6 daddr; char buffer[] = "Hello World6"; Vps_printf(" DanS-----Network: start IPv6 interface main\n"); if ((inet_pton(AF_INET6, (char *)&src[0], &saddr.sin6_addr)) != 1) { Vps_printf("invalid ipv6 addr \r\n"); return ; } if ((inet_pton(AF_INET6, (char *)&dst[0], &daddr.sin6_addr)) != 1) { Vps_printf("invalid ipv6 addr \r\n"); return ; } addr_len = sizeof(struct sockaddr_in6); saddr.sin6_family = AF_INET6; saddr.sin6_port = htons(30000); daddr.sin6_family = AF_INET6; daddr.sin6_port = htons(40000); udp6_socket = socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP); if (udp6_socket == -1) { Vps_printf("create udp6_socket fail\r\n");//the codes are run and printed here Vps_printf("failed socket create (%d)\n",fdError()); return; } if (bind(udp6_socket, (struct sockaddr *)&saddr, addr_len)) { Vps_printf("udp6 bind addr fail, err : %d\r\n", 0); if( udp6_socket != (-1) ) fdClose( udp6_socket ); Vps_printf("\n== End Timeout Test ==\n\n"); //close(udp6_socket); return; } /* transmit */ ret = sendto(udp6_socket, &buffer[0], sizeof(buffer), 0, (struct sockaddr *)&daddr, addr_len); if (ret > 0) { Vps_printf("udp6 send %d bytes success \r\n", ret); } fdClose( udp6_socket ); //close(udp6_socket); return; } The error is reported in yellow section. a. The NDK_enable_IPv6 switch for the corresponding usecase has been turned on in TDA2. b. What else needs to be modified for IPv6 to function properly? Could you help give an example? Could you help check this case? Thanks. Best Regards, Cherry

Hi, Quick update: NDK version in NetWorking: ndk_2_24_02_31/NSP version: nsp_gmacsw_4_16_01_01. And may I know is there any update? Thanks and regards, Cherry

Part Number: TDA2 SD card boot, run ALG_TIDL on the DSP, what should you pay attention to? How to set “ Void chains_tidlDsp_SetAppPrms(chains_tidlDspObj *pUcObj, Void *appObj) ”like this : Void chains_tidlDsp_SetAppPrms(chains_tidlDspObj *pUcObj, Void *appObj) { chains_tidlAppObj *pObj = (chains_tidlAppObj*)appObj; /* Null Source Parameters */ setNullSrcPrm(pObj); /* TIDL Pre Process */ pUcObj->Alg_tidlpreprocPrm.outPad = TIDL_MAX_PAD_SIZE; pUcObj->Alg_tidlpreprocPrm.numOutputQueues = NUM_PIPELINES; pUcObj->Alg_tidlpreprocPrm.procMode = TIDLPREPROC_LINK_PROCMODE_RGBPAD; /* * Set the TIDL algorithm parameters for all the 'NUM_PIPELINES' instances. */ /* TIDL on DSP1 */ pUcObj->Alg_tidl_1Prm.cacheInvInBuf = 1; pUcObj->Alg_tidl_1Prm.cacheWbOutBuf = 1; pUcObj->Alg_tidl_1Prm.pAlgCreateParams = pObj->pAlgCreateParams; //pUcObj->Alg_tidl_1Prm.curCoreId = TIDL_COREID_EVE1;//myz pUcObj->Alg_tidl_1Prm.curCoreId = TIDL_COREID_EVE1; //pUcObj->Alg_tidl_1Prm.currLayersGroupId = TIDL_LAYER_GROUPID_EVE1;//myz pUcObj->Alg_tidl_1Prm.currLayersGroupId = TIDL_LAYER_GROUPID_EVE1; pUcObj->Alg_tidl_1Prm.ocmcAddr = NULL; /* Null Link */ if(TRUE == pObj->enableOutFileWrite) { pUcObj->NullPrm.appCb = dumpOutCb; pUcObj->NullPrm.appCbArg = pObj; } else { pUcObj->NullPrm.appCb = NULL; pUcObj->NullPrm.appCbArg = NULL; } }

Hi, Sorry, I did not under stand your question. the above function is used to set app prms for usecase running on dsp. Regards, Anuj

Hi, Anuj Yes, I set app prms for usecase running on dsp, but DSP operation results are wrong . Thanks, Mary

Hi, Actual TIDL alg runs on EVE only i.e. different convolution layers. Regards, Anuj

Hi, Anuj When I chose to run TIDL on eve, the result was correct. When I chose DSP to run TIDL, the result was wrong. I do not know why. For a simple example, when I run TIDL, I use usecase f: TIDL Usecase, and then select "1: DSP" to run the result is wrong, but when I choose "2: EVE", the result is correct. Thanks! Mary

Hi, TIDL running on eve will give the proper result as it does the complete processing there. If you run TIDL on DSP then it will not do the complete processing for different layers so result is not proper. If you want to know the difference in processing of TIDL while running on DSP vs EVE. Then please raise a new thread with a proper subject and proper explanation of your question. Regards, Anuj

Hi, OK, Thanks! Mary

Hi, Please close the thread. Regards, Anuj

Ticket Name: TDA2: The GPMC interface of TDA2

Part Number: TDA2 Hi The GPMC interface of TDA2 has four chip selectable signals (CS0-CS3). May I ask if different chip selectable signals can be configured in different interface forms? For example, CS0 is set to multiplexed and N_Flash is used for Boot; CS3 is set to non-multiplex, and normal asynchronous memory interface is used to connect external devices. Thank you!

Hi, Yes you can connect different interfaces using different chip selects. You will need to set GPMC configuration accordingly. Regards, Rishabh

Ticket Name: TDA2: Understanding Best Suitable TDA2X processor for the Cascaded Design

Part Number: TDA2 Other Parts Discussed in Thread: AWR1243 Hello, I am trying to figure out the maximum possible 2D and 3D complex FFT size possible using TDA2x and TDA2px for our application. For the cascaded design that will hopefully be released in the first quarter of 2019 by TI, could you please tell me what is the exact part number of TDA2x that you have used? Based on the datasheet of TDA2X ADAS processors, from Pg 142, TDA2xxT is the best processor to use because it has the fastest DSP and EVE processing speed. Based on pg 6, TDA2SXx and TDA2SGx of TDA2Sxx subfamily is the best processor because it suits all the hardware requirements for supporting 4 AWR1243s together. Also, could you also tell me the max datarate that the videoports of TDA2x can handle? TDA2x has only 3 VIP ports present. Then how do you connect and transfer data from four AWR1243s to the three VIP ports? Could you please give a brief explanation to it? Thank you! Best Regards, Nishant

Nishant, The part number we use in the board is x5777 which is the pre-production part for the TDA2x device. This supports the mazimum speed grade mentioned in the Datasheet. For the exact number of FFTs that can be performed, I would advice you to feed your system configuration in the Radar System planner to see if your required usecase would fit in the device. TDA has 3 VIP instances. For the number of ports available for capture please refer to Figure 9-2. VIP Environment of the TRM. Here you would see each VIP has a slice. We are connecting the AWR1243 to VIN 1A, 2A, 3A, 4A. The data rate we are supporting from the default FPGA image is 150 MHz 16 bits which is sufficient for 2400 Mbps (600 Mbps 4-lane AWR configuration). Thanks and Regards, Piyali

Thank you Piyali for your help with all my questons! Best Regards, Nishant

Ticket Name: Linux/TDA2: question about vmem-exp

Part Number: TDA2 Tool/software: Linux hi , TI experts, I am using Linux usecase (OV490 3D srv ) in vision SDK 3.04.00. Now my problem is that the display output only tex[0], tex[3], tex[1] and tex[2] are same with tex[1], tex[3]. I find out in vmem-exp.c ( kernel driver ), vmem_export_single function export the 2 video virtual addr （such as 0xa7a2b000, 0xa7a2b500） to a same dmafd. It seems like the PAGE_MASK (4K Align) mask the offset(0x500). If this, how GPU map the correct physical address ? I mean, the same dmafd get 2 different address (such as YUV 0xa7a2b000, 0xa7a2b500) ? regards, John

Hello, This is a standard Linux limitation in Linux. DMABUF can be used only to export certain pages from the kernel For GPU, most likely, one of the following should work - just pass one dmabuf, GPU finds out the UV offset based on the size of Y - pass the same dmabuf for both Y and UV and provide offset values Regards, Nikhil D

Hi ,Nikhil thanks for reply. "- pass the same dmabuf for both Y and UV and provide offset values" In Vision SDK SGX drivers, I cannot find the provided offset values in System_eglWindowGetTexYuv(). For frameBuffer as below: Y1 Y2 UV1 UV2 It can only checkout the Y1 and UV1, Y2 and UV2 are missed. Can u give me more tips to find offset manipulation? regards, John

John, are you still facing this issue? I am closing this thread.

Ticket Name: Compiler/TDA2SG: Utils_setCpuFreq not work success

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2, SYSBIOS Tool/software: TI C/C++ Compiler Hi ,my eve is run in 900MHZ, when i want to dynamic adjustment ，i call the function “”Utils_setCpuFreq“” ，but that is no success。 I work in tda2s， LateAttach ，how can I do？

Hi, First of all, EVE in TDA2 doesn't support Dynamic frequency and voltage scaling at run-time. The frequency and voltage has to be set at the boot time and remains static. Utils_setCpuFreq() is not actually changing frequency or voltage. It is used to pass the CPU frequency value in to TI RTOS / SYSBIOS kernel so it can calculate the CPU load correctly based on OS timer. SDK doesn't provide any API to change frequency or voltage at the run-time. At the boot time, Secondary Bootloader (SBL) can program EVE to different frequency based on OPP selected at the build time. Regards, Stanley

Ticket Name: RTOS/TDA2: Why TIDL is NOT supported with Linux?

Part Number: TDA2 Tool/software: TI-RTOS Hi Team, Quick high-level question, why TIDL is NOT supported with Linux? Does it related to EDMA issue?

Hi, Please check below thread.. e2e.ti.com/.../702847 Thanks, Praveen

Ticket Name: TDA2: TDA2x EVM power cord

Part Number: TDA2 Hi, I purchased an tda2 evaluation module kit and i need to buy a power supplier. the shop recommends: Recommended Power Supply Options 12V, 5A, 65W compatible wall supplies Spectrum Digital Part# 701029-0001 CUI Inc. - p/n SDI65-12-U-P5 CUI Inc. - p/n SDI65-12-UD-P5 CUI Inc. - p/n SDI65-12-U-P6 CUI Inc. - p/n SDI65-12-UD-P6 Volgen America/Kaga Electronics USA - p/n KTPS65-1250DT-3P-VI-C-P1 But i need it quite urgently- can i purchase a power cord from anyone in Israel? Can i just use a random power cord that supplies the same V? also, is it the same power supplier as the TDA2 regular board? Thanks, S

Hi Stav, you can use a power supply with the following specs (check here: www.ti.com/.../TDA2EVM5777 ): 12V DC output 5A output Positive inner and negative outer terminals Female barrel with 2.5mm or 2.1mm inner diameter and 5.5mm outer diameter, insertion depth is 8.85mm Regards, Yordan

Ticket Name: TDA2: EVE Kernel C code in vision SDK

Part Number: TDA2 Hi, I try understand how to use VCOP and ARP32 in vision sdk. I read guides for EVE and found next steps: 1. Write kernel .k file 2. Get .obj file by cl-arp32 3. Compile ELF file I have some questions: 1. I have .k file. I have simple algorith in Vision SDK, that works on ARP32. What should I do to connect .k file with vision SDK algorithm plugin? 2. What is AlgIvision? It is used in EVE algPlugins run precompiled EVE library, it's right? Where I can read about it? 3. Also I met *.eve.lib in SDK, how can I get if i have .k file? Thank you for answers.

I have found answer on first question: 1. Add *.k file in SRC_FILES.MK like " SRCS_K_arp32_1 += <filename>.k " and define function prototype in .c file where it is called.

Hi Danil, Please find my answer's inline 1. I have .k file. I have simple algorith in Vision SDK, that works on ARP32. What should I do to connect .k file with vision SDK algorithm plugin? >>> refer answe for point 3. 2. What is AlgIvision? It is used in EVE algPlugins run precompiled EVE library, it's right? Where I can read about it? >>> Can you point to the file or folder which you are referring here? 3. Also I met *.eve.lib in SDK, how can I get if i have .k file? >>> These are the library generated when you build eve sw library. The same is located at <VSDK_PATH>ti_components\algorithms\eve_sw_01_xx_xx_xx. You can refer evesw_getting_started.pdf to see how to build these. If you add your kernel to the kernels\kernels_list.txt file it will get build and be part of libevekernels.eve.lib. This procedure can also be used for your first question Regards, Anshu

Hi, I found reference on AlgIvision in censusLink_algPlugin.c, functions AlgIvision_create(), AlgIvision_process()

Hi, You can refer <VSDK_PATH>ti_components\algorithms\eve_sw_01_xx_xx_xx\apps\docs\EVE_Applets_UserGuide.pdf chapter 2 to understand the ivision API's used in these functions. Regards, anshu

Ticket Name: TDA2SX: automatically inserts VLAN tags when sending Ethernet packets

Part Number: TDA2SX Hi TI experts, we use custom board with TDA2x and sending multicast packets, but we can't recieve it. After capturing packets through wireshark we discovered VLAN tags in packets header. We didn't enable VLAN Tagging at code or any configuration file. What's way to disable VLAN tags from Ethernet packets? Some additional information: 1) Device: TDA2x custom board 2) Operation system: TI RTOS 3) SDK version: PROCESSOR_SDK_RADAR_03_07_00_00 4) Ethernet interface: Configured at Eth0

I just add a some new information. When we change destination IP from 239.168.1.50 to 192.168.1.100 VLAN Tagging is gone. I can't understand why is multicast IP add VLAN tag?

Dmitry, there are similar report about the issue. we are investigating the driver. sorry for the extended delays. jian

Jian, Thanks a lot! I will wait for feedback.

Dmitry, I am putting a TI internal link here for internal reference. sorry you will not be able to see the ticket. I will close the ticket for now. If the issue is blocking your project, please reopen. Otherwise it will stay closed till the JIRA is resolved, then an update will be posted here. https://jira.itg.ti.com/browse/LCPD-28065 Jian

Ticket Name: TDA2SX: How to initialize McSPI in the IPU1_1 core

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hello, engineer （Based on the（PROCESSOR_SDK_RADAR_03_08_00_00）framework） I initialized McSPI in the IPU1_0 kernel， I use the API in the file utils_mcspi.c， and it worked properly.When I calling the same code on IPU1_1, code compilation passed normally, but there was an exception during startup, The code startup phase stops after the log “Putting MPU in Retention...” 。 I tried the following modifications （1）add utils_mcspi.c \ into SRCS_ipu1_1 in file vision_sdk\links_fw\src\rtos\utils_common\src\SRC_FILES.MK （2）add ipu1_1 into bsp_mcspi_default_SOCLIST in file ti_components\drivers\pdk_01_10_04_05\packages\ti\drv\bsp_lld\mcspi\bsp_mcspi_component.mk But neither operation works. So how can I use McSPI in the IPU1_1 kernel? Could you please give me some guidance and suggestions. Thank you.

TDA2 is new to me. Could you please provide some debugging suggestions，thank you.

now，the code can startup from sd card, when McSPI used in the IPU1_1 core, but when call "Bsp_boardSelectDevice(BSP_DRV_ID_MCSPI, BSP_DEVICE_MCSPI_INST_ID_1)" , the IPU1_1 core crash. the log as follow:

Ticket Name: Linux/TDA2: Linux + BIOS mode build a new use-cases

Part Number: TDA2 Tool/software: Linux When I refer to the documentation VisionSDK_UserGuide_BuildSystem.pdf to build my own usecase in Linux + BIOS mode，I have already completed step 9 （Open file \vision_sdk\apps\src\hlos\adas\src\common\chains_main.c） ，then i make -s -j to build，but There was an error （ error: implicit declaration of function 'MY_usecase_run' [-Werror=implicit-function-declaration] MY_usecase_run(&gChains_usecaseCfg); ）.I want to know more detail about function MY_usecase_run()，how to write the function of MY_usecase_run(). The Second problem is when i Generate usecase files use ./vsdk.exe –file configFile ，the next step is to write chains_newTestDisplay.c file ？ and how to write the chains_newTestDisplay.c file？ Thank you very much for answering me.

Hi, MY_usecase_run() (or you can choose a more descriptive name for your usecase) function is the entry point of your usecase and should be located in your chains_newTestDisplay.c file. You can take as example the function chains_vipSingleCam_SgxDisplay() which is called from vision_sdk\apps\src\hlos\adas\src\common\chains_main.c when certain menu item is selected (it is not called directly, but via Chains_menuSingleCameraRun() function, but you can get the idea). You can look how chains_vipSingleCam_SgxDisplay() and the usecase vip_single_cam_sgx_display (or any other usecase) is implemented to get directions how to implement your new usecase. You can also check chapter 2 "Use Case Development" in vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_DevelopmentGuide.pdf. Regards, Yordan

Hi, i have resolved my first problem by refer to the chains_vipSingleCam_SgxDisplay() . my new chain is UseCase: chains_newTestDisplay, NullSource (A15) -> Decode -> Alg_FrameCopy (A15) -> VPE -> Display . i refer to chains_nullSrc_Display.c to write my chains_newTestDisplay.c file, but when i run my usecase on the HW platform it crashed. the crash info is: [HOST] [HOST ] 806.707100 s: IPC_OUT_0 : Create in progress !!! [HOST] [HOST ] 806.707161 s: IPC_OUT_0 : Create Done !!! [HOST] [IPU2 ] 806.707344 s: IPC_IN_0 : Create in progress !!! [HOST] [IPU2 ] 806.708534 s: IPC_IN_0 : Create Done !!! [HOST] [IPU2 ] 806.708930 s: DECODE: Create in progress ... !!! ASSERT (frameCopyLink_algPlugin.c|AlgorithmLink_frameCopyCreate|369) [HOST] [HOST ] 806.938479 s: IPC_IN_0 : Create in progress !!! [HOST] [HOST ] 806.938937 s: IPC_IN_0 : Create Done !!! [HOST] [HOST ] 806.938998 s: ALGORITHM: Create in progress (algId = 0) !!! [HOST] [IPU2 ] 806.934697 s: DECODE: Creating CH0 of 1280 x 720 [1] [0],target bitrate = 10000 Kbps ... i want to know the rules or more detail to write the chains_newTestDisplay.c file. looking forward to answering me. Regards, Xie Baojian

Hi, there is a new thread about this issue: e2e.ti.com/.../694186 Experts has been notified and will reply there. I will close this one. Regards, Yordan

Ticket Name: TDA2PXEVM: Create an input file for a usecase that gets SYSTEM_BUFFER_TYPE_BITSTREAM data:

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 We have a tda2 VAYU application board and PROCESSOR_SDK_VISION_03_06 installed on my Ubunu 16.04PC. We are running tidl_od usecase. Our purpose is to create a new pair of index and mpeg file, that we can use in TIDL_SSD_CFG.TXT in order to run this example. Is there any documentation on how to create it? If so, can you direct me to it? Thanks

Hi Yoav, please check this E2E post: Regards, Yordan

Part Number: TDA2 Tool/software: TI C/C++ Compiler Hi experts, I'm trying to implement application code that is using openCV However, when I try to compile it, linking error occurs ( undefined reference error ) I checked header file declaration and it exists in proper directory It seems that using <opnecv2/objdetect> has a problem. Using <opencv2/imgproc> and <opencv2/core> works well... Please help me.. application.cpp--------------------------------------------------------------------------------------------------------------------------------------- .. #include "DMS_Algo_Typedef.h" ... void* openclDilationThreadFunc(void* args) { sDMS *DMS = new sDMS; .... } DMS_Algo_Typedef.h------------------------------------------------------------------------------------------------------------------------------- typedef struct sFaceDetector { sParam_faceDetector param_init; sParam_faceDetector param; cv::Rect faceROI; cv::Mat faceRoiImage; cv::CascadeClassifier classifier; cv::Rect face; unsigned char fFaceDetect; } sFaceDetector; ... typedef struct sDMS { // Face detection sFaceDetector faceDetector; // Eye detection sEyeDetector eyeDetector; // Object management sGlobalObject objects; // Image cv::Mat inputFrame; cv::Size imgSize; // State unsigned char detectState; } sDMS;

Are you using BIOS/Linux?

I'm using BIOS ~!

Hi Please refer ti_components\open_compute\opencv\opencv-3.1.0\docs\vayu_arm_bios_opencv_test_report.xlsx and use the modules which are listed in this report as pass and verified. Object detect module is not listed in this and hence has not verified so you should avoid using these. Thanks, Pramod

I should modify my code. Thanks a lot !

Ticket Name: Compiler/TDA2: Ethernet Issue

Part Number: TDA2 Tool/software: TI C/C++ Compiler hi, ethernet is not working properly. its connecting and disconnecting everytime thanks kalaiventhan

Hello Kalaiventhan, Can you please give more information about the platform and software used? Regards, Prasad

hi, i tried through QNX software for load some file one board working with Ethernet(1 gbs) ,another board is not working i think this board (100 mbs only) thanks kalai

Hello Kalai, I will ask our Linux/QNX expert to comment.

Hi Please provide additional information - the HW platform details(TI EVm vs customer board) , any failure logs (link status information etc) Usually the link negotiation part is in HW, SW only sets up the initial configuration. It would be good to review the HW schematics if it is for a new board design

Hi Kalai, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not please provide additional info that Sriram requested. Regards, Yordan

Ticket Name: TDA2HV: Will TDA2 device operate properly if VDD_RTC is disconnected from VDD (RTC SS not enabled) during usage?

Part Number: TDA2HV Other Parts Discussed in Thread: TDA2 A TI customer asks the following: "We would like to know what would happen if the VDD_RTC pin of the TDA2x device is not supplied. Currently, VDD_RTC is connected to VDD. Please know that we do not use the RTC sub-system in the design. Will the SoC work properly or can it hang?" On behalf of the customer, I searched the TDA2x Data Manual and Technical Reference Manual for instances of VDD_RTC. Reviewing the documents, I do not see any warning related to the question. I do see that VDD_RTC appears in the required power-up and power-down sequencing; however, I believe the customer's concern is related to a use case after power-up and before power-down. I searched the TI Public E2E database for VDD_RTC and TDA2, but I did not find any relevant posts about the topic. So, specifically: If VDD_RTC is tied high and becomes disconnected during normal use, what would happen to the SoC? Would it damage the device? Would it cause the SoC to hang? If the customer's system does not use the RTC sub-system, does the power-up and power-down sequence matter? Currently, the VDD_RTC is held high. With kind regards, Jason

Hi Jason, Datasheet has a footnote to Figure 5-2. Recommended Power-Up Sequencing regarding VDD_RTC: (4) vddshv5, vdd_rtc, and vdda_rtc domains: – If RTC mode is used, then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot be combined with other rails. – If RTC-mode is not supported then the following combinations are approved: – vdda_rtc can be combined with vdds18v – vdd_rtc can be combined with vdd – vddshv5 can be combined with other 1.8 V or 3.3 V vddshvn rails If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements. My understanding is that these are the possible connections for VDD_RTC (when RTC low power mode used/unused) found working by TI. Everything else (like VDD_RTC droop) can lead to unpredictable outcome. Regards, Stan

Hello Stan, I am grateful for your response; thank you! I saw the same note and considered it. However, the customer's key question has to do with momentary or prolonged disconnection of the VDD_RTC pin. Is it possible that the SoC be damaged? Is it possible that the SoC would reset or hang? I believe that because the pin is optional, the customer's configuration disables the RTC funtion and the pin is not connected the the PRCM, there would be no long-term damage or unexpected reset/hang. But I am not the expert. I only make an assumption based on past experience and what I've recently read in the Data Manual and Technical Reference Manual. Any way for you to comment? With kind regards, Jason

Hi Jason, just to update you: Stan is currently out of office and some delay in response might be expected. Regards, Yordan

Hi Jason, Sorry for late reply. The TI instructions are to keep all power supplies powered even if that part (e.g. RTS) will not be used. Typically, the device will operate normally, but long-term reliability WILL be affected, meaning that end-product must have this fixed (all power supplies connected and ramped as specified in datasheet). Regards, Stan

Thank you! I have shared this response with the customer.

Ticket Name: TDA4VM: TDAEVM-Fusion Daughter card connection & Power connection

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hello all, We would like to connect Fusion Daughter card with TDA4EVM CPBoard. https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/psdk_rtos_auto/docs/user_guide/evm_setup_j721e.html#j721e-som From the above link connector J25 is used for connection. How about the power cable connection ? It is not clear. Regards, Gokul

Hi Gokul, Attached is a picture of local working TDA4 EVM setup. For a TDA2 EVM setup the cables would be switched. Regards, Kip

Hello Kip, Images are not able to download. can you please check from your end ? Regards, Gokul

Hi Gokul, Were you able to get the Fusion board powered up/ Is it okay to close this thread? Thanks, Kip

Part Number: TDA2 Tool/software: TI-RTOS Using TDA2x with TI-RTOS, we can get live hdmi output. May I know 1) How to capture an image to sdcard? 2) How to capture an video to sdcard? Thank you very much.

Hi, You can use a null link in your usecase to dump the video into your sd card. Please refer to null_src_display usecase. In images what you want to dump? Encoded frame or a raw yuv frame? Regards, Anuj

Hi, Are you able to dump the video. If yes then please close the thread. Regards, Anuj

Ticket Name: TDA2EXEVM: File Structure and Explain the Hierarchy of Code Compilation and Execution

Part Number: TDA2EXEVM Hi, I am having problem in finding the proper document to understand the whole structure of this board. How it works, rather than just using the userguides to specifically execute the specific. I would like to learn how the code process works, including the main function which executes the module and creating an independent development environment by importing the library along with their documentation. Just consider that most of the developers who are willing to use this board have no background knowledge about this or Embedded systems, I believe. Thank you.

Hi Owais, you can look at this training for introduction of TDAx boards and VisionSDK: training.ti.com/tda2-and-tda3-processors-training-series Regards, Yordan

Ticket Name: TDA4VM: BAM plugins

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hello guys, I'd like to know more about the BAM plugins in VXLIB: http://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/vxlib_c66x_1_1_4_0/docs/doxygen/html/bamplugins.html What does "BAM block based processing framework" mean? Is it somehow related or similar to the User Kernel Tiling extension in OpenVX (https://www.khronos.org/registry/OpenVX/specs/1.1/html/d0/d84/page_design.html#sec_known_extensions)? Thanks for your help, Fernando A. Endo

Fernando, Fernando Endo said: What does "BAM block based processing framework" mean? This is a TI custom framework that uses DMA libraries to copy blocks/tiles of images into DSP L2 RAM in a ping pong fashion, and does tiling processing across a graph of supported kernels. If the graph has 3 sequential kernels, for example, then then one block of input is DMA'd to L2 RAM and processed through all 3 kernels using only L2 SRAM scratch memory for intermediate outputs, and then final output is DMA'd back to DDR. In parallel to the kernel processing, the DMA would have already retrieved the next block. This continues until the full image is processed through all 3 kernels. The benefit here is the faster processing due to data already being in L2 SRAM instead of latencies due to DDR access, as well as reduced overall DDR bandwidth as compared to doing all 3 kernels as full frame processing to/from DDR. The link you have given is from VXLIB documentation, which indicates which kernels have BAM plugins already available to be submitted in callbacks to the BAM framwork. In TIOVX documentation : you can see the TIOVX target kernel functions that are used to create BAM graphs within a target OpenVX kernel on C66. Fernando Endo said: Is it somehow related or similar to the User Kernel Tiling extension in OpenVX It is achieving a similar goal, but it is not using the Khronos Tiling extension. NOTE: As of PSDRA 6.02 release last week, the TIOVX and VXLIB components support BAM, however, the DMAUTILS component which BAM is dependent on has not been fully ported to TDA4x (this works on TDA2/3x if you want to prototype). This is planned, but since this functionality is deemed an optimization, it has been planned at lower priority to other functional features. Please let me know if you have further interest, and if you would like to use this feature, at what point will it be needed from a scheduling point of view.

Hello Jesse, Thanks for your help and insightful explanations. Jesse Villarreal said: Please let me know if you have further interest, and if you would like to use this feature, at what point will it be needed from a scheduling point of view. It depends on how fast computation can be with BAM. Do you have any pointer of speedups achieved in TDA2/3 compared to the non-BAM kernels? Kind regards, Fernando

In general, it depends on the kernel. If the kernel is highly bottlenecked by the memory IO latency, I have seen more than 2x improvement in performance. If the kernel is highly compute limited, then you may NOT see a big speedup. Regards, Jesse

Ticket Name: TDA2: How to make TIDL Test Clips

Part Number: TDA2 Hi, Our customer has an avi file that records the road. Our customer would like to use this file as a TIDL Test file instead of the inData_semseg file provided by TI. Please let me know how to make an avi file the TIDL Test Clips(inData_semseg file). Thanks JP Park

Hi JP Park, can you check if that thread can help you: e2e.ti.com/.../660676 Regards, Yordan

Hi Yordan Kamenov Thanks to you, the problem has been solved. Thanks for your reply. Regards, JP Park

Ticket Name: TDA2E: Counting an external signal edge

Part Number: TDA2E Other Parts Discussed in Thread: MMWCAS-DSP-EVM Hello. I need to count the rise or falling edges of an external clock signal which frequency is up to 300 kHz using the TDA2xx on the MMWCAS-DSP-EVM board (I just use the Ethernet peripheral so I can unmount lot of components if necessary). As you can imagine using an interrupt approach is not reliable at such high frequency, so, I intend to use a counter module that directly writes into a register the number of time the specific edge arrives. I took a look into "Timers" chapter inside TRM document (SPRUI29G) but it seams there is no way to increment the counter register using an external source. Could somebody provide me some guide? Which other module can I use to reach my goal? Thanks in advice, Pablo.

Hi, You can refer to TRM Ch 28 PWM which has eCAP to capture input signal. However, you have to check if EVM has exposed any pin which is routed to eCAP. https://software-dl.ti.com/processor-sdk-linux/esd/docs/06_03_00_106/linux/Foundational_Components/Kernel/Kernel_Drivers/Display/PWM.html Regards, Stanley

Ticket Name: CCS: The CortexA project of TDA2 established by CCS9.30 failed to link

Tool/software: Code Composer Studio Hi Team, The customer is experiencing below issue and needs your help. **** Build of configuration Debug for project A15_Null_demo **** "D:\\ti\\ccs930\\ccs\\utils\\bin\\gmake" -k -j 8 all -O Building file: "../startup_ARMCA15.S" Invoking: GNU Compiler "D:/ti/PROCESSOR_SDK_RADAR_03_08_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/bin/arm-none-eabi-gcc-4.9.3.exe" -c -mcpu=cortex-a15 -march=armv7-a -mtune=cortex-a15 -marm -mfloat-abi=hard -mfpu=neon -DTDA2xx -I"D:/ti_work2020/workspace_v9.30/A15_Null_demo" -I"D:/ti/PROCESSOR_SDK_RADAR_03_08_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/arm-none-eabi/include" -Og -g -gdwarf-3 -gstrict-dwarf -Wall -specs="nosys.specs" -MMD -MP -MF"startup_ARMCA15.d" -MT"startup_ARMCA15.o" -x assembler-with-cpp -o"startup_ARMCA15.o" "../startup_ARMCA15.S" ../startup_ARMCA15.S:1:0: warning: switch -mcpu=cortex-a15 conflicts with -march=armv7-a switch @****************************************************************************** ^ Finished building: "../startup_ARMCA15.S" Building target: "A15_Null_demo.out" Invoking: GNU Linker "D:/ti/PROCESSOR_SDK_RADAR_03_08_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/bin/arm-none-eabi-gcc-4.9.3.exe" -mtune=cortex-a15 -marm -DTDA2xx -Og -g -gdwarf-3 -gstrict-dwarf -Wall -specs="nosys.specs" -mfloat-abi=hard -Wl,-Map,"A15_Null_demo.map" --entry Entry -nostartfiles -nostdlib -static -Wl,--gc-sections -L"D:/ti/PROCESSOR_SDK_RADAR_03_08_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/lib/gcc/arm-none-eabi/4.9.3/fpu" -L"D:/ti/PROCESSOR_SDK_RADAR_03_08_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/arm-none-eabi/lib/fpu" -Wl,--defsym,STACKSIZE=0x10000 -Wl,--defsym,HEAPSIZE=0x400 -o"A15_Null_demo.out" "./main.o" "./startup_ARMCA15.o" -Wl,--start-group "D:/ti/PROCESSOR_SDK_RADAR_03_08_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/lib/gcc/arm-none-eabi/4.9.3/fpu/libgcc.a" "D:/ti/PROCESSOR_SDK_RADAR_03_08_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/arm-none-eabi/lib/fpu/libm.a" "D:/ti/PROCESSOR_SDK_RADAR_03_08_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/arm-none-eabi/lib/fpu/libc.a" "D:/ti/PROCESSOR_SDK_RADAR_03_08_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/arm-none-eabi/lib/fpu/librdimon.a" "D:/ti/PROCESSOR_SDK_RADAR_03_08_00_00/ti_components/cg_tools/windows/gcc-arm-none-eabi-4_9-2015q3/arm-none-eabi/lib/fpu/libg.a" -Wl,--end-group makefile:147: recipe for target 'A15_Null_demo.out' failed ./startup_ARMCA15.o: In function `Enter_BootLoader': D:\ti_work2020\workspace_v9.30\A15_Null_demo\Debug/../startup_ARMCA15.S:122: undefined reference to `_start' collect2.exe: error: ld returned 1 exit status gmake[1]: *** [A15_Null_demo.out] Error 1 gmake: *** [all] Error 2 makefile:143: recipe for target 'all' failed **** Build Finished **** Thanks, AnnieA15_Null_demo.rar

Could you check what causes the following error? ./startup_ARMCA15.o: In function `Enter_BootLoader': D:\ti_work2020\workspace_v9.30\A15_Null_demo\Debug/../startup_ARMCA15.S:122: undefined reference to `_start'

Ticket Name: TDA2EG-17: TDA2 EVE performance vs DDR

Part Number: TDA2EG-17 Hi Champs: Customer places the DDR as 1 channel, type, (not interleaving type. Here is their finding as the below ------------------ we found that DL accelerators on TDA2xx platform(EVEs) are running in parallel which processing independent frame on each core. It brings about system will increase frame rate by adding more EVE cores, but the system will get the similar latency by such upgrade. So, there are some problem related to achieve latency sensitive(<33ms, 30 fps) application on TDA2xx platform to our project. ------------------ Do we have the solution / comment to help them improves the Latency? BR Rio

Hi Rio, Apologies for delay in repose. Can you share the Standalone DL performance when you have only one EVE running and when you have all the EVE cores running the same DL in paralle.

Ticket Name: RTOS/TDA2E: NDK LLDP and SNMP support

Part Number: TDA2E Other Parts Discussed in Thread: TDA2, CC3200 Tool/software: TI-RTOS Hello Experts, One of our customers is looking for LLDP support with TDA2 devices. Does TI NDK support LLDP and SNMP? If not is there any plans to add that support? Thanks!

Hi Prasad, TI does not have SNMP support, but we've partnered with InterNiche who does supply it. We even have an example on processors.wiki.ti.com, but for the TM4C device (but still with the NDK). We basically supply just the binary to proof it works. processors.wiki.ti.com/.../TI-RTOS_SNMP We don't have source code since that needs to be worked out with InterNiche. InterNiche's contact information is on the examples page. Todd

Hello Todd, Thanks for your reply. Looks like SNTP offering from InterNiche is based on UDP and not LLDP. I will ask my customer to check SNMP offering from InterNiche. By any chance is there any plans to add LLDP support in NDK?

No current plans.

Hello Prasad, DMH Software offers SNMP-Agent implementation for the TI-RTOS SimpleLink platform. We built and tested the SNMP-Agent for TI-RTOS on the CC3200 Dev. Board. Please see more information here: www.dmhsoftware.com/ti-simplelink-iot-platform Please contact DMH for more information: info@dmhsoftware.com We will be happy to provide an evaluation SDK. Yigal Hochberg DMH Software

Ticket Name: TDA2P-ACD: RadarSDK of TDAx for AWR2243.

Part Number: TDA2P-ACD Other Parts Discussed in Thread: AWR2243, TDA2 Hello Support team. AWR2243 has been released. And then customer needs to use this AWR2243 instead of AWR1243P for cascade usecase. I understood that TI has delivered RadarSDK for TDA2P(TDA2/TDA3). (1) Can this Radar SDK support AWR2243 instead of AWR1243P ? (2) Do you have a plan to update RadarSDK in future ? Best Regards KORO

Hi Koro, The team is working to release a patch to support AWR2243 with Radar SDK. Meanwhile, there are few e2e threads talk about the workaround to make Radar SDK work with AWR2243. https://e2e.ti.com/support/sensors/f/1023/p/882929/3273642#3273642 Regards, Jitendra

Hello Jitendra-san Thanks a lot. O.K. It is good news to release patch. Br KORO

Ticket Name: RTOS/TDA2: example to store SRV image on SDCARD

Part Number: TDA2 Tool/software: TI-RTOS Dear Team, Is there any example to show how SRV video image can be stored on SD-CARD? My customer want to have an example to store combined image of 4ch SRV, but any usecase would be welcome. My customer is using VisionSDKv3.0. Thanks and Best Regards, SI.

Hi, Please use links_fw/src/rtos/links_ipu/dss_m2mwb/ link. Take a reference of the below usecase vision_sdk\apps\src\hlos\adas\src\usecases\avbrx_sv_display_avbtx Regards, Anuj

Ticket Name: TDA4VM: How to display chinese charactors on the screen with the Draw2D String function.

Part Number: TDA4VM HI ti: We are working on the TDA4 EVM. Now we need to display chinese charactors on our screen. I found that , there are several ASCII charactors fonts. Is there any tools to generate the *_font.c file ? Please help us. Tks a lot !

Hi Wang, There is not any utility to convert font. Font files just contains RGB565 value of the font.. You could search on below link to understand how to convert them. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/811499/rtos-tda2-string-font-setting https://e2e.ti.com/support/processors-group/processors/f/processors-forum/770547/tda3xevm-font-property Regards, Brijesh

Hi Brijesh, I have realized this function. Steps as below: 1、Use spacial tool to generate the chinese font 2、Compare the string to the font 3、Follow the font instructionst to draw the pixel. And if anyone want to get the c source file .Please click here. https://gitee.com/tda4/ti-tda4/tree/feature/ Also the chinese blog link is as below： blog.csdn.net/.../125503932 Good luck and best wishes !

In the upper left corner. 雨 means : rain 雾 means : fog

Ticket Name: Linux/TDA2PXEVM: TDA2P custom board - NVMe SSD - DMA Usage

Part Number: TDA2PXEVM Tool/software: Linux Hi TI, we are having issues while writing files to SSD (Intel Optane 900P) over NVMe using our custom TDA2P board. Write speed is good but the CPU load is around 80 percent. We would like to see if we are using DMA/eDMA for this transfer. The SW running on TDA2p is linux/SDK. Do you have propositions for lowering this CPU load? Regards, Stefan.

Hi Stefan, Can you please provide the commands used to write to SSD? Reason I ask is if commands such as dd are used it could involve mem copy increasing the load. Also can you provide a snapshot of top when the writes are performed. DMA can be used to write to the SSD, however with the SSD servicing as an EP the DMA writes must be triggered by the SSD (most end-points trigger DMA read / writes, host only programs registers to trigger events such as DMA copy). Regards Shravan

Hey Shravan, we are writing to a preallocated 8GB file (fallocate) and then just write (system write) to it. root@dra7xx-evm:/# top top - 12:01:23 up 6 min, 2 users, load average: 1.50, 0.66, 0.27 Tasks: 106 total, 3 running, 103 sleeping, 0 stopped, 0 zombie %Cpu(s): 0.2 us, 85.4 sy, 0.0 ni, 12.1 id, 2.1 wa, 0.0 hi, 0.2 si, 0.0 st KiB Mem : 1819728 total, 133908 free, 58388 used, 1627432 buff/cache KiB Swap: 0 total, 0 free, 0 used. 1715276 avail Mem PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND 1214 root 20 0 1208 456 288 R 75.0 0.0 0:35.31 a.out 75 root 20 0 0 0 0 R 70.1 0.0 0:08.41 kworker/u4:3 Regards, Stefan.

Hi Stefan, Can you confirm that you're A15 is running at 1.8GHz? Please set the scaling governor to "performance" by running the below command. echo "performance" > /sys/devices/system/cpu/cpufreq/policy0/scaling_governor Regards Shravan

Hi Shravan, we have modified our .dts file so it runs on 1800MHz. Please note the bolded part of the following command. root@dra7xx-evm:~# omapconf show opp OMAPCONF (rev v1.73-17-g578778b built Thu Aug 31 13:16:54 IST 2017) HW Platform: Generic DRA74X (Flattened Device Tree) DRA76X ES1.0 GP Device (STANDARD performance (1.0GHz)) Error: I2C Read failed Error: I2C Read failed Error: I2C Read failed UNKNOWN POWER IC SW Build Details: Build: Version: _____ _____ _ _ Kernel: Version: 4.4.84 Author: root@rtrkn096-lin Toolchain: gcc version 5.3.1 20160113 (Linaro GCC 5.3-2016.02) Type: #5 SMP PREEMPT Date: Thu Aug 16 14:47:18 CEST 2018 |-----------------------------------------------------------------------------------| | | Temperature | Voltage | Frequency | OPerating Point | |-----------------------------------------------------------------------------------| | VDD_CORE / VDD_CORE0 | 42C / 107F | NA | | NOM | | L3 | | | 266 MHz | | | DMM | | | 266 MHz | | | EMIF1 | | | 266 MHz | | | EMIF2 | | | 266 MHz | | | LP-DDR2 | | | 666 MHz | | | L4 | | | 266 MHz | | | IPU1 | | | (2128 MHz) (1) | | | Cortex-M4 Cores | | | (1064 MHz) (1) | | | IPU2 | | | 2128 MHz | | | Cortex-M4 Cores | | | 1064 MHz | | | DSS | | | 192 MHz | | | BB2D | | | (2128 MHz) (1) | | | | | | | | | VDD_MPU / VDD_CORE1 | 43C / 109F | NA | | PLUS | | MPU (CPU1 ON) | | | 1800 MHz | | | | | | | | | VDD_GPU / VDD_CORE2 | 42C / 107F | NA | | HIGH | | GPU | | | 532 MHz | | | | | | | | | VDD_DSPEVE / VDD_CORE3 | 41C / 105F | NA | | NOM | | DSP1 | | | 750 MHz | | | DSP2 | | | 750 MHz | | | EVE1 | | | 535 MHz | | | EVE2 | | | 535 MHz | | | | | | | | | VDD_IVA / VDD_CORE4 | 43C / 109F | NA | | HIGH | | IVA | | | 532 MHz | | | | | | | | |-----------------------------------------------------------------------------------| Notes: (1) Module is disabled, rate may not be relevant. Regards, Stefan.

Hi Stefan, I've had the look at the driver and below are some observations / comments: 1. I don't think using DMA will decrease the sytem load. Since the SSD card acts as an endpoint, DMA is initiated from the SSD (and not the TDA2P board) 2. The load in the system could be due to the copies involved between user and kernel space To avoid user-space copies, you can use the splice commands. In your final use-case, you want to write camera streams to the SSD, the data from the camera streams is exported to Linux as a DMA-buf file-descriptor (refer Documentation/virt-mem-export.txt in the Linux kernel and /hlos/src/links/ipcIn/ipcInLink_drv.c in VSDK). Since the input is also a file, splice is a classic command to copy data between two files without copy between user-space and kernel space. You can find more information here. blog.plenz.com/.../so-you-want-to-write-to-a-file-real-fast.html Please note let the output file (file written to SSD), needs to still be pre-allocated using fallocate (in-fact comparison with and without fallocate is mentioned in the above blog-post). Regards Shravan

Ticket Name: TDA2: the detailed about Sgx3Dsrv

Part Number: TDA2 hi， Could you please tell me the output of the Sgx3Dsrv module？ What is the format of the output of the Sgx3Dsrv？ I mean is it YUV raw data or h264 compressed data？ What is the protocol of that packed stream data？ And the response data struct of code？

Hi Th output of Sgx3Dsrv module from the GPU (SGX core) is ARGB32, which is fed to the display HW of TDA2x SoC. No protocol for any packed stream data is used here, just elementary video stream is generated and displayed regards, Shiju

Ticket Name: Compiler/PROCESSOR-SDK-DRA8X-TDA4X: TDA4- Deep Learning question: Can we run the different network model (DeepLearning) on Different Core concurrently?

Part Number: PROCESSOR-SDK-DRA8X-TDA4X Tool/software: TI C/C++ Compiler Hi . Customer is using TDA2 as their current products now. We get a question: #1. Does TDA2 EX17 can run the different network model on different core concurrently? for ex: Arm to run TensorFlow SSDV1. EVE to run TensorFlow SpineNet? #2. Following #1, if TDA2 cannot do that, does TDA4 be able to do this? If yes, is there any document to address this? Thanks. BR Rio

SDK version ? Regards Vineet

Hi Vineet: Customer is always using / evaluating the newest SDK for TDA2/TDA4. Thanks. BR Rio

Hi Rio, Isn't this thread related to the following thread : https://e2e.ti.com/support/processors/f/791/t/956938 Regards, Anshu

Hi Anshu: Yes, those 2 E2E are the same, so, where is the solid answer for those 2 E2E? please specify. Thanks. BR Rio

Hi Rio, As I understand that Praveen is already looking into the other thread and I will ping him once again. Can we close this thread and get the reply in the other thread itself? Regards, Anshu

Ticket Name: TDA2SX: I2C bitbanging

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Dear Supporter, Due to short of I2C ports, we try to take I2C bitbanging solution. Is there any example of software demonstrated ways to implement such feature on TDA2? Thank you very much. Best Regards, Wilson Hung

Hi Wilson, We do NOT have any reference implementation on this. - Keerthy

Ticket Name: RTOS/TDA2: Lane Detection Algorithm in Rear Camera view

Part Number: TDA2 Tool/software: TI-RTOS Hi Everyone , I am trying to understand Lane Detection algorithm and I am referring to the "LaneDetection_DSP_Userguide.pdf" . I like to know whether it is possible to implement Lane detection algorithm in rear view camera . Is there any limitations if we implement the Lane detection algorithm in rear view camera . Regards , Surendar

It is designed for Front Camera configuration. If you have rear view similar to front camera view is should work. However it is not tested for rear view. If you have fisheye lens distortion, you may need to correct it before using this lane detect.

Ticket Name: TDA2: what does NDK_PROC_TO_USE mean?

Part Number: TDA2 Hi, I'm new for SOCs and vision sdk, and often meet NDK_PROC_TO_USE (Supported values: ipu1_0 ipu1_1 a15_0 none) parameter. But I can't find its function and how it influence. Where should I find any information about NDK_PROC_TO_USE parameter?

Hi Danil, NDK_PROC_TO_USE selects the CPU on which NDK (Network Developer's Kit) runs. “none” means NDK is disabled. On TDA3x SoC due to pinmux conflict when MMCSD is enabled (FATFS_PROC_TO_USE != none) NDK is disabled automatically by build system. Recommended values, On TDA3x, ipu1_0 On TDA2x, TDA2Ex - BIOS ONLY mode and AVB is enabled, ipu1_1 - BIOS ONLY mode and AVB is disabled, a15_0 - Linux+BIOS mode and AVB is enabled, ipu2 - Linux+BIOS mode and AVB is disabled, none You can check VisionSDK_UserGuide_BuildSystem.pdf and VisionSDK_UserGuide_NetworkTools.pdf in VisionSDK docs folder for details. Regards, Yordan

Ticket Name: TDA2: TDA2 DDR3L Circuit Design Changes

Part Number: TDA2 Other Parts Discussed in Thread: X5777BXGABC We made the following design changes for the DDR3L circuit in the TDA2 DEMO board: 1. X5777BXGABC only use DDR1 interface, do not use DDR2 interface; 2. Two 8Gb @16bit DDR3 SDRAM: Changed the manufacturer, the chip specification is the same as the DEMO board, the frequency is up to 1066 MHz, and the rate is 1600MT/s; 3. A 2Gb @8bit DDR as an ECC extension: Changed the manufacturer, the chip's capacity is different from the DEMO board (DEMO board 4Gb, more than 2Gb with an A15 address line), the highest frequency of 1066 MHz, the rate of 1600MT/s 4. pcb layout with DEMO board Please ask: 1. Does the X5777BXGABC software need to be adapted? 2. What software is available for DDR3 board level calibration and stress test tools?

It is possible that the software needs to be modified. For instance, the DMM and MPU memory adapter settings will need to be modified such that only EMIF1 is accessed when read/write requests are initiated by the CPUs, especially if the two EMIFs were previously interleaved. In addition, a larger density memory on ECC will impact the refresh timing such as tRFC. However in this case, tRFC should be calculated based off of the 8Gb part attached to data, which appears to match the DEMO board. It is recommended that you confirm register settings using the EMIF tools .xls : http://www.ti.com/lit/zip/sprac36 For calibration of the DLL ratios, it is recommended that you use hardware leveling. Best regards, Kevin

Ticket Name: CCS/TDA2: how can i do eve work in Visual Studio?

Part Number: TDA2 Tool/software: Code Composer Studio use c_intrinsics_host_port-0_91_00-Setup.exe i can emulation C66 code in Visual Studio. now i am do a eve project ，i am plan to do this in Visual Studio first then i have to move the code into CCS project and run it on the evm board! i make a new Visual Studio project and i put ti_ccsv7\ccsv7\tools\compiler\arp32_1.0.9\include\vcop\vcop.h in the project as many eve function is emulat is vcop.h #define VCOP_HOST_EMULATION 1. arp32.h and vcopmem.h also put in the project but complie have many problems in arp32.h vcop.h 179 IntelliSense: 未定义标识符 "VCOP_MEMVIEW" e:\ti6657\vc_program\eve_sample\eve_sample\vcop.h 2323 22 eve_sample 170 IntelliSense: 未定义标识符 "builtin" e:\ti6657\vc_program\eve_sample\eve_sample\arp32.h 108 14 eve_sample 153 IntelliSense: 不允许使用不完整的类型 e:\ti6657\vc_program\eve_sample\eve_sample\arp32.h 83 14 eve_sample 147 IntelliSense: 不允许使用不完整的类型 e:\ti6657\vc_program\eve_sample\eve_sample\arp32.h 73 14 eve_sample 错误 107 error C2374: “__attribute__”: 重定义；多次初始化 e:\ti6657\vc_program\eve_sample\eve_sample\arp32.h 82 1 eve_sample

Shuai, For visual studio build you only need to include vcop.h and define VCOP_HOST_EMUlATION in the build. EVE SW build system already supports host emulation build and you can use the following command ( after setting all the environment variables and visual studio environment variables) : gmake TARGET_PLATFORM=PC ( run this command from the top most directory of EVE SW). Regards, Anshu

Hi Anshu I am no want to build all the eve SW . i make a new Visual Studio project , in this try to run median3x3. i move code in the Visual Studio project (ti_SDK_VISION_03_02_00_00\ti_components\algorithms\eve_sw_01_18_00_00\kernels\imgsiglib\vcop_median3x3) like the image upstairs post.

Shuai, As mentioned earlier you need to define in your build VCOP_HOST_EMULATION = 1 for host emulation build. Regards, Anshu

Ticket Name: Linux/TDA2EXEVM: TDA2 - 'Undefined reference Error'

Part Number: TDA2EXEVM Tool/software: Linux Hi there, I am using vision sdk version 2.12. I am trying to add a new usecase in vision_sdk/hlos/examples/adas/src/usecase. The main function that I have used is Void chains_multichannel_analog_dvr(Chains_Ctrl *chainsCfg); which is defined in the corresponding usecase .c file. This function was called in vision_sdk//hlos/examples/adas/src/common/chains_main.c which includes a header #include <vision_sdk/hlos/examples/adas//include/chains.h>. The function was declared in the above mentioned header. While compiling I am getting the following error.(earlier there some use-cases which are working fine) ----------------------------------------------------------------------------------------------------------- # vision_sdk_linux_demo: tda2ex-evm: Compiling chains_multichannel.c # vision_sdk_linux_demo: tda2ex-evm: Compiling chains_multichannel_priv.c # vision_sdk_linux_demo: tda2ex-evm: Compiling defLinkMultich_tsk.c # vision_sdk_linux_demo: tda2ex-evm: Creating archive vision_sdk_linux_demo.a # vision_sdk_linux_demo: tda2ex-evm: Linking /home/madan/McCDVR/mccdvr/Source/vision_sdk/binaries/tda2ex_mccdvr_all/lib/a15/release/vision_sdk_linux_demo.a(chains_main.o): In function `main': chains_main.c:(.text.startup+0x3e): undefined reference to `chains_multichannel_analog_dvr' collect2: error: ld returned 1 exit status make[4]: *** [exe] Error 1 make[3]: *** [apps] Error 2 make[2]: *** [demo] Error 2 make[1]: *** [vision_sdk_linux] Error 2 make: *** [vision_sdk_linux_all] Error 2 ------------------------------------------------------------------------------------------------------------ to be informed, i have included the new use-case in the following files, in configs/cfg.mk LINUX_TDA2XX_UC_LIST = \ /*some more use-case inclusions*/ UC_vip_2CH_vdec_encode \ UC_multichannel_Analog \ in system_cfg.h #define UC_vip_2CH_vdec_encode_no #define UC_multichannel_Analog in uc_cfg.mk UC_vip_4CH_vdec_display=no UC_multichannel_Analog=yes and in MAKEFILE_adas.MK ifeq ($(UC_multichannel_Analog),yes) $(MAKE) -fMAKEFILE.MK -C$(vision_sdk_PATH)/hlos/examples/adas/src/usecases/multichannel_Analog MODULE=vision_sdk_linux_demo $(TARGET) endif and also have checked make make showconfig ans i have the below information. # Use-cases included in build, # UC_cabin_channel_dvr UC_front_channel_dvr UC_McCDVR_TriChannel UC_multichannel_Analog # How can i solve this. Regards Balaji T

Hi Balaji, Lets Check with an existing UC where all it has been added & you need to do similar changes for newly added UC 1. Run grep command for an existing UC folder, check where all it has been added grep -ri "vip_single_cam_sgx_display" from vision_sdk folder 2. Run grep command for an existing UC entry function name present in .c file & check where all it has been added grep -ri "chains_vipSingleCam_SgxDisplay" from vision_sdk folder 3. In similar places, you need to add your newly added UC 4. After adding in all places just do a clean build Regards Surya

Hi Surya, Hope you are doing well. My issue got resolved, in uc_cfg.mk UC_vip_4CH_vdec_display=no UC_multichannel_Analog=yes(space)- i had given this extra space. Thank you Regards Balaji T

Ticket Name: Compiler/PROCESSOR-SDK-DRA8X-TDA4X: TDA4 u-boot.img

Part Number: PROCESSOR-SDK-DRA8X-TDA4X Tool/software: TI C/C++ Compiler Hi . #1. When I try to build the u-boot for TDA4, there is a directory output: --> /opt/ti-processor-sdk-linux-j7-evm-07_01_00_10/board-support/u-boot_build# ls a72 r5 And there are 2 u-boot.img in the A72 and R5 folder. this is the A72 : 1035136 Dec 21 17:22 u-boot.img , And in this folder of the pre-build, there are 2 u-boot.img. -rw-r--r-- 1 root root 1035160 Nov 20 04:57 u-boot.img -rw-r--r-- 1 root root 1035160 Nov 20 04:57 u-boot-j7-evm.img Can anyone explain which is the u-boot.img I need to flash into SD card? Why those files are having different size? #2. Besides, there is no any document to explain how to R5/A72 u-boot.img difference and how to use it. #3. I'm facing this issue: libfdt fdt_check_header(): FDT_ERR_BADMAGIC No FDT memory address configured. Please configure the FDT address via "fdt addr <address>" command. Aborting! Bad Linux ARM64 Image magic! So, I want to compile the u-boot.spl , which output of the SPL file can have this FDT imported? Do not tell me to do this: env default -f -a , since this solution never work on the newest SDK !! BR Rio

Hi Rio, TDA4 is pretty different when compared to TDA2. The RoM Code expects tiboot3.bin as the first image. Here are few details about the images that you need to compile and copy to SD card: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/latest/exports/docs/linux/Foundational_Components_U-Boot.html#u-boot-user-s-guide Look at the image formats section: tiboot3.bin contains the R5 SPL & corresponding DTB.. tispl.bin contains the A72 SPL, corresponding DTB & ATF/OPTEE u-boot.img the A72 u-boot.img. sysfw.itb that is dmsc/m3 binary. The above 4 binaries are must and should for you to boot. So to answer your questions: 1. under r5 please copy the tiboot3.bin & under A72 please copy tispl.bin & u-boot.img to SD card boot partition. (sysfw.itb can be copied from pre-built binaries) 2. https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/latest/exports/docs/linux/Foundational_Components_U-Boot.html#u-boot-user-s-guide Check the Image formats section. you will understand the difference very well. 3. First make use of $SDK_PATH/bin/mksdboot.sh script: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/latest/exports/docs/linux/Overview/Processor_SDK_Linux_Formatting_SD_Card.html?highlight=mksdboot#partitioning-sd-card This will create a working card & then on top of that if you make custom changes you can copy the Image & k3-j721e-common-proc-board.dtb to the boot folder of your rootfs partition. Best Regards, Keerthy

Hi Keerthy: #1. I have found this Jira, and after checking the patch, the patch is already inside the newest SDK. https://jira.itg.ti.com/browse/LCPD-19753 I have rebuilt my uboot A72/R5. and copied them into the SD card. However, this issue remains. #2. My SD card containing is as the below. root@ubuntu-vm:/opt/ti-processor-sdk-linux-j7-evm-07_01_00_10/board-support/prebuilt-images# ls /media/root/BOOT/ bl31.bin k3-j721e-common-proc-board.dtb k3-j721e-vision-apps.dtbo u-boot.img uenv.txt.jailhouse bl32.bin k3-j721e-common-proc-board-infotainment.dtbo sysfw.itb uEnv.txt uenv.txt.psdkra Image k3-j721e-common-proc-board-jailhouse.dtbo tiboot3.bin uenv.txt.base version Image-j7-evm.bin k3-j721e-pcie-backplane.dtbo ti-fs-firmware-j721e-gp.bin uenv.txt.disp_sharing ipc_echo_testb_mcu1_0_release_strip.xer5f k3-j721e-proc-board-tps65917.dtb tispl.bin uenv.txt.dra821a #3. To make it quick, may you share me your SD card contain files onto the TI drive? Thanks. BR Rio

Rio, All i am using is the SDK prebuilt binaries: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/latest/exports/tisdk-default-image-j7-evm.tar.xz Best Regards, Keerthy

Ticket Name: TDA2SG: TDA2 BOOT settings cause startup problems

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2, Hello expert We heard that if the hardware is set with two BOOT modes (SD card and QSPI FLASH), if the SD card of TDA2 is not disabled, there is a small probability that TDA2 will fail to start. I want to confirm whether there are other customers reporting this problem ? Is it necessary to change our current hardware BOOT configuration? (PS: The TDA2SG hardware BOOT of our current platform is set to sysboot[5:0]=000111, which can be booted from SD card and QSPI FLASH. We hope to achieve the following functions: After mass production, SOC can be booted from QSPI FLASH, and Upgrade the program in QSPI FLASH via SD card）

Hi, Which SDK version is being planned to be used in production? Best Regards, Keerthy

Hi,Keerthy We use version 3.07

Hi, The supported boot modes in tda2xx is: Which boot mode are you using? Refer the below thread if you want to flash the images to the QSPI memory. Thanks Gaviraju

Hi，Gaviraju We heard that there is a small chance that TDA2 cannot be booted from QSPI FLASH, when the hardware does not disable the SD card of TDA2, and the hardware has been set to two boot modes (SD card and QSPI FLASH). I want to confirm if there are other customers reporting this issue? Do we need to change our current hardware BOOT configuration? Our BOOT mode is shown in the screenshot, The TDA2x TRM version is Silicon Revision 2.0, 1.1 SDK version 3.07

Hi, On your board when you do not have the SD card with the above dip switch settings are you seeing that you see u-boot coming up from QSPI? Best Regards, Keerthy

yes, when I do not have the SD card with the above dip switch settings , u-boot coming up from QSPI is OK .

Hi, So the question is mainly with the consistency of the QSPI boot as back up boot mode when SD is primary correct? - Keerthy

YES , How can I solve this problem without changing the hardware BOOTMODE setting?

HI, user3378603 said: We heard that there is a small chance that TDA2 cannot be booted from QSPI FLASH, when the hardware does not disable the SD card of TDA2, and the hardware has been set to two boot modes (SD card and QSPI FLASH). Any document or e2e thread that is describing that? That would help me to check internally. Best Regards, Keerthy

It seems that he has not solved this problem

Thanks. I will check on this internally & get back by next week. Best Regards, Keerthy

Hi, I am yet to receive a response from our experts. I will revert back as soon as i hear from them. Best Regards, Keerthy

Hi, Our RoM code expert recommended NOT to use the settings(sysboot[5:0]=000111, which can be booted from SD card and QSPI FLASH) for production devices as SD boot mode has significant boot time impact before it switches to backup mode. Best Regards, Keerthy

Hi，Keerthy The hardware we designed requires a QSPI FLASH boot mode, so which boot modes TI recommends us to upgrade the code of QSPI FLASH without such problems? Best Regards

Hi, Could you please describe a bit more? I did not follow. QSPI as primary boot or secondary? - Keerthy

HI,Keerthy Our products are mainly started by QSPI_4 boot. According to the requirements of Table 29-9. Booting Devices Order in the TRM manual. When QSPI is used as primary, is it necessary to use "Automotive Production Booting" in automotive product applications? Is there anything wrong with using "Memory Preferred Booting" (0b10 0b0111) for automotive products? When QSPI is used as secondary, is there anything wrong with using "Peripheral Preferred Booting" (0b00 0b0111) in automotive products? Best Regards

Hi, I am yet to get a response from our RoM expert. I will keep you posted. Best Regards, Keerthy

Hi, For peripheral boot with SD followed by QSPI _4 production boot mode there is an errate which can prevent device the device booting from QSPI_4. So we definitely don’t recommend this setting and suggest to use memory boot for production. Best Regards, Keerthy

Thank you Keerthy , According to our current boot configuration(sysboot[5:0]=000111）, it seems that as long as the SD card is not inserted, there is no QSPI boot failure problem. By the way, is this problem in this Errata document? It seems that I did not find the relevant one! https://www.ti.com.cn/cn/lit/er/sprz397j/sprz397j.pdf?ts=1614580814431&ref_url=https%253A%252F%252Fwww.ti.com.cn%252Fproduct%252Fcn%252FTDA2SG%253FkeyMatch%253DTDA2%2526tisearch%253DSearch-CN-everything%2526usecase%253DGPN

Hi, You are right no public documentation. I will get back if i find one but for the thread can we resolve this or you still blocked? - Keerthy

Ticket Name: TIDL/Deep Learing Benchmark Performance and Support

Other Parts Discussed in Thread: TDA2, TDA2HV, TDA2HG Dear Sir, I have some queries with respect to DL model development on TI platform. Pl help me with my following questions. 1. TIDL document lists the results of a semantic-segmentation network running on the TDA2 SoC using TIDL - which version of TDA2. is it only on TDA2xP? 2. Is there Benchmark of any open source model ported on TDA2X for calculating the speed/processing time? 3. Does TIDL software package which is part of vision SDK supported on TDA2HG and TDA2HV 4. Is it possible to use custom layers which is designed by developer which are not part of TIDL package 5. Is there simulator support for TDA2H 6. Is there GPU support in TDA2H? Can we run deep learning model on GPU? or we need persist with EVE and DSP for model Inference 7. Is there simulator support for TIDL 8. Is TDA2H available for procurement in India immediately Thanks, Sachin

1.TIDL supported on TDA2x and TDA3x 2.Please refe out data sheet for layer level performance data also modles trained by TI. 3. TIDL is stansdalone package, Check you data manula for TDA2HG and HV. itf the part has EVE or DSP. yoyu cann run TIDL 4. You can split network into multiple partions and run with custom layer in between 5.We do not have simulator 6.Plase check yout data manula for GPU avialbilyt. TIDL does not use GPU 7.No 8.Please chack here www.ti.com/.../TDA2EVM5777

Ticket Name: RTOS/TDA3LX: TDA3 OPP_PLUS

Part Number: TDA3LX Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hi, My customer wants to increase the TDA3 DSP and EVE speed. I notice that the TDA3 can run in OPP_PLUS mode. For TDA2, I think the SBL code for OPP_PLUS has been already implemented in \PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\boot\sbl_auto\sbl_app\src, but I cannot find any detail information about TDA3 OPP_PLUS. I have several questions about the SW/HW OPP_PLUS configuration. Could you please provide more details about the OPP_PLUS of the TDA3. 1. How to configure the Software for OPP_PLUS for TDA3 by using SBL? Is it same as the TDA2? 2. How to configure the Software for OPP_PLUS for TDA3 by using GEL? 3. Any special requirements for the hardware or PCB ? Thanks, Frank

Hi Frank, TDA3xx OPP Plus is supported on a particular part i.e. TDA3xxS. In order to configure SBL for EVE 900 MHz and DSP 1000 MHz you need to set SBL_LIB_CONFIG_DSP_1000GHZ_EVE_900MHZ to 1 in PROCESSOR_SDK_VISION_03_07_00_00\ti_components\drivers\pdk_01_10_03_07\packages\ti\boot\sbl_auto\sbl_lib\src\tda3xx\sbl_lib_config_tda3xx.h. For gel you need to call TDA3xx_PRCM_Clock_Config_OPPPLUS_TDA3xx_15x15 API. Regards, Rishabh

Do you mean "TDA3SXX"? I can turn on the "OPP_PLUS" for the TDA3 on the D3 board now. Do I need additional cooling system for the chip? Also I notice that the video PLL will not work. Which function needs the video PLL? ISS capture? Video input port?

Hi, Can you specify the exact part that you are using in you system. I am not aware of thermal characteristics of D3 board so for cooling you need to check with D3 Engineering. Video PLL is needed by DSS. Hence in case of OPP Plus display won't work. Regards, Rishabh

Hi Rishabh, The part number of TDA3 on D3 board is xTDA3SXXBABFQ1. So I guess the TDA3SXX is the special part number that you were talking about, and B is the speed grade. Thanks, Frank

Hi Frank, xTDA3SXX is the ADAS superset part. To have 900/1000 frequency you need to have part with speed grade S. Please see Device Comparison table from data manual for different parts: http://www.ti.com/document-viewer/TDA3MV/datasheet/device-comparison-int-device-comparison#int_Device_Comparison Regards, Rishabh

Thank you. But why I can still turn on the OPP PLUS on this chip? I print the DSP and EVE frequencies by Chains_prfLoadCalcEnable(), and it shows that the DSP frequency is 1000 MHz and EVE is 900 MHz. I also can use OPP HIGH and the DSP freuqnecy = 745 MHz and EVE frequency = 666.67 MHz.

Hi Frank, As I mentioned previously xTDA3SXX is the ADAS superset part which is used for SW development. This part can be run at max supported frequency. However this part is not meant to be used in production. For production you will need to order one of the parts mentioned in Data Manual and depending upon the speed grade you will be able to set the EVE/DSP frequency. Hope this helps. Regards, Rishabh

Hi Rishabh, Thank you for your quick response. This could resolve my issue. Have a nice day. Best, Frank.

Hi Frank, I am closing this thread as issue has been resolved. Regards, Rishabh

Ticket Name: Linux/TDA2: OpenCV use case running Failed (Build via Linux)

Part Number: TDA2 Tool/software: Linux Dear TI: By configure as OpenCX, I got the OpenCV use case (in Linux in VSDK3.4) but got assertion when running the openCV use case: [HOST] [IPU2 ] 222.668974 s: CAPTURE: VIP1 Slice0 PortA capture mode is [ 8-bit] !!! ASSERT (chains_vipSingleCamOpenCVCannySgxDisplay_priv.c|chains_vipSingleCamOpenCVCannySgxDisplay_Create|166) Please advise. Thanks and best regards He Wei

More logs: ASSERT (chains_vipSingleCamOpenCVCannySgxDisplay_priv.c|chains_vipSingleCamOpenCVCannySgxDisplay_Create|166) [HOST] [HOST ] 90.233239 s: IPC_IN_0 : Create in progress !!! [HOST] [HOST ] 90.233605 s: IPC_IN_0 : Create Done !!! [HOST] [HOST ] 90.233697 s: ALG: ERROR: No alg create function specified (algId = 5) !!!

Hi He Wei, The issue has been fixed & will be available with next vision sdk release Regards Surya

Dear Surya, Thanks for the update. Can I have the patch first? (And what is the schedule for next VSDK release?) Thanks and best regards He Wei

Hi He Wei, PFA patch Follow the steps mentioned in Readme.txt file OpenCV_Fix.zip Regards Surya

Hi He Wei, VSDK next release will be available by mid of October Regards Surya

Dear Surya, Thanks a lot. it works now!! And just to confirm: the entire OpenCV 3.1.0 is pre-built (including object detection libs for linux) is in VSDK already? Thanks and best regards H e Wei

Yes, OpenCV 3.1.0 packaged with VSDK release contains pre-built libs only Regards Surya

Dear Surya, May I know the list of the openCV "pre-build libs"module for Linux? especially if it contains the object detection lib? I am trying to search in targetfs but can't find any libopencv*.a. And I try to build with object detection function but face error: "undefined reference to `cvHaarDetectObjects'" I have include the relevant header file. but no idea to check if the actual relevant libs are included in VSDK or not. I am bit stuck here. Please advise. Thanks and best regards He Wei

Dear Surya, I found in makefile. Thanks and best regards He Wei

Ticket Name: RTOS/TDA2: SerDes DS90UB933 can pair with DS90UB914

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, I see below from "Camera SerDes Overview" of TI web. I have TDA2 that mount DS90UB914Q deserializers and target camera module use DS90UB933 serializers. Because I have not EE resource can support. Could you please check can they pair? Is Pair the DS90UB933 serializers with DS90UB914Q deserializers? Thanks for your support.

Hi Prince, Atleast the 933 specs does not mention the support for 914 deserializer, so it will not work.. Rgds, Brijesh

Hi Brijesh, Understand. Thanks for your reply.

Ticket Name: TDA2E: Caffe jacinto Sparse Training Sparsity Question

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Hello, As title, I finished and saved a caffemodel after the sparse training with the total sparsity of 63% and everything seems normal and the model ran pretty fast on the TDA2 dev borad. However, when I used the model as pretrained model for sparse training tuning (sparse training will calculate the sparsity of the model before training), the output log is showing the model has the sparsity of 36% only. The displayed two different sparsity(s) to the same model confuses me, do you know what the issue is? Thanks, Wei Chih

HI Wei Chih, Could you please provide the log to understand the problem Thanks, Praveen

Hi Praveen, I will upload the log file to you tomorrow when I'm back to the office. However, let me try to explain it again: After finishing the sparse training, I got a 15000iter.caffemodel with 63% sparsity. But when I use the 15000iter.caffemodel as the pre-trained model for another sparse training, before the sparse training starts, caffe will calculate the sparsity of the input weights (15000iter.caffemodel), the calculated sparsity is showing 37% only. My suspicion is that the pretrained model's weights did not fully transferred to the new training model. Correct me if I am wrong, caffe will compare layers' name, if the layers name matched between the two models, then the weights will be copied/used. If not, initializing weights as defined in prototxt. Strangely I'm using the exact same model, the layers should be exactly the same, but it seems like not all the weights were used from the pre-trained model. Is this an expected behavior? If so, could you kindly explain what is happening behind the scene? Thanks a lot. Much appreciated, Wei Chih

Hi Wei Chih, I think we have not tried to use a sparse model as pre-trained for another sparse training. This flow may not be properly supported in caffe-jacinto. Thanks, Praveen

Ticket Name: TDA2SG: RSTOUTn release during power up

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Hello team, Customer tried two experiments about RSTOUTn -1) If RESETn is released before PORz, RSTOUTn outputs 2ms after PORz. -2) If RESETn is released after PORz, RSTOUTn outputs 2ms after PORz not RSTOUTn. According to the power up sequence in TDA2 data manual, RESETn to RSTOUTn delay is 2ms. But based on observation, RSTOUTn comes after PORz not RESETn. Please make clear which one between RESETn and PORz will make RSTOUTn release during power-up. The probed plot is attached in PPT file. Thanks, Lloyd Question about TDA2 RSTOUTn.pptx

Hi Lloyd, - PORz pin is a power-on, global cold reset. (i.e. system is being powered) - RESETn pin is a global warm reset (system was powered before, no need to reset everything again) - RSTOUTn pin allows other ICs in the system to get reset. This pin is asserted (low) on every global reset (warm or cold, software or hardware). The low signal gets extended for some milliseconds. In both of your cases 1) and 2), you are issuing a global cold reset. That's why RSTOUT gets deasserted after PORz. (not RESETn). Kindly try asserting a warm reset. This can be done by asserting low RESETn while system is running, and then desserting it. You should observe RSTOUT assertion, and deassertion with delay. Please note also that Data manual requires RESETn and PORz to be deasserted simultaneously during power-up. Therefore, it is no matter if note (14) says 'delay after resetn' or 'after porz', but in fact it is after PORz , so I will request documentation team to update the note. Thanks, Stan

Ticket Name: TDA2EVM5777: Caffe jacinto quantization API for model evaluation on computers

Part Number: TDA2EVM5777 Hello, Since the provided testing python script for caffe jacinto trained SSD models doesn't support quantization. I wonder does TI or anywhere else has the python API to quantize models for accuracy testing? The testing we are doing is not just hit or miss, but evaluating the offsets of accuracy in cm compare to ground truth. Thanks, Wei Chih

Hi Wei Chih, We do not support quantizing the models in Caffe - but you can do that directly in TIDL for TDA2x. But if your purpose is just to get an approximate sense of accuracy, we have it in our scripts. For example, this script: https://git.ti.com/cgit/jacinto-ai-devkit/caffe-jacinto-models/tree/scripts/train_imagenet_classification.sh has a last phase called test_quantize that reports rough accuracy with quantization. An example config file and log is captured here: https://git.ti.com/cgit/jacinto-ai-devkit/caffe-jacinto-models/tree/trained/image_classification/imagenet_jacintonet11v2/test_quantize But this has not been matched properly with what TIDL produces and may not always be correct. Your best bet is to measure the accuracy using TIDL. Best regards,

Ticket Name: TDA2: What is the DDR3L RAM max size supported using 16bits data bus width at each EMIF interface?

Part Number: TDA2 What is the DDR3L RAM max size supported using 16bits data bus width at each EMIF interface? Reference to the 'TDA2X Vision EVM Kit', if I change the RAM to 512MB (MT41K256M16TW-107) at each EMIF interface using only 16bits data bus width, can 16bits data bus able to support full 512MB RAM speed? Do I need to modify any software configuration setting from 'Linux and RTOS Processor SDK for Vision' to have it works upon boot up?

Hi, I have forwarded your question to DDR expert. For VisionSDK changes you can look at chapter "6 Memory map of the application" in VisionSDK_Linux_DevelopmentGuide.pdf and VisionSDK_UserGuide_MemoryMap.pdf in docs folder of VisionSDK and also this Application Note: www.ti.com/.../spraca1.pdf Regards, Yordan

If you use 2 x 8Gb (8-bit width) DDR3L memories on each EMIF, you would have 4GB total memory. Note that only the MPU can access greater than 2GB DDR memory. The data bus width does not impact the DRAM frequency.

Ticket Name: TDA2EVM5777: TDA2 FPD link Fakra connector

Part Number: TDA2EVM5777 Hello I saw the Fakra connector on the FPD link board as below CN15 is male Fakra, and is the CN16(NOPOP) female Fakra? we are finding the female Fakra connector,is there any vendor information of female Fakra? thank you

Hi, can you check here: www.rosenberger.com/.../fakra.php www.amphenolrf.com/connectors.html Regards, Yordan

Ticket Name: RTOS/TDA3XEVM: C66x CPU clock in the platform

Part Number: TDA3XEVM Other Parts Discussed in Thread: SYSBIOS, TDA2 Tool/software: TI-RTOS Hello, I have imported the example project "benchmark_TDA3x_C66xx" into the CCS 7.4 and selected the platform of TDA3EVM. This platform is taken from SYS/BIOS 6.53.1.03. I am wondering, why the CPU clock is set to 600 MHz. The C66x of the TDA3 is specified to 500 MHz. What is wrong here? By the way, the following includes in the benchloop.c file must be changed from /* POSIX module Headers */ #include <ti/sysbios/posix/semaphore.h> #include <ti/sysbios/posix/pthread.h> in to #include <ti/posix/ccs/semaphore.h> #include <ti/posix/ccs/pthread.h> Best regards, Milan

Hi Milan, I have forwarded your question to an expert for comment. Regards, Yordan

Hi Milan, This comes from a default definition from bios_6_XX_XX_XX\packages\ti\platforms\evmTDA3XX\package\ti_platforms_evmTDA3XX.java po.addFld("DSP", (Proto)om.findStrict("xdc.platform.IExeContext.Cpu", "ti.platforms.evmTDA3XX"), Global.newObject("id", "0", "clockRate", 600.0, "catalogName", "ti.catalog.c6000", "deviceName", "TDA3XX", "revision", "1.0"), "rh"); You are free to modify this in the project specific CFG file by setting: var BIOS = xdc.useModule('ti.sysbios.BIOS'); BIOS.cpuFreq.hi = 0; BIOS.cpuFreq.lo = 500000000; This will take effect for calculating the DSP software frequency. BTW, note niether of these settings actually dial up the PLL. I am not aware of the project benchmark_TDA3x_C66xx you mention. Can you please highlight where you have got this project from? Thanks and Regards, Piyali

Hi Piyali, thank you for your answer. I think the 600 MHz entry in the platform is an copy and paste error from TDA2 clocks. The project "benchmark_TDA3x_C66xx" comes from the TI Resource Explorer: I know, it is possible to set the clocks and memory settings with the SYS/BIOS cfg script. Is it possible to compile the software without the default platform or with a simple linker file? The separate platform handling makes the workflow too complicated. Best regards, Milan

Hi Milan, Thanks for pointing out the source. Since this is a BIOS based project, the first thing it will try to run is the XDC configuro step which looks for a platform. You can additionally add your own linker files but a base linker file will be created by this configuro step from the platform. It would help us, if you could kindly elaborate how you intend to use this project. We can check if there are any alternatives based on your feedback. Regarding the earlier comment regarding posix headers, you are right. It seems the example include paths correspond to older BIOS releases. I will inform our BIOS team to update this. Thanks and Regards, Piyali

Hi Piyali, I have chosen this project, because I want optimize an algorithm for the C66x with time measuring possibility. By this way I recognized that the CPU clock was set wrong in the platform, so that the time measurement can not be correct. The DSP runs with 500 MHz. Additional the CPU clock is also set wrong in the SYS/BIOS config. This is why I ask for to bypass the platform completely and to disable the XDC configuro. I would like to handle this configurations in the SYS/BIOS config and additionally in the linker file. In case of multicore processors the best way for clear configuration (CPU-Clock, memory, sections,...) would be in a single file. Is it possible? Best regards, Milan

Hi Milan, If you are looking only for measuring the time for an algorithm on the DSP and do not really have any BIOS dependency, you can also use a standalone non RTSC based CCS project. For profiling you can use the TSC timers in the C66x which run a the C66x frequency. I am copying the assembly code to read the timers for quick reference: .global _CSL_tscEnable .global CSL_tscEnable _CSL_tscEnable: BNOP B3, 4 ; MVC A4, TSCL ; Initiate CPU Timer by writing to TSCL .global _CSL_tscRead .global CSL_tscRead .sect ".text:cslsys_section:tsc" _CSL_tscRead: BNOP B3, 2 ; Branch Return Pointer MVC TSCL, B0 ; Read TSCL MVC TSCH, B1 ; Read TSCH || MV B0, A4 MV B1, A5 extern void CSL_tscEnable(void); extern CSL_Uint64 CSL_tscRead (void); Thanks and Regards, Piyali

Ticket Name: TDA2: complie tda2xx_evm_linux_opencx error

Part Number: TDA2 the error info ,is as flow: where i Can get ti/opencl/bin/x86/clocl ??? # Configuro done! # Making tda2xx-evm:ipu2:release:vision_sdk_lib... # Linking into /home/disk4/install_dir/vision_sdk/binaries/apps/tda2xx_evm_linux_opencx/vision_sdk/bin/tda2xx-evm/vision_sdk_ipu2_release.xem4... # # # /home/disk4/install_dir/vision_sdk/binaries/apps/tda2xx_evm_linux_opencx/vision_sdk/bin/tda2xx-evm/vision_sdk_ipu2_release.xem4 created. # ‘/home/disk4/install_dir/vision_sdk/binaries/apps/tda2xx_evm_linux_opencx/obj/vision_sdk/tda2xx-evm/ipu2/release/vision_sdk_configuro/osa_mem_map.h’ -> ‘/home/disk4/install_dir/vision_sdk/links_fw/src/hlos/osa/include/osa_mem_map.h’ # system: tda2xx-evm: Compiling system_ipc.c # osa: tda2xx-evm: Compiling osa_mem.c # osa: tda2xx-evm: Compiling osa_remote_log_client.c # osa: tda2xx-evm: Compiling osa_remote_log_server.c # system: tda2xx-evm: Creating archive system.a # osa: tda2xx-evm: Creating archive osa.a Compiling OpenCL file copy.cl make[7]: /home/disk4/install_dir/vision_sdk/../ti_components/os_tools/linux/targetfs/usr/share/ti/opencl/bin/x86/clocl: Command not found make[7]: *** [copy.dsp_h] Error 127 make[6]: *** [opencl_build] Error 2 make[5]: *** [vision_sdk_linux_demo] Error 2 make[4]: *** [apps] Error 2 make[3]: *** [apps_exe_hlos] Error 2 make[2]: *** [apps_hlos] Error 2 make[1]: *** [apps] Error 2 make: *** [vision_sdk] Error 2

Hi, you need to apply file system patch and clone some components. Please follow chapter "2.4.2.2.4 Opencl supported package" from VisionSDK_Linux_UserGuide.pdf. Regards, Yordan

hello , i installed the opencl support package . but it still error. the error msg as follow: # links_a15_sgxFrmcpy: tda2xx-evm: Creating archive links_a15_sgxFrmcpy.a # links_a15_sync: tda2xx-evm: Creating archive links_a15_sync.a # osa: tda2xx-evm: Creating archive osa.a # system: tda2xx-evm: Creating archive system.a # links_a15_nullSrc: tda2xx-evm: Creating archive links_a15_nullSrc.a Compiling OpenCL file copy.cl >> WARNING: invalid compiler option --bc_file=copy.bc (ignored) "/home/disk4/install_dir/vision_sdk/../ti_components/os_tools/linux/targetfs/usr/share/ti/opencl/dsp.syms", line 9: error #10022-D: invalid option: --single_data_segment "/home/disk4/install_dir/vision_sdk/../ti_components/os_tools/linux/targetfs/usr/share/ti/opencl/dsp.syms", line 10: error #10022-D: invalid option: --no_entry_point warning #10247-D: creating output section ".stack" without a SECTIONS specification warning #10210-D: creating ".stack" section with default size of 0x400; use the -stack option to change the default size undefined first referenced symbol in file --------- ---------------- main /home/disk4/install_dir/ti_components/cg_tools/linux/ti-cgt-c6000_8.1.0/lib/rts6600_elf.lib<args_main.obj> error #10234-D: unresolved symbols remain error #10010: errors encountered during linking; "copy.out" not built >> Compilation failure make[7]: *** [copy.dsp_h] Error 255 make[6]: *** [opencl_build] Error 2 make[5]: *** [vision_sdk_linux_demo] Error 2 make[4]: *** [apps] Error 2 make[3]: *** [apps_exe_hlos] Error 2 make[2]: *** [apps_hlos] Error 2 make[1]: *** [apps] Error 2 make: *** [vision_sdk] Error 2

Hi, can you download ti-cgt-c6000_8.1.0 ( www.ti.com/.../8.1.0), place it under <install_dir>/ti_components/cg_tools/linux and add it to the path (export PATH=<path_to_dsp_compiler_8.1.x>/bin:$PATH) and give a try? Regards, Yordan

i sloved this problem , thanks a lot

Ticket Name: TDA2E: Flashing the TDA2 Image

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Hello, I am using Radar TDA2 SDK (PROCESSOR_SDK_RADAR_03_07_00_00). I have compilation on windows. I have compiled the SDK with following option set MAKEAPPNAME=apps set MAKECONFIG=tda2xx_cascade_bios_radar gmake -s -j8 depend gmake -s -j8 Now next step for me is to flash this image. So i started following the VisionSDK_UserGuide_TDA2xx.pdf under section 3.6 (load using SD card) so i opted for option 3.6.1 (Option 1: Steps to prepare a bootable SD card ) and made the card bootable. So i went to step 3.6.3 (Steps to generate MLO) and than i saw a new folder comes up under C:\PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\binaries\apps with name tda3xx_evm_bios_radar even thogh my compilation was for tda2xx_cascade_bios_radar. I guess it was ok. After this i did step 3.6.4 (Steps to generate appImage ). Now the document in section 3.6.5 says i need to copy this generated MLO and App files.(Once the AppImage and MLO are generated , Copy the MLO and AppImage at root folder of formatted SD Card) But i cannot able to see which App and MLO files i need to copy to root folder. My question form where i can get these files to be copied My folder structures are For vision_sdk\binaries\apps C:\PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\binaries\apps>dir Directory of C:\PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\binaries\apps 07/24/2019 08:26 AM <DIR> . 07/24/2019 08:26 AM <DIR> .. 07/23/2019 03:52 PM <DIR> tda2xx_cascade_bios_radar 07/24/2019 08:36 AM <DIR> tda3xx_evm_bios_radar Inside tda3xx_evm_bios_radar C:\PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\binaries\apps\tda3xx_evm_bios_radar>dir Volume in drive C is Windows Volume Serial Number is 4EAB-E65F Directory of C:\PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\binaries\apps\tda3xx_evm_bios_radar 07/24/2019 08:36 AM <DIR> . 07/24/2019 08:36 AM <DIR> .. 07/24/2019 08:36 AM <DIR> nor_flash_writer 07/24/2019 08:35 AM <DIR> qspi_flash_writer 07/24/2019 08:36 AM <DIR> sbl 07/24/2019 08:29 AM <DIR> ti 07/24/2019 08:26 AM <DIR> vision_sdk tda3xx_evm_bios_radar\sbl C:\PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\binaries\apps\tda3xx_evm_bios_radar\sbl>dir Directory of C:\PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\binaries\apps\tda3xx_evm_bios_radar\sbl 07/24/2019 08:36 AM <DIR> . 07/24/2019 08:36 AM <DIR> .. 07/24/2019 08:34 AM <DIR> mflash_uart 07/24/2019 08:34 AM <DIR> nor 07/24/2019 08:36 AM <DIR> nor_flash_writer 07/24/2019 08:31 AM <DIR> qspi 07/24/2019 08:35 AM <DIR> qspi_flash_writer 07/24/2019 08:32 AM <DIR> qspi_sd Can someone please tell me what and which files i need to copy into root folder of the SD card to use the Sw i bring up. This is the first time i am trying to bring up this board. Br Deepak Joshi

Hi Deepak, My suggestion will be to change MAKECONFIG in PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\build\Rules.make. When you tried to build SBL and AppImage make would have searched for TDA3 paths and failed. There will be a folder named sd under SBL and Vision SDK will have AppImage in sbl_boot folder. Please note that Processor SDK Vision and Processor SDK Radar are quite similar wrt infrastructure. So you can find similar paths in Radar release package Regards, Rishabh

Hi Deepak, The exact path is vision_sdk\binaries\apps\tda2xx_cascade_bios_radar\vision_sdk\bin\tda2xx-evm\sbl_boot\AppImage and vision_sdk\binaries\apps\tda2xx_cascade_bios_radar\sbl\sd\opp_nom\tda2xx-cascade-radar\MLO Regards, Rishabh

Hello Rishabh, Thanks for yours reply so now under C:\PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\binaries\apps\tda2xx_evm_bios_radar, I see Sbl folder which i will copy directly to root of the SD card. Now for the AppImage i went to the path suggested by you C:\PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\binaries\apps\tda2xx_evm_bios_radar\vision_sdk\bin\tda2xx-evm\sbl_boot. Do i need to copy only sbl_boot or the three image files which has been generated. Thanks once again for yours help. Br Deepak joshi

Hi Deepak, You only need to copy MLO and AppImage. In my second reply I have mentioned exact files. Regards, Rishabh

Hello Rishabh, Thanks once again checked yours second reply. Now i have MLO and AppImage. So one last question before i plug this in TDA2 Cascade board, my SD card will have only two files and it will boot up ? my SD card folder structure will look like this F:\>dir Volume in drive F has no label. Volume Serial Number is 5D38-3D40 Directory of F:\ 07/24/2019 02:32 PM 119,988 MLO 07/24/2019 02:35 PM 6,438,676 AppImage 2 File(s) 6,558,664 bytes 0 Dir(s) 61,295,820,288 bytes free So it has only two files AppImage and MLO. Br Deepak Joshi

Hi Deepak, Yes the EVM will boot up with only these two files. Regards, Rishabh

Ticket Name: CCS/TDA2: Vlib old version

Part Number: TDA2 Tool/software: Code Composer Studio Hi Where can we find VLIB version for host emulation？The latest VLIB version does not support host emulation, but we can not find old version of VLIB. 3.6.2 Installing VLIB package for host emulation Object detection source package relies on VLIB source package to build the target in host emulation mode. Install VLIB package and link the pre-built host emulation VLIB libraries against Object detection module. After installing VLIB, set the environment variable to “VLIB_HOST_INSTALL_DIR” to the installed directory like <install directory>\packages

This is only available as part of the source release. If you need the source release, you can contact your local TI representative.

Ticket Name: Compiler/TDA2EVM5777: GPU demo code

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler How to get GPU demo code ? It can run on Tda2x . How to get GPU development reference manual or get API about it?

Hi Henry, There are several examples for GPU that can be run on the TDA2, please refer to this documentation: https://processors.wiki.ti.com/index.php/DRA7xx_GLSDK_Software_Developers_Guide#Graphics_Demos_from_Command_Line to get started. The GPU development reference manual - the Software Developers Guide linked above is a good starting point to get started. You should also refer to the build instructions and look into the various code/examples to assist with development. Also, refer https://processors.wiki.ti.com/index.php/DRA7xx_GLSDK_Software_Developers_Guide#Using_the_PowerVR_Tools for additional tools to optimize/understand the performance of your application. Regards Karthik

Ticket Name: AM625: Comparison of gpu performance between AM625 and tda2

Part Number: AM625 Other Parts Discussed in Thread: TDA2, Hi Expert, Is there a gpu performance comparison between AM625 and tda2? Thanks Daniel

Hi Daniel, Here are the GPU specs of AM625: https://dev.ti.com/tirex/explore/node?node=AElcVr5KOuYgL.MzoxnzDw__XaWts8R__LATEST. I believe tda2 has SGX544 and it has more GFLOPS/Pixel fillrate compared to AM625 but it cannot support OpenGLES3.1 and Vulkan. Regards, Krunal

Ticket Name: Linux/TDA2E: vision SDK 3.02 A15 set clock freqency SysCtlClockSet()

Part Number: TDA2E Tool/software: Linux Hi, I would like to change a15 clock freqency. Can I use SysCtlClockSet() function to change clock freqency and use SysCtlClockGet() to check? If I can not use this function.Which function I can to use? Thanks yumei SysCtlClockSet()

Hi Yumei, do you run Linux on A15? You an check this guide how to configure A15 frequency: Also in Linux kernel Dynamic Voltage and Frequency scaling is enabled: Regards, Yordan

Hi Yordan I run Linux on A15. I try to use CPUFreq to change frequency. I want to run below code in my sdk folder(PROCESSOR_SDK_VISION_03_02_00_00/vision_sdk/build/),but it is failed. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- distclean
make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- dra7xx-evm_defconfig
make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- zImage -j8 it show error message like: make: *** No rule to make target `distclean'. Stop. make: *** No rule to make target `tisdk_dra7xx-evm_defconfig'. Stop. make: *** No rule to make target `zImage'. Stop. I see this code from this question last reply: https://e2e.ti.com/support/processors/f/791/t/648120?Linux-AM5728-CPU-frequency-scaling-support Did i run error path or error code? thanks Yumei

Hi Yumei, You need to build the kernel from the kernel folder and not from Vision-SDK. In the kernel folder (present in ti_components/os_tools), run the following commands to make kernel: make ARCH=arm omap2plus_defconfig ./ti_config_fragments/defconfig_builder.sh -t ti_sdk_dra7x_release make zImage make modules make MOD_INSTALL_PATH=<path_to_your_file_system> modules_install Then copy the zImage and the modules in the file-system to your target. To change the frequency you need to have CONFIG_CPU_FREQ_GOV_USERSPACE=y in the kernel config. Regards Shravan

hi When I run make zImage to sjow some error message below. warning: (INTEL_SOC_DTS_IOSF_CORE && MMC_SDHCI_ACPI && PUNIT_ATOM_DEBUG) selects IOSF_MBI which has unmet direct dependencies (PCI) # # configuration written to .config # warning: (INTEL_SOC_DTS_IOSF_CORE && MMC_SDHCI_ACPI && PUNIT_ATOM_DEBUG) selects IOSF_MBI which has unmet direct dependencies (PCI) make: *** No rule to make target `zImage'. Stop. Do I need to set up other things before make zImage? thanks Yumei

Hi Yumei, can you try the following: make ARCH=arm omap2plus_defconfig ./ti_config_fragments/defconfig_builder.sh -t ti_sdk_dra7x_release make ti_sdk_dra7x_release_defconfig make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- zImage make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- modules and see if you get errors? regards, Yordan

Hi Yumei, I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Hi Yordan I still show some error message when make zImage. But I continue run other step. I confuse about whith modules I need to copy to sd card. Because I find folder name modules in my sd card not a file. Thanks Yumei

Hi Yumei, what is the error you get? Regards, Yordan

Hi Yotdan below message is the error,when I run make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- zImage. drivers/built-in.o: In function `hip04_mask_irq': /home/autorad/PROCESSOR_SDK_VISION_03_02_00_00/ti_components/os_tools/linux/kernel/omap/drivers/irqchip/irq-hip04.c:98:(.text+0x1960): additional relocation overflows omitted from the output make: *** [vmlinux] Error 1 thanks Yumei

Hi Yumei, what are the changes you have compared to the original tag REL_VISION_SDK_03_02_00_00? Regards, Yordan

Hi Yoedan Do you mean to chage which file in sd card? Thanks Yumei

Hi Yumei, what are your changes in the kernel source code, compared to the default from the SDK? Are you able to compile it without any modifications? Regards, Yordan

Hi Yordan I cannot to compile it without any modifications. Because original code which I want to set frequency,it had been modified many times by the others. Thanks Yumei

Hi Yordan I cannot compared to the original code,because my original code which had been modified many times by the others. Yumei

Hi Yumei, are you able to build the kernel with "make linux" from vision_sdk/build directory? Regards, Yordan

Ticket Name: CCS/TDA2: TIDL EVE used case not hitting breakpoint

Part Number: TDA2 Tool/software: Code Composer Studio Hi, I am working on TIDL library and I have the following issue, I build the eve.out file in DEBUG mode and run it on TDA2x but the breakpoint does not hit main() function in tidl_tb.c file, instead it just runs continuously, and hence I am not able to debug the source code. Could you please tell me if I have to make changes in the GEL files. The build syntax I am using is gmake CORE=eve TARGET_BUILD=debug all Thank you Regards, Nithin

Hi Nithin, did you define EVE_SW_CONFIG to 1 in "TDA2xx_multicore_reset.gel" file and check?. #define EVE_SW_CONFIG 1 Thanks, Praveen

Hi Praveen, I tried that. But then I get this error. Trouble Reading Memory Block at 0xa58427a on Page 1 of Length 0x1: (Error -1065 @ 0xA584278) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.407.3) Thanks. Regards, Nithin

Hi Nithin, Can you try below steps and check, 1. Power-cycle the broad 2. Reset the EVE core before loading .out file Thanks, Praveen

Ticket Name: Compiler: VPE Link : Support for YUV420P

Tool/software: TI C/C++ Compiler Hello Everyone, Does VPE link support SYSTEM_DF_YUV420P format? I tried converting YUV420SP to YUV420P using Vpe Link, but it fails to set it. Instead it is setting SYSTEM_DF_YUV422I_YUYV format . Dont know why? And if, VPE does not support YUV420P format ,how can we add support for it in VPE? Regards, Neha

Hi Neha, VPE does support YUV420 to YUV420 output.. Can you share your create parameters? Rgds, Brijesh

Sure. Below is the function to set VPE parameters in the usecase. static Void TF_Algo_setVPEParams( VpeLink_CreateParams *pPrm, UInt32 numCh, UInt32 OutWidth, UInt32 OutHeight, UInt32 inCropWidth, UInt32 inCropHeight) { UInt32 chId; VpeLink_ChannelParams *chPrms; UInt32 outId = 0; pPrm->enableOut[0] = TRUE; for (chId = 0; chId < numCh; chId++) { chPrms = &pPrm->chParams[chId]; #ifndef TDA3XX_128MB_DDR chPrms->outParams[outId].numBufsPerCh = VPE_LINK_NUM_BUFS_PER_CH_DEFAULT; #else chPrms->outParams[outId].numBufsPerCh = 2U; #endif chPrms->outParams[outId].width = OutWidth; chPrms->outParams[outId].height = OutHeight; #ifdef YUV420P Vps_printf("YUV420P converted in VPE***********\n"); chPrms->outParams[outId].dataFormat = SYSTEM_DF_YUV420P; #endif chPrms->scCfg.bypass = FALSE; chPrms->scCfg.nonLinear = FALSE; chPrms->scCfg.stripSize = 0; chPrms->scCropCfg.cropStartX = 0; chPrms->scCropCfg.cropStartY = 0; chPrms->scCropCfg.cropWidth = inCropWidth; chPrms->scCropCfg.cropHeight = inCropHeight; } } Usecase is as follows: NetworkRx (A15) -> Decode -> Dup -> VPE -> Sync -> Alg_Plugin1 (DSP1) -> DssM2mWb -> Display_Video The dataformat received in Alg_Plugin1 is not set to SYSTEM_DF_YUV420P instead it is set to SYSTEM_DF_YUV422I_YUYV, don't know why? Please note I need to set "SYSTEM_DF_YUV420P", i.e YUV420 planar. Thanks, Neha

Please note: I want to convert YUV420 Semi Planar to YUV420 Planar. I want to process YUV420 Planar dataformat.

No module supports conversion from from 420SP to 420P.

Ticket Name: TDA2: user mode failing on tda2x with TIDL

Part Number: TDA2 Hi，dear I changed the cfg and used my pose model with TIDL. My pose model is imported successfully by TIDI import tool. However when running on the tda2x board, it failed with logs below. And I snapshot the file where error occurs . Could you tell me what is wrong with my pose recog model? The output of my model is arbitrarily float32 value or int32 value.

And if I want to show the output of my pose model which is a value matrix? Is there any tools for writing these output to the file?

Hi, You can refer to the overlay code (used for visualisation of segmentation output) in "AlgorithmLink_tidlpostprocProcess" function located in "apps\src\rtos\alg_plugins\tidl\tidlpostprocLink_algPlugin.c" file. Regarding the error from log, did you change anything in the config? If so please share config file and complete log for analysis? Thanks, Praveen

Tks for your advice. 1. We should concern one key point , my cnn case is pose regcog which you can just consider it as some input image data going through the pose model then output one float32/int32 value 2d matrix. Note that it is different from any mature case in TIDL. So please evaluate the change. 2. I just replace the ssd para/net bin with my pose cnn model para/net bin . Also I replace the segmentation para/net bin with my cnn model. Nothing else has been changed. 3. The log file shows the error which is nearly the same. You can see the picture above which shows the dos command window. F.Y.I

Ticket Name: TDA2: PROCESSOR_SDK_VISION_03_05_00_00 TIDL , CAFFE-JACINTO MODEL IMPORTING ISSUE for .BIN file generation

Part Number: TDA2 Hello Sir, I am trying to import the caffe jacinto example networks from github. I am following the TIDL_library_User Guide.pdf. section 3.6.4 Issue: 3. Now run the “importTestCases.bat” from the below path. a. {TIDL_install_path}\utils\tidlModelImport After following till step-3, Bin files are not created in the respective directory mentioned in the Process. when i tried to look to the log.txt file then it has message "Couldn't open inputParamsFile file: ..\..\test\testvecs\config\caffe_jacinto_models\trained\image_classification\imagenet_jacintonet11v2\sparse\imagenet_jacintonet11v2_iter_160000.caffemodel" I have cross-checked the path many times, but their is no issue in that. I have even checked the import text file for OutputNetfile path for .bin file, and it has also the same path,where it should generate the .bin file. Kindly do needful. Thanks and Regards, Vyom Mishra

Hi Vyom, you mentioned that you checked the path, but I noticed that when I clone the caffe_jacinto repo it is in directory "caffe-jacinto-models" while the document and import tool expect "caffe_jacinto_models. Can you confirm that your directory is with underscores and not dashes? Regards, Yordan

Hello Yordan, I had edited the same before only. I have found the reason for the above thread. So Now I am able to create .bin file. Solution: I just copied RE.TIDL folder to other drive and tried to execute the .bat file, it worked. Reason I found is that, due to long paths of the folder and files, the application is not able to execute those files. So it's better to move TIDL folder to the new drive to generate .bin files. Thanks and Regards, Vyom Mishra

Ticket Name: RTOS/AM5728: Video encode by IVA

Part Number: AM5728 Other Parts Discussed in Thread: TDA2, Tool/software: TI-RTOS hi, AM5728 and TDA2 have a IVA accelerator to encode video, in TDA2 rtos sdk i finde out rtos based program for video encoding is it possible to use that for am5728 ?? because for am5728 ti support IVA just for Linux ?!

Hi, Sorry the AM57x RTOS driver only support VIP and DSS, not IVA. There is not plan for this. Regards, Eric

Ticket Name: Linux/TDA2: system_cfg.h missing

Part Number: TDA2 Tool/software: Linux Dear , today i try to build my code but i found some error like that "system_cfg.h" is missing . please help me i am using linux platform thank you

Hi Vijender, Can you provide details on what you were building and the error log. Regards, Rishabh

Hello Rishabh this is the simple code " /** * main.c */ int main(void) { //app_init_a15(); App_init(); return 0; } " Error is like that >> Compilation failure subdir_rules.mk:7: recipe for target 'app_init_a15.obj' failed "/home/vijender/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/common/app_init/app_init_a15.c", line 81: fatal error #1965: cannot open source file "system_cfg.h" 1 catastrophic error detected in the compilation of "/home/vijender/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/common/app_init/app_init_a15.c". Compilation terminated. gmake: *** [app_init_a15.obj] Error 1 gmake: Target 'all' not remade because of errors. **** Build Finished ****

Hi Vijender, Were you able to build default Vision SDK Linux? Can you refer to VisionSDK_Linux_UserGuide.pdf for steps on Linux build. Regards, Rishabh

Ticket Name: RTOS: TDA2 RTOS bmp array heapmem

Tool/software: TI-RTOS Hello, We want to create a array for bmp of RGB888, and convert it to RGB565. When creating a array [1024 * 720 *3] and compile, we will get some error. We guess they are because of HeapMem, or overflowed ...etc But we can successfully compile when we create a array [640 * 480 * 3] Q1：Can we create a array [1024*720*3], and we can successfully compile ? Q2：where could we get information of heapmem setting from code or document ? Thank, Ting

Hi Ting, How are you allocating the array. Are you specifying some section or allocating from stack? What is the build configuration you are using? Regards, Rishabh

Hi Rishabh Thanks for your reply. I create a array and give it value, like "static const unsigned char bmp_test[] = { 117,104,85,69,56,37,30,19,2,73,......}" Counts of value are size of array, and now it is 1024*720*3. I have find some memory setting for A15, IPU...... But I don't know how to match my array Thank, Ting

Hi Ting, It seems that you are allocating buffer from stack, you need to allocate from UTILS_HEAPID_DDR_CACHED_SR. You can grep the same in Vision SDK to see how to use it. Regards, Rishabh

Hi Rishabh Thanks for your reply. Sorry, I have another thing to do, but I will grep "UTILS_HEAPID_DDR_CACHED_SR". Before I try that, maybe I can end this problem. When I get a new problem, I will ask a new question. Thanks, Ting

Hi Ting, Thanks. I am closing the thread. Regards, Rishabh

Ticket Name: Functional Safety ADAS

Other Parts Discussed in Thread: TDA2 Hi, I am relating to that thread: https://e2e.ti.com/support/arm/automotive_processors/f/1021/t/595646?TDA2HV-Functional-Safety-ADAS I am wondering why TI decided to not develop the TDA2x in compliance with ISO 26262 considering that everyone else is doing so. Is there a specific reason? Thanks and best regards, Samir

Samir, TI Jacinto TDAx automotive processors have a number of safety and security features supported in hardware including: Auxiliary Arm® Cortex™-M4 MPUs Hardware firewalls MMUs Memory ECC support Display write-back path Security accelerators Additionally, the TDA3 family includes: Clock, voltage and interrupt monitors Hardware CRC block Window watchdog timers and Other enhanced safety mechanisms for safe computation and AUTOSAR. The safety features enable customers to design systems that can achieve ASIL-B or higher safety levels. Could you help us understand the end equipment you are looking at ? We can help you map your safety and processing requirements to one of the devices of the TDA2/3 family of devices. Thanks and Regards, Piyali

Ticket Name: TDA2EVM5777: How much the performance varies in tda2 as compared to PC

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi, I have recently implemented the semantic segmentation using Caffe-Jacinto's Jsegnet on PC and TDA2 successfully with my own dataset which require two objects for pixel classification. However, the results I have got on PC are pretty much better than the results I got on tda2. Can you guys tell me why the performance has gone so lower on tda2, I believe it shouldn't be that worse. Thank you. With best regards, H.M. Owais

Hi , Yes, you are correct, it shouldn't be worse. Please refer to TIDL datasheet where we provided the performance of most of the semantic segmentation layers on EVE and DSP cores for checking the performance. Thanks, Praveen

Ticket Name: RTOS/TDA2: TDA2x: Invalid MultiProc id

Part Number: TDA2 Tool/software: TI-RTOS Hello, I'm working with a TDA2EVM5777 and use Vision SDK version 2.5 (old Version because of legacy reason). I wrote a new link and wanted to test it in a usecase. After compiling i try to load the program but got this message in the console: [Cortex_M4_IPU1_C0] IPU1-0 Remote Log Shared Memory @ 0xa0d00000 IPU1-1 Remote Log Shared Memory @ 0xa0d04010 HOST Remote Log Shared Memory @ 0xa0d08020 DSP1 Remote Log Shared Memory @ 0xa0d0c030 DSP2 Remote Log Shared Memory @ 0xa0d10040 EVE1 Remote Log Shared Memory @ 0xa0d14050 EVE2 Remote Log Shared Memory @ 0xa0d18060 EVE3 Remote Log Shared Memory @ 0xa0d1c070 EVE4 Remote Log Shared Memory @ 0xa0d20080 ti.sdo.ipc.Ipc: line 102: ti.sdo.ipc.Ipc: line 102: assertion failure: A_invalidMultiProcId: Invalid MultiProc id xdc.runtime.Error.raise: terminating execution [C66xx_DSP1] ti.sdo.ipc.Ipc: line 101: ti.sdo.ipc.Ipc: line 101: assertion failure: A_invalidMultiProcId: Invalid MultiProc id xdc.runtime.Error.raise: terminating execution What is the reason for this failure and how can i fix this?

Hi Julian, Will it be possible for you to try compiling this using VSDK 3.6 software-dl.ti.com/.../index_FDS.html If not can you share the changes you have made in a zip file? Regards, Rishabh

Thank you for the fast reply. In the used Project are links and a usecase which i need. They are not included in newer versions of vision sdk because its a project from someone else. For this reason i didn't compile it with a newer version of vision SDK. What kind of changes should I share? Only the Link i created or every file where i changed anything.

Hi, Can you share all files you changed on top of VSDK 2.5. Regards, Rishabh

All the files I change in the Project are in this file. I deleted the usecase to test the link. Only an unused link is left in the project. But then i get the same Error.

Hi Julian, Can you try to build VSDK 2.5 and run without these changes to check the sanity of system. Regards, Rishabh

Hi Rishabh, I can build and run VSDK2.5 without these changes. There is no Error in consol and I can choose the different usecases. I am sure that there are a few mistakes in my new link but I don'tunderstand why this Error happens so early without calling the new link in any usecase. Regards, Julian

Hi Julian, At a glance code seems fine. Can you add a while loop in the start of main application for DSP1 and then connect using CCS & debug further. Regards, Rishabh

Hi Julian, Is there an update on this? Regards, Rishabh

Hi Rishabh, Thank you for your help. I finally found my problem. In the Function MultiProc_getId there was something strange. UInt16 MultiProc_getId(String name) { Int i; UInt16 id; Assert_isTrue(name != NULL, ti_sdo_utils_MultiProc_A_invalidProcName); id = MultiProc_INVALIDID; for (i = 0; i < ti_sdo_utils_MultiProc_numProcsInCluster; i++) { if ((ti_sdo_utils_MultiProc_nameList[i] != NULL) && (strcmp(name, ti_sdo_utils_MultiProc_nameList[i]) == 0)) { id = i + MultiProc_module->baseIdOfCluster; } } return (id); } In the debugger I observed that the Variable 'i' started in the for loop with '-1' instead of '0'. I thought that maybe there was something wrong compiled. Therefor I used 'gmake -s all' instead of 'gmake -s' to rebuild everything. This solved my Problem. Regards, Julian

Hi Julian, Thanks for the confirmation. I am closing the thread. Regards, Rishabh

Part Number: TDA2SX Hi TI experts, I still have a problem with VLAN tags from related question. Have you any ideas? Best Regards, Dmitry

Ticket Name: CCS/J6EVM5777: load using nor FLASH in J6-EVM but error

Part Number: J6EVM5777 Tool/software: Code Composer Studio software : vision SDK 3.07 board: J6EVM(X5777) i want to load using nor , and Reference resources is doc-- "VisionSDK_UserGuide_TDA2xx.pdf" in sdk when i put sbl_nor_opp_high_a15_0_release.bin to board bu CCS, it is normal when i erase the nor flash and read file /********************************************************************/ [CortexA15_0] Starting NOR Flash Writer. CFI Query...passed. NOR Initialization: Command Set: Spansion Manufacturer: SPANSION Size: 0x40 MB Enter the file path to flash: DIR/sbl_nor_opp_high_a15_0_release.bin Erasing the NOR Flash upto range: 0xC000000 Erased through 0x8020000 ... ... ... ... Erased through 0xC000000 Erase Completed Load Options: ------------- 0 -> fread using code (RTS Library) 1 -> load raw using CCS (Scripting console) Enter Load Option: 0 Reading 101316 bytes from file... Read 16384 bytes [16%] from file... Read 32768 bytes [32%] from file... Read 49152 bytes [48%] from file... Read 65536 bytes [64%] from file... Read 81920 bytes [80%] from file... Read 98304 bytes [97%] from file... Read 101316 bytes [100%] from file. Done!! /********************************************************************/ but when writing the data to nor flash, it is comes error as follows: /********************************************************************/ Writing 0x18BC4bytes to NOR... Data verify failed. Buffered write failed @ address 0x%x Trying normal write Failed flashing @ 0x%x Normal write also failed NOR Write Failed...Aborting! ERROR: Writing NOR failed. NOR flashing failed! /********************************************************************/

Hi Li, For NOR you need HW modifications. Have you done any modifications on the EVM? Regards, Rishabh

Hi Rishabh, yes, i have adjust the SW2, SW3 and SW5 in the EVM as the document said. as following picture shows:

SW2[1:16] -> 10101100 10000101 SW5[1:10] -> 0100100000

Hi Li, Please refer to chapter "6.1 TDA2xx Board Modification for NOR BOOT Mode" of SBL user guide http://processors.wiki.ti.com/images/b/b7/TDA_SBL_UserGuide.pdf Regards, Rishabh

Hi Rishabh, thanks for your help! i have read the doc, and the EVM switch setting is right as doc ,like SW2 and SW5 but as the document discribe, that is means i should change the resistor in the borad?

Hi Li, Yes you need to change the resistors on the board. Regards, Rishabh

Hi Rishabh, thanks for your help, your answer is very helpful! thanks again! best regard, Li

Hi Li, Please mark the answers that helped you in solving your issue as "This resolved my issue" and close the thread. Regards, Rishabh

Ticket Name: TDA2HG: TDA2HG run VSDK 03 05

Part Number: TDA2HG Other Parts Discussed in Thread: TDA2, Hello, We are ready to use the TDA2HG device. For TDA2HG，which config can we use in application/tda2_app/apps/configs based on VSDK 03 05? Is it supported by VSDK 03 05? Thanks Terence

Hi Terence, for TDA2HG, you need to use "tda2xx_evm_bios_all" or "tda2xx_evm_linux_all". Regards, Yordan

Ticket Name: Linux/TDA2: TDA2xx/linux BUILD_OPENCV_SRC

Part Number: TDA2 Tool/software: Linux MAKECONFIG?= tda2xx_evm_linux_opencx, my vision_sdk/apps/configs/tda2xx_evm_linux_opencx/cfg.mk file is : # IPU1 (core 0 & 1 are) not supported when IPU_PRIMARY_CORE=ipu2 PROC_IPU1_0_INCLUDE=no PROC_IPU1_1_INCLUDE=no PROC_IPU2_INCLUDE=yes PROC_A15_0_INCLUDE=yes PROC_DSP1_INCLUDE=no PROC_DSP2_INCLUDE=no PROC_EVE1_INCLUDE=no PROC_EVE2_INCLUDE=no PROC_EVE3_INCLUDE=no PROC_EVE4_INCLUDE=no VSDK_BOARD_TYPE=TDA2XX_EVM # Supported values: DDR_MEM_1024M DDR_MEM=DDR_MEM_1024M # Supported values: ipu1_0 ipu1_1 a15_0 none NDK_PROC_TO_USE=none # # Used to control building of algorithm source. # By default algorithm source not included in Vision SDK # BUILD_ALGORITHMS=no # # Applies profile to all cores # # Supported profiles: release debug #PROFILE=debug PROFILE ?= release PROFILE_ipu1_0 ?= $(PROFILE) PROFILE_ipu1_1 ?= $(PROFILE) PROFILE_ipu2 ?= $(PROFILE) PROFILE_c66xdsp_1 ?= $(PROFILE) PROFILE_c66xdsp_2 ?= $(PROFILE) PROFILE_arp32_1 ?= $(PROFILE) PROFILE_arp32_2 ?= $(PROFILE) PROFILE_arp32_3 ?= $(PROFILE) PROFILE_arp32_4 ?= $(PROFILE) PROFILE_a15_0 ?= $(PROFILE) # # For TDA2xx & TDA2Ex - vision SDK can run on either IPU1 or IPU2 subsystem # For TDA3xx - We have only IPU1 and hence IPU1 is the only option # Select IPU primary core from the available IPU1 & IPU2 subsytems # # Supported values: ipu1_0 ipu2 IPU_PRIMARY_CORE=ipu2 IPU_SECONDARY_CORE=ipu1_0 # # Set A15_TARGET_OS # A15 can run Linux or Bios # # A15_TARGET_OS support # Platform BIOS Linux # # TDA2XX_EVM yes yes # TDA3XX_EVM yes no # TDA2EX_EVM yes yes # # Supported values: Bios Linux A15_TARGET_OS=Linux IVAHD_INCLUDE=no VPE_INCLUDE=no DSS_INCLUDE=yes AVB_INCLUDE=no # # Enable below macro to enable DCAN integration into Vision SDK. # DCAN_INCLUDE=no CPU_IDLE_ENABLED=yes # # Enable below macro to view the bandwidth used by different IPs in the device # as a graphical plot on the display screen. # DATA_VIS_INCLUDE=no OPENCL_INCLUDE=yes TREAT_WARNINGS_AS_ERROR = yes HS_DEVICE=no DEFAULT_UBOOT_CONFIG := dra7xx_evm_vision_config DEFAULT_KERNEL_CONFIG := omap2plus_defconfig # For TDA2x DEFAULT_DTB := dra7-evm-infoadas.dtb # # Enable macro for OpenCV # ENABLE_OPENCV=yes CMEM_INCLUDE=yes BUILD_OPENCV_SRC=yes BUILD_LLVM=no include $($(MAKEAPPNAME)_PATH)/configs/$(MAKECONFIG)/uc_cfg.mk When I turn on the switch BUILD_OPENCV_SRC=yes and Then compile，The following error occurred: # osa: tda2xx-evm: Creating archive osa.a In file included from opencvCannyAlgo.c:84:0: iOpenCVCannyAlgo.h:82:28: fatal error: opencv/highgui.h: No such file or directory compilation terminated. In file included from opencvCannyLink_priv.h:104:0, from opencvCannyLink_algPlugin.c:77: iOpenCVCannyAlgo.h:82:28: fatal error: opencv/highgui.h: No such file or directory compilation terminated. In file included from canny.cpp:85:0: iCanny.h:81:28: fatal error: opencv/highgui.h: No such file or directory compilation terminated. make[6]: *** [depend] Error 1 make[5]: *** [vision_sdk_linux_demo] Error 2 make[4]: *** [apps] Error 2 make[3]: *** [apps_exe_hlos] Error 2 make[2]: *** [apps_hlos] Error 2 make[1]: *** [apps] Error 2 make: *** [vision_sdk] Error 2 Is there anything else I need to set up?

Hi, I see you set BUILD_OPENCV_SRC=yes. Please check this thread: e2e.ti.com/.../692767 Regards, Yordan

Ticket Name: Compiler/PROCESSOR-SDK-DRA8X-TDA4X: TIDL Multi_Cam Demo steps?

Part Number: PROCESSOR-SDK-DRA8X-TDA4X Tool/software: TI C/C++ Compiler Hi Champs: #1. I'm using the SDK7.0.1 to demo with 4 Camera with TIDL. #2. I have read these documents: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/vision_apps/docs/user_guide/group_apps_dl_demos_app_tidl_cam.html #3. However, the document is not matching the SDK7 TIDL contains. My camera seems show nothing on the screen. (I have connected 4 Sony IMX390 with FDPLink cables, those cables are the same with the TDA2 used). #4. Please see my log below and guide us how to output the camera demo for this TDA4 EVM + SDK7.0.1. THanks. BR Rio Multi_4_Cam_AI_Demo_Log.txt

Rio, You seem to have run many applications? Which application are you seeing an issue? These are are the available examples, app_tidl - file based object classification demo app_tidl_cam - camera based object classification demo (tested with single !MX390 camera) app_tidl_od - file based object detection demo app_tidl_seg - file based semantic segmentation demo app_tidl_avp/avp2/avp3 - file based multi-instance, multi-view demos and so on...

Ticket Name: Linux/TDA2: stack error

Part Number: TDA2 Tool/software: Linux i am using tda2 evm and SDK_VISION_03_04_00_00 i run a case have some problem ,follow is the log , i dont know what is about ! how can i check it? [HOST] [HOST ] 54.125754 s: #### ENTERING SAMPLE_APP:NULL SOURCE -> DISPLAY USE CASE #### [HOST] [HOST ] 55.353016 s: length_fr=14310568,hlos_model_fr_site=a1f5b800,model_fr_site=-1577732096 [HOST] [HOST ] 55.353016 s: hlos_model_fr_0=0.002201,model_fr_1=-0.027109 ,model_fr_2=0.124923,model_fr_3=0.056501 [HOST] [HOST ] 56.362837 s: IPC_OUT_0 : Create in progress !!! [HOST] [HOST ] 56.362898 s: IPC_OUT_0 : Create Done !!! [HOST] [DSP1 ] 56.362990 s: IPC_IN_0 : Create in progress !!! [HOST] [DSP1 ] 56.363386 s: IPC_IN_0 : Create Done !!! [HOST] [DSP1 ] 56.363600 s: ALGORITHM: Create in progress (algId = 0) !!! [HOST] [DSP1 ] 56.363752 s: [HOST] [DSP1 ] 56.363783 s: ### XDC ASSERT - ERROR CALLBACK START ### [HOST] [DSP1 ] 56.363783 s: [HOST] [DSP1 ] 56.363844 s: E_spOutOfBounds: Task 0xa19de98c stack error, SP = 0xa1b01bd8. [HOST] [DSP1 ] 56.363874 s: [HOST] [DSP1 ] 56.363874 s: ### XDC ASSERT - ERROR CALLBACK END ### [HOST] [DSP1 ] 56.363905 s: thanks Shuai

Hi Shuai, Which usecase you are running? From the log, it looks like it is running out of stack size. could you try increasing stack size? Rgds, Brijesh

Ticket Name: Linux/TDA2: TDA2 supported Image Format

Part Number: TDA2 Tool/software: Linux Does TDA2 support output format of AR0132AT6C00XPEA0 as below, 30fps? Does it need any buffer in between?

Hi, Well it can capture these RAW images formats, but it cannot convert into YUV. There is no hardware module to convert RAW to YUV. You need to write your own SW algo for the same. Rgds, Brijesh

Ticket Name: SAT0089 Muti - deser datasheet

Other Parts Discussed in Thread: DS90UB914A-Q1, DS90UB913A-Q1 Hello All, Currently, I am working on SAT0089, SAT0088 deser-ser. I am referring below link for schematic and other stuff. I cannot find datasheet here. Can TI provide datasheet for this boards http://support.spectrumdigital.com/boards/sat0088_0089/

Hello Swati, These boards are designed by Spectrum Digital, not TI so if you want information about the boards you must contact Spectrum Digital. It looks like these boards use these TI parts: DS90UB913A-Q1 and DS90UB914A-Q1 The datasheets for those parts are here: https://www.ti.com/lit/gpn/DS90UB913A-Q1 https://www.ti.com/lit/gpn/DS90UB914A-Q1

Ticket Name: RTOS/TDA2: Running a model on multiple cores

Part Number: TDA2 Tool/software: TI-RTOS Hi, I can not find the use of "coreID" on the vision sdk. I want to know when I read the NET.BIN and the PRM.bin, what is the role of the "coreID"? If I set the layersGroupId = 4, what's the mean on the vision sdk? Thank you. BR, Tianxing

Hi, This "coreID" is not used in VSDK for TIDL usecases, so you can ignore it. The "layersGropuId" is not a single value, it indicates group of layers in the net are processed together, so this parameter needs to be set for all the layers in the net. Please refer to config files in TIDL OD usecase

Hi, Could I set the layer execute on the dsp or eve, when the tidl usecase run? Thank you.

Hi, That depends on the use case, for TIDL OD usecase you can set all layers to run on EVE except Concat, Flatten and detectionOutput layers. How set this is shown in the import config files of SSD. Thanks, Praveen

Hi Praveen, Could you give me a sample, thank you. BR, Tianxing

Attached the sample import config file.. tidl_import_JDetNet.txt # Default - 0
randParams         = 0 

# 0: Caffe, 1: TensorFlow, Default - 0
modelType          = 0 

# 0: Fixed quantization By tarininng Framework, 1: Dyanamic quantization by TIDL, Default - 1
quantizationStyle  = 1 

# quantRoundAdd/100 will be added while rounding to integer, Default - 50
quantRoundAdd      = 25

numParamBits       = 8
# 0 : 8bit Unsigned, 1 : 8bit Signed Default - 1
inElementType      = 0 

inputNetFile       = "..\..\test\testvecs\config\caffe_jacinto_models\trained\image_detection\jdetNet_768x320\deploy.prototxt
inputParamsFile       = "..\..\test\testvecs\config\caffe_jacinto_models\trained\image_detection\jdetNet_768x320\ti-jdetNet_768x320.caffemodel"
outputNetFile      = "..\..\test\testvecs\config\tidl_models\jdetnet\tidl_net_jdetNet_ssd.bin"
outputParamsFile   = "..\..\test\testvecs\config\tidl_models\jdetnet\tidl_param_jdetNet_ssd.bin"

rawSampleInData = 1
preProcType   = 4
sampleInData = "..\..\test\testvecs\input\trace_dump_0_768x320.y"
tidlStatsTool = "..\quantStatsTool\eve_test_dl_algo.out.exe"
layersGroupId = 0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	2	1	2	1	2	1	2	1	2	1	2	1	2	1	2	1	2	1	2	2	2	2	2	2	2	0
conv2dKernelType = 0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

 Thanks, Praveen

Hi Praveen, If means that layer run on which core to be set by the layersGroupId of the config file, I see the 1 for EVE and the 2 for DSP? When I read the source code of tidlModelImport, the layersGroupId is assignment to coreID as follow: tIDLNetStructure.TIDLLayers[tiLayerIndex].coreID = gParams.layersGroupId[tiLayerIndex]; tIDLNetStructure.TIDLLayers[tiLayerIndex].layersGroupId = gParams.layersGroupId[tiLayerIndex]; On line 4161 of function caffe_import() Could I set the layers run on EVE1, EVE2 or DSP1, DSP2 by the layerGroupId. BR, Tianxing

Yes, you can do that by assigning unique layersGroupId for each of the cores. For example, if you wish to run your network on two EVE and two DSP cores, then you can assign layersGroupId as follows.. 1 for EVE1, 2 for EVE2, 3 for EVE3, 4 for DSP. Please note that same mapping should used in running inference. Thanks, Praveen

Hi Praveen, Thank you for your reply. What' s the mean that "same mapping should used in running inference"? That' s mean when I create chain, I should used the EVE1, EVE2, DSP1 and DSP2? Best Regard, Tianxing

Yes. Thanks, Praveen

Hi Praveen, However, I can't find the relationship between the config fie and sdk code. Best Regards, Tianxing

Please refer to tidl and VSDK documents to better understanding. Also, search in the e2e forum you may get some more information you are looking for. Thanks, Praveen

Ticket Name: Linux/TDA2: MAKECONFIG?= tda2xx_evm_linux_opencl make fail on VSDK3.4

Part Number: TDA2 Tool/software: Linux Dear Officer, I have update the c6000 to 8.1.0. but still got the below error: make[7]: Entering directory `/home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/apps/src/hlos/adas/src/alg_plugins/openclframecopy/kernel' echo Compiling OpenCL file copy.cl Compiling OpenCL file copy.cl /home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/../ti_components/os_tools/linux/targetfs/usr/share/ti/opencl/bin/x86/clocl -t copy.cl >> WARNING: invalid compiler option --bc_file=copy.bc (ignored) "/home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/../ti_components/os_tools/linux/targetfs/usr/share/ti/opencl/dsp.syms", line 9: error #10022-D: invalid option: --single_data_segment "/home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/../ti_components/os_tools/linux/targetfs/usr/share/ti/opencl/dsp.syms", line 10: error #10022-D: invalid option: --no_entry_point warning #10247-D: creating output section ".stack" without a SECTIONS specification warning #10210-D: creating ".stack" section with default size of 0x400; use the -stack option to change the default size undefined first referenced symbol in file --------- ---------------- main /home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/ti_components/cg_tools/linux/ti-cgt-c6000_8.1.0/lib/rts6600_elf.lib<args_main.obj> error #10234-D: unresolved symbols remain error #10010: errors encountered during linking; "copy.out" not built >> Compilation failure make[7]: *** [copy.dsp_h] Error 255 make[7]: Leaving directory `/home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/apps/src/hlos/adas/src/alg_plugins/openclframecopy/kernel' make[6]: *** [opencl_build] Error 2 make[6]: Leaving directory `/home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/apps/src/hlos/adas/src/alg_plugins/openclframecopy' make[5]: *** [vision_sdk_linux_demo] Error 2 make[5]: Leaving directory `/home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/apps/src/hlos' make[4]: *** [apps] Error 2 make[4]: Leaving directory `/home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/apps/src/hlos' make[3]: *** [apps_exe_hlos] Error 2 make[3]: Leaving directory `/home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/build' make[2]: *** [apps_hlos] Error 2 make[2]: Leaving directory `/home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/build' make[1]: *** [apps] Error 2 make[1]: Leaving directory `/home/cheepeng/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/build' make: *** [vision_sdk] Error 2 Please advise. Thanks and best regards He Wei

Dear TI, After set the PATH to c6000 to 8.1.0/bin, issue is resolved. Thanks and best regards He Wei

Hi He Wei, thanks for sharing the solution of the problem. Regards, Yordan

Ticket Name: TDA2EVM5777: TDA2EVM5777 EVM_3V3_SD

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello Why the R823 in TDA2 EVM is no-pop? Why the TPD2E001DRL need power supply? And why shouldn't R823 connect to EVM_3V3 for continue power for card detection function but EVM_3V3_SD? Thank you

Hi, I'm not aware of the exact reason, my presumption is that INSERT pins being a card-present-contact away from human fingers would not need ESD protection. See more about SD card ESD here: Regards, Stan

Ticket Name: CCS/TDA2EVM5777: Ethernet framework

Part Number: TDA2EVM5777 Tool/software: Code Composer Studio Hello sir , I would like create application that has to transfer image and CAN data from PC to board over Ethernet. which document it will helpful for me to develop application using TI provided Library . Thanks and Regards, Madhav

Hi Madhav, Which version of Vision SDK are you using ? You can find a bunch of getting started guides under the docs folder inside the main SDK folder. Please provide more details about your SW environment. Regards, Anand

Hello Anand, Vision SDK version 3.0.6. Windows 10 code compose studio 8.3.0 Regards, Madhav

Hi Madhav, I see that the thread e2e.ti.com/.../2972950 is a possible duplicate of this thread. Please close this thread. We can continue discussion in the other thread. Regards, Anand

Ticket Name: CCS/TDA2: CCS 7.4/ TDA2X EVM JTAG connection issue

Part Number: TDA2 Tool/software: Code Composer Studio Hello everyone. while connecting TDA2 EVM board with XDS560v2 STM TRAVELER emulator , JTAG connection is not detected. I have attached the log related to the issue: [Start: Spectrum Digital XDS560V2 STM TRAVELER Emulator_0] Execute the command: %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity [Result] -----[Print the board config pathname(s)]------------------------------------ /home/tiautomotive/.ti/ti/0/0/BrdDat/testBoard.dat -----[Print the reset-command software log-file]----------------------------- This utility has selected a 560/2xx-class product. This utility will load the program 'sd560v2u.out'. E_RPCENV_IO_ERROR(-6) No connection: DTC_IO_Open::dtc_conf Download failed for file /home/tiautomotive/ti/ccsv7/ccs_base/common/uscif/./././././xds560v2.out An error occurred while soft opening the controller. -----[An error has occurred and this utility has aborted]-------------------- This error is generated by TI's USCIF driver or utilities. The value is '-250' (0xffffff06). The title is 'SC_ERR_ECOM_EMUNAME'. The explanation is: An attempt to access the debug probe via USCIF ECOM has failed. [End: Spectrum Digital XDS560V2 STM TRAVELER Emulator_0] So i request you to look this issue & help us as soon as possible because of this our project is on hold. Regards Surbhi

Hi Surbhi, can you check this: software-dl.ti.com/.../ccsv7_debugging_jtag_connectivity_issues.html there are some guidelines how to debug JTAG connection problems. Regards, Yordan

Hello, In addition to the above suggestion, make sure you have the dip switch sys-boot configured for debug mode. See thanks, Alex

Hi Yordan, I have already gone through this : software-dl.ti.com/.../ccsv7_debugging_jtag_connectivity_issues.html the suggested tips, i tried. I also installed drivers for CCS. But didn't find any change in my issue (attached log earlier). So is, their is any issue with OS as i am using UBUNTU14.04. Regards Surbhi

Hi, I have checked with the dip switch sys-boot & it too is configured for debug mode. I have followed the instruction mentioned in "PROCESSOR_SDK_VISION_03_01_00_00/vision_sdk/docs/UserGuides" section 3.4. thanks. Surbhi

Hello, Just for clarification, are you creating a new target configuration and click "Test connection"? Is that when the error appear? Or are you trying to fire up the cores and connect to one of them? thanks Alex

Also make sure you don't boot an OS or you won't be able to debug with Jtag, see my post from here: e2e.ti.com/.../2500613 thanks, Alex

Hi Surbhi, Can you check if correct XDS560 emulator is selected in target configuration? One is supposed to be used through LAN and other through USB. Regards, Rishabh

Hello everyone, I have attached the image of JTAG which i am using for my project, & i have also checked for the correct XDS560 traveler emulator which is selected in target configuration. " Just for clarification, are you creating a new target configuration and click "Test connection"? Is that when the error appear? Or are you trying to fire up the cores and connect to one of them? " --> yes i have created the new target configuration & after that i have checked for the "Test connection" then that error (log is been attached earlier) occurs. --> As i thought it might be the issue of CCS, so i updated & re-installed the drivers for CCS. still that issue is there. Regards Surbhi

OK, can you also try the suggested workaround here: thanks Alex

Hello, I haven't heard back from you, I hope you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Thanks, Alex

Hello, Yes, the issue was resolved. I simply uninstalled the CCS & again installed & updated it. It seems the issue was due to CCS. Thank you guys. Regards Surbhi

Ticket Name: Linux/TDA2: what is Video Capture and AVB Capture mean?

Part Number: TDA2 Tool/software: Linux Excuse me! i am build visionsdk follow VisionSDK_Linux_UserGuide.pdf, 3.1 Build Linux Vision SDK for Video Capture and Display use-cases 3.2 Build Linux Vision SDK for AVB Capture, Decode and Display UCs But I don't know what the difference between 3.1 and 3.2 ? what is Video Capture mean? what is AVB Capture mean?

Hi , There are some modules disabled in kernel and built for certain usecases . AVB is one of them 3.1 The usecase chain will have capture / null src as input source for the stream . Hence the steps to be followed to build application for all capture usecase , 3,2 The usecase uses AVB (network) as capture source, Here Networking is disabled from kernel and handled at ipu . Hence changes to be done to disable ethernet from kernel. Regards Chetan.M

Hi:Chetan.M execute make –s –j depend For a moment, the virtual machine is automatically restarted. After restarting execute make –s –j is also have this problem , and no application’s .out file in ti_components/os_tools/linux/targetfs/opt/vision_sdk BESTWISHES shuai

Hi Shuai , There is another thread for the build issue please use that thread , You can close the thread and mark answered if above issue is solved . Regards Chetan.M

Hi Chetan.M insufficient memory YOURS shuai

Hi Chetan.M I want to read a.AVI video file as an input, then i should use 3.1?? Regards shuai

Yes you need to use null src as input , 3.1 is the build you need to use. Regards Chetan.M

Hi Chetan.M null_src_decode_display this one ，but where should i add my code of open file? BESETWISHES SHUAI

Hi Shuai, I see other thread by you with same question on null src. Can you please close the thread and marked answer . Regards Chetan.M

Ticket Name: Compiler/TDA2EVM5777: Put the board in UART boot mode

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi, I want to boot bios from qspi. According to mflash user guide l need to change the SYSBOOT switch on EVM: For TDA2xx-evm, change the switch SW3[0:7], SW4[8:15] to [11001000][100000001] and SW5 to [00010000] But i don't understand which switches i have to change, because in my EVM i have SYSBOOT SW2[0:7] and SW3[8:15], and also USERCONFIG SW5[0:9].

Hi Dmitry, which user's guide you refer? In section "3.5 Boot Modes" of vision_sdk/docs/VisionSDK_UserGuide_TDA2xx.pdf there is: Also you can check section "29.2.4 Sysboot Configuration" in device's TRM. Regards, Yordan

In section "3.5 Boot Modes" of vision_sdk/docs/VisionSDK_UserGuide_TDA2xx.pdf nothing about UART boot mode and this reason i don't understand how can i use mflash tool for boot bios. Regards, Dmitry

Hi Dmitry, sorry for the delay. For UART boot on TDA2, can you try SySBOOT [0:5] = 0b110010 Regards, Yordan

Hi Yordan: For UART boot(mflash), How to setup sw2,sw3 & sw5. Regards, Jemy

Hi, The issue is resolved? Thanks Gaviraju

Hi Gaviraju! Still don't understand how to setup sw2,sw3 & sw5 for TDA2xx-evm. Regards, Dmitry

Hi, Refer to the below document file: ti_components/drivers/pdk_01_10_04_05/packages/ti/boot/sbl_auto/docs/AppNote_mflash.pdf or file: ti_components\drivers\pdk_01_10_04_05\packages\ti\boot\sbl_auto\tools\mflash\Readme.md There is a small correction in AppNote_mflash.pdf regarding the SYSBOOT switch change For TDA2xx-evm, change the switch SW3[0:7], SW4[8:15] to [11001000][100000001] and SW5 to [00010000] Please ignore the above SYSBOOT switch change & follow the below SYSBOOT switch change For TDA2xx-evm, change the SYSBOOT switches SW2[0:7] and SW3[8:15] to [11001000][100000001] and SW5 to [00010000] Thanks Gaviraju

Thanks, Gaviraju!

Ticket Name: TDA2: EVE/VCOP deinterleave(), interleave() problem

Part Number: TDA2 Hi, I try release simple mean filter window 3x3. I use npt() and get the same result as host emulation (visual studio vcop.h library), but when i change npt() to deinterleave(), interleave(), the result is diffrent. __vptr_uint16 bufx, __vptr_uint8 output, w = 640; npt loops: for (int I1 = 0; I1 < blockH; I1++) { for (int I2 = 0; I2 < w / VCOP_SIMD_WIDTH; I2++) { __agen indexOut = I1 * w * sizeof(*output) + I2 * sizeof(*output) * VCOP_SIMD_WIDTH; __agen index = I1 * bufWidth * sizeof(*bufx) + I2 * sizeof(*bufx) * VCOP_SIMD_WIDTH; Vec10 = (bufx)[index].npt(); Vec20 = (bufx + 2)[index].npt(); Vec30 = (bufx + 4)[index].npt(); Vec10 += Vec20 + Vec30; Vec20 = Vec10 * VecMul; Vec30 = Vec20 << Vshift; output[indexOut].npt() = Vec30; } } deinterleave(), interleave() loops: for (int I1 = 0; I1 < blockH; I1++) { for (int I2 = 0; I2 < w / VCOP_2SIMD_WIDTH; I2++) { __agen indexout = I1 * w * sizeof(*output) + I2 * sizeof(*output) * VCOP_2SIMD_WIDTH; __agen index0 = I1 * bufWidth * sizeof(*bufx) + I2 * sizeof(*bufx) * VCOP_2SIMD_WIDTH; (Vec10, Vec11) = (bufx)[index0].deinterleave(); (Vec20, Vec21) = (bufx + sizeof(*bufx))[index0].deinterleave(); (Vec30, Vec31) = (bufx + 2 * sizeof(*bufx))[index0].deinterleave(); Vec10 += Vec20 + Vec30; Vec11 += Vec21 + Vec31; Vec20 = Vec10 * VecMul; Vec21 = Vec11 * VecMul1; Vec30 = Vec20 << Vshift; Vec31 = Vec21 << Vshift1; output[indexout].interleave() = (Vec30, Vec31); } } Where is the problem? Thank you for help.

The next loop for VCOP_2SIMD_WIDTH works correct. In documentation for deinterleave aligment must be for word. Word mean 4 or 2 bytes? for (int I1 = 0; I1 < blockH; I1++) { for (int I2 = 0; I2 < w / VCOP_2SIMD_WIDTH; I2++) { __agen indexout = I1 * w * sizeof(*output) + I2 * sizeof(*output) * VCOP_2SIMD_WIDTH; __agen index0 = I1 * bufWidth * sizeof(*bufx) + I2 * sizeof(*bufx) * VCOP_2SIMD_WIDTH; Vec10 = (bufx)[index0].npt(); Vec11 = (bufx + 16)[index0].npt(); Vec20 = (bufx + sizeof(*bufx ) )[index0].npt(); Vec21 = (bufx + 16 + sizeof(*bufx) )[index0].npt(); Vec30 = (bufx + 2 * sizeof(*bufx) )[index0].npt(); Vec31 = (bufx + 16 + 2 * sizeof(*bufx) )[index0].npt(); Vec10 += Vec20 + Vec30; Vec11 += Vec21 + Vec31; Vec20 = Vec10 * VecMul; Vec21 = Vec11 * VecMul1; Vec30 = Vec20 << Vshift; Vec31 = Vec21 << Vshift1; output[indexout].npt() = Vec30; (output+8)[indexout].npt() = Vec31; } }

I have mistake, make alignment equal 2 bytes, but it must be 4 bytes.

Hi Danil, thanks for updating the thread. Regards, Yordan

Ticket Name: TDA2: Building standalone application to run on DSP (C66x core)

Part Number: TDA2 Other Parts Discussed in Thread: MATHLIB Hi, I am going through the Vision SDK code. I have a few queries: 1) EVE software supports building separate test bench applications for individual kernels. Does DSP software also support the same? 2) If yes, what is the procedure for building separate kernel applications for test purpose? 3) Where is the DSP executable generated? Regards, Shruti

Shruti To build individual EVE kernels, you need to go to those packages in \ti_components\algorithms\eve_sw_01_19_00_00 and build them. same for DSP - \ti_components\algorithms\dsplib_c66x_3_4_0_0, \ti_components\algorithms\vlib_c66x_3_3_2_0 etc. regards, Shiju

Hi Shiju, I found the documentation to build EVE and I am able to do it successfully. But I did not find any document which describes how to build standalone kernel applications for DSP. Can you please point them out? Also, I am using Vision SDK version 3.3.0.0. But I do not find dsplib_c66x folder into it, there is only vlib_c66x_3_3_0_3. I am unable to find any makefiles or such which will help me build. Do I need to use another version of VisionSDK? Please help me out with this. Regards, Shruti

Hi Shruti If you are in the initial phase of the project better use the latest Vision SDK (v3.5) version You can down load from - www.ti.com/.../processor-sdk-tdax below the DSP Kernel packages comes along with VSDK 1. dsplib_c66x_3_4_0_0 2. mathlib_c66x_3_1_0_0 3. vlib_c66x_3_3_2_0 4. vxlib_c66x_1_1_3_0 Please note that some of these are in full source format and a few in only lib format. regards, Shiju

Hi Shiju, I was using VisionSDK v3.3, but it does not include dsplib package. So I downloaded v3.5 now which includes the dsplib package. It also has the documentation on how to build the individual kernels. Thank you for the help. Regards, Shruti

Ticket Name: TDA2: horizontal flip support on TDA2x

Part Number: TDA2 Hi, I know that ISS ISP RSZ in TDA3x supports horizontal flip. Does VPE or Other Block in TDA2x support horizontal flip function? Regards JP Park

Hi JP, VPE in itself does not support any flipping. But you could use Tiler to flip the images.. Rgds, Brijesh

Hi Brijesh, Thank you for your reply. ok. I will try the flipping using Tiler. Regards JP Park

Ticket Name: Linux/TDA2EVM5777: Linux Process CPU Affinity Isolation

Part Number: TDA2EVM5777 Tool/software: Linux Hello, I am running PROCESSOR_SDK_VISION_03_01_00_00 Linux running on the tda2evm5777 and I need to set all linux processes to a single A15 (A15_0), including and in particular, the ethernet driver. This is so I can expect less interrupts from Linux when running my own applications on the second A15 (A15_1) When I run the taskset command to set the cpu affinity for all of the processes in linux to go on A15_0, some processes do not change cpu affinity. I have tried isolcpus, but not all processes get changed to be on A15_0. How can I force all processes to be on A15_0, including the ethernet driver, so I can run my own program,on A15_1 and have those be the only things running in linux on that core? How can I set the ethernet driver to run only on A15_0?

Hi bulk of the packet reception and handling runs from interrupt context and bottom-half (softirq) context for networking. For this, you will need to set the interrupt affinity as in https://www.kernel.org/doc/Documentation/IRQ-affinity.txt Additionally the end application that generates/consumes the data also may need to be pinned - you can use cpuset to achieve this https://github.com/lpechacek/cpuset/blob/master/doc/tutorial.txt

Ticket Name: [TDA3] Stereo camera solution

Other Parts Discussed in Thread: TDA2 Dear we will develop stereo camera system in car sysem. Presently we select the TDA3 solution. But we are not sure whether you can use TDA3 that can meet the effectiveness of stereo camera. From TI ADAS SoC solution get 1. Stereo Front Camera Hight Level Block of of TDA2 can support stereo camera solution, but TDA3 doesn't have this. TDA3 is a cost-down solution, so we worry it cannot meet the stereo camera performance requirement. Can you check the TDA3 or you suggest to use TDA2? And tell me why is main reason. 2. From Stereo Front Camera Hight Level Block of TDA2 can see, you use a FPGA(optional) to link from camera IF to TDA2. Can you tell us what is his main function? If it is "must", who can provide this image of FPGA? Or TI has support this (or provide this SW code) Br. Ivan Wu ivan.wu@tungthih.com.tw

Can I add a question? 3. About stereo camera, VIN1a and VIN2a of TDA3 can input the video signal of 2 camera at the same time?

You can interface up to four cameras through each VIN (Internally each VIN has 2 slices and each slice has 2 ports). I think what matters here is resolution, fps and data format of stream you are capturing. There shouldn't be any problem for two signals.

Hi, Yogesh Thank your response But I don't know can Camera 1 and Camera 2 be worked at the same time or they are use "Time division multiplexing"? Br. Ivan Wu

Hi Ivan, TDA3x can do stereo but the maximum resolution and the maximum number of disparities it can handle, will be less than what TDA2x can handle. What is the target resolution, frame rate and maximum disparity you are trying to achieve in your system ? regards, Victor Cheng

Hi, Victor Presently we would plan to use HD (720p) resolution, and this fps criteria should be defined at 30 ~ 60 fps. About this, do you have any suggestion? Br. Ivan Wu

Hi Ivan, For 720P, the maximum frame rate TDA3x can handle would be 7.5 fps with a maximum number of disparities of 32. regards, Victor Cheng

Ivan, If you have Vision SDK, you can refer to the data sheet under vision_sdk\docs. It explains stereo usecase in detail and how much processing is needed for 640x360@30 fps processing on TDA2x (Capture is still 1280 x 720 from two cameras on xCAM) this info can be used to extrapolate for tda3x in your case but as Victor said for tda3x 720p stereo would yield very low fps.

Hi Ivan Wu, The VIP in both TDA3x & TDA2x can receive multiple video streams. VIP1 & VIP2 are two separate instances of VIP. This allows SoC to receive multiple video streams simultaneously. Depending on the camera interface & other system needs (width of parallel port, display width, etc...) we can check on the feasibility. Regards, Sujith

Ivan, For that you either need external logic or use TDA's gpio's to sync between two camera using features provided by sensors. This is done on one of our reference designs but with TDA2x www.radiumboards.com/TI_TDA2x_Based_xCAM_Platform.php

Ticket Name: RTOS/TDA2: Adding new usecase and get compiling error “unresolved symbols remain”

Part Number: TDA2 Tool/software: TI-RTOS Hello，I'm trying to add new usecase to VSDK, and when I compiled it, I got the error "unresolved symbols remain". Below is the log: ================================================================ # Making tda2xx-evm:ipu1_0:release:vision_sdk_lib... # Linking into D:/PROCESSOR_SDK_VISION_03_05_00_00/vision_sdk/binaries/apps/tda2xx_evm_bios_all/vision_sdk/bin/tda2xx-evm/vision_sdk_ipu1_0_release.xem4... # undefined first referenced symbol in file --------- ---------------- Chains_lyratidlOD D:/PROCESSOR_SDK_VISION_03_05_00_00/vision_sdk/binaries/apps/tda2xx_evm_bios_all/lib/tda2xx-evm/ipu1_0/release/app_libs.aem4<chains_main_bios_tidl.oem4> error: unresolved symbols remain error: errors encountered during linking; "D:/PROCESSOR_SDK_VISION_03_05_00_00/vision_sdk/binaries/apps/tda2xx_evm_bio s_all/vision_sdk/bin/tda2xx-evm/vision_sdk_ipu1_0_release.xem4" not built gmake[7]: *** [D:/PROCESSOR_SDK_VISION_03_05_00_00/vision_sdk/binaries/apps/tda2xx_evm_bios_all/vision_sdk/bin/tda2xx-evm/vision_sdk_ipu1_0_release.xem4] Error1 gmake[6]: *** [ipu1_0] Error 2 gmake[5]: *** [apps_ipu1_0] Error 2 gmake[4]: *** [apps] Error 2 gmake[3]: *** [apps] Error 2 gmake[2]: *** [apps_exe] Error 2 gmake[1]: *** [apps] Error 2 gmake: *** [vision_sdk] Error 2 ================================================================ Below is what I have done: 1. I prepared all the file according the usecasegen document 2. Add the usecase to uc_cfg.mk under vision_sdk/apps/configs/tda2xx_evm_bios_all, 3. Add the usecase to cfg.mk under vision_sdk/apps/configs/cfg.mk 4. in vision_sdk/apps/Makefile, I add: -include $(MODULE_SRC_BASE_PATH)/rtos/usecases/lyra_tidl_OD/SRC_FILES.MK Then I removed the binaries directory and do gmake -s -j depend, then gmake -s -j, and then I get the error I described previously. Did I do anything wrong here? I also run the command gmake -s showconfig and I did see my usecase was built. The last one UC_lyra_tidl_OD is the usecase I added. Below is the log: =============================================================================== # Use-cases included in build, # UC_srv_calibration UC_lvds_vip_dual_cam_dual_display UC_lvds_vip_multi_cam_view UC_lvds_vip_sv_analytics_us UC_lvds_vip_sv_standalone UC_lvds_vip_single_stereo UC_lvds_vip_single_stereo_auto_calib UC_lvds_vip_single_stereo_calibration UC_network_rx_tx UC_network_stereo_display UC_null_src_dec_display UC_null_src_display UC_ov490_vip_sv_standalone UC_saveDisFrame UC_vip_single_cam_analytics2 UC_vip_single_cam_dense_optical_flow UC_vip_single_cam_dual_display UC_vip_single_cam_edge_detection UC_vip_single_cam_frame_copy UC_vip_single_cam_frame_copy_safety UC_vip_single_cam_lane_detection UC_vip_single_cam_object_detection2 UC_vip_single_cam_sfm UC_vip_single_cam_sparse_optical_flow UC_vip_single_cam_subframe_copy UC_vip_single_cam_tlr UC_vip_single_cam_view UC_vip_single_cam_view_encdec UC_tidl UC_semSeg UC_tidl_OD UC_lyra_tidl_OD # # =================================================================================

Hi, Seems like you are calling Chains_lyratidlOD function from apps/src/rtos/common/chains_main_bios_tidl.c file. But have you defined your usecase entry function with the same name Chains_lyratidlOD. Please add some error in your usecase file to confirm that these are getting build. Regards, Anuj

Hello Anuj， the problem is solved~ thanks for your reply.

Ticket Name: Compiler/TDA2EX17EVM: [Build Issue] errors encountered during linking

Part Number: TDA2EX17EVM Tool/software: TI C/C++ Compiler Hi TI Team I modify usecase framecopy (vision_sdk\apps\src\rtos\alg_plugins\framecopy) to be my algorithm link and add a API in "Alg_FrameCopyProcess"(frameCopyAlgoLocalDma.c).But I build SDK fail and have the errors as below: ... ... "E:/jacob_adb/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2ex_evm_bios_all/obj/vision_sdk/tda2ex-evm/c66xdsp_1/release/vision_sdk_configuro/linker_mod.cmd", line 202: error: program will not fit into available memory. placement with alignment fails for section ".cinit" size 0x35c8be . Available memory ranges: DSP1_DATA_MEM size: 0xd00000 unused: 0x2db2b2 max hole: 0x2db2a4 error: errors encountered during linking; "E:/jacob_adb/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2 ex_evm_bios_all/vision_sdk/bin/tda2ex-evm/vision_sdk_c66xdsp_1_release.xe66" not built gmake[7]: *** [E:/jacob_adb/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/binaries/apps/tda2ex_evm_bios_all/vision_sdk/bin/tda2ex-evm/vision_sdk_c66xdsp_1_release.xe66] Error 1 gmake[7]: Leaving directory `E:/jacob_adb/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/links_fw/src/rtos/bios_app_common/tda2ex/dsp1' gmake[6]: *** [c66xdsp_1] Error 2 gmake[6]: Leaving directory `E:/jacob_adb/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/links_fw/src/rtos/bios_app_common/tda2ex/dsp1' gmake[5]: *** [apps_dsp1] Error 2 gmake[5]: Leaving directory `E:/jacob_adb/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/links_fw/src/rtos' gmake[4]: *** [apps] Error 2 gmake[4]: Leaving directory `E:/jacob_adb/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/links_fw/src/rtos' gmake[3]: *** [apps] Error 2 gmake[3]: Leaving directory `E:/jacob_adb/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/apps' gmake[2]: *** [apps_exe] Error 2 gmake[2]: Leaving directory `E:/jacob_adb/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/build' gmake[1]: *** [apps] Error 2 gmake[1]: Leaving directory `E:/jacob_adb/PROCESSOR_SDK_VISION_03_07_00_00/vision_sdk/build' gmake: *** [vision_sdk] Error 2 I add the same API in "Alg_FrameCopyProcess"(frameCopyAlgoCpu.c) and it's OK.Could you give me some suggestions for the issue? Thanks so much. Best Regards, Jacob Lin

Hi, Its better that you increase your DSP data memory in memory map file by reducing any unwanted section size. please refer below doc vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_MemoryMap.pdf Regards, Anuj

Hi Anuj I refer the document to modify the DSP1_DATA_MEM and get another error as below: ... ... [IPU1-1] 13.359330 s: SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1023 [IPU1-1] 13.359482 s: SYSTEM: Heap = LOCAL_DDR @ 0x00000000, Total size = 262144 B (256 KB), Free size = 254984 B (249 KB) [HOST ] 13.359940 s: SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1023 [HOST ] 13.359940 s: SYSTEM: Heap = LOCAL_DDR @ 0x00000000, Total size = 6291456 B (6144 KB), Free size = 6250736 B (6104 KB) [DSP1 ] 11.861038 s: IPC_IN_0 : Create in progress !!! [DSP1 ] 11.861465 s: IPC_IN_0 : Create Done !!! [DSP1 ] 11.861648 s: ALGORITHM: Create in progress (algId = 0) !!! [DSP1 ] 11.861739 s: ALG_FRAMECOPY: DMA: Allocated CH (TCC) = 0 (0) [DSP1 ] 11.873574 s: ALGORITHM: Create Done (algId = 0) !!! [DSP1 ] 11.873726 s: IPC_OUT_0 : Create in progress !!! [DSP1 ] 11.873787 s: IPC_OUT_0 : Create Done !!! [DSP1 ] 13.360184 s: SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1023 [DSP1 ] 13.360214 s: SYSTEM: Heap = LOCAL_L2 @ 0x00800000, Total size = 227264 B (221 KB), Free size = 227264 B (221 KB) [DSP1 ] 13.360245 s: SYSTEM: Heap = LOCAL_DDR @ 0x00000000, Total size = 524288 B (512 KB), Free size = 504528 B (492 KB) [IPU2 ] 13.360733 s: SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1023 [IPU2 ] 13.360855 s: SYSTEM: Heap = LOCAL_DDR @ 0x00000000, Total size = 262144 B (256 KB), Free size = 254936 B (248 KB) [DSP1 ] 13.859177 s: [DSP1 ] 13.859208 s: ### XDC ASSERT - ERROR CALLBACK START ### [DSP1 ] 13.859238 s: [DSP1 ] 13.859299 s: out of memory: handle=0x83d8b9b0, size=3686408 [DSP1 ] 13.859330 s: [DSP1 ] 13.859330 s: ### XDC ASSERT - ERROR CALLBACK END ### [DSP1 ] 13.859360 s: [DSP1 ] 13.859482 s: ti.sysbios.heaps.HeapMem: line 221: ti.sysbios.heaps.HeapMem: line 221: out of memory: handle=0x83d8b9b0, size=3686408 ... ... Do you give me suggestion again? Thanks a lot. Best Regards, Jacob Lin

Hi, Why are you allocating 3 MB of data from DSP1 local heap. We allocate only very small data from local heap. If the data size is large then please use Ulits_memAlloc() ang provide heapId as SR1. Regards, Anuj

Hi Anuj OK and I have resolved the issue.Thanks. Best Regards, Jacob Lin

Ticket Name: TDA2SX: How to implement gateway configuration support

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi team, Here's an issue from the customer may need your help: GateWay IP configuration in TDA2x is required to implemented and the customer has tried the the following modifications: /* * Add the default gateway. Since it is the default, the * destination address and mask are both zero (we go ahead * and show the assignment for clarity). */ bzero(&RT, sizeof(RT)); RT.IPDestAddr = 0; RT.IPDestMask = 0; RT.IPGateAddr = inet_addr(GatewayIP); CfgAddEntry(hCfg, CFGTAG_ROUTE, 0, 0, sizeof(CI_ROUTE), (UINT8 *)&RT, 0) Does modifying the GateWayIP values above correctly modify the GateWay IP? Thanks and regards, Cherry

Cherry, Unfortunately this post does not have any information of the SDK being used or the component that is being modfied. We cannot answer this question until more information is provided. Regards Karthik

Hi Karthik, Thanks for your support. NDK version in NetWorking:ndk_2_24_02_31 NSP version: nsp_gmacsw_4_16_01_01 The GateWay IP is modified in the stackInitHookDynEth1() function in NDK_nsp_hook.C. And the issue is how is the GateWay IP configured in TDA2? Please let me know if you need any further information. Thanks and regards, Cherry

Ticket Name: TDA2P-ACD: [valeo BYD project] camera image is not properly received

Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 hi, TI experts: I use TDA2PX soc, the video pipeline is camera->933->962->soc. we have two kind of camera, both have ISP in image sensor and the output format is YUYV(8bit), the difference is one resoluton is 1280*960, and another is 1100*880. when we use 1280*960 camera, we can get proper image, and our config is below: PCapIssCalcfg->inFmt[StreamId].width = VIDEO_IP_RAW_CAPTURE_WIDTH*2; PCapIssCalcfg->inFmt[StreamId].height = AR_CAMERA_ACTIVE_VIDEO_IP_RAW_CAPTURE_HEIGHT; PCapIssCalcfg->inFmt[StreamId].pitch[0] = VIDEO_IP_RAW_CAPTURE_WIDTH*2; PCapIssCalcfg->inFmt[StreamId].dataFormat = 0x0U; PCapIssCalcfg->csi2DataFormat[StreamId] = VPS_ISS_CAL_CSI2_YUV422_8B; PCapIssCalcfg->inFmt[StreamId].bpp = FVID2_BPP_BITS16; /* Input stream from which camera channel */ PCapIssCalcfg->csi2VirtualChanNo[StreamId] = StreamId; PCapIssCalcfg->streamType[StreamId] = VPS_ISS_CAL_TAG_PIX_DATA; PCapIssCalcfg->isBysOutCfgValid[StreamId] = FALSE; PCapIssCalcfg->bysInEnable[StreamId] = FALSE; /* CSI2 and other */ PCapIssCalcfg->isVportCfgValid[StreamId] = FALSE; PCapIssCalcfg->writeToMem[StreamId] = TRUE; PCapIssCalcfg->pixProcCfg[StreamId].extract = VPS_ISS_CAL_PIX_EXRCT_B16_LE;/*VPS_ISS_CAL_PIX_EXRCT_B16_LE*/ PCapIssCalcfg->isPixProcCfgValid[StreamId] = TRUE ;/*TRUE*/ PCapIssCalcfg->pixProcCfg[StreamId].decCodec = VPS_ISS_CAL_DPCM_DEC_BYPASS; PCapIssCalcfg->pixProcCfg[StreamId].enableDpcmInitContext = FALSE; PCapIssCalcfg->pixProcCfg[StreamId].encCodec = VPS_ISS_CAL_DPCM_ENC_BYPASS; PCapIssCalcfg->pixProcCfg[StreamId].pack = VPS_ISS_CAL_PIX_PACK_B16;/*VPS_ISS_CAL_PIX_PACK_B16*/ PCapIssCalcfg->pixProcCfg[StreamId].addr = 0X0u; PCapIssCalcfg->pixProcCfg[StreamId].offSet = 0X0u; PCapIssCalcfg->pixProcCfg[StreamId].contextToBeUsed = FALSE ; retVal = Fvid2_control(pCamObj->pInstObj->drvHandle, IOCTL_VPS_CAPT_SET_ISS_PARAMS, PCapIssCalcfg , NULL); when use 1100*880 camera, we only change the MACRO VIDEO_IP_RAW_CAPTURE_WIDTH, AR_CAMERA_ACTIVE_VIDEO_IP_RAW_CAPTURE_HEIGHT from 1280,960 to 1100,880 but the image is not ok, you can see it, so what's the issue? SX

Xu, I assume that you are using TDA2 LInks and chains framework. So the camera input is a link. Can you share your modification? Additionally, Can you pls help to capture the camera data from camera link and share the image ? Thanks. Regards, Fredy Zhang

Xu, I checked your input Data. The width is 1088. So suggest that you can set the width to 1088. Thanks. Regards, Fredy Zhang

Ticket Name: Linux/TDA2PXEVM: Streaming data over USB

Part Number: TDA2PXEVM Other Parts Discussed in Thread: AWR1243, TDA2 Tool/software: Linux I have a TDA2PxEVM board mated to a custom board with cascaded AWR1243 radar chips. Currently we are streaming all the raw data from the EVM to a laptop via Gigabit Ethernet, but the data rate of the cascaded chips exceeds what Gigabit Ethernet can handle, so I want to use USB 3.0. Eventually we will do processing in the TDA2px, but for now we want to log and process the data on the laptop. I was told previously that the best way to use USB is to run Linux on the A15 core. I have a Ubuntu 18.04LTS development system. I am new to USB development and would like more specific advice about the best (and easiest) way to stream data over USB 3.0 and achieve as close to the 5 Gbps theoretical limit as possible. Questions: Is it possible/advisable to use Linux USB gadget drivers to send Ethernet traffic over USB? If so, perhaps that would minimize needed modifications to the existing code. Which is the best choice of gadget driver type to use that is supported? It appears that there are several different possible types of gadget drivers. How would I configure and use the gadget driver approach? Or, is there a better USB approach? Are custom drivers needed for the embedded or host? What practical data transfer rates should be achievable over USB 3.0? As a stopgap solution, I assume it would be easy to write to a USB SSD drive from embedded Linux? Are there any steps I would need to take to enable that (e.g. drivers to install)? Thanks!

Is it possible/advisable to use Linux USB gadget drivers to send Ethernet traffic over USB? If so, perhaps that would minimize needed modifications to the existing code.
 Explore the option of g_ether gadget driver. It emulates ethernet over USB and you can use that to connect to PC Which is the best choice of gadget driver type to use that is supported? It appears that there are several different possible types of gadget drivers. For streaming usecase, you can use USB UVC gadget(which will have ISO endpoints, which is in theory suited for streaming usecase). You can use g_ether gadget driver(Network overhead would be there, but minimal code change for you). You can use Mass storage gadget device g_mass_storage (CONFIG_USB_MASS_STORAGE kernel config) How would I configure and use the gadget driver approach? As a stopgap solution, I assume it would be easy to write to a USB SSD drive from embedded Linux? Are there any steps I would need to take to enable that (e.g. drivers to install)? 1. Make sure USB controller at TDA2x side configured as gadget. You can check here for example : 2. Enable USB Mass Storage Gadget driver with kernel configuration: as mentioned in this link : linux-sunxi.org/.../Mass_storage 3. You can enable USB ethernet driver as mentioned here : processors.wiki.ti.com/.../Networking_over_USB Or, is there a better USB approach? Are custom drivers needed for the embedded or host? Custom drivers would take a lot of effort from both TDA2x end and the PC end. Better would be go with Mass Storage Gadget or Gadget Ethernet over USB, as mentioned above. What practical data transfer rates should be achievable over USB 3.0? Please refer here for USB performance in TDA2x : www.ti.com/.../sprac21.pdf

This is the link to TDA2 performance document (the forum engine did not displayed it correctly in Dwarakesh's post): proddms.itg.ti.com/.../sprac21.pdf Regards, Yordan

Ticket Name: CCS/TDA2-17: About TDA2 Wiki

Part Number: TDA2-17 Other Parts Discussed in Thread: TDA2 Tool/software: Code Composer Studio Hi. http://processors.wiki.ti.com/index.php/TDA2x Most of the link on the above TDA2 Wiki are going. For ex: There is a product preview paper on TDA2x; 595-ADAS Applications Processor TDA2x System-on-Chip Technical Brief – OCTOBER 2013 http://focus.ti.com/general/docs/video/Portal.tsp?entryid=0_00ag9mtw&lang=en&DCMP=pro-ap-tda2x-131016&HQS=pro-ap-tda2x-pr-v2 Can anyone to fix the TDA2 wiki? THanks. BR Rio

Hi Rio, There are multiple documents for TDA2 available here: http://www.ti.com/tool/TDA2EVM5777#technicaldocuments Are you looking for a particular document that you cannot find? Regards, Rishabh

Ticket Name: TDA2SX: eMMC replacement

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi Team, In customer SOP project uses TDA2SXBTQABCRQ1 Due to the current shortage of eMMC, customer would like to replace the eMMC model to: Samsung KLMBG4GEUF-B04Q Need to confirm with you, does TDA2 support this series of eMMC models? Is there a driver or something that needs to be matched? Is there a list of eMMCs supported by TDA2 that can be provided to customer?

Hi Ti Team, could you please help confirm the question? thanks.

Hi, Any emmc part compliant with JEDEC 4.5 spec should work without any change. Regards, Vishal

Ticket Name: TDA2: IVAHD encoder sample application hangs at H264ENC_create

Part Number: TDA2 Hi I am trying to generate the encoded output file by running the TI ivahd encoder sample application TestAppDM816x/TestAppOmap4 on TDA2PX evm board but the application hangs at handle[insChanid] = H264ENC_create((H264ENC_Fxns *)&H264ENC_TI_IH264ENC, &gParams[insChanid]); I haven't modified any encoder configuration and i am running the default application. On suspend the running i am seeing the following error message in diassembly window: Memory map prevented reading 0xFEF4000C [code=0x20000] Any workarounds so that i should be able to generate the output file. Regards Mayank

Hi Mayank, Can you please single step through the code to localize where inside the H264ENC_create you are crashing? Typical reasons for a crash would be access to a memory space which is not mapped/understood by the CPU core. Thanks and Regards, Piyali

Hi, It is hanging in AlgInit function.Currently i am trying to run it on A15 core. Is there any procedure to run the sample application on multiple core or any other particular core. I tried running it on m4_0 and m4_1 core but with both it is giving similar results. Has anybody tried successfully running it.Please write in detail the procedure. Regards Mayank

Hi Mayank, I think you will have modify the Base address in \codecs\h264enc\app\test\inc\h264enc_ti_config.h The existing is for OMAP4 & NETRA. #define M3_HZ change this;//(250000000) #define MEM_BASE_IVAHD0 change this;//0xBB000000 #define REG_BASE_IVAHD0 change this;//0xBA000000 #define RST_CNTL_BASE_IVAHD0 change this;//0xAA306F10

Hi Prashant, Thanks for your mail.You mentioned in your mail that the above macros needs to be changed. Currently i am working on TDA2PX evm board,what would be the correct values of above macros for the evm that i am using. Regards Mayank

Hi Mayank, The base address will be present in the TRM of this target. Do you have the TRM?

Hi Mayank, The TRM is at http://www.ti.com/lit/ug/spruif0a/spruif0a.pdf The addresses would be #define MEM_BASE_IVAHD0 change this;//0x5B000000 #define REG_BASE_IVAHD0 change this;//0x5A000000 #define RST_CNTL_BASE_IVAHD0 change this;//0x4AE06F10 Regards, Piyali

Hi Prashant, Thanks for your continuous support. In the TRM that i am having for TDA2PX evm in the iva subssytem following lines are mentioned: NOTE: The IVA-HD subsystem is a set of video encoder and decoder hardware accelerators. The list of supported codecs can be found in the software development kit (SDK) documentation. The IVA-HD subsystem availability is device part number dependent. Refer to device Data Manual, for more information I could not find the register settings that you have mentioned in the TRM. Are you sure that these register settings will fix the crash issue. Regards Mayank

Hi Mayank, Please refer the above post from Piyali on the Address you need to set. I have not tried running the sample testapp on TDA2PX. But to run this code on different targets we will be using respective Base address. So, theoretically it should work.

Hi Prashant, Thanks for your continuous support.I configured the register settings as suggested by Piyali but i am getting the same crash at H264Enc_Create. Regards Mayank

Hi Mayank, Can you tell me the detailed procedure you followed to run this on TDA2PX? It would help to debug further.

Hi Mayank, We have not heard back from you on this one. I assume you were able to move ahead. Please let us know if otherwise. The thread would be closed automatically if there is no reply. Thanks and Regards, Piyali

Ticket Name: Linux/TDA2: function of the IPU1 and IPU2

Part Number: TDA2 Tool/software: Linux Hi , I found the following description on TDA2x Technical Reference Manual SPRUI29D chapter 7.1.1: The device instantiates two dual Cortex®-M4 image processor unit (IPU) subsystems. • IPU1 subsystem is available for general purpose usage • IPU2 subsystem is dedicated to IVA support and is not available for other processing And, on the vision_sdk links_fw/include/link_api/system_linkId.h, I can see only the IPU1_0's link id, for example, SYSTEM_LINK_ID_DISPLAY_0, SYSTEM_LINK_ID_VENC_0, SYSTEM_LINK_ID_VDEC_0. What's the function each IPU? Could I create the IPU2 link id to work? Thanks. Regards, Tianxing

Hi Tianxing, Both the IPUs are available for general purpose usage. This paragraph is leftover from a previous generation device and will be removed from the TRM. Regards, Rishabh

Hi Rishabh, Thanks, that's mean I can used IPU1 and IPU2 equivalent . However, vision sdk has not defined the IPU2 link. For example, SYSTEM_LINK_ID_CAPTURE_0, SYSTEM_LINK_ID_VDEC_0, it only belong to IPU1_0. If I want to used IPU2 to capture or decode, maybe I should define the link used IPU2_LINK? Regards, Tianxing

Hi Tianxing, Any link that is supported on IPU can be run on either IPU1 or IPU2. Capture, display are supported on both IPUs. Regards, Rishabh

Hi Rishabh, My question is that, should I define a decode link, display link or capture link id used the macro define: #define IPU2_LINK(x) (SYSTEM_MAKE_LINK_ID(SYSTEM_PROC_IPU2 , (x))) Thanks, Tianxing

Hi Tianxing, You need to change anything here. You should change only the primary core in cfg.mk and rest will be taken care depending on it. Regards, Rishabh

Hi Rishabh, Now, I set as follow: PROC_IPU1_0_INCLUDE=yes PROC_IPU1_1_INCLUDE=no PROC_IPU2_INCLUDE=yes PROC_A15_0_INCLUDE=yes PROC_DSP1_INCLUDE=yes PROC_DSP2_INCLUDE=yes PROC_EVE1_INCLUDE=yes PROC_EVE2_INCLUDE=yes PROC_EVE3_INCLUDE=yes PROC_EVE4_INCLUDE=yes IPU_PRIMARY_CORE=ipu1_0 IPU_SECONDARY_CORE=ipu2 I think if I want to create link on ipu2, I should define the ipu2 link Id, is right? And If I only set the ipu2 as primary, I need not care the link id. Regards, Tianxing

Hi Tianxing, Yes you need not care about the link id. Changing primary core is sufficient. Regards, Rishabh

Hi Rishabh, The another question is that if I used IPU2 and IPU1 both, the IPU2 link Id maybe defined, is right? Regards, Tianxing

Hi Tianxing, Please find the new TDA TRM here: www.ti.com/.../sprui29e.pdf Regards, Rishabh

Hi Tianxing, Is there an update on this issue? Regards, Rishabh

Ticket Name: TDA2SX: TDA2+ ACD Package information?

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Where can i find information regarding the packaging of the TDA2 plus ACD package.

Hi Julio, I wasn't able to find an ACD package for TDA2x. Did you mean ABC?

Hi Stanislav, Sure, can you point me to that information.

Hi, Julio, The information is in chapter 10 Mechanical Packaging and Orderable Information in Data Manual. You can download the data manual for the appropriate silicon revision from: Regards, Mariya

Mariya Petkova, Thank you for the information, i found out my question was on an unreleased device. Thank you, Julio

Ticket Name: TDA3XEVM: TDA3 RVP loads eve binary failed when debugging on CCS

Part Number: TDA3XEVM Other Parts Discussed in Thread: TDA2 Hi sirs, I am now doing porting TIDL OD on TDA3. I met some issus (), so I try to debug on TDA3 RVP. When I loaded EVE binary file, it was failed. The error is: ARP32_EVE_1: Trouble Reading Memory Block at 0xa1000000 on Page 1 of Length 0x4: (Error -1065 @ 0xA1000000) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.3.0.00003)
ARP32_EVE_1: File Loader: Verification failed: Target failed to read 0xA1000000@Data
ARP32_EVE_1: GEL: File: C:\PROCESSOR_SDK_VISION_03_07\vision_sdk\binaries\apps\tda3xx_rvp_bios_all\vision_sdk\bin\tda3xx-rvp\vision_sdk_arp32_1_release.xearp32F: Load faile Can you give me advise to fix this problem? Thank you, Gary

Hi Gary, can you check if you have following macros in the GEL file: VISION_SDK_CONFIG -> 0 EVE_SW_CONFIG -> 1 You can check section "3.6 Setup EVE in CCS" in PROCESSOR_SDK_VISION_03_07_00_00\ti_components\algorithms\eve_sw_01_20_00_00\docs\eve_sw_getting_started.pdf for detailed setup instructions. Regards, Yordan

Hi Yordan, I check my gel file (TDA3xx_multicore_reset.gel) and change #define VISION_SDK_CONFIG -> 1. I didn't see EVE_SW_CONFIG, so I did nothing for this. The error remained the same after following steps in "3.6 Setup EVE in CCS" Is there any other way to cause this error? Does there any boot mode need to be set like TDA2? Although I don't see that on TDA3 user guide. ps. I work on TDA3 rvp board. Thank you, Gary

Hi, To debug the EVE image of vision SDK, you need to disable all the gels because vision SDK already setups all the register when you boot from flash or SD card and choose the 'load symbol' option of CCS. regards, Victor

Hi Victor, I'm not clear about "disable all the gels". Do you mean not to run "TDA3xx_MULTICORE_EnableAllCores" and then load program file for each core by using "load symbols"? Thank you, Gary

Hi Gary, Some gel are automatically loaded when starting the debug configuration.The best method to avoid that is to create new TDA3x target configuration, select advanced tab and remove the default initialization script from the input 'initialization script'. box. For Cortex_M4_IPU1_C0, remove TDA3xx_cortexM4_startup.gel, for CS_DAP_DebugSS remove TDA3xx_dap_startup.gel. I have attached a snapshot of the CCS window when you create the default tda3x target configuration, it shows the presence of the initialization script. For your debugging purpose, you just need to remove the scripts before saving the configuration. regards, Victor

Hi Victor, Thank you for your clear reply. Gary

Ticket Name: Linux/TDA2: PCIe communication two boards RTOS

Part Number: TDA2 Tool/software: Linux Hi, I have seen example for PCIe write_loopback for EP and RC for TDA2xx RTOS. How can we make this to communicate two TDA2x boards, one EP and one RC ?

Hi, Can you see processors.wiki.ti.com/.../PDK_TDA_CSL_User_Guide Regards, Rishabh

Hi, If I try to compile the example I am getting a message like this:- Nothing to be done for tda2xx-evm tda2xx a_15 csl_pcie_rc_write_loopback_app

Hi, The CORE should be a15_0. Regards, Rishabh

I explicitly added CORE param as a15_0 in make command , made a change in source code. cleaned the build, rebuilt, still did not compile.

You don't need to make any changes in source code. Refer to processors.wiki.ti.com/.../PDK_TDA_Building_The_Package on how to build PDK examples. Regards, Rishabh

Can you list the steps you are following. Also make sure that you have removed all custom changes. Regards, Rishabh

Ticket Name: PROCESSOR-SDK-DRA8X-TDA4X: Which core is use for CPSW2? & CPSW2 work in core mcu2_1

Part Number: PROCESSOR-SDK-DRA8X-TDA4X Hello Sir, I trying to initialize all the CPSW2 deriver on MCU2_1. In the vision App application UDMA driver is already initlizsed in the mcu2_1 core. So whenever I try to run the function CpswAppUtils_udmaOpen, it crashed. 1. Can I use the handle of initialized UDMA? If yes what are the changes required. 2. Is CPSW2 work in core mcu2_1? (Cpsw2 design for the mcu core only.). 3. Which other core is use for CPSW2? Thank you VIjender

Vijender, CPSW2G currently is supported on Linux, on A72 core. Rgds, Brijesh

Ticket Name: TDA4: Floating point exception (core dumped) when running tidl_demos

Other Parts Discussed in Thread: TDA2 I trained a caffemodel by caffejacinto and imported it by tidl importer successfully. But I runned the tidl demo in TDA4 RASDK vision apps called apps_tidl_od using my caffemodel, there is an error The logs is shown below. 0.0s: VX_ZONE_INIT:Enabled 0.28s: VX_ZONE_ERROR:Enabled 0.31s: VX_ZONE_WARNING:Enabled Computing checksum at 0x00007FAA51E91F50, size = 252384 Floating point exception (core dumped) What's the reason about the error and how should I do to avoid it? By the way, the caffemodel works well on TDA2.

Can you please tell the exact PSDKRA version you are trying?

psdk_rtos_auto_j7_07_00_00_11 Actually, this problem has been solved by updating the image preprocess kernel code. I think it can be closed. thank you!

Ticket Name: Linux/TDA2: A15 (Linux) EVE chain. How does it works?

Part Number: TDA2 Tool/software: Linux Hi, I have read in manual that A15 can't get acsess directly to EVE cores, and using IPU is recomended to organize link to EVE. When I set chain from A15 to EVE, vision sdk (I use 3.4) automatically connect cores throw IPU or I should do this manually? And I have quenstion about EVE configuration under Linux. In manuals is next steps: 1. Get .xearp32F 2. Convert .xearp32F -> .h (bin to hex converter utility was used). It means convert binary to header file like for TI Logo is used in sample app? bin to hex converter utility was used is uncluded in vision sdk? 3. What finction I should call to load program to EVE from IPU?

Hello For "vision SDK Bios only" version EVE cores are handled same as any other cores like DSP or M4. With "vision SDK Linux" EVE loading and all inter processor communication between A15 and EVE are automatically taken care by EVE loader of VSDK, Its routed via IPU, Integreator/App need not to do anything special to address this. EVE firmware .xearp32F is embedded in IPU2 binary, yes, you are correct, SDK had tools to Convert .xearp32F -> .h (bin to hex converter utility used). you do not need to do anything special on IPU to program EVE, just port your Algos to EVE, create the UC on A15 as usual and build VSDK Linux, rest all are taken care in VSDK regards, Shiju

Ticket Name: TDA2E: MMWCAS-DSP-EVM

Part Number: TDA2E Other Parts Discussed in Thread: TDA2, MMWCAS-DSP-EVM I am using MMWCAS-DSP-EVM and want to program the DSP inside TDA2. I can connect the A15 with no problem but not the DSPs.How to connect DSP using JTAG/?

Hello, I am directing your inquiry to the domain engineer best able to support you. Best, Kelvin

Hi Kelvin Thanks! BR Jack

Hi Kelivin For how long I can get the result? Thanks! BR Jack

Hi Chung, Can you confirm if you have followed all the steps from section 3.9 of the following document? PROCESSOR_SDK_RADAR_03_08_00_00/vision_sdk/docs/UserGuides/VisionSDK_UserGuide_TDA2xx.pdf Regards, Kaushik

Hi Sir It is not working for me. Please advice what I can do for next step. Sorry, I do need help on this. BR Jack

Hi Sir I also gotthis. BR Jack

I did not find the zip field in my folder. BR Jack

Hi Chung, Please find the link below: https://software-dl.ti.com/sdo/sdo_apps_public_sw/CCSv9/auto_rvp_rsp_device_support_1.1.8.zip You should get the required GEL files from this package. Alternatively, you can add this product (TDA2) on the latest version of CCS installation as well. Regards, Kaushik

Hi Kaushik It is stil not working for me. I got the message for connection test through CCS12. [Start: Spectrum Digital XDSPRO USB Emulator] Execute the command: %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity [Result] -----[Print the board config pathname(s)]------------------------------------ C:\Users\jackho\AppData\Local\TEXASI~1\CCS\ ccs1250\0\0\BrdDat\testBoard.dat -----[Print the reset-command software log-file]----------------------------- This utility has selected a 560/2xx-class product. This utility will load the program 'sd560v2u.out'. The library build date was 'Sep 6 2023'. The library build time was '14:41:42'. The library package version is '9.13.0.00201'. The library component version is '35.35.0.0'. The controller does not use a programmable FPGA. The controller has a version number of '6' (0x00000006). The controller has an insertion length of '0' (0x00000000). The cable+pod has a version number of '8' (0x00000008). The cable+pod has a capability number of '7423' (0x00001cff). This utility will attempt to reset the controller. A error occurred while attempting to reset the controller. -----[An error has occurred and this utility has aborted]-------------------- This error is generated by TI's USCIF driver or utilities. The value is '-128' (0xffffff80). The title is 'SC_ERR_CMD_INVALID_MULT'. The explanation is: Unified-SCIF is operating in multiple client mode. The operation being attempted is invalid in this mode. It is likely a problem with `SC_CMD' in SMG_call(). [End: Spectrum Digital XDSPRO USB Emulator]

hI Kaushik I got them all connected. thanks!

Ticket Name: TDA2x EVM (Vayu EVM): DDR3 reset signal and VTT turn off

Other Parts Discussed in Thread: TDA2 Hello team, I have two questions about DDR3 reference schematic in Vayu EVM (516582G4_VAYU_EVM_03MAR_2015A.pdf). 1. In Vayu reference schematic, DDR3 reset signals (DDR1_RST, DDR2_RST) come from 1V35_DDR power, not from TDA2 DDR reset singals (AG21,R24). Is there any specific reason not to use TDA2 DDR reset signals? 2. In Vayu reference schematic, VTT regulation LOD includes TR circuit on VTT supply. It looks to discharge VTT supply when it is off. What is the specific reason to add this kinds of circuit, and is it the mendatory for VTT supply? Best regards, Lloyd

Hello Lloyd, All this is to support Suspend-To-RAM (STR), aka Fast Suspend-Resume (FSR). During STR the DDR3 memories must of course remain powered while the SoC is entirely off (except for possibly its RTC domains), and they must NOT be in reset (otherwise the memory chips shall exit the Suspend state and loose their contents). Therefore the DDRx_RST signals are derived from the PG output of the memory subsystem power buck (if you notice, the DDR3 supply for the SoC goes through a switch that is off during suspend, but the buck stays on). The SoC reset outputs pull low while it is off and would reset the chips if they were used for this purpose. On the other hand, the memory chips must see a stable low on CKE while in suspend. Therefore we actively discharge VTT, so that no glitches occur on CKE during the power-down (upon suspend entry) and power-up (upon resume) sequences - these are possible through the termination resistors of the other C/A bus signals. If STR/FSR is not a design requirement, the active discharge circuit is not needed, and the DDR3 resets can be driven by the SoC. Hope this answers your questions. Best regards, Lubo

Ticket Name: [TDA4M] Question about the removal of AUDIO_EXT_REFCLK source

Other Parts Discussed in Thread: TDA2 Hi, I have a question about AUDIO_EXT_REFCLK clocks. If audio functions are not used, can you confirm that AUDIO_EXT_REFCLK0/1/2/3 clock related circuit can be removed and these audio external clocks are only used for MCASP or other usages? Regards, Soolim

Hi Soolim, These clocks are similar to those in TDA2/TDA3, i.e. they are used for MCASP, ATL, and AASRC and are not mandatory if you will not use all of these audio modules. Regards, Stan

Ticket Name: TDA2: How to config MJPEG Encoder to support lossless mode?

Part Number: TDA2 Dear Champs, My customer would like to use IVAHD to encode lossless MJPEG. Per MJPEG_Encoder_HDVICP2_UserGuide.pdf (under \ti_components\codecs\ivahd_jpegvenc_01_00_16_01_production\packages\ti\sdo\codecs\jpegvenc\docs), lossless mode is supported but the config method is not mentioned all thru the user guide. Could you help provide the config method? Thanks.

Hi, Lossless Mode is not supported for Mjpeg Codec. Regards, Anuj

Ticket Name: Linux/TDA2: change C66link

Part Number: TDA2 Tool/software: Linux Hi: i am use SDK_VISION_03_04_00_00 uenv.txt is fdtfile=dra7-evm-infoadas.dtb args_mmc=setenv bootargs 'console=ttyO0,115200n8 vram=16M root=/dev/nfs rw nfsroot=172.17.218.22:/home/hancan/PROCESSOR_SDK_VISION_03_04_00_00/ti_components/os_tools/linux/targetfs rootwait ip=dhcp mem=1024M' i change code of hlos just build and reboot ,but if i chage code of rtos (for exmple SDK_VISION_03_04_00_00\vision_sdk\apps\src\rtos\alg_plugins\framecopy\ frameCopyAlgoLocalDma.c ) i have to copy firmware of C66 to sd ( PROCESSOR_SDK_VISION_03_04_00_00/ti_components/os_tools/linux/targetfs/lib/firmware$ sudo cp dra7-* /media/hancan/rootfs/lib/firmware/ ) if not copy the chage is not done. how to solve this ? shuai

Hi Shuai, If you use NFS as your filesystem instead of an file-system on the SD card, then you can set the LINUX_TARGETFS in build/tools_path.mk file to point to your filesystem. Similarly you need to use the uenv_nfs file present in build/hlos/scripts/linux/ folder and update the nfsroot variable to point to the IP address and the folder on your PC. If you're having the file-system on your SD card, then you must copy the firmware every-time. Regards Shravan

Ticket Name: RTOS/TDA2SX: TDA2 A15 generic timer

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hi, I try to use generic timer as MPU system tick source, but I found that only IPU 1_0 boots normally. What should I do to use generic timer? Thanks&Regards.

Hi, can you check chapter "7.1.2 BIOS Tick and Time Stamp Provider Concerns" in vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_DevelopmentGuide.pdf and see if it can give you some directions? Regards, Yordan

Hi Yang, Can you explain what you mean by "only IPU 1_0 boots normally". Also MPU timer is used by TDA2 SBL. You can refer to the same. Regards, Rishabh

Hi, On the UART console, I can only find logs output by IPU 1_0.

Hi Yang, Can you share the UART log? Regards, Rishabh

Hi, I have found the reason. When A15 idle and execute PMLIBCpuIdle function, A15 sleeps and its clock is gated. This results in generic timer stopping work, so A15 can not be waked up by system tick.

I have another question. In function PmlibDoWFI, ACTLR.SMP is set to 0. But I can't find this bit is enabled again after wake-up. When SMP bit is set again?

Hi Yang, Yes.. the timer inside the A15 would stop if clock gated. You should used the SoC level GP Timers for the OS Tick instead to allow the A15 to wake up from low power. Thanks and Regards, Piyali

Yang, The SMP bit should be set again in the ISR context which after it wakes up. Are you using the dual A15 subsystem in SMP mode? If no, then you would not need to set this back to 1. However, if you are setting the A15 to work in SMP mode you would need to set the ACTLR.SMP in the ISR routine which is run after the A15 wakes up from low power. Thanks and Regards, Piyali

Hi, Piyali Yes, I am using MPU in SMP mode. OK. So user should be responsible for setting SMP bit again. I think this is not convenient, because every ISR should do this in theory. Is it necessary that disable SMP before sleep? Is the reason for clearing SMP bit that A15 power is placed in retention state after sleep?

Hi Yang, The clearing of ACTLR.SMP bit is required before going to retention or placing the Cortex A15 in power off mode (power down modes). You need not to place the setting of SMP in all user ISR routines. This is only required in the function which is called when IRQ or FIQ is triggered. (2 interrupts). The other user-defined ISRs are called only after this from these two functions. You can skip this if you are only getting the A15s to clock gated (power on) state. Thanks and Regards, Piyali

Hi Piyali, OK. Thank you! By the way, I think TI should update SDK or at least make a statement about this.

Ticket Name: How to use IPU1_0 instead of A15_0 to process NDK in TDA2x-EVM

Hi all, When NDK_PROC_TO_USE=a15_0 by default, the target works normally. But when I set NDK_PROC_TO_USE=ipu1_0, the target halts after run. ipu1_0 is halted at Network_waitConnect() and the return status is 0. Meanwhile, there is no longer any response from UART when I try to send cmd to it. I have tried ipu1_1, the same result appeared. I did have done "gmake -s depend" before "gmake -s" as the guide metioned. my VSDK version is 2.08 I wonder if someone could help me. Thanks a lot.

Hello Benz, Can you send output of gmake -config after configuring NDK_PROC_TO_USE=ipu1_1? Also have you tried doing clean build after making changes? (remove binaries folder) Regards, Prasad

Hello Prasad, Thank you for you tips. I did "gmake -s clean" before build cmd, and the target works well.

Ticket Name: TDA4VM: TDA4 RTOS SDK network utilities

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi, In TDA4 RTOS SDK, do we have something similar as the TDA2.TDA3's network_rx, network_tx tools ? I saw that we have some ETHFW demo involving Plex media server but I just need a simple client/server example app that is able to save a file on PC over ethernet. regards, Victor

Hi Victor, No simple utility on RTOS of the kind you are looking for. Can you spell out your requirement : Do you want to stream a file from your EVM to your PC ? or do you want to use the CPSW 9G as a switch and connect multiple devices over it ? Regards Vineet

Hi Vineet, I actually implemented the tool since it didn't exist on TDA4. The ticket can be closed. Thanks. regards, Victor

Ticket Name: Can TDA2 plus ISP handle RCCB format?

Hello, Can ISP handle RCCB raw format? If not possible, is it limitation of HW or SW? Best regards, Wilson.

Hi Wilson, I think it can, have a look at the AppNote @ www.ti.com/.../spraca8.pdf Regards, Brijesh

Brijesh, Thanks very much.

Ticket Name: TDA2P-ACD: Whether we have the AVS voltage gap between OPP_LOW/OPP_NOM/OPP_OD/OPP_PLUS

Part Number: TDA2P-ACD Hi experts: Our customer want to use MCU ADC monitor the VDD_MPU/VDD_DSP/VDD_GPU PMIC voltage is match with software AVS setting. They want to know every AVS level the gap is fix or random value? It means that MCU get AVS Efuse value, they want to use fix +/-6% margin to judgement PMIC output voltage is right or wrong. As DM said the AVS range is -3.5%, +5%.We know that voltage for OPP_OD > OPP_NOM, but I believe +/-6% margin is too big. We do not know the AVS voltage distribution of TDA2P. Please help us review it? Best Regards! Han Tao

Hi Han Tao, I suggest the customer should compare the voltage on the rails to the EFUSE value per sample. That way the variance is only driven by the step voltage size of the PMIC which is a fixed value and one does not have to take in to account the % variance in the AVS per sample. Basically read voltage from ADC and the compare against EFUSE for sample +/- PMIC step voltage. The EFUSE value can be read from TDA2PX and passed on to MCU using SPI or I2C or which ever communication mechanism present between TDA2P and MCU. This can be a one time thing per ECU and stored in MCU flash as well. Thanks and Regards Piyali

Ticket Name: PROCESSOR-SDK-TDAX: TPS659039 Power Diagnostic

Part Number: PROCESSOR-SDK-TDAX Other Parts Discussed in Thread: TDA2 Hi, We would like to implement Power Diagnostic via TPS659039 INT pin and reading Register Status. These status will be monitored, •VSYS_MON •HOTDIE •SHORT •WDT I have a question, if these issues happen(for example - SHORT), could TDA2 possibility work fine and read the PMIC register? Br, Yuki

Hi Yuki-san If the PMIC fails the TDA would not be working fine. Hence having a diagnostic from TDA in a fail situation would not be helpful. Thanks and Regards Piyali

Ticket Name: TDA2: Integrating multi kernel

Part Number: TDA2 Hi guys, I am trying to integrate two kernel in the eve applet with BAM,but the graph creation fails with this error message: printf("Graph construction failed!!! Decrease the value of BLK_WIDTH or BLK_HEIGHT\n"); I tried with: --> block width =8 & block_height=8 -->node list,edge list & the parameters i checked. Any help is appreciated. Regards Surbhi

Hi Surbhi, This indicates that with current block sizes the internal memory is not enough. Given that you are already trying a very small block size I am suspecting that some of the parameter's for the BAM node is not correct. Can put a break point at BAM_autoAllocMemRec function and step in to see which parameter is in-correct. This is the function where all the internal memories are allocated. Regards, Anshu

Hi Surbhi, Were you able to make progress on this issue? Regards, Anshu

Ticket Name: RTOS/TDA2SG: About CNN Performance

Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS Hi SIr Does TI have any performance report about CNN calculation and the unit is Tops for TDA2 and TDA3. for NXP S32V23x , the CNN accelerator is about 10 Tops by using Apex V3 with 4xA53/1xM4. please advise BR Yimin

Hi Yimin, please check TIDeepLearningLibrary_DataSheet.pdf in "PROCESSOR_SDK_VISION_03_06_00_00\ti_components\algorithms\REL.TIDL.01.01.03.00\modules\ti_dl\docs" directory. Regards, Yordan

Ticket Name: RTOS/TDA2SX: VPE scale function

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Tool/software: TI-RTOS We use hardware VPE scale successfully on TDA2. We want to simulate VPE scale function on PC side. Do you have VPE scale function by C code.

Hi Joe, I have forwarded your question to an expert for comment. Regards, Yordan

Unfortunately, no we don't have PC code for VPE. Please talk to your local FAE to see if there is any way. Rgds, Brijesh

Ticket Name: RTOS/TDA2: compiler Error : undefined

Part Number: TDA2 Tool/software: TI-RTOS Hi, We create an new use case it is the flow below but when I do "gmake -s -j" it show the error below where should I define them? BR Allen

Hi Allen , In the sdk we support only one instance of file read hence the 2nd instance throws a error 2 file read is not tested in the sdk . Regards Chetan.M

Ticket Name: RTOS/TDA2: Problems with integrating existing framecopy algorithm into existing NetworkRxDecDisplay UseCase

Part Number: TDA2 Tool/software: TI-RTOS Hello, We are working on a TDA2xx EVM with Bios (tda2xx_evm_bios_all) We tried to integrate the framecopy algorithm into the NetworkRxDecDisplay UseCase. (See picture) The defaul unedited NetworkRxDecDisplay UseCase is working fine, but the new edited UseCase doesn't work. It starts, but when we start to stream the data from the pc to the Board, this error occurs: PC side: Does anyone know, how we can fix that? Kind Regards

Hi , On which core are you running networking .? A15 or ipu1_1 From figure it shows a15 but from log it says ipu1_1 Regards Chetan.M

Hello, we set NDK_proc_to_use to ipu1_1 in build-config Regards

but the usecase you have generated network rx on A15 . ? Can you try changing it on ipu ( core where you have networking enabled) . ? Regards Chetan.M

But the standard NetworkRxDecDisplay UseCase (without the framecopy) works fine. We can send video data with the network tx tool and it's displaying on the display without an error Regards

Sorry this use case is a bit confusing... In the use case Picture, it seems to indicate the NetworkRx is running on A15 but it will actually be overwritten in chains_networkRxDecDisplay_SetAppPrms() depending on where the NDK_proc_to_use is set. So, in reality, since NDK_proc_to_use=ipu1_1, the NetworkRx link will be running on IPU1_1. We do that because we want to make the same use case code working wherever NDK resides. When you create your own use case, you have to create NetworkRx Link on the same core as the NDK_proc_to_use is set.

Hello, ok, thanks for the explanation . We will try it with the NetworkRx link created on ipu1_1 and let you know if it works then. Thanks and regards

Did it solve the issue , Please close the thread if the issue is solved Regards Chetan.M

Ticket Name: Linux/TDA2: Building .so library

Part Number: TDA2 Tool/software: Linux Hi everyone, I'm trying to build shared object library instead of apps.out executable for VisionSDK 3.04 on Linux. As far as I can see, in common_footer_a15.mk there is a target so: and it should build shared object. However, I am unable to find out setup to build shared object instead of executable. Configuration for which I am trying to build is tda2xx_evm_linux_all. Does anyone have experience with this? Thanks in advance, Sasa

Hi, In VSDK we do not build .so file but you can build .a files. Please check how all a15 links has been build. Regards, Anuj

Ticket Name: TDA2SX: Running python script for additional proccessing

Part Number: TDA2SX Other Parts Discussed in Thread: AWR1243 Hi, I am running the TDA2SX board with an AWR1243 attached for cascade radar imaging with the processor SDK radar (RTOS). Is it possible to add a python script within the processing pipeline on the board before being sent through the network to my PC? If not, would it be possible/advisable if I switched to vision SDK on linux instead? Thanks, Stefan

Hi Stefan, We don't have support for python script. What are you trying to do with python script? You can run Linux Vision SDK. However, there is radar processing support, only radar ADC data capture. Regards, Stanley

Hi Stanley, Thank you for your reply! The idea is to utilize as much of the board as we can by adding additional processing code on it. I'm not sure what type of processing my team would like to do, but it would be easier for them to write this code in Python rather than C. Thanks, Stefan

Our compiler can only support C/C++ code.

Ticket Name: How to cross compile tidl-api-master (with examples) from source code with gcc-arm-none-eabi-9-2019-q4-major-x86_64-linux toolchains?

How to cross compile tidl-api-master (with examples) from source code with gcc-arm-none-eabi-9-2019-q4-major-x86_64-linux toolchains? Can anybody give me a clue about it?

What is the SDK version and TIDL version that you are using ? Thanks, Praveen

Hello, My version is Vision SDK 3.04. Thanks

Could you point this folder "tidl-api-master " in SDK ?

Thanks for the response, How can i do that? Could you please explain a bit? Should i do it by changing Makefile under "/../PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/build" directory

Hi, Which processor platform are you using ? Because vision_sdk is the software for TDAx platform and TI-DL is accessed through openVX framework, not through tidl-api-master. tidl-api-master runs on Sitara platform.

My platform is tda2xx. I pointed makefile of the tidl source code from sdk makefile by adding $(MAKE) -C $(vision_sdk_PATH)/tidl-api-master . But after making some environment corrections in tidl make file i get some compile errors. First opencl version used in tidl code is different from the one in vision sdk 3.04. Second boost library is used in tidl and it is not exist in sdk. I dont know any other type of inconvenience will appear. What is the compatible versions of boost and opencl libraries for tidl source code? Any suggestion will be appreciated... i compiled boost and solved appeared errors making patch in the link below. https://patches.linaro.org/patch/59550/ Thanks

I want to use "tidl-api-master" in "TDA2xx" platform. is it possible cross compile and use it with TDA2xx platform instead of Links and Chains Concept? There are very few TIDL example in VisionSDK with Links and Chains Concept.

No, it is not possible. The TIDL software programming and support is different in these two SDKs Thanks, Praveen

Ticket Name: Linux/TDA2: How to get the serial number of the chip of tda2x

Part Number: TDA2 Tool/software: Linux How to get the serial number of the chip of tda2x

Hi, shuai wang32, Please refer to 1.5 TDA2x Device Identification section in Technical Reference Manual. Regards, Mariya

Hi, Please refer to Table 1-2. DIE_ID in the device TRM. Although not explicitly stated, I think DIE_ID is a unique die ID identificator. Regards, Stan

Hi Stan I'm going to use the only chip ID to encrypt it. Table 1-2. DIE_ID Is it appropriate？ shuai

Hi Shuai, Yes this is correct. Regards, Rishabh

HI Rishabh: HOW CAN I get the DIE_ID number on A15 in linux! unsigned int chipid[4]; chipid[0]=STD_FUSE_DIE_ID_0; chipid[1]=STD_FUSE_DIE_ID_1; chipid[2]=STD_FUSE_DIE_ID_2; chipid[3]=STD_FUSE_DIE_ID_3; printf("chipid[0]=%d ,chipid[1]=%d,chipid[2]=%d,chipid[3]=%d\n",chipid[0],chipid[1],chipid[2],chipid[3]); chains_main.c:142:12: error: 'STD_FUSE_DIE_ID_1' undeclared (first use in this function)

Hi Shuai, These are registers in the Control Module. Search for CTRL_WKUP_STD_FUSE_DIE_ID_0(0x4AE0 C200) in Control Module chapter in TRM. Regards, Rishabh

Hi You will not be able to just access the device physical registers on Linux Linux uses a full fledged MMU to ensure isolation between Kernel and user mode access Accessing device register from an User application is typically not allowed unless you are writing a user space driver for a peripheral If it is for some debug you can use tools such as omapconf( github.com/.../wiki) to temporarily map the device registers and read/write to it

I have a A15 algorithm link needs to be encrypted and used for users, I want to use chip ID to correspond to encrypted files, so how do I get the chip ID in the A15's algorithm LINK? In this way, I can verify whether the chip ID matches the encrypted file.

Hi Are you suggesting that you would like to use the chip ID as an input for the encryption process - is the encryption based on the chip id itself or a device unique key

Hi Sriram based on the chip id itself ！ BESTwishes shuai

Using a emulator can look at the register of ID ， also read Physical Address, but canot read Physical Address in code of linux.

****** Segmentation fault caught .... Faulty address is 0x4ae0c200, called from 0xb6c4d1a9 Totally Obtained 0 stack frames. signal number =11 Signal number = 11, Signal errno = 0 SI code = 1 (Address not mapped to object) Fault addr = 0x4ae0c200 [bt] Execution path:

Hi Can you clarify where will you need to read the chip id from If it is from user space, you have to resort to one of the following 1. Read from RTOS(on M4) , pass this information as part of IPC to application on A15 2. On A15 Use tool like omapconf and some scripting to pass this information to your application 3. Emulate ompaconf type mapping from a custom driver to map and read the device id information

Hi：Sriram i want to read chip id on A15 algorithm link !

Hi：Sriram On A15 Use tool like omapconf is there any sample or document for guide ! shuai

Hi For omapconf usage refer wiki link : github.com/.../wiki

Hi Shuai, We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Ticket Name: Linux/TDA2: No reading u-boot.img

Part Number: TDA2 Tool/software: Linux Hi Expert, I'm running Linux Vision SDK v03.02.00(4.4.84) on TDA2Ex. After completing mk-eMMC-boot.sh, the following error occurred during startup. Could you please give some suggestion here? If the sd card can start normally, but it will fail in saveenv, is it related? Thanks in advance.

Hi, Are you sure the boot and root-fs partitions are correctly mounted on the emmc partition? To ensure this, please follow the below steps: 1. Boot from SD card by using the below SYSBOOT settings (this is setting it to forcefully boot from SD card, you may want to halt at u-boot and run env default -fa and saveenv) : SYSBOOT[0:15]: 00001100 10000001 2. Mount the emmc boot and rootfs partitions of emmc using the mount command to ensure the boot and rootfs partitions are flashed correctly into EMMC mount /dev/mmcblkxpy /media/boot # mmcblkx is the emmc media, py is the boot partition mount /dev/mmcblkxpb /media/rootfs # mmcblkx is emmc media, pa is the rootfs partition If you're not able to mount it, please reflash the emmc 3. Once this works, please set the SYSBOOT settings to below (this is setting it to forcefully boot from EMMC, you may want to halt at u-boot and run env default -fa and saveenv): SYSBOOT[0:15]: 00011100 10000001 You should see the board boot normally. Regards Shravan

Hi, 1. Halt at u-boot and run env default -fa and saveenv. 2. Mount the emmc boot and rootfs partitions of emmc. 3. Boot from EMMC, halt at u-boot and run env default -fa and saveenv. but the board not boot normally. Could you please give some suggestion here? Thanks in advance.

Hi, There seems to be an issue with MLO and u-boot.img built. Can you please checkout the tag 'REL_VISION_SDK_03_02_00_00' on u-boot and rebuild it? (run make linux from Vision-SDK). Also ensure your USERCONFIG (SW5) switch-settings is as below. SW5 [1:10]: 00101 00000 Regards Shravan

Ticket Name: Linux: TDA2 PROCESSOR_SDK_VISION_03_07_00_00 new-usercase draw Ti logo

Tool/software: Linux Hi I builded a new usecase "my_usecase", and I wanted to draw Ti logo first a. MAKECONFIG?=tda2xx_evm_linux_all b. my_usecase.txt UseCase: my_usecase GrpxSrc -> Display_Grpx c. grpxSrcLink_my_usecase.c Int32 GrpxSrcLink_my_usecase_draw(GrpxSrcLink_Obj *pObj) { Draw2D_RegionPrm region; Draw2D_BmpPrm bmpPrm; /* fill full buffer with background color */ region.color = DISPARITY_BACKGROUND_COLOR; region.colorFormat = SYSTEM_DF_BGR16_565; region.startX = 0; region.startY = 0; region.height = pObj->info.queInfo[0].chInfo[0].height; region.width = pObj->info.queInfo[0].chInfo[0].width; Draw2D_fillRegion(pObj->draw2DHndl,&region); /* draw bitmap's */ /* TI logo */ bmpPrm.bmpIdx = DRAW2D_BMP_IDX_TI_LOGO_1; Draw2D_drawBmp(pObj->draw2DHndl, 1600 +80, DISPARITY_FRAME_THICKNESS, &bmpPrm ); return SYSTEM_LINK_STATUS_SOK; } I had build and run apps.out, I only got "Hello" and "test" from Vps_printf of my_usecase.c in usecases. But nothing output of logo or icon . It is still show 1920*1080 and FPS from HDMI on my output device Do any link or display function not set for my usecase to draw logo ?

Hi, Have you looked at the application present in the sample_apps folder which displays the TI logo on the screen? This sample chain to display content to screen can be found in the sample_app/src/hlos/usecases/nullSrc_display folder and uses the nullSrc link. Regards Shravan

Ticket Name: TDA2SX: Http server out of memory error

Part Number: TDA2SX Hi TI experts, we use custom board with TDA2x and run http server. Errors occur when opening the web interface: [IPU1-0] 23.601994 s: ### XDC ASSERT - ERROR CALLBACK START ### [IPU1-0] 23.602055 s: [IPU1-0] 23.602238 s: out of memory: handle=0x86c72264, size=65544 [IPU1-0] 23.602330 s: [IPU1-0] 23.602360 s: ### XDC ASSERT - ERROR CALLBACK END ###

Problem was solved by increasing heapMemParams.size in Ipu1_0.cfg.

Ticket Name: RTOS/TDA2: fail of a new use case

Part Number: TDA2 Tool/software: TI-RTOS Hi, Our FAE told us a new flow below for our use case It's img file below but we got the error below Can you tell us where is wrong? BR Allen

Hi Allen , If you trace the error , the return of Draw2D_setBufInfo is SYSTEM_LINK_STATUS_EINVALID_PARAMS the function is defined in draw2d.c file Please go through the function and verify if all the required parameters are set fine . Regards Chetan.M

Ticket Name: TDA2: miss zlib when build opencv

Part Number: TDA2 Hi, I want to build opencv on tda2 board and VSDK 3.0. clone the file on http://git.ti.com/opencv Then, got some error message like this Linking C static library ../lib/libzlib.a Error running link command: No such file or directory make[2]: *** [3rdparty/lib/libzlib.a] Error 2 make[1]: *** [3rdparty/zlib/CMakeFiles/zlib.dir/all] Error 2 make: *** [all] Error 2 although, i didn't choose build_zlib How can i fix this problem?

Hi, could you try to apply the patches for opencl as described in chapter "2.4.2.2.4 Opencl supported package" in VisionSDK_Linux_UserGuide.pdf and try to rebuild? Regards, Yordan

Ticket Name: Linux/TDA2: Matrix transposed

Part Number: TDA2 Tool/software: Linux how can i make Matrix transposed fast can EDMA done? 256*64 to 64*256 thanks!

Hi Shuai, can you check this post and see if it can give you some directions: e2e.ti.com/.../1447538 Regards, Yordan

Ticket Name: TDA2PXEVM: please share EVE Programmer's Guide doc to us

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 HI my friends, recently, we are developing on TDA2 , and we need to study EVE, but we don't have EVE's programmer guide, we need it. please share it to us. Thanks a lot. Best Regards, Charles.Shu

Hi Charles, it requires NDA, so you may need to contact your local TI's representative and we can enable via TI CDDS delivery mechanism for you Regards, Pramod

Ticket Name: RTOS/TDA2: How CCS uses c++ to compile

Part Number: TDA2 Tool/software: TI-RTOS 1、Using CCS8.2, create a new opencv project on the A15 module. When compiling, the following error occurs. How to solve it? C:/ti/ti_components/open_compute/opencv/opencv-3.1.0/include/opencv2/core/base.hpp:49:4: error: #error base.hpp header must be compiled as C++ # error base.hpp header must be compiled as C+ 2、Whether the opencv library can be used in the dsp module creation project, can provide the routines that opencv uses on dsp。

Hi @hua liu liu , in ti_components\open_compute\opencv\opencv-3.1.0\docs there are instructions for cross compiling OpenCV (both for BIOS and Linux). Did you followed them? Regards, Yordan

Ticket Name: TDA2EG-17: Can a thread share works to dual core?

Part Number: TDA2EG-17 Hello this article: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/692229/linux-tda2-hao-can-i-use-2-a15 said that "You can think as a single A15 core with CPU clock/frequency doubled" for dual core. But this article: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/862271/tda2hg-why-the-a15-usage-just-50-can-not-up-to-90 said one thread can only run in one core. So it means multi-threads will be separated to dual core automatically, but one thread can't. Is it? Thanks. BR, Jeff

Jeff, One thread can be scheduled only on one CPU. - Keerthy

Ticket Name: TDA2: SRV using GPU

Part Number: TDA2 Hello, I am trying to implement the following scenario on TDA2x EVM: (1) Transfer 4 test images from PC to EVM...I do not know how I can do this yet (2) Run OpenGL-based SRV algorithm on the 4 images...I am assuming OpenGL code can only execute on the TDA2x GPU (3) Transfer output SRV image from EVM to PC...again, not sure how this is to be done Question 1 - Can you point me to some relevant and useful references to implement this scenario? Question 2 - In your opinion, how many CPU cores from the EVM will be required at a minimum to implement this scenario? Question 3 - What is "host CPU" in the context of TDA2x EVM? Does it refer to A15 core 0? Question 4 - How is the GPU programmed on TDA2x? Is it possible to access it through SYS/BIOS? Question 5 - What should be my development environment for this implementation? Windows or Linux? Thank you.

Hi, Please find your answer below (1) Transfer 4 test images from PC to EVM...I do not know how I can do this yet Please use network_rx_tx link to receive or send data over network (2) Run OpenGL-based SRV algorithm on the 4 images...I am assuming OpenGL code can only execute on the TDA2x GPU yes (3) Transfer output SRV image from EVM to PC...again, not sure how this is to be done same as que (1) Question 1 - Can you point me to some relevant and useful references to implement this scenario? Please go through the below usecase vision_sdk\apps\src\hlos\adas\src\usecases\lvds_vip_multi_cam_3d_srv vision_sdk\apps\src\rtos\usecases\network_rx_tx Question 2 - In your opinion, how many CPU cores from the EVM will be required at a minimum to implement this scenario? Please check the usecase jpg file to have idea which all cores are required Question 3 - What is "host CPU" in the context of TDA2x EVM? Does it refer to A15 core 0? Yes, as you have to run vision sdk linux. Question 4 - How is the GPU programmed on TDA2x? Is it possible to access it through SYS/BIOS? Please go through the below module to have some idea about sgxmodule which uses GPU. vision_sdk\apps\src\hlos\modules\sgx3Dsrv Question 5 - What should be my development environment for this implementation? Windows or Linux? On your pc side you can have either of windows or linux as VSDK supports both OS. Regards, Anuj

Ticket Name: TDA2EVM5777: Does the board support fusion of camera data and radar data?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 1,the EVM of the camera data access is through the Vision application Board Fpd_link access and then incoming CPU Board? 2, laser radar is generally ETH interface, can directly through the CPU board two Gbit ETH interface access it? 3, Vision Application board can interface is what to do? Can I use it for ultrasonic radar/millimeter-wave data access? 4, CPU Borad of the 2 Dcan interface can only be used to receive headers? Do you support the output of vehicle control information?

I am not sure I understood all your questions. Kindly help me understand the system: 1. What is the camera interface you are trying to use FPD Link --> VIP? 2. I understand Lidar is via Ethernet. So it is possible to use the TDA2 EVM 3. For Ultra-sonic and Radar what is the interface you are looking at? 4. CAN interface can be used for both input and output . Thanks and Regards, Piyali

1.is the VIP an abbreviation for Video Input Port? 3.For Ultra-sonic and Radar what is the interface you are looking at?------CAN

Yes.. the VIP is Video Input port. The TDA2xx EVM support 2 can interfaces. On the DCAN1 there is an on-board transciever. On the DCAN2 interface you would need to connect an external tranciever. Thanks and Regards, Piyali

Ticket Name: TDA2-17: Color 3D Model in GPU Based Surroundview

Part Number: TDA2-17 Hello, How do I enable a color 3D model using the TDA2xx EVM and the SGX based surroundview? All of the Car models are rendered as Grayscale despite having color texture files. Thanks

Hi Ben, you will need the source release of the surround view and rebuild it with CAR_YUV flag set, please check those threads for details: Regards, Yordan

Ticket Name: Embedded Xvisor for Ti platforms

Other Parts Discussed in Thread: TDA2 Hi All, Is possible to port xvisor on any of TI platform like DM8148 , TDA2x ? If so then what are steps to port ? Regards, Vinayak

Hello Vinayak, Let me move this to the TDAxx forum, they might be able to help you. Regards, Karl

Hi, Experts are notified and will write directly in the thread. Regards, Mariya

Hi Vinayak, In general, Hypervisor is an offering from TI 3rd parties. TI does not have an inhouse solution for Hypervisor. Specifically, there are current working solutions on Xen and COQOS from 3Ps. I haven't seen an XVisor port on TI platform. Nevertheless, since Xvisor supports ARMv8, it should be possible to enable it on J6 / TDA2. However, we wouldn't be able to guide you directly on this. We can put you in touch with our 3Ps. Please contact your FAE for 3P details. Regards, Anand

Ticket Name: TDA2EVM5777: SEL_HDMI_I2C2

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello I'm studying the schematics of TDA2EVM5777 Why RU108 select for HDMI I2C is connected to TDA2 ball E15 I checked the MUXMODE of ball E15 there's no GPIO function in E15 which function do E15 use to select HDMI I2C? thanks~

Hi user3829173, Could you please show me the TDA2EVM5777 schematic that you exploring? According to Vision Application Board Schematic Rev D.pdf - link - www.ti.com/.../sprr225 (TDA2EVM5777), the HDMI SCL/SDA pins of RU108 must be connected to F17 (i2c2_scl) and C25 (i2c2_sda). Regards, Lyuben.

Hi Lyuben The schematics file name is "516582H_VAYU_EVM_13NOV2015_H",but I don't know how to provide you the link. What I confused is not I2C scl & sda,but the select pin of RU108 Pin1 of RU108 is connected to ball E15 of TDA2 but there is no GPIO function in ball E15 , why can E15 control the select pin of RU108? Thank you~

user3829173, If you want to attach files, links, etc. go to the right corner under the replay box and push Insert Code, Attached Files and more Regards, Mariya

I found the answer in the VAYU_CPU_User_Guide_1_320151029 p34 thank you

Ticket Name: TDA2: Issue for building the Test Application Executable through GMAKE

Part Number: TDA2 Hi, I am trying to dump TIDL intermediate output in floating point by enabling "ENABLE_FLOAT_TRACE" in import tool source code. But while building test application encountered an error that is, " The system cannot find the path specified. gmake: *** [C:\PROCESSOR_SDK_VISION_03_05_00_00\ti_components\algorithms\REL.TIDL.01.01.02.00\out\vayu\eve\release\modules\ti_dl\test\.\src\report_utils.obj] Error 1 " TIDL build path: C:\PROCESSOR_SDK_VISION_03_05_00_00\ti_components\algorithms\REL.TIDL.01.01.02.00\modules\ti_dl\test Please find attached console image for your reference. Please guide to remove this error. Regards, Gouri P.

HI, As this is the duplicate the thread for the below thread and so closing this thread, please post follow up questions in that thread. e2e.ti.com/.../2802698 Thanks, Praveen

Ticket Name: TDA2SX: TDA2S VISION SDK 0305 Linux output 720p bt601/bt656 to DS90UB933

Part Number: TDA2SX Hello! expert I need to run Linux from tda2s Vout1 output bt601 SDK:PROCESSOR_SDK_VISION_03_05_00_00, tda2sx--vout1[0:7] vout1_sync vout1_v/hsync--->（BT601）----->DS90UB933----(CML)------>DS90UB934, How to output 720p bt601 to ds90ub933 to ds90ub934 under vision_SDK 0305 Linux? Bt655 output supported? Bt601 output supported? Does ds90ub933 support bt656 and bt601 output?

Hi, Well, i can answer from DSS point of view. DSS definitely supports BT601 output. But it is not supported or no example is available in vision sdk.. Rgds, Brijesh

Ticket Name: TDA2PXEVM: TDA2x,demo code cascade_radar_object_detect will need much more time than the PDF said 36ms, how can I get this tested rerults?

Part Number: TDA2PXEVM I don't know why the demo code tda2xx_cascade_bios_radar-cascade_radar_object_detect will need a much more time than the PDF said. example:Would you like help me test it again?,Please tell me why and what I shuld do to reduce the time cost by DSP .(2) what is the optizimation lever in DSP and where I can change it?

How did you get the time it took? Could you share the log? Please make sure it is release build, not debug build. In release build, the optimization level is already set to -O3.

Ticket Name: CCS/TDA2: Adaboost train

Part Number: TDA2 Tool/software: Code Composer Studio I used github.com/.../acf-jacinto train my data , when I used small amount of data to train,the model no problem.But if the positive image large (more than 10000), the adaboost going to happen stopping eraly. I changed the code, if not used cellSum to deal with the feature channel,the above situation would not happened,but the train weights cannot used in TDA2X object detecion .How can I deal with it or how train large dataset ?

I did not exactly understand the problem, but can you add one line after the line: github.com/.../acfJacintoTrainTest.m Please add the following and then do training: opts.nPos=10000; %num positive to be collected

Thanks for you reply. Add the opts.nPos can't solve the problem. I use opts.pPyramid.pChns.pFastMode.enabled=1; %default: 0 Adaboost early stopping,train log as follows Sampling windows completed=100.0% [elapsed=35.4s / remaining~=0.0s] Sampled 30000 windows from 2048 images. Done sampling windows (time=37s). Extracting features... done (time=14s). Training AdaBoost: nWeak= 32 nFtrs=2560 pos=10150 neg=30000 i= 16 alpha=5.000 err=0.000 loss=9.03e-34 stopping early Done training err=0.0000 fp=0.0000 fn=0.0000 (t=0.3s). Done training stage 0 (time=119s). --------------------------------------------------------------------------- Training stage 1 Sampling windows completed=100.0% [elapsed=123.8s / remaining~=0.0s] Sampled 10000 windows from 10176 images. Done sampling windows (time=126s). Extracting features... done (time=13s). Training AdaBoost: nWeak=128 nFtrs=2560 pos=10150 neg=30000 i= 16 alpha=5.000 err=0.000 loss=1.80e-35 stopping early But if used opts.pPyramid.pChns.pFastMode.enabled=0; %default: 0 Adaboost train OK. On the pFastMode.enabled = 1, The adaboost train easy to appear with early stopping on my training sample. How do I handle this situation?(I check the code in chnsCompute.m,it use cellSum to deal with channel feature,Maye be caused it?)

I am not sure about the reason for this issue as I have not faced this with the datasets that I have tried. Question 1: As I understand, this issue happens only if your positive samples are more than 10000. Can you try to manually select a smaller set of positive samples, so that this issue is not there? Is this an acceptable solution. Question 2: As I understand, you are able to train properly if you set: opts.pPyramid.pChns.pFastMode.enabled=0; Have you tried using the output descriptor (trained with this modification) in TDA2x object detection?

Hi @user5920690 , We haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Ticket Name: TDA2PXEVM: TDA2PXEVM: HI,I think there is a bug in your code \PROCESSOR_SDK_RADAR_03_07_00_00,PLease check it out,Or help me understrand it

Part Number: TDA2PXEVM C:\PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\links_fw\src\rtos\utils_common\src\utils.c,it will make the cpuMhz always 20Mhz. UInt64 Utils_getCurTimeInUsec(void) { static UInt32 cpuMhz = 500U; /* default */ static Bool isInitialized = (Bool)FALSE; Types_Timestamp64 ts64; UInt64 curTs; if(!isInitialized) { /* do this only once */ Types_FreqHz cpuHz; isInitialized = (Bool)TRUE; Timestamp_getFreq(&cpuHz); cpuMhz = cpuHz.lo / (1000U*1000U); /* convert to Mhz */ Vps_printf(" *** UTILS: CPU MHz = %d Mhz ***\n", cpuMhz); } Timestamp_get64(&ts64); curTs = (UInt64) ts64.hi << (UInt64)16U; curTs = (UInt64) curTs << (UInt64)16U; curTs = (UInt64) curTs | (UInt64)ts64.lo; return (curTs/cpuMhz); }

Hi Dan, I will close this thread as it is the same as this one: Experts are looking at the other thread and will reply there soon. Regards, Yordan

Ticket Name: Linux/TDA2: No communication on SATA interface

Part Number: TDA2 Tool/software: Linux Hi everyone, I am using VSDK Linux configuration running on TDA2x SoC and trying to have communication between TDA2x and hard disk drive via SATA interface. However, I have no communication at all. All 4 signals on SATA connectors are on 0 level. During the u-boot execution I noticed messages SCSI: SATA link 0 timeout. AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode and during kernel execution message SATA link down (SStatus 0 SControl 300). Can someone explain me what these messages mean? Also, I noticed that result of command parted -l is giving me only partitions on SD card from which system is run, but there is no SATA device. Should there be some change in configuration of linux kernel so SATA interface is active? Thanks in advance, Sasa

Hi Sasa, If I remember well, most EVMs do not have a power supply for the hdd. Can you check the hdd spins and all necessary power supplies are in place (they should be described on the hdd itself) . Most probably you will need to provide power externally. Thanks, Stan

Hi Stan, we are using custom board with SATA interface on it. Power supply for HDD is external and it is working properly. Best regards, Sasa

Hi Sasa, sorry for the delayed response. I have pinged a Linux expert to help. Regards, Yordan

Hi Sasa We have not been testing SATA connectivity as part of our SDK releases for some time now(not much of customer traction for SATA in automotive) Can you clarify on the SDK version that you are testing and also attach a full kernel bootup log - can review and provide feedback. In general SATA link down message indicates that the link establishment did not work - need to check for potential connectivity issues. As Yprdan asked before, can you confirm if the external HDD is independently powered and you see the HDD spinning up as part of the init sequence?

Hi Sriram, problem was SATA connector which was soldered in wrong way(turned for 180 degrees around). Thank you for your effort. Regards, Sasa

Ticket Name: Compiler: TDA2XX RTOS new usecase can not include network_api.h

Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi, I want to imlement a sever soceket, so create a new usecae by following step 6.1 of vision SDK Build System User Guild and include some h file =============================================================== #include <sys/socket.h> #include <arpa/inet.h> #include <unistd.h> #include <sys/types.h> #include <netdb.h> #include <ifaddrs.h> #include <sys/ioctl.h> #include <net/if.h> =============================================================== but compile printf error message =============================================================== ".\src/rtos/usecases/new_usecase/new_usecase.h", line 13: fatal error: cannot o en source file "sys/socket.h" 1 catastrophic error detected in the compilation of "X:/TDA2/vision_sdk/apps/sr /rtos/common/chains_main_bios_misc.c". Compilation terminated. >> Compilation failure gmake[4]: *** [X:/TDA2/vision_sdk/binaries/apps/tda2xx_evm_bios_all/obj/app_lib /tda2xx-evm/ipu1_0/release/chains_main_bios_misc.oem4] Error 1 gmake[3]: *** [ipu1_0] Error 2 gmake[2]: *** [app_libs] Error 2 gmake[1]: *** [apps_libs] Error 2 gmake: *** [apps] Error 2 =============================================================== it seem the iclude path is not set of makefile? Where is the makefile and what's the parameter name?

Hi, sys/socket.h is Linux header and you should not include it if you create usecase for rtos. Can you check how "./links_fw/src/rtos/utils_common/src/network_api.c" is implemented and which headers it includes and use it in your usecase. Regards, Yordan

Hi Yordan, thanks for your help, but it has error link message after i adding the h file according to "./links_fw/src/rtos/utils_common/src/network_api.h", fuctions of socket can't find link path the error message show below =================================== # undefined first referenced symbol in file --------- ---------------- NDK_accept X:/TDA2/vision_sdk/binaries/apps/tda2xx_evm_bios_all/lib/tda2xx-evm/ ipu1_0/release/app_libs.aem4<new_usecase.oem4> NDK_bind X:/TDA2/vision_sdk/binaries/apps/tda2xx_evm_bios_all/lib/tda2xx-evm/ ipu1_0/release/app_libs.aem4<new_usecase.oem4> NDK_listen X:/TDA2/vision_sdk/binaries/apps/tda2xx_evm_bios_all/lib/tda2xx-evm/ ipu1_0/release/app_libs.aem4<new_usecase.oem4> NDK_recv X:/TDA2/vision_sdk/binaries/apps/tda2xx_evm_bios_all/lib/tda2xx-evm/ ipu1_0/release/app_libs.aem4<new_usecase.oem4> NDK_socket X:/TDA2/vision_sdk/binaries/apps/tda2xx_evm_bios_all/lib/tda2xx-evm/ ipu1_0/release/app_libs.aem4<new_usecase.oem4> error: unresolved symbols remain error: errors encountered during linking; "X:/TDA2/vision_sdk/binaries/apps/tda2xx_evm_bios_all/vision_sdk/bin/tda2xx- evm/vision_sdk_ipu1_0_release.xem4" not built gmake[7]: *** [X:/TDA2/vision_sdk/binaries/apps/tda2xx_evm_bios_all/vision_sdk/b in/tda2xx-evm/vision_sdk_ipu1_0_release.xem4] Error 1 gmake[6]: *** [ipu1_0] Error 2 gmake[5]: *** [apps_ipu1_0] Error 2 gmake[4]: *** [apps] Error 2 gmake[3]: *** [apps] Error 2 gmake[2]: *** [apps_exe] Error 2 gmake[1]: *** [apps] Error 2 gmake: *** [vision_sdk] Error 2 ===================================

Hi, can you set "NDK_PROC_TO_USE=ipu1_0" in vision_sdk\apps\configs\tda2xx_evm_bios_all\cfg.mk and try (you will need to run 'make depend' after modifying cfg.mk). Regards, Yordan

Hi, I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Yordan

Ticket Name: TDA2PXEVM: How to increase size of L2SRAM memory region for DSP core in TDA2P VSDK 3.0.6 relase

Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2, SYSBIOS In VSDK 3.0.6 <<.bss:heapMemL2>> region is assigned to L2SRAM memory segment, In my code I had to increase UTILS_MEM_HEAP_L2_SIZE (which is indirectly assigned to UTILS_MEM_L2RAM_SIZE) [#define UTILS_MEM_L2RAM_SIZE ((224U+32U) * 1024U)] As shown above, we had increase it to 256K(0x40000) from 224K (0x38000). . With this change, I am getting below error i.e. not able to fit memory. "<work_dir>/source/vision/platform/ti/tda2/binaries/apps/harman_proto_A_bios/obj/vision_sdk/harman_tda2px-proto_A/c66xdsp_1/release/vision_sdk_configuro/linker_mod.cmd", line 238: error: program will not fit into available memory. run placement with alignment fails for section ".bss:heapMemL2" size 0x40000 . Available memory ranges: L2SRAM size: 0x38000 unused: 0x38000 max hole: 0x38000 Can you guide me where this region is defined and how to increase the region size.

Hi, It seems that L2SRAM size is defined as 224 KB in SDK. Can you run grep for L2SRAM in Vision SDK and change it to 256 KB. Regards, Rishabh

I have already searched in SDK but couldnt find.

Hi, Can you see PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\links_fw\src\rtos\links_common\system\system_rsc_table_dsp.h. Regards, Rishabh

Yeah but I am seeing only below code, it corresponds to DSP_L2SRAM not L2SRAM. I had increased this also (see below) but it doesnt solve my issue #define DSP_L2SRAM_BASE 0x00800000 #define DSP_L2SRAM_SIZE 0x00040000 { TYPE_DEVMEM, DSP_L2SRAM_BASE, DSP_L2SRAM_BASE, DSP_L2SRAM_SIZE, 0, 0, "DSP_L2SRAM", },

Hi Ritesh, L2SRAM belongs to DSP only. There is on chip memory that can be used by different cores known as OCMC. I checked with our DSP expert. You can have max 256 KB of L2SRAM and 32 KB is reserved for BIOS. Hence you cannot increase the L2SRAM. Regards, Rishabh

Will this be related to the platform configuration in BIOS packages. In BIOS user guide i see that size of L2SRAM etc can be configured from CCS. But unfortunately, Instructions are not so clear in user guide. Do let me know if you have any pointers. I am sure something needs to be done to reconfigure platform files in BIOS folder.

Hi Ritesh, Can you please check my above reply. Regards, Rishabh

Hi Rishabh, We are not increasing L2SRAM size beyond 256K. As mentioned in first msg, just trying to increase it from 224KB to 256KB. Regards

Hi Ritesh, I understand that you are trying to increase L2SRAM size to 256 KB which is max allowed by hardware. In this case you are using SYSBIOS on DSP and SYSBIOS needs 32 KB for it's internal use. Hence application can have max 224 KB of L2SRAM. Same is set and used by Vision SDK. Hope this helps. Regards, Rishabh

No , it is not resolved.

Ritesh, Can you provide details on the need of additional L2SRAM. In case you want to allocate additional buffers you can use DDR. Regards, Rishabh

Ticket Name: Linux/TDA2: Why CPU utilization can't be improved anymore

Part Number: TDA2 Tool/software: Linux i am using SDK_VISION_03_04_00_00 i run my algorithm on a15 i test CPU usage rate by top . can CPU usage rate increase？ and make my algorithm fast. what is the nic 45% idle irq mean? thanks ! shuai

Hi Shuai, The CPU utilization depends on previous links connected to the A-15 link. If the link connected to the A-15 link sends data periodically and the A15 link is able to process the data before the next burst of data, then the CPU load will be limited. If a while loop is run in the link you will notice the A15 load also spike to 100%. Regards Shravan

Hi Shravan i run the program in the main with out link. (sample_app\src\hlos\chains_common\chains_main.c) i do not call usecase. Regards shuai

Hi Shuai, In an idle state the sample-app.out application runs nothing and thus the A15 load is almost 0% due to the application. You need to check what modifications you've made (most likely you're polling on the status of some content) which is causing the increased load. Regards Shravan

Ticket Name: Compiler/TDA2EG-17: TDA2Ex-17 qspi flash

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2 Tool/software: TI C/C++ Compiler Hi，ti expert I am using vision 03.08 to develop on the user board.When I was debugging the qspi flash, I wrote a flash format image file from the linux system to the flash, and then restarted the system, but there was no output from the serial port.The boot sequence of my hardware is sd--->qspi. Why does writing data to qspi flash affect the normal startup of the system?

Hi, Could you please make sure that your SD boot is primary and QSPI is secondary? Also ensure that the images in the SD card are release images that are known to work. QSPI formatting should not impact SD boot. Best Regards, Keerthy

Hi, Yes, I have confirmed, I modified the startup sequence to the following mode: The system can be started normally. The following new problems have occurred: 1、I execute the following command in linux system $ dd if=/dev/urandom of=test.bin bs=64 count=1024 $ dd if=/dev/mtd0 of=12.bin bs=64 count=1024 $ diff test.bin 12.bin The data of the two times is the same, indicating that the data has been successfully written to the spi flash 2、I restart the system, enter the uboot command line, and execute the following command: => fatload mmc 0 0x82000000 MLO 185461 bytes read in 10 ms (17.7 MiB/s) => md 0x82000000 0x10 82000000: 00000040 0000000c 00000000 00000000 @............... 82000010: 00000000 45534843 4e495454 00005347 ....CHSETTINGS.. 82000020: ffffffff ffffffff ffffffff ffffffff ................ 82000030: ffffffff ffffffff ffffffff ffffffff ................ => sf probe 0 SF: Detected gd25s513mdy2g with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf erase 0 0x30000 SF: 196608 bytes @ 0x0 Erased: OK => sf write 0x82000000 0x0 0x30000 device 0 offset 0x0, size 0x30000 SF: 196608 bytes @ 0x0 Written: OK => sf read 0x82000000 0x0 0x30000 device 0 offset 0x0, size 0x30000 SF: 196608 bytes @ 0x0 Read: OK => md 0x82000000 0x10 82000000: 00000000 00000000 00000000 00000000 ................ 82000010: 00000000 00000000 00000000 00000000 ................ 82000020: 00000000 00000000 00000000 00000000 ................ 82000030: 00000000 00000000 00000000 00000000 ................ From the last command, we can know that what is read out is empty.Did not write successfully, but the process of writing shows success How can I find the cause? Thanks！

Hi, The QSPI boot is not supported in vision SDK 3.08 & only SD boot is supported. This is clearly mentioned in the vision SDK Linux user-guide. Thanks Gaviraju

Hi, I now change to the v03.07 sdk package and use qspi4 as the boot device to burn images of MLO, kernel dtb, kernel and other cores. What are the special requirements for the files? What is the location of the image in qspi? How to set the uboot startup command? Thanks！

Hi, Follow the below threads to flash the boot images to QSPI memory. Thanks Gaviraju

Hi, Thanks for your reply.How to set the bootargs parameters of uboot from qspi flash?

Hi, I will check with the U-boot expert & let you know. Thanks Gaviraju

Hi, Please refer the below link: Thanks Gaviraju

Hi, Thanks. But this is not a big reference for me. My board only has qspi flash, so I need to set bootargs, and I need to set which kernel and dtb mirrors are read from. The root file system I use is in ubifs format, so I need to set boot parameters. So can you tell me the startup parameter configuration for booting from qspi flash?

Hi, I could not find references for TDA2. There is one for AM654x: https://elixir.bootlin.com/u-boot/latest/source/include/configs/am65x_evm.h#L120 Similar thing needs to be tried for TDA2. You will have to experiment a bit. There is some older link: https://processors.wiki.ti.com/index.php/UBIFS_Support That gives an over all idea but might not be relevant now. Best Regards, Keerthy

Ticket Name: Compiler/TDA2EVM5777: How can i shift the data of frame from camera sensor?

Part Number: TDA2EVM5777 Tool/software: TI C/C++ Compiler Hi, I'm working with custom board. It is based on TDA2x EVM board. The lvds camera that i'm using sends data in format of YVYU. So, i want to shift 2 bytes of data to make it as YUYV format in ProcessData function of Capture Link. I reffered http://processors.wiki.ti.com/index.php/PDK/PDK_VPS_FVID2_User_Guide to know the data format of YUV422 interleaved and add the below source code in ProcessData function of Capture Link. pFrame->addr[0][0] = pFrame->addr[0][2]; pFrame->addr[1][0] = pFrame->addr[1][2]; However, it doesn't work well. Could you let me know how can i reformat the data of frame? (I mean the way how can i access the data of frame) Thanks and Regards, Yoo

Hi Yoo, What do you mean by shift? For YUV422, driver will always output frame in addr[0][0] location.. Regards, Brijesh

Hi Brijesh, I mean i want to move back 2bytes of data received from camera sensor. For example, If the data from camera is arranged as Y U Y V Y U Y V, i want to remove the first Y U data from the buffer. In this case, i want to access to addr of FVID2_frame. Could you let me know whether this way is possible or acceptable? Regards, Yoo

Hi, I checked from comment in source code and documentation that the data is arranged in single plane when the data format is YUV422 interleaved and progressive. The remain thing what i to do is make the data to start from Y V not Y U. To do this, i added this below line in CaptureLink_drvProcessData function of captureLink_drv.c . ((System_VideoFrameBuffer*)(sysBuf->payload))->bufAddr[0] += 2; I think if i add this line, the data which starts from Y U Y V Y U Y V will be reformated as Y V Y U Y V Y U. Please let me know this way is acceptable. Thanks and Regards, Yoo

Yoo, it cannot be done in VIP. VIP cannot just shift 2 bytes. Instead of VIP doing it, can you ask sensor/decoder to drop, or shift start position? Rgds, Brijesh

Hi Brijesh, Thanks for your help. Could you tell me more about where to modify the sensor to postpone the starting point two bytes behind? Is that part in ti_components/drivers/pdk_01_10_03_07/packages/ti/drv/vps path? Regards, Yoo

Yoo, No, it depends on the sensor that you are using. If sensor supports it, you could shift in sensor. In VIP, you could swap the bytes, but cannot shift. Rgds, Brijesh

Hi Brijesh, If i want to swap U data with V data, how could i access to data? In VIP, there are addr element of FVID2_frame and ((System_VideoFrameBuffer*)(sysBuf->payload))->bufAddr[0]. Which one that i need to use? Also, i really appreciate if you guide me to swap those data efficiently. Thanks again. Regards, Yoo

Hi Yoo, FVID2_Frame address is what driver uses.. If you set the output frame format to YVYU from YUYV, then chroma is swapped. Regards, Brijesh

Hi Brijesh, I wonder how the UV channel data is arranged in second plane of frame when the data format is YUV420_SP. I tried to set some value of output frame as 0 and checked that values were changed. At first, i thought it organized as order of U V U V U V. However, when i swapped the value of U with value of V, the output was not changed. The below line is what i used to set some value of frame as 0. memset(((System_VideoFrameBuffer*)(sysBuf->payload))->bufAddr[1], 0, sizeof(unsigned char) * 115200); And this is what i used to swap the U data with V data. for (i = 0; i < 102400; i+=2) { unsigned char tmp = (unsigned char)(*((unsigned char*)pFrame->addr[0][1] + i)); *((unsigned char*)pFrame->addr[0][1] + i) = (unsigned char)(*((unsigned char*)pFrame->addr[0][1] + i + 1)); *((unsigned char*)pFrame->addr[0][1] + i + 1) = tmp; } I think the data is not arranged as i assumed. Could you please let me know the order of U/V data in second plane? Thanks and Regards, Yoo

Hi Yoo, Yes, for YUV420 output, chroma plane would have U followed by V and so on. When you say, it is not working, what does it mean? You don't see bytes swapped in memory? Is your buffer cached/ In that case, you would require to invalidate cache before updating buffer and then write back cache after updating.

Hi Brijesh, Yes, i didn't see any bytes swapped. The frames that are shown in display were all same with before i apply swap the data. I applied swap in capture link of vip_capture directory. What i can't understand, if the cause of my problem is not invalidating/updating cache, why memset function works well... Anyway, I'm going to try to use cache function and reply in this thread. Thanks and Regards, Yoo

Hi Byeongheon Yoo, Any further update on this question? Is it resolved? Rgds, Brijesh

Ticket Name: Linux/TDA2: Measuring load

Part Number: TDA2 Tool/software: Linux Hi Expert, I'm running Linux Vision SDK v03.02.00(4.4.84) on TDA2Ex. run usecase: "chains_lvdsVipMultiCam_Sgx3Dsrv" Can get the load of DSP1 and M4-2 as the picture below. But the value of A15 is fixed, How to modify? grpxSrcLink_svStandalone_layout.c Int32 GrpxSrcLink_displaySurroundViewStandaloneStats(GrpxSrcLink_Obj *pObj) Delete line 449, 450, The value of A15 is 0. Could you please give some suggestion here? Thanks in advance.

Hi, Currently there isn't support in the VSDK-Linux framework to measure the B/W of A15. To measure the load of A15, Linux itself provides several tools such as top, htop, vmstat etc. It is feasible to monitor the CPU load while the application is running by launching a separate session (using telnet, ssh etc.) and running these commands. Regards Shravan

HI, It is expected to use the "load average" in the "top" command as the A15 load monitoring. But don't know how to convert "load average" to percentage(%). How does the value in the top command translate to the load percentage? Figure1，red line → load average: 0.43 Figure2，red line → load average: 14.82 Figure3，red line → load average: 157.15 Figure1，Before executing app.out. Figure2，After executing app.out Figure3，Execute many bc commands Thanks in advance.

Hi, You may find the script provided in this link useful. github.com/.../How-Linux-CPU-Usage-Time-and-Percentage-is-calculated Regards Shravan

Hi, Use the script inside the link, The result is the same as the "mpuload" command. 100% directly after opening app.out, should this be "usage rate"? I need to know if there is a load limit that has been reached? How much can be used? Figure1，executing app.out. Figure2，exit app.out Thanks in advance.

Hi, This means the load on the CPU is 100%. When you run apps.out, there is some code running on A15, which makes the load 100%. Regards Shravan

Hi, As shown below, the load is already 100% when app.out is executed, but the bc command can still be executed. It will only reduce the CPU usage of the app.out(81% → 3.8%) and bc commands. Why is the load already 100% still able to execute other commands? How do evaluate the performance of A15 on app.out? Thanks in advance.

Hi, I'm not sure what your exact use-case is, however, if you take the VSDK release as is, and run 'apps.out' the A15 load is expected to be 2-3%. 'bc' commands are still able to run, despite 'apps.out' being 100% load, because the scheduler in Linux, schedules processes to run on the core, using various factors. You can find more information here. To determine the load on A15, please use the top command, and the value (100-idle) (present at the head of the top command), will give you the CPU load. Regards Shravan

Hi, test bc command: # Echo "scale=5000; 4*a(1)" | bc -l -q As shown in Figure 1, A15 does not execute the bc command. As shown in Figure 2 below, A15 executes a bc command. As shown in Figure 3 below, A15 executes multiple bc commands. How do know how many bc commands can execute on A15? Thanks in advance.

Hi, Theoretically it should be possible to run as many tasks as possible, however beyond a certain number of processes more time is spend switching process than executing it. I think the issue pertaining to measuring load on A15 has been addressed. For any further queries, please create a new thread. Regards Shravan

Ticket Name: TDA3MV: PMHAL_PRCM_CLK_VID_PIX_CLK && dss pixelclocks

Part Number: TDA3MV Other Parts Discussed in Thread: TDA2 Hi, Our customized tda3mv pcba had a display jitter problem, i already read sprac62 document, and also https://e2e.ti.com/support/processors/f/791/p/818232/3031781?tisearch=e2e-sitesearch&keymatch=vout1_clk%20jitter#3031781 i saw fae said "VIDEO1_DCLK is about 28MHz with signal integrity like #1. The trigger delay shows that this clock has period jitter but that is not unexpected. ". i found three method may could solve display jitter, if clock>70M 1. add clock cleaner 2. use DPLL HDMI to VP1, not DPLL_VIDEO (only for tda2) 3.. set N,M,dive... , the trm show note below NOTE: It is preferred to minimize the value for N parameter (it minimizes lock time and jitter). Then M should be chosen to provide correct frequency (with lowest delta as possible). is method 3 could sovle my problem on tda3x? i read tda3x trm document, see "The VP1_PCLK clock for the VP1 output is provided directly from the DISPC_CLK1 input clock ", and TDA3xx_ClockRate_SetConfig_Generator.xlsm document, see PMHAL_PRCM_CLK_VID_PIX_CLK, Frequency=74000000, PMHAL_PRCM_DPLL_EVE_VID_DSP, M=222, N=4, PMHAL_PRCM_DPLL_POST_DIV_M2, 3, In chains_common.c, How the frequency of display pixelclocks is generated? Is related to PMHAL_PRCM_CLK_VID_PIX_CLK, M, N values ? or any others advices to solve this problem? new edit, this change looks like can let N to be more less, i will try this SJay

Hi SJay, Typically these value are calculated internally by PM driver, I think there is a flag in the API, which calculates M & N values, This flag allows to calculate lower M & N values or higher M & N values.. Can you please try changing this flag? There should API like SetClockRate in display controller link. Please check this api and change the flag. Rgds, Brijesh

Hi Brijesh , i know you mean, but i had checked the function DisplayCtrlLink_configureVideoPllAndClkSrcForLCD() in my usecase will be called in chains_common setting Rgds, SJay

ok, can you change code in DisplayCtrlLink_configureVideoPllAndClkSrcForLCD and see if it works? Rgds, Brijesh

Hi Brijesh, origin max mn m=1188 n=128 m2=5 change min mn m=297 n=8 m2=20 Finally, this change is work. The display out not jitter anymore. SJay

Ticket Name: TDA2EXEVM: channel switching in single channel display.

Part Number: TDA2EXEVM Hello there, We are having an use-case for 6-channel display. Capture(6-channels) -> VPE -> Merge -> Display. For switching between the channels we are using the below API, Int32 System_linkControl(UInt32 linkId, UInt32 cmd, Void *pPrm, UInt32 prmSize, Bool waitAck) If we want to switch the API, the parameter "params.activeChId" from structure typedef struct { UInt32 activeChId; /**< Active chID from which frames should be displayed */ } DisplayLink_SwitchChannelParams; are assigned the value to change the channels. But every-time channel 0 is displayed first. even though we have changed the activeChId to some other value not 0. For our requirement we need to display data based on the activeChId value. Please suggest the solution. Thanks & regards Balaji T

Hi, Can you confirm the function "DisplayLink_drvSwitchCh" is called or not after sending the command using the API "System_linkControl"? Thanks Gaviraju

Hi Gaviraju, In file ./links_fw/src/rtos/links_ipu/display/displayLink_drv.c API DisplayLink_drvSwitchCh(pObj, &switchParams) i have enabled the print. While giving switch command to System_linkControl , that print is not getting printed in the debug screen, Regards Balaji T

Hi, It seems you are not sending a command properly(Make sure link ID argument is correct or not) in the System_linkControl function call. refer "chains_lvdsVipMultiCam_Display_SwitchDisplayChannel" function here they are trying to switch the input channel to display. Thanks Gaviraju

Ticket Name: TDA2EVM5777: How to burn BIOS(sbl and appimage) into qspi ?

Part Number: TDA2EVM5777 Hi, I want to boot bios from qspi, I reference the manual VisionSDK_UserGuide_TDA2xx.pdf - 3.7Load using QSPI.But I don't have JTAG,I cannot use ccs to download the binary. I heard there are also ways using the USB boot mode to load and execute an image from DDR3 to then run a secondary boot loader that can flash QSPI-NOR or eMMC flash. So could you indicate which documents mention this? Regards

Hi, You can use Mflash to flash via UART. Please see PROCESSOR_SDK_VISION_03_07_00_00\ti_components\drivers\pdk_01_10_03_07\packages\ti\boot\sbl_auto\docs\AppNote_mflash.pdf Regards, Rishabh

Hi,Rishabh I follow the guide, I compile the sbl_mflash_tda2px-evm and copy AppImage_BE and MLO into mflash directory. And I enabled UART3 by two simple registers modification on the evm. I use below command try to download the AppImage_BE and MLO. sudo ./mflash.out -M sbl_mflash_tda2px-evm -P 0 -F AppImage_BE 0x80000 -F MLO 0x00 -C But it crash in Opening port for sbl_mflash. Here's the complete download log lyp@lyp-desktop:~/hd2/tda2/sdk_3.07/ti_components/drivers/pdk_01_10_03_07/packages/ti/boot/sbl_auto/tools/mflash$ sudo ./mflash.out -M sbl_mflash_tda2px-evm -P 0 -F AppImage_BE 0x80000 -F MLO 0x00 -C
Usage: mflash -M <sbl_mflash> -P <Port Number> -C [optional: to clean the QSPI Flash]-F <fileName> <offset> -F <fileName> <offset> ... [PC] sbl_mflash sbl_mflash_tda2px-evm
[PC] File	0	AppImage_BE
[PC] Offset	0	0x80000
[PC] File	1	MLO
[PC] Offset	1	0x00
[PC] com /dev/ttyUSB0
[PC] ##########Starting USB/UART Flasing Utility##############
[PC] Put UART Boot Mode, make fresh UART connection & restart
[PC] Press Enter when done...
[PC] Opening serial port successful.
[RBL]4	[RBL]1	[RBL]5	[RBL]1	[RBL]56	[RBL]41	[RBL]7	[RBL]3	[RBL]13	[RBL]4	[RBL]1	[RBL]5	[RBL]1	[RBL]56	[RBL]41	[RBL]7	[RBL]3	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]14	[RBL]21	[RBL]1	[RBL]0	[RBL]0	[RBL]4	[RBL]1	[RBL]5	[RBL]1	[RBL]56	[RBL]41[RBL]4	[RBL]1	[RBL]5	[RBL]1	[RBL]56	[RBL]41	[RBL]7	[RBL]3	[RBL]13	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]14	[RBL]21[RBL]1	[RBL]0	[RBL]4	[RBL]1	[RBL]5	[RBL]1	[RBL]56	[RBL]4	[RBL]1	[RBL]5	[RBL]1	[RBL]56	[RBL]41	[RBL]7	[RBL]3	[RBL]13[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]14	
[PC] Requesting the ASIC ID
[RBL]4	[RBL]1	[RBL]5	[RBL]1	[RBL]56	[RBL]41	[RBL]7	[RBL]3	[RBL]13	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]14	[RBL]21	[RBL]1	[RBL]4	[RBL]1	[RBL]4	[RBL]1	[RBL]5	[RBL]1	[RBL]56	[RBL]41	[RBL]7	[RBL]3	[RBL]13	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]14	[RBL]4	[RBL]1	[RBL]4	[RBL]1	[RBL]5	[RBL]1	[RBL]56	[RBL]41	[RBL]7	[RBL]3	[RBL]13	[RBL]2	[RBL]4	[RBL]1	[RBL]5	[RBL]1	[RBL]56	[RBL]41	[RBL]7	[RBL]3	[RBL]13	[RBL]14	[RBL]21	[RBL]1	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]0	[RBL]4	[RBL]1	
[PC] Requesting PERI_REQ mode
[PC] Sending SBL_MFLASH filesize.
[PC] Size of sbl_mflash = 51468
[PC] Sending SBL_MFLASH... Please wait
[PC] File Size  = 51468
[PC] #
[PC] Transfer Complete. Time = 4.000
[PC] Opening port for sbl_mflash.
 I think there are something wrong with my operation....Do you have some idea? Regards

Hi, Your original question mentions TDA2xx whereas as per your reply you are trying to use TDA2Px. Can you confirm what is the exact SoC you are using. Regards, Rishabh

Rishabh, It's TDA2PX. Regards

Hi, Can you confirm if you have followed the step "Put UART Boot Mode, make fresh UART connection & restart". Regards, Rishabh

Hi Rishabh, Yes,I sure I make this. I have to give up this way. I try to boot up in Linux and flash image into /dev/mtd0 and it success.But I meet another problem. I will ask a new question in new thread. Thanks

Ticket Name: RTOS/TDA2: ndk_2_24_00_11 jumbo packet support

Part Number: TDA2 Tool/software: TI-RTOS Hello, One of customer is trying to enable jumbo packet support on their custom board. They referred to the NDK wiki (http://processors.wiki.ti.com/index.php/Enabling_Jumbo_Packet_Support_for_C6678#NDK_modifications) and also made NSP changes. They see application crashing with this changes. Jumbo is validated on TDA2xx EVM by us but with ndk_2_24_02_31. Customer is using ndk_2_24_00_11 Just wondering if jumbo is supported on this version. Thanks.

Upon further debug, the application fails in the PTP stack which uses NDK Raw socket APIs. Any dependency of raw sockets on jumbo?

Hi Prasad, Someone will look into this. Todd

Hello Todd, Just to update, we have jumbo packet working on customer board. But it fails once PTP stack is enabled.

Prasad, Jumbo packet support should have been working in NDK 2.24.00.11, but we don't validate that. There were many bug fixes between that release and NDK 2.42.02.31. Could be that one of those fixed jumbo packets, but nothing obvious stands out. Jumbo packets should also work with RAW sockets. I guess you already figured that out. Not familiar with PTP stack. Is that Precision Time Protocol? Is customer implementing that on top of NDK RAW sockets with jumbo packets enabled? We don't have any experience with that setup. I don't have much to offer. Let us know more details on the failure, and hopefully we can advise. ~Ramsey

Hello Ramsey, Do you have the list of releases and bug fixes? Can you please point me to that? Yes, PTP is precision time protocol stack, the customer has implemented it on the top on NDK RAW sockets. It works normally without Jumbo but fails when jumbo enabled. Customer is looking if any issue in their stack. Meanwhile I wanted to check if any known issues with Jumbo and RAW sockets combination.

Hello Ramsey, New information from customer - In PTP, there is a Raw Ethernet communication using the NDK's api 'recvnc()' which always returns -1. res=recvnc(sockfd, (void **)&ncbuf, MSG_DONTWAIT, &ncbufh); As the raw ethernet receive fails, it tries to re-initialise every time and hence it gets stuck there. Note: Without jumbo frames enabled, this functionality was working normally. Does this NDK package support jumbo frames (for raw ethernet mode) ?

Prasad, Our expectation is that NDK RAW sockets should work with jumbo Ethernet frames. What is the error code when recvnc() returns -1? Please use the fdError() function (serrno.h) to retrieve the error code. Thanks, ~Ramsey

Ramsey, Error code returned from fdError() is '9'. I guess this indicates 'Bad file descriptor' ? Regards, Pradyumna

Pradyumna, I've looked at the code, but I don't see an obvious reason that recvnc() would set error to NDK_EBADF. As this error always happens on the first call to recvnc(), would it be possible to run in the debugger? This would allow you to step through the code and see why an error is being raised. Please note this function is an inline, the actual function name is NDK_recvnc() in the file /ti/ndk/stack/fdt/socket.c. If this is not possible, you will need to instrument the code by adding calls to DbgPrintf(). Then you will need to rebuild the NDK libraries. This post might help with the details. ~Ramsey

Did this get resolved?

Hi Ramsey, The issue with recvnc() is resolved. Ethernet frame data buffer was not long enough for incoming packets and the socket was being overwritten with garbage values. Thanks for the support. Regards, Pradyumna

Ticket Name: TDA2: PreprocType Role

Part Number: TDA2 Hello Sir, While Importing and inferring model, I came across the term PreProcType. I have explored its code from tidl_image_preproc.c As per my understanding, we have values 0-5 in which, PreProcType=0 is mentioned in comments for Caffe_jacinto models and PreProcType=1 for Caffe, other is not known. Then I looked out all the models which had 0,1,2,3 PreProcType's and came into conclusions i.e. , we have assigned PreProcType according to models and somewhere according to the Image resolution. (**kindly comment on my conclusion). I have some Queries as follow: Q1) When did we require PreProcType, while Importing or at Inference as both Import_config and Infer_config file has the information of PreProcType. Q2) I tried to split the network in 4 Sub-Networks(10 layers each) for JDetNet, I inferred the first subnetwork with PreProcType and rest three subnetworks were commented for the PreProcType, So is this the correct way or I have to not comment the PreProcType for all subnetworks. Q3) All the models except Cifar, I observed PreProcType in Inference and Import Config file were the same but Why Cifar Import_config file has PreProcType=3 and at inference_config PreProcType=0..? One more query regarding the availability of deploy.prototxt file. This path PROCESSOR_SDK_VISION_03_05_00_00\ti_components\algorithms\REL.TIDL.01.01.02.00\modules\ti_dl\test\testvecs\config\caffe_jacinto_models\trained\object_detection\voc0712\JDetNet\ssd768x320_ds_PSP_dsFac_32_hdDS8_0\sparse doesnt have Deploy.prototxt file available with .caffemodel to Import the JDetNet model. So I have used deploy.prototxt available in the below folder PROCESSOR_SDK_VISION_03_05_00_00\ti_components\algorithms\REL.TIDL.01.01.02.00\modules\ti_dl\test\testvecs\config\caffe_jacinto_models\trained\object_detection\voc0712\JDetNet\ssd768x320_ds_PSP_dsFac_32_hdDS8_0\test_quantize Q) Only this file we have to use for Importing or do we have to use some other deploy.prototxt file? If present kindly share the path.(In all models of caffe_jacinto and Caffe, I have found .caffemodel and Deploy.prototxt file were present under same folder i.e., Sparse) Kindly do the needful. Thanks and Regards Vyom mishra

1.PreProcType shall be used if "rawImage = 0" in both import and infer config 2.The first part can take input as either raw or jpeg. if it is jpeg then PreProcType shall be set based on the pre-processing used in training. for rest of the input shall be raw so,PreProcType is ignored 3.In infer config rawImage = 1 So PreProcType is ignored 4.You can find more models here github.com/.../trained

Ticket Name: RTOS/TDA2: "errors encountered during linking" When I call a filter in framecopy algorithm plugin

Part Number: TDA2 Tool/software: TI-RTOS I try to add a filter, "EVELIB_firFilter2D", in framecopy algorithm plugin in TDA2PX/vision_sdk/apps/src/rtos/alg_plugins/framecopy/frameCopyAlgoEve.c. I write a test code. But in the building process, I meet link error as below. If anybody can help? Thanks a lot! "/home/derek/TDA2PX/vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/eve2/linker_cmd_eve2_debug.cmd", line 13: warning: no matching section warning: creating output section ".edmaUtilsMem" without a SECTIONS specification error: no valid memory range(null) available for placement of ".edmaUtilsMem" error: program will not fit into available memory. run placement with alignment fails for section ".edmaUtilsMem" size 0x2e4 page 0 "/home/derek/TDA2PX/vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/eve1/linker_cmd_eve1_debug.cmd", line 7: warning: no matching section "/home/derek/TDA2PX/vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/eve1/linker_cmd_eve1_debug.cmd", line 8: warning: no matching section "/home/derek/TDA2PX/vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/eve1/linker_cmd_eve1_debug.cmd", line 13: warning: no matching section

Hi, Can you share the changes which you have done for that link. Regards, Anuj

Hi Anuj, Thanks for your reply. The following is my change in file vision_sdk/apps/src/rtos/alg_plugins/framecopy/frameCopyAlgoEve.c function Alg_FrameCopyProcess. char coeff[9] = {28, 28, 28, 28, 29, 28, 28, 28, 28}; uint8_t rndShift = 8; EVELIB_firFilter2D((UInt8 *)inputPtr, (wordWidth<<2), height, (wordWidth<<2), height, 1, (UInt8 *)outputPtr, (wordWidth<<2), height, (wordWidth<<2), height, 1, coeff, 3, 3, 1, 1, rndShift );

If there is any configure file or .cmd file need to change?

Hi , Please add a section like below Program.sectMap[".edmaUtilsMem"] = "EVE1_DATA_MEM"; in \vision_sdk\links_fw\src\rtos\bios_app_common\tda2xx\eve1\Eve1.cfg Do the same for all other EVE cores also. Regards, Anuj

Hi Anuj, It works. Thanks a lot! :)

Ticket Name: TDA2EVM5777: How to use I2C high speed mode?

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi expert, We have a requirement to use I2C5 to communicate between TDA2 SOC and MCU. I checked the Source code and found the I2C API path. Would this API support high speed mode and is easy to apply on the vision sdk? If it is not applicable, is there any other sample code? C:\PROCESSOR_SDK_VISION_03_05_00_00\ti_components\drivers\pdk_01_10_01_06\packages\ti\drv\stw_lld\i2clld\src\lld_hsi2c.c

Hi, The supported i2c bus speed is 100Khz and 400Khz for this I2C driver. It doesn't support HS mode. We don't have example i2c driver for HS mode. However, the I2C hardware on TDA2 is capable of running HS mode. Regards, Stanley

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello I'm studying the TDA2 EVM circuit , and I want to build up a ADAS by 1 camera input via mipi interface but it looks no mipi interface in TDA2, just only parallel interface is there mipi interface in TDA2 video input? which document can I refer to the information I need? thank you

No, TDA2 does not support MIPI interface. Rgds, Brijesh

So the video input of TDA2 support just only parallel interface? thank you~

Yes, no support for serial interface at least for Video. only parallel interface. Rgds, Brijesh

Got it ! Thank you very much~

Ticket Name: TDA2EXEVM: TIDL OD use+case generate wrong result with user model

Part Number: TDA2EXEVM Hi TIDL experts, Thank you for your great support until now. I have a SSD-based model and i try to put it on the OD use-case. And it create unexpected result, a lot of random small boxes on the screen. I check the import layer level and also the tidl tb results , and all of them are the similar with caffe and proper. So it seems that the mismatch result is generated by the OD-usecase . Is there any suggestion or possible solution about this? The original question is this thread: e2e.ti.com/support/processors/f/791/t/729679#pi239031349=2 Thank you. Best Regards, Eric Lai

Hi Eric Lai, There is a new vision SDK release version 03.05.00.00 available now, can you please check with this new release and report here. Thanks, Praveen

Hi Praveen, Okay, I will give it a try. Thank you so much. Best Regards, Eric Lai

Hi Praveen, I tried the new version SDK. And like the previous version, the result is matching between caffe , import ,and also tidl testbench. On the use-case, finally the result is proper , the unexpected small box are gone. Thank you. But there is still some different between the video from caffe and use-case. Especially for the small object, the confidence is lower. I set the quanthistory to zero, the result is the same. Is there any possible reason about this? Best Regards, Eric Lai

Hi Eric Lai, Can you experiment with below quant history parameters and check. createParams.quantHistoryParam1 = 5; // increase in steps of +5 createParams.quantHistoryParam2 = 5; // increase in steps of +5 createParams.quantMargin = 0; // increase in steps of +5 Thanks, Praveen

Hi Praveen, I tried the parameters but the results are similar. It seems that it's not the reason of this issue? Any suggestion about this? Best Regards, Eric Lai

Hi Praveen, Any update? On the use-case, the result is different. Btw, the number of layers of my model is almost 120. Maybe this is the reason why it cause this issue? Best Regards, Eric Lai

Hi Eric Lai, How big is the difference in behaviour on the use-case verses tidl test bench. Can you please share some screen shots of the output so that I will get it reviewed with VSDK expert for quick look and suggestions. Thanks, Praveen

Hi Praveen, Caffe , import and TIDL testbench are matching. And here is the video result on caffe and OD use-case. The confidence of the some object are lower . You can see some boxes are blinking . I have no idea about this issue. Thank you. Best Regards, Eric Lai TDA2_result.rar caffe_result.rar

Hi Eric Lai, Can you decrease the confidence threshold and check? Thanks, Praveen

Hi Praveen, The original threshold of caffe and usecase are the same. ( =0.3) And I follow your instruction to decrease the threshold. ( =0.1) And the result seems better but still not proper. The boxes are still blinking not like the original caffe. Best Regards, Eric Lai

Ticket Name: Linux/TDA2: Difference between vip_Single_Cam_objectdetection2 and tidl_OD

Part Number: TDA2 Tool/software: Linux Hi , I have few questions to get clarified on 1) I like to know what is difference between vip_Single_Cam_objectdetection2 and tidl_OD . I believe both are doing the same TSR+PD+VD ? On what basis it is differentiated 2) Vip_single_cam_object detection2 requires any bin file? (like NET.prm which we use in tild_OD). If it requires I like to know where it is used in the usecase. if not how it is detecting the vehicles 3) Is it possible to port vip_Single_Cam_objectdetection2 into linux platform? is there any dependencies on this

1. vip_Single_Cam_objectdetection2 Uses HOG + Adaboost for Object detction , tidl_OD uses SSD for object detction. 2. No it Vip_single_cam_object detection2 does not need net NET.prm 3. Yes you can. Refer the vip_Single_Cam_objectdetection2 use case doc for modules and used by this use case

Hi Kumar , thank you for clarifying it , I like to know whether it is possible to port tidl_OD in linux . We feel that tidl_OD will be better than objectdetection2 . So can you kindly suggest that porting tidl_OD is possible or not in linux . Regards, Surendar

Hi, Porting of tidl_OD usecase on linux is not been integrated or tested. If you want to do then you can start and let me know if you face any issue. Regards, Anuj

Hi, There is no update on this thread since a long time. Is there issue resolved? Regards, Anuj

Hi , I am working on it , if there is any issues Ill update on this same thread Regards , Surendar

Hi Anuj , I have followed following steps to run tidl_OD usecase on linux platform 1) Copied tidl_OD usecase and paste it in under adas/src/usecase folder 2) Copied object detection and tidl algplugins and paste it in under adas/src/alg_plugins 3) for the above folders I have modified the makefile respectively 4) In apps/src/hlos/adas/include/chains.h added "Chains_tidlOD" 5) in vision_sdk/apps/src/hlos/MAKEFILE_adas.mk added the path for tidl usecase like below $(MAKE) -fMAKEFILE.MK -C$($(MAKEAPPNAME)_PATH)/src/hlos/adas/src/usecases/tidl_OD MODNAME=$(MAKEAPPNAME) CORE=a15_0 $(TARGET) 6) in vsdk/apps/configs/tda2xx_evm_linux_all/uc_cfg.mk added tidl_OD folder usecase as "yes" 7) in vsdk/apps/configs/cfg.mk added tidl_OD usecae under "LINUX_TDA2XX_UC_LIST" when i compiled using "make -s -j depend && make -s -j " I am getting the following error : PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/apps/src/include/chains.h:125:55: fatal error: ti/drv/vps/include/platforms/bsp_platform.h: No such file or directory kindly help me in resolving this issue Regards, Surendar

Hi , I resolved that issue by changing the path of header files from <src/include/chains_common.h> to <apps/src/hlos/common/chains_common.h> . Now I got the following error PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/apps/src/include/chains_common_tidl.h:92:22: fatal error: itidl_ti.h: No such file or directory This has to do the with path , I have set the environment for tidl in /home/vkchlt0206/PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/build/hlos/makerules/linux/env.mk as same below tidl_INCLUDE= $(tidl_PATH)/modules/ti_dl/inc export tidl_INCLUDE Still I am getting the same error . Kindly advise did I miss any thing Regards , Surendar

Hi, Any updates on this

Hi, Have you added the tidl path as include in includes_a15.mk file. You have to add as -I option. Please take rtos reference. Regards, Anuj

Hi Anuj , can you tell me rtos reference file so that i could add tidl path as similar to that in includes_A15 file. I couldn't find the path Regards , Surendar

Hi Anuj , Any updates on this Regards, Surendar

Hi Anuj , Any updates on this

Hi, Sorry for the delayed reply. Please add below line in includes_a15.mk as done in rules_m4.mk INCLUDES += -I$(tidl_INCLUDE) Regards, Anuj

Hi Anuj, I have added the line you mentioned in includes_a15.mk . I have clean compiled and still I am getting the same error as below /PROCESSOR_SDK_VISION_03_04_00_00/vision_sdk/apps/src/include/chains_common_tidl.h:92:22: fatal error: itidl_ti.h: No such file or directory I have also tried adding the line in the UC MAKEFILE.MK and I am getiing the same error . Kindly advise me where I went wrong Regards , Surendar.

Hi, Try to build without -s option and check while building chains_tidlOD.c what all package are getting include. Check how the path for those packages has been provided in the makerules and add similarly for the tidl. Regards, Anuj

Hi, Are you able to resolve the issue. Regards, Anuj

Hi Anuj , I am not currently working on this . So we can close this issue as of now

Ticket Name: CCS/TDA2: biasDmaAutoIncrement_DMA_in_Init Execution time anomaly

Part Number: TDA2 Tool/software: Code Composer Studio In my project, there were 5 places that used EDMA. I found an anomaly in one place. I find that the EDMA configuration function in this place has a lot of time to use 1MS, and I think it should be a very small time, where the function of the configuration function is not included in the functions that actually carry the data. static int32_t biasDmaAutoIncrement_conv3x3short_ti_multi_DMA_in_Init( uint8_t *dmaAutoContextInOut, short *inBufExt, short *inBufInt[2], int16_t in_width, int16_t in_height, int16_t width, int16_t height, int channels) { int32_t status = 1; EDMA_UTILS_autoIncrement_initParam_v2 initParamV2; initParamV2.pingPongOffset[0] = (uint32_t)inBufInt[1] - (uint32_t)inBufInt[0]; initParamV2.pingPongOffset[1] = initParamV2.pingPongOffset[0]; initParamV2.initParams.numInTransfers = 1; initParamV2.initParams.numOutTransfers = 0; //parameters for ping transfer from external to internal memory and vice versa initParamV2.initParams.transferType = EDMA_UTILS_TRANSFER_IN; //parameters for out transfer - ping initParamV2.initParams.transferProp[0].roiWidth = width * 2; initParamV2.initParams.transferProp[0].roiHeight = height * channels; initParamV2.initParams.transferProp[0].roiOffset = 0; initParamV2.initParams.transferProp[0].blkWidth = width * 2; initParamV2.initParams.transferProp[0].blkHeight = height; initParamV2.initParams.transferProp[0].blkOffset = 0; initParamV2.initParams.transferProp[0].extBlkIncrementX = 0; initParamV2.initParams.transferProp[0].extBlkIncrementY = height; initParamV2.initParams.transferProp[0].intBlkIncrementX = 0; initParamV2.initParams.transferProp[0].intBlkIncrementY = 0; initParamV2.initParams.transferProp[0].extMemPtrStride = width * 2; initParamV2.initParams.transferProp[0].interMemPtrStride = in_width * 2; initParamV2.initParams.transferProp[0].extMemPtr = (uint8_t *)(inBufExt); initParamV2.initParams.transferProp[0].interMemPtr = (uint8_t *)(inBufInt[0]); initParamV2.initParams.transferProp[0].dmaQueNo = 1; //configure EDMA for ping set both Ext -> Int and Int -> Ext EDMA_UTILS_autoIncrement_init_v2(dmaAutoContextInOut,&initParamV2); status = EDMA_UTILS_autoIncrement_configure_v2(dmaAutoContextInOut,EDMA_UTILS_TRANSFER_IN); return status; } unsigned long long WH_time[10]; double WH_cost[10]; TSCH = 0; TSCL = 0; WH_time[0] = _itoll(TSCH,TSCL); int status = biasDmaAutoIncrement_conv3x3short_ti_multi_DMA_in_Init( dmaAutoContextInOut, indata, pInBufInt, in_width, in_height, width, height, channels); WH_time[1] = _itoll(TSCH,TSCL); WH_cost[0] = (double)(WH_time[1] - WH_time[0]) / 1000000.0; printf("biasDmaAutoIncrement_conv3x3short_ti_multi_DMA_in_Init= %f ms\n",WH_cost[0]);

Hi Shuai, If I understood your question correctly, you mean biasDmaAutoIncrement_conv3x3short_ti_multi_DMA_in_Init function is taking 1ms of time. Looking at your code you are using _itoll(TSCH,TSCL) instruction to read the counters. These counters only gives you the cycles consumed and doesnt give you time directly. To measure the time you need to divide this number by the frequency at which the DSP core is running. Regards, Anshu

Hi Shuai, I am hoping that this resolved your issue and hence I am closing this thread. You can revisit it if you have more question. Regards, Anshu

HI Anshu C66 of TDA2X frequency is 500MHZ you mean actual time is like this ??? WH_time[1] = _itoll(TSCH,TSCL); WH_cost[0] = (double)(WH_time[1] - WH_time[0])*1000 / (1000000.0*500); printf("biasDmaAutoIncrement_conv3x3short_ti_multi_DMA_in_Init= %f ms\n",WH_cost[0]); shuai

HI Anshu so biasDmaAutoIncrement_conv3x3short_ti_multi_DMA_in_Init function is taking 2ms of time , i think is too big ，i think it should be 0.01MS shuai

Hi Shuai, Can you profile inside of the function to figure out which part is taking more time? Regards, Anshu

Hi Shuai, Were you able to make progress in this issue? If yes kindly close this thread. Regards, Anshu

Ticket Name: RTOS/TDA2: What HDMI output seem like has crop when TDA2 receive 12 bits data from DVP of image sensor.

Part Number: TDA2 Tool/software: TI-RTOS Hi Sir, We need receive 12 bits data from DVP of image sensor. I refer VIP Input Data Width section of PDK_Application_Notes_Video_Driver_Porting.pdf to modify videoIfWidth parameter to FVID2_VIFW_16BIT. But seem like image has crop as below Could you please give me some advise? Many thanks.

P.S. VIP port : 1A VSDK revision : V03.04.00(04-Jul-2018) Test use case : Chains_vipSingleCam_Display();

Hi, You mean, it captures full frame over 8bit interface, but crops it in 16bit interface?? Could you please help me understand issue. Rgds, Brijesh

Hi Brijesh, Yes we image sensor will output YUV420SP + 12 bits data width from DVP port. As TI document suggest if we need receive data width more than 8 bits that need to changing "videoIfWidth" to FVID2_VIFW_16BIT.(Original is FVID2_VIFW_8BIT) Image sending frame to TDA2 but crops just occurs when "videoIfWidth" has modified FVID2_VIFW_16BIT.(FVID2_VIFW_8BIT is OK) Hope above will help we in same page.

Update information as below. We use OV10635 to output YUV 8 by DVP interface and modify "videoWidth" parameter to compare. videoIfWidth = FVID2_VIFW_8BIT => DVP data width = 8bits videoIfWidth = FVID2_VIFW_16BIT => DVP data width = 10 bits, 12 bits, 14 bits When "videoWidth = FVID2_VIFW_16BIT" seem like frame has crops. Test environment:

Hi, How are displaying 12/10 bit YUV data? Display does not support YUV422 in 10bit. Also please note that 10/12bit YUV422 will be stored in 16bit container. You need to convert it into 8bit packed as supported by display.. Rgds, Brijesh

Hi Brijesh, Thanks for replying. I don't change any setting of display link. I just change all FVID2_VIFW_8BIT setting to FVID2_VIFW_16BIT of capture link. About data stored in container have any document can sharing?

Hi, It is not about changing display link. Display HW does not support 10bit YUV data. You need to convert it into 8bit YUV data.. Data will be stored as shown below in 16bit container. Here 'x' is your bit value 000000xx xxxxxxxx Rgds, Brijesh

Hi Brijesh, Do you mean what ever I receive YUV 8 or 12 bits width data from DVP of image sensor finally that all needs to convert to 8 bits YUV data if we want pass it to display link? Could you please show me where are data container in SDK? Thanks for your support.

Yes, Display does not support more than 8bits per color component. Rgds, Brijesh

Hi Brijesh, Last question is where are capture data container in SDK? I will create new ticket if have any concern. Many thanks.

Hi, I did not get the question.. Regards, Brijesh

Hi Brijesh, My question is what function or data structure of SDK that are you say image frame container? I can trace the function or data structure to study. Hope above description is helpful.

Hi Prince, From the VIP point of view, VIP supports only 8bit per component data type. For more than 8bit per color component, we treat 10/12 bit each component as if it is YUV422 and configure VIP accordingly. This is why the output is in 16bit container. Rgds, Brijesh

Hi Brijesh, Thanks for your support. I will create new ticket if I have any concern. Have nice day~~

Ticket Name: TDA2EVM5777: TDA2 PCB footprint

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello I found package outline of TDA2 on the spec. But I don't know how to build a pcb footprint of it. Is there PCB recommend document? thank you

Hi, Here is the TDA2's PCB: www.ti.com/.../sprr209 Regards, Yordan

Hello I have this PCB file. But the outline of TDA footprint is too big , the board space is too small to place all components in. If we don't need the 4 NPTH holes on the outline due to there is no necessary to put on the heat sink, what is the clearance "x" should be? thank you

Hi, sorry for the delayed response. We are working on this and will update as soon as we have results. Regards, Yordan

The CAD/CAE symbols are now available on the web at http://www.ti.com/product/TDA2/pinout-quality The .bxl file can now be downloaded from https://webench.ti.com/cad/dlbxl.cgi/TI_BXL/TDA2_ABC_760.bxl Let us know if that doesn't meet your needs. Regards, Kyle

Ticket Name: Compiler/TDA2EG-17: TDA2 with 4 Channel BT656 input + 1 TVI output output , format 1080P?

Part Number: TDA2EG-17 Other Parts Discussed in Thread: TDA2, Tool/software: TI C/C++ Compiler Hi Champs: We have a customer wants to have 1080p format for 4 Channel BT656 input 1 TVI output output. Is this do-able? The TVI output is something like this: https://community.nxp.com/docs/DOC-335803 https://videos.cctvcamerapros.com/surveillance-systems/what-is-hd-tvi.html And the desired TVI IC is : Techpoint TP2854. TP2854: Automotive Grade 4 Channel 1080P/720P/D1 Receiver with MIPI CSI-2 Output Support http://www.techpointinc.net/products.html Please comment us if this is do-able on TDA2 or TDA4. THanks. BR Rio

Hi Rio, Yes, you could use VIP to capture 4 channel BT656 input. But i am not sure about output. What is HDTVI? DSS can output 1080p resolution over DPI (parallel embedded sync or discrete sync) and HDMI output. Can some external chip be used to convert to HDTVI format? Regards, Brijesh

Hi Brijesh: Thanks for helping. The HD-TVI is this: http://smartvisiondirect.com/topic/hdtvi/ https://www.supercircuits.com/compare-hd-analog-video-formats The customer is using the TP2854 IC that converts HD=TVI to MIPI CSI-2. So, this shall work on the TDA2? I need to double confirm from you. Thanks. BR Rio

Hi Rio, As far as i understand from the above link, HDTVI is difference format, uses different cabling. I think TDA2x cannot directly output this format. If they are anyway going to convert output to CSI2, they can use DPI to CSI conversion chip. Since external chip, which can be directly connected to TDA2x output.. Rgds, Brijesh

Hi Brijesh, It's Jim from whetron. You can refer to link : drive.google.com/open The purpose is to achieve all HD-TVI video interface for AVM System. 4-channel camera with HD-TVI signal input and 1-channel HD-TVI signal output. Also, Support up to 1080P. The questions are : Could TDA2EG-17 support 4-channel BT656(1 clock, 8 bit data, without H/V Sync) or MIPI-CSI2 input ? Refer to page 1. Could TP2824 , TP2854 or TP2915 work on the TDA2EG-17 ?

Hi Jim, Rio, VIP in TDA2EG definitely supports BT656 input. What i am not sure, how many VIP instances are supported in this devices. Could you please check? If there are atleast two instances supported, both can have two ports, and each port can support 8bit BT656 input. For Techpoint devices, it says it supports 4xBT656, but how does it output? Does it output in multiplexed mode or 4 different BT656 output? Also what is the sequence of SAV/EAV codes? Sometimes HD resolutions output different SAV/EAV codes. VIP supports only standard SAV/EAV codes.. Rgds, Brijesh

Ticket Name: Linux/TDA2: 1: 1CH VIP capture + OpenCL Copy (A15->DSP) + SGX Copy + DISPLAY run fail

Part Number: TDA2 Tool/software: Linux i build tda2xx_evm_linux_opencx and try to run OpenCL Usecases but failed! MAKECONFIG?= tda2xx_evm_linux_opencx [HOST] [HOST ] OpenCompute Usecases [HOST] [HOST ] ---------------------------- [HOST] [HOST ] 2: OpenCV Usecases [HOST] [HOST ] 3: OpenCL Usecases [HOST] [HOST ] [HOST] [HOST ] x: Exit [HOST] [HOST ] [HOST] [HOST ] Enter Choice: [HOST] [HOST ] 3 [HOST] [HOST ] 284.193070 s: [HOST] [HOST ] 284.193100 s: [HOST] [HOST ] [HOST] [HOST ] OpenCL Usecases [HOST] [HOST ] ---------------------------- [HOST] [HOST ] 1: 1CH VIP capture + OpenCL Copy (A15->DSP) + SGX Copy + DISPLAY [HOST] [HOST ] [HOST] [HOST ] x: Exit [HOST] [HOST ] [HOST] [HOST ] Enter Choice: [HOST] [HOST ] 1 [HOST] [HOST ] 288.289208 s: [HOST] [IPU2 ] 288.289361 s: CHAINS: Sensor create in progress [HOST] [IPU2 ] 288.289910 s: VIDEO_SENSOR: INST0 : I2C1 : I2C Addr = 0x30 [HOST] [IPU2 ] 288.386933 s: VIDEO_SENSOR: VIP 0: DRV ID 1203 (I2C ADDR 0x30): a635:0000:7fa2 [HOST] [IPU2 ] 288.387268 s: CHAINS: Sensor create ... DONE !!! [HOST] [IPU2 ] 288.402183 s: CAPTURE: Create in progress !!! [HOST] [IPU2 ] 288.402580 s: CAPTURE: VIP1 Slice0 PortA capture mode is [ 8-bit] !!! ASSERT (chains_vipSingleCamOpenCLFrameCopySgxDisplay_priv.c|chains_vipSingleCamOpenCLFrameCopySgxDisplay_Create|165) [HOST] [HOST ] 288.525071 s: IPC_IN_0 : Create in progress !!! [HOST] [HOST ] 288.525498 s: IPC_IN_0 : Create Done !!! [HOST] [HOST ] 288.525559 s: ALG: ERROR: No alg create function specified (algId = 6) !!! [HOST] [IPU2 ] 288.523973 s: CAPTURE: Create Done !!! [HOST] [IPU2 ] 288.524461 s: IPC_OUT_0 : Create in progress !!! [HOST] [IPU2 ] 288.524827 s: IPC_OUT_0 : Create Done !!! ▒OMAP SD/MMC: 0, OMAP SD/MMC: 1 ** First descriptor is NOT a primary desc on 1:1 ** *** Warning - bad CRC, using default environment

CMEM Error: init: Failed to open /dev/cmem: 'No such file or directory' TIOCL FATAL: The cmemk kernel module is not installed. Consult the OpenCL UserGuide at software-dl.ti.com/.../index.html

Hi Shuai, did you followed "vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_UserGuide_opencx.pdf"? There is a chapter about installing cmem module. Regards, Yordan

Ticket Name: Linux/TDA2: OpenCL use case running Failed (Build via Linux)

Part Number: TDA2 Tool/software: Linux Dear TI: After build the OpenCL successfully ((Linux) and run the OpenCL use case , I got the below issue: [HOST] [HOST ] 194.371225 s: Kernel Set Arg Error: -48 [HOST] [HOST ] 194.371225 s: Kernel Set Arg Error: -48 [HOST] [HOST ] 194.371225 s: Kernel Set Arg Error: -48 [HOST] [HOST ] 194.403922 s: Kernel Set Arg Error: -48 [HOST] [HOST ] 194.403922 s: Kernel Set Arg Error: -48 [HOST] [HOST ] 194.403922 s: Kernel Set Arg Error: -48 [HOST] [HOST ] 194.403952 s: Kernel Set Arg Error: -48 [HOST] [HOST ] 194.403952 s: Kernel Set Arg Error: -48 Please advise. Thanks and best regards He Wei

Wei please refer VisionSDK_UserGuide_opencx.pdf to build and run openCL demos. Did you make any chances in VSDK or just trying to rebuild and run the demos? BTW, which openCL Usecase/demo you are trying out? regards, Shiju

Dear Shiju, You means we need to rebuild the openCL demos? Currently I am following VisionSDK_Linux_UserGuide.pdf to build with: MAKECONFIG=tda2xx_evm_linux_opencl After build successfully, and launching on sd card as: $> cd /opt/vision_sdk $> ./load_ocl_kos.sh (needed only for opencl usecases) $> source ./opencl_env.sh (needed only for opencl usecases) $> source ./vision_sdk_load.sh $> ./$(MAKEAPPNAME).out Then I select the 1st available OpenCL use case to run. So this will not work if not rebuild OpenCL demo following VisionSDK_UserGuide_opencx.pdf ? Thanks and best regards He Wei

He Wei Sorry, We had an issue with OpenCL, as the openCL demos on A15 Linux are broken from VSDK 3.2 onward due a non-compatibility issue between Linux Kernel and openCL pre-built package. OpenCL on A15 linux is depreciated from VSDK 3.2 release onwards regards, Shiju

Ticket Name: TDA2SX: phy is often automatically disconnected and soon connected automatically

Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi all, I'm now running networktx demo to test network function with a TDA2x EVB(Vayu).But I find a problem that phy is often automatically disconnected and soon connected automatically. My VisionSDK version is 2.9.1.0. And I use BIOS only on all cores. Here's the log. [IPU1-0] 9550.666564 s: NDK: Link Status: 1000Mb/s Full Duplex on PHY 2 [IPU1-0] 9917.376166 s: NDK: Link Status: No Link on PHY 2 [IPU1-0] 9920.269718 s: send failed (55) [IPU1-0] 9920.303086 s: send failed (55) [IPU1-0] 9920.369700 s: send failed (55) [IPU1-0] 9920.403068 s: send failed (55) [IPU1-0] 9920.436344 s: send failed (55) [IPU1-0] 9920.503050 s: send failed (55) [IPU1-0] 9920.536326 s: send failed (55) [IPU1-0] 9920.569663 s: send failed (55) [IPU1-0] 9920.636308 s: send failed (55) [IPU1-0] 9920.669615 s: send failed (55) [IPU1-0] 9920.703013 s: send failed (55) [IPU1-0] 9920.769596 s: send failed (55) [IPU1-0] 9920.802964 s: send failed (55) [IPU1-0] 9920.836271 s: send failed (55) [IPU1-0] 9920.902946 s: send failed (55) [IPU1-0] 9920.936283 s: send failed (55) [IPU1-0] 9920.969560 s: send failed (55) [IPU1-0] 9921.036234 s: send failed (55) [IPU1-0] 9921.069511 s: send failed (55) [IPU1-0] 9921.102909 s: send failed (55) [IPU1-0] 9921.169493 s: send failed (55) [IPU1-0] 9921.176569 s: NDK: Link Status: 1000Mb/s Full Duplex on PHY 2 [IPU1-0] 9978.377844 s: NDK: Link Status: No Link on PHY 2 [IPU1-0] 9981.221069 s: send failed (55) [IPU1-0] 9981.254346 s: send failed (55) [IPU1-0] 9981.321051 s: send failed (55) [IPU1-0] 9981.354328 s: send failed (55) [IPU1-0] 9981.387695 s: send failed (55) [IPU1-0] 9981.454279 s: send failed (55) [IPU1-0] 9981.487677 s: send failed (55) [IPU1-0] 9981.521106 s: send failed (55) [IPU1-0] 9981.587628 s: send failed (55) [IPU1-0] 9981.621088 s: send failed (55) [IPU1-0] 9981.654242 s: send failed (55) [IPU1-0] 9981.721100 s: send failed (55) [IPU1-0] 9981.754224 s: send failed (55) [IPU1-0] 9981.787592 s: send failed (55) [IPU1-0] 9981.854175 s: send failed (55) [IPU1-0] 9981.887573 s: send failed (55) [IPU1-0] 9981.921094 s: send failed (55) [IPU1-0] 9981.987525 s: send failed (55) [IPU1-0] 9982.021045 s: send failed (55) [IPU1-0] 9982.054138 s: send failed (55) [IPU1-0] 9982.120996 s: send failed (55) [IPU1-0] 9982.154120 s: send failed (55) [IPU1-0] 9982.178185 s: NDK: Link Status: 1000Mb/s Full Duplex on PHY 2 [IPU1-0] 10012.478740 s: NDK: Link Status: No Link on PHY 2 [IPU1-0] 10015.745684 s: send failed (55) [IPU1-0] 10015.779906 s: send failed (55) [IPU1-0] 10015.812389 s: send failed (55) [IPU1-0] 10015.879887 s: send failed (55) [IPU1-0] 10015.912249 s: send failed (55) [IPU1-0] 10015.945647 s: send failed (55) [IPU1-0] 10016.012230 s: send failed (55) [IPU1-0] 10016.045598 s: send failed (55) [IPU1-0] 10016.079942 s: send failed (55) [IPU1-0] 10016.145580 s: send failed (55) [IPU1-0] 10016.180015 s: send failed (55) [IPU1-0] 10016.212194 s: send failed (55) [IPU1-0] 10016.279448 s: NDK: Link Status: 1000Mb/s Full Duplex on PHY 2 [IPU1-0] 10287.886201 s: NDK: Link Status: No Link on PHY 2 [IPU1-0] 10290.643018 s: send failed (55) [IPU1-0] 10290.676325 s: send failed (55) [IPU1-0] 10290.742969 s: send failed (55) [IPU1-0] 10290.776276 s: send failed (55) [IPU1-0] 10290.809613 s: send failed (55) [IPU1-0] 10290.876227 s: send failed (55) [IPU1-0] 10290.909595 s: send failed (55) Thanks.

Hi, I have forwarded your question to networking experts. Regards, Yordan

Hello, What is Vayu EVM revision you working on? Also kindly share TDA2 silicon revision. Some of TDA2 EVM revisions has known stability issues with 1000Mbps link. You can try connecting 100Mbps connection and see if you see same behavior.

Hi，Prasad. Vayu EVM revision is 2.0.I did some test yesterday, and we have some of the findings. That's what happens when I connect this EVM to the router, and when I get to the LAN, the problem doesn't show up

Ticket Name: TDA4VM: Linux OS memory size

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hello Jacinto team, My customer is considering TDA4 for its Automotive Vision application, and they are asking me about the size that Linux OS takes on theTDA4 SoC: from previous experience with TDA2, they know Linux took ~1Gb of Flash memory. Do you know what is the memory requirement for Linux OS on TDA4 ? Best regards, Antoine

Hi Antoine, This is the output of free command on our latest 7.3 Linux SDK. So ~1 GB with Linux. ~3GB is free out of total 4GB DDR on board. If no other questions please click verify answer. Best Regards, Keerthy

Ticket Name: TDA2: Question for VIP YUV to RGB

Part Number: TDA2 Hi, The VIP input is YUV 422: 1、If we change outParams[0].dataFormat to SYSTEM_DF_RGB24_888, the capture does not work(CaptureLink_drvProcessData() has no print log). 2、If we change outParams[0].dataFormat to SYSTEM_DF_YUV420SP_UV, the capture working(CaptureLink_drvProcessData() has print log). Does any possible param set loss or other sugguestion for this issue?

Hi Bin Ye, Can you please check if CSC is enabled in the path? It should work. Rgds, Brijesh

Hi Brijesh, We have some new clue for this issue: 1、In function VpsHal_dssConfVidPipe, the “vidConf->inFmt.dataFormat” is always FVID_DF_YUV420SP_UV whatever the outParams[0].dataFormat is set to SYSTEM_DF_RGB24_888 or SYSTEM_DF_YUV420SP_UV or other format. It is hard for us to find how the dataFormat coming due to the some function invoking is not explicit between ti component and vision_sdk. Could you tell us what is the source configure place for inFmt.dataFormat? 2、In function VpsHal_dssConfVidPipe, only YUV format could entry halDssVidConfCscEnable as below. Does it need to add condition for RGB? if ((vidConf->inFmt.dataFormat == FVID2_DF_YUV422I_YUYV) || (vidConf->inFmt.dataFormat == FVID2_DF_YUV420SP_UV) || (vidConf->inFmt.dataFormat == FVID2_DF_YUV422I_UYVY)) { halDssVidConfCscEnable(handle, (UInt32) 1U); } 3、In function halDssConvFvid2DataFmt, there is no case for FVID2_DF_RGB24_888(only have FVID2_DF_BGR24_888), does it means RGB888 not support? Int32 halDssConvFvid2DataFmt(UInt32 handleId, UInt32 fvid2Fmt) { Int32 fmt; Int32 dssVidPipe, dssWbPipe; dssVidPipe = VpsHal_dssIsVidPipe(handleId); dssWbPipe = VpsHal_dssIsWbPipe(handleId); if (((Int32) TRUE == dssVidPipe) || ((Int32) TRUE == dssWbPipe)) { switch (fvid2Fmt) { case FVID2_DF_YUV422I_UYVY: fmt = 0xb; break; case FVID2_DF_YUV422I_YUYV: fmt = 0xa; break; case FVID2_DF_YUV420SP_UV: fmt = 0; break; case FVID2_DF_BGR24_888: /*RGB24-888*/ fmt = 0x9; break; case FVID2_DF_XBGR_4444: /*RGBX12_4444*/ fmt = 0x1; break; case FVID2_DF_BGRX_4444: /*XRGB12_4444*/ fmt = 0x4; break; case FVID2_DF_BGRA16_4444: /* ARGB16_4444*/ fmt = 0x5; break; case FVID2_DF_ABGR16_4444: /*RGBA16_4444*/ fmt = 0x2; break; case FVID2_DF_BGRX16_5551: /*xRGB16-1555*/ fmt = 0xF; break; case FVID2_DF_BGRA16_5551: /*ARGB16-1555*/ fmt = 0x7; break; case FVID2_DF_BGR16_565: /* RGB16- 565*/ fmt = 0x6; break; case FVID2_DF_BGRX24_8888: /*xRGB24-8888*/ fmt = 0x8; break; case FVID2_DF_XBGR24_8888: /*RGBx24-8888*/ fmt = 0xE; break; case FVID2_DF_BGRA32_8888: /*ARGB32-8888*/ fmt = 0xc; break; case FVID2_DF_ABGR32_8888: /*RGBA32-8888*/ fmt = 0xd; break; case FVID2_DF_ARGB32_8888: /*BGRA32-8888*/ fmt = 0x3; break; default: fmt = BSP_EFAIL; break; } } Rgds, Ye

Has any sugguestion for this issue? We are very puzzled...

Hi Bin Ye, The code that you are looking at is for the DSS. DSS support YUV to RGB using CSC and it supports on BGR format.. But i guess what you are looking for is YUV to RGB conversion in VIP, isn't it? Regards, Brijesh

Ok, we'll check it, thx.

Ticket Name: [TIDL_J7] Import and infer Example for jSegNet.

Other Parts Discussed in Thread: TDA2 Hi, After look into the tidk_j7_00_09_01_00 package, there is no import example for jSegNet. I only see segmentation_list_x.txt in test/testvecs/config. Can TI provide an example for jSegNet import and infer ? Charles

Sorry, it's tidl_j7_00_09_01_00 not tidk_j7_00_09_00_00.

Hi Charles, Can you check if you have ti_dl\test\testvecs\config\infer\internal\caffe\tidl_infer_jSegNet.txt? In case it is not there please wait for 1.0 release happening towards the end of this month. Regards, Rishabh

Hi, The infer file is there, but there is no import file and corresponding caffe model, sample image and label files. Will these files be attached in the 1.0 release ? Charles

Hi Charles, Sorry for the delayed response. We are using this network for internal TIDL validation and it is not a part of 1.0 release. We will validate a public version of this network and share with you. Regards, Rishabh

Hi, Thanks. We also need an example talking about "how to import the segmentation model". I didn't see the details in the j7 tidl documents. (Only an example for classification model) We have several segmentation models already running in TDA2 and would like to test them in TDA4 EVM. Hope you can help it! Charles

Hi, Rishabh Do you have a date for validating the public version of jSegNet? Charles

Hi Charles, I will be able to look at this next week. Regards, Rishabh

Hi Charles, You can download the caffe model from https://github.com/tidsp/caffe-jacinto-models/tree/caffe-0.17/trained/image_segmentation/cityscapes5_jsegnet21v2/sparse. Deploy.prototxt needs to be changed slightly. Modified file is attached 3005.deploy.prototxt Regards, Rishabh

Ticket Name: PROCESSOR-SDK-DRA7X: Linux - How to enable A15 dual core on TDA2

Part Number: PROCESSOR-SDK-DRA7X Other Parts Discussed in Thread: TDA2SX Hi, I use "omapconf show opp" to check CPU status, now the SDK only support to enable A15 core-0. How can I enable A15 core-1 in kernel device-tree? br, KS

Hi KS, I think that by default Linux starts both A15 cores in SMP mode (if the particular device have two cores). Can you clarify which device and which SDK ypu use? Regards, Yordan

Hi, I attach the SOC picture as the following, we use TDA2SX. And SDK version is PROCESSOR_SDK_VISION_03_05_00_00. There is the log msg, 5810.omapconf.txt oToBrite:/mnt/video_storage# omapconf show opp 
OMAPCONF (rev v1.73-17-g578778b built Mon Sep 17 14:55:36 IST 2018)

HW Platform:
  Generic DRA74X (Flattened Device Tree)
  DRA75X ES2.0 GP Device (STANDARD performance (1.0GHz))
  UNKNOWN POWER IC

SW Build Details:
  Build:
release_details_get(): could not open /etc/issue.net file?!
    Version: UNKNOWN
  Kernel:
    Version: 4.4.84+
    Author: yukichen@dell-r540
    Toolchain: gcc version 5.3.1 20160113 (Linaro GCC 5.3-2016.02)
    Type: #1 PREEMPT
    Date: Thu Apr 23 11:36:29 CST 2020

/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor not found, no CPUFREQ?

cpu_is_online(1): error opening /sys/devices/system/cpu/cpu1/online file!
omapconf: warning: no matching rate for VDD_GPU OPP.Please check rates against Data Manual recommendations.
|-----------------------------------------------------------------------------------|
|                        | Temperature | Voltage | Frequency      | OPerating Point |
| VDD_CORE / VDD_CORE0   | 59C / 138F  | NA      |                | NOM             |
|   L3                   |             |         |  266  MHz      |                 |
|   DMM                  |             |         |  266  MHz      |                 |
|   EMIF1                |             |         |  266  MHz      |                 |
|   EMIF2                |             |         |  266  MHz      |                 |
|     LP-DDR2            |             |         |  532  MHz      |                 |
|   L4                   |             |         |  266  MHz      |                 |
|   IPU1                 |             |         | (2128 MHz) (1) |                 |
|     Cortex-M4 Cores    |             |         | (1064 MHz) (1) |                 |
|   IPU2                 |             |         |  2128 MHz      |                 |
|     Cortex-M4 Cores    |             |         |  1064 MHz      |                 |
|   DSS                  |             |         |  192  MHz      |                 |
|   BB2D                 |             |         | (2128 MHz) (1) |                 |
|                        |             |         |                |                 |
| VDD_MPU / VDD_CORE1    | 60C / 140F  | NA      |                | NOM             |
|   MPU (CPU1 OFF)       |             |         |  1000 MHz      |                 |
|                        |             |         |                |                 |
| VDD_GPU / VDD_CORE2    | 59C / 138F  | NA      |                | UNKNOWN         |
|   GPU                  |             |         |  354  MHz      |                 |
|                        |             |         |                |                 |
| VDD_DSPEVE / VDD_CORE3 | 58C / 136F  | NA      |                | NOM             |
|   DSP1                 |             |         |  750  MHz      |                 |
|   DSP2                 |             |         |  750  MHz      |                 |
|   EVE1                 |             |         |  535  MHz      |                 |
|   EVE2                 |             |         |  535  MHz      |                 |
|                        |             |         |                |                 |
| VDD_IVA / VDD_CORE4    | 60C / 140F  | NA      |                | HIGH            |
|   IVA                  |             |         |  532  MHz      |                 |
|                        |             |         |                |                 |

Notes:
  (1) Module is disabled, rate may not be relevant.

Hi, Could you update any information? There is the dmesg log form kernel. Board_2020-05-15_13-13-49.log

Hi, I have modified kernel dts and config by myself. the command - "omapconf show opp" shows CPU 1 ON. Br, Ks.

Ticket Name: TDA2EXEVM: Changing TDA2 Memory Map

Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2, SYSBIOS Hi, I need to have much bigger DDR memory foot print for DSP1. Looks like all memory allocation request ended up a rquest to IPU0 for allocation. And ultimately the size of the Frame Buffer on SR1 needs to be much bigger. I tried to change the TDA2 memory map based on this doc https://processors.wiki.ti.com/index.php/VSDK/VisionSDK_UserGuide_MemoryMap 1. Created a new memory map C:\TI\processor_sdk_radar_03_08_00_00\vision_sdk\apps\build\tda2xx\mem_segment_definition_bios_1024mb.xs file for 1024MB with below changes: DDR3_SIZE = 1024*MB; DDR3_BASE_SIZE_0 = 1019*MB; if(java.lang.System.getenv("ECC_FFI_INCLUDE")=="yes") { /* Ensure ECC regions are 64kB aligned */ SR1_FRAME_BUFFER_SIZE = 809.5*MB; SR1_BUFF_ECC_ASIL_SIZE = 1*MB; SR1_BUFF_ECC_QM_SIZE = 40*MB; SR1_BUFF_NON_ECC_ASIL_SIZE = 1*MB; } else { SR1_BUFF_ECC_ASIL_SIZE = 4*KB; SR1_BUFF_ECC_QM_SIZE = 4*KB; SR1_BUFF_NON_ECC_ASIL_SIZE = 4*KB; SR1_FRAME_BUFFER_SIZE = 851.5*MB - } 2. From C:\TI\processor_sdk_radar_03_08_00_00\vision_sdk\build\rtos\tda2xx, modified the 4 config_a15.bld, config_m4.bld, etc...to look for 1024mb .xs file if (platformMem == "DDR_MEM_1024M") { var MemSegDefine = xdc.loadCapsule("" + appPath + "/build/tda2xx/mem_segment_definition_bios_1024mb.xs"); } if (platformMem == "DDR_MEM_512M") { var MemSegDefine = xdc.loadCapsule("" + appPath + "/build/tda2xx/mem_segment_definition_bios.xs"); } 3. Modified C:\TI\processor_sdk_radar_03_08_00_00\vision_sdk\apps\configs\tda2xx_cascade_bios_radar\cfg.mk DDR_MEM=DDR_MEM_1024M 4. Modified C:\TI\processor_sdk_radar_03_08_00_00\vision_sdk\build\rtos\makerules\components.make ifeq ($(PLATFORM),$(filter $(PLATFORM), tda2xx-evm tda2xx-rvp)) vision_sdk_CFLAGS = -DTDA2XX_BUILD -DTDA2XX_FAMILY_BUILD -DSOC_TDA2XX -DPLATFORM_EVM_SI vision_sdk_CFLAGS += -D_DRA7xx -D_SC_VER_1_16 -D__sysbios__ ifeq ($(DDR_MEM),DDR_MEM_512M) vision_sdk_CFLAGS += -DTDA2XX_512MB_DDR else vision_sdk_CFLAGS += -DTDA2XX_1024MB_DDR endif After that rebuilt the code with a fresh build (ie: gmake -s -j depend, etc...), Run the AppImage and it got stuck at boot in the attached screenshot. Please advice...any feedback is appreciate it. Thanks, --Khai

Hi, Have you done clean build by deleting the binaries folder? Thanks Gaviraju

Yes

Have you removed below changes in the 4 config_a15.bld, config_m4.bld, etc.. ? if(A15TargetOS == "Bios") { var MemSegDefine = xdc.loadCapsule("" + appPath + "/build/tda2xx/mem_segment_definition_bios.xs"); } Thanks Gaviraju

Hi Gaviraju, But I have this kind of logic in all 4 files with 1024MB memory check below: if(A15TargetOS == "Bios") { if (platformMem == "DDR_MEM_1024M") { var MemSegDefine = xdc.loadCapsule("" + appPath + "/build/tda2xx/mem_segment_definition_bios_1024mb.xs"); } if (platformMem == "DDR_MEM_512M") { var MemSegDefine = xdc.loadCapsule("" + appPath + "/build/tda2xx/mem_segment_definition_bios.xs"); } } Thanks, --Khai

Hi, Discard all your changes & refer to to below document. vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_UserGuide_MemoryMap.pdf Chapter 6.5: How To – Modify 512MB Bios Memory map to 1GB Bios Memory map Please apply the changes mentioned in the above steps. Thanks Gaviraju

Hi Gaviraju, There are a few outdated steps against existing Processor SDK 3.08 source tree. I was able to get it to work, however. The main thing missing in the PDF User Guide is the SR1 Frame Buffer size needs to be changed higher as EVEs and DSPs memory allocations are moved to SR0 thus freeing up about 100MB of DDR3 on SR1. This helped a little bit but not actually an increase to 1024 MB from the original 512MB. Is this the best we can do? Can SR1 Frame Buffer cross over to the non-cached SR0? Thanks, --Khai

Hi, Please refer the below section vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_UserGuide_MemoryMap.pdf 6.2 Changing size of a Section in the Memory map Thanks Gaviraju

Ticket Name: TDA2: Modifying linkercmd files

Part Number: TDA2 Hi, In Vision SDK, the linkercmd files are autogenerated. If I need to add a new section or edit the existing sections how to do it? Regards, Navinprashath.R.R

Hi Navin, You require to change bld file to add a new section and then inform about the new section to the BIOS. Then you could redirect the data structure to these memory section. You could refer to HDVPSS_DESC_MEM data section. It creates a new memory section of 2MB size, which is used for storing HDVPSS descriptors. Regards, Brijesh

hi for example, <1> to add/modify a section refer file - \vision_sdk\apps\build\tda2xx\mem_segment_definition_bios.xs <2> to redirect the data structure to these memory section (for core IPU1-0) - refer file \vision_sdk\links_fw\src\rtos\bios_app_common\tda2xx\ipu1_0\Ipu1_0.cfg for DSP1 - refer \vision_sdk\links_fw\src\rtos\bios_app_common\tda2xx\dsp1\Dsp1.cfg regards, Shiju

Ticket Name: Linux/TDA2: TDA2H and TDA3x ：DSP benchmarks

Part Number: TDA2 Tool/software: Linux Dear TI experts， When i run below test code on dsp，i found out the TDA3x's DSP is more efficient. Test Code: #define TSC_getDelay(preTSC) ((unsigned int)((0xFFFFFFFFl+TSCL)-(unsigned long long)preTSC)+ 1) short *T0; T0 = (short*) Utils_memAlloc(UTILS_HEAPID_DDR_CACHED_SR, 10240, 8U); //DDR { int t=0; int t0_time; int pclk; TSCL=0; pclk=TSCL; for(t =0;t<10240;t++) { T0[t] = t; } t0_time= TSC_getDelay(pclk); Vps_printf("DEBUG:---DDR = %d Result = %d ",t0_time,T0[1024]); } Result: [DSP1 ] 38.649484 s: DEBUG:---DDR = 12412 Result = 1024 //TDA3X with 709M DSP ;VSDK2.12 [HOST] [DSP2 ] 58.513542 s: DEBUG:---DDR = 43946 Result = 1024 //TDA2H with 750M DSP; VSDK2.12 linux Any ideas what is going on? Thank you. Best Regards Sid

Have you checked if they are both built in release mode? You can double check the asm file generated for this file and see that the ASM code for this code section is the same for both.

also make sure no task preemption during the execution of this code, it can be assured by interrupt disable and enable before and after the code as below UInt hwiKey = Hwi_disable(); :::::::::::::::::::::::::::::::::::: code ::::::::::::::::::::::::::::::::::: Hwi_restore(hwiKey); regards, Shiju

Hi Jesse & Shiju, Thanks . I found out when run the test code before my usecase started on tda2x, the result will be close to tda3x. The tda3x is only run a simple chains for test. when my usecase start on tda2x, there will have other three alg plugin links also run on dsp2, therefore the test code will consume more times to run. I think i need Optimization my alg code. Best Regards Sid

Ticket Name: TDA2: can not parse the inference result file(stats_tool_out.bin)

Part Number: TDA2 Hi everybody I suffered from a problem when we try to deploy tensorflow pre-trained model on td2x. Every step is fine(as described below). But, we can not parse the inference result file(stats_tool_out.bin) What is the format of 1-D vector as described in http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_TIDL.html ? How can we parse it? Does stats_tool_out.bin depend on training framework(e.g. caffe or tensorflow)? Can anyone help us? Steps are as follows: We have transformed the pre-trained model(MobileNet_v1_1.0_224) in https://github.com/tensorflow/models/tree/master/research/slim through the command below python "tensorflow\python\tools\optimize_for_inference.py" -- input=mobilenet_v1_1.0_224.pb --output=mobilenet_v1_1.0_224_final.pb -- input_names=input --output_names="softmax/Softmax" Then, we use tidl_model_import.out.exe and mobilenet_v1_1.0_224_final.pb to produce two bin files. Finally, we fed a image and the two bin files to get prediction file (stats_tool_out.bin)

it is raw binary file output tensors. One byte for each element in the tensor. For this case it is softmax output 1001 bytes. Refer "TIDeepLearningLibrary_UserGuide.pdf" for more information

"One byte for each element in the tensor" <= Does it mean that each byte stands for the score of each class?

Yes. it is fixed poitn format. refer users guide if you want to convert it to floating point

Could I ask another question? Is the format of stats_tool_out.bin defined by TI and independent of the output format of training framework(e.g. caffe or tensorflow)?

Yes it is independent of caffe or tensorflow. It is just biinary file. Read the file as a binary to a memory and typecast it to a byte array (signed or unsigned char based last tensor type) that all.

Ticket Name: TDA2: EVE: Unaligned access in VCOP ST INTRLV operation

Part Number: TDA2 HI, I have written a code in 16SIMD alignment , but while compiling the same on the simulator this warning comes EVE_1: Warning: Unaligned access in VCOP ST INTRLV operation the image resolution for which i have tested is 112x64. And because of this the output is not getting generated. Regards Surbhi

Surbhi, Half word interleave/de-interleave stores/loads must be word aligned ( that's the constraint with these instruction). Regards, Anshu

Ticket Name: TDA2E: Questions: About yuv422 display

Part Number: TDA2E Other Parts Discussed in Thread: TDA2 Hi, Support The processor we use is TDA2 ECO 23*23. My video output resolution is 1780*720, When I RGB output video, everything is normal. When I yuv output, a part of the picture is green in external display.I used dss to convert rgb to yuv, it was normal before conversion, and part of it was green after conversion.I use jtag dump dss link image,i use 7yuv to view the image. When the resolution is 1780*720, the image is distorted and some parts are green. When the resolution is 1784*720, the image is not distorted, but there are green parts.

Hi yongzheng lv, The first issue is due to pitch/line offset, it must be 16byte aligned. 1780x2 is not 16byte aligned. but 1784x2 is 16byte aligned. I think Green bar is due to input image. Are you sure sensor is outputting frame of size 720 lines? Rgds, Brijesh

Ticket Name: Linux/TDA2: Use EDMA similarly to EDMA LLD on RTOS?

Part Number: TDA2 Tool/software: Linux Hello, EDMA Low Level Driver for RTOS is defined very well and easy to use. It provides enough flexibility regarding usage of A/B/CCNT, indexing, linking and chaining. I need that flexibility in Linux. However the only thing I managed to do is use DMA engine which is awfully limited in its features (only contiguous memcpy). I found that in 'edma.c' file there is a lot of well known API for EDMA usage. However, there is a lot of functions there and the steps that need to be taken are not intuitive. I would like an example of a simple code that I can run in a kernel module that enables me to reserve a few channels and param sets, possibly link the param sets and start a transfer. I find it such a shame that there are no examples for advanced EDMA usage on Linux whereas there are tons of examples for RTOS. Thank you in advance. Regards, Nick

Nick Linux includes a generic framework for DMA drivers which is "dmaengine" , the EDMA implementation plugs in to this framework. Drivers within the kernel use the dmaengine API for data movement primitives. You can look for more information on its usage inside the Kernel documentation folders : www.kernel.org/.../

Hi Sriram, Sorry but this does not answer my question. I said that I already use the "dmaengine" and that I'm not satisfied with what I can do with it. As I can see it is limited to contiguous memory transfers. But what if I have jumps that have to be made, I need the flexibility of EDMA's BIDX and CIDX parameters. With "dmaengine" I cannot do anything like that which is a pitty because EDMA can do so much more. I have just found this: processors.wiki.ti.com/.../EDMA_sample_test_application but it does not build successfully because it is for DaVinci boards. Is there anything like this for TDA2 boards? Or even better, if all EDMA features can be used with "dmaengine" I would like to know how to do it. Thank you in advance. Regards, Nick

Nick The Linux side implementation only supports the DMAengine interface currently - and this is abstracted to handle a number of DMA implementations , hence you get only the common subset of features

Ticket Name: Linux/TDA2: remoteproc1: handling crash #1 in 40800000.dsp omap_hwmod: timer5: _wait_target_disable failed

Part Number: TDA2 Tool/software: Linux i am using SDK_VISION_03_02_00_00\vision_sdk\sample_app\src\rtos\alg_plugins\framecopy , i add my work after framecopy, #define L2SRAM_SIZE (32*1024) unsigned char L2SRAM[L2SRAM_SIZE]; #define L2TMP_SIZE (180*1024) unsigned char L2TMP[L2TMP_SIZE]; this can cause some problem , log is follow [ 52.906434] remoteproc1: crash detected in 40800000.dsp: type mmufault [ 52.913086] omap-iommu 40d01000.mmu: 40d01000.mmu: errs:0x00000002 da:0x20202020 pgd:0xed7bc808 *pgd:px00000000 000) [ 52.923429] remoteproc1: handling crash #1 in 40800000.dsp (TCC) = 8448b000 (8448b000)

Hi, These variables names has been used by the system. so please do not use them. What are you modifying inside SDK_VISION_03_02_00_00\vision_sdk\sample_app\src\rtos\alg_plugins\framecopy ? Regards, Anuj

Hi Anuj I test my algorithm using this link . I have find it cause by follow code. i get cycles in many place like this in my code. but why it handling crash? //unsigned long long WH_time[10]; // double WH_cost[10]; // TSCH = 0; //TSCL = 0; // WH_time[0] = _itoll(TSCH, TSCL); Image_Resize(pHandle, (ASVLOFFSCREEN*)psImgSrc); // WH_time[1] = _itoll(TSCH, TSCL); //WH_cost[0] = (double)(WH_time[1] - WH_time[0]) / 1000000.0; // printf("Image_Resize = %f ms\n", WH_cost[0]); // Vps_printf("forward_neImage_Resize = %f ms\n",WH_cost[0]); Regards, shuai

Hi, I did not understand your last message. Can you explain in more detail. And what are you trying to do in this link. Can you share the changes. Regards, Anuj

Hi: Anuj in framecopy link, i add my algorithm Interface function after framecopy is done， Initialization add in Alg_FrameCopyCreate . it Include 10 .c file and 8 .h file , i add .c file name in SRC_FILES.MK to Compile them. but in the 10 .c i add follow code to get functions cycles in many place . and i think this caused the problem, now it move away my algorithm is run successful. unsigned long long WH_time[10]; double WH_cost[10]; TSCH = 0; TSCL = 0; WH_time[0] = _itoll(TSCH, TSCL); WH_time[1] = _itoll(TSCH, TSCL); WH_cost[0] = (double)(WH_time[1] - WH_time[0]) / 1000000.0 befor this i use ccs Compile the 10 .c and 8.h ,create my.lib. i make a lib Folder in framecopy and put my.lib in it . but when i Compile the sdk it looks like canot find functions in my.lib so i changed i add all souce code in . then can you tell me what is the problem? i think make a lib first is nice . BESTWISHES SHUAI

Ticket Name: Linux/TDA2: Alignment trap

Part Number: TDA2 Tool/software: Linux i am use SDK_VISION_03_04_00_00 run my algorithm ，have some problem when run the program. follow is the log [ 1327.806627] Alignment trap: not handling instruction edc37a00 at [<00050702>] [ 1327.813818] Unhandled fault: alignment exception (0x811) at 0x00000249 [ 1327.822094] pgd = d8c3c000 [ 1327.824814] [00000249] *pgd=be053831 ./start: line 3: 874 Bus error (core dumped) ./sample_app.out i add some log to find where is the program. I found that there is a problem with a function, before this function to print log 1 and then enter the function to add a print log2, when the program runs, Log1 can come out, but log2 can not come out. could you analys what is the problem?

Hi, Please go through the below thread e2e.ti.com/.../41140 Regards, Anuj

Hi Anuj maybe stack space is not enough， could you tell me how to adjust the size of stack space？ where is the config file？ BESTWISHES shuai

Hi Shuai, If you want to increase the stack size used please modify the macro SYSTEM_DEFAULT_TSK_STACK_SIZE defined in links_fw/src/hlos/system/system_priv_common.h in vision-sdk. The error doesn't seem to be due to lack of stack space, but because of misaligned address access. I would suggest stepping through your code using gdb or any other debugger and finding the root-cause of the misaligned access. Regards Shravan

Ticket Name: TDA2E: EVE output data format with beamforming in Processor Radar SDK

Part Number: TDA2E Other Parts Discussed in Thread: TDA2, AWR1243 Hi expert, We are working on TDA2+AWR1243 cascade board for beamforming test. There is two TX beam steering which is chirp based and frame based as below Is the EVE output data format same in these two scenarios? As mentioned in the graph as below. If not, what's the difference? Thanks a lot. Best Regards, Allen

Hi Allen, The figure which you mentioned is the output of Doppler FFT from the EVE processing. This will be same irrespective of the input, what will actually change is the way input is given to EVE FFT applet. The input is described using FFT_TI_BufferDescriptor structure. We have validated he first case (Chirp based). But I can see a potential problem if you use frame based sequence as TDA2X dma supports a maximum jump of 16 bit signed integer so if your frame jump is more than maximum 16 bit signed integer it will not work. Regards, Anshu

Hi Anshu, Based on the sequence of frames, the number of frames is equal to the number of burst. In radarFft2. C, Eve is operated in the unit of burst. The input and output addresses correspond to their respective offset and width. How can I get the DMA parameters corresponding to the input and output of Doppler FFT. My Doppler FFT results are incorrect. Thanks.

Hi Allen, DMA is programmed inside FFT_TI_dmaControl ( file : apps\fft\algo\src\fft_graph_int.c ). For doppler FFT fftDirection value will be FFT_TI_DIRECTION_VERTICAL. Regards, Anshu

Ticket Name: TDA2: TDA2EVM [VAYU EVM XC5777X CPU BOARD] How to set the board for capture the lvds camera by raw[0~7] ?

Part Number: TDA2 Hi master: My board is TDA2EVM [VAYU EVM XC5777X CPU BOARD] The board run OV10635 camera well, the des out raw is [2~9], now we need to use another camera the des out raw is [0~7], How can I set the board? thanks. kevin.zd

Hi Kevin, Can you please clarify, if the question is on processing RAW data format vs YUV or connecting camera to the EVM? Regards, Sujith

sorry. my camera is same as ov10635 camera, only output Raw pin is 0~7, the camera ov10635 is 2~9, evm board + ov10635 camera. ov10635-> ds90ub913[Din 2~9 ] - ds90ub914[Dout2-9] -> CPLD->J6 Vipx[0~7] evm board + my camera. mycamera-> ds90ub913[Din 0~7 ] - ds90ub914[Dout 0-7] -> CPLD->J6 Vipx[0~7] how set the board config SW ? Make my camera work well.

Hi Kevin, Do you use the vision app board and multides board to connect the camera? What board settings are you using for the ov10635x camera? Regards, Prasad

Hi Prasad: Please see my attach file pics. TI Board PIC.zip kevin.zd

Hi Kevin, Were you able to resolve this? Regards, Sujith

Ticket Name: TDA2: TDA2 5h AWR1243 frame over PCIe

Part Number: TDA2 Other Parts Discussed in Thread: AWR1243 To achieve 32 channel radar we are putting two of the TDA2 Cascade Radar hosts together. TI has recommended these two TDA2 chips are connected together by PCI-e to facilitate synchronization for all 32 channels. Will it be possible to pass a AWR1243 4 channel VIP frame between the two TDA2 chips to process data in the center channel?

Pass the VIP frames over PCI-e in real time?

Zach, what is the kind of data rates you are looking at? We have PCIe based storage to SSD which can potentially reach 400-420 MBytesps data rates. On Processor SDK 3.6 release there is a known issue for the PCIe speeds which limits the data rate to 1.6 Gbits ps, which is planned to be fixed in 3.7. Thanks and Regards, Piyali

Hi Piyali, We are planning 30 frames per second of 128 doppler for the 1024 bits per chirp for 12 transmitter at the AWR1243 ADC resolution for 12 bits so per channel: 30 x 128 x 1024 x 128 x 12 x 12 = 566,231,040 bits per second for each channel. We have been thinking in terms for a VIP frame with we assume had 4 channel interlaced per VIP frame. So we need 4 times this number of bits per second. This is more then the 1.6 Gbps currently supported by PICe. When will SDK 3.7 release? Is this same SDK of the TDA2-AWR1243 we are on hold for? What is the PCI-e expected data rate at that time? Can we plan on taking the VIP and separate it into channels and pass just on channel each way between the two TDA2 rather then the 4 channel VIP frame? Regards, Zach

Hi Zach, To set your expectation correctly, we don't have application level SW for board to board communication over PCIe. We have bare metal PCIe driver which can be used as your base to implement your own SW for the board to board communication. Or, we have third party who can provide board-to-board PCIe solution. The bare metal driver can transfer data between board at > 4Gbps. The 1.6Gbps throughput Piyali mentioned was the PCIe SSD card write throughput using Linux SW with block driver. We are working on improving the performance. However, this is not applicable to your usage since it doesn't have support for board to board communication. Regards, Stanley

Thank you Stanley. Please provide the third party who can provide board-to-board PCIe solution contact information? Thank again, Zach

You can contact RT-RK.

Ticket Name: Linux/TDA2: TDA2xx/linux load_cmem_ko.sh

Part Number: TDA2 Tool/software: Linux Hi， When I follow document VisionSDK_UserGuide_opencx.pdf，In the 1.2 step ./load_cmem_ko.sh. But in my vision_sdk there is no this file. How can I get load_cmem_ko.sh？ Thanks

Hi Xie Baojian, This file is present under "vision_sdk\build\hlos\scripts\linux" folder When you build any linux configuration (like tda2xx_evm_linux_all or tda2xx_evm_linux_opencx) , this file is copied to file system path (/opt/vision_sdk) Regrads Surya

Hi Surya, there is no load_cmem_ko.sh in my "vision_sdk\build\hlos\scripts\linux" folder. What's the problem? How can I get the load_cmem_ko.sh？ Regrads, Xie Baojian

Hi Xie Baojian, Which version of Vision SDK are you using ? Regards Surya

Hi Surya, my vision SDK is PROCESSOR_SDK_VISION_03_02_00_00. Regards, Xie Baojian

Hi Xie Baojian, This is the file which will load cmem "load_ocl_kos.sh" Regards Surya

Ticket Name: TDA2: EVE/KernelC:- using IF condition in VCOP

Part Number: TDA2 Hello, I want to use if condition inside for loop. As of now, i know that if condition should be use with LCV of the for loop. I am using the same, #define I3EQUALS2 ((I3==2)) for(int I3=0;I3<3;I3++) { if(I3EQUALS2) { //code to be execute } } But I'm getting below error on console, error #26001-D: syntax error - expected IDENTIFIER error #26001-D: syntax error near ')' error #26001-D: syntax error near '=' ,m...something like this. Please suggest solution for this!!

hi Kajal, Is this loop written for VCOP or ARP32? Regards, Anshu

Loop is written for VCOP. for(int I1=0;I1<rows;I1++) { for(int I2=0;I2<(cols/VCOP_SIMD_WIDTH);I2++) { for(int I3=0;I3<3;I3++){ //code } } } Regards, Kajal

you cannot have If condition inside VCOP. You may use select instruction to selectively pick certain values from the vector based on another vector. Regards, Anshu

Hello Anshu, Yes , we can use select instruction. cmov_test kernel is using if condition in vcop (EVE_example_kernels_1.0.0.0/kernelslib/cmov_test), that's why asked, why issue is with my case. Anyhow I want to check condition with LCV (Depending on LCV's value i.e scalar) and select works with vector. So How do I solve this? Regards, Kajal

Hi Kajal, The if statement used in the example which you are mentioning is not a typical if condition. It basically is doing a condition move. Based on the condition it is moving src to dst. You cannot have any other piece of code in this "if" condition. Thats the reason you are getting build errors. Regards, Anshu

Thanks for the information Anshu. Regards, Kajal

Ticket Name: TDA2: CSI2 to VIP frame definition in SDK

Part Number: TDA2 Other Parts Discussed in Thread: AWR1243 SDK detail for Cascade Radar Host Processor Board PROC055 we need the definition of the FPGA transfer function converting AWR1243 four channels stream on 4 CSI2 lanes, to the parallel 24 bit data signal of VIP input to the TDA2.

You would find the FPGA image which converts the CSI to 16 bit parallel in the SDK www.ti.com/.../processor-sdk-tdax under: D:\PROCESSOR_SDK_RADAR_\ti_components\drivers\pdk_\packages\ti\drv\vps\unit_test\cascadeRadarUt\fpgaimage

Ticket Name: Compiler/TDA2: DSP2 crashed after __c_init00 , before main() was called

Part Number: TDA2 Tool/software: TI C/C++ Compiler We use TAD2x Hardware platform, VisionSDK 3_03, all Bios system, DSP compiler ti-cgt-c6000_8.1.3. We have an algorithm run on DSP2 within a link. When the DSP2 's program was loaded into DDR and started run from __c_init00, the DSP2 will crash before main() was called (I debug it by JTAG). There is no error when I compile it. When I comment off all the call of our algorithm functions in the link 's "_init: and "_process", DSP2 starts OK. This algorithm runs fine on TDA2x 's DSP1 with visionSDK 2_10, DSP compiler ti-cgt-c6000_8.1.3. Please help me! The DSP2's binary and map file was attached.tda2xx-evm_DSP2_binary_map_file.rar

Hi, Do you get the same result with compiler version 7.4.2? I would suggest you to use the same compiler versions that were used to validate the particular release. Regards, Rishabh

Dear Rishabh, We can't use compiler C6000_7.4.2 or c6000_7.4.14 in our project. Our project use Opencv 2.3.1 on DSP. Compiler C6000_7.4.2 can't compile Opencv2.3.1 and our algorithm code successful. Compiler C6000_7.4.2 don't support many syntax, but compiler ti-cgt-c6000_8.1.3 support. So, I use compiler ti-cgt-c6000_8.1.3 on visionSDK_2_10 in our project. Now, I need to transplant our algorithm to visionSDK_3_03. When I use compiler ti-cgt-c6000_8.1.3 replace compiler C6000_7.4.2 in visionSDK_3_03, after "make clean", and rebuild again, the system can't bootup(I think the DSP1 and DSP2 both crashed), although I don't add any algorithm in the usercase. When I don't "make clean", just add our algorithm into the usercase, the DSP2 crashed before main. Is it possilbe for me to use compiler ti-cgt-c6000_8.1.3 in the whole visionSDK_3_03, just recompile some basic lib to make it work in short time? This issue have blocked our project for 3 weeks. Please help me. Thank you very much.

Hi Bao, One point to keep in mind is that compiler change alone is not sufficient in most of the cases. BIOS, XDC and IPC versions usually change when compiler versions are changed. In SDK 2.10 there might be a different version of these components as compared to 3.3 release. Hence I would suggest you to stick to the old SDK version for time being in your project and continue your development. We are moving to C6000_8.2.4 for Vision SDK 3.5 release which will happen at the end of 3Q 2018. You should migrate to this release once it is available on ti.com. Regards, Rishabh

Hi, I haven’t heard back from you, I’m assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Rishabh

Hi Rishabh, I 'm thinking other solution for our project temporay. After VisionSDK 3.5 released, I will switch back to DSP. Thanks for your help.

Hi, Okay thanks for the update. Regards, Rishabh

Ticket Name: TDA2EVM5777: [TDA2x] Importing caffe-jacinto-model to TIDL

Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hello, My customer is trying to run TIDL test application on TDA2. They are using TIDL 01.01.03.00 in PROCESSOR SDK VISION 03.07.00.00. (1)They want to import “ssd768x320_ds_PSP_dsFac_32_hdDS8_0” from below link. https://git.ti.com/cgit/jacinto-ai-devkit/caffe-jacinto-models/tree/trained/object_detection/voc0712/JDetNet We can find deploy.prottxt only in directory “test_quantize”. Can we use it for importing the network to TIDL? (2)After importing the network by step (1), they compared the result with JDetNet structure on Web. It looks like there are some difference in network structure between them. Example: [Layer #] [Original network] [Imported network] Layer No.8 Pooling Convolution Layer No.10 Convolution Pooling We also see the difference in parameter values. Please find attachment for details. Could you please let us know the reason of the difference? Do we need to do anything for that? TIDL_network_data.xlsx Best regards, -Shibata

Hi Shibata, (1) Yes, please use the deploy.prototxt from directory “test_quantize”. (2) This is expected because both the model are different, the "JDetNet structure on Web" had only 4 classes, but this model in git has 21 classes. For more details please refer to below e2e link. https://e2e.ti.com/support/processors/f/791/t/689617 Thanks, Praveen

Hi Praveen, Thanks a lot for your comments. Regards, -Shibata

Ticket Name: TDA2: EVE:Execute Single Kernel into multi EVE cores

Part Number: TDA2 Hi guys, We need to execute a single kernel on different EVE cores with the following scenario. 1. The input image will be in x*y dimension. 2. It has to be broken into x1*y1, x2*y2, x3*y3 dimensions. 3. The kernel should be executed in all the EVE cores for these different image sections. 4. After the executions in all the cores completed, the individual outputs should be merged into x*y dimension single image. And, the execution can be done with or without the support of VisionSDK. Can you please suggest the steps or methodologies to do so. Regards Surbhi

Hello Surbhi, The first step would be to develop an applet on EVE to process any frame of dimensions x*y on one single EVE core. You can find more information on how to implement an applet by reading this post and its attached presentation: Then next step is to create a vision SDK alg-plugin that would be instantiated on 4 different cores but running the same applet with different image dimensions as parameters. Finally you need to create a merge applet and its alg-plugin to run on the 4th core. regards, Victor

Ticket Name: TDA4VM: TDA4VM OD(Jdetnet 768x320) green screen on EVB

Part Number: TDA4VM Other Parts Discussed in Thread: TDA2, Hello, I tried testing JDetnet 768x320(TDA2 ssd) by run_app_tidl_avp.sh on TDA4VM , but it has green color on screen. The model output on PC via import tools(simulator) and the output value on TDA4V EVB looks good as below LOG(2.). I knew that it was related to 'kp_valid_ptr' in the tivxKernelODDrawDetectionsProcess (Vx_od_draw_detections_target.c) if((pPSpots->score >= params->viz_th) && (kp_valid_ptr[i] == 1) && (data_ptr_1 != 0x0) && (data_ptr_2 != 0x0)) { drawPoints(params, data_ptr_1, data_ptr_2, &kp_ptr[i*total_points_per_box*2],total_points_per_box, pPSpots->label); } It is '0', when EVB print log of the val for debugging the problem. could you explain the value in detail ? could you recommend on how the green screen issue resolve? The cfg file is as below. 1. PSDK: 6.1.0 cfg file in_size 1280 720 od_size 768 320 viz_th 0.4 0.2 enable_psd 0 enable_vd 1 enable_sem_seg 0 2. printf LOG [C6x_1 ] 96.427864 s: KHDBG: KernelODDrawProcess +++++++++ [C6x_1 ] 96.427926 s: NumObj[ 4] ObjInfoSize[28] Offset[16] !! [C6x_1 ] 96.427973 s: >>> L[2.0] S[0.359] viz_th[0.200] kp_valid_ptr[0], data_ptr_1[bddc0000], data_ptr_2[bde00000] [C6x_1 ] 96.428017 s: >>> L[2.0] S[0.334] viz_th[0.200] kp_valid_ptr[0], data_ptr_1[bddc0000], data_ptr_2[bde00000] [C6x_1 ] 96.428061 s: >>> L[2.0] S[0.229] viz_th[0.200] kp_valid_ptr[0], data_ptr_1[bddc0000], data_ptr_2[bde00000] [C6x_1 ] 96.428105 s: >>> L[2.0] S[0.229] viz_th[0.200] kp_valid_ptr[1], data_ptr_1[bddc0000], data_ptr_2[bde00000] [C6x_1 ] 96.428134 s: KHDBG: KernelODDrawProcess --------- [C6x_1 ] 96.458682 s: KHDBG: KernelODDrawProcess +++++++++ [C6x_1 ] 96.458728 s: NumObj[ 3] ObjInfoSize[28] Offset[16] !! [C6x_1 ] 96.458770 s: >>> L[2.0] S[0.409] viz_th[0.200] kp_valid_ptr[0], data_ptr_1[bd560000], data_ptr_2[bd5a0000] [C6x_1 ] 96.458813 s: >>> L[2.0] S[0.261] viz_th[0.200] kp_valid_ptr[0], data_ptr_1[bd560000], data_ptr_2[bd5a0000] [C6x_1 ] 96.458857 s: >>> L[2.0] S[0.229] viz_th[0.200] kp_valid_ptr[0], data_ptr_1[bd560000], data_ptr_2[bd5a0000] [C6x_1 ] 96.458885 s: KHDBG: KernelODDrawProcess --------- [C6x_1 ] 96.489408 s: KHDBG: KernelODDrawProcess +++++++++ [C6x_1 ] 96.489454 s: NumObj[ 2] ObjInfoSize[28] Offset[16] !! [C6x_1 ] 96.489495 s: >>> L[2.0] S[0.373] viz_th[0.200] kp_valid_ptr[0], data_ptr_1[bddc0000], data_ptr_2[bde00000] [C6x_1 ] 96.489539 s: >>> L[2.0] S[0.366] viz_th[0.200] kp_valid_ptr[0], data_ptr_1[bddc0000], data_ptr_2[bde00000] [C6x_1 ] 96.489567 s: KHDBG: KernelODDrawProcess --------- [C6x_1 ] 96.519823 s: KHDBG: KernelODDrawProcess +++++++++ [C6x_1 ] 96.519869 s: NumObj[ 3] ObjInfoSize[28] Offset[16] !! [C6x_1 ] 96.519926 s: >>> L[2.0] S[0.584] viz_th[0.200] kp_valid_ptr[0], data_ptr_1[bd560000], data_ptr_2[bd5a0000] [C6x_1 ] 96.519977 s: >>> L[2.0] S[0.229] viz_th[0.200] kp_valid_ptr[0], data_ptr_1[bd560000], data_ptr_2[bd5a0000] [C6x_1 ] 96.520022 s: >>> L[2.0] S[0.229] viz_th[0.200] kp_valid_ptr[1], data_ptr_1[bd560000], data_ptr_2[bd5a0000] [C6x_1 ] 96.520053 s: KHDBG: KernelODDrawProcess --------- BR, Khethan

Khethan, The AVP Demo is trained for fish-eye images and not rectilinear images, we have added an example to perform simple object detection on rectiliner images. This demo will be available publicly by May 2020 but if you need it before that, you will need to have a CDDS account where I can share the new demos. As the AVP demo works on fish-eye images, the parking sport is trapezoidal in nature. So a rectangle co-ordinates of (xmin, ymin) (xmax, ymax) does not apply. So we identify what is called as key-points, basically points at the four corners of the parking lot and then do some post-processing to interpolate the points and draw lines on a fish eye-image. If you are doing simple object detection, you will be unable to use this demo out-of-the-box. I am not sure why you are observing a green screen, its possible that you are not selecting the right input in Mosaic Node. When you disable PSD and segmentation, the Mosaic input list gets changed and the logic to select the inputs need to be updated. Regards, Shyam

Hello Shyam, Thanks for you quick reply. I understand what you say and will be able to resolve the problem. I have CDDS account, so could you please share the new example demos ? BR, Khethan

Ticket Name: TDA2: TI DL : Support for SSD on EVE for TDA2x

Part Number: TDA2 Hi.. Currently the latest release is TIDL.01.00.00.00 . Does this support SSD(Single Shot MultiBox Detector) now? Regards Shashi

No. TIDL.01.01.00.00 will support Caffe based SSD. TIDL.01.01.00.00 will be available via SDK release by April 6 Regards, Kumar.D

I Interpret this as TIDL.01.01.00.00 doesnot support Caffe based SSD.

Current release TIDL.01.00.00.00 does not support Caffe based SSD Next release TIDL.01.01.00.00 will support Caffe based SSD

Ticket Name: Linker command files for CCS

Other Parts Discussed in Thread: TDA2 Hello, I am using CCS v6.2 to check simple program for each core on TDA2 Vayu EVM. However, CCS project (Selected “Empty project w/ main.c”) does not provide linker command files. How can I get the command files for A15, C66 and M4? Best regards, Kenshow

Hello Kenshow, Try the attached one. You may include it in <CCS install folder>\ccsv6\ccs_base\c6000\include. TDA2x_C66.cmd Hope it helps, thanks, Alex

Hi Alex, Thanks for C66x command file. Also, I would like to need command files of A15 (gcc base) and M4. Can I get them? Best regards, Kenshow

Sure, attached. TDA2x.lds TDA2x_CM4.cmd Thanks, Alex

Hi Alex, Thank you very much for useful files. I 'll be able to check my programs on each cores. Best regards, Kenshow

Ticket Name: TDA3XEVM: Import OpenCV algorithm on TDA3X EVM

Part Number: TDA3XEVM Hello all, I have an algorithm implemented in openCV and I want to import it on TDA3X EVM? . and can you also tell me also if TDA3X support importing algorithms from Tensor flow, Thanks in advance

Please refer EVE SW package documentation in the SDK for computer vision-related function and integration of the same in the system. For TensorFlow - ref the TIDL (Deep learning library SW) documentation.

Hello Kumar, For openCV , you refer me to "EVE SW package documentation" , but unfortunately I can't find it , also I try to use this use case <vip_single_cam_opencvcanny> , I assign Alg_OpennCVCanny to DSP1 instead of APU as TDA3X EVM don't have APU. When I try to build the use case the following error appears. Error: Link [Alg_OpenCVCanny] cannot be assigned to CPU [DSP1] (Valid CPUs:[A15]) !!! Shall I able to import such algorithm on TDA3x ? thanks in advance

EVE SW documantion can be found in the below ti_components/algorithms/eve_sw_01_19_00_00/eve_sw_releasenotes.pdf

Hello Kumar, Thank you kumar for your illustration , but my question is that openCV library is supported on TDA3x or not.

No Opencv is not supported in TDA3x

Does opencv supported on TDA2XX? I want to created a new Link by opencv.

Hello dolpy, I think you can use OpenCv on TDA2x ,I think you shall only follow points 1.3 & 1.4 in this document. file:///C:/PROCESSOR_SDK_VISION_03_05_00_00/vision_sdk/docs/FeatureSpecificUserGuides/VisionSDK_UserGuide_opencx.pdf

Thanks

Ticket Name: DRA74: TDP of DRA74

Part Number: DRA74 For the TDP on DRA74 or TDA2 If we already have the power consumption of the chip, how do we get the TDP value? What is the conversion efficiency between the two? We downloaded the model data of TDA2 on the official website as follows, can the Power(W) value of 2.568 be fixed? Should we fill in the power consumption or TDP?

waiting

Feng, The thermal design power estimate should be based on a realistic load for your application running on the SoC, generally considering a run-time in the 'minutes' range. You should contact your local TI representative to fill out a "resource loading" for your application, and we can use that to provide a power estimate. Is that how you got the 2.568W number that you quote? Regards, Kyle

Hi Kyle 2.568W is a default value in the thermal simulation model of the official website. We have already filled in the "resource loading" you mentioned. According to the basic principle of the circuit, power (P) = current (A) × voltage (V).we calculate that the total power (P) is 15W. But you know, thermal design power (TDP) is not the same as power (P). TDP refers to the thermal effect of CPU current and other forms of heat. We want to know the TDP value for the thermal design.

Feng, We do not specify a single TDP value for the SoC. You are right that 15W is almost certainly too high of a power estimate to make sense for thermal analysis. In general, the Resource Loading (and resulting power estimate) can be populated with different analysis types in mind. From a PMIC capacity perspective, the load on any given processor(s) and domain(s) whether concurrent or serialized must be met by the PMIC so in this case configuring all cores active with relatively high load may make sense. From a thermal analysis perspective, a different approach should be followed. There is no single right answer. You can either reduce the utilization for each core to a value that makes sense over an extended period of time (minutes). Or you can define multiple resource loadings representing different time slices of activity for the SoC (1 second high activity, 5 second moderate activity 10 second idle, repeat...). This must be done with a knowledge of the application, and can't simply be derated based on a TDP value. Regards, Kyle