Abstract
Abstract: This paper proposes wideband low-power low-jitter self-biased phase-locked loop (SBPLL) for multi-rate serial link transmitter application. It adopts a proposed low-power source-degeneration voltage-to-current converter not only to save power but also to reduce the phase noise contributed by the voltage-to-current converter. The proposed SBPLL is implemented in a 65-nm CMOS process, and the active core area is 0.01 mm 2 . Measurement result shows that the SBPLL can generate clock with frequency from 1.25 to 6.25 GHz and the loop bandwidth can be kept around 20 MHz regardless of the output frequency. The rms jitter integrated from 10 kHz to 300 MHz is 780 fs at carrier frequency of 6.25 GHz and maximum power efficiency is 0.496 mW/GHz with 1.2-V supply. The figure-of-merit (FOM) is −237.2 dB. The measurement results also show good robustness of the SBPLL over temperature and supply voltage variation.
Introduction
The multi-rate serial link data transmitter (MRTX) [1, 2] is attractive in industry because it is compatible for both new link standards and legacy systems. In the MRTX, the wideband low-jitter phase-locked loop (PLL) is one of the most critical building blocks. Usually the LC voltage controlled oscillator (LC-VCO) based PLLs [3] are used in the MRTX, but the high-Q inductor and the digital controlled switched capacitor array in the LC-VCO occupy large area. The ring oscillator (RO) based PLLs [4, 5] are attractive due to the small area and the wide frequency tuning range. But the RO often has poor phase noise. To suppress the phase noise of RO and thus achieve low rms jitter, wide loop bandwidth is necessary. In ref.
[6] the loop bandwidth of the ROPLL for transmitter was set to be higher than 25 MHz (estimated from the phase noise curve) so that it can achieve 414 fs rms jitter at 10-GHz clock frequency. However, the wider the loop bandwidth, the less stable the PLL will be over process, voltage and temperature (PVT) variation. In addition, it need manually adjust the current of the charge pump to keep the loop stable over wide covered frequency range. The RO based PLLs with self-bandwidth control techniques [7, 8, 9 ] are attractive to solve these problems. The loop bandwidth can be kept relatively constant over wide frequency cover range and PVT variation. So the loop bandwidth can be set sufficiently high to suppress the phase noise of RO and thus achieve low-jitter performance without the issue of stability due to the PVT variation. However, the bias generation circuits in [7] occupy much area. Although the self-biased PLL (SBPLL) without any bias circuit [8] was proposed, the operational amplifier (OPAMP) in the voltage-to-current (VI) converter consumes much power, especially when the loop bandwidth is large [9] . The SBPLL with source-degeneration VI (SDVI) was proposed to omit OPAMP in the VI and thus save power and area [9] , but the bias branch in the SDVI still consumes much power.
In this paper, we propose a low-power low-jitter wideband RO based SBPLL. It adopts a proposed low-power SDVI (LPSDVI) to remove the bias branch in the conventional SDVI [9] . Therefore the power consumption and phase noise contributed from the VI can be reduced effectively. The rest of this paper is organized as follows. The architecture of the proposed SBPLL is presented in section 2. Section 3 presents the proposed SDVI and other blocks are shown in section 4. Section 5 shows the measurement results of the proposed SBPLL and the conclusion are given in section 6.
2 Architecture of the proposed SBPLL Fig. 1 shows the architecture of the proposed wideband SBPLL. It can generate differential clock with frequency range from 1.25 GHz to 6.25 GHz. So the SBPLL can be used for the half-rate MRTX with date rate range from 2.5 Gb/s to 12.5 Gb/s. The SBPLL consists of a proposed LPSDVI, a phase/frequency detector (PFD), a self-biased charge pump (SBCP), a loop filter (LPF), a start-up circuit, a ring current controlled oscillator (RCCO), a differential-to-single-ended converter (D2S), a multi-modules divider (MMD), a clock buffer (CLKBUF) and a output buffer (OUTBUF). The CLKBUF is used to drive the MRTX and the OUTBUF is implemented for testing purpose. By removing the bias branch in the conventional SDVI [9], the LPSDVI can save power consumption and reduce the phase noise contributed from the VI. The detailed analysis of the LPSDVI is shown in section 3. The reference clock frequency is set to be 312.5 MHz and the loop bandwidth is set to be about 20 MHz, which is wide enough to suppress the phase noise from RCCO and thus achieve low-jitter performance. The bias current of SBCP is proportional to the control current of RCCO to achieve constant loop bandwidth. B is the ratio of width to length ratio between M1 and M2 and the ratio of resistance between R3 and R2. The start-up circuit proposed in our prior work [9] is used in this SBPLL to make the RCCO oscillate when the SBPLL is powered up.
Similar to the analysis method in [8, 9] , the loop bandwidth can be expressed as
where f REF is the reference frequency and B, R1 and R2 are shown in Fig. 1 . As equation (1) shows, the loop bandwidth can be kept relatively constant regardless of output frequency and PVT variation.
Proposed SDVI
In this section we introduce the proposed LPSDVI circuit first and then show its advantages by making performance comparison between the LPSDVI and the conventional SDVI [9] . Fig. 2(a) shows the detailed schematic of the SDVI circuit. Compared with the conventional SDVI shown in Fig. 2(b) , the bias branch is removed so that power consumption can be saved. The LPSDVI has two current branches, I C branch and I B CP branch. I C is the control current of RCCO and I B CP is the biased current of SBCP. The number of VI cell in I C branch is set to be B to make the ratio between I C and I B CP be B, as shown in Fig. 2(a) . The deep n-well (DNW) NMOS transistor is adopted to connect the source and drain together and thus avoid the body effect. Fig. 2(a) and (b) also show the noise model of the LPSDVI and the conventional SDVI, respectively. The noise of control current in the LPSDVI can be expressed as
where g m1 is the transconductance of M1 shown in Fig. 1 and N is the thermal noise parameter of NMOS. The noise of control current in conventional SDVI can be expressed as
where g m1 , g m2 and g m3 is the transconductance of M1, M2 and M3 shown in Fig. 2 (b) respectively and P is the thermal noise parameter of PMOS. Compare equation (2) with (3), we can get that the LPSDVI has less noise source and thus can achieve lower noise of control current with lower power consumption. Fig. 3(a) gives the simulated phase noise of RCCO with the LPSDVI and conventional SDVI, respectively. The C shown in Fig. 2 (b) in this simulation is set to be 1. It shows that the LPSDVI can reduce the phase noise contributed from the voltage-to-current converter. Fig. 3(b) also gives the simulated power consumption of the LPSDVI and conventional SDVI, respectively. The two VIs are connected to the same RCCO for fair comparison and the C is also set to be 1. It indicates that nearly half power consumption of the VI can be saved. If we increase the value of C, the power consumption of conventional SDVI can be reduced. However, as equations (3) shows, the current noise will be increased. So the phase noise induced from VI will also be increased.
In summary, the LPSDVI can not only reduce the phase noise induced from the VI but also reduce the power of the SBPLL. So the LPSDVI is suitable for lowpower low-jitter wideband SBPLL design. Fig. 4(a) shows the schematic of the RCCO. The two-stage structure is adopted to save power and area. The delay cell includes two main inverters (INV1 and INV2) and two cross-coupled inverters (INV3 and INV4) . The cross-couple inverters are adopted not only to speed up the signal transition at the output of each delay cell but also to guarantee oscillation condition [6] . Fig. 4(b) shows the post-layout simulation result of the tuning curve of the RCCO at different PVT corners. The RCCO and the LPSDVI are connected together and the tuning range is simulated by sweeping the input voltage V C of the LPSDVI. It shows that the RCCO can cover the frequency range from 1.25 GHz to 6.25 GHz at different PVT corners.
Design of other building blocks in the SBPLL
The schematic of the CLKBUF is shown in Fig. 5(a) . It includes two stages. The first stage is implemented with the AC-coupled resistive feedback buffer [6] to avoid the duty-cycle distortion. The second stage is an inverter to drive the MRTX. The metal-oxide-metal (MOM) capacitor is adopted in the first stage of CLKBUF to save area. The D2S shown in Fig. 5(b) is used to convert the RCCO output into the single-ended full-swing clock to drive the MMD. Post-layout simulation shows the power consumption of CLKBUF and D2S at maximum output frequency (6.25 GHz) is 190 µW and 60 µW, respectively.
The CP proposed in our prior work [10] is adopted not only to achieve fast switching speed, low-power consumption and good current matching but also to suppress the reverse leakage. The PFD and MMD are implemented in the trulysingle-phase clock (TSPC) logic circuits to save power consumption [9] . The capacitor of LPF is implemented with stacked MOS capacitor, MOM capacitor and metal-isolator-metal (MIM) capacitor to achieve large capacitance with small area.
Implementation and measurement results
The proposed SBPLL was implemented in 65 nm CMOS process. The core area (exclude the OUTBUF for testing purpose) is 0.01 mm 2 , as shown in Fig. 6(a) . The supply voltage is 1.2 V. The maximum power consumption is 3.1 mW including the CLKBUF but excluding the OUTBUF for testing purpose. The breakdown of the power consumption is shown in Fig. 6(b) . The measurement results show the PLL can generate frequency range from 1.25 GHz to 6.25 GHz. Fig. 7(a) shows the phase noise at carrier frequency of 6.25 GHz, 4.375 GHz and 2.5 GHz, respectively. It shows that the loop bandwidth is around 20 MHz regardless of output frequency. Fig. 7(b) shows the spectrum at carrier frequency of 6.25 GHz. The reference spur is −59.2 dBc. The maximum power efficiency is 0.496 mW/GHz at carrier frequency of 6.25 GHz. The measured rms jitter integrated from 10 kHz to 100 MHz at carrier frequency of 6.25 GHz, 4.37 GHz and 2.5 GHz is 0.78 ps, 1.11 ps and 2.58 ps, respectively. Fig. 8(a) and (b) show the rms jitter (int. 10 kHz∼300 MHz) over temperature and supply voltage variation. The rms jitter variation is less than 15% over temperature range from −20°C to 80°C. The rms jitter variation is less than 0.2 ps with a supply range from 1.1 to 1.3 V. Table I , our SBPLL shows the best power efficiency and it can operate robustly with the widest supply and temperature range. The figure-of-merit (FOM) is also better than most of the works listed in Table I . Although the PLL in ref.
[6] achieves the best FOM in Table I , it need manually adjust the coarse control current of RCCO and the current of CP, which is not PVT tolerable and not suitable for wideband clock generation.
Conclusion
A wideband low-power low-jitter 1.25-to-6.25 GHz SBPLL was proposed and implemented in 65 nm CMOS process. The low-power source-degeneration voltage-to-current converter was adopted not only to save power but also to reduce the phase noise contributed from VI. The measured loop bandwidth can be kept around 20 MHz. The rms jitter integrated from 10 kHz to 300 MHz at a carrier frequency of 6.25 GHz is 0.78 ps and the FOM is −237.2 dB. The maximum power efficiency is 0.496 mW/GHz and core area is 0.01 mm 2 . Measurement also shows robustness over temperature and supply voltage variation.
Acknowledgments
This work was supported by National Nature Science Foundation of China under grants 61306027, 61331003, and 61474108 and Beijing Nature Science Foundation under grants 4152051. 

{'paper_id': '10807863', 'title': 'A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter', 's2_url': 'https://api.semanticscholar.org/CorpusID:10807863', 'source': 'S2ORC'}