Abstract
Abstract. Digital pulse width modulation (DPWM) has advantages of strong anti-interference ability, high efficiency and good flexibility, therefore it has been widely used in switching power supply, communications, power control and transform and other fields. This paper proposed a high resolution DPWM control circuit based on field programmable gate array (FPGA), which solved the problem of low resolution and instability of the traditional DPWM control circuit. The principle of the proposed circuit is presented in this paper, and the circuit has been successfully implemented on the Xilinx Artix-7 FPGA development board. The experiment shows that, when the frequency of the circuit is 50 MHz, the resolution of DPWM can reach 78ps, and the proposed DPWM control circuit has wide application prospects.
Introduction
Due to the wide application of digital control circuit in power electronics, an improved high resolution digital pulse width modulator (DPWM) control circuit is described. In recent years, DPWM has been widely used in many power converters. The resolution of DPWM is the main factor affecting the accuracy in the output voltage/current control which determines the performance of the power converter [1, 2] .
Compared with the analog control technology, digital control technology of pulse width modulator has many advantages, such as strong program capability and advanced control algorithm. So, the pulse width modulator realized by the digital control circuit is studied. The proposed DPWM control circuit is made up of clock generation circuit, synchronous pulse generation circuit, I/O delay element (IODELAYE) delay circuit and OR gating circuit.
In order to obtain DPWM with high resolution, some experts present several design schemes based on FPGA, which generally have the following structures: counter-based DPWM, delay chain based DPWM, a dithering approach or hybrid DPWM [3] . The first three structures have their own defects, so the advanced DPWM usually adopts the hybrid structure design [4] . At the same time, the advanced DPWM mentioned before are mostly based on structure of counter, comparator and RS latch. However, these structures have low resolutions and of poor stability, so we propose an improved high resolution DPWM control circuit based on FPGA.
The Structure of DPWM Control Circuit
Figure1 shows the structure of DPWM control circuit. It is composed of the clock generation circuit, the synchronous pulse width generation circuit, the IODELAYE delay circuit and the OR gating circuit. The process can be depicted as follows. The clock generation circuit generates the internal clock signal CK which is applied to the synchronous pulse width generation circuit and IODELAYE delay circuit, respectively; synchronous pulse width generation circuit outputs the rising signal R, before being used as input signal of the IODELAYE delay circuit and OR gating circuit; the IODELAYE delay circuit delays the rising signal R to obtain the falling signal F which is input to the OR gating circuit; the rising signal R and the falling signal F are input to the OR gating circuit which outputs the signal of the DPWM.
The Principle of High-Resolution DPWM
This section explains the principle of the synchronous pulse width generation circuit, the OR gating circuit, the clock generation circuit and the IODELAYE delay circuit in detail.
The Principle of DPWM
The IODELAYE tap resolution is given by ( ) The RS latch in the advanced DPWM is easy to impact on timing and always affected by the temperature, so the function is not stable [1] . As a result, this new DPWM control circuit uses the OR gate to realize the function of RS latch, making the DPWM more stable. At the same time, the synchronous pulse width generation circuit is used to work with the OR gating circuit. The rising edge of the signal R in the OR gating circuit determines the rising edge of the DPWM signal, and the falling edge of the signal F determines the falling edge of the DPWM.
The Principle of the Proposed DPWM Structure
The synchronous pulse width generation circuit is composed of a pulse width generator and a D flip-flop shown in Figure2. Traditional pulse width generator is realized by the counter and the comparator. Its width is equal to the period of clock. In this paper, we propose a new synchronous pulse width generation circuit based on pulse width generator to work with the OR gating circuit. The synchronous pulse width generation circuit controls the width of the rising signal R by the input signal dc (10:5) (see Figure3). Thus the DPWM is more stable and reliable. According to the Artix-7 Xilinx data sheet, IODELAYE module has three diverse working modes which are shown as follows:
(1) Fixed delay mode: the number of delay taps is configured by block attributes. 
In this paper, we adopt the third working mode, namely, the loadable variable mode.
The Operation of the Proposed DPWM
In the operation of the proposed DPWM, the input duty cycle command dc(10:0)="00010010011" is 11 bits. The 6 high bits "000100" are the most significant bits (MSBs) used as the control word of the synchronous pulse width generation circuit. Thus, the dc (4:0) decides the delay of the rising signal R and the pulse width of the rising signal R is equal to an integer clock cycle T. The OR gating circuit delays a decimal clock cycle T based on the rising signal R. The output DPWM of the OR gating circuit shows that the rising edge of the signal R determines the rising edge of DPWM, and the falling edge of the signal F determines the falling edge of DPWM.
Program Implementation of High-Resolution DPWM Architecture
This section draws the implementation of DPWM based on FPGA. The DPWM control circuit is implemented on the Xilinx Artix-7 development board. This development board contains a 50MHz clock oscillator used as the input clock. The output of Xilinx Artix-7 development board is connected to the oscilloscope (4GHz, 20GSa/s) as shown in Figure7. Meanwhile, the waveforms can also be observed on an oscilloscope screen. Figure8(a) and (b) present the experimental results of DPWM for the different least significant bits from "000000" to "11111". The horizontal axis represents different LSBs, while the vertical axis represents the pulse width and pulse width increment of DPWM, respectively. The Figure8 (a) shows a monotonic behavior and a stable on-time step, and in the Figure8 (b), the fluctuates around 78ps. Analyzing the results of the experiment reveals that the resolution of the DPWM control circuit is 78ps and the circuit is stable. The proposed structure is feasible.
Figure9 shows three different pulses when the LSBs are "00000","01110" and "11100"on the oscilloscope. 
Conclusion
This paper proposes an improved implementation based on FPGA to realize the DPWM. The proposed DPWM control circuit has been implemented on a Xilinx Artix-7 FPGA. This improved method makes the DPWM signal more stable. In conclusion, the experimental results show a resolution of 78ps for the DPWM control circuit, certifying the feasibility of the proposal.

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