Struct st8b7c:f320:99b9:690f:4595:cd17:293a:c069sim8b7c:f320:99b9:690f:4595:cd17:293a:c069Simd #[repr(simd)]pub struct Simd<T, const LANES: usize>(_)where T: SimdElement, LaneCount<LANES>: SupportedLaneCount; 🔬This is a nightly-only experimental API. (portable_simd #86656) A SIMD vector of LANES elements of type T. Simd<T, N> has the same shape as [T; N], but operates like T. Two vectors of the same type and length will, by convention, support the operators (+, *, etc.) that T does. These take the lanes at each index on the left-hand side and right-hand side, perform the operation, and return the result in the same lane in a vector of equal size. For a given operator, this is equivalent to zipping the two arrays together and mapping the operator over each lane. let a0: [i32; 4] = [-2, 0, 2, 4]; let a1 = [10, 9, 8, 7]; let zm_add = a0.zip(a1).map(|(lhs, rhs)| lhs + rhs); let zm_mul = a0.zip(a1).map(|(lhs, rhs)| lhs * rhs); // `Simd<T, N>` implements `From<[T; N]> let (v0, v1) = (Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from(a0), Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from(a1)); // Which means arrays implement `Into<Simd<T, N>>`. assert_eq!(v0 + v1, zm_add.into()); assert_eq!(v0 * v1, zm_mul.into()); Simd with integers has the quirk that these operations are also inherently wrapping, as if T was Wrapping<T>. Thus, Simd does not implement wrapping_add, because that is the default behavior. This means there is no warning on overflows, even in “debug” builds. For most applications where Simd is appropriate, it is “not a bug” to wrap, and even “debug builds” are unlikely to tolerate the loss of performance. You may want to consider using explicitly checked arithmetic if such is required. Division by zero still causes a panic, so you may want to consider using floating point numbers if that is unacceptable. Layout Simd<T, N> has a layout similar to [T; N] (identical “shapes”), but with a greater alignment. [T; N] is aligned to T, but Simd<T, N> will have an alignment based on both T and N. It is thus sound to transmute Simd<T, N> to [T; N], and will typically optimize to zero cost, but the reverse transmutation is more likely to require a copy the compiler cannot simply elide. ABI “Features” Due to Rust’s safety guarantees, Simd<T, N> is currently passed to and from functions via memory, not SIMD registers, except as an optimization. #[inline] hints are recommended on functions that accept Simd<T, N> or return it. The need for this may be corrected in the future. Safe SIMD with Unsafe Rust Operations with Simd are typically safe, but there are many reasons to want to combine SIMD with unsafe code. Care must be taken to respect differences between Simd and other types it may be transformed into or derived from. In particular, the layout of Simd<T, N> may be similar to [T; N], and may allow some transmutations, but references to [T; N] are not interchangeable with those to Simd<T, N>. Thus, when using unsafe Rust to read and write Simd<T, N> through raw pointers, it is a good idea to first try with read_unaligned and write_unaligned. This is because: read and write require full alignment (in this case, Simd<T, N>’s alignment) the likely source for reading or destination for writing Simd<T, N> is [T] and similar types, aligned to T combining these actions would violate the unsafe contract and explode the program into a puff of undefined behavior the compiler can implicitly adjust layouts to make unaligned reads or writes fully aligned if it sees the optimization most contemporary processors suffer no performance penalty for “unaligned” reads and writes that are aligned at runtime By imposing less obligations, unaligned functions are less likely to make the program unsound, and may be just as fast as stricter alternatives. When trying to guarantee alignment, [T]8b7c:f320:99b9:690f:4595:cd17:293a:c069s_simd is an option for converting [T] to [Simd<T, N>], and allows soundly operating on an aligned SIMD body, but it may cost more time when handling the scalar head and tail. If these are not sufficient, then it is most ideal to design data structures to be already aligned to the Simd<T, N> you wish to use before using unsafe Rust to read or write. More conventional ways to compensate for these facts, like materializing Simd to or from an array first, are handled by safe methods like Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array and Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_slice. Implementations sourceimpl<T, const LANES: usize> Simd<T, LANES>where T: SimdElement, LaneCount<LANES>: SupportedLaneCount, sourcepub fn reverse(self) -> Simd<T, LANES> 🔬This is a nightly-only experimental API. (portable_simd #86656) Reverse the order of the lanes in the vector. sourcepub fn rotate_lanes_left<const OFFSET: usize>(self) -> Simd<T, LANES> 🔬This is a nightly-only experimental API. (portable_simd #86656) Rotates the vector such that the first OFFSET elements of the slice move to the end while the last LANES - OFFSET elements move to the front. After calling rotate_lanes_left, the element previously in lane OFFSET will become the first element in the slice. sourcepub fn rotate_lanes_right<const OFFSET: usize>(self) -> Simd<T, LANES> 🔬This is a nightly-only experimental API. (portable_simd #86656) Rotates the vector such that the first LANES - OFFSET elements of the vector move to the end while the last OFFSET elements move to the front. After calling rotate_lanes_right, the element previously at index LANES - OFFSET will become the first element in the slice. sourcepub fn interleave( self, other: Simd<T, LANES>) -> (Simd<T, LANES>, Simd<T, LANES>) 🔬This is a nightly-only experimental API. (portable_simd #86656) Interleave two vectors. Produces two vectors with lanes taken alternately from self and other. The first result contains the first LANES / 2 lanes from self and other, alternating, starting with the first lane of self. The second result contains the last LANES / 2 lanes from self and other, alternating, starting with the lane LANES / 2 from the start of self. #![feature(portable_simd)] let a = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([0, 1, 2, 3]); let b = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([4, 5, 6, 7]); let (x, y) = a.interleave(b); assert_eq!(x.to_array(), [0, 4, 1, 5]); assert_eq!(y.to_array(), [2, 6, 3, 7]); sourcepub fn deinterleave( self, other: Simd<T, LANES>) -> (Simd<T, LANES>, Simd<T, LANES>) 🔬This is a nightly-only experimental API. (portable_simd #86656) Deinterleave two vectors. The first result takes every other lane of self and then other, starting with the first lane. The second result takes every other lane of self and then other, starting with the second lane. #![feature(portable_simd)] let a = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([0, 4, 1, 5]); let b = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([2, 6, 3, 7]); let (x, y) = a.deinterleave(b); assert_eq!(x.to_array(), [0, 1, 2, 3]); assert_eq!(y.to_array(), [4, 5, 6, 7]); sourceimpl<T, const LANES: usize> Simd<T, LANES>where T: SimdElement, LaneCount<LANES>: SupportedLaneCount, sourcepub const LANES: usize = LANES 🔬This is a nightly-only experimental API. (portable_simd #86656) Number of lanes in this vector. sourcepub const fn lanes(&self) -> usize 🔬This is a nightly-only experimental API. (portable_simd #86656) Returns the number of lanes in this SIMD vector. Examples let v = u32x8b7c:f320:99b9:690f:4595:cd17:293a:c069splat(0); assert_eq!(v.lanes(), 4); sourcepub fn splat(value: T) -> Simd<T, LANES> 🔬This is a nightly-only experimental API. (portable_simd #86656) Constructs a new SIMD vector with all lanes set to the given value. Examples let v = u32x8b7c:f320:99b9:690f:4595:cd17:293a:c069splat(8); assert_eq!(v.as_array(), &[8, 8, 8, 8]); sourcepub const fn as_array(&self) -> &[T; LANES] 🔬This is a nightly-only experimental API. (portable_simd #86656) Returns an array reference containing the entire SIMD vector. Examples let v: u64x4 = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([0, 1, 2, 3]); assert_eq!(v.as_array(), &[0, 1, 2, 3]); sourcepub fn as_mut_array(&mut self) -> &mut [T; LANES] 🔬This is a nightly-only experimental API. (portable_simd #86656) Returns a mutable array reference containing the entire SIMD vector. sourcepub const fn from_array(array: [T; LANES]) -> Simd<T, LANES> 🔬This is a nightly-only experimental API. (portable_simd #86656) Converts an array to a SIMD vector. sourcepub const fn to_array(self) -> [T; LANES] 🔬This is a nightly-only experimental API. (portable_simd #86656) Converts a SIMD vector to an array. sourcepub const fn from_slice(slice: &[T]) -> Simd<T, LANES> 🔬This is a nightly-only experimental API. (portable_simd #86656) Converts a slice to a SIMD vector containing slice[..LANES]. Panics Panics if the slice’s length is less than the vector’s Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069LANES. Examples let source = vec![1, 2, 3, 4, 5, 6]; let v = u32x8b7c:f320:99b9:690f:4595:cd17:293a:c069from_slice(&source); assert_eq!(v.as_array(), &[1, 2, 3, 4]); sourcepub fn cast<U>(self) -> Simd<U, LANES>where U: SimdElement, 🔬This is a nightly-only experimental API. (portable_simd #86656) Performs lanewise conversion of a SIMD vector’s elements to another SIMD-valid type. This follows the semantics of Rust’s as conversion for casting integers to unsigned integers (interpreting as the other type, so -1 to MAX), and from floats to integers (truncating, or saturating at the limits) for each lane, or vice versa. Examples let floats: Simd<f32, 4> = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([1.9, -4.5, 8b7c:f320:99b9:690f:4595:cd17:293a:c069INFINITY, 8b7c:f320:99b9:690f:4595:cd17:293a:c069NAN]); let ints = floats.cast8b7c:f320:99b9:690f:4595:cd17:293a:c069<i32>(); assert_eq!(ints, Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([1, -4, i8b7c:f320:99b9:690f:4595:cd17:293a:c069MAX, 0])); // Formally equivalent, but `Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069cast` can optimize better. assert_eq!(ints, Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array(floats.to_array().map(|x| x as i32))); // The float conversion does not round-trip. let floats_again = ints.cast(); assert_ne!(floats, floats_again); assert_eq!(floats_again, Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([1.0, -4.0, 442-315-3384.0, 0.0])); sourcepub unsafe fn to_int_unchecked<I>(self) -> Simd<I, LANES>where T: FloatToInt<I>, I: SimdElement, 🔬This is a nightly-only experimental API. (portable_simd #86656) Rounds toward zero and converts to the same-width integer type, assuming that the value is finite and fits in that type. Safety The value must: Not be NaN Not be infinite Be representable in the return type, after truncating off its fractional part If these requirements are infeasible or costly, consider using the safe function cast, which saturates on conversion. sourcepub fn gather_or( slice: &[T], idxs: Simd<usize, LANES>, or: Simd<T, LANES>) -> Simd<T, LANES> 🔬This is a nightly-only experimental API. (portable_simd #86656) Reads from potentially discontiguous indices in slice to construct a SIMD vector. If an index is out-of-bounds, the lane is instead selected from the or vector. Examples let vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18]; let idxs = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([9, 3, 0, 5]); let alt = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([-5, -4, -3, -2]); let result = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069gather_or(&vec, idxs, alt); // Note the lane that is out-of-bounds. assert_eq!(result, Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([-5, 13, 10, 15])); sourcepub fn gather_or_default(slice: &[T], idxs: Simd<usize, LANES>) -> Simd<T, LANES>where T: Default, 🔬This is a nightly-only experimental API. (portable_simd #86656) Reads from potentially discontiguous indices in slice to construct a SIMD vector. If an index is out-of-bounds, the lane is set to the default value for the type. Examples let vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18]; let idxs = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([9, 3, 0, 5]); let result = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069gather_or_default(&vec, idxs); // Note the lane that is out-of-bounds. assert_eq!(result, Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([0, 13, 10, 15])); sourcepub fn gather_select( slice: &[T], enable: Mask<isize, LANES>, idxs: Simd<usize, LANES>, or: Simd<T, LANES>) -> Simd<T, LANES> 🔬This is a nightly-only experimental API. (portable_simd #86656) Reads from potentially discontiguous indices in slice to construct a SIMD vector. The mask enables all true lanes and disables all false lanes. If an index is disabled or is out-of-bounds, the lane is selected from the or vector. Examples let vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18]; let idxs = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([9, 3, 0, 5]); let alt = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([-5, -4, -3, -2]); let enable = Mask8b7c:f320:99b9:690f:4595:cd17:293a:c069rom_array([true, true, true, false]); // Note the mask of the last lane. let result = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069gather_select(&vec, enable, idxs, alt); // Note the lane that is out-of-bounds. assert_eq!(result, Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([-5, 13, 10, -2])); sourcepub unsafe fn gather_select_unchecked( slice: &[T], enable: Mask<isize, LANES>, idxs: Simd<usize, LANES>, or: Simd<T, LANES>) -> Simd<T, LANES> 🔬This is a nightly-only experimental API. (portable_simd #86656) Reads from potentially discontiguous indices in slice to construct a SIMD vector. The mask enables all true lanes and disables all false lanes. If an index is disabled, the lane is selected from the or vector. Safety Calling this function with an enabled out-of-bounds index is undefined behavior even if the resulting value is not used. Examples let vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18]; let idxs = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([9, 3, 0, 5]); let alt = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([-5, -4, -3, -2]); let enable = Mask8b7c:f320:99b9:690f:4595:cd17:293a:c069rom_array([true, true, true, false]); // Note the final mask lane. // If this mask was used to gather, it would be unsound. Let's fix that. let enable = enable & idxs.simd_lt(Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069splat(vec.len())); // We have masked the OOB lane, so it's safe to gather now. let result = unsafe { Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069gather_select_unchecked(&vec, enable, idxs, alt) }; assert_eq!(result, Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([-5, 13, 10, -2])); sourcepub fn scatter(self, slice: &mut [T], idxs: Simd<usize, LANES>) 🔬This is a nightly-only experimental API. (portable_simd #86656) Writes the values in a SIMD vector to potentially discontiguous indices in slice. If two lanes in the scattered vector would write to the same index only the last lane is guaranteed to actually be written. Examples let mut vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18]; let idxs = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([9, 3, 0, 0]); let vals = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([-27, 82, -41, 124]); vals.scatter(&mut vec, idxs); // index 0 receives two writes. assert_eq!(vec, vec![124, 11, 12, 82, 14, 15, 16, 17, 18]); sourcepub fn scatter_select( self, slice: &mut [T], enable: Mask<isize, LANES>, idxs: Simd<usize, LANES>) 🔬This is a nightly-only experimental API. (portable_simd #86656) Writes the values in a SIMD vector to multiple potentially discontiguous indices in slice. The mask enables all true lanes and disables all false lanes. If an enabled index is out-of-bounds, the lane is not written. If two enabled lanes in the scattered vector would write to the same index, only the last lane is guaranteed to actually be written. Examples let mut vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18]; let idxs = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([9, 3, 0, 0]); let vals = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([-27, 82, -41, 124]); let enable = Mask8b7c:f320:99b9:690f:4595:cd17:293a:c069rom_array([true, true, true, false]); // Note the mask of the last lane. vals.scatter_select(&mut vec, enable, idxs); // index 0's second write is masked, thus omitted. assert_eq!(vec, vec![-41, 11, 12, 82, 14, 15, 16, 17, 18]); sourcepub unsafe fn scatter_select_unchecked( self, slice: &mut [T], enable: Mask<isize, LANES>, idxs: Simd<usize, LANES>) 🔬This is a nightly-only experimental API. (portable_simd #86656) Writes the values in a SIMD vector to multiple potentially discontiguous indices in slice. The mask enables all true lanes and disables all false lanes. If two enabled lanes in the scattered vector would write to the same index, only the last lane is guaranteed to actually be written. Safety Calling this function with an enabled out-of-bounds index is undefined behavior, and may lead to memory corruption. Examples let mut vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18]; let idxs = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([9, 3, 0, 0]); let vals = Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069from_array([-27, 82, -41, 124]); let enable = Mask8b7c:f320:99b9:690f:4595:cd17:293a:c069rom_array([true, true, true, false]); // Note the mask of the last lane. // If this mask was used to scatter, it would be unsound. Let's fix that. let enable = enable & idxs.simd_lt(Sim8b7c:f320:99b9:690f:4595:cd17:293a:c069splat(vec.len())); // We have masked the OOB lane, so it's safe to scatter now. unsafe { vals.scatter_select_unchecked(&mut vec, enable, idxs); } // index 0's second write is masked, thus was omitted. assert_eq!(vec, vec![-41, 11, 12, 82, 14, 15, 16, 17, 18]); Trait Implementations sourceimpl<'lhs, 'rhs, T, const LANES: usize> Add<&'rhs Simd<T, LANES>> for &'lhs Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Add<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Add<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the + operator. sourcefn add( self, rhs: &Simd<T, LANES>) -> <&'lhs Simd<T, LANES> as Add<&'rhs Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<T, const LANES: usize> Add<&Simd<T, LANES>> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Add<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Add<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the + operator. sourcefn add( self, rhs: &Simd<T, LANES>) -> <Simd<T, LANES> as Add<&Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<T, const LANES: usize> Add<Simd<T, LANES>> for &Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Add<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Add<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the + operator. sourcefn add( self, rhs: Simd<T, LANES>) -> <&Simd<T, LANES> as Add<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<f32, N>> for Simd<f32, N>where f32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<f32, N>The resulting type after applying the + operator. sourcefn add(self, rhs: Simd<f32, N>) -> <Simd<f32, N> as Add<Simd<f32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<f64, N>> for Simd<f64, N>where f64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<f64, N>The resulting type after applying the + operator. sourcefn add(self, rhs: Simd<f64, N>) -> <Simd<f64, N> as Add<Simd<f64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<i16, N>> for Simd<i16, N>where i16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i16, N>The resulting type after applying the + operator. sourcefn add(self, rhs: Simd<i16, N>) -> <Simd<i16, N> as Add<Simd<i16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<i32, N>> for Simd<i32, N>where i32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i32, N>The resulting type after applying the + operator. sourcefn add(self, rhs: Simd<i32, N>) -> <Simd<i32, N> as Add<Simd<i32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<i64, N>> for Simd<i64, N>where i64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i64, N>The resulting type after applying the + operator. sourcefn add(self, rhs: Simd<i64, N>) -> <Simd<i64, N> as Add<Simd<i64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<i8, N>> for Simd<i8, N>where i8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i8, N>The resulting type after applying the + operator. sourcefn add(self, rhs: Simd<i8, N>) -> <Simd<i8, N> as Add<Simd<i8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<isize, N>> for Simd<isize, N>where isize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<isize, N>The resulting type after applying the + operator. sourcefn add( self, rhs: Simd<isize, N>) -> <Simd<isize, N> as Add<Simd<isize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<u16, N>> for Simd<u16, N>where u16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u16, N>The resulting type after applying the + operator. sourcefn add(self, rhs: Simd<u16, N>) -> <Simd<u16, N> as Add<Simd<u16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<u32, N>> for Simd<u32, N>where u32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u32, N>The resulting type after applying the + operator. sourcefn add(self, rhs: Simd<u32, N>) -> <Simd<u32, N> as Add<Simd<u32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<u64, N>> for Simd<u64, N>where u64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u64, N>The resulting type after applying the + operator. sourcefn add(self, rhs: Simd<u64, N>) -> <Simd<u64, N> as Add<Simd<u64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<u8, N>> for Simd<u8, N>where u8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u8, N>The resulting type after applying the + operator. sourcefn add(self, rhs: Simd<u8, N>) -> <Simd<u8, N> as Add<Simd<u8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<const N: usize> Add<Simd<usize, N>> for Simd<usize, N>where usize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<usize, N>The resulting type after applying the + operator. sourcefn add( self, rhs: Simd<usize, N>) -> <Simd<usize, N> as Add<Simd<usize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the + operation. Read more sourceimpl<T, U, const LANES: usize> AddAssign<U> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Add<U>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Add<U>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, sourcefn add_assign(&mut self, rhs: U)Performs the += operation. Read more sourceimpl<T, const LANES: usize> AsMut<[T; LANES]> for Simd<T, LANES>where T: SimdElement, LaneCount<LANES>: SupportedLaneCount, sourcefn as_mut(&mut self) -> &mut [T; LANES]Converts this type into a mutable reference of the (usually inferred) input type. sourceimpl<T, const LANES: usize> AsMut<[T]> for Simd<T, LANES>where T: SimdElement, LaneCount<LANES>: SupportedLaneCount, sourcefn as_mut(&mut self) -> &mut [T]Notable traits for &[u8]impl Read for &[u8] impl Write for &mut [u8] Converts this type into a mutable reference of the (usually inferred) input type. sourceimpl<T, const LANES: usize> AsRef<[T; LANES]> for Simd<T, LANES>where T: SimdElement, LaneCount<LANES>: SupportedLaneCount, sourcefn as_ref(&self) -> &[T; LANES]Converts this type into a shared reference of the (usually inferred) input type. sourceimpl<T, const LANES: usize> AsRef<[T]> for Simd<T, LANES>where T: SimdElement, LaneCount<LANES>: SupportedLaneCount, sourcefn as_ref(&self) -> &[T]Notable traits for &[u8]impl Read for &[u8] impl Write for &mut [u8] Converts this type into a shared reference of the (usually inferred) input type. sourceimpl<T, const LANES: usize> Binary for Simd<T, LANES>where T: SimdElement + Binary, LaneCount<LANES>: SupportedLaneCount, sourcefn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>Formats the value using the given formatter. sourceimpl<'lhs, 'rhs, T, const LANES: usize> BitAnd<&'rhs Simd<T, LANES>> for &'lhs Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitAnd<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitAnd<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the & operator. sourcefn bitand( self, rhs: &Simd<T, LANES>) -> <&'lhs Simd<T, LANES> as BitAnd<&'rhs Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<T, const LANES: usize> BitAnd<&Simd<T, LANES>> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitAnd<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitAnd<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the & operator. sourcefn bitand( self, rhs: &Simd<T, LANES>) -> <Simd<T, LANES> as BitAnd<&Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<T, const LANES: usize> BitAnd<Simd<T, LANES>> for &Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitAnd<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitAnd<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the & operator. sourcefn bitand( self, rhs: Simd<T, LANES>) -> <&Simd<T, LANES> as BitAnd<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<const N: usize> BitAnd<Simd<i16, N>> for Simd<i16, N>where i16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i16, N>The resulting type after applying the & operator. sourcefn bitand( self, rhs: Simd<i16, N>) -> <Simd<i16, N> as BitAnd<Simd<i16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<const N: usize> BitAnd<Simd<i32, N>> for Simd<i32, N>where i32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i32, N>The resulting type after applying the & operator. sourcefn bitand( self, rhs: Simd<i32, N>) -> <Simd<i32, N> as BitAnd<Simd<i32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<const N: usize> BitAnd<Simd<i64, N>> for Simd<i64, N>where i64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i64, N>The resulting type after applying the & operator. sourcefn bitand( self, rhs: Simd<i64, N>) -> <Simd<i64, N> as BitAnd<Simd<i64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<const N: usize> BitAnd<Simd<i8, N>> for Simd<i8, N>where i8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i8, N>The resulting type after applying the & operator. sourcefn bitand(self, rhs: Simd<i8, N>) -> <Simd<i8, N> as BitAnd<Simd<i8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<const N: usize> BitAnd<Simd<isize, N>> for Simd<isize, N>where isize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<isize, N>The resulting type after applying the & operator. sourcefn bitand( self, rhs: Simd<isize, N>) -> <Simd<isize, N> as BitAnd<Simd<isize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<const N: usize> BitAnd<Simd<u16, N>> for Simd<u16, N>where u16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u16, N>The resulting type after applying the & operator. sourcefn bitand( self, rhs: Simd<u16, N>) -> <Simd<u16, N> as BitAnd<Simd<u16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<const N: usize> BitAnd<Simd<u32, N>> for Simd<u32, N>where u32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u32, N>The resulting type after applying the & operator. sourcefn bitand( self, rhs: Simd<u32, N>) -> <Simd<u32, N> as BitAnd<Simd<u32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<const N: usize> BitAnd<Simd<u64, N>> for Simd<u64, N>where u64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u64, N>The resulting type after applying the & operator. sourcefn bitand( self, rhs: Simd<u64, N>) -> <Simd<u64, N> as BitAnd<Simd<u64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<const N: usize> BitAnd<Simd<u8, N>> for Simd<u8, N>where u8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u8, N>The resulting type after applying the & operator. sourcefn bitand(self, rhs: Simd<u8, N>) -> <Simd<u8, N> as BitAnd<Simd<u8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<const N: usize> BitAnd<Simd<usize, N>> for Simd<usize, N>where usize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<usize, N>The resulting type after applying the & operator. sourcefn bitand( self, rhs: Simd<usize, N>) -> <Simd<usize, N> as BitAnd<Simd<usize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the & operation. Read more sourceimpl<T, U, const LANES: usize> BitAndAssign<U> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitAnd<U>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitAnd<U>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, sourcefn bitand_assign(&mut self, rhs: U)Performs the &= operation. Read more sourceimpl<'lhs, 'rhs, T, const LANES: usize> BitOr<&'rhs Simd<T, LANES>> for &'lhs Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitOr<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitOr<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the | operator. sourcefn bitor( self, rhs: &Simd<T, LANES>) -> <&'lhs Simd<T, LANES> as BitOr<&'rhs Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<T, const LANES: usize> BitOr<&Simd<T, LANES>> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitOr<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitOr<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the | operator. sourcefn bitor( self, rhs: &Simd<T, LANES>) -> <Simd<T, LANES> as BitOr<&Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<T, const LANES: usize> BitOr<Simd<T, LANES>> for &Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitOr<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitOr<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the | operator. sourcefn bitor( self, rhs: Simd<T, LANES>) -> <&Simd<T, LANES> as BitOr<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<const N: usize> BitOr<Simd<i16, N>> for Simd<i16, N>where i16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i16, N>The resulting type after applying the | operator. sourcefn bitor( self, rhs: Simd<i16, N>) -> <Simd<i16, N> as BitOr<Simd<i16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<const N: usize> BitOr<Simd<i32, N>> for Simd<i32, N>where i32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i32, N>The resulting type after applying the | operator. sourcefn bitor( self, rhs: Simd<i32, N>) -> <Simd<i32, N> as BitOr<Simd<i32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<const N: usize> BitOr<Simd<i64, N>> for Simd<i64, N>where i64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i64, N>The resulting type after applying the | operator. sourcefn bitor( self, rhs: Simd<i64, N>) -> <Simd<i64, N> as BitOr<Simd<i64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<const N: usize> BitOr<Simd<i8, N>> for Simd<i8, N>where i8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i8, N>The resulting type after applying the | operator. sourcefn bitor(self, rhs: Simd<i8, N>) -> <Simd<i8, N> as BitOr<Simd<i8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<const N: usize> BitOr<Simd<isize, N>> for Simd<isize, N>where isize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<isize, N>The resulting type after applying the | operator. sourcefn bitor( self, rhs: Simd<isize, N>) -> <Simd<isize, N> as BitOr<Simd<isize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<const N: usize> BitOr<Simd<u16, N>> for Simd<u16, N>where u16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u16, N>The resulting type after applying the | operator. sourcefn bitor( self, rhs: Simd<u16, N>) -> <Simd<u16, N> as BitOr<Simd<u16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<const N: usize> BitOr<Simd<u32, N>> for Simd<u32, N>where u32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u32, N>The resulting type after applying the | operator. sourcefn bitor( self, rhs: Simd<u32, N>) -> <Simd<u32, N> as BitOr<Simd<u32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<const N: usize> BitOr<Simd<u64, N>> for Simd<u64, N>where u64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u64, N>The resulting type after applying the | operator. sourcefn bitor( self, rhs: Simd<u64, N>) -> <Simd<u64, N> as BitOr<Simd<u64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<const N: usize> BitOr<Simd<u8, N>> for Simd<u8, N>where u8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u8, N>The resulting type after applying the | operator. sourcefn bitor(self, rhs: Simd<u8, N>) -> <Simd<u8, N> as BitOr<Simd<u8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<const N: usize> BitOr<Simd<usize, N>> for Simd<usize, N>where usize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<usize, N>The resulting type after applying the | operator. sourcefn bitor( self, rhs: Simd<usize, N>) -> <Simd<usize, N> as BitOr<Simd<usize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the | operation. Read more sourceimpl<T, U, const LANES: usize> BitOrAssign<U> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitOr<U>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitOr<U>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, sourcefn bitor_assign(&mut self, rhs: U)Performs the |= operation. Read more sourceimpl<'lhs, 'rhs, T, const LANES: usize> BitXor<&'rhs Simd<T, LANES>> for &'lhs Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitXor<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitXor<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the ^ operator. sourcefn bitxor( self, rhs: &Simd<T, LANES>) -> <&'lhs Simd<T, LANES> as BitXor<&'rhs Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<T, const LANES: usize> BitXor<&Simd<T, LANES>> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitXor<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitXor<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the ^ operator. sourcefn bitxor( self, rhs: &Simd<T, LANES>) -> <Simd<T, LANES> as BitXor<&Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<T, const LANES: usize> BitXor<Simd<T, LANES>> for &Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitXor<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitXor<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the ^ operator. sourcefn bitxor( self, rhs: Simd<T, LANES>) -> <&Simd<T, LANES> as BitXor<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<const N: usize> BitXor<Simd<i16, N>> for Simd<i16, N>where i16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i16, N>The resulting type after applying the ^ operator. sourcefn bitxor( self, rhs: Simd<i16, N>) -> <Simd<i16, N> as BitXor<Simd<i16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<const N: usize> BitXor<Simd<i32, N>> for Simd<i32, N>where i32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i32, N>The resulting type after applying the ^ operator. sourcefn bitxor( self, rhs: Simd<i32, N>) -> <Simd<i32, N> as BitXor<Simd<i32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<const N: usize> BitXor<Simd<i64, N>> for Simd<i64, N>where i64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i64, N>The resulting type after applying the ^ operator. sourcefn bitxor( self, rhs: Simd<i64, N>) -> <Simd<i64, N> as BitXor<Simd<i64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<const N: usize> BitXor<Simd<i8, N>> for Simd<i8, N>where i8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i8, N>The resulting type after applying the ^ operator. sourcefn bitxor(self, rhs: Simd<i8, N>) -> <Simd<i8, N> as BitXor<Simd<i8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<const N: usize> BitXor<Simd<isize, N>> for Simd<isize, N>where isize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<isize, N>The resulting type after applying the ^ operator. sourcefn bitxor( self, rhs: Simd<isize, N>) -> <Simd<isize, N> as BitXor<Simd<isize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<const N: usize> BitXor<Simd<u16, N>> for Simd<u16, N>where u16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u16, N>The resulting type after applying the ^ operator. sourcefn bitxor( self, rhs: Simd<u16, N>) -> <Simd<u16, N> as BitXor<Simd<u16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<const N: usize> BitXor<Simd<u32, N>> for Simd<u32, N>where u32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u32, N>The resulting type after applying the ^ operator. sourcefn bitxor( self, rhs: Simd<u32, N>) -> <Simd<u32, N> as BitXor<Simd<u32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<const N: usize> BitXor<Simd<u64, N>> for Simd<u64, N>where u64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u64, N>The resulting type after applying the ^ operator. sourcefn bitxor( self, rhs: Simd<u64, N>) -> <Simd<u64, N> as BitXor<Simd<u64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<const N: usize> BitXor<Simd<u8, N>> for Simd<u8, N>where u8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u8, N>The resulting type after applying the ^ operator. sourcefn bitxor(self, rhs: Simd<u8, N>) -> <Simd<u8, N> as BitXor<Simd<u8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<const N: usize> BitXor<Simd<usize, N>> for Simd<usize, N>where usize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<usize, N>The resulting type after applying the ^ operator. sourcefn bitxor( self, rhs: Simd<usize, N>) -> <Simd<usize, N> as BitXor<Simd<usize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the ^ operation. Read more sourceimpl<T, U, const LANES: usize> BitXorAssign<U> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: BitXor<U>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as BitXor<U>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, sourcefn bitxor_assign(&mut self, rhs: U)Performs the ^= operation. Read more sourceimpl<T, const LANES: usize> Clone for Simd<T, LANES>where T: SimdElement, LaneCount<LANES>: SupportedLaneCount, sourcefn clone(&self) -> Simd<T, LANES>Returns a copy of the value. Read more source1.0.0 · fn clone_from(&mut self, source: &Self)Performs copy-assignment from source. Read more sourceimpl<T, const LANES: usize> Debug for Simd<T, LANES>where T: SimdElement + Debug, LaneCount<LANES>: SupportedLaneCount, sourcefn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>Formats the value using the given formatter. Read more sourceimpl<T, const LANES: usize> Default for Simd<T, LANES>where T: SimdElement + Default, LaneCount<LANES>: SupportedLaneCount, sourcefn default() -> Simd<T, LANES>Returns the “default value” for a type. Read more sourceimpl<'lhs, 'rhs, T, const LANES: usize> Div<&'rhs Simd<T, LANES>> for &'lhs Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Div<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Div<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the / operator. sourcefn div( self, rhs: &Simd<T, LANES>) -> <&'lhs Simd<T, LANES> as Div<&'rhs Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<T, const LANES: usize> Div<&Simd<T, LANES>> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Div<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Div<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the / operator. sourcefn div( self, rhs: &Simd<T, LANES>) -> <Simd<T, LANES> as Div<&Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<T, const LANES: usize> Div<Simd<T, LANES>> for &Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Div<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Div<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the / operator. sourcefn div( self, rhs: Simd<T, LANES>) -> <&Simd<T, LANES> as Div<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<f32, N>> for Simd<f32, N>where f32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<f32, N>The resulting type after applying the / operator. sourcefn div(self, rhs: Simd<f32, N>) -> <Simd<f32, N> as Div<Simd<f32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<f64, N>> for Simd<f64, N>where f64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<f64, N>The resulting type after applying the / operator. sourcefn div(self, rhs: Simd<f64, N>) -> <Simd<f64, N> as Div<Simd<f64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<i16, N>> for Simd<i16, N>where i16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i16, N>The resulting type after applying the / operator. sourcefn div(self, rhs: Simd<i16, N>) -> <Simd<i16, N> as Div<Simd<i16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<i32, N>> for Simd<i32, N>where i32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i32, N>The resulting type after applying the / operator. sourcefn div(self, rhs: Simd<i32, N>) -> <Simd<i32, N> as Div<Simd<i32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<i64, N>> for Simd<i64, N>where i64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i64, N>The resulting type after applying the / operator. sourcefn div(self, rhs: Simd<i64, N>) -> <Simd<i64, N> as Div<Simd<i64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<i8, N>> for Simd<i8, N>where i8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i8, N>The resulting type after applying the / operator. sourcefn div(self, rhs: Simd<i8, N>) -> <Simd<i8, N> as Div<Simd<i8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<isize, N>> for Simd<isize, N>where isize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<isize, N>The resulting type after applying the / operator. sourcefn div( self, rhs: Simd<isize, N>) -> <Simd<isize, N> as Div<Simd<isize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<u16, N>> for Simd<u16, N>where u16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u16, N>The resulting type after applying the / operator. sourcefn div(self, rhs: Simd<u16, N>) -> <Simd<u16, N> as Div<Simd<u16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<u32, N>> for Simd<u32, N>where u32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u32, N>The resulting type after applying the / operator. sourcefn div(self, rhs: Simd<u32, N>) -> <Simd<u32, N> as Div<Simd<u32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<u64, N>> for Simd<u64, N>where u64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u64, N>The resulting type after applying the / operator. sourcefn div(self, rhs: Simd<u64, N>) -> <Simd<u64, N> as Div<Simd<u64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<u8, N>> for Simd<u8, N>where u8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u8, N>The resulting type after applying the / operator. sourcefn div(self, rhs: Simd<u8, N>) -> <Simd<u8, N> as Div<Simd<u8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<const N: usize> Div<Simd<usize, N>> for Simd<usize, N>where usize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<usize, N>The resulting type after applying the / operator. sourcefn div( self, rhs: Simd<usize, N>) -> <Simd<usize, N> as Div<Simd<usize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the / operation. Read more sourceimpl<T, U, const LANES: usize> DivAssign<U> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Div<U>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Div<U>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, sourcefn div_assign(&mut self, rhs: U)Performs the /= operation. Read more sourceimpl<T, const LANES: usize> From<[T; LANES]> for Simd<T, LANES>where T: SimdElement, LaneCount<LANES>: SupportedLaneCount, sourcefn from(array: [T; LANES]) -> Simd<T, LANES>Converts to this type from the input type. sourceimpl<T, const LANES: usize> From<Mask<T, LANES>> for Simd<T, LANES>where T: MaskElement, LaneCount<LANES>: SupportedLaneCount, sourcefn from(value: Mask<T, LANES>) -> Simd<T, LANES>Converts to this type from the input type. sourceimpl<T, const LANES: usize> From<Simd<T, LANES>> for [T; LANES]where T: SimdElement, LaneCount<LANES>: SupportedLaneCount, sourcefn from(vector: Simd<T, LANES>) -> [T; LANES]Converts to this type from the input type. sourceimpl From<Simd<f32, 16>> for __m512 sourcefn from(value: Simd<f32, 16>) -> __m512Converts to this type from the input type. sourceimpl From<Simd<f32, 4>> for __m128 sourcefn from(value: Simd<f32, 4>) -> __m128Converts to this type from the input type. sourceimpl From<Simd<f32, 8>> for __m256 sourcefn from(value: Simd<f32, 8>) -> __m256Converts to this type from the input type. sourceimpl From<Simd<f64, 2>> for __m128d sourcefn from(value: Simd<f64, 2>) -> __m128dConverts to this type from the input type. sourceimpl From<Simd<f64, 4>> for __m256d sourcefn from(value: Simd<f64, 4>) -> __m256dConverts to this type from the input type. sourceimpl From<Simd<f64, 8>> for __m512d sourcefn from(value: Simd<f64, 8>) -> __m512dConverts to this type from the input type. sourceimpl From<Simd<i16, 16>> for __m256i sourcefn from(value: Simd<i16, 16>) -> __m256iConverts to this type from the input type. sourceimpl From<Simd<i16, 32>> for __m512i sourcefn from(value: Simd<i16, 32>) -> __m512iConverts to this type from the input type. sourceimpl From<Simd<i16, 8>> for __m128i sourcefn from(value: Simd<i16, 8>) -> __m128iConverts to this type from the input type. sourceimpl From<Simd<i32, 16>> for __m512i sourcefn from(value: Simd<i32, 16>) -> __m512iConverts to this type from the input type. sourceimpl From<Simd<i32, 4>> for __m128i sourcefn from(value: Simd<i32, 4>) -> __m128iConverts to this type from the input type. sourceimpl From<Simd<i32, 8>> for __m256i sourcefn from(value: Simd<i32, 8>) -> __m256iConverts to this type from the input type. sourceimpl From<Simd<i64, 2>> for __m128i sourcefn from(value: Simd<i64, 2>) -> __m128iConverts to this type from the input type. sourceimpl From<Simd<i64, 4>> for __m256i sourcefn from(value: Simd<i64, 4>) -> __m256iConverts to this type from the input type. sourceimpl From<Simd<i64, 8>> for __m512i sourcefn from(value: Simd<i64, 8>) -> __m512iConverts to this type from the input type. sourceimpl From<Simd<i8, 16>> for __m128i sourcefn from(value: Simd<i8, 16>) -> __m128iConverts to this type from the input type. sourceimpl From<Simd<i8, 32>> for __m256i sourcefn from(value: Simd<i8, 32>) -> __m256iConverts to this type from the input type. sourceimpl From<Simd<i8, 64>> for __m512i sourcefn from(value: Simd<i8, 64>) -> __m512iConverts to this type from the input type. sourceimpl From<Simd<isize, 2>> for __m128i sourcefn from(value: Simd<isize, 2>) -> __m128iConverts to this type from the input type. sourceimpl From<Simd<isize, 4>> for __m256i sourcefn from(value: Simd<isize, 4>) -> __m256iConverts to this type from the input type. sourceimpl From<Simd<isize, 8>> for __m512i sourcefn from(value: Simd<isize, 8>) -> __m512iConverts to this type from the input type. sourceimpl From<Simd<u16, 16>> for __m256i sourcefn from(value: Simd<u16, 16>) -> __m256iConverts to this type from the input type. sourceimpl From<Simd<u16, 32>> for __m512i sourcefn from(value: Simd<u16, 32>) -> __m512iConverts to this type from the input type. sourceimpl From<Simd<u16, 8>> for __m128i sourcefn from(value: Simd<u16, 8>) -> __m128iConverts to this type from the input type. sourceimpl From<Simd<u32, 16>> for __m512i sourcefn from(value: Simd<u32, 16>) -> __m512iConverts to this type from the input type. sourceimpl From<Simd<u32, 4>> for __m128i sourcefn from(value: Simd<u32, 4>) -> __m128iConverts to this type from the input type. sourceimpl From<Simd<u32, 8>> for __m256i sourcefn from(value: Simd<u32, 8>) -> __m256iConverts to this type from the input type. sourceimpl From<Simd<u64, 2>> for __m128i sourcefn from(value: Simd<u64, 2>) -> __m128iConverts to this type from the input type. sourceimpl From<Simd<u64, 4>> for __m256i sourcefn from(value: Simd<u64, 4>) -> __m256iConverts to this type from the input type. sourceimpl From<Simd<u64, 8>> for __m512i sourcefn from(value: Simd<u64, 8>) -> __m512iConverts to this type from the input type. sourceimpl From<Simd<u8, 16>> for __m128i sourcefn from(value: Simd<u8, 16>) -> __m128iConverts to this type from the input type. sourceimpl From<Simd<u8, 32>> for __m256i sourcefn from(value: Simd<u8, 32>) -> __m256iConverts to this type from the input type. sourceimpl From<Simd<u8, 64>> for __m512i sourcefn from(value: Simd<u8, 64>) -> __m512iConverts to this type from the input type. sourceimpl From<Simd<usize, 2>> for __m128i sourcefn from(value: Simd<usize, 2>) -> __m128iConverts to this type from the input type. sourceimpl From<Simd<usize, 4>> for __m256i sourcefn from(value: Simd<usize, 4>) -> __m256iConverts to this type from the input type. sourceimpl From<Simd<usize, 8>> for __m512i sourcefn from(value: Simd<usize, 8>) -> __m512iConverts to this type from the input type. sourceimpl From<__m128> for Simd<f32, 4> sourcefn from(value: __m128) -> Simd<f32, 4>Converts to this type from the input type. sourceimpl From<__m128d> for Simd<f64, 2> sourcefn from(value: __m128d) -> Simd<f64, 2>Converts to this type from the input type. sourceimpl From<__m128i> for Simd<i16, 8> sourcefn from(value: __m128i) -> Simd<i16, 8>Converts to this type from the input type. sourceimpl From<__m128i> for Simd<i32, 4> sourcefn from(value: __m128i) -> Simd<i32, 4>Converts to this type from the input type. sourceimpl From<__m128i> for Simd<i64, 2> sourcefn from(value: __m128i) -> Simd<i64, 2>Converts to this type from the input type. sourceimpl From<__m128i> for Simd<i8, 16> sourcefn from(value: __m128i) -> Simd<i8, 16>Converts to this type from the input type. sourceimpl From<__m128i> for Simd<isize, 2> sourcefn from(value: __m128i) -> Simd<isize, 2>Converts to this type from the input type. sourceimpl From<__m128i> for Simd<u16, 8> sourcefn from(value: __m128i) -> Simd<u16, 8>Converts to this type from the input type. sourceimpl From<__m128i> for Simd<u32, 4> sourcefn from(value: __m128i) -> Simd<u32, 4>Converts to this type from the input type. sourceimpl From<__m128i> for Simd<u64, 2> sourcefn from(value: __m128i) -> Simd<u64, 2>Converts to this type from the input type. sourceimpl From<__m128i> for Simd<u8, 16> sourcefn from(value: __m128i) -> Simd<u8, 16>Converts to this type from the input type. sourceimpl From<__m128i> for Simd<usize, 2> sourcefn from(value: __m128i) -> Simd<usize, 2>Converts to this type from the input type. sourceimpl From<__m256> for Simd<f32, 8> sourcefn from(value: __m256) -> Simd<f32, 8>Converts to this type from the input type. sourceimpl From<__m256d> for Simd<f64, 4> sourcefn from(value: __m256d) -> Simd<f64, 4>Converts to this type from the input type. sourceimpl From<__m256i> for Simd<i16, 16> sourcefn from(value: __m256i) -> Simd<i16, 16>Converts to this type from the input type. sourceimpl From<__m256i> for Simd<i32, 8> sourcefn from(value: __m256i) -> Simd<i32, 8>Converts to this type from the input type. sourceimpl From<__m256i> for Simd<i64, 4> sourcefn from(value: __m256i) -> Simd<i64, 4>Converts to this type from the input type. sourceimpl From<__m256i> for Simd<i8, 32> sourcefn from(value: __m256i) -> Simd<i8, 32>Converts to this type from the input type. sourceimpl From<__m256i> for Simd<isize, 4> sourcefn from(value: __m256i) -> Simd<isize, 4>Converts to this type from the input type. sourceimpl From<__m256i> for Simd<u16, 16> sourcefn from(value: __m256i) -> Simd<u16, 16>Converts to this type from the input type. sourceimpl From<__m256i> for Simd<u32, 8> sourcefn from(value: __m256i) -> Simd<u32, 8>Converts to this type from the input type. sourceimpl From<__m256i> for Simd<u64, 4> sourcefn from(value: __m256i) -> Simd<u64, 4>Converts to this type from the input type. sourceimpl From<__m256i> for Simd<u8, 32> sourcefn from(value: __m256i) -> Simd<u8, 32>Converts to this type from the input type. sourceimpl From<__m256i> for Simd<usize, 4> sourcefn from(value: __m256i) -> Simd<usize, 4>Converts to this type from the input type. sourceimpl From<__m512> for Simd<f32, 16> sourcefn from(value: __m512) -> Simd<f32, 16>Converts to this type from the input type. sourceimpl From<__m512d> for Simd<f64, 8> sourcefn from(value: __m512d) -> Simd<f64, 8>Converts to this type from the input type. sourceimpl From<__m512i> for Simd<i16, 32> sourcefn from(value: __m512i) -> Simd<i16, 32>Converts to this type from the input type. sourceimpl From<__m512i> for Simd<i32, 16> sourcefn from(value: __m512i) -> Simd<i32, 16>Converts to this type from the input type. sourceimpl From<__m512i> for Simd<i64, 8> sourcefn from(value: __m512i) -> Simd<i64, 8>Converts to this type from the input type. sourceimpl From<__m512i> for Simd<i8, 64> sourcefn from(value: __m512i) -> Simd<i8, 64>Converts to this type from the input type. sourceimpl From<__m512i> for Simd<isize, 8> sourcefn from(value: __m512i) -> Simd<isize, 8>Converts to this type from the input type. sourceimpl From<__m512i> for Simd<u16, 32> sourcefn from(value: __m512i) -> Simd<u16, 32>Converts to this type from the input type. sourceimpl From<__m512i> for Simd<u32, 16> sourcefn from(value: __m512i) -> Simd<u32, 16>Converts to this type from the input type. sourceimpl From<__m512i> for Simd<u64, 8> sourcefn from(value: __m512i) -> Simd<u64, 8>Converts to this type from the input type. sourceimpl From<__m512i> for Simd<u8, 64> sourcefn from(value: __m512i) -> Simd<u8, 64>Converts to this type from the input type. sourceimpl From<__m512i> for Simd<usize, 8> sourcefn from(value: __m512i) -> Simd<usize, 8>Converts to this type from the input type. sourceimpl<T, const LANES: usize> Hash for Simd<T, LANES>where T: SimdElement + Hash, LaneCount<LANES>: SupportedLaneCount, sourcefn hash<H>(&self, state: &mut H)where H: Hasher, Feeds this value into the given Hasher. Read more source1.3.0 · fn hash_slice<H>(data: &[Self], state: &mut H)where H: Hasher, Feeds a slice of this type into the given Hasher. Read more sourceimpl<I, T, const LANES: usize> Index<I> for Simd<T, LANES>where T: SimdElement, I: SliceIndex<[T]>, LaneCount<LANES>: SupportedLaneCount, type Output = <I as SliceIndex<[T]>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputThe returned type after indexing. sourcefn index(&self, index: I) -> &<Simd<T, LANES> as Index<I>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the indexing (container[index]) operation. Read more sourceimpl<I, T, const LANES: usize> IndexMut<I> for Simd<T, LANES>where T: SimdElement, I: SliceIndex<[T]>, LaneCount<LANES>: SupportedLaneCount, sourcefn index_mut(&mut self, index: I) -> &mut <Simd<T, LANES> as Index<I>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the mutable indexing (container[index]) operation. Read more sourceimpl<T, const LANES: usize> LowerExp for Simd<T, LANES>where T: SimdElement + LowerExp, LaneCount<LANES>: SupportedLaneCount, sourcefn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>Formats the value using the given formatter. sourceimpl<T, const LANES: usize> LowerHex for Simd<T, LANES>where T: SimdElement + LowerHex, LaneCount<LANES>: SupportedLaneCount, sourcefn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>Formats the value using the given formatter. sourceimpl<'lhs, 'rhs, T, const LANES: usize> Mul<&'rhs Simd<T, LANES>> for &'lhs Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Mul<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Mul<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the * operator. sourcefn mul( self, rhs: &Simd<T, LANES>) -> <&'lhs Simd<T, LANES> as Mul<&'rhs Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<T, const LANES: usize> Mul<&Simd<T, LANES>> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Mul<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Mul<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the * operator. sourcefn mul( self, rhs: &Simd<T, LANES>) -> <Simd<T, LANES> as Mul<&Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<T, const LANES: usize> Mul<Simd<T, LANES>> for &Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Mul<Simd<T, LANES>>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Mul<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, type Output = Simd<T, LANES>The resulting type after applying the * operator. sourcefn mul( self, rhs: Simd<T, LANES>) -> <&Simd<T, LANES> as Mul<Simd<T, LANES>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<f32, N>> for Simd<f32, N>where f32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<f32, N>The resulting type after applying the * operator. sourcefn mul(self, rhs: Simd<f32, N>) -> <Simd<f32, N> as Mul<Simd<f32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<f64, N>> for Simd<f64, N>where f64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<f64, N>The resulting type after applying the * operator. sourcefn mul(self, rhs: Simd<f64, N>) -> <Simd<f64, N> as Mul<Simd<f64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<i16, N>> for Simd<i16, N>where i16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i16, N>The resulting type after applying the * operator. sourcefn mul(self, rhs: Simd<i16, N>) -> <Simd<i16, N> as Mul<Simd<i16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<i32, N>> for Simd<i32, N>where i32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i32, N>The resulting type after applying the * operator. sourcefn mul(self, rhs: Simd<i32, N>) -> <Simd<i32, N> as Mul<Simd<i32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<i64, N>> for Simd<i64, N>where i64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i64, N>The resulting type after applying the * operator. sourcefn mul(self, rhs: Simd<i64, N>) -> <Simd<i64, N> as Mul<Simd<i64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<i8, N>> for Simd<i8, N>where i8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<i8, N>The resulting type after applying the * operator. sourcefn mul(self, rhs: Simd<i8, N>) -> <Simd<i8, N> as Mul<Simd<i8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<isize, N>> for Simd<isize, N>where isize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<isize, N>The resulting type after applying the * operator. sourcefn mul( self, rhs: Simd<isize, N>) -> <Simd<isize, N> as Mul<Simd<isize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<u16, N>> for Simd<u16, N>where u16: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u16, N>The resulting type after applying the * operator. sourcefn mul(self, rhs: Simd<u16, N>) -> <Simd<u16, N> as Mul<Simd<u16, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<u32, N>> for Simd<u32, N>where u32: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u32, N>The resulting type after applying the * operator. sourcefn mul(self, rhs: Simd<u32, N>) -> <Simd<u32, N> as Mul<Simd<u32, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<u64, N>> for Simd<u64, N>where u64: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u64, N>The resulting type after applying the * operator. sourcefn mul(self, rhs: Simd<u64, N>) -> <Simd<u64, N> as Mul<Simd<u64, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<u8, N>> for Simd<u8, N>where u8: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<u8, N>The resulting type after applying the * operator. sourcefn mul(self, rhs: Simd<u8, N>) -> <Simd<u8, N> as Mul<Simd<u8, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<const N: usize> Mul<Simd<usize, N>> for Simd<usize, N>where usize: SimdElement, LaneCount<N>: SupportedLaneCount, type Output = Simd<usize, N>The resulting type after applying the * operator. sourcefn mul( self, rhs: Simd<usize, N>) -> <Simd<usize, N> as Mul<Simd<usize, N>>>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the * operation. Read more sourceimpl<T, U, const LANES: usize> MulAssign<U> for Simd<T, LANES>where T: SimdElement, Simd<T, LANES>: Mul<U>, LaneCount<LANES>: SupportedLaneCount, <Simd<T, LANES> as Mul<U>>8b7c:f320:99b9:690f:4595:cd17:293a:c069Output == Simd<T, LANES>, sourcefn mul_assign(&mut self, rhs: U)Performs the *= operation. Read more sourceimpl<const LANES: usize> Neg for Simd<f32, LANES>where f32: SimdElement, LaneCount<LANES>: SupportedLaneCount, type Output = Simd<f32, LANES>The resulting type after applying the - operator. sourcefn neg(self) -> <Simd<f32, LANES> as Neg>8b7c:f320:99b9:690f:4595:cd17:293a:c069OutputPerforms the unary - operation. Read more sourceimpl<const LANES: usize> Neg for Simd<f64, LANES>where f64: SimdElement, LaneCount<LANES>: SupportedLaneCount, type Output = Simd<f64, LANES>The
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