Title of Invention: WIRING SUBSTRATE AND DISPLAY DEVICE Abstract: A wiring substrate includes a signal supply unit, a plurality of wirings disposed in a wiring region in which an intermediate region is interposed between the wiring region and the signal supply units, and having different distances from the signal supply unit, and a plurality of coupling wirings disposed in the intermediate region, and coupled to the signal supply unit and the plurality of wirings, in which the plurality of coupling wirings includes a first coupling wiring coupled to a wiring having a short distance from the signal supply unit, and a second coupling wiring coupled to a wiring having a long distance from the signal supply unit among the plurality of wirings, and the first coupling wiring is folded back to the signal supply unit side in the middle of running from the signal supply unit to the wiring region. Detailed Description: TECHNICAL FIELD The present disclosure relates to a wiring substrate and a display device. BACKGROUND ART In the related art, as an example of a lead wiring device, a device described in JP 2010-72256A below is known. The lead wiring device described in JP 2010-72256A includes an insulating layer that electrically insulates, a coupling portion penetrating the insulating layer, an external coupling terminal formed on one surface of the insulating layer, and a lead wire formed on the other surface of the insulating layer. The external coupling terminal and the lead wire are coupled to each other by the coupling portion. One end portion of the lead wire is coupled to a conductor. The other end portion of the lead wire is coupled to the external coupling terminal by the coupling portion at a position separated from a first end portion of the external coupling terminal on the conductor side by a predetermined distance. SUMMARY OF INVENTION In the lead wiring device described in JP 2010-72256A described above, one end portion of the lead wire is coupled to the external coupling terminal by the coupling portion at a position separated from the end portion of the external coupling terminal on the conductor side by a predetermined distance. Therefore, an adjustment range of a resistance value of the lead wire can be expanded. However, in the lead wiring device described in JP 2010-72256A, since the disposition of the coupling portion can be changed only within the range of the length of the external coupling terminal, it can not be said that the adjustment range of the resistance value of the lead wire is sufficiently expanded, and further improvement is desired. The present disclosure is completed based on the above-described circumstances, and the adjustment range related to a wiring resistance of the coupling wiring is further expanded. Solution to Problem (1) According to an aspect of the present disclosure, there is provided a wiring substrate including a signal supply unit, a plurality of wirings disposed in a wiring region in which an intermediate region is interposed between the wiring region and the signal supply unit, and having different distances from the signal supply unit, and a plurality of coupling wirings disposed in the intermediate region, and coupled to the signal supply unit and the plurality of wirings, in which the coupling wiring includes a first coupling wiring coupled to a wiring having a short distance from the signal supply unit, and a second coupling wiring coupled to a wiring having a long distance from the signal supply unit among the plurality of wirings, and the first coupling wiring is folded back to the signal supply unit side in the middle of running from the signal supply unit to the wiring region. (2) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of the above (1), the first coupling wiring includes a signal supply unit coupling portion coupled to the signal supply unit and extending toward the wiring region side, a wiring coupling portion coupled to the wiring and extending toward the signal supply unit side, and an intermediate portion coupled to each of an extension end-side portion of the signal supply unit coupling portion and an extension end-side portion of the wiring coupling portion. (3) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of the above (2), in the first coupling wiring, the signal supply unit coupling portion, the wiring coupling portion, and the intermediate portion are formed of a plurality of conductive films with an insulating film interposed therebetween, and the signal supply unit coupling portion, the wiring coupling portion, and the intermediate portion include portions that at least partially overlap each other through the insulating film. (4) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of the above (3), the signal supply unit coupling portion, the wiring coupling portion, and the intermediate portion are formed of the conductive films different from each other, and the signal supply unit coupling portion and the wiring coupling portion are disposed so as not to overlap each other, and the intermediate portion is disposed so as to partially overlap the signal supply unit coupling portion and the wiring coupling portion, respectively. (5) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of the above (3) or (4), the signal supply unit coupling portion, the wiring coupling portion, and the intermediate portion are formed of the conductive films different from each other, and the intermediate portion is formed of the conductive film located at an intermediate position between both the conductive film constituting the signal supply unit coupling portion and the conductive film constituting the wiring coupling portion through insulating films, respectively, and is coupled to the signal supply unit coupling portion and the wiring coupling portion through contact holes formed to open in each of the insulating films. (6) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of any one of the above (2) to (5), the first coupling wiring is configured such that the extension end-side portion of the signal supply unit coupling portion is disposed closer to the wiring region than the extension end-side portion of the wiring coupling portion. (7) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of the above (6), the first coupling wiring is configured such that the extension end-side portion of the signal supply unit coupling portion is disposed at a position adjacent to the wiring region, and the extension end-side portion of the wiring coupling portion is disposed at a position adjacent to the signal supply unit. (8) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of the above (6) or (7), in the first coupling wiring, the signal supply unit coupling portion, the wiring coupling portion, and the intermediate portion are formed of a plurality of conductive films with an insulating film interposed therebetween, and the signal supply unit coupling portion, the wiring coupling portion, and the intermediate portion each have parallel portions parallel to each other, and the parallel portions include portions that at least partially overlap each other through the insulating film. (9) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of any one of the above (1) to (8), the second coupling wiring has a plurality of second coupling wiring constituting portions formed of a plurality of conductive films having an insulating film interposed therebetween, and coupled to each other. (10) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of the above (9), the plurality of second coupling wiring constituting portions include portions that at least partially overlap each other through the insulating film. (11) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of the above (10), the second coupling wiring includes three or more second coupling wiring constituting portions, and the three or more second coupling wiring constituting portions are disposed in parallel with each other and to overlap each other through the insulating film. (12) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of any one of the above (1) to (11), the wiring substrate further including a plurality of second wirings disposed in the wiring region and extending so as to intersect the wiring, in which the plurality of wirings are disposed such that an arrangement interval thereof is larger than an arrangement interval of the plurality of second wirings. (13) In the wiring substrate according to the aspect of the present disclosure, in addition to the configuration of any one of the above (1) to (12), the first coupling wiring is folded back while meandering in a zigzag shape. (14) According to an aspect of the present disclosure, there is provided a display device including the wiring substrate according to any one of (1) to (13), and a plurality of pixel units disposed in the wiring region and coupled to the plurality of wirings. According to this disclosure, the adjustment range related to a wiring resistance of the coupling wiring can be further expanded. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic plan view of a liquid crystal panel provided in a liquid crystal display device according to Embodiment 1 of the present disclosure. FIG. 2 is a plan view illustrating a pixel array on an array substrate constituting the liquid crystal panel. FIG. 3 is a cross-sectional view of the liquid crystal panel taken along line A-A of FIG. 2. FIG. 4 is a cross-sectional view of the liquid crystal panel taken along line B-B of FIG. 2. FIG. 5 is a cross-sectional view of the array substrate taken along line C-C of FIG. 2. FIG. 6 is a cross-sectional view of the array substrate taken along line D-D of FIG. 2. FIG. 7 is a plan view mainly illustrating a coupling wiring on the array substrate. FIG. 8 is a plan view illustrating a first coupling wiring on the array substrate. FIG. 9 is a cross-sectional view of the array substrate taken along line E-E of FIG. 8. FIG. 10 is a cross-sectional view of the array substrate taken along line F-F of FIG. 8. FIG. 11 is a cross-sectional view of the array substrate taken along line G-G of FIG. 8. FIG. 12 is a cross-sectional view of the array substrate taken along line H-H of FIG. 8. FIG. 13 is a plan view illustrating a second coupling wiring on the array substrate. FIG. 14 is a cross-sectional view of the array substrate taken along line I-I of FIG. 13. FIG. 15 is a cross-sectional view of the array substrate taken along line J-J of FIG. 13. FIG. 16 is a plan view illustrating a first coupling wiring on an array substrate constituting a liquid crystal panel according to Embodiment 2 of the present disclosure. FIG. 17 is a plan view illustrating a pixel array on an array substrate constituting an organic EL display panel according to Embodiment 3 of the present disclosure. FIG. 18 is a circuit diagram illustrating an electrical configuration of a pixel on the array substrate. FIG. 19 is a cross-sectional view taken along line K-K of FIG. 17 on the array substrate. FIG. 20 is a plan view mainly illustrating patterns of a first metal film, a second metal film, and a third metal film provided on the array substrate. FIG. 21 is a plan view mainly illustrating patterns of a semiconductor film and a fourth metal film provided on the array substrate. FIG. 22 is a cross-sectional view of a vicinity of a coupling portion between a terminal unit coupling portion and an intermediate portion of the first coupling wiring on the array substrate. DESCRIPTION OF EMBODIMENTS Embodiment 1 Embodiment 1 of the present disclosure will be described with reference to FIGS. 1 to 15. In the present embodiment, an array substrate 21 constituting a liquid crystal panel (display panel) 11 will be described as an example. An X axis, a Y axis, and a Z axis are illustrated in a portion of each drawing, and each axis direction is drawn so as to be the direction illustrated in each drawing. An upper side of FIGS. 3 to 6, 9 to 12, 14, and 15 is defined as a front side, and a lower side is defined as a rear side. FIG. 1 is a schematic plan view of the liquid crystal panel 11. As illustrated in FIG. 1, the liquid crystal display device 10 is provided with at least the liquid crystal panel (display device, display panel) 11 having an elongated rectangular shape and capable of displaying an image and a backlight device (lighting device) serving as an external light source, which irradiates the liquid crystal panel 11 with light used for display. In the present embodiment, a screen size of the liquid crystal panel 11 is approximately 30 inches (specifically, 31.5 inches), for example, and the resolution is equivalent to “WXGA”. The backlight device is disposed on the rear side (rear surface side) with respect to the liquid crystal panel 11, and includes a light source (for example, LED or the like) that emits white light or an optical member converting light from the light source into planar light by applying an optical action to the light. As illustrated in FIG. 1, in the liquid crystal panel 11, a center-side portion of the screen is a display region (wiring region) AA where an image is displayed. The display region AA is a range surrounded by a chain line in FIG. 1. On the other hand, a frame-shaped outer peripheral portion surrounding the display region AA on the screen of the liquid crystal panel 11 is a non-display region NAA in which no image is displayed. In the present embodiment, the long side dimension in the display region AA is, for example, 697.7 mm, and the short side dimension is, for example, 392.3 mm. The liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21. A front side (front surface side) among the pair of substrates 20 and 21 is a CF substrate (counter substrate) 20, and a rear side (rear surface side) is an array substrate (wiring substrate, active matrix substrate) 21. Each of the CF substrate 20 and the array substrate 21 is formed by laminating various films on the inner surface side of a glass substrate. Polarizing plates are attached to the outer surfaces of the substrates 20 and 21, respectively. As illustrated in FIG. 1, the CF substrate 20 is bonded to the array substrate 21 such that one end portion thereof is aligned with the short side direction (Y axis direction) while the short side dimension is shorter than the short side dimension of the array substrate 21. Therefore, the other end portion of the array substrate 21 in the short side direction is a non-overlapping portion 21A of the CF substrate, which projects laterally from the CF substrate 20 and does not overlap the CF substrate 20. A flexible substrate 13 having a driver 12 is mounted on the non-overlapping portion 21A of the CF substrate by chip on board (COB). The driver 12 is formed of an LSI chip having a drive circuit therein, is mounted on the flexible substrate 13 by chip on film (COF), and processes various signals supplied through the flexible substrate 13. In the present embodiment, only one driver 12 is mounted on the flexible substrate 13. The flexible substrate 13 has a configuration in which a large number of wiring patterns are formed on a substrate formed of a synthetic resin material having insulating properties and flexibility (for example, polyimide resin). The flexible substrate 13 has one end coupled to the non-display region NAA of the liquid crystal panel 11 and the other end coupled to a control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the driver 12 through the flexible substrate 13, processed there, and thereafter supplied to the liquid crystal panel 11 through the flexible substrate 13. In the present embodiment, only one flexible substrate 13 is mounted at a substantially central position in the long side direction (X axis direction) in the non-overlapping portion 21A of the CF substrate on the array substrate 21. In the non-overlapping portion 21A of the CF substrate on the array substrate 21, a plurality of coupling wirings (leading wiring) 15 are provided to be routed in an extended fan shape from a mounting region of the flexible substrate 13 to the display region AA. The coupling wiring 15 will be described later. In the non-display region NAA of the array substrate 21, a pair of gate circuit units (signal supply units) 14 are provided so as to interpose the display region AA from both sides in the X axis direction. The gate circuit unit 14 is a unit for supplying a scanning signal to a gate wiring 26 described later, and is provided monolithically on the array substrate 21. FIG. 2 is a plan view of the array substrate 21 and the CF substrate 20 constituting the liquid crystal panel 11 in the display region AA. As illustrated in FIG. 2, a thin film transistor (switching element, TFT) 23 and a pixel electrode 24 are provided on the inner surface side of the display region AA on the array substrate 21. The TFTs 23 and the pixel electrodes 24 are arranged in a matrix (in rows and columns) at intervals along the X axis direction and the Y axis direction. Around the TFT 23 and the pixel electrode 24, a gate wiring (second wiring, scanning wiring) 26 and a source wiring (wiring, image wiring, data wiring) 27, which form a substantially lattice shape, are provided so as to surround these. The gate wiring 26 extends along the X axis direction, while the source wiring 27 extends along the Y axis direction. In the present embodiment, the resolution of the liquid crystal panel 11 is equivalent to “WXGA”, and as described later, the three color filters 28 have a configuration in which those exhibiting different colors from each other are repeatedly disposed along the source wiring 27 (Y axis direction). Therefore, the number of the gate wirings 26 is “768×3=2304”, and the number of source wirings 27 is “1366”. The gate wiring 26 and the source wiring 27 are coupled to an upper layer-side gate electrode 23A and a lower layer-side gate electrode 23E of the TFT 23 and a source region 23B, respectively, and the pixel electrode 24 is coupled to a drain region 23C of the TFT 23. The TFT 23 is driven based on various signals supplied to the gate wiring 26 and the source wiring 27, respectively, and controls the supply of a potential to the pixel electrode 24 with the driving. The TFT 23 is disposed adjacent to the pixel electrode 24 to be coupled on one side (left side in FIG. 2) in the X axis direction. As illustrated in FIG. 2, the pixel electrode 24 has an elongated long shape in a plan view, and a longitudinal direction coincides with the X axis direction, and a short direction coincides with the Y axis direction. The ratio of a longitudinal dimension to a short dimension in the pixel electrode 24 is 3. While the gate wiring 26 is interposed between the pixel electrodes 24 adjacent in the short direction (Y axis direction), the source wiring 27 is interposed between the pixel electrodes 24 adjacent in the longitudinal direction (X axis direction). The arrangement interval of the gate wiring 26 is approximately the same as the short dimension of the pixel electrode 24, and the arrangement interval of the source wiring 27 is approximately the same as the longitudinal dimension of the pixel electrode 24 and is larger than the arrangement interval of the gate wiring 26. Therefore, as compared with the case where the pixel electrode has a vertically elongated shape, the arrangement interval of the source wiring 27 is approximately the ratio obtained by dividing the short dimension of the pixel electrode 24 by the longitudinal dimension (for example, approximately ⅓). Accordingly, the number of source wirings 27 per unit length in the X axis direction is approximately the same ratio as described above (for example, approximately ⅓). As compared with the case where the pixel electrode has a vertically elongated shape, the arrangement interval of the gate wiring 26 is approximately the ratio obtained by dividing the longitudinal dimension of the pixel electrode 24 by the short dimension (for example, approximately 3). Accordingly, the number of gate wirings 26 per unit length in the X axis direction is approximately the same ratio as described above (for example, approximately 3). As a result, the number of the source wirings 27 can be reduced, so that the number of image signals supplied to the source wiring 27 is reduced. As illustrated in FIG. 2, the pixel electrode 24 having an elongated rectangular shape as described above includes a stem electrode unit 24A and a plurality of branch electrode units 24B coupled to the stem electrode unit 24A, and has a fishbone shape as a whole in a plan view. The stem electrode unit 24A has a cross shape in a plan view, and includes a portion extending along the X axis direction and a portion extending along the Y axis direction. The plurality of the branch electrode units 24B are disposed in each of four regions partitioned by the cross-shaped stem electrode unit 24A, has one end coupled to the stem electrode unit 24A, and extends in such a manner as to extend substantially radially from the center of the stem electrode unit 24A. Therefore, the plurality of branch electrode units 24B disposed in four regions adjacent to each other in the X axis direction and the Y axis direction have a relationship in which the extending directions intersect each other. The plurality of branch electrode units 24B are disposed side by side at substantially equal intervals in the above-described four regions, and slits 24S having a substantially constant width are provided between adjacent branch electrode units 24B. The extending direction of the slit 24S coincides with the extending direction of the branch electrode unit 24B, and extends in such a manner that the slit 24S substantially radially extends from the center of the stem electrode unit 24A in each of the four regions described above. As described above, it can be said that the pixel electrode 24 is divided into four domains 24D in which the extending directions of the slits 24S are different from each other, and each domain 24D is disposed in the pixel electrode 24 two by two in the X axis direction and the Y axis direction. It can be said that the stem electrode unit 24A in the pixel electrode 24 is a boundary portion between the four domains 24D. Each of these four domains 24D has an elongated rectangular shape in a plan view. Here, since a partial recessed portion (portion where the pixel electrode 24 is absent) is formed in a portion of the front surface of the array substrate 21 that overlaps the slit 24S described above, and an electric field corresponding to the shape of the recessed portion is formed. Therefore, liquid crystal molecules contained in a liquid crystal layer 22 described later are aligned along the recessed portion. Therefore, the liquid crystal panel 11 according to the present embodiment is in a multi-domain vertical alignment (MVA) mode in which the alignment of the liquid crystal molecules included in the liquid crystal layer 22 differs for each domain 24D of the pixel electrode 24, so that the wide viewing angle is achieved. As illustrated in FIG. 2, the TFT 23 includes an upper layer-side gate electrode (first gate electrode) 23A formed of a portion of the gate wiring 26. The upper layer-side gate electrode 23A is formed of a portion of the gate wiring 26 that intersects a channel region 23D. A scanning signal transmitted to the gate wiring 26 is supplied to the upper layer-side gate electrode 23A. The TFT 23 includes a source region 23B coupled to the source wiring 27. The source wiring 27 includes a source wiring widened portion 27A protruding toward the pixel electrode 24 to be coupled in the X axis direction (right side in FIG. 2) from a position opposite to the pixel electrode 24 to be coupled in the Y axis direction (lower side in FIG. 2) with respect to the intersection portion with the gate wiring 26. The source region 23B has a substantially L-shape in a plan view, and a portion extending along the X axis direction is coupled to the above-described source wiring widened portion 27A. The TFT 23 includes the drain region 23C which is disposed at an interval from the source region 23B in the Y axis direction. An end portion of the drain region 23C opposite to the source region 23B (channel region 23D) is coupled to the pixel electrode 24. The TFT 23 is disposed to overlap the upper layer-side gate electrode 23A on the upper layer side, and has the channel region 23D coupled to the source region 23B and the drain region 23C. Similarly to the upper layer-side gate electrode 23A, the channel region 23D has an elongated rectangular shape in a plan view, one end portion in the Y axis direction (lower end portion in FIG. 2) is coupled to a portion of the source region 23B extending along the Y axis direction, and the other end portion (upper end portion in FIG. 2) is coupled to the drain region 23C, respectively. Furthermore, the TFT 23 includes a lower layer-side gate electrode (second gate electrode) 23E disposed so as to overlap the channel region 23D on the upper layer side. The lower layer-side gate electrode 23E has an elongated rectangular shape in a plan view, similar to the upper layer-side gate electrode 23A and the channel region 23D. Since the lower layer-side gate electrode 23E is electrically coupled to the upper layer-side gate electrode 23A, the scanning signal transmitted to the gate wiring 26 is supplied at the same timing as the upper layer-side gate electrode 23A. As described above, the channel region 23D is interposed between the upper layer side and the lower layer side in the Z axis direction by the upper layer-side gate electrode 23A and the lower layer-side gate electrode 23E. Therefore, the drain current flowing through the channel region 23D can be increased as compared with the case where only one gate electrodes is disposed to overlap the channel region 23D. As a result, the pixel electrode 24 can be sufficiently charged even when the charging time of the pixel electrode 24 charged by the TFT 23 is shortened as the number of the gate wirings 26 is increased. FIG. 3 is a cross-sectional view of the pixel unit PX of the liquid crystal panel 11 cut along the X axis direction. FIG. 4 is a cross-sectional view of the pixel unit PX of the liquid crystal panel 11 cut along the Y axis direction. As illustrated in FIGS. 3 and 4, the liquid crystal panel 11 has a liquid crystal layer 22 that is disposed between the pair of substrates 20 and 21, and that includes liquid crystal molecules, which are substances whose optical performance changes with the application of an electric field. In the display region AA on the inner surface side of the CF substrate 20 constituting the liquid crystal panel 11, three color filters 28 of blue (B), green (G), and red (R) are provided. A plurality of color filters 28 are arranged in a matrix in the X axis direction and the Y axis direction so as to overlap the pixel electrodes 24 on the array substrate 21 side in a plan view. In the color filters 28, those exhibiting different colors from each other are repeatedly disposed along the source wiring 27 (Y axis direction), and those exhibiting the same color are continuously disposed along the gate wiring 26 (X axis direction). In the liquid crystal panel 11, the R, G, and B color filters 28 disposed along the Y axis direction, and the three pixel electrodes 24 facing each color filter 28 form a pixel unit PX of three colors. In the liquid crystal panel 11, display pixels capable of performing color display with a predetermined gradation are formed by the R, G, and B three color pixel units PX adjacent to each other along the Y axis direction. The arrangement pitch in the X axis direction in the pixel unit PX is, for example, approximately 510 μm (more specifically, for example, 510.75 μm), and the arrangement pitch in the Y axis direction is, for example, approximately 170 μm (more specifically, for example, 170.25 μm). In the display region AA on the inner surface side of the CF substrate 20, as illustrated in FIGS. 3 and 4, a black matrix (light shielding unit between pixels) disposed so as to partition between the color filters 28 facing the adjacent pixel electrodes 24. 29 is formed. The black matrix 29 has a substantially lattice-like planar shape, and has a pixel opening portion 29A at a position where the black matrix 29 overlaps most of the pixel electrodes 24 in a plan view. The light transmitted through the pixel electrode 24 can be emitted to the outside of the liquid crystal panel 11 by the pixel opening portion 29A. The black matrix 29 is disposed to overlap at least the TFT 23, the gate wiring 26, and the source wiring 27 on the array substrate 21 side in a plan view. On the inner surface side of the color filter 28, a counter electrode 30 is provided. The counter electrode 30 is provided in a solid shape at least in the display region AA, and faces all the pixel electrodes 24 with the liquid crystal layer 22 interposed therebetween. By supplying a reference potential (common potential) to the counter electrode 30, a potential difference is generated between the counter electrode 30 and the pixel electrode 24 charged by the TFT 23. The alignment state of the liquid crystal molecules in the liquid crystal layer 22 changes based on this potential difference, so that a predetermined gradation display can be performed for each pixel. An overcoat film OC for flattening the innermost surface of the CF substrate 20 is provided between the color filter 28 and the counter electrode 30. It is preferable to provide a space for maintaining the thickness (cell gap) of the liquid crystal layer 22 on the inner surface side of the counter electrode 30. Alignment films for aligning liquid crystal molecules included in the liquid crystal layer 22 are provided on the innermost surfaces of the substrates 20 and 21 that are in contact with the liquid crystal layer 22. In the present embodiment, a vertical alignment film is used as the alignment film. In the display region AA on the inner surface side of the array substrate 21, a capacitance wiring 25 is provided as illustrated in FIGS. 2 to 4. The capacitance wiring 25 is disposed at a substantially intermediate position between two adjacent source wiring 27 in the X axis direction, and extends along the Y axis direction in parallel with the source wiring 27. The same reference potential as that of the counter electrode 30 is supplied to the capacitance wiring 25 by the flexible substrate 13 (refer to FIG. 1) described above. The capacitance wiring 25 collectively crosses a plurality of pixel electrodes 24 (pixel electrode rows) disposed along the Y axis direction, and are respectively disposed to be overlapped on a substantially central portion of each of the pixel electrodes 24 in the long side direction (X axis direction). Moreover, a capacitance forming unit 31 which is disposed to overlap the pixel electrode 24 and is coupled to the capacitance wiring 25 is provided in the display region AA on the inner surface side of the array substrate 21. The capacitance forming unit 31 can be maintained at the reference potential by the capacitance wiring 25 and form an electrostatic capacitance between the pixel electrodes 24 to be overlapped, so that the charged potential of the pixel electrode 24 can be maintained. The capacitance forming unit 31 includes a portion extending along the Y axis direction and overlaps a substantially central portion in the long side direction of the pixel electrode 24, and a portion extending along the X axis direction and overlaps a substantially central portion in the short side direction (Y axis direction)of the pixel electrode 24. That is, the capacitance forming unit 31 has a cross shape in a plan view, and is disposed so that substantially the entire area thereof overlaps the stem electrode unit 24A of the pixel electrode 24. Therefore, the capacitance forming unit 31 is disposed so as to be selectively overlapped with the boundary portion between the domains 24D adjacent to each other in the X axis direction and the Y axis direction in the pixel electrode 24. Here, in the vicinity of the boundary portion between the plurality of domains 24D in the pixel electrode 24, since it is difficult for the liquid crystal molecules to be aligned in a desired direction, for example, in a direction along the slit 24S where the pixel electrode 24 is absent, the amount of transmitted light tends to be locally reduced. On the other hand, as described above, when the capacitance forming unit 31 is disposed to selectively overlap the boundary portion between the adjacent domains 24D of the pixel electrode 24, a decrease in the amount of transmitted light which may occur due to the capacitance forming unit 31 being disposed to overlap the pixel electrode 24 is suppressed. Therefore, the aperture ratio can be improved as compared with the case where the capacitance forming unit is disposed not to be overlapped with the stem electrode unit 24A and to be overlapped with the domain 24D. The capacitance wiring 25 is provided with a branch unit 25A that overlaps a portion of the capacitance forming unit 31 extending along the X axis direction. Here, various films laminated on the inner surface side of the array substrate 21 will be described with reference to FIGS. 5 and 6. FIGS. 5 and 6 are cross-sectional views of the vicinity of the TFT 23 on the array substrate 21, respectively. As illustrated in FIGS. 5 and 6, on the array substrate 21, a first metal film (conductive film) 32, a lower layer-side gate insulating film (second gate insulating film) 33, a semiconductor film 34, an upper layer-side gate insulating film (first gate insulating film) 35, a second metal film (conductive film) 36, a first interlayer insulating film (insulating film) 37, a third metal film (conductive film) 38, a second interlayer insulating film (insulating film) 39, a flattening film (insulating film) 40, and a transparent electrode film 41 are sequentially laminated from a lower layer side (glass substrate side). Each of the first metal film 32, the second metal film 36, and the third metal film 38 is formed of a single layer film formed of one type of metal material or laminated films or alloys formed of different types of metal materials, and thus has conductivity and light shielding property. As illustrated in FIGS. 5 and 6, the first metal film 32 forms the lower layer-side gate electrode 23E of the TFT 23, the capacitance wiring 25, and the like. The second metal film 36 forms the gate wiring 26, the upper layer-side gate electrode 23A of the TFT 23, and the like. The third metal film 38 forms a pixel intermediate electrode 42 coupled to both the drain region 23C and the pixel electrode 24, as illustrated in FIG. 5, in addition to form the source wiring 27 and the capacitance forming unit 31. Since the pixel electrode 24 is coupled to the drain region 23C through the pixel intermediate electrode 42, as compared with a case where the pixel electrode is directly coupled to the drain region 23C, a problem such as a film break in the pixel electrode 24 is unlikely to occur, and the coupling reliability is high. The transparent electrode film 41 is formed of a transparent electrode material (for example, Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO)). The transparent electrode film 41 forms the pixel electrode 24 and the like. As illustrated in FIGS. 3 and 4, the capacitance forming unit 31 is configured to include the third metal film 38 disposed above the first metal film 32 and the second metal film 36, that is, close to the transparent electrode film 41. Therefore, a large electrostatic capacitance can be formed between the pixel electrodes 24 and the capacitance forming unit 31. As a result, the function of holding the potential of the pixel electrode 24 is enhanced. The semiconductor film 34 is an oxide semiconductor film using, for example, an oxide semiconductor as a material, and has a transparent property. The semiconductor film 34 forms the source region 23B, the drain region 23C, the channel region 23D, and the like, which form the TFT 23. Examples of a specific material of the semiconductor film 34 include an In-Ga-Zn-O-based semiconductor (for example, indium gallium zinc oxide). Here, the In-Ga-Zn-O-based semiconductor is a ternary oxide of indium (In), gallium (Ga), and zinc (Zn), and a ratio (composition ratio) of In, Ga, and Zn is not particularly limited. The ratio includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, and the like, and is not necessarily limited thereto. The In-Ga-Zn-O-based semiconductor may be amorphous or crystalline. In the case of a crystalline semiconductor, the semiconductor is preferably a crystalline In-Ga-Zn-O-based semiconductor in which the c axis is aligned substantially perpendicular to the layer surface. Here, a portion of the semiconductor film 34 (portion that does not overlap the second metal film 36) is reduced in resistance during the manufacturing process, and the semiconductor film 34 is configured to include a low resistance region and a non-resistance region. Specifically, after the semiconductor film 34 is patterned to have a predetermined planar shape, a low resistance treatment is performed using the upper layer-side gate insulating film 35 and the second metal film 36 laminated and formed on the upper layer side as a mask. A portion of the semiconductor film 34 that is exposed without being covered by the second metal film 36 (portion that does not overlap the second metal film 36) is the low resistance region, and a portion covered by the second metal film 36 (portion overlapping with the second metal film 36) is the non-resistance-lowering region. In FIG. 5, the low resistance region in the semiconductor film 34 is illustrated in a hatched shape. The low resistance region of the semiconductor film 34 has a significantly low resistivity, for example, approximately 1/10,000,000,000 to 1/100, as compared with the non-resistance-lowering region, and functions as a conductor. The source region 23B and the drain region 23C of the TFT 23 are configured to include the low resistance region of the semiconductor film 34. In the non-resistance-lowering region on the semiconductor film 34, electric charge can be moved only under specific conditions (when a scanning signal is supplied to each of the gate electrodes 23A and 23E), and in the low resistance region, electric charge can normally be moved and functions as a conductor. The non-resistance-lowering region of the semiconductor film 34 forms the channel region 23D of the TFT 23. On the lower layer side with respect to the channel region 23D, the lower layer-side gate electrode 23E formed of the first metal film 32 having a light shielding property in the TFT 23 is disposed to overlap. The lower layer-side gate electrode 23E can block light irradiated from the rear side to the channel region 23D. For example, such light is light for display irradiated from the backlight device to the liquid crystal panel 11 or the like. Since the above-described light toward the channel region 23D is blocked by the lower layer-side gate electrode 23E, a change in the performance of the TFT 23 that may occur when the light is irradiated to the channel region 23D can be suppressed. The lower layer-side gate insulating film 33, the upper layer-side gate insulating film 35, the first interlayer insulating film 37, and the second interlayer insulating film 39 are each formed of an inorganic material such as silicon nitride (SiNx) and silicon oxide (SiO2). The flattening film 40 is formed of, for example, an organic material such as PMMA (acrylic resin), and has a larger film thickness than these of the other insulating films 33, 35, 37, and 38 formed of an inorganic material. The innermost surface of the array substrate 21 is flattened by the flattening film 40. As illustrated in FIGS. 5 and 6, the lower layer-side gate insulating film 33 maintains the first metal film 32 on the lower layer side and the semiconductor film 34 on the upper layer side in an insulated state. In particular, the interval between the upper layer-side gate electrode 23A and the channel region 23D is kept constant by the portion of the lower layer-side gate insulating film 33 that overlaps the upper layer-side gate electrode 23A. The upper layer-side gate insulating film 35 maintains the semiconductor film 34 on the lower layer side and the second metal film 36 on the upper layer side in an insulated state. In particular, the interval between the lower layer-side gate electrode 23E and the channel region 23D is kept constant by the portion of the upper layer-side gate insulating film 35 that overlaps the lower layer-side gate electrode 23E. The upper layer-side gate insulating film 35 is patterned together with the second metal film 36 disposed on the upper layer side, and has a formation range that overlaps a substantially entire area of the second metal film 36 (excluding gate contact hole CH4 described later). The first interlayer insulating film 37 maintains the second metal film 36 on the lower side and the third metal film 38 on the upper side in an insulated state. The second interlayer insulating film 39 and the flattening film 40 maintain the third metal film 38 on the lower side and the transparent electrode film 41 on the upper side in an insulated state. As illustrated in FIG. 5, a first pixel contact hole CH1 for coupling the pixel intermediate electrode 42 to the drain region 23C is formed to open at a position that overlaps both the drain region 23C and the pixel intermediate electrode 42 in the first interlayer insulating film 37. Second pixel contact holes CH2 for coupling the pixel electrode 24 to the pixel intermediate electrode 42 are respectively formed to open at positions that overlap both the pixel electrode 24 and the pixel intermediate electrode 42 among the second interlayer insulating film 39 and the flattening film 40. The drain region 23C and the pixel electrode 24 are coupled to the pixel intermediate electrode 42 through these each pixel contact hole CH1 and CH2, respectively. Since the pixel intermediate electrode 42 is disposed so as to cover a portion facing the first pixel contact hole CH1 of the drain region 23C formed of the semiconductor film 34 from the upper layer side, when the second interlayer insulating film 39 is etched through the patterned flattening film 40, the drain region 23C can be prevented from being over-etched. A source contact hole CH3 for coupling the source wiring widened portion 27A to the source region 23B is formed to open at a position in the first interlayer insulating film 37 that overlaps both the source wiring widened portion 27A and the source region 23B of the source wiring 27. As illustrated in FIG. 6, gate contact holes CH4 for coupling the upper layer-side gate electrode 23A to the lower layer-side gate electrode 23E are formed to open at positions that overlap both the upper layer-side gate electrode 23A and the lower layer-side gate electrode 23E and do not overlap the channel region 23D among the lower layer-side gate insulating film 33 and the upper layer-side gate insulating film 35. A capacitance wiring contact hole CH5 for coupling the capacitance forming unit 31 to the capacitance wiring 25 is formed to open at a position that overlaps both the central portion of the capacitance forming unit 31 having a cross-shaped planar shape and the capacitance wiring 25 among the lower layer-side gate insulating film 33 and the first interlayer insulating film 37 (refer to FIG. 2). Next, the coupling wiring 15 will be described with reference to FIG. 7. FIG. 7 is a plan view mainly illustrating the coupling wiring 15 on the non-overlapping portion 21A of the CF substrate on the array substrate 21. As illustrated in FIG. 7, the coupling wiring 15 is disposed in an intermediate region MA interposed between the mounting region and the display region AA of the flexible substrate 13 in the Y axis direction in the non-overlapping portion 21A of the CF substrate on the array substrate 21. In the present embodiment, the disposition direction of the terminal unit 16, the intermediate region MA, and the display region AA in the non-overlapping portion 21A of the CF substrate coincides with the Y axis direction, and the direction orthogonal to the same disposition direction (disposition orthogonal direction) coincides with the X axis direction. The coupling wiring 15 is coupled to the terminal unit 16 provided in the mounting region (terminal region) of the flexible substrate 13 and the source wiring 27 provided in the display region AA in the intermediate region MA. The signal supplied from the terminal unit 16 can be transmitted to the source wiring 27 by the coupling wiring 15. The terminal unit 16 to be coupled to one of the coupling wiring 15 is electrically coupled to a terminal unit provided on the flexible substrate 13 through an anisotropic conductive film called anisotropic conductive film (ACF), receives a signal supplied from the flexible substrate 13, and supplies the signal to the coupling wiring 15. A plurality of source wirings 27 to be coupled to the other of the coupling wiring 15 are disposed in the display region AA at intervals along the X axis direction. Therefore, the plurality of source wirings 27 disposed along the X axis direction include a wiring having a short linear distance from the terminal unit 16 to be coupled and a wiring having a long linear distance from the terminal unit 16 to be coupled. In particular, in the present embodiment, since only one flexible substrate 13 is mounted on the liquid crystal panel 11, the difference in the linear distance from the terminal unit 16 to the source wiring 27 tends to increase. Specifically, the source wiring 27 disposed at the central position in the X axis direction in the display region AA has a linear distance to the terminal unit 16 to be coupled of approximately 11 mm, and the source wiring 27 disposed at the end position in the X axis direction in the display region AA has a linear distance to the terminal unit 16 to be coupled of approximately 328 mm. The difference in the linear distance is caused by the difference in the positional relationship in the X axis direction between each source wiring 27 and each terminal unit 16 to be coupled. Therefore, a difference in wiring resistance occurs between the coupling wiring 15 coupled to each of the source wiring 27 having different linear distances from the terminal unit 16 in magnitude, and even when the same signal is transmitted, there is a concern that a difference in the degree of dullness of those signals may be occur. In the present embodiment, the coupling wiring 15 is directly coupled to the source wiring 27 without passing through another circuit or the like. Therefore, the same number of coupling wiring 15 and terminal units 16 as the number of source wirings 27 are provided. Hereinafter, when the plurality of coupling wirings 15 are distinguished from each other, the above-described one having a short linear distance is referred to as a “first coupling wiring”, and a suffix α is added to the reference numeral. The above-described one having a long linear distance is referred to as a “second coupling wiring”, and a suffix β is added to the reference numeral. When these are collectively referred to without distinction, a suffix
{'application_number': '<application-reference appl-type="utility">\n<document-id>\n<country>US</country>\n<doc-number>16839170</doc-number>\n<date>20200403</date>\n</document-id>\n</application-reference>', 'publication_number': '<publication-reference>\n<document-id>\n<country>US</country>\n<doc-number>20200321358</doc-number>\n<kind>A1</kind>\n<date>20201008</date>\n</document-id>\n</publication-reference>', 'source_file': './application/2020/ipa201008.xml', 'source_data': 'USPTO-Application'}