Title of Invention: Semiconductor device Abstract: A demodulation signal is generated by provision of a demodulation signal generation circuit to the semiconductor device capable of wireless communication and by obtainment of a difference between voltages having opposite polarities by the demodulation signal generation circuit. Alternatively, a plurality of demodulation signal generation circuits and a selective circuit which selects a demodulation signal generation circuit depending on characteristics of a received signal are provided, where operation of a second demodulation signal generation circuit stops when a first demodulation signal generation circuit is operated. The selective circuit includes an inverter circuit, a flip-flop circuit, and a selector circuit. When the second demodulation signal generation circuit has a comparator and the like, power consumption thereof is reduced. Detailed Description: TECHNICAL FIELD The present invention relates to semiconductor devices. In particular, the present invention relates to semiconductor devices which can transmit and receive information without contact by utilizing wireless communication. BACKGROUND ART In recent years, individual recognition technology in which individual identification information is given to an individual object to clarify information such as a history of the object has attracted attention. In particular, the development of semiconductor devices which can transmit and receive data without contact by utilizing wireless communication through a radio wave has been advanced. Such semiconductor devices are referred to as an IC tag, an RFID tag, and the like, which have begun to be used for management of articles in markets, or the like. In general, many of objects which are referred to as an RFID tag and the like that have been put into practical use include an element formation layer and an antenna layer having a circuit formed of a transistor or the like. Such semiconductor devices capable of wireless communication perform wireless communication with a reader/writer through an electromagnetic wave, so that the semiconductor devices can be operated by receiving power from a power supply and data from the reader/writer. In wireless communication between the reader/writer and the semiconductor device, in general, a transmission side device (a reader/writer) transmits a modulated carrier wave and a reception side device (a semiconductor device) demodulates the carrier wave, so that data is extracted and information is transmitted and received. In the semiconductor devices capable of wireless communication, there is an amplitude modulation method (an amplitude shift keying (ASK) modulation method) as one of methods which modulate a carrier wave. An ASK modulation method is a method which transmits information by generation of a difference in amplitude of a carrier wave and use of this amplitude difference as a modulation signal. Here, when an amplitude in a low state (a difference between a signal line (an amplitude peak) and a reference line (an amplitude center) is a and an amplitude in a high state (a difference between a signal line (an amplitude peak) and a reference line (an amplitude center) is b, a modulation factor m can be expressed as m=(b−a)/(b+a). The transmission side device can decide a modulation factor by a method in accordance with both the transmission side device and the reception side device which perform wireless communication. The reception side device receives a modulation signal of which modulation factor is decided by the transmission side device, and demodulates the modulation signal. Since the semiconductor device capable of wireless communication includes an integrated circuit provided with a minute semiconductor element, a problem of variation or the like arises and it has been difficult to manufacture a semiconductor device having favorable electric characteristics. However, a semiconductor device having favorable electric characteristics has nearly been realized with various improvements (for example, see Patent Document 1: Japanese Published Patent Application No. 2006-268838). Note that the semiconductor device capable of wireless communication performs transmission, reception, and the like of a signal in accordance with a communication method based on various standards as communication thereof. With a communication method which is standardized with ISO/IEC 15693 which is a standard of a vicinity-type wireless IC card, a 13.56 MHz carrier wave is modulated in order to obtain a modulation factor of 100% or 10%, and data is encoded with a pulse position modulation method which identifies data by change of a modulation position of a pulse position. There are ISO/IEC14443 (TYPE-A) and ISO/IEC18000-3 as standards similar to ISO/IEC 15693. In ISO/IEC14443 (TYPE-A), it is prescribed that a carrier wave of which modulation factor is 100% is expressed with an amplitude of which initial amplitude (an amplitude in a state without modulation) is less than or equal to 5%. Note that a communication frequency of these standards is 13.56 MHz. Further, various means can be considered in order to demodulate a signal of which modulation factor is 10% (for example, see Patent Document 2: Japanese Published Patent Application No. 2000-172806). DISCLOSURE OF INVENTION In general, a reception side device includes an analog circuit having a demodulation circuit, a power supply circuit, a modulation circuit, and the like, and a digital circuit connected to the analog circuit. As an output of the demodulation circuit, a demodulation signal is outputted from the analog circuit and inputted into the digital circuit. When a carrier wave of which modulation factor is 100% is used for wireless communication, a state in which an amplitude is 0 (a state in which an amplitude peak and a reference line accord with each other) is included. Therefore, in a semiconductor device capable of wireless communication which operates by generating power from a power supply through a received electromagnetic wave, it is difficult to supply power from a power supply when an amplitude of a carrier wave of which modulation factor is 100%, which is used for wireless communication, is 0. Accordingly, the operation of the semiconductor device is interfered. In such a semiconductor device, a certain amplitude is secured so as to supply power with the use of a carrier wave of which modulation factor is small (for example, a carrier wave of which modulation factor is 10%); thus, the semiconductor device can be operated. FIG. 4 illustrates a circuit configuration of a general demodulation circuit which demodulates a carrier wave of which modulation factor is 100%. A circuit of FIG. 4 includes a first diode, a second diode, a first resistor, a second resistor, a first capacitor, a second capacitor, and a third capacitor. In the circuit illustrated in FIG. 4, an input portion is connected to one end of the first capacitor. The other end of the first capacitor is connected to an anode (a first electrode) of the first diode and a cathode (a second electrode) of the second diode. A cathode (a second electrode) of the first diode is connected to each of one ends of the first resistor, the second resistor, and the second capacitor. An anode (a first electrode) of the second diode is grounded. Each of the other ends of the first resistor and the second capacitor are also grounded. The other end of the second resistor is connected to one end of the third capacitor and an output portion. The other end of the third capacitor is grounded. Although the circuit illustrated in FIG. 4 can demodulate a carrier wave of which modulation factor is large (for example, a carrier wave of which modulation factor is 100%), it is difficult to demodulate a carrier wave of which modulation factor is small (for example, a carrier wave of which modulation factor is 10%). This is because the demodulation circuit of FIG. 4 has large influence of noise, which results from a carrier wave, on an amplitude waveform, and this influence cannot be disregarded when a modulation factor thereof is small (for example, when the modulation factor is 10%). Therefore, the noise can be reduced by employment of a low-pass filter or the like for the demodulation circuit; however, the noise is not sufficiently reduced. Thus, the present invention provides a semiconductor device having a circuit which can generate a demodulation signal (a demodulation circuit generation circuit) without any problem also as to a modulation signal of which modulation factor is small (for example, a signal of which modulation factor is 10%). Note that the following are provided in a circuit configuration proposed in Patent Document 2: a first demodulation means which regenerates data from a (IS014443-A) 100% ASK signal (a signal of which modulation factor is 100%); a second demodulation means which regenerates data from a (IS014443-B) 10% ASK signal (a signal of which modulation factor is 10%); and a selector means which selects each of regeneration signals. Further, in order to control the selector means, a means which generates a selective control signal by input of the regeneration signal and a transmission signal of the first demodulation means is provided. According to the configuration of Patent Document 2, a means which regenerates data that is not selected by the selector means can be said as a useless circuit in terms of operation of a semiconductor device. In particular, it is apparent that an amplifier circuit is incorporated into the second demodulation means which regenerates data from a 10% ASK signal (a signal of which modulation factor is 10%). Thus, when power consumed in the amplifier circuit is as large as one which cannot be disregarded as compared with consumption power of the whole semiconductor device, this will cause to deteriorate performance of the semiconductor device. Thus, the present invention provides a semiconductor device in which, when data of a signal of which modulation factor is large (for example, a signal of which modulation factor is 100%) is selected, the operation of the amplifier circuit which is incorporated into the second demodulation means which regenerates data of a signal of which modulation factor is small (a signal of which modulation factor is 10%) is stopped and low power is consumed. In the meantime, the demodulation circuit illustrated in FIG. 4 has a simple configuration, in which operation of a semiconductor device is not interfered. Therefore, the demodulation circuit is appropriate as a demodulation signal generation circuit for demodulating a signal of which modulation factor is large (for example, a signal of which modulation factor is 100%). There is a case where a configuration appropriate for operation is different between the case where a carrier wave of which modulation factor is small (for example, the case where a modulation factor is 10%) and the case where a carrier wave of which modulation factor is large (for example, the case where a modulation factor is 100%). For example, when a carrier wave of which modulation factor is 100% is demodulated using a circuit which demodulates a demodulation signal of which modulation factor is 10%, there is a fear that an unnecessary element is operated and power is consumed uselessly. Thus, the present invention provides a semiconductor device in which a circuit which generates a demodulation circuit in the case where a carrier wave of which modulation factor is small (for example, the case where a modulation factor is 10%) and a circuit which generates a demodulation circuit in the case where a carrier wave of which modulation factor is large (for example, the case where a modulation factor is 100%) are separately provided. Further, the present invention provides a semiconductor device which can identify a modulation factor, switch a circuit which is used depending on a modulation factor, stop part of operation of a circuit which is not used, and generate a demodulation signal which is appropriate depending on a modulation factor with minimum power. A semiconductor device of the present invention includes one or a plurality of demodulation signal generation circuits, and any of the demodulation signal generation circuits has a first demodulation circuit which demodulates a modulation signal, a second demodulation circuit which demodulates an electric signal (a modulation signal) which has a polarity opposite to that of an electric signal in the first demodulation circuit, and a comparator. A demodulation signal outputted from the first demodulation circuit and a demodulation signal outputted from the second demodulation circuit are each inputted into an input portion of the comparator, whereby a voltage difference of these demodulation signals is obtained. In the above semiconductor device, a difference between an amplitude of the signal demodulated by the first demodulation circuit and an amplitude of the signal demodulated by the second demodulation circuit is obtained by the comparator. Since the amplitude of the signal demodulated by the first demodulation circuit and the amplitude of the signal demodulated by the second demodulation circuit have the same phase, influence of noise, which results from a carrier wave, can be reduced to demodulate the signals stably. Alternatively, a semiconductor device of the present invention preferably has a selective circuit which selects either a first demodulation signal generation circuit or a second demodulation signal generation circuit depending on a modulation signal to stop the other demodulation signal generation circuit. Specifically, the semiconductor device of the present invention includes the following: the first demodulation signal generation circuit which generates a demodulation signal from a carrier wave of which modulation factor is large (for example, a carrier wave of which modulation factor is 100%); the second demodulation signal generation circuit which generates a demodulation signal from a carrier wave of which modulation factor is small (for example, a carrier wave of which modulation factor is 10%); and the selective circuit which selects, depending on a modulation factor, which of the first demodulation signal generation circuit and the second demodulation signal generation circuit is used. The selective circuit includes a logic element that identifies a difference between modulation factors and a logic element group that determines a demodulation signal generation circuit to be used. First, in the semiconductor device of the present invention, the first demodulation signal generation circuit corresponding to a carrier wave of which modulation factor is large (for example, a carrier wave of which modulation factor is 100%) outputs a first demodulation signal, and the second demodulation signal generation circuit corresponding to a carrier wave of which modulation factor is small (a carrier wave of which modulation factor is 10%) outputs a second demodulation signal. That is, the first demodulation signal generation circuit can demodulate a carrier wave of which modulation factor is large (for example, a carrier wave of which modulation factor is 100%), and the second demodulation signal generation circuit can demodulate a carrier wave of which modulation factor is small (for example, a carrier wave of which modulation factor is 10%). Further, it is not assured that the first demodulation signal generation circuit demodulates a carrier wave of which modulation factor is small (for example, a carrier wave of which modulation factor is 10%) and the second demodulation signal generation circuit demodulates a carrier wave of which modulation factor is large (for example, a carrier wave of which modulation factor is 100%). In a digital circuit, the first demodulation signal is monitored and, if the first demodulation signal is effective, the signal is transmitted to an amplitude circuit (for example, a comparator or the like) which is included in the second demodulation signal generation circuit and the circuit operation is stopped. The first demodulation signal generation circuit is appropriate for demodulating a carrier wave of which modulation factor is large (for example, a carrier wave of which modulation factor is 100%). However, in a carrier wave of which modulation factor is small (for example, a carrier wave of which modulation factor is 10%), there is a carrier wave having an amplitude of a certain degree (for example, an amplitude of which degree is 90%) even during a modulated period, as compared with an amplitude during an unmodulated period. Therefore, it is difficult for the first demodulation signal generation circuit to demodulate a carrier wave of which modulation factor is small. Whether the first demodulation signal can be demodulated or not is determined using a logic element (for example, an inverter), and other signals (for example, a clock signal) is not necessary. The clock signal is a periodic signal which is used in operating the digital circuit or the like. In general, a clock is generated from an oscillation circuit, a frequency division circuit, or the like. Note that the logic element refers to an element formed of a plurality of circuits which are provided in order to achieve a certain object in the digital circuit, in this specification. Note that “the case where a modulation factor is 10%” and “the case where a modulation factor is 100%” are described in this specification; however, a range of a modulation factor which is approximately greater than or equal to 10% and less than or equal to 30% is typically described as “the case where a modulation factor is 10%”. In addition, a range of a modulation factor which is approximately greater than or equal to 90% and less than or equal to 100% is typically described as “the case where a modulation factor is 100%”. Thus, a modulation factor should not be interpreted as being strictly limited to the figures which are described and all modulation factors can be applied within a scope that does not depart from the meaning of the present invention. With the use of the present invention, a demodulation signal of a modulation signal of which modulation factor is small (for example, a modulation signal of which modulation factor is 10%) can be generated. Therefore, a semiconductor device capable of wireless communication can be operated even when the modulation signal of which modulation factor is small is used, and power from a power supply is continuously supplied during reception of a wireless signal. Thus, the semiconductor device can be operated stably. Further, in a semiconductor device of the present invention, influence of noise, which results from a carrier wave, can be reduced; thus, a highly reliable demodulation signal can be generated stably. In a semiconductor device of the present invention, different demodulation signal generation circuits are used in the cases of a carrier wave of which modulation factor is small (for example, a carrier wave of which modulation factor is 10%) and a carrier wave of which modulation factor is large (for example, a carrier wave of which modulation factor is 100%). Therefore, as to a parameter of an element included in each of the demodulation signal generation circuits, it is not necessary to take into consideration even the case where a modulation factor is different; thus, flexibility in designing the semiconductor device is improved. Further, in the second demodulation signal generation circuit, the second demodulation signal is generated by detection of a difference between an output of a first bias circuit and an output of a second bias circuit in the second demodulation signal generation circuit. Therefore, even with a signal of which modulation factor is small, a demodulation signal can be generated stably. Accordingly, information can be transmitted and received. When a signal of which modulation factor is small is used, power from a power supply is continuously supplied; therefore, the semiconductor device can be operated stably. Noise that exists in each of the outputs of the first bias circuit and the second bias circuit has the same phase. In the present invention, the second demodulation signal is generated by comparison of the outputs of the first bias circuit and the second bias circuit. Therefore, the noise of each of the outputs is cancelled, and influence of noise, which results from a carrier wave, is reduced; thus, a signal can be demodulated. Consequently, as to a wireless signal of which modulation factor is small (for example, a carrier wave of which modulation factor is 10%), the signal can be also detected stably. In the case where a carrier wave of which modulation factor is small (for example, the case where a modulation factor is 10%) and the case where a carrier wave of which modulation factor is large (for example, the case where a modulation factor is 100%), power consumption of the semiconductor device of the present invention can be reduced by switching the demodulation signal generation circuit to be used and stopping part of operation of the circuit which is not used. According to the present invention, a demodulation signal is monitored in the digital circuit only using the shape of a waveform of the first demodulation signal; therefore, the semiconductor of the present invention can be realized with a simple circuit configuration without the necessity of a complicated circuit. BRIEF DESCRIPTION OF DRAWINGS In the accompanying drawings: FIG. 1 is a diagram illustrating a semiconductor device of the present invention; FIG. 2 is a diagram illustrating a semiconductor device of the present invention; FIG. 3 is a diagram illustrating a semiconductor device of the present invention; FIG. 4 is a diagram illustrating a semiconductor device of the present invention; FIG. 5 is a diagram illustrating a semiconductor device of the present invention; FIGS. 6A to 6C (6C-1 to 6C-3) are diagrams each illustrating a semiconductor device of the present invention; FIGS. 7A (7A-1 and 7A-2) and 7B (7B-1 and 7B-2) are diagrams each illustrating a semiconductor device of the present invention; FIG. 8 is a diagram illustrating a semiconductor device of the present invention; FIGS. 9A to 9C are diagrams each illustrating a semiconductor device of the present invention; FIGS. 10A and 10B are diagrams each illustrating a semiconductor device of the present invention; FIG. 11 is a diagram illustrating a semiconductor device of the present invention; FIGS. 12A to 12E are views each illustrating a semiconductor device of the present invention; FIGS. 13A to 13F are views each illustrating an example in which a semiconductor device of the present invention is mounted; FIG. 14 is a diagram illustrating a semiconductor device of the present invention; FIGS. 15A to 15D are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 16A to 16C are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 17A and 17B are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 18A and 18B are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 19A and 19B are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 20A to 20C are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 21A to 21C are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 22A and 22B are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 23A to 23C are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 24A to 24C are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 25A to 25C are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 26A and 26B are views illustrating a manufacturing method of a semiconductor device to which the present invention is applied; FIGS. 27A and 27B are waveforms illustrating each portion of a semiconductor device to which the present invention is applied; FIGS. 28A and 28B are waveforms illustrating each portion of a semiconductor device to which the present invention is applied; FIGS. 29A and 29B are waveforms illustrating each portion of a semiconductor device to which the present invention is applied; FIG. 30 is a diagram illustrating a semiconductor device of the present invention; FIG. 31 is a diagram illustrating a semiconductor device of the present invention; FIGS. 32A and 32B are waveforms illustrating each portion of a semiconductor device to which the present invention is applied; and FIGS. 33A and 33B are waveforms illustrating each portion of a semiconductor device to which the present invention is applied. BEST MODE FOR CARRYING OUT THE INVENTION Embodiment modes and an embodiment of the present invention will be hereinafter described with reference to the accompanying drawings. However, the present invention can be implemented in various modes, and it is easily understood by those skilled in the art that modes and details thereof can be modified in various ways without departing from the meaning and the scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiment modes and an embodiment below. Note that the same reference numeral is used in common to denote the same component in different drawings in structures of the present invention described below. Embodiment Mode 1 This embodiment mode will describe an example of a structure of a semiconductor device of the present invention which includes a demodulation signal generation circuit with reference to drawings. FIG. 2 illustrates a block diagram of a semiconductor device of the present invention. A semiconductor device 100 of the present invention transmits and receives data wirelessly to and from a reader/writer 116 by an electromagnetic wave. The reader/writer 116 is preferably connected to a control device 120 through a communication line 118. The control device 120 controls communication between the reader/writer 116 and the semiconductor device 100. The semiconductor device 100 includes an antenna circuit 102, a power supply circuit 112, an analog circuit 104, a digital circuit 106, and a memory circuit 108. The analog circuit 104 has a demodulation signal generation circuit 150 and a modulation circuit 114. Alternatively, the semiconductor device 100 does not include an antenna but does include a wiring used to connect to an external antenna. The wiring and the external antenna may be connected with each other. In this case, the antenna which is separately manufactured is connected to the wiring. A connection terminal (a terminal electrode) which is electrically connected to the wiring may be used to connect the wiring and the antenna. Further, the semiconductor device 100 is not limited to the above structure, and may include a clock generation circuit, a central processor unit (hereinafter referred to as a CPU), or the like. Note that the clock generation circuit refers to a circuit which generates and supplies to each circuit a clock signal having a frequency necessary for operations of the digital circuit 106, the memory circuit 108, and the like based on an AC induced voltage which is generated in the antenna circuit 102. An oscillation circuit or a frequency division circuit may be used for the clock generation circuit. The antenna circuit 102 preferably having an antenna and a rectifier circuit receives an electromagnetic wave, which is transmitted from the reader/writer 116, and generates an AC induced voltage. The induced voltage becomes power from a power supply of the semiconductor device 100 and also includes data transmitted from the reader/writer 116. The shape of the antenna that can be used for the present invention is not particularly limited. Therefore, a signal transmission method applied to the antenna circuit 102 included in the semiconductor device 100 can be an electromagnetic coupling method, an electromagnetic induction method, a radio wave method, or the like. The transmission method may be selected as appropriate by a practitioner in consideration of the intended use of the device. Thus, an antenna with an optimum length and shape may be provided in accordance with the transmission method. In the present invention, an electromagnetic induction method having a communication frequency of 13.56 MHz is preferably used as the signal transmission method. In the case of applying an electromagnetic coupling method or an electromagnetic induction method (for example, a 13.56 MHz band) as the transmission method, a conductive film which functions as the antenna is formed in an annular form (for example, a loop antenna) or a helical form (for example, a spiral antenna) in order to utilize electromagnetic induction that occurs with changes in magnetic density. In the case of using a microwave method (for example, UHF band (860 to 960 MHz), 2.45 GHz band, or the like) which is one kind of radio wave methods as the transmission method, the length and shape of the conductive film which functions as the antenna may be determined as appropriate in consideration of the wavelength of radio waves used for the signal transmission. For example, the conductive film which functions as the antenna may be formed in a linear form (for example, a dipole antenna), a flat form (for example, a patch antenna), or the like. Further, the shape of the conductive film which functions as the antenna is not limited to the linear form, and the conductive film may be provided in a curved form, a serpentine form, or a form combining them in consideration of the wavelength of the radio waves. FIGS. 12A to 12E each illustrate an example of the shape of the antenna provided in the antenna circuit 102. For example, as illustrated in FIG. 12A, a layout may be used in which an antenna 1201 is disposed all around a chip 1200 provided with a signal processing circuit. Alternatively, as illustrated in FIG. 12B, a layout may be used in which a chip 1202 provided with a signal processing circuit is coiled around by a thin antenna 1203. Further, as illustrated in FIG. 12C, a layout may be used in which an antenna of which shape is like that of an antenna 1205 for receiving high-frequency electromagnetic waves is disposed for a chip 1204 provided with a signal processing circuit. Alternatively, as illustrated in FIG. 12D, a layout may be used in which an antenna of which shape is like that of an antenna 1207 which is 180-degree omnidirectional (such that it can receive signals equally from any direction) is disposed for a chip 1206 provided with a signal processing circuit. As a further alternative, as illustrated in FIG. 12E, a layout may be used in which an antenna of which shape is like that of an antenna 1209 with a long rod shape is disposed for a chip 1208 provided with a signal processing circuit. The antenna circuit 102 may be formed by combination of the antennas with the above shapes. In FIGS. 12A to 12E, a connection method between the chip 1200 or the like provided with a signal processing circuit and the antenna 1201 or the like is not particularly limited as long as a signal can be transmitted and received between the chip and the antenna. By giving FIG. 12A as an example, the antenna 1201 and the chip 1200 provided with a signal processing circuit are connected to each other by wire bonding or bump bonding. Alternatively, part of the chip may be used as an electrode to be attached to the antenna 1201. With this method, the chip 1200 can be attached to the antenna 1201 with the use of an anisotropic conductive film (hereinafter referred to as ACF). Further, an appropriate length of the antenna differs depending on the frequency of a signal to receive. In general, in the case where, for example, a frequency of 2.45 GHz is used, the length of the antenna may be approximately 60 nm (a half of the wavelength) or approximately 30 mm (a quarter of the wavelength). The power supply circuit 112 rectifies an induced voltage, which is generated in the antenna circuit 102, by a diode or the like, and stabilizes the induced voltage with the use of a capacitor, thereby adjusting so as to maintain a stable potential having a certain potential difference from a reference potential (a potential of a reference line). The digital circuit 106 performs the following operations based on a demodulated signal: analyzing instructions; controlling the memory circuit 108; outputting data for external transmission to the modulation circuit 114; and the like. The digital circuit 106 may include a decoding circuit, an information judging circuit, or the like, in addition to a generation circuit of a memory control signal. Further, the digital circuit 106 may include a circuit which converts part or all of data extracted from the memory circuit 108, which is transmitted from the semiconductor device 100 to the reader/writer 116, into an encoded signal. The memory circuit 108 stores at least specific data (individual identification information) of the semiconductor device 100. The memory circuit 108 includes a control circuit, which performs writing or reading of data in accordance with the digital circuit 106, and a circuit having a memory element. The memory circuit 108 includes one or more of an organic memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), a ferroelectric random access memory (FeRAM), a mask read-only memory (ROM), a programmable read only memory (PROM), an electrically programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), and a flash memory. As long as the memory content of the memory circuit 108 is specific data (individual identification information or the like) of the semiconductor device 100, a nonvolatile memory which can store memory without being supplied with power is preferably used. On the other hand, as long as temporary memory is used in processing performed by the semiconductor device 100 is stored, a volatile memory may be used. Particularly in the case of a so-called passive type in which the semiconductor device 100 has no battery, a nonvolatile memory is preferably used as the memory circuit 108. The organic memory has a structure in which a layer containing an organic compound is sandwiched between a pair of conductive layers, which has at least two advantages because the structure is simple. One advantage is that a manufacturing process can be simplified and that the cost can be reduced. The other advantage is that it is easy to reduce the area of the memory circuit and increase in capacitor can be realized easily. Therefore, it is preferable to use the organic memory for the memory circuit 108. The modulation circuit 114 transmits load modulation to the antenna circuit 102 based on a signal from the digital circuit 106. The demodulation signal generation circuit 150 demodulates and extracts data included in the induced voltage which is generated in the antenna circuit 102. In the semiconductor device of this embodiment mode, an electromagnetic wave from the reader/writer is received and power by the electromagnetic wave is supplied to drive the semiconductor device. Therefore, although a passive-type semiconductor device is described in this embodiment mode, the present invention is not limited thereto. As a structure in which a battery is contained inside the semiconductor device, power may be supplied from a battery to drive the semiconductor device. In the electromagnetic wave transmitted from the reader/writer, a carrier wave having a certain frequency is modulated from a sub-carrier wave. A signal included in the sub-carrier wave is a binarized digital signal which is transmitted to the semiconductor device from the reader/writer. As to a modulation method of the carrier wave, there are an amplitude shift keying (ASK) modulation method which changes amplitude and a frequency shift keying (FSK) modulation method which changes a frequency. This embodiment mode describes the case in which an electromagnetic wave modulated by the ASK modulation method is demodulated. The demodulation signal generation circuit 150 included in the semiconductor device 100 of the present invention is described with reference to FIG. 30. FIG. 30 illustrates a block diagram of the demodulation signal generation circuit 150 which can be used for this embodiment mode. The demodulation signal generation circuit 150 includes a first demodulation circuit 154, a second demodulation circuit 156, a first bias circuit 158, a second bias circuit 160, and a comparator 162. Although these circuits included in the demodulation signal generation circuit 150 are described below, the present invention is not limited thereto. An input portion 152 of the demodulation signal generation circuit 150 illustrated in FIG. 30 is connected to an input portion 600 of the first demodulation circuit 154 and an input portion 620 of the second demodulation circuit 156. An output portion 616 of the first demodulation circuit 154 is connected to an input portion 800A of the first bias circuit 158, and an output portion 636 of the second demodulation circuit 156 is connected to an input portion 800B of the second bias circuit 160. An output portion 808A of the first bias circuit 158 is connected to a first input portion 900A of the comparator 162, and an output portion 808B of the second bias circuit 160 is connected to a second input portion 900B of the comparator 162. An output portion 912 of the comparator 162 is connected to an output portion 166 of the demodulation signal generation circuit 150. Note that the output portion 912 of the comparator 162 and the output portion 166 of the demodulation signal generation circuit 150 are preferably connected to each other through an analog buffer circuit 164 as illustrated in FIG. 30. As the analog buffer circuit 164, a source follower circuit, a common source amplifier circuit, and the like can be given. Noise can be removed more effectively and a demodulation signal can be generated stably by provision of the analog buffer circuit 164. FIGS. 6A to 6C (6C-1 to 6C-3) each illustrate an example of a configuration of a demodulation circuit which is used as each of the first demodulation circuit 154 and the second demodulation circuit 156. FIG. 6A illustrates the first demodulation circuit 154. The first demodulation circuit 154 includes the input portion 600, the output portion 616, a first diode 604, a second diode 606, a first resistor 608, a second resistor 612, a first capacitor 602, a second capacitor 610, and a third capacitor 614. The input portion 600 is connected to one end of the first capacitor 602. The other end of the first capacitor 602 is connected to an anode of the first diode 604 and a cathode of the second diode 606. A cathode of the first diode 604 is connected to each of one ends of the first resistor 608, the second capacitor 610, and the second resistor 612. The other end of the second resistor 612 is connected to one end of the third capacitor 614 and the output portion 616. Further, an anode of the second diode 606, each of the other ends of the first resistor 608, the second capacitor 610, and the third capacitor 614 are connected to a reference potential (VSS). FIG. 6B illustrates the second demodulation circuit 156. The demodulation circuit illustrated in FIG. 6B includes the input portion 620, the output portion 636, a first diode 624, a second diode 626, a first resistor 628, a second resistor 632, a first capacitor 622, a second capacitor 630, and a third capacitor 634. The input portion 620 is connected to one end of the first capacitor 622. The other end of the first capacitor 622 is connected to a cathode of the first diode 624 and an anode of the second diode 626. An anode of the first diode 624 is connected to each one ends of the first resistor 628, the second capacitor 630, and the second resistor 632. The second resistor 632 is connected to one end of the third capacitor 634 and the output portion 636. Further, a cathode of the second diode 626, each of the other ends of the first resistor 628, the second capacitor 630, and the third capacitor 634 are connected to a reference potential (VSS). Each of the first diode 604, the second diode 606, the first diode 624, and the second diode 626 of FIGS. 6A and 6B may be formed of a diode-connected TFT. A diode illustrated in FIG. 6C-1, a diode-connected n-type TFT illustrated in FIG. 6C-2, and a diode-connected p-type TFT illustrated in FIG. 6C-3 are equivalent as a circuit. FIGS. 7A (7A-1 and 7A-2) each illustrate an example in which a circuit 618, which is part of the first demodulation circuit 154, illustrated in FIG. 6A is formed using any of the TFTs illustrated in FIGS. 6C (6C-1 to 6C-3). Similarly, FIGS. 7B (7B-1 and 7B-2) each illustrate an example in which a circuit 638, which is part of the second demodulation circuit 156, illustrated in FIG. 6B is formed using any of the TFTs illustrated in FIGS. 6C (6C-1 to 6C-3). In the circuit illustrated in FIG. 7A-1, n-type TFTs 700 and 702 are used as diode-connected TFTs. In the circuit illustrated in FIG. 7A-2, p-type TFTs 704 and 706 are used as diode-connected TFTs. In the circuit illustrated in FIG. 7B-1, n-type TFTs 708 and 710 are used as diode-connected TFTs. In the circuit illustrated in FIG. 7B-2, p-type TFTs 712 and 714 are used as diode-connected TFTs. The first demodulation circuit 154 and the second demodulation circuit 156 may be formed by combination of the circuits illustrated in FIGS. 6A to 6C (6C-1 to 6C-3) and FIGS. 7A (7A-1 and 7A-2) and 7B (7B-1 and 7B-2). The first demodulation circuit 154 having the circuit 618 illustrated in FIG. 7A-1 and the second demodulation circuit 156 having the circuit 638 illustrated in FIG. 7B-2 may be used, or the first demodulation circuit 154 having the circuit 618 illustrated in FIG. 7A-2 and the second demodulation circuit 156 having the circuit 638 illustrated in FIG. 7B-1 may be used. Alternatively, the first demodulation circuit 154 having the circuit 618 illustrated in FIG. 7A-2 and the second demodulation circuit 156 having the circuit 638 illustrated in FIG. 7B-2 may be used. Preferably, the circuit 618 illustrated in FIG. 7A-1 is used for the first demodulation circuit 154, and the circuit 638 illustrated in FIG. 7B-1 is used for the second demodulation circuit 156. In general, carriers of an n-type TFT have higher mobility than those of a p-type TFT. Therefore, n-type TFTs are used for all TFTs included in the first demodulation circuit and the second demodulation circuit, so that operation performance of the circuits can be improved. The first capacitor 602 (or the first capacitor 622) is provided to compensate center of a wave amplitude (a reference line). The first resistor 608 (or the first resistor 628) is provided to make constant current flowing through a point b1 (or a point b2). Further, the second capacitor 610 (or the second capacitor 630) is provided to smooth a waveform. The resistance of the first resistor 608 (or the first resistor 628) is adjusted as appropriate depending on the degree of electrostatic capacitance of the second capacitor 610 (or the second capacitor 630). When the resistance of the first resistor 608 (or the first resistor 628) is small, an amplitude of the carrier wave is reduced; and when the resistance is excessive, a breakdown phenomenon of the second diode 606 (or the second diode 626) occurs; thus, the semiconductor device does not operate normally. Furthermore, the second resistor 612 (or the second resistor 632) and the third capacitor 614 (or the third capacitor 634) function as a low-pass filter which removes a high-frequency component. FIG. 8 illustrates an example of a configuration of the first bias circuit 158 and the second bias circuit 160. In a bias circuit illustrated in FIG. 8, an input portion 800 (the input portion 800 is hereinafter referred to as the input portion 800A and the input portion 800B in the first bias circuit and the second bias circuit, respectively) is connected to one end of a capacitor 802 (the capacitor 802 is hereinafter referred to as a capacitor 802A and a capacitor 802B in the first bias circuit and the second bias circuit, respectively). The other end of the capacitor 802 is connected to an output portion 808 (the output portion 808 is hereinafter referred to as the output portion 808A and the output portion 808B in the first bias circuit and the second bias circuit, respectively), and each of one ends of a first resistor 804 (the first resistor 804 is hereinafter referred to as a first resistor 804A and a first resistor 804B in the first bias circuit and the second bias circuit, respectively) and a second resistor 806 (the second resistor 806 is hereinafter referred to as a second resistor 806A and a second resistor 806B in the first bias circuit and the second bias circuit, respectively). The other end of the first resistor 804 is connected to a power supply potential (VDD), and the other end of the second resistor 806 is connected to a reference potential (VSS). The capacitor 802 is provided to isolate the input portion 800 galvanically from the power supply potential to which the first resistor 804 is connected. The first resistor 804 and the second resistor 806 are provided to generate a difference between potentials of signals which are inputted into the first input portion 900A and the second input portion 900B included in the comparator 162. It is preferable that resistance R1A of the first resistor 804A, resistance R1B of the first resistor 804B, resistance R2A of the second resistor 806A, and resistance R2B of the second resistor 806B be R1A=R2B≠R1B=R2A. Malfunction in the comparator 162 can be prevented by inclusion of the first bias circuit 158 and the second bias circuit 160. FIGS. 9A to 9C each illustrate an example of a configuration of the comparator 162. The comparator 162 includes two input portions such as a differential circuit, a differential amplifier, or an operational amplifier, and a circuit having a function to compare two signals inputted into the input portions can be used. The comparator 162 includes the first input portion 900A, the second input portion 900B, a first TFT 902 to a fifth TFT 910, and an output portion 912. In the comparator 162, the first input portion 900A is connected to the output portion 808A of the first bias circuit 158, and the second input portion 900B is connected to the output portion 808B of the second bias circuit 160. The first input portion 900A is connected to a gate electrode of the first TFT 902, and the second input portion 900B is connected to a gate electrode of the second TFT 904. One of a source electrode and a drain electrode of the first TFT 902 is connected to one of a source electrode and a drain electrode of the fifth TFT 910 and one of a source electrode and a drain electrode of the second TFT 904. The other of the source electrode and drain electrode of the first TFT 902 is connected to one of a source electrode and a drain electrode of the third TFT 906, a gate electrode of the third TFT 906, and a gate electrode of the fourth TFT 908. The other of the source electrode and drain electrode of the third TFT 906 is connected to a power supply potential (VDD). One of a source electrode and a drain electrode of the fourth TFT 908 is connected to the power supply potential (VDD). The other of the source electrode and drain electrode of the fourth TFT 908 is connected to the output portion 912 and the other of the source electrode and drain electrode of the second TFT 904. A gate electrode of the fifth TFT 910 is connected to a constant current circuit 1003 through a wiring 914. The other of the source electrode and drain electrode of the fifth TFT 910 is connected to a reference potential (VSS). Note that the wiring 914 is connected to the constant current circuit 1003. In FIG. 9A, a sixth TFT 916 is constantly turned on or not provided. Operation when a signal is inputted into the first input portion 900A and the second input portion 900B of the comparator 162 is described. A current which flows through the fifth TFT 910 which is a constant current source of the comparator 162 is set Id. Here, since the third TFT 906 and the fourth TFT 908 form a current mirror circuit, a current of Id/2 flows between the source electrode and the drain electrode of each of the third TFT 906 and the fourth TFT 908. In addition, a potential of each of points a illustrated in FIGS. 9A to 9C is set V5. Here, the case where a different potential is applied to two TFTs which form a differential pair is described. First, the case where a potential of the first input portion 900A is higher than a potential of the second input portion 900B is considered. A current which flows through the first TFT 902 and the second TFT 904 is expressed in the following formula (1). Here, Vgs is a gate voltage; Vds, a drain voltage; Vth, a threshold voltage; k, a transconductance coefficient; and λ, a channel length modulation coefficient. I ds = I d 2 = k  ( V gs - V th ) 2  ( 1 + λ · V ds ) [ FORMULA   1 ] Since a potential of the first input portion 900A is higher than a potential of the second input portion 900B
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