Title of Invention: Vertical memory devices having dummy channel regions Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions. Detailed Description: Part general_description_paragraphs: Part CROSS-REFERENCE TO RELATED APPLICATION: This application claims priority under 35 U.S.C. §119 from Korean Patent Application No. 10-2015-0111358 filed on Aug. 7, 2015 in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference in its entirety. Part BACKGROUND: A demand exists for memory devices that have an increased integration density. One method for increasing the integration of a memory device is to use vertical transistor structures instead of planar transistor structures in the memory device. Part SUMMARY: Aspects of the inventive concepts provide highly integrated vertical memory devices that may have improved breakdown voltage characteristics. According to aspect of the inventive concepts, a semiconductor device includes a semiconductor substrate; a gate electrode layer structure that includes a plurality of spaced-apart gate electrode layers stacked on an upper surface of the semiconductor substrate; a plurality of channel regions penetrating the gate electrode layers; a plurality of dummy channel regions penetrating at least the lowermost of the gate electrode layers; and a substrate insulating layer between the semiconductor substrate and the dummy channel regions. According to another aspect of the inventive concepts, a semiconductor device includes a semiconductor substrate having an upper surface that defines a horizontal plane; a gate electrode layer structure that includes a plurality of gate electrode layers and a plurality of insulating layers that are alternately stacked in a vertical direction on the upper surface of the semiconductor substrate; a plurality of dummy channel regions that penetrate the gate electrode layer structure, the dummy channel regions comprising respective annular channel layers that penetrate a lowermost of the gate electrode layers; and a plurality of channel regions that penetrate the gate electrode layer structure, the channel regions comprising respective epitaxial patterns on the semiconductor substrate and respective annular channel regions on an upper surface of the respective epitaxial patterns, wherein the dummy channel regions are spaced-apart from the semiconductor substrate. According to yet another aspect of the inventive concepts, a semiconductor memory device includes a semiconductor substrate having an upper surface that has a plurality of recesses therein; a substrate insulating layer that includes a plurality of substrate insulating patterns in the respective recesses; a gate electrode layer structure on the upper surface of the semiconductor substrate; and a plurality of dummy channel regions vertically penetrating the gate electrode layer structure, wherein the dummy channel regions directly contact the substrate insulating layer. According to another aspect of the inventive concepts, a memory device may include: a substrate; a plurality of gate electrode layers and a plurality of insulating layers stacked on an upper surface of the substrate, the gate electrode layers extending different lengths in a first direction that is parallel to the upper surface of the substrate; a plurality of channel regions, each of the channel regions extending in a second direction that is perpendicular to the upper surface of the substrate to penetrate at least some of the gate electrode layers and insulating layers, the channel regions being adjacent first ends of the gate electrode layers; a plurality of dummy channel regions adjacent second ends of the gate electrode layers; and a substrate insulating layer between the dummy channel regions and the substrate. According to another aspect of the inventive concepts, a memory device may include: a peripheral circuit region including a plurality of peripheral circuit devices provided on a first substrate and a first interlayer insulating layer covering the peripheral circuit devices; and a cell region including a plurality of channel regions and a plurality of dummy channel regions extending in a direction perpendicular to an upper surface of a second substrate that is different from the first substrate, and a plurality of gate electrode layers and a plurality of insulating layers that are stacked on the second substrate such that the gate electrode layers and the insulating layers are adjacent the channel regions and the dummy channel regions, wherein the peripheral circuit region and the cell region are disposed vertically each other and the second substrate includes a substrate insulating layer provided below the dummy channel regions and is not provided below the channel regions. According to another aspect of the inventive concepts, a memory device may include: a plurality of channel regions extending in a direction perpendicular to an upper surface of a substrate; a plurality of gate electrode layers adjacent the channel regions, the gate electrode layers extending different lengths in a first direction that is parallel to the upper surface of the substrate; a plurality of peripheral circuit devices that are electrically connected to at least some of the gate electrode layers; a plurality of dummy channel regions between the channel regions and the peripheral circuit devices; and a substrate insulating layer underneath each of the dummy channel regions. Part DETAILED DESCRIPTION: Hereinafter, exemplary embodiments of the inventive concepts will be described in detail with reference to the accompanying drawings. Throughout the specification, it will be understood that when an element is referred to as being “on” or “connected to” or “coupled to” another element, it can be on, connected to, or coupled to the other element, or intervening elements may be present. However, when an element is referred to as being “directly on” or “directly connected to”, or “directly coupled to” another element, it will be understood that intervening elements are not present. The same reference numerals are used throughout to designate the same or like elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Also, though terms such as “first” and “second” are used herein to describe various elements, components, regions, layers, and/or portions, the elements, components, regions, layers, and/or portions are not limited to these terms. These terms are used only to differentiate one element, component, region, layer, or portion from others thereof. Therefore, an element, a component, a region, a layer, or a portion referred to as a first element, a first component, a first region, a first layer, or a first portion in an embodiment may be referred to as a second element, a second component, a second region, a second layer, or a second portion in another embodiment. Relative terms such as “below” or “above” or “upper” or “lower” may be used herein to describe a relationship of one element, layer or region to another element layer or region as illustrated in the drawings. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, a first element of a device that is illustrated in the drawings as being above a second element may be below the second element if the device is turned upside down. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Also, it will be understood that the terms “comprises” and/or “comprising,” when used herein, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. Hereinafter, exemplary embodiments are described with reference to accompanying drawings that are schematic illustrations of idealized embodiments (and intermediate structures) of the inventive concepts. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. All embodiments can be combined in any way and/or combination. FIG. 1 is a block diagram schematically illustrating a memory device 10 according to an exemplary embodiment of the inventive concepts. Referring to FIG. 1, the memory device 10 includes a memory cell array 20, a low decoder 30, and a core logic circuit 55. The core logic circuit 55 may include a read/write circuit 40 and a control circuit 50. The memory cell array 20 may include a plurality of memory cells that are arranged in a plurality of columns and rows. The memory cells included in the memory cell array 20 may be connected to the low decoder 30 through a plurality of word lines WL, a common source line CSL, a string select line SSL, and a ground select line GSL, and may be connected to the read/write circuit 40 through a plurality of bit lines BL. In an exemplary embodiment, a plurality of memory cells that are arranged in the same row may be connected to the same word line WL, and a plurality of memory cells that are arranged in the same column may be connected to the same bit line BL. The memory cells included in the memory cell array 20 may be divided into a plurality of memory blocks. Each of the memory blocks may include a plurality of word lines WL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of bit lines 13L, and at least one common source line CSL. The low decoder 30 may receive address information ADDR from an external source and may decode the received address information ADDR to select at least one of the word lines WL, the common source lines CSL, the string select lines SSL, and/or the ground select lines GSL that are connected to the memory cell array 20. The read/write circuit 40 may select at least one of the bit lines BL that are connected to the memory cell array 20 according to a command received from the control circuit 50. The read/write circuit 40 may read out data stored in a memory cell or write data into a memory cell that is connected to a bit line BL that is selected based on the command received from the control circuit 50. In order to perform the foregoing operations, the read/write circuit 40 may include circuits such as a page buffer, an input/output buffer, and a data latch. The control circuit 50 may control operations of the low decoder 30 and the read/write circuit 40 in response to a control signal CTRL that is transmitted from an external source. In a case in which data stored in the memory cell array 20 is read, the control circuit 50 may control the low decoder 30 to supply a voltage for a read operation to a word line that is connected to one or more memory cells in which the data that is to be read is stored. When the voltage for the read operation is supplied to a specific word line WL, the control circuit 50 may control the read/write circuit 40 to read out data stored in a memory cell connected to the word line WL to which the voltage for a read operation has been supplied. In a case in which data is to be written to the memory cell array 20, the control circuit 50 may control the low decoder 30 to supply a voltage for a write operation to a specific word line that is connected to a memory cell into which data is to be written. When the voltage for the write operation is supplied to the specific word line WL, the control circuit 50 may control the read/write circuit 40 to write data into the memory cell. FIG. 2 is an equivalent circuit diagram illustrating a memory cell array of a memory device according to an exemplary embodiment of the inventive concepts. The memory device may be a vertical NAND flash device. Referring to FIG. 2, the memory cell array may include a plurality of memory cell strings each including memory cells MC1 to MCn connected in series, a ground select transistor GST and a string select transistor SST, with the ground select transistor located at a first end of the memory cells MC1 to MCn and the string select transistor located at the other end of the serially-connected memory cells MC1 to MCn. The memory cells MC1 to MCn in each memory cell string may be connected to respective word lines WL1 to WLn. The word lines Wl1 to WLn may be used to select respective ones of the memory cells MC1 to MCn. A gate terminal of the ground select transistor GST may be connected to a ground select line GSL, and a source terminal of the ground select transistor GST may be connected to a common source line CSL. A gate terminal of the string select transistor SST may be connected to a string select line SSL, and a source terminal of the string select transistor SST may be connected to a drain terminal of memory cell MCn. In FIG. 2, a single ground select transistor GST and a single string select transistor SST are included in each memory cell string. It will be appreciated, however, that in other embodiments a plurality of ground select transistors GST and/or a plurality of string select transistors SST may be included in each memory cell string. A drain terminal of the string select transistor SST may be connected to one of the bit lines BL1 to BLm. When a signal is applied to the gate terminal of the string select transistor SST through the string select line SSL, a signal applied through the bit lines 13L1 to BLm may be transferred to the memory cells MC1 to MCn of the memory cell string that includes the string select transistor SSL, to thereby perform a data read or write operation. Also, by applying a signal to the gate terminal of the ground select transistor GST through the gate select line GSL, an erase operation to remove all electric charges stored in the memory cells MC1 to MCn may be performed. FIG. 3 is a plan view illustrating a memory device 100 according to an exemplary embodiment of the inventive concepts. Referring to FIG. 3, the memory device 100 includes channel regions CH, dummy channel regions DCH, a plurality of contacts 111 to 116 (110) that are connected to a plurality of gate electrode layers stacked on a substrate such that the plurality of contacts 111 to 116 (110) are adjacent the dummy channel regions DCH, and a substrate insulating layer 105 disposed between the dummy channel regions DCH and the substrate. In the exemplary embodiment of FIG. 3, the channel regions CH, the dummy channel regions DCH, and the plurality of contacts 110 may extend in a Z-axis direction, and an upper surface of the substrate may correspond to an X-Y plane, where the X, Y and Z directions are perpendicular to each other. In the exemplary embodiment of FIG. 3, a diameter of an X-Y plane cross-section of each dummy channel region DCH is shown as being larger than a diameter of an X-Y plane cross-section each channel region CH, but the configuration is not limited thereto. That is, the diameters of the X-Y plane cross-sections of the dummy channel region DCH may be smaller than or equal to the diameters of the X-Y plane cross-sections of the channel regions CH in other embodiments. The gate electrode layers that are connected to the contacts 110 may be stacked on an upper surface of the substrate in the Z-axis direction. A plurality of common source lines 103 may be provided that separate the gate electrode layers and the channel regions CH into a plurality of regions. A separating insulating layer 104 may be provided adjacent each common source line 103. A separation insulating layer 104 may be provided on each of opposed sidewalls of each common source line 103. The channel regions CH may be spaced apart from one another in a first direction (the X-axis direction) and a second direction (the Y-axis direction). The number and disposition of the channel regions CH may vary according to exemplary embodiments. For example, in some embodiments, the channel regions CH may be disposed in a zigzag pattern as illustrated in FIG. 3. As shown in FIG. 3, the channel regions CH in a first region may be symmetrical to the channel regions CH in each adjacent region, but the disposition of the channel regions CH is not limited thereto. Each of the plurality of regions defined by the common source lines 103 and the separating insulating layers 104 may together form a unit cell of the memory device 100. A source region may be provided below the common source line 103 in the Z-axis direction. When a predetermined voltage is applied to the source region, data erasing may be performed in units of unit cells of the memory device 100. Hereinafter, the memory device 100 will be further described with reference to FIGS. 4 and 5. FIG. 4 is a cross-sectional view of the memory device 100 taken along line Ia-Ia′ of FIG. 3, and FIG. 5 is a cross-sectional view of the memory device 100 taken along line IIa-IIa of FIG. 3. The memory device 100 may have a cell-on-peri (COP) structure. Referring to FIGS. 4 and 5, a cell region C having a plurality of gate electrode layers 131 to 136 (which may be collectively referred to as the gate electrode layers 130) and channel regions CH may be provided above a peripheral circuit region P having a plurality of peripheral circuit devices 180. The peripheral circuit region P may include a first substrate 101, and the cell region C may include a second substrate 102. The first and second substrates 101 and 102 may be separate substrates. The first substrate 101 may be a semiconductor substrate having a first conductivity type (e.g., p-type). For example, the first substrate may be a semiconductor substrate that includes at least one selected from the group consisting of a single crystalline silicon layer, a silicon on insulator (SOI) wafer, a silicon layer formed on a silicon germanium (SiGe) layer, a single crystalline silicon layer formed on an insulating layer, and a polycrystalline silicon layer formed on an insulating layer. In some embodiments, the first substrate 101 may be a single crystalline substrate, and the second substrate may be a polycrystalline silicon substrate. The second substrate 102 may be formed on a first interlayer insulating layer 106, and thus the second substrate 102 may include polycrystalline silicon. In order to improve the crystallinity of the second substrate 102, at least a portion of the first substrate 101 may extend in the Z-axis direction so as to come into contact with a lower surface of the second substrate 102 and the second substrate 102 may be crystallized. Alternatively, a polycrystalline silicon region may be formed on the first interlayer insulating layer 106 and the second substrate 102 may be formed using the polycrystalline silicon region as a seed layer. The polycrystalline silicon region used as the seed layer may be provided on an upper surface of the first interlayer insulating layer 106 or may be provided within a groove pattern formed in the first interlayer insulating layer 106 and extending in a specific direction. The peripheral circuit region P may include the first substrate 101, the peripheral circuit devices 180, and a first interlayer insulating layer 106. In an exemplary embodiment, the peripheral circuit devices 180 may include at least one planar transistor. Referring to FIGS. 4 and 5, the at least one planar transistor may have a source/drain region 181, a gate electrode 182, a gate spacer film 183, and a gate insulating layer 184. The first interlayer insulating layer 106 may be provided on the peripheral circuit device 180, and wiring patterns 185 that are disposed within the first interlayer insulating layer 106 may be connected to the gate electrode 182 and/or the source/drain region 181. The first interlayer insulating layer 106 may include a silicon oxide, and may include a high deposition plasma (HDP) oxide film or a tetra-ethyl-ortho-silicate (TEOS) oxide film. The cell region C may be disposed on the peripheral circuit region P. Referring to FIGS. 4 and 5, within the cell region C, the second substrate 102 may be on an upper surface of the first interlayer insulating layer 106 of the peripheral circuit region P. The channel regions CH may extend in a direction that is perpendicular to an upper surface of the second substrate 102 (i.e., the Z-direction), and the gate electrode layers 130 may be stacked on the upper surface of the second substrate 102 such that the gate electrode layers 130 are adjacent the channel regions CH. A plurality of insulating layers 141 to 147 (140) may be disposed between the gate electrode layers 130. The gate electrode layers 130 may have different lengths in the first direction (X-axis direction), forming a step structure. In the region in which the step structure is provided, the gate electrode layers 131-136 may be connected to the respective contacts 111-116. A second interlayer insulating layer 107 may be provided on the plurality of gate electrode layers 130. The second interlayer insulating layer 107 may include a silicon oxide, and may include a high deposition plasma (HDP) oxide film or a tetra-ethyl-ortho-silicate (TEOS) oxide film. Each channel region CH may include a channel layer 170, a gate insulating layer 160 disposed between the channel layer 170 and the gate electrode layer 130, an embedded insulating layer 173 provided within the channel layer 170, and an epitaxial pattern 171 that is provided beneath the channel layer 170 and insulating layer 173. The channel layer 170 may have an annular shape and the embedded insulating layer 173 may fill a space within the annular channel layer 170. In an exemplary embodiment, the channel layer 170 may have a columnar shape such as a cylindrical shape or a prismatic shape. While not shown in the drawings, each channel region CH may have a sloped side surface such that a width thereof is reduced in a direction (the Z-direction) toward an upper surface of the second substrate 102. A drain region 175 is provided on the top surface of each channel region CH. The drain region 175 may include doped polysilicon. The channel layers 170 may vertically overlap respective ones of the epitaxial patterns 171. Herein, a first structure that is formed on an underlying substrate “vertically overlaps” a second structure that is formed on the substrate if a line that is perpendicular to a plane defined by the top surface of the substrate bisects both the first and second structures. The epitaxial patterns 171 may be aligned underneath respective ones of the channel layers 170 so that a vertical axis of each epitaxial pattern is aligned with a vertical axis of a respective one of the channel layers 170. Each channel layer 170 may be electrically connected to the second substrate 102 through the epitaxial pattern 171. Each channel layer 170 may include a semiconductor material such as polysilicon or single crystalline silicon, and the semiconductor material included in the channel layer 170 may be an undoped material or may be doped with a p-type or n-type impurity. The epitaxial patterns 171 may be formed via selective epitaxial growth (SEG). The epitaxial patterns 171 may be collectively referred to herein as an epitaxial layer 171. In an exemplary embodiment, the dummy channel regions DCH may be positioned adjacent ends of respective ones of the gate electrode layers 131-136. In particular, as shown in FIG. 5, each dummy channel region DCH may be adjacent one end of one of the gate insulating layers 130 (namely the left end in the view of FIG. 5). As the number of gate electrode layers 130 increases, the length of lower ones of the gate electrode layers 130 may also increase. As the length of a gate electrode layer 130 increases, so does the possibility that the gate electrode layer 130 will be bent or broken, rather than being structurally supported, in a region far away from the channel regions CH. In an exemplary embodiment, since the dummy channel regions DCH are provided adjacent the ends of the gate electrode layers 130 that are remote from the channel regions CH, the dummy channel regions DCH may support the gate electrode layers 130, decreasing the probability that the gate electrode layers 130 may be bent or broken. However, the inventive concepts are not limited to configurations in which the dummy channel regions DCH directly contact an end of a respective gate electrode layer 130. A substrate insulating pattern 105 may be provided below each dummy channel region DCH. Each substrate insulating pattern 105 may include silicon oxide or another insulating material, and like the first and second interlayer insulating layers 106 and 107, the substrate insulating patterns 105 may include an HDP oxide film or a TEOS oxide film. Since the substrate insulating patterns 105 cover lower surfaces and lower portions of the side surfaces of the respective dummy channel regions DCH, unlike the channel regions CH, selective epitaxial growth (SEG) may not occur in the dummy channel regions DCH, and the epitaxial patterns 171 may not be formed. Thus, a problem in which a height of the epitaxial pattern 171 is not controlled as desired during a manufacturing process so that the gate electrode layer 131 corresponding to the ground select transistor GST is electrically connected to other of the gate electrode layers 132 to 136 may be avoided. In the exemplary embodiment illustrated in FIG. 5, it is illustrated that a thickness of each substrate insulating pattern 105 is greater than that of the second substrate 102, but the inventive concepts are not limited thereto. The substrate insulating patterns 105 may be collectively referred to herein as a substrate insulating layer 105. The dummy channel regions DCH may vertically overlap respective ones of the substrate insulating patterns 105. Referring to FIGS. 4 and 5, the gate electrode layers 130 and the insulating layers 140 may be alternately stacked in the Z-axis direction. The gate electrode layers 130 may be adjacent the channel regions CH, and may form the gate electrodes for the ground select transistor GST, the memory cell transistors MC1 to MCn, and the string select transistor SST. Gate electrode layers 132-135 may form word lines WL1 to WLn and may be commonly connected in adjacent memory cell strings in a predetermined unit arranged in the first direction (X-axis direction) and the second direction (Y-axis direction). While a total of six gate electrode layers 131-136 are illustrated in FIGS. 4-5, other numbers of gate electrodes 130 may be provided. For example, in exemplary embodiments, a total number of the gate electrode layers 130 forming the memory cell transistors MC1 to MCn may be 2N (where N is a natural number). The gate electrode layer 131 for the ground select transistors GST may be connected to the ground select line GSL. In FIGS. 4 and 5, a single gate electrode layer 135 for the string select transistors SST and a single gate electrode layer 131 for the ground select transistors GST are illustrated, but it will be appreciated that more than one string select transistor SST and/or more than one ground select transistor GST may be provided in each memory cell string. The gate electrode layers 131 and 136 corresponding to the ground select transistors GST and the string select transistors SST may have a structure different from the structure of the gate electrode layers 132-135 that correspond to the memory cell transistors MC1 to MCn. The gate electrode layers 130 may include a polysilicon or metal silicide material. The metal silicide material may be selected from among, for example, cobalt (Co), nickel (Ni), hafnium (Hf), platinum (Pt), tungsten (W), and titanium (Ti). In exemplary embodiments, the gate electrode layers 130 may include a metal, such as tungsten (W). The gate electrode layers 130 may further include a diffusion barrier. For example, the diffusion barrier may include at least one of tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN). The gate electrode layers 130 may be alternately stacked with the insulating layers 140 in the Z-axis direction. Like the gate electrode layers 130, the insulating layers 140 may be separated in the Y-axis direction from other insulating layers 140 by the separating insulating layers 104, and the insulating layers 140 may have decreasing length in the X-axis with increasing distance from the second substrate 102 such that the insulating layers 140 form a step structure. The insulating layers 140 may include an insulating material such as silicon oxide or silicon nitride. A gate insulating layer 160 may be interposed between each gate electrode layer 132-136 and the channel layer 170, and between the epitaxial pattern 171 and gate electrode layer 131. The gate insulating layer 160 may include a blocking layer 162, a charge storage layer 164, and a tunneling layer 166 that are sequentially stacked between the channel layer 170 and each gate electrode layer 130. The blocking layer 162 may include a high-k dielectric material. Herein, a high-k dielectric material refers to a dielectric material having a dielectric constant higher than that of silicon oxide. The tunneling layer 166 may be a layer that is configured to tunnel electric charges to the charge storage layer 164 via Fowler-Nordheim (F-N) tunneling. The tunneling layer 166 may include, for example, silicon oxide. The charge storage layer 164 may be a charge trap layer or a floating gate conductive layer. For example, the charge storage layer 164 may include a dielectric material, quantum dots, or nanocrystals. The quantum dots or nanocrystals may be formed of a conductor such as fine particles of metal or a semiconductor. FIG. 6 is a perspective view illustrating a region “A” of the memory device 100 illustrated in FIG. 3. Referring to FIGS. 4, 5, and 6, the memory device 100 may have a COP structure in which a cell region C is disposed on a peripheral circuit region P. The substrate insulating layer 105 may be provided in a portion of the second substrate 102 that acts as a semiconductor substrate for forming the cell region C. The substrate insulating layer 105 may include silicon oxide or the like. The substrate insulating layer 105 may be provided in portions of the second substrate 102 that are underneath the dummy channel regions DCH. Consequently, the dummy channel regions DCH may directly contact the substrate insulating layer 105 and may not directly contact the second substrate 102. Thus, unlike the channel regions CH, selective epitaxial growth (SEG) will not occur in the lower portions of the dummy channel regions DCH during the formation of the epitaxial layer 171. During a manufacturing process of the memory device 100, in order to form the gate electrode layers 130, the insulating layers 140 and sacrificial layers (not shown in FIGS. 3-6) may be alternately stacked in the Z-axis direction to form a mold on the second substrate 102, and thereafter, the sacrificial layers may be selectively removed through openings that are is formed for the common source lines 103 and the separating insulating layers 104. The sacrificial layers may be removed after the formation of the dummy channel regions DCH and the channel regions CH. If the epitaxial patterns 171 are formed in the lower portions of the dummy channel regions DCH, it may be difficult to control the height of the epitaxial patterns 171, and thus a portion of the gate insulating layer 160, for example, the charge storage layer 164, that is included in the dummy channel regions DCH may be removed when the sacrificial layers are removed. If this occurs, after the sacrificial layers are removed, when a conductive material such as polysilicon, a metal, or a metal silicide material is injected to form the gate electrode layers 130 in the openings created by removal of the sacrificial layers, the conductive material may also be introduced into the regions from which portions of the gate insulating layer 160 has been removed, and this conductive material may electrically connect the middle portions of the gate electrode layers 130. However, in an exemplary embodiment, since the substrate insulating patterns 105 are provided below the dummy channel regions DCH so that the epitaxial patterns 171 are not included in the dummy channel regions DCH, the foregoing problem may be reduced or prevented. FIG. 7 is a plan view illustrating a memory device 200 according to another exemplary embodiment of the inventive concepts. Referring to FIG. 7, the memory device 200 may include a cell region C and a peripheral circuit region P. The cell region C and the peripheral circuit region P may be adjacent each other in the first direction (X-axis direction) and may be regions that are defined on a single substrate 201. A plurality of peripheral circuit devices 280 in the form of planar transistors having source/drain regions 281 and gate electrodes 282 may be provided in the peripheral circuit region P. Channel regions CH, dummy channel regions DCH, common source lines 203, separating insulating layers 204, and a plurality of contacts 211 to 216 (210) may be disposed in the cell region C. The channel regions CH and the dummy channel regions DCH may vertically penetrate through at least a portion of a plurality of gate electrode layers (see FIGS. 8 and 9) that are stacked on an upper surface (X-Y plane) of the substrate 201. The contacts 211-216 may be connected to respective ones of the gate electrode layers. The gate electrode layers may be divided into a plurality of unit cell regions by the common source lines 203 and the separating insulating layers 204. In the exemplary embodiment illustrated in FIG. 7, a plurality of substrate insulating patterns 205 are provided that are disposed between the dummy channel regions DCH and the substrate 201. These substrate insulating patters 205 may be collectively referred to herein as a substrate insulating layer 205. Each substrate insulating pattern 205 may extend in the Y-axis direction. Each substrate insulating pattern 205 may correspond to a plurality of dummy channel regions DCH. Hereinafter, the structure of the memory device 200 will be described in further detail with reference to FIGS. 8 through 10. FIG. 8 is a cross-sectional view taken along line Ib-Ib′ of the memory device of FIG. 7, FIG. 9 is a cross-sectional view taken along line IIb-IIb′ of the memory device of FIG. 7, and FIG. 10 is a perspective view illustrating a region “B” of the memory device of FIG. 7. Referring to FIG. 8, a plurality of gate electrode layers 231 to 236 (230) and a plurality of insulating layers 241 to 247 (240) may be alternately stacked in the Z-axis direction on an upper surface of the substrate 201. The gate electrode layers 230 may have different lengths in the first direction (X-axis direction) to form a step structure, and in the region in which the step structure is formed, the gate electrode layers 230 may be connected to respective ones of the contacts 210. The insulating layers 240 may extend with the same length in the first direction (X-axis direction) as respective gate electrode layers 230 that are adjacent thereto. The peripheral circuit device 280 disposed in the peripheral circuit region P may be a planar transistor and may include a source/drain region 281, a gate electrode 282, a gate spacer film 283, and a gate insulating layer 284. Isolation films 286 may be formed between adjacent peripheral circuit devices 280 and/or between the peripheral circuit devices 280 and the gate electrode layers 230. The channel regions CH may penetrate through the gate electrode layers 230. Each channel region may include a channel layer 270 that extends in the Z-axis direction and that is adjacent the gate electrode layers 230 with the gate insulating layer 260 interposed therebetween. In particular, the gate insulating layer 260 may be interposed between each gate electrode layer 232-236 and the channel layer 270. The gate insulating layer 260 may include a blocking layer 262, a charge storage layer 264, and a tunneling layer 266. An inner space of the channel layer 270 may be filled with an embedded insulating layer 273. An epitaxial pattern 271 may form the lower portion of each channel region CH. The gate insulating layer 260 may also be between each epitaxial pattern 271 and the gate electrode layer 231. A drain region 275 may be provided on the opposite end of each channel region CH. Referring to FIG. 9, the dummy channel regions DCH may be adjacent respective ends of the gate electrode layers 230. Like the channel regions CH, the dummy channel regions DCH may include a channel layer 270 and an embedded insulating layer 273. A drain region 275 may be formed on an upper surface of each dummy channel region DCH. However, the dummy channel regions DCH do not include the epitaxial patterns 271. A substrate insulating pattern 205 including silicon oxide or the like may be disposed beneath each dummy channel region DCH. Each substrate insulating pattern 205 may be between a respective one of the dummy channel regions DCH and the substrate 201 and may prevent formation of the epitaxial pattern 271 in the lower portions of the respective dummy channel region DCH through selective epitaxial growth. Thus, a short circuit phenomenon that may occur between some gate electrode layers 230 and the channel regions CH may be avoided when the gate electrode layers 230 are formed after the formation of the dummy channel regions DCH, and the breakdown voltage (BV) characteristics of the gate electrode layer 231 that is connected to the ground select line GSL may be improved. According to an exemplary embodiment, the substrate insulating patterns 205 may extend in a specific direction within the substrate 201. Referring to FIGS. 7 and 10, the substrate insulating patterns 205 may extend in the Y-axis direction within the substrate 201. Thus, two dummy channel regions DCH may correspond to each substrate insulating pattern 205. That is, one substrate insulating pattern 205 may be disposed between two dummy channel regions DCH and the substrate 201. FIG. 11 is a plan view illustrating a memory device 300 according to another exemplary embodiment of the inventive concepts. Referring to FIG. 11, the memory device 300 may include channel regions CH, dummy channel regions DCH that are provided separately from the channel regions CH, a plurality of contacts 311 to 316 (310) that are connected to a plurality of gate electrode layers, and separating insulating layers 304 and common source lines 303 that divide the gate electrode layers into a plurality of unit cell regions. The gate electrode layers may extend with different lengths in the first direction (X-axis direction) and may be physically and/or electrically connected to respective ones of the contacts 310. In an exemplary embodiment, substrate insulating patterns 305 may be provided below the respective dummy channel regions DCH, and thus, epitaxial patterns 371 that form lower portions of the channel regions CH may not be included in the dummy channel regions DCH. FIG. 12 is a cross-sectional view of the memory device 300 taken along line Ic-Ic′ of FIG. 11, FIG. 13 is a cross-sectional view of the memory device 300 taken along line IIc-IIc′ of FIG. 11, and FIG. 14 is a perspective view illustrating a region “C” of the memory device 300 that is illustrated in FIG. 11. Referring to FIG. 12, the memory device 300 may have a cell-on-peri (COP) structure in which a cell region C is disposed on a peripheral circuit region P. The peripheral circuit region P may include a first substrate 301, and a plurality of peripheral circuit devices 380 and a first interlayer insulating layer 306 may be disposed on the first substrate 301. The peripheral circuit devices 380 may comprise planar transistors that include source/drain regions 381, gate electrode layers 382, gate spacer films 383, and gate insulating layers 384, and may be electrically connected to wiring patterns 385. A second substrate 302 may be disposed on an upper surface of the first interlayer insulating layer 306. The second substrate 302 may include a first layer 302a that may directly contact an upper surface of the first interlayer insulating layer 306, and a second layer 302b that is disposed on an upper surface of the first layer 302a. The first layer 302a may be provided as a seed layer for forming the second layer 302b. In an exemplary embodiment, the second layer 302b may be formed via epitaxial growth using the first layer 302a as a seed layer. The first layer 302a may be a silicon layer formed using disilane (Si2H6) as a silicon source, and in particular, the first layer 302a may include large-grained polycrystalline silicon. An average diameter of crystal grains included in the first layer 302a may be greater than a thickness of the first layer 302a. For example, an average diameter of the crystal grains included in the first layer 302a may be a few to tens of micrometers. The second layer 302b may be formed through selective epitaxial growth using the first layer 302a as a seed layer. Like the first layer 302a, the second layer 302b may include polycrystalline silicon, and an average size, for example, an average diameter, of the polycrystalline silicon crystal grains included in the second layer 302b may be greater than that of the polycrystalline silicon crystal grains included in the first layer 302a. Thus, compared to the first layer 302a, the second layer 302b may have relatively few defects. The second layer 302b may be thicker than the first layer 302a in the Z-axis direction. In the cell region, a pocket P-well may be formed within the second substrate 302, and here, the pocket P-well may be formed only in the second layer 302b and not in the first layer 302a. Thus, the second layer 302b may be grown to have a thickness sufficient for forming the pocket P-well. The cell region C may include a plurality of gate electrode layers 331 to 336 (330) and a plurality of insulating layers 341 to 347 (340). The gate electrode layers 330 and the insulating layers 340 may be alternately stacked on the second substrate 302 in the Z-axis direction. The gate electrode layers 330 and the insulating layers 340 may extend with different lengths in the first direction (X-axis direction) to form a step structure. In the region in which the step structure is formed, the contacts 310 may be connected to respective ones of the gate electrode layers 330. Each channel region CH may include a channel layer 370, an embedded insulating layer 373 and an epitaxial pattern 371. A drain region 375 may be provided above each channel region CH. The drain region 375 may comprise polysilicon. The polysilicon may or may not be doped with an impurity. The epitaxial patterns 371 may be grown via selective epitaxial growth from the second substrate 302. Gate insulating layers 360 may be provided between each channel layer 370 and the gate electrode layers 332-336 and between each epitaxial pattern 371 and the gate electrode layer 331. Each gate insulating layer 360 may include a blocking layer 362, a charge storage layer 364, and the tunneling layer 366. The blocking layer 362 may surround the gate electrode layers 330. Referring to FIG. 13, dummy channel regions DCH may be provided adjacent first ends of the gate electrode layers 330. Like the channel regions CH, the dummy channel regions DCH may include a channel layer 370 and an embedded insulating layer 373. A drain region 375 may be provided above each dummy channel region DCH. However, the epitaxial patterns 371 are not included in the dummy channel regions DCH. A substrate insulating pattern 305 that includes silicon oxide or the like may be provided between each dummy channel region DCH and the second substrate 302. The substrate insulating patterns 305 may be collectively referred to herein as a substrate insulating layer 305. The substrate insulating patterns 305 may prevent formation of the epitaxial patterns 371 in the dummy channel regions DCH through selective epitaxial growth. Thus, a short circuit phenomenon that may occur between some gate electrodes 330 and the channel regions CH may be avoided even though the gate electrode layers 330 are formed after forming the dummy channel regions DCH, and the breakdown voltage (BV) characteristics of the gate electrode layer 331 that is connected to the ground select line GSL may be improved. According to an exemplary embodiment, each substrate insulating pattern 305 may extend in a specific direction within the substrate 302. Referring to FIGS. 11 through 14, each substrate insulating pattern 305 may extend in the X-axis direction within the substrate 302. Thus, multiple dummy channel regions DCH may correspond to each substrate insulating pattern 305. For example, as shown in FIGS. 13 and 14, five dummy channel regions DCH may correspond to one substrate insulating pattern 305. In other words, one substrate insulating pattern 305 may surround the lower portions of five dummy channel regions DCH. FIG. 15 is a plan view illustrating a memory device 400 according to yet another exemplary embodiment of the inventive concepts. Referring to FIG. 15, the memory device 400 may include a cell region C and a peripheral circuit region P. The cell region C and the peripheral circuit region P may be adjacent each other in the first direction (X-axis direction) and may be defined in a single substrate 401. A plurality of peripheral circuit devices 480 that have source/drain regions 481 and planar gate electrodes 482 may be provided in the peripheral circuit region P. Channel regions CH, dummy channel regions DCH, common source lines 403, separating insulating layers 404, and a plurality of contacts 411 to 416 (410) may be disposed in the cell region C. The channel regions CH and the dummy channel regions DCH may penetrate through at least some of a plurality of gate electrode layers in the Z-axis direction that are stacked on an upper surface (X-Y plane) of the substrate 401, and the contacts 410 may be connected to respective ones of the gate electrode layers. The gate electrode layers may be divided into a plurality of unit cell regions by the common source line 403 and the separating insulating layers 404. Substrate insulating patterns 405 are disposed between the dummy channel regions DCH and the substrate 401 to cover lower portions of the respective dummy channel regions DCH. The substrate insulating patterns 405 may be collectively referred to herein as a substrate insulating layer 405. In the exemplary embodiment of FIG. 15, it is illustrated that one substrate insulating pattern 405 is provided per unit cell region, but the substrate insulating patterns 405 may also be formed differently. For example, two or more substrate insulating patterns 405 may be provided per unit cell region. Hereinafter, the memory device 400 will be described with reference to FIGS. 16 through 18. FIG. 16 is a cross-sectional view of the memory device 400 taken along line Id-Id′ of FIG. 15, FIG. 17 is a cross-sectional view of the memory device 400 taken along line IId-IId′ of FIG. 15, and FIG. 18 is a perspective view illustrating a region “D” of the memory device 400 that is illustrated in FIG. 15. Referring to FIG. 16, a plurality of gate electrode layers 431 to 436 (430) and a plurality of insulating layers 441 to 447 (440) may be alternately stacked on an upper surface of the substrate 401 in the Z-axis direction. The gate electrode layers 430 may extend with different lengths in the first direction (X-axis direction) to form a step structure, and in the region in which the step structure is formed, the gate electrode layers 430 may be connected to respective ones of the contacts 410. The insulating layers 440 may extend with the same length in the first direction as the gate electrode layers 430 that are adjacent thereto. Each channel region CH may include a channel layer 470, an embedded insulating layer 473 and an epitaxial pattern 471. A drain region 475, which may be identical to the drain region 375 described above, may be provided above each channel region CH. Gate insulating layers 460 may be provided between each channel layer 470 and the gate electrode
{'bibliographic_information': "{'country': 'US', 'doc-number': '14987835', 'kind': 'B2', 'date': '20160105', 'disclaimer_text': 'This patent is subject to a terminal disclaimer.', 'invention_title': 'Vertical memory devices having dummy channel regions'}", 'source_file': './grant/2017/ipg170725.xml', 'source_data': 'USPTO-Grant'}