Title of Invention: Noise injected virtual timer Abstract: Techniques are described for injecting noise in a timer value provided to an instruction requesting the timer value. A plurality of tasks may execute on a processor, wherein the processor may comprise one or more processing cores and each task may include a plurality of computer executable instructions. In accordance with one technique for injecting noise in the timer value, a request for a first timer value is received by one or more computer executable instructions belonging to a first task from the plurality of tasks, and in response, a second timer value is provided to the first task instead of the first timer value, wherein the second timer value is derived from the first timer value and a random number. Detailed Description: Part general_description_paragraphs: Part CROSS REFERENCE TO RELATED APPLICATIONS: This application claims priority to U.S. patent application Ser. No. 14/509,984, filed Oct. 8, 2014, issued as U.S. Pat. No. 9,378,363 on Jun. 28, 2016, the content of which is herein incorporated in its entirety. Part BACKGROUND: Any given computing device may execute several security sensitive and non-security sensitive tasks, simultaneously or near simultaneously, on a computing system. Some non-security sensitive tasks may include malicious tasks that may either subvert the execution of the security sensitive task or steal information from the execution of the security sensitive task. A simple example of a security sensitive task may include a user trying to establish a secure communication session with a backend server, such as a bank, using a web interface to access his or her account information. A malicious task that can gain access to the session key for the secure communication session between the user and the backend server may be able to connect to the backend server and gain access to the user's sensitive information. In a multi-tenant environment, where multiple tenants or users may concurrently execute tasks on the same computing device, the risk to the security sensitive tasks from potentially executing malicious tasks is exacerbated, since the computing resources of the computing device are no longer dedicated to a single tenant. Part DETAILED DESCRIPTION: In the following description, various embodiments will be described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the embodiments. However, it will also be apparent to one skilled in the art that the embodiments may be practiced without the specific details. Furthermore, well-known features may be omitted or simplified in order not to obscure the embodiment being described. Techniques are described for injecting noise in the timer value, so that an attacker from the malicious task, such as a virtual machine, cannot reliably use the time stamp counter to observe the response time of the shared hardware resources on the processor. According to one example technique, in response to a request for a timer value by instructions executing from within a task, a virtual timer value is received instead of the hardware timer value. The virtual timer value may be derived using at least the timer value and a random value. According to another technique, in response for a request for a timer value, an artificial and indeterminate amount of delay may be introduced before accessing of the timer value from the hardware timer. In one implementation, access to the hardware timer for the timer value may be gated by an artificially injected micro-architectural event. Current processing and system architectures are capable of executing a plurality of processing tasks simultaneously. These tasks may include a myriad of security sensitive tasks and non-security sensitive tasks. In addition, in some instances, malicious tasks may manage to install themselves and execute alongside security sensitive tasks. A hardware processor may support the execution of a plurality of processing tasks simultaneously by using multiple cores and/or multi-threading. A processor may include multiple cores and/or multi-threading may provide several logical processors for simultaneously executing and completing the execution of tasks. A multi-core processor may include multiple processing units within the same processor. In some embodiments, the multi-core processors may share certain resources, such as busses, buffers and second or third level of caches. In some instances, each core in a single or multi-care processor may also include multiple executing logical processors. Such a core that supports multiple logical processors may be referred to as a multi-threaded processor. Besides sharing higher level caches and busses, the tasks executing on a multi-threaded processor may also share several stages of the execution pipeline and lower level caches. Therefore, in a multi-core and/or multi-threaded processor several hardware resources are shared amongst the various tasks executing on the processor. Examples of these hardware resources include several stages of the execution pipeline of a core, several temporary storage buffers, caches and busses. A malicious task executing simultaneously, or near simultaneously on the processor along with a security sensitive task may be able to deduce security sensitive information from the security sensitive task by observing the response time of certain hardware resources shared between logical processors supported by the same processor. For example, in certain instances, it may be possible for the malicious task to steal the session key for a secure connection established for a user logged into her bank account through a web browser. Such attacks where a malicious task can steal information for a concurrently running security task by observing a resource shared by the two tasks may be referred to as a side-channel attack. Side-channel attacks may be particularly concerning in multi-tenant environments, such as cloud services, where the cloud service provider may schedule the processing of tasks from different tenants (e.g., users) on the same processor. In such an environment, the tasks associated with a tenant may be scheduled as an instantiation of an operating environment within a virtual machine. In certain implementation, a virtual machine is an emulation of the underlying hardware. Executing tasks associated with a tenant in a virtual machine enables a processor to service multiple tenants simultaneously or near simultaneously. In such an execution environment, a malicious tenant executing a malicious task inside a virtual machine (i.e., malicious virtual machine) may be able to steal secrets from another virtual machine executing security sensitive tasks on the same processor. In one instantiation of the side-channel attacks, a virtual machine executing a malicious task simultaneously, or near simultaneously on the processor along with a virtual machine executing a security sensitive task can deduce security sensitive information from the security sensitive task by observing the response time of certain shared hardware resources. The response time for a shared resource may be measured using a hardware time stamp counter. Orchestrating a side-channel attack would be significantly more difficult without an accurate time stamp counter that has enough granularity to enable detection of the differences between the response times of the shared resources in different states. In a multi-tenant environment, where multiple tenants or users may concurrently execute tasks on the same computing device, the risk to the security sensitive tasks from potentially executing malicious tasks is exacerbated, since the computing resources of the computing device are no longer dedicated to a single tenant. A multi-tenant environment may refer to an environment where multiple users or accounts, each referred to as a “tenant,” may be serviced simultaneously by a computing device and/or the processor of the computing device. For example, in a multi-tenant environment, a processor comprising one or more processing cores and operating in a multi-tenant environment may include one processing core that may simultaneously service instructions associated with two distinct tenants. In some instances, each tenant may be operating as part of a separate virtual machine. Next, techniques are described for injecting noise in the timer value, so that an attacker from the malicious virtual machine cannot reliably use the time stamp counter to observe the response time of the shared hardware resources on the processor. According to one exemplary technique, in response to a request for a timer value by instructions executing from within a virtual machine, a virtual timer value is received instead of the hardware timer value. The virtual timer value may be derived using at least the timer value and a random value. In certain embodiments, a timer value may refer to a value provided by a time stamp counter. In certain processor and system architectures, such as the x86 architecture, a time stamp counter may refer to a counter that counts the number of cycles since the processor reset. In one implementation, the time stamp counter value is retrieved by executing the read time stamp counter (RDTSC) instruction. It should be noted, that the means by which the timer value is provided are not limited to the time stamp counter and may include other timers, counters and clock values, provided by the processor, chipset, or any other component on or off the system. FIG. 1 illustrates an exemplary execution environment in which virtualization technology is used for performing embodiments described herein. Generally, “virtualization technology” may be used for providing isolation between different operating environments sharing the same physical resources. In other words, virtualization may provide a logical abstraction of computing resources from physical constraints. One common abstraction is referred to as a virtual machine (also known as guest), or VM, which provides the content running in the VM a direct interface to the physical hardware while maintaining the abstraction. Generally, virtualization technology allows multiple VMs running on the same physical hardware to operate independently and isolated from each other. The one or more VMs on the system are managed by a Virtualized Machine Monitor, or VMM (also known as hypervisor or host). The VMM is a software or firmware layer responsible for hosting and managing VMs. The VMM usually executes at a higher privilege level than the VMs and manages the system's processor and memory, and allocates other resources for each VM. FIG. 1 illustrates device hardware 102 executing VMM 104. VMM 104 manages a first VM 106 (VM1) and a second VM 110 (VM2). Device hardware 102 may include one or more processors besides other components for operating a computing system, as described in further detail in FIG. 18 and FIG. 19. In certain implementations, the processors may include hardware support for virtualization technology. For example, INTEL and AMD brand processors provide hardware hooks that support virtualization technology. Qualcomm Incorporated also provides a software abstraction layer which enables multiple operating systems and other clients to execute concurrently on a single processor, through the virtualization and portioning of physical hardware resources. As described above, certain processors may be architected to share hardware resources when possible, for more efficiently utilizing certain hardware components. For example, multiple processing cores may share caches and certain busses on the processor. Furthermore, in some implementations, multiple execution threads may operate on the same thread sharing the execution pipeline and level 1 and level 2 caches. In FIG. 1, VMM 104 manages VM1 106 executing a first task 108 and VM2 110 executing a second task 112. In one scenario, second task 112 may be a security sensitive task. An example of a security sensitive task may be an encryption operation performed by second task 112 to establish a secure communication channel with a trusted entity, such as a user logging into their bank account. Another example of a security sensitive task may involve a user encrypting data for safe storage. On the other hand, first task 108 executing in VM1 106 may be a malicious task. As shown in FIG. 1, first task 108 may be configured to execute a read timer command to measure the response time for certain accesses to shared processor resources such as caches, buffers and/or busses. In certain embodiments, a task may refer to a group of executable instructions. Example of a task may include a processing thread, a process, or an application that may include multiple processes. FIG. 2 illustrates a variation of the exemplary execution environment shown in FIG. 1 that is configured to provide a virtual timer value instead of the timer value. FIG. 2 includes virtual timer configuration module 202 and virtual timer module 204. Virtual timer configuration module 202 and virtual timer module 204 are implemented as part of VMM 104. VMM 104 is generally more privileged than the VM's managed by VMM 104. In certain implementations, virtual timer configuration module 204 may configure VM1 106 such that all requests for reading the timer value from the hardware (e.g., RDTSC) from VM1 106 results in a virtual machine exit (VMexit) to VMM 104. In other words, VM1 106 is configured such that any attempt to read the timer value from VM1 106 results in an automatic transfer of the execution from VM1 106 to VMM 104. Exemplary details of virtual timer configuration module 202 are described with reference to FIG. 11 further below. Virtual timer module 204 may be configured to provide VM1 106 with a virtual timer value instead of the timer value or the time stamp counter value provided by the hardware. Virtual timer module 204 may inject noise into the reading of the timer value by VM1 106 by deriving the virtual timer value using the timer value and a random number. For example, in certain implementations, virtual timer module 204 may retrieve the timer value from the hardware and replace the last few bits of the timer value with random number bits from a random number generator. Exemplary details of virtual timer module 204 are described with reference to FIGS. 4-10 further below. In one exemplary scenario, VM1 106 automatically transfers control to VMM 104 upon execution of an instruction that requests the timer value from hardware (e.g., RDTSC). Virtual timer module 204 executing in VMM 104 may generate the virtual timer value using at least the timer value and a random number. VMM 104 populates the appropriate registers in the processor state and returns execution control to VM1 106. VM1 106 continues execution by reading the virtual timer value from the expected registers. In most instances, virtualization of the read timer resource may not even be noticeable to VM1 106. In other words, according to certain embodiments, code executing within VM1 106 may not be able to differentiate between a timer value and a virtual timer value. When VM1 106 executes the read timer instruction, VM1 106 automatically transfers control to VMM 104. Virtual timer module 204 generates the virtual timer value and returns the execution back to the instruction after the read timer instruction with the virtual timer value as the result (instead of the timer value). From the perspective of VM1 106, the execution returns back as if the read timer value instruction completed successfully. Therefore, a malicious VM executing instructions for reading the timer value from hardware may be completely oblivious to the fact that the timer value is virtualized. In such a virtualized environment, launching a successful side-channel attack by a VM would be unsuccessful since the timer value may no longer be reliable for the purposes of the attack. As shown in FIG. 3, virtual timer module 304 may be implemented in hardware. For example, virtual timer module 304 may be implemented in the processor logic. In certain implementations, aspects of virtual timer module 304 may be implemented in processor microcode, processor hardware or any combination thereof. Similar to that described with reference to FIG. 2, VM1 106 may be configured by virtual timer configuration module 302. Virtual timer configuration module 302 may dictate the policy for enabling noise injection for the virtual timer and the nature of the noise injection. Exemplary details of virtual timer configuration module 302 are described with reference to FIG. 11 further below. In FIG. 3, VM1 106 may be configured by VMM 104, using virtual timer configuration module 302, to provide a virtual timer value instead of the timer value for a request for timer value from VM1 106. Once VM1 106 is configured by virtual timer configuration module 302, virtual timer module 304 may provide the virtual timer value to VM1 106 upon request of a timer value. As shown in FIG. 3, the request for the timer value from VM1 106 may be directly handled by virtual timer module 304 implemented in the processor logic without transferring control to VMM 104. In some instances, servicing the request for providing a virtualized timer value instead of the timer value in hardware may be faster than transferring control to VMM 104 and back from VMM 104. Exemplary details of virtual timer module 304 are described with reference to FIGS. 4-10. FIG. 4 is a block diagram illustrating exemplary aspects of the virtual timer module, according to certain embodiments of the disclosure. Virtual timer module 400 may be implemented as part of VMM 104, as discussed with reference to FIG. 2, or as part of device hardware 102, such as the processor (hardware or microcode), as discussed with reference to FIG. 3, or any combination thereof. Furthermore, time counter 402, delta generator 404, random number generator 406 and virtual time generator 408 may all be implemented in hardware, software, firmware (e.g., processor microcode) or any combination thereof. Virtual timer module 400 may be configured to provide the VM with the virtual timer value upon receiving a request for the timer value. In certain embodiments, time counter (T) 402 provides the counter value maintained by the processor or the computing system. In some instances, a phase locked loop (PLL) may be used for generating a locked output for time counter (T) 402 relative to an input signal. In one example, the input signal for the PLL, also referred to as the reference signal, may be derived from the processor clock or the core cycle counter for each processing core of the processor. Traditionally, in some implementations, the request for the timer value returns the value generated by time counter (T) 402 without any further modifications to the timer value. In certain instruction sets, such as x86 architecture, the read time stamp counter (RDTSC) instruction returns the current time stamp counter value. However, embodiments described herein are not limited to the time stamp counter. In certain embodiments, random number generator 406 may generate a random number (α). Various techniques may be used in generating the random number without deviating from the scope of the disclosure. Furthermore, various entropy sources, individually or in combination with each other may be used in providing quality entropy for the generation of the random number. For example, random number generator 406 may collect entropy from a variety of sources, such as quantum mechanical noise sources, nuclear decay, thermal noise and clock drift. In some instances, random number generator 406 may collect entropy from sources resident on the processor, sources off the processor and any combination thereof. In some implementations, random number generator 406 may generate a random number for each processor core associated with the processor. In some implementations, random number generator 406 may be implemented by the processor, VMM or any other entity, and the virtual timer module may simply request the random number from random number generator 406, instead of implementing a random number generator. In certain embodiments, delta (Δ) generator 404 derives the time difference between the current timer value (t) and the last timer value (t−1) from time counter 402. In one implementation, the delta generated by delta generator 404 may be represented by the following equation: Δ=floor(T(t)−T(t−1)) where T(t)=RDTSC(t) at time t Virtual time generator 408 receives input from time counter 402, delta generator 404 and random number generator 406 and generates the virtual timer value. In one exemplary implementation, the virtual timer value generated by virtual time generator 408 may be represented by the following equation: VT(t)=(T(t)+α*Δ) where T(t)=RDTSC(t) As illustrated by the above equation and further discussed with reference to FIG. 5B below, the random number (α) offsets the timer value scaled by the difference between two consecutive time counter values (Δ). Implementation of such a technique may result in increasing the difficulty in mounting a side-channel attack since the attacker can no longer rely on the accuracy of the timer value. FIG. 5A is an exemplary graph illustrating the output from time counter 402 without noise injection. In FIG. 5A, the x-axis represents time (t) and the y-axis represents the time from time counter 402. In one implementation, the time value for the time counter 402 is generated from the RDTSC instruction. The steps of graph 502 may represent the output of back to back execution of the RDTSC instruction. The graph of time 502 represents the change in time as measured by time counter 402 with respect to the actual passage of time. In FIG. 5A, the change in the timer value between two time cycles (t and t−1) may be represented by Δ. FIG. 5B is an exemplary graph illustrating the output of the virtual timer module, according to certain aspects disclosed with respect to FIG. 4. In FIG. 5B, the x-axis represents time (t) and the y-axis represents the output time (i.e., virtual timer value) from virtual timer module 400. Graph 504 is a representation of the virtual timer value with respect to the passage of time, as describe with respect to FIG. 4. The steps of graph 504 may represent the output of back-to-back requests from a VM for the timer value. As seen in FIG. 5B, the steps of graph 504 (representing the value of virtual timer module 400) are offset from the steps of graph 502 (representing the output of time counter 402). According to aspects of the disclosure discussed with reference to FIG. 4, the offset is calculated using the random number (α) generated by random number generator 406, but scaled proportionally by the difference between the current timer value and the last timer value (Δ). Scaling the random number by the difference between the current timer value and the last timer value may help ensure monotonicity of the counter. For example, such a technique may prevent a second request form two back-to-back requests for timer values from virtual timer module 400 to generate a number that is smaller than the previously generated number. FIG. 6 is a block diagram illustrating exemplary aspects of the virtual timer module, according to certain other embodiments of the disclosure. Virtual timer module 600 may be implemented as part of VMM 104, as discussed with reference to FIG. 2, or as part of device hardware 102, such as the processor (hardware or microcode), as discussed with reference to FIG. 3, or any combination thereof. Furthermore, time counter 602, delta generator 604, random number generator 606 and virtual time generator 608 may all be implemented in hardware, software, firmware (e.g., processor microcode) or any combination thereof. Virtual timer module 600 may be configured to provide the VM with the virtual timer value upon receiving a request for the timer value. In certain embodiments, time counter (T) 602 provides the counter value maintained by the processor. In certain embodiments, time counter (T) 602 may be similar to time counter 402 in FIG. 4. In certain embodiments, random number generator 606 may generate at least two random numbers (α,β). Similar to what has been described for random number generator 406 in FIG. 4, various techniques may be used in generating the random number without deviating from the scope of the disclosure. Furthermore, various entropy sources, individually or in combination with each other may be used in providing quality entropy for the generation of the random number. In certain implementations, random number generator 606 may generate two random numbers (α,β) for each processor core associated with the processor. In certain embodiments, delta (Δ) generator 604 derives the time difference between the current timer value (t) and the last timer value (t−1) from time counter 602. In one implementation, the delta generated by delta generator 604 may be represented by the following equation: Δ=floor(T(t)−T(t−1)) where T(t)=RDTSC(t) at time t Virtual time generator 608 receives input from time counter 602, delta generator 604 and random number generator 606 and generates the virtual timer value. In one exemplary implementation, the virtual timer value generated by virtual time generator 608 may be represented by the following equation: VT(t)=(T(t+t*β)+α*Δ) where T(t)=RDTSC(t) As illustrated by the above equation and further discussed with reference to FIG. 7B below, the first random number (α) offsets the timer value scaled by the difference between the two time counter values (Δ), whereas the second random number (β) scales the time for which the output from time counter 602 is used or sampled. Therefore, this technique perturbs the timer value by not only offsetting the timer value generated by a random number, but also offsetting the time at which time counter 602 is sampled. For instance, the virtual timer value (i.e., VT(t)) for time (t) directly depends on the time value sampled from time counter 602 at time (t+t*β). This technique further increases the difficulty in mounting a side-channel attack since the attack can no longer rely on the accuracy of the timer value or a relation between the time at which the timer value was returned and the time at which the time was sampled. FIG. 7A is an exemplary graph illustrating the output from a timer counter without noise injection. The exemplary graph in FIG. 7A corresponds to the exemplary graph in FIG. 5A. For example, graph 702 in FIG. 7A corresponds to graph 502 in FIG. 5A. Similarly, delta (Δ) in FIG. 7A corresponds to delta (Δ) in FIG. 5A. FIG. 7B is an exemplary graph illustrating the output of the virtual timer module, according to certain aspects disclosed with respect to the FIG. 6 block diagram. In FIG. 7B, the x-axis represents time (t) and the y-axis represents the output time (i.e., virtual timer value) from virtual timer module 600. Graph 704 is a representation of the virtual timer value with respect to the passage of time, as describe with respect to FIG. 6. The steps of graph 604 may represent the output of back-to-back requests from a VM for the timer value. As seen in FIG. 7B, the steps of graph 704 (representing the value of virtual timer module 600) are offset (α*Δ) from the steps of graph 702 (representing the output of time counter 602) by a random scaled value. In addition, the time at which the time counter is sampled may also be offset (t*β) by a random scale. Such a technique amplifies the level of difficulty in relying on the timer values by a malicious task executing from a VM in performing a side-channel attack or any other attack that utilizes the timer values. The timer is perturbed using a random number both in the value and the relation between the time at which the timer value was returned and the time at which the time was sampled. FIG. 8 is another block diagram illustrating exemplary aspects of the virtual timer module, according to certain other embodiments of the disclosure. Virtual timer module 800 may be implemented as part of VMM 104, as discussed with reference to FIG. 2, or as part of device hardware 102, such as the processor (hardware or microcode), as discussed with reference to FIG. 3, or any combination thereof. Furthermore, time counter 802, random number generator 804, monotonic noise injector 806, noise tolerance determinator 810 and virtual time generator 808 may all be implemented in hardware, software, firmware (e.g., processor microcode) or any combination thereof. Virtual timer module 800 may be configured to provide the VM with the virtual timer value upon receiving a request for the timer value. In certain embodiments, time counter (T) 802 provides the counter value maintained by the processor. In certain embodiments, time counter (T) 802 may be similar to time counter 402 in FIG. 4. In certain embodiments, random number generator 804 generates a random number. Similar to what has been described for random number generator 406 in FIG. 4, various techniques may be used in generating the random number without deviating from the scope of the disclosure. Furthermore, various entropy sources, individually or in combination with each other may be used in providing quality entropy for the generation of the random number. In certain implementations, the processor may share random number generator 804 amongst one or more processing cores. In other implementations, each processing core associated with the processor may have a dedicated random number generator 804. In certain aspects, noise tolerance determinator 810 may provide constructs for injecting noise to monotonic noise injector 806. For example, noise tolerance determinator 810 may determine the number of bits of the random number generator to use for injecting noise into the timer value. In one aspect, noise tolerance determinator 810 maintains the monotonicity of the virtual timer value generated by virtual timer module 800 by shaping the injection of noise to the timer value, accordingly. The software operating inside the VMs may make legitimate (non-malicious) requests for the timer value. However, the software operating inside the VM may not need the level of granularity provided by current hardware timers to operate properly. Therefore, the software may have a certain inherent tolerance for the level of noise injected into the timer value. In one scenario, the value provided by back-to-back timer reads from the software may result in one such characteristic that may determine the upper bound of noise and/or how noise is injected into the timer value. For example, there may be a minimum number of cycles (referred herein as “Z”) within which it may be possible for instructions executing on the processor to perform two back-to-back reads of the timer value while maintaining monotonicity of the timer. In certain implementations, to produce an obfuscated time value, noise tolerance determinator 810 may determine the number of least significant bits that may be replaced by cryptographic quality random numbers/noise. In one implementation, noise tolerance determinator 810 may determine the number of least significant bits of the timer value which can be directly replaced with an integer less than or equal to log2(Z) in order to guarantee monotonicity of the timer values. For example, if Z=36 cycles, log2(36)≈5.1699, and noise tolerance determinator 810 may then replace at most 5 of the least significant bits of the timer value and still guarantee monotonicity in the worst case. In one implementation, monotonic noise injector 806 may receive the random number from random number generator 804 and the number of least significant bits of random number generator 804 to be used for noise injection from noise tolerance determinator 810. In one implementation, monotonic noise injector 806 may mask out bits, reduce the number of bits from random number generator 804 or further process the random number from random number generator 806 using the constructs from noise tolerance determinator 810 and send the resultant random number to virtual time generator 808 for generating the virtual timer value. In one implementation, virtual time generator 808 receives the input timer value from time counter 802 and the resultant random value from monotonic noise injector 806 and generates the virtual timer value. In one implementation, virtual time generator 808 replaces bits from the timer value from time counter 802 with bits from the resultant random value from monotonic noise injector 806 to generate the virtual timer value. Aspects of the above implementation described with reference to FIG. 8 provide an exemplary technique for injecting noise into the timer value to the extent that the monotonicity of the virtual timer value generated is maintained. FIG. 9 is yet another block diagram illustrating exemplary aspects of the virtual timer module, according to certain other embodiments of the disclosure. virtual timer module 900 may be implemented as part of VMM 104 as discussed with reference to FIG. 2 or as part of device hardware 102, such as the processor (hardware or microcode), as discussed with reference to FIG. 3, or any combination thereof. Furthermore, time counter 902, random number generator 904, monotonic noise injector 906, noise efficacy determinator 910 and virtual time generator 908 may all be implemented in hardware, software, firmware (e.g., processor microcode) or any combination thereof. Virtual timer module 900 may be configured to provide the VM with the virtual timer value upon receiving a request for the timer value. In certain embodiments, time counter (T) 902 provides the counter value maintained by the processor. In certain embodiments, time counter (T) 902 may be similar to time counter 402 in FIG. 4. In certain embodiments, random number generator 904 generates a random number. Similar to that described for random number generator 406 in FIG. 4, various techniques may be used in generating the random number without deviating from the scope of the disclosure. Furthermore, various entropy sources, individually or in combination with each other may be used in providing quality entropy for the generation of the random number. In certain implementations, the processor may share random number generator 904 amongst one or more processing cores. In other implementations, each processing core associated with the processor may have a dedicated random number generator 904. In certain aspects, noise efficacy determinator 910 may indicate to monotonic noise injector 910 the lower limits of the amount and type of noise needed for effectively reducing observability by the attacker of the shared micro-architectural structures within the processor using the timer values. For example, for at least some attacks, mounting the side-channel attack becomes more challenging with the number of bits used as noise for the timer since it is harder for the attacker to discriminate the state of micro-architectural structures. In an exemplary scenario, a typical Level 1 (L1) hit load latency may be 3 cycles, and the typical L1 miss to Level 2 (L2) may be 12 cycles. The difference between the L1 hit and L1 miss to L2 hit is 9 cycles. In such scenario, the attacker must be able to collect enough data samples to distinguish a 9 cycle difference in the access time for the corresponding L1 line in order to discern information about the L1 usage by a security sensitive task. The difference between the access time needed to discern the micro-architectural state of the processor may be referred to as “D.” Noise efficacy determinator 910 may determine that the number of bits of noise that may be needed to obfuscate the access times between the two micro-architectural states of the L1 cache may be greater than or equal to log2(D*N), where N is a constant. For the above example, where the constant value for N is 4, then log2(9*4)≈4.7549. In such a scenario, noise efficacy determinator 910 may indicate to monotonic noise injector 906 that 5 (>4.7549) least significant bits of the timer value may be replaced with the noise to reduce the attacker's observability to ¼=25%. In one implementation, monotonic noise injector 906 may receive the random number from random number generator 904 and the information about the least number of least significant bits of the random number to replace from noise efficacy determinator 910. In one implementation, monotonic noise injector 906 may mask out bits, reduce the number of bits from random number generator 904 or further process the random number from random number generator 906 using the information from noise efficacy determinator 910 and send the resultant random number to virtual time generator 908 for generating the virtual timer value. In one implementation, virtual time generator 908 receives the input timer value from time counter 902 and the resultant random value from monotonic noise injector 906 and generates the virtual timer value. In one implementation, virtual time generator 908 replaces bits from the timer value from time counter 902 with bits from the resultant random value from monotonic noise injector 906 to generate the virtual timer value. FIG. 10 is still another block diagram illustrating exemplary aspects of the virtual timer module, according to certain other embodiments of the disclosure. Virtual timer module 1000 may be implemented as part of VMM 104 as discussed with reference to FIG. 2, or as part of device hardware 102, such as the processor (hardware or microcode), as discussed with reference to FIG. 3, or any combination thereof. Furthermore, time counter 1002, random number generator 1004, noise accumulator 1006, noise tolerance determinator 1010 and virtual time generator 1008 may all be implemented in hardware, software, firmware (e.g., processor microcode) or any combination thereof. Virtual timer module 1000 may be configured to provide the VM with the virtual timer value upon receiving a request for the timer value. In certain embodiments, time counter (T) 1002 provides the counter value maintained by the processor. In certain embodiments, time counter (T) 1002 may be similar to time counter 402 in FIG. 4. In certain embodiments, random number generator 1004 generates a random number. Similar to that described for random number generator 406 in FIG. 4, various techniques may be used in generating the random number without deviating from the scope of the disclosure. Furthermore, various entropy sources, individually or in combination with each other may be used in providing quality entropy for the generation of the random number. In certain implementations, the processor may share random number generator 1004 amongst a plurality of processing cores. In other implementations, each processing core associated with the processor may have a dedicated random number generator 1004. In certain embodiments, noise accumulator 1006 accumulates the noise over time or over multiple requests, instead of just injecting the noise generated from the current request. Although continuous back-to-back reads of the timer value may be possible, it is expected that in the typical cases reads of the timer value would be relatively much fewer and farther between. In certain implementations, accumulating noise allows achieving greater noise injection while maintaining monotonicity of the virtual timer value and the correct rate of count over long periods of time. Noise accumulator 1006 adds a new random number (α) every time the timer value is requested. The random number (α) is added to an accumulator (A) for each timer read request, as follows: A=A+α; The accumulator (A) accumulates noise in a relatively large number of bits. In one implementation, the accumulator is a memory location or a register with the same width as the time counter. The random number (α) may be generated using the initial random number received form random number generator 1004 and the constraints for the number of bits to be used by noise tolerance determinator 1010. In certain implementations, the noise tolerance for an implementation using a noise accumulator may be higher than an implementation just replacing the least significant bits of the time counter with the current random value, as describe with reference to FIG. 8. Noise tolerance determinator 810 in FIG. 8 may be limited in the amount of injected noise to log2(Z), where Z may refer to the minimum number of cycles within which it may be possible for instructions executing on the processor to perform two back-to-back reads of the timer value while maintaining monotonicity of the timer. However, if more noise could be injected it would be possible to further occlude the observability of the attacker and thereby reduce the success rate of such side-channel attacks. Noise tolerance determinator 1010 may allow for a greater amount (or bits) of noise to be injected, while maintaining monotonicity, since the noise is accumulated and the variance in the noise cannot cause the noise in one timer value request to undercut the timer value presented in the previous request for the timer value. Therefore, in certain implementations, noise tolerance determinator 1010 may indicate the desired number of bits to around log2(D), where D may be greater than Z. In one implementation, virtual time generator 1008 receives the input timer value (C) from time counter 1002 and the accumulator value (A) from noise accumulator 1006 and generates the virtual timer value by adding the counter value (C) and the accumulator value (A), as follows: Virtual Timer Value=C+A Furthermore, in some implementations, in order to maintain the correct rate of time count over the long term, the accumulated noise A may be gradually “burned down” by decrementing once every B number of cycles, where B>1. In certain implementations, for ease of implementation, the designer may select power of 2 values for B. The burn down of A may ocarter@example.org. In effect, this may cause the sum of C and A (i.e., the virtual timer value) to increment at a slower rate than normal for a certain period of time after a given read of the timer value. In certain implementations, the rate of burn down may be made configurable so that the return to long term normalcy occurs accordingly. By configuring D and B, a significant increase in D (i.e. significant occlusion of observability by the attacker) can be expected while maintaining relatively normal behavior for the system overall. Aspects of the exemplary virtual timer modules and the techniques described with reference to FIGS. 4-10 for generating the virtual timer value may be combined with one another without departing from the scope of the disclosure. For example, in one implementation, noise efficacy determinator 910 of FIG. 9 may be used along with noise tolerance determinator 810 of FIG. 8 to determine the amount and nature of the noise injected in the timer value. In another exemplary implementation, noise efficacy determinator 910 of FIG. 9 may be used along with noise accumulator 1006 and noise tolerance determinator 1010 of FIG. 10. Therefore, the methods, techniques and modules described with reference to FIGS. 4-10 may be implemented in various combinations with each other in implementing the virtual timer module without deviating from the scope of the disclosure. FIG. 11 is a block diagram illustrating exemplary aspects of the virtual timer configuration module, according to certain embodiments of the disclosure. Virtual timer configuration module 1100 may be implemented as the virtual timer configuration module 202 in FIG. 2 or the virtual timer configuration module 302 in FIG. 3, or any combination thereof. Furthermore, activate virtual timer module 1102, random number generation source module 1104, noise configuration module 1106 and Task/VM ID module 1108 may be implemented in hardware, software, firmware (e.g., processor microcode) or any combination thereof. Virtual timer configuration module 1100 may provide the configuration for the virtual timer modules described in the preceding figures. In some implementations, virtual timer configuration module 1100 may provide an interface for programming mechanisms and features provided by the processor (hardware or microcode). For example, in one implementation, the processor may provide the configuration registers for enabling/disabling, selecting entropy sources and selecting noise parameters, and virtual timer configuration module 1100 in VMM 104 may program those configuration parameters. Activate virtual timer module 1102, may activate or deactivate the virtual timer feature. Activate virtual timer module 1102 may provide a combination of settings to activate or deactivate the virtual timer feature globally for the processor, and/or on a per core, per thread, a per task and/or per virtual machine basis. For example, virtual timer module 1102 may set one or more activate bits in one or more configuration registers provided by the processor to activate the virtual timer feature and clear the one or more activate bits to deactivate the virtual timer feature. Several such configuration bits may be provided for activating or deactivating the virtual timer feature on various different granularities. In certain embodiments. Task/VM ID module 1108 may identify the task and/or VM to activate the virtual timer feature. For example, referring to FIGS. 1-3, VMM 104 may configure Task/VM ID module 1108 to identify and activate the virtual timer feature for VM1 106. The determination of activating the virtual timer may be based on the trust associated with any particular VM. For instance, VMM 104 may choose not to activate the virtual timer feature for a secure and trusted VM, such as VM2 110, but may turn on the virtual timer feature for an untrusted or unknown VM (e.g., VM1 106). In certain other implementations, a group ID may be used by the Task/VM ID module 608 for identifying and activating the resource allocation feature for a plurality of VMs or Tasks. For example, in one implementation, a mask may be used to select a group of VMs or Tasks. In certain implementations, random number generator source module 1104 may determine the sources of entropy used for generating the random number generator. For example, several configuration bits may be defined for selecting the various sources of entropy available, such as quantum mechanical noise sources, nuclear decay, thermal noise and clock drift. In some instances, the random number generator source may be present in software, on the processor, off the processor and/or any combination thereof. In certain implementations, noise configuration module 1106 may help determine the amount and quality of noise injected in the timer value. For example, noise configuration module 1106 may provide certain override features for noise injection parameters for noise injection modules described with reference to FIGS. 4-10, such as the noise tolerance determinator, the monotonic noise injector, the noise accumulator or any other module or component discussed for shaping the noise for the timer value. FIG. 12 is a block diagram illustrating techniques for providing a virtual timer value instead of the timer value, according to certain embodiments of the disclosure. Although in FIGS. 1-11 aspects of the disclosure have been described with respect to virtualized environments, embodiments described herein are not limited to such an environment. FIG. 12 illustrates device hardware 1202 executing privileged code in kernel privilege 1212. Device hardware 1202 may include one or more processors, besides other components for operating a computing system. In certain implementations, the processors may provide hardware support for virtualizing the timer values for specific tasks. Examples of such processors may include but are not limited to Intel®, Qualcomm® and AMD® processors. Similar to what has been discussed before, for example, with reference to FIG. 1, certain processors may be architected to share hardware resources, when possible, for more efficiently utilizing certain hardware components. For example, multiple processing cores may share caches and certain busses on the processor. Furthermore, in some implementations, multiple execution threads may operate on the same processor sharing the execution pipeline and level 1 and level 2 caches. Such sharing of hardware resources between tasks operating on the processor may enable side-channel attacks by a malicious task to retrieve sensitive information from a task executing or that may include sensitive information. In certain implementations, privileged code/binary executing at kernel privilege 1212 may include operating system code/binary running at very high privilege levels on the device hardware. In certain aspects, the level of privilege may determine the level of direct access and control of the hardware resources. Traditionally, the kernel of the operating systems and drivers operate at kernel privilege level 1212 (e.g., Ring 0 privilege level), and tasks such as applications and processes operate at user privilege level 1214 (e.g., Ring 3 privilege level). The binary executing at kernel privilege 1212 manages a first task 1206 and a second task 1208. In one scenario, second task 1208 may be a security sensitive task. An example of a security sensitive task may include an encryption operation performed by second task 1208 to establish a secure communication channel, such as a user logging into their bank account. On the other hand, first task 1206 may be a malicious task. As shown in FIG. 12, first task 1206 may be configured to mount a side-channel attack by executing one or more read timer commands to measure the response time for certain accesses to shared processor resources such as caches, buffers and busses. In certain embodiments, a task may refer to a group of executable instructions. Example of a task may include a processing thread, a process or an application that may include multiple processes. Furthermore, in certain implementations, FIG. 12 comprises virtual timer configuration module 1214 and virtual timer module 1210. Virtual timer configuration module 1214 may be implemented as part of kernel privilege 1212 in the operating system, and virtual timer module 1210 may be implemented as part of device hardware 1202, such as the processor (hardware or microcode). In certain implementations, virtual timer configuration module 1214 may configure device 1200 such that all requests for reading the time stamp counter (TSC) from the hardware (e.g., RDTSC) from first task 1206 result are trapped by device hardware 1202. In other words, device 1200 may be configured such that any attempt to read the timer value from first task 1206 results in virtual timer module 1210 returning a virtual timer value instead of the hardware timer value. Virtual timer configuration module 1214 may be implemented using any combination of techniques discussed above with reference to FIG. 11. Virtual timer module 1210 may be configured to provide first task 1206 with a virtual timer value instead of the timer value or the time stamp counter value provided by the hardware. Virtual timer module 1210 may inject noise into the timer value, by deriving a virtual timer value using the timer value and a random number. For example, in
{'bibliographic_information': "{'country': 'US', 'doc-number': '15190045', 'kind': 'B1', 'date': '20160622', 'extension': '158', 'disclaimer_text': 'This patent is subject to a terminal disclaimer.', 'invention_title': 'Noise injected virtual timer'}", 'source_file': './grant/2018/ipg181204.xml', 'source_data': 'USPTO-Grant'}