Title of Invention: ESD protection circuit for IC with separated power domains
Abstract: An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.
Detailed Description: Part general_description_paragraphs: Part BACKGROUND OF THE INVENTION: 1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. In particular, the present invention relates to an ESD protection circuit suitable for applying in an integrated circuit (IC) with separated power domains.
2. Description of the Prior Art
ESD is one of the most important reliability issues for IC products, which must be taken into consideration during the design phase of all ICs. With the advance of IC fabrication technologies, more and more circuit blocks are integrated in a single chip. In such a system-on-chip (SoC) application, the interface circuits in ICs with separated power domains are often damaged by ESD stresses.
A variety of ESD detection circuits for ICs with separated power domains were proposed. FIG. 1 and FIG. 2 respectively illustrate the traditional ESD protection circuits. In FIG. 1, the labels VDD1 and VSS1 represent power rails in a first power domain; VDD2 and VSS2 represent power rails in a second power domain. The PMOS MPESD and the NMOS MNESD are used to protect the interface circuits between the two power domains.
Generally, ESD occurs when one pin of an IC is grounded and another pin of the IC contacts an electrostatically pre-charged object. In the circuit of FIG. 1, when VDD1 is zapped by a positive ESD stress with VSS2 grounded, the ESD energy will be conducted to the gate terminals of MP2 and MN2 through MP1. MNESD, which is a gate-grounded NMOS (GGNMOS), will be turned on to clamp the gate potential of MN2. Therefore, MN2 can be protected against ESD damages.
For the circuit in FIG. 1, when VDD1 is zapped by a positive ESD stress with VDD2 grounded, the parasitic P+/N-well diode (between the signal line and VDD2) in MPESD will clamp the gate potential of MP2 to protect MP2 against ESD damages. Similarly, when VSS1 is zapped by a negative ESD stress with VSS2 grounded, the parasitic N+/P-well diode (between VSS2 and the signal line) in MNESD will clamp the gate potential of MN2 to protect MN2 against ESD damages. Further, when VSS1 is zapped by a negative ESD stress with VDD2 grounded, the gate-VDD PMOS (GDPMOS) MPESD will be turned on to clamp the gate potential of MP2. Therefore, MP2 can be protected against ESD damages.
In FIG. 2, two diodes DP and DN are used to protect MP2 and MN2. When the ESD overstress voltage appears at the gate terminals of MP2 and MN2, DP and DN will clamp the voltage across the gate oxides of MP2 and MN2. With the power-rail ESD clamp circuit between VDD2 and VSS2, MP2 and MN2 can be protected against ESD damages.
FIG. 3 illustrates an ESD protection circuit proposed in “ESD protection design to overcome internal damages on interface circuits of a CMOS IC with multiple separated power pins” reported by M.-D. Ker, C.-Y. Chang, and Y.-S. Chang in IEEE Trans. Components and Packaging Technologies, vol. 27, no. 3, pp. 445-451, September 2004. In this circuit, two ESD clamp devices MNESD1 and MNESD2 are placed between VDD2 and the signal line, and between the signal line and VSS2, respectively.
When VSS1 is zapped by a negative ESD stress with VDD2 grounded, MNESD1 will be turned on to clamp the gate potential of MP2. When VSS1 is zapped by a negative ESD stress with VSS2 grounded, the parasitic N+/P-well diodes (between VSS2 and the signal line) in MNESD1 and MNESD2 will clamp the gate potential of MN2 to protect MN2. The gate terminal of MNESD1 is connected to its source terminal, so MNESD1 is turned off under normal circuit operating conditions.
When VDD1 is zapped by a positive ESD stress with VSS2 grounded, the GGNMOS MNESD2 will be turned on to clamp the gate potential of MN2 to protect MN2 against ESD damages. When VDD1 is zapped by a positive ESD stress with VDD2 grounded, MNESD1 will act as a diode-connected NMOS to clamp the gate potential of MP2.
Part SUMMARY OF THE INVENTION: The invention provides several new ESD protection circuits for ICs with separated power domains. The first embodiment according to the invention is an ESD protection circuit including a P-type MOSFET. The P-type MOSFET is coupled between a first circuit in a first power domain and a second circuit in a second power domain. The source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. The gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. The drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. The body terminal of the P-type MOSFET is also coupled to the connection node.
The second embodiment according to the invention is an ESD protection circuit including a detection unit and a discharging unit. The detection unit is configured in a first power domain. The discharging unit is configured in a second power domain and coupled to the detection unit. The discharging unit is turned off during normal power operations and triggered by the detection unit in an ESD event.
The advantage and spirit of the invention may be understood by the following recitations together with the appended drawings.
Part DETAILED DESCRIPTION OF THE INVENTION: Please refer to FIG. 4, which illustrates the ESD protection circuit in the first embodiment according to the invention. In this embodiment, the ESD protection circuit includes a PMOS (MPESD). The labels VDD1 and VSS1 represent power rails in a first power domain; VDD2 and VSS2 represent power rails in a second power domain. As shown in FIG. 4, MPESD is coupled between a first circuit (MP1, MN1) in the first power domain and a second circuit (MP2, MN2) in the second power domain.
The source and body terminals of MPESD are coupled to a connection node for connecting the first circuit and the second circuit. The gate terminal of MPESD is coupled to VDD2. The drain terminal of MPESD is coupled to VSS2. In actual applications, the gate terminal of MPESD can be coupled to VDD2 via a resistor (not shown).
MPESD is used to clamp the voltage across the gate oxides of MP2 and MN2. When VDD1 is zapped by a positive ESD stress with VSS2 grounded, the ESD energy will be conducted to the gate terminals of MP2 and MN2 through MP1. Since the gate terminal of MPESD is connected to VDD2, which is floating in this ESD condition, MPESD will be turned on when the ESD overstress voltage appears at the gate terminals of MP2 and MN2. Therefore, the gate voltage and MN2 will be clamped by MPESD under this ESD condition. Moreover, since VDD2 is biased under normal circuit operating conditions, MPESD will not be turned on to degrade the signal.
When VSS1 is zapped by a negative ESD stress with VSS2 grounded, the parasitic P+/N-well diode (between VSS2 and the connection node) in MPESD will clamp the gate potential of MN2 to protect MN2 against ESD damages.
FIG. 5 shows an embodiment based on the circuit in FIG. 4. Compared to the embodiment in FIG. 4, the ESD protection circuit in FIG. 5 further includes an N MOS (MNESD) to provide additional protection. The drain terminal of MNESD is coupled to the connection node. The other terminals (gate, source, and body) of MNESD are coupled to VSS2. As shown in FIG. 5, the gate terminal of MNESD can be coupled to VSS2 via a resistor.
When VDD1 is zapped by a positive ESD stress with VSS2 grounded, MNESD will be turned on to clamp the gate voltage of MN2. When VSS1 is zapped by a negative ESD stress with VSS2 grounded, the parasitic N+/P-well diode (between VSS2 and the connection node) in MNESD will clamp the gate potential of MN2 to protect MN2 against ESD damages.
FIG. 6 shows another embodiment based on the circuit in FIG. 4. Compared to the embodiment in FIG. 4, the ESD protection circuit in FIG. 6 also further includes a clamp NMOS (MNESD) to provide additional protection. In this embodiment, the drain terminal of MNESD is coupled to VDD2. The gate and source terminals of MNESD are both coupled to the connection node. The body terminal of MNESD is coupled to VSS2. As shown in FIG. 6, the gate terminal of MNESD can be coupled to the connection node via a resistor.
The function of MPESD in FIG. 6 is the same as that in FIG. 4. When VDD1 is zapped by a positive ESD stress with VSS2 grounded, MPESD will be turned on to clamp the gate voltage of MN2. When VDD1 is zapped by a positive ESD stress with VDD2 grounded, MNESD will act as a diode-connected NMOS to protect MP2. When VSS1 is zapped by a negative ESD stress with VDD2 grounded, MNESD will be turned on to clamp the gate potential of MP2. When VSS1 is zapped by a negative ESD stress with VSS2 grounded, the parasitic P+/N-well diode (between VSS2 and the connection node) in MPESD and the parasitic N+/P-well diode (between VSS2 and the connection node) in MNESD will clamp the gate potential of MN2 to protect MN2.
FIG. 7(A) shows another embodiment based on the circuit in FIG. 4. In this embodiment, the drain terminal of MP3 is coupled to VSS2 via a first resistor (R1). And, the ESD protection circuit further includes a discharging component 70 coupled between the connection node and VSS2. As shown in FIG. 7(A), the discharging component 70 has a trigger terminal coupled to the node between MP3 and R1. Through the trigger terminal, the discharging component 70 is turned off during normal power operations and triggered by MP3 in an ESD event.
FIG. 7(B) through FIG. 7(E) illustrates several examples of the discharging component 70. As shown in these figures, the discharging component 70 can be one selected from the group consisting of: an NMOS with its gate as the trigger terminal, an NPN BJT, a P-type substrate-triggered SCR, and an NMOS with its body as the trigger terminal and its gate coupled to VSS2 via a second resistor (R2).
Please refer to FIG. 8, which illustrates the ESD protection circuit in the second embodiment according to the invention. In this embodiment, the ESD protection circuit includes a detection unit 82 and a discharging unit 84. The detection unit 82 is configured in the first power domain (VDD1, VSS1). The discharging unit 84 is configured in the second power domain (VDD2, VSS2) and coupled to the detection unit 82. The discharging unit 84 is turned off during normal power operations and triggered by the detection unit 82 in an ESD event.
FIG. 9 shows an exemplary circuit of the detection unit 82 and the discharging unit 84. In this example, the detection unit 82 includes a capacitor (C), a first resistor (R1), and a PMOS (MP3). The capacitor and the first resistor are formed in series between VDD1 and VSS1. As shown in FIG. 9, the gate terminal of MP3 is coupled to the node between C and R1. The source terminal of MP3 is coupled to VDD1. The drain terminal of MP3 is coupled to and used for triggering the discharging unit 84.
Also as shown in FIG. 9, the discharging unit 84 includes a second resistor (R2) and two NMOSs (MNESD and MN3). The drain terminal of MNESD is coupled to a connection node for connecting the first circuit (MP1, MN1) and the second circuit (MP2, MN2). The gate terminal of MNESD is coupled to the drain terminal of MP3. The source terminal of MNESD is coupled to VSS2. The drain terminal of MN3 is coupled to the drain terminal of MP3. The gate terminal of MN3 is coupled to VDD2 via R2. The source terminal of MN3 is coupled to VSS2.
In the example shown in FIG. 9, MP3 is used to turn on MNESD under ESD conditions. When VDD1 is zapped by a positive ESD stress with VSS2 grounded, MP3 will be turned on to boost the gate voltage of MNESD due to the RC delay. Therefore, MNESD will be turned on to protect MN2. The function of MN3 is turning off MNESD during normal circuit operations.
Since MN3 in FIG. 9 is turned on under normal circuit operating conditions, MP3 and MN3 can be combined as an inverter (INV1), as shown in FIG. 10. Moreover, INV1 can be viewed as a triggering component. The triggering component has a positive power end coupled to VDD1 and a negative power end coupled to VSS1. An input of the triggering component is coupled to a node between R1 and C. An output of the triggering component is coupled to and used for triggering the discharging unit 84.
In actual applications, INV1 can be replaced by an M-input NAND with all inputs coupled together or an N-input NOR with all inputs coupled together. Herein, M and N are positive integers larger than 1, respectively.
In the embodiment of FIG. 10, the discharging unit 84 is an NMOS (MNESD). When VDD1 is zapped by a positive ESD stress with VSS2 grounded, the PMOS in INV1 will be turned on to boost the gate voltage of MNESD due to the RC delay. Therefore, MNESD will be turned on to protect MN2. The NMOS in INV1 is turned on to turn off MNESD under normal circuit operating conditions.
Please refer to FIG. 11, which illustrates an embodiment similar to that in FIG. 10. The discharging unit 84 in this embodiment is also an NMOS (MNESD). However, in this embodiment, the body terminal of MNESD is coupled to the output of INV1. The gate terminal of MNESD is coupled to the second negative power line via a resistor (R2). In this embodiment, MNESD can provide similar functions as that in FIG. 10. Furthermore, as shown in FIG. 12(A) and FIG. 12(B), MNESD can also be replaced by an NPN BJT or a P-type substrate-triggered SCR.
FIG. 13 shows another exemplary circuit of the detection unit 82 and the discharging unit 84. In FIG. 13, the detection unit 82 is formed by a resistor (R) and a capacitor (C) coupled in series between VDD1 and VSS1. The RC circuit is used to control the discharging unit 84, MPESD. Under normal circuit operating conditions, the RC circuit sends the VDD1 voltage to the gate terminal of MPESD to turn off MPESD. When VDD1 is zapped by a positive ESD stress with VSS2 grounded, MPESD will be turned on to clamp the gate voltage of MN2 due to the RC delay. Therefore, MN2 can be protected under ESD conditions.
As shown in FIG. 14(A), the ESD clamp device MPESD in FIG. 13 can be replaced by a PMOS with its gate coupled to VDD2 via a resistor (R2) and its body coupled to the node between R1 and C. Further, as shown in FIG. 14(B) and FIG. 14(C), the ESD clamp device MPESD in FIG. 13 can also be replaced by a PNP BJT or an N-type substrate-triggered SCR.
In this invention, several new ESD protection circuits are proposed. All the circuits can effectively provide ESD protection functions for interface circuits between different power domains.
With the example and explanations above, the features and spirits of the invention will be hopefully well described. Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teaching of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.


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