Title of Invention: ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME Abstract: In an array substrate and a method of manufacturing the array substrate, an array substrate includes a first switching element, a second switching element, a third switching element and a fourth switching element. The first switching element is electrically connected to a first data line. The second switching element is electrically connected to a second data line adjacent to the first data line. The third switching element is electrically connected to a data power line interposed between the first and second data lines. The fourth switching element is electrically connected to a gate power line receiving a voltage having different polarity from a voltage applied to the data power line. Therefore, light transmittance, opening ratio and display quality are improved. Detailed Description: PRIORITY STATEMENT This application claims priority under 35 USC §119 to Korean Patent Application No. 2009-3560, filed on Jan. 16, 2009 and Korean Patent Application No. 2009-32787, filed on Apr. 15, 2009 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety. BACKGROUND OF THE INVENTION 1. Field of the Invention Example embodiments of the present invention relate to an array substrate and a method of manufacturing the array substrate. More particularly, example embodiments of the present invention relate to an array substrate capable of light transmittance, opening ratio and optical characteristics and a method of manufacturing the array substrate. 2. Description of the Related Art A liquid crystal display (LCD) device that is one of flat panel display devices has been widely used in various fields. The LCD device includes an array substrate having a pixel electrode and an opposite substrate having a common electrode to form an electric field. Also, the LCD device further includes a liquid crystal layer interposed between the array substrate and the opposite substrate. When a voltage difference is applied to the pixel electrode and the common electrode, an electric field is formed between the pixel electrode and the common electrode. Liquid crystals of the liquid crystal layer vary arrangement in response to the electric field applied thereto, and thus light transmittance of the liquid crystal layer is changed by controlling polarization of an incident light, thereby displaying an image. The LCD device also controls a switching element electrically connected to each of the pixel electrodes, and a plurality of signal lines such as a gate line and a data line to apply the voltage to the pixel electrode. The LCD device receives an input image signal from an externally provided graphic controller. The input image signal includes luminance information of the pixels. Each of the pixels receives a data voltage corresponding to the luminance information. Each of pixels of the LCD device displays an image of a luminance corresponding to a gray-scale of the image signal based on the pixel voltage difference between the data voltage applied to the pixel and a common voltage applied to the common electrode. The range of the pixel voltage difference applied to the pixel and common electrodes is predetermined by a driving part of the LCD device. The driving part of the LCD device may be directly mounted on the array substrate as a chip type, or may be attached to the array substrate using a flexible circuit film. The integrated circuit chip is expensive in manufacturing the LCD device. In order to reduce the manufacturing cost, the range of the pixel voltage difference is restricted. Also, parasite capacitance may be formed between the data lines, so that image display quality of the LCD device may be deteriorated. In addition, when the number of the gate and data lines on the array substrate is increased, opening ratio of the display device is decreased. SUMMARY OF THE INVENTION Example embodiments of the present invention provide an array substrate capable of light transmittance, opening ratio and optical characteristics. Example embodiments of the present invention provide a method of manufacturing the above-mentioned array substrate. According to one aspect of the present invention, an array substrate includes a first switching element, a second switching element, a third switching element and a fourth switching element. The first switching element is electrically connected to a first data line. The second switching element is electrically connected to a second data line adjacent to the first data line. The third switching element is electrically connected to a data power line interposed between the first and second data lines. The fourth switching element is electrically connected to a gate power line receiving a voltage having different polarity from a voltage applied to the data power line. Voltages having opposite polarities may be applied to the first and second data lines, respectively. The array substrate may further include a first gate line substantially parallel with the gate power line, a first pixel electrode electrically connected to the first switching element, a second pixel electrode electrically connected to the second switching element, a first common electrode electrically connected to the third switching element, and a second common electrode electrically connected to the fourth switching element. The first pixel electrode and the first common electrode may be disposed in a first pixel region, and the second pixel electrode and the second common electrode may be disposed in a second pixel region adjacent to the first pixel region along the first gate line. The array substrate may further include a fifth switching element electrically connected to the first data line, a sixth switching element electrically connected to the second data line, a seventh switching element electrically connected to the gate power line, and an eighth switching element electrically connected to the data power line. The array substrate may further include a first gate line extended in a direction substantantially parallel with the gate power line, a third pixel electrode electrically connected to the fifth switching element, a fourth pixel electrode electrically connected to the sixth switching element, a third common electrode electrically connected to the seventh switching element, and a fourth common electrode electrically connected to the eighth switching element. The third pixel electrode and the third common electrode may be disposed in a third pixel region adjacent to the first pixel region along the first data line, and the fourth pixel electrode and the fourth common electrode may be disposed in a fourth pixel region adjacent to the second pixel region along the first data line. The array substrate may further include a first gate line extended in a direction substantially parallel with the gate power line, and a second gate line adjacent to the first gate line. The first, second, third and fourth switching elements may be electrically connected to the first gate line, and the fifth, sixth, seventh and eighth switching elements may be electrically connected to the second gate line. Each of the first and second pixel electrodes and the first and second common electrodes may include a plurality of branching parts. The branching part of the first pixel electrode may alternate with the branching part of the first common electrode, and the branching part of the second pixel electrode may alternate with the branching part of the second common electrode. According to another aspect of the present invention, there is provided a method of manufacturing an array substrate as follows. A gate line and a gate power line substantially parallel with the gate line are formed. A first data line, a second data line and a data power line may be interposed between the first data line and the second data line. A first switching element electrically connected to the first data line and the gate line, a second switching element electrically connected to the second data line and the gate line, a third switching element electrically connected to the data power line and the gate line, and a fourth switching element electrically connected to the gate power line and the gate line are formed. The gate power line receives a voltage having different polarity from a voltage applied to the data power line. A first pixel electrode electrically connected to the first switching element, a second pixel electrode electrically connected to the second switching element, a first common electrode electrically connected to the third switching element and a second common electrode electrically connected to the fourth switching element may further be formed. The first pixel electrode and the first common electrode may be formed in a first pixel region, and the second pixel electrode and the second common electrode may be formed in a second pixel region adjacent to the first pixel region along the gate line. The first, second, third and fourth switching elements may be formed by forming a fifth switching element electrically connected to the first data line, a sixth switching element electrically connected to the second data line, a seventh switching element electrically connected to the gate power line, and an eighth switching element electrically connected to the data power line. According to still another aspect of the present invention, an array substrate includes a first pixel electrode, a second pixel electrode, a first common electrode and a second common electrode. The first pixel electrode is overlapped with first and second power lines extended along a gate line. The first and second power lines receive voltages having different polarities, respectively. The first pixel electrode is electrically connected to a first data line. The second pixel electrode is overlapped with the first and second power lines. The second pixel electrode is electrically connected to a second data line receiving a voltage having an opposite polarity to a voltage applied to the first data line. The first common electrode is overlapped with the first and second power lines, and is electrically connected to the first power line. The second common electrode is overlapped with the first and second power lines, and is electrically connected to the second power line. A capacitance of each of first storage capacitors formed by overlapping the first and second pixel electrodes and the first and second common electrodes with the first power line may be substantially the same as a capacitance of each of second storage capacitors formed by overlapping the first and second pixel electrodes and the first and second common electrodes with the second power line. The first common electrode may be partially overlapped with the first and second data lines. The array substrate may further include a third data line adjacent to the second data line. The second common electrode may be partially overlapped with the second and third data lines, and the first and second common electrodes may be overlapped with first and second regions of the second data line, respectively. The first region may have substantially the same size as the second region. The first and second pixel electrodes and the first and second common electrodes may form a V-shape. The first and second pixel electrodes may include a plurality of first bending branches, and the first and second common electrodes comprise a plurality of second bending branches. The first bending branches of the first pixel electrode may alternate the second bending branches of the first common electrode, and the first bending branches of the second pixel electrode may alternate the second bending branches of the second common electrode. A distance between adjacent first and second bending branches adjacent to the first data line or the third data line may be greater than a distance between adjacent first and second bending branches adjacent to a center between the first and second data lines and a center between the second and third data lines. According to further still another aspect of the present invention, a method of manufacturing an array substrate is provided as follows. A gate line, a first power line and a second power line are formed. The gate line and the first and second power lines are substantially parallel with each other. A first data line and a second data line are adjacent to the first data line. The second data line receives a voltage having opposite polarity to a voltage applied to the first data line. The first and second data lines are substantially parallel with each other. A first pixel electrode electrically connected to the first data line, a second pixel electrode electrically connected to the second data line, a first common electrode electrically connected to the first power line and a second common electrode electrically connected to the second power line are formed. The first and second pixel electrodes and the first and second common electrodes are overlapped with the first and second power lines. According to further still another aspect of the present invention, an array substrate includes a pixel electrode and a common electrode. The pixel electrode is electrically connected to a first data line. The common electrode is electrically connected to a second data line receiving a voltage having opposite polarity to a voltage applied to the first data line. The common electrode is overlapped with the first and second data lines and being adjacent to the first data line. An overlapped area between the common electrode and the first data line may be substantially the same as an overlapped area between the common electrode and the second data line. According to further still another aspect of the present invention, a method of manufacturing an array substrate is provided as follows. A first data line and a second data line adjacent to the first data line are formed. The second data line receives a voltage having opposite polarity to a voltage applied to the first data line. A pixel electrode electrically connected to the first data line and a common electrode electrically connected to the second data line are formed. The pixel electrode and the common electrode are overlapped with the first and second data lines. According to some example embodiments of the present invention, the range of the pixel voltage difference is increased by the power lines receiving the various voltages, so that light transmittance of the array substrate may be increased. Also, the storage capacitors are formed using the power lines, so that opening ratio of the array substrate is increased. In addition, a parasite capacitor that may be generated in the data lines by overlapping between the data lines and the pixel electrodes receiving different voltages may be prevented, so that image display quality of the array substrate may be increased. BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the present invention will become more apparent by describing in detailed example embodiments thereof with reference to the accompanying drawings. FIG. 1 is a plan view illustrating illustrating a liquid crystal display (LCD) device in accordance with one embodiment of the present invention; FIG. 2 is a cross-sectional view taken along a line I-I′ shown in FIG. 1; FIG. 3 is a cross-sectional view taken along a line II-II′ shown in FIG. 1; FIG. 4 is an equivalent circuit diagram illustrating the LCD device shown in FIG. 1; FIG. 5 is a plan view illustrating an LCD device in accordance with another embodiment of the present invention; FIG. 6 is a cross-sectional view taken along a line III-III′ shown in FIG. 5; FIG. 7 is a cross-sectional view taken along a line IV-IV′ shown in FIG. 5; FIG. 8 is an equivalent circuit diagram illustrating the LCD device shown in FIG. 5; FIG. 9 is a plan view illustrating an LCD device in accordance with still another embodiment of the present invention; FIG. 10 is a plan view illustrating an LCD device in accordance with further still another embodiment of the present invention; FIG. 11 is an equivalent circuit diagram illustrating the LCD device shown in FIG. 10; FIG. 12 is a plan view illustrating an LCD device in accordance with further still another embodiment of the present invention; FIG. 13 is an equivalent circuit diagram illustrating pixels of an LCD device in accordance with still another embodiment of the present invention; FIG. 14 is waveform diagrams of voltages applied to a first gate line, a first swing voltage line and a second swing voltage line of FIG. 13; FIG. 15 is an equivalent circuit diagram illustrating pixels of an LCD device in accordance with still another embodiment of the present invention; FIG. 16 is an equivalent circuit diagram illustrating pixels of an LCD device in accordance with still another embodiment of the present invention; FIG. 17 is an equivalent circuit diagram illustrating pixels of an LCD device in accordance with still another embodiment of the present invention; FIG. 18 is a plan view illustrating an LCD device in accordance with still another embodiment of the present invention; FIG. 19 is an equivalent circuit diagram illustrating pixels of the LCD device of FIG. 18; FIG. 20 is a plan view illustrating an LCD device in accordance with still another embodiment of the present invention; and FIG. 21 is an equivalent circuit diagram illustrating pixels of the LCD device of FIG. 20. DETAILED DESCRIPTION OF THE INVENTION The present invention is described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the present invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Example embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures) of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings. FIG. 1 is a plan view illustrating illustrating a liquid crystal display (LCD) device in accordance with one embodiment of the present invention. FIG. 2 is a cross-sectional view taken along a line I-I′ shown in FIG. 1. FIG. 3 is a cross-sectional view taken along a line II-II′ shown in FIG. 1. Referring to FIGS. 1 to 3, the LCD device includes an array substrate 100, an opposite substrate 200 and a liquid crystal layer 300. In FIG. 1, a first pixel PX(n,n) and a second pixel PX(n,n+1) of the LCD device are illustrated. The array substrate 100 includes a lower base substrate 110. A pixel region is defined in the lower base substrate 110. The lower base substrate 110 has a plate shape. A transparent material that may be used for the lower base substrate 110 may include glass, quartz, synthetic resin, etc. These may be used alone or in a combination thereof. A gate metal layer is formed on the lower base substrate 110. The gate metal layer may include a gate line 121, a gate power line 125 and a storage line 131. The gate line 121 is extended in a longitudinal direction to transmit a gate signal. Each of the gate lines 121 includes a first gate electrode 124a, a second gate electrode 124b, a third gate electrode 124c and a fourth gate electrode 124d that are upwardly protruded. The first and third gate electrodes 124a and 124c correspond to the first pixel PX(n,n). The second and fourth gate electrodes 124b and 124d correspond to the second pixel PX(n,n+1). The storage line 131 receives a voltage such as a common voltage, and is extended in the longitudinal direction. Each of the storage lines 131 is interposed between two adjacent gate lines 121, and is adjacent to a lower gate line 121 of the two adjacent gate lines 121. The storage line 131 includes a first storage electrode 133a and a second storage electrode 133b. The first storage electrode 133a corresponds to the first pixel PX(n,n), and the second storage electrode 133b corresponds to the second pixel PX(n,n+1). The gate power line 125 transmits a power voltage or a ground voltage in each frame. The gate power line 125 may be extended in the longitudinal direction, and each of the gate power line 125 includes a gate power line 127 upwardly protruded. Each of the first and second storage electrodes 133a and 133b has a rectangular shape having two chamfered corners adjacent to a lower side. Alternatively, each of the first and second storage electrodes 133a and 133b may have various shapes and various arrangements. The gate insulating layer 140 is formed on the lower base substrate 110 to cover the gate line 121, the first, second, third and fourth gate electrodes 124a, 124b, 124c and 124d, the storage line 131 and the first and second storage electrodes 133a and 133b. A first semiconductor layer 154a, a second semiconductor layer 154b, a third semiconductor layer 154c and a fourth semiconductor layer 154d are formed on the gate insulating layer 140. The first, second, third and fourth semiconductor layers 154a, 154b, 154c and 154d may include hydrogenated amorphous silicon, polycrystalline silicon, etc. The first, second, third and fourth semiconductor layers 154a, 154b, 154c and 154d are formed on the first, second, third and fourth gate electrodes 124a, 124b, 124c and 124d, respectively. Two first ohmic contact layers 163a and 165a are formed on the first semiconductor layers 154a. Two second ohmic contact layers 163b and 165b are formed on the second semiconductor layers 154b. Two third ohmic contact layers 163c and 165c are formed on the third semiconductor layers 154c. Two fourth ohmic contact layers 163d and 165d are formed on the fourth semiconductor layers 154d. The first to fourth ohmic contact layers 163a, 163b, 163c, 163d, 165a, 165b, 165c and 165d may include n+ hydrogenated amorphous silicon that is implanted by n type impurities at a high concentration, silicide, etc. A data metal layer including a first data line 171a, a second data line 171b, a data power line 171c, a first drain electrode 175a, a second drain electrode 175b, a third drain electrode 175c and a fourth drain electrode 175d is formed on the first to fourth ohmic contact layers 163a, 163b, 163c, 163d, 165a, 165b, 165c and 165d and the gate insulating layer 140. The first and second data lines 171a and 171b transmit data signals. The data power line 171c transmits a driving voltage or a ground voltage by a frame. When the driving voltage is applied to the data power line 171c, the ground voltage may be applied to the gate power line 125. When the ground voltage is applied to the data power line 171c, the driving voltage is applied to the gate power line 125. The first and second data lines 171a and 171b and the data power line 171c are extended in a horizontal direction crossing the gate line 121 and the storage line 131. The first and second data lines 171a and 171b and the data power line 171c include a first source electrode 173 a, a second source electrode 173b and a third source electrode 173c. The first, second and third source electrodes 173a, 173b and 173c have U-shape bent toward the first, second and third gate electrodes 124a, 124b and 124c, respectively. The fourth source electrode 173d that has a U-shape bent toward the fourth gate electrode 124d is extended toward an upper portion of the gate power electrode 127 to be electrically connected to the gate power electrode 127. An end of a rod shape of each of the first, second, third and fourth drain electrodes 175a, 175b, 175c and 175d faces each of the first, second, third and fourth source electrodes 173a, 173b, 173c and 173d, and is surrounded by each of the first, second, third and fourth source electrodes 173a, 173b, 173c and 173d. A first contact electrode 177a connected to the first drain electrode 175a is overlapped with a left half of the first storage electrode 133a, and a second contact electrode 177b connected to the second drain electrode 175b is overlapped with a right half of the second storage electrode 133b. A third contact electrode 177c connected to the third drain electrode 175c is overlapped with a right half of the first storage electrode 133a, and a fourth contact electrode 177d connected to the fourth drain electrode 175d is overlapped with a left half of the second storage electrode 133b. The first gate electrode 124a, the first source electrode 173a, the first drain electrode 175a and the first semiconductor layer 154a form a first switching element Qa. The second gate electrode 124b, the second source electrode 173b, the second drain electrode 175b and the second semiconductor layer 154b form a second switching element Qb. The third gate electrode 124c, the third source electrode 173c, the third drain electrode 175c and the third semiconductor layer 154c form a third switching element Qc. The fourth gate electrode 124d, the fourth source electrode 173d, the fourth drain electrode 175d and the fourth semiconductor layer 154d form a fourth switching element Qd. A channel of the first switching element Qa is formed in the first semiconductor layer 154a between the first source electrode 173a and the first drain electrode 175a. A channel of the second switching element Qb is formed in the second semiconductor layer 154b between the second source electrode 173b and the second drain electrode 175b. A channel of the third switching element Qc is formed in the third semiconductor layer 154c between the third source electrode 173c and the third drain electrode 175c. A channel of the fourth switching element Qd is formed in the fourth semiconductor layer 154d between the fourth source electrode 173d and the fourth drain electrode 175d. A first one 163a of the two first ohmic contact layers 163a and 165a is interposed between the first semiconductor layer 154a and the first source electrode 173a to decrease contact resistance between the first semiconductor layer 154a and the first source electrode 173a, and a second one 165a of the two first ohmic contact layers 163a and 165a is interposed between the first semiconductor layer 154a and the first drain electrode 175a to decrease contact resistance between the first semiconductor layer 154a and the first drain electrode 175a. A first one 163b of the two second ohmic contact layers 163b and 165b is interposed between the second semiconductor layer 154b and the second source electrode 173b to decrease contact resistance between the second semiconductor layer 154b and the second source electrode 173b, and a second one 165b of the two second ohmic contact layers 163b and 165b is interposed between the second semiconductor layer 154b and the second drain electrode 175b to decrease contact resistance between the second semiconductor layer 154b and the second drain electrode 175b. A first one 163c of the two third ohmic contact layers 163c and 165c is interposed between the third semiconductor layer 154c and the third source electrode 173c to decrease contact resistance between the third semiconductor layer 154c and the third source electrode 173c, and a second one 165c of the two third ohmic contact layers 163c and 165c is interposed between the third semiconductor layer 154c and the third drain electrode 175c to decrease contact resistance between the third semiconductor layer 154c and the third drain electrode 175c. A first one 163d of the two fourth ohmic contact layers 163d and 165d is interposed between the fourth semiconductor layer 154d and the fourth source electrode 173d to decrease contact resistance between the fourth semiconductor layer 154d and the fourth source electrode 173d, and a second one 165d of the two fourth ohmic contact layers 163d and 165d is interposed between the fourth semiconductor layer 154d and the fourth drain electrode 175d to decrease contact resistance between the fourth semiconductor layer 154d and the fourth drain electrode 175d. The first switching element Qa is electrically connected to the first data line 171a. The third switching element Qc is electrically connected to the data power line 171c. The first and third switching elements Qa and Qc are formed in the first pixel PX(n,n). The second switching element Qb is electrically connected to the second data line 171b. The fourth switching element Qd is electrically connected to the gate power line 125. The second and fourth switching elements Qb and Qd are formed in the second pixel PX(n,n+1). Voltages having opposite levels are applied to the first and second data lines 171a and 171b, respectively. Voltages having opposite levels are applied to the data power line 171c and the gate power line 125. A gate contact hole 129 is formed on the gate power electrode 127 through the gate insulating layer 140. The fourth source electrode 173d is connected to the gate power line 125 through the gate contact hole 129. The data insulating layer 180 is formed on the gate insulating layer 140 to cover the first and second data lines 171a and 171b, the data power line 171c, the first, second, third and fourth source electrodes 173a, 173b, 173c and 173d and the first, second, third and fourth drain electrodes 175a, 175b, 175c and 175d. A first contact hole 185a is formed on the first contact electrode 177a through the data insulating layer 180. A second contact hole 185b is formed on the second contact electrode 177b through the data insulating layer 180. A third contact hole 185c is formed on the third contact electrode 177c through the data insulating layer 180. A fourth contact hole 185d is formed on the fourth contact electrode 177d through the data insulating layer 180. A plurality of pixel electrodes 191 is formed on the data metal layer 180. The pixel electrodes 191 includes a first pixel electrode 191a, a second pixel electrode 191b, a first common electrode 191c and a second common electrode 191d. The pixel electrodes 191 may include a transparent conductive material, a reflective material, etc. Examples of the transparent conductive material that may be used for the pixel electrodes 191 may include indium tin oxide (ITO), indium zinc oxide (IZO), carbon nano tube (CNT), etc. Examples of the reflective material that may be used for the pixel electrodes 191 may include aluminum, silver, chromium, an alloy thereof, etc. These may be used alone or in a combination thereof. The first and second pixel electrodes 191a and 191b and the first and second common electrodes 191c and 191d are formed on the data insulating layer 180. In another embodiment, a transparent metal layer may be patterned to form the first and second pixel electrodes 191a and 191b and the first and second common electrodes 191c and 191d. The first pixel electrode 191a makes contact with the first contact electrode 177a, and the second pixel electrode 191b makes contact with the second contact electrode 177b. The first common electrode 191c makes contact with the third contact electrode 177c, and the second common electrode 191d makes contact with the second contact electrode 177d. For example, the pixel electrodes 191 may have a rectangular shape. The first pixel electrode 191a and the second common electrode 191d are electrically connected to the first and fourth drain electrodes 175a and 175d, respectively. The first pixel electrode 191a and the second common electrode 191d include a first central extension extended in the horizontal direction, and a first branching part extended from the first central extension. An upper portion of the first branching part with respect to the central extension is extended in a first diagonal direction, and a lower portion of the first branching part with respect to the first central extension is extended in a second diagonal direction. The first diagonal direction may form an angle of about 45 degrees or about 225 degrees with respect to the gate line 121. The second diagonal direction may form an angle of 135 degrees or about 315 degrees with respect to the gate line 121. The second pixel electrode 191b and the first common electrode 191c are electrically connected to the second and third drain electrodes 175b and 175c, respectively. The second pixel electrode 191b and the first common electrode 191c include a second central extension extended in the horizontal direction, and a second branching part extended from the second central extension. An upper portion of the second branching part with respect to the second central extension is extended in the first diagonal direction, and a lower portion of the first branching part with respect to the central extension is extended in the second diagonal direction. The first diagonal direction may form an angle of about 45 degrees or about 225 degrees with respect to the gate line 121. The second diagonal direction may form an angle of 135 degrees or about 315 degrees with respect to the gate line 121. That is, the first and second branching parts in each of the first and second pixels PX(n,n) and PX(n,n+1) alternate with each other to form a comb shape. The first pixel electrode 191a is physically and electrically connected to the first drain electrode 175a through the first contact hole 185a to receive a voltage from the first drain electrode 175a. The second pixel electrode 191b is physically and electrically connected to the second drain electrode 175b through the second contact hole 185b to receive a voltage from the second drain electrode 175b. The first common electrode 191c is physically and electrically connected to the third drain electrode 175c through the third contact hole 185c to receive a voltage from the third drain electrode 175c. The second common electrode 191d is physically and electrically connected to the fourth drain electrode 175d through the fourth contact hole 185d to receive a voltage from the fourth drain electrode 175d. The first and second pixel electrodes 191a and 191b, the first and second common electrodes 191c and 191d and the liquid crystal layer 300 form a liquid crystal capacitor Clc. In the present embodiment, although the first, second, third and fourth switching elements Qa, Qb, Qc and Qd are turned off, a voltage difference between the first and second pixel electrodes 191a and 191b and the first and second common electrodes 191c and 191d is maintained. The first drain electrode 175a electrically connected to the first pixel electrode 191a and the third drain electrode 175c electrically connected to the first common electrode 191c are overlapped with the first storage electrode 133a, and the gate insulating layer 140 is interposed between the first drain electrode 175a and the first storage electrode 133a and between the first common electrode 175c and the first storage electrode 133a, thereby forming the first and third storage capacitors Csta and Cstc. The second drain electrode 175b electrically connected to the second pixel electrode 191b and the fourth drain electrode 175d electrically connected to the second common electrode 191d are overlapped with the second storage electrode 133b, and the gate insulating layer 140 is interposed between the second drain electrode 175b and the second storage electrode 133b and between the second common electrode 175d and the second storage electrode 133b, thereby forming the second and fourth storage capacitors Cstb and Cstd. The first, second, third and fourth storage capacitors Csta, Cstb, Cstc and Cstd maintain the voltage difference applied to the liquid crystal capacitor Clc. The lower alignment layer 11 is formed on the lower base substrate 110 including the first and second pixel electrodes 191a and 191b and the first and second common electrodes 191c and 191d to align liquid crystal molecules of the liquid crystal layer 300 in a vertical direction. Thus, the liquid crystal molecules of the liquid crystal layer 300 are aligned from the array substrate 100 toward the opposite substrate 200. The opposite substrate 200 faces the array substrate 100. The opposite substrate 200 includes an upper base substrate 210, a light blocking pattern 220, a color filter pattern 230, an overcoating layer 250 and an upper alignment layer 21. The light blocking pattern 220 may prevent leakage of light between adjacent pixel electrodes 191, and defines an opening region facing the pixel electrode 191. The color filter pattern 230 is formed in the opening region defined by the light blocking pattern 220. The color filter pattern 230 may include a red color filter, a green color filter and a blue color filter. The overcoating layer 230 covers the color filter pattern 230 and the light blocking pattern 220. The overcoating layer 250 is formed on the light blocking pattern 220 and the color filter pattern 230. The overcoating layer 250 may include an insulating material. For example, the overcoating layer 250 may have a substantially flat surface to cover the color filter 230. Alternatively, the overcoating layer 250 may be omitted. The upper alignment layer 21 is formed on the overcoating layer 250 to align the liquid crystal molecules of the liquid crystal layer 300 in the vertical direction. The liquid crystal layer 300 is interposed between the array substrate 100 and the opposite substrate 200. The liquid crystal layer 300 includes the liquid crystal molecules having positive dielectric anisotropy. When the electric field is not applied to the liquid crystal molecules, the liquid crystal molecules are vertically aligned with respect to the surfaces of the array substrate 100 and the opposite substrate 200. The liquid crystal molecules of the liquid crystal layer 300 vary arrangement in response to the electric field formed between the first and second pixel electrodes 191a and 191b and the first and second common electrodes 191c and 191d, and thus light transmittance of the liquid crystal layer 300 is changed. For example, when different voltages are applied to the first and second pixel electrodes 191a and 191b and the first and second common electrodes 191c and 191d, an electric field substantially parallel with the surfaces of the array substrate 100 and the opposite substrate 200 may be formed between the first and second pixel electrodes 191a and 191b and the first and second common electrodes 191c and 191d. Then, the vertically aligned liquid crystal molecules with respect to the array substrate 100 and the opposite substrate 200 change arrangement, so that the liquid crystal molecules are inclined toward the horizontal direction substantially parallel with the direction of the electric field. Thus, polarizing characteristics of the liquid crystal layer 300 are changed, so that the light transmittance of the liquid crystal layer 300 is changed, thereby displaying an image. When the LCD device uses the vertically aligned liquid crystal molecules, contrast ratio and viewing angle of the LCD device are improved. Also, two different voltages having opposite polarities with respect to the common voltage are applied to the pixel electrode 191, so that driving voltage of the switching elements Qa, Qb, Qc and Qd and the response speed of the liquid crystal molecules are improved. Furthermore, the interference caused by a kickback voltage is prevented, thereby preventing flicker on the LCD device. FIG. 4 is an equivalent circuit diagram illustrating the LCD device shown in FIG. 1. Referring to FIGS. 1 to 4, the LCD device includes a plurality of signal lines Dj, Dj+1, −Dj+1/2, +Dj+1, Gi and Gi+1. The LCD device may further include a plurality of pixels electrically connected to the signal lines Dj, Dj+1, −Dj+1/2, Gi and Gi+1. The pixels are arranged in a matrix shape. In FIG. 2, the LCD device includes the array substrate 100, the opposite substrate 200 facing the array substrate 100, and the liquid crystal layer 300 interposed between the array substrate 100 and the opposite substrate 200. The signal lines Dj, Dj+1, −Dj+1/2, Gi and Gi+1 includes a first gate line Gi, a second gate line Gi+1, a first data line Dj, a second data line Dj+1, a third data line −Dj+1/2 and a fourth data line +Dj+1/2. The first and second gate lines Gi and Gi+1 transmit a gate signal (a scan signal). The first and second data lines Dj and Dj+1 transmit a data voltage. The driving voltage and the ground voltage are applied to the third and fourth data lines −Dj+1/2 and +Dj+1/2 by the frame. The first gate line Gi, the second gate line Gi+1 and the fourth data line +Dj+1/2 are extended in a column direction, and are substantially parallel with each other. The first data line Dj, the second data line Dj+1 and the third data line −Dj+1/2 are extended in a row direction, and are substantially parallel with each other. The voltages having the opposite polarities are applied to the first and second data lines Dj and Dj+1, respectively. The voltages having the opposite polarities are applied to the third data line −Dj+1/2 and the fourth data line +Dj+1/2. The driving voltage and the ground voltage are alternately applied to the third and fourth data lines −Dj+1/2 and +Dj+1/2 in every frame. For example, an area corresponding to the first and second data lines Dj and Dj+1 is smaller than an area corresponding to the third and fourth data lines −Dj+1/2 and +Dj+1/2. For example, the first and second data lines Dj and Dj+1 of FIG. 4 correspond to the first and second data lines 171a and 171b of FIG. 1 formed in the first and second pixels PX(n,n) and PX(n,n+1). The first gate line Gi of FIG. 4 corresponds to the gate line 121 of FIG. 1. The third and fourth data lines −Dj+1/2 and +Dj+1/2 of FIG. 4 correspond to the data power line 171c and the gate power line 125 of FIG. 1. The first, second, third and fourth switching elements Qa, Qb, Qc and Qd are electrically connected to the first and second data lines 171a and 171b, the data power line 171c and the gate power line 125. Referring again to FIG. 4, the first, second, third and fourth data lines Dj, Dj+1, −Dj+1/2 and +Dj+1/2 are electrically connected to the first, second, third and fourth switching elements Qa, Qb, Qc and Qd. Alternatively, the first and second data lines Dj and Dj+1 may be electrically connected to a fifth switching element Qe and a sixth switching element Qf, respectively. Also, the third and fourth data lines −Dj+1/2 and +Dj+1/2 may be electrically connected to a seventh switching element Qg and a eighth switching element Qh. The fifth, sixth, seventh and eighth switching elements Qe, Qf, Qg and Qh may be electrically connected to the second gate line Gi+1. A third pixel PX(n+1,n) and a fourth pixel PX(n+1,n+1) maybe disposed on a next line to the first and second pixels PX(n,n) and PX(n,n+1). The fifth and eighth switching elements Qe and Qh may be formed in the third pixel PX(n+1,n). The sixth and seventh switching elements Qf and Qg may be formed in the fourth pixel PX(n+1,n+1). Referring again to FIGS. 1 and 4, the branching part of the first pixel electrode 1191a and the branching part of the first common electrode 191c are alternately arranged. The branching part of the second pixel electrode 191b and the branching part of the second common electrode 191d are alternately arranged. For example, a branching part of the third pixel electrode electrically connected to the fifth switching element Qe and a branching part of the fourth common electrode electrically connected to the eighth switching element Qh are alternately arranged. Also, a branching part of the fourth pixel electrode electrically connected to the sixth switching element Qf and a branching part of the third common electrode electrically connected to the seventh switching element Qg are alternately arranged. Voltages having opposite polarities are applied to the first data line Dj and the second data line Dj+1. Voltages having opposite polarities are applied to the third data line −Dj+1/2 and the fourth data line +Dj+1/2. Thus, adjacent pixels of the first, second, third and fourth pixels PX(n,n), PX(n,n+1), PX(n+1,n) and PX(n+1,n+1) receive different voltages having the opposite polarities. Referring again to FIGS. 1 to 4, the storage line 131 is overlapped with the pixel electrodes electrically connected to the first, second, third, fourth, fifth, sixth, seventh and eighth switching elements Qa, Qb, Qc, Qd, Qe, Qf, Qg and Qh to form first, second, third, fourth, fifth, sixth, seventh and eighth storage capacitors Cst1, Cst2, Cst3, Cst4, Cst5, Cst6, Cst7 and Cst8, respectively. For example, the ground voltage may be applied to the storage line 131. The liquid crystal layer 300 in the first, second, third and fourth pixels PX(n,n), PX(n,n+1), PX(n+1,n) and PX(n+1,n+1) functions as a dielectric material of the liquid crystal capacitor Clc. The liquid crystal capacitor Clc is formed by the pixel electrodes and the liquid crystal layer 300. The liquid crystal layer 300 has dielectric anisotropy. When the electric field is not applied to the liquid crystal layer 300, the liquid crystal molecules of the liquid crystal layer 300 are vertically aligned between the array substrate 100 and the opposite substrate 200. Hereinafter, a method of manufacturing the array substrate will be explained with reference to FIGS. 1 to 4. The gate line 121, the gate power line 125 and the storage line 131 are substantially parallel with
{'application_number': '<application-reference appl-type="utility">\n<document-id>\n<country>US</country>\n<doc-number>12469429</doc-number>\n<date>20090520</date>\n</document-id>\n</application-reference>', 'publication_number': '<publication-reference>\n<document-id>\n<country>US</country>\n<doc-number>20100182523</doc-number>\n<kind>A1</kind>\n<date>20100722</date>\n</document-id>\n</publication-reference>', 'source_file': './application/2010/ipa100722.xml', 'source_data': 'USPTO-Application'}