Title of Invention: Method of manufacturing a semiconductor device Abstract: There is provided a method of manufacturing a semiconductor device having a TFT with sufficient characteristics and little fluctuation by accurately controlling the addition amount of impurity ions to the semiconductor layer using an ion doping device. A semiconductor device having a TFT showing sufficient and stable characteristics may be obtained by increasing the ratio of the dopant amount in the doping gas and decreasing the ambient atmosphere components (C, N, O) and hydrogen to be simultaneously added with the impurity ions at the time of doping. Detailed Description: Part general_description_paragraphs: Part BACKGROUND OF THE INVENTION: 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that has a circuit configured with a thin film transistor (hereinafter referred to as the TFT). For example, the present invention relates to an optoelectronic device, such as a liquid crystal display panel, and an electronic apparatus comprising such an optoelectronic device as a component. In the present specification, the term “semiconductor device” refers in general to such a device that exhibits its intended function by employing semiconductor characteristics. Accordingly, all of an optoelectronic device, a semiconductor circuit, and an electronic apparatus are included in the semiconductor devices. 2. Description of the Related Art Recently, techniques for constituting a thin film transistor (TFT) by employing a semiconductor thin film (having a thickness approximately in the range from several nm to several hundreds nm) formed on a substrate that has an insulating surface has been drawing much attention. The thin film transistor has been widely used in various electronic devices such as an IC and an optoelectronic device. In particular, development of the thin film transistor as a switching element for an image display device has been urged. A TFT employing a crystalline semiconductor film (typically a polysilicon film or the like) as its semiconductor film has been widely used more often since the crystalline semiconductor film has a larger mobility that that of an amorphous semiconductor film (typically an amorphous silicon film or the like). However, the polysilicon TFT has an disadvantage in that impurities, defects or the like in a channel forming region tend to have significant adverse effects on TFT characteristics, especially on a threshold characteristic, although the polysilicon TFT has many advantages over the amorphous silicon TFT. For example, a negative shift of a threshold voltage from 0 V leads to a normally-on characteristic, thereby resulting in the situation in which a normal switching operation cannot be realized. In order to overcome these problems, it has been known to control a threshold value of a TFT by adding boron ions or the like into a channel forming region with an ion doping apparatus or an ion implantation apparatus. In general, in an IC fabrication process, impurity ions are selectively implanted with an ion implantation apparatus. In such an ion implantation apparatus, impurity ions are accelerated by means of an electrical field and then a mass separation is performed, so that only target ions are implanted. This ion implantation apparatus can exhibit high precision, although the apparatus is very expensive and its throughput is low. The ion implantation apparatus is not suitable particularly for mass-production of an active matrix display device in which a large-size substrate has to be processed. In view of the above fact, for mass-production of the active matrix display device in which a large-size substrate has to be processed, an ion doping apparatus is typically employed since it can realize a batch process for adding impurity ions into a large-size semiconductor thin film. In this ion doping apparatus, source material gases are flowed into a chamber and plasmarized therein by a known method, thereby ionizing the contained impurity ions to be added to a crystalline semiconductor film. Although other ions than the target ion species may be added into the film since no mass separation is performed, a satisfactory throughput can be realized. In the above-mentioned conventional method for controlling a threshold value, it is required to set an amount of boron ions to be added into the channel forming region to an extremely small level. However, when the ion doping apparatus is employed, it has been difficult to precisely control the boron ions of a minute amount to be doped into the channel forming region. For example, in the case where the boron ions are added into a region to become a channel forming region in a sample (semiconductor substrate) with an ion doping apparatus, boron concentration distributions as shown in FIGS. 23 to 25 can be usually obtained. Specifically, FIGS. 23 to 25 show graphs indicating boron concentration distributions (obtained by SIMS measurements) in the case where the boron ions are added at an accelerating voltage of 80 keV in accordance with the conventional method. In each of FIGS. 23 to 25, the horizontal axis represents the depth, while the vertical axis represents the concentration. Moreover, the impurity concentrations contained in the sample prior to the doping process were also measured. FIG. 26 shows the concentration distribution of hydrogen (H) contained in the sample prior to the doping process. Similarly, FIG. 27 shows the concentration distribution of carbon (C), while FIG. 28 shows the concentration distributions of oxygen (O) and nitrogen (N). As shown in FIGS. 23 to 25, it has been clearly observed that nitrogen (N), oxygen (O), carbon (C), and hydrogen (H) are also added through the doping process in addition to boron. Thus, it is clear that during the doping, the component of the ambient atmosphere are also added into the sample. The present inventors have come to the idea that the thus added ambient atmospheric components may cause the TFT characteristics to be varied. Since the doping amount has to be controlled depending on various parameters (an RF power, a frequency, a degree of vacuum, a gas concentration, or the like), these parameters are required to be always maintained in the certain ranges. However, even when these parameters were set within the certain ranges, the threshold values varied. In accordance with the conventional ion doping method, the TFT characteristics such as the threshold characteristic may also be varied due to the ambient atmospheric components unintentionally added, thereby resulting in the fact that the TFT characteristics cannot be precisely controlled. Part SUMMARY OF THE INVENTION: The source material gas conventionally used for doping is diborane (B2H6) of 0.1% diluted with hydrogen. With this gas, the dopant species ratio in the resultant plasma is low, and furthermore, it takes a long period of time to dose. Accordingly, a larger amount of ambient atmospheric components may be ionized during the process to be simultaneously added into the sample. As one of the measures to overcome the above-mentioned problems, in accordance with the present invention, the concentration ratio of impurity ions (typically, B, P) with respect to hydrogen is increased, thereby resulting in reduction in the concentrations of the ambient atmospheric components (C, N, O) to be simultaneously added into a semiconductor layer or realizing the situation in which no ambient atmospheric components are added into the semiconductor film. The TFT including a channel forming region formed in accordance with the present invention can exhibit excellent TFT characteristics with reduced variations for the respective TFT characteristics. According to the present invention, for example, the threshold value that is one of the TFT characteristics can be extremely precisely controlled. The structure of the present invention disclosed in the present specification relates to a method of manufacturing a semiconductor device in which after an insulating film is formed on a semiconductor film, an impurity element providing the semiconductor film with the p-type conductivity through the insulating film is ion-doped at the concentration in the range from 1×1015 to 5×1017 atoms/cm3, comprising the step of doping a boron element into the semiconductor film by employing a source material gas including diborane diluted with hydrogen to the concentration range from 0.5% to 5%, preferably to the range from 0.5% to 1%. Further, another structure of the present invention relates to a method of manufacturing a semiconductor device, comprising the step of ion-doping an impurity element providing a semiconductor film with the p-type conductivity or an impurity element providing the semiconductor film with the n-type conductivity at the concentration in the range from 1×1015 to 5×1017 atoms/cm3, characterized in that the concentration of carbon to be ion-doped simultaneously with the impurity element in the semiconductor film is set to be at 3×1017 atoms/cm3 or less. Further, another structure of the present invention relates to a method of manufacturing a semiconductor device, comprising the step of ion-doping an impurity element providing a semiconductor film with the p-type conductivity or an impurity element providing the semiconductor film with the n-type conductivity at the concentration in the range from 1×1015 to 5×1017 atoms/cm3, characterized in that the concentration of nitrogen to be ion-doped simultaneously with the impurity element in the semiconductor film is set to be at 1×1017 atoms/cm3 or less. Further, another structure of the present invention relates to a method of manufacturing a semiconductor device, comprising the step of ion-doping an impurity element providing a semiconductor film with the p-type conductivity or an impurity element providing the semiconductor film with the n-type conductivity at the concentration in the range from 1×1015 to 5×1017 atoms/cm3, characterized in that the concentration of oxygen to be ion-doped simultaneously with the impurity element in the semiconductor film is set to be at 3×1017 atoms/cm3 or less. Further, in the above-mentioned respective structures, the method of manufacturing semiconductor device is characterized in that the concentration of hydrogen to be ion-doped simultaneously with the impurity element in the semiconductor film is set to be at 1×1019 atoms/cm3 or less. Further, another structure of the present invention relates to a method of manufacturing a semiconductor device, comprising the step of ion-doping an impurity element providing a semiconductor film with the p-type conductivity or an impurity element providing the semiconductor film with the n-type conductivity at the concentration in the range from 1×1015 to 5×1017 atoms/cm3, characterized in that the concentration of hydrogen to be ion-doped simultaneously with the impurity element in the semiconductor film is set to be at 1×1019 atoms/cm3 or less. Further, in the above-mentioned respective structures, the ion doping is characterized by the fact that no mass separation is performed, which means that a plasma doping method rather than an ion implantation method is performed. In addition, although it may be possible to add only hydrogens into the semiconductor film with the ion implantation method, the resultant implantation depth tends to be very deep since the mass of hydrogen is very small. Accordingly, it is very difficult to add hydrogen to a desired depth at a desired concentration. On the other hand, with the ion doping which does not involve the mass separation, only B atoms, or alternatively B atoms coupled with hydrogen, can be added into the semiconductor film, when a diborane gas is used. Further, in the above-mentioned respective structures, the ion-doping is characterized in that the doping is performed through an insulating film after the insulating film is formed on the semiconductor film. By adjusting a film thickness of the insulating film, the implantation depth can be adjusted, so that the ions can be implanted to a desired depth in the semiconductor film at a desired concentration. In addition, this insulating film also functions to protect the semiconductor film against contamination derived from the ambient atmosphere. It should be noted that in the case where the ions can be added to a desired depth in the semiconductor film at a desired concentration without providing the insulating film, it is not necessary to provide any insulating film. Further, in the above-mentioned respective structures, the semiconductor film may function as a channel forming region of the TFT. In other words, the ion doping in the aforementioned method can be referred to as the channel doping. Furthermore, in the present invention, the ambient atmospheric components (C, N, O) or hydrogen to be simultaneously added during the doping process can be reduced by increasing the ratio of dopants (here, referring to an impurity element that provides the semiconductor with the n-type or p-type conductivity) against the doping gas during the channel doping process. Further, in the above-mentioned respective structures, the method is characterized in that in the ion-doping step, a gas containing diborane, BF2, or boron is used to dope the impurity element providing the semiconductor film with the p-type conductivity. Further, in the above-mentioned respective structures, the method is characterized in that in the ion-doping step, either one of gases containing P or As, and phosphine is used, and the impurity element providing the semiconductor film with the n-type conductivity is doped. Further, in the above-mentioned respective structures, the method is characterized in that the impurity element is boron, and the boron element is doped into the semiconductor film by employing a source material gas that contains diborane diluted with hydrogen to the concentration in the range from 0.5% to 5%. Further, in the above-mentioned respective structures, the method is characterized in that the impurity element is boron, and the boron element is doped into the semiconductor film by employing a source material gas that contains diborane diluted with hydrogen to the concentration in the range from 0.5% to 1%. Note that, in the present specification, the term gate electrode refers to a portion of gate wiring positioned above the channel forming region via a gate insulating film. In addition, the present invention is not limited to the specific means disclosed in the above. In contrast, any means capable of suppressing the addition of ambient atmospheric components to be added during the doping as low as possible, and thereby controlling an amount of impurity ions to be added into a region that is to become the channel forming region to a minute amount (desirably, to the range from 1×1015 to 5×1017 atoms/cm3), may be employed. For example, as one of the other means, the concentration of the ambient atmospheric components (C, N, O) to be added into the semiconductor layer may be controlled by adjusting a film thickness of an insulating film deposited on the semiconductor film. Part DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS: Embodiments of the present invention will be described below. The present invention is intended to precisely control an added amount of impurity ions (to function as donors or acceptors) contained in a channel forming region by employing an ion doping apparatus. Among the conditions as employed in FIGS. 23 to 25, a source material gas including diborane diluted with hydrogen to the concentration of 5% instead of 0.1% was used, while the other conditions, for example an ion current density and a total dosage, were set to be at the identical levels. After performing the doping process under these conditions, the impurity concentrations were measured. FIG. 1 shows the thus measured concentrations (B, H, C), FIG. 2 shows the thus measured concentrations (B, H, N), and FIG. 3 shows the thus measured concentrations (B, H, O). In FIG. 23, it is observed that the concentrations of doped borons and carbons are substantially at the same level. Since boron and carbon have substantially the same molecular amounts, substantially the same concentration profiles (the peak locations) are obtained. On the other hand, in FIG. 1, it is observed that the carbon concentration shows a concentration profile different from that of the boron concentration, and furthermore is at the reduced level as compared with that in FIG. 23. In FIG. 1, the carbon concentrations in the depth range from 1000 Å to 12000 Å are 1×1015 to 2×1017 atoms/cm3. In addition, the boron concentration has its peak at around 1500 Å in the range from 1×1015 to 5×1018 atoms/cm3. Similarly, in FIG. 2, it is observed that the nitrogen concentration is reduced by one-tenth of that in FIG. 24. In FIG. 2, the nitrogen concentrations in the depth range from 1000 Å to 12000 Å are 5×1015 to 1×1017 atoms/cm3. In addition, it is also observed that the oxygen concentration in FIG. 3 is reduced as compared to that in FIG. 25. In FIG. 3, the oxygen concentrations in the depth range from 1000 Å to 12000 Å are 8×1015 to 5×1017 atoms/cm3. When comparing FIGS. 1 to 3 indicating the data obtained after the doping with the references (FIGS. 26 to 28) indicating the data obtained prior to the doping, the respective concentrations of the ambient atmospheric components (C, N, O) are almost at the same. Thus, it can be seen that almost no ambient atmospheric components (C, N, O) are simultaneously doped into the semiconductor layer at the doping. This phenomena are derived from the fact that the percentage of boron elements with respect to the total number of atoms in a reaction chamber can be increased by increasing the concentration of diborane. Within the reaction chamber evacuated to the degree of vacuum of 10−6 to 10−7 Torr, small amounts of gases of the other elements (C, N, O) still remain. However, when a source material gas having a concentration higher than those gases of the other elements (C, N, O) is flowed into the chamber to perform the doping, almost no other elements (C, N, O) are doped to the sample. When the concentration of diborane is increased, the percentage of boron elements with respect to the total number of atoms in the reaction chamber can be increased, a set forth above. In addition, the number of ions to be ionized and doped is believed to be limited to a certain level since only a predetermined amount of energy is applied for ionization. This fact is also believed to have a certain effect on the above phenomena. More specifically, in contrast to an increase in the percentage of boron elements, the numbers of ions of the other elements (C, N, O) to be doped are believed to be reduced. Hydrogen atoms are hardly influenced since their percentage with respect to the total number of atoms is extremely high, as compared to the other elements. It should be noted, however, that by adding hydrogens to the semiconductor layer, the added hydrogens are allowed to be diffused in a subsequent heat treatment process, which improves the TFT characteristics. This advantage cannot be obtained with the ion implantation method in which hydrogen atoms are not simultaneously added to the target semiconductor layer. Moreover, when the impurity elements of the same concentration are intended to be added under the different dilution conditions, a larger amount of hydrogen atoms is added with a lower dilution concentration. For example, with the dilution concentration of 0.1%, more hydrogen atoms of approximately ten times as many as those in the case with the dilution concentration of 5% are added to the semiconductor layer. When a larger amount of hydrogen atoms is added, more damages are applied to the semiconductor layer. Accordingly, it is preferable to set in the semiconductor film, the concentration of hydrogen atoms to be ion doped simultaneously with the impurity elements at 1×1019 atoms/cm3 or lower. When the boron concentration of 1×1017 atoms/cm3 is intended to be realized in the semiconductor layer by employing a source material gas which contains diborane diluted with hydrogen to the concentration of 5%, a period of time to be required for the process is significantly reduced to 16 sec, which makes it difficult to control the apparatus. Accordingly, it is desirable to employ a source material gas including diborane diluted with hydrogen to the concentration in the range from 0.5% to 1%. The above mentioned reduction in the process time is also believed to be related to the fact that almost no ambient atmospheric components (C, N, O) are doped into the semiconductor layer. The TFT including a channel forming region made of the thus formed semiconductor layer exhibits excellent characteristics, and a desired threshold value can be realized. FIG. 29 shows results of the Gaussian function fitting. With the ion doping method, two peaks (one is derived from B+ ions, and the other from B2+ ions) appear, unlike the case with the ion implantation method. The data in FIG. 29 were obtained with a sample in which a silicon oxide film (4000 Å) is deposited on a semiconductor substrate. Although the impurity ions are described as boron ions in the above, the present invention is not limited to such a case. Instead of boron, other impurity ions for providing the p-type conductivity, or any impurity ions for providing the n-type conductivity (P ions or As ions), can be used. In addition, the present invention is not limited to the specific means for increasing the concentration of diborane as disclosed in the above. For example, as one of the other means, the concentration of the ambient atmospheric components (C, N, O) to be added into the semiconductor layer may be controlled by adjusting a film thickness of an insulating film deposited on the semiconductor film. This utilizes the fact that different ions exhibit different implantation depths and distributions due to differences in molecular weights or the like. Although the above data have been obtained with semiconductor substrates as the samples, the same phenomena as set forth above can be observed with respect to a semiconductor film formed on a semiconductor substrate. In particular, by applying the above-mentioned method to a process for performing the doping to form a channel forming region of the TFT, impurity elements providing the n-type or p-type conductivity can be added at a desired concentration, thereby resulted in a desired threshold voltage being realized. The present invention having the above-described features will be further described in more detail with respect to the following embodiments. Part Embodiment 1: One of embodiments of the present invention will be described with reference to FIGS. 4A to 4D, 5A to 5C, 6A, and 6B. In particular, a method for simultaneously forming a pixel TFT and a retaining capacitance in a pixel portion as well as a TFT in a driver circuit to be disposed in the peripheral portion of the pixel portion will be described in detail. In FIG. 4A, as a substrate 101, a glass substrate made of, e.g., barium borosilicate glass, aluminum borosilicate glass, such as a #7059 glass or a #1737 glass available from Corning, may be used. Alternatively, a quartz substrate may be used as the substrate 101. In the case where the glass substrate is employed, the substrate 101 may be heat treated in advance at a temperature lower than the glass deformation temperature by about 10 to 20° C. Then, an underlying film 102 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon Oxynitride film is formed on a surface of the substrate 101 in which a TFT is to be formed, in order to prevent impurities from being diffused from the substrate 101. For example, a silicon oxynitride film 102a is formed from SiH4, NH3, and N2O with a plasma CVD method to have a thickness of 10 to 200 nm (preferably 50 to 100 nm), and then a hydrogenated silicon oxynitride film 102b is formed similarly from SiH4 and N2O to have a thickness of 50 to 200 nm (preferably 100 to 150 nm). Although the underlying film 102 is described to have a two-layer structure, a single layer of an insulating film may be deposited. Alternatively, two or more layers of insulating films may be deposited as the underlying film 102. A silicon oxynitride film is formed with a parallel-plate type plasma CVD method. For forming the silicon oxynitride film 102a, SiH4 of 10 sccm, NH3 of 100 sccm, and N2O of 20 sccm are introduced into the reaction chamber. Other parameters are set as follows: a substrate temperature of 325° C., a reaction pressure of 40 Pa, a discharge power density of 0.41 W/cm2, and a discharge frequency of 60 MHz. On the other hand, for forming the hydrogenated oxynitride silicon film 102b, SiH4 of 5 sccm, N2O of 120 sccm, and H2 of 125 sccm are introduced into the reaction chamber. Other parameters are set as follows: a substrate temperature of 400° C., a reaction pressure of 20 Pa, a discharge power density of 0.41 W/Cm2, and a discharge frequency of 60 MHz. These two films can be continuously formed only by changing the substrate temperature and switching the reaction gases to be used. The thus formed oxynitride silicon film 102a has a density of 9.28×1022/cm3. This is a fine and hard film that exhibits a slow etching rate of about 63 nm/min at 20° C. against a mixture solution (available from Stella Chemifa under commercial designation of LAL500) which contains hydrogen fluoride ammonium (NH4HF2) of 7.13% and ammonium fluoride (NH4F) of 15.4%. Such a film used as the underlying film is effective for preventing alkaline metal elements from being diffused from the glass substrate into the semiconductor layer formed on the underlying film. Then, a semiconductor layer 103a with a thickness of 25 to 80 nm (preferably 30 to 60 nm) and having an amorphous structure is formed with a plasma CVD method, a sputtering method, or the like. A semiconductor film having an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film. Alternatively, a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be employed. In the case where the amorphous silicon film is formed with a plasma CVD method, it is possible to continuously form both of the underlying film 102 and the amorphous semiconductor layer 103a. For example, after depositing the silicon oxynitride film 102a and the hydrogenated silicon oxynitride film 102b with a plasma CVD method as set forth above, the reaction gases are switched from the combination of SiH4, N2O and H2 to the combination of SiH4 and H2, or only SiH4. Then, these films can be continuously deposited without being exposed to the ambient atmosphere. As a result, surface contamination of the hydrogenated silicon oxynitride film 102b can be prevented, and variations in the characteristics and/or a threshold voltage of the resultant TFTs can be reduced. Thereafter, a crystallization process is performed to form a crystalline semiconductor layer 103b from the amorphous semiconductor layer 103a. For that purpose, various methods such as a laser annealing method, a thermal annealing method (a solid phase growth method), or a rapid thermal annealing method (RTA method) can be employed. In the case where the glass substrate or a plastic substrate that has poor heat-resistivity is to be employed, a laser annealing method is especially preferable to be performed. In the RTA method, an infrared lamp, a halogen lamp, a metal halide lamp, a Xenon lamp or the like is used as a light source. Alternatively, in accordance with the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652, the crystalline semiconductor layer 103b may be formed through a crystallization process employing catalytic elements. In the crystallization process, it is preferable to allow the hydrogens contained in the amorphous semiconductor layer to be first purged. For that purpose, a heat process is performed at 400 to 500° C. for about one hour, so that the amount of hydrogens contained in the amorphous semiconductor layer is reduced to 5 atom % or lower. By performing the crystallization process thereafter, the surface of the resultant crystallized film can be prevented from being roughened. Alternatively, when an SiH4 gas and an Ar gas are used as the reaction gases and the substrate temperature is set at 400 to 450° C. during the formation process of the amorphous silicon film with the plasma CVD method, the amount of hydrogens contained in the amorphous silicon film can be reduced to 5 atom % or lower. In such a case, no heat treatment is required to be performed for purging the contained hydrogens. In the case where the crystallization is performed with the laser annealing method, an excimer laser or an Ar laser of a pulse-oscillation type or a continuous-emission type is used as its light source. When an excimer laser of the pulse-oscillation type is used, the laser rays are shaped into a linear shape and the laser annealing process is then performed. Although the laser annealing conditions can be appropriately set, for example, a laser pulse oscillation frequency is set at 30 Hz, and a laser energy density is set in the range from 100 to 500 mJ/cm2 (typically in the range from 300 to 400 mJ/cm2). The entire substrate surface is then irradiated with the linear beam with an overlapping ratio of the linear beams at 80 to 98%. Thus, the crystalline semiconductor layer 103b can be obtained as shown in FIG. 4B. Then, a resist pattern is formed on the crystalline semiconductor layer 103b with a photolithography technique by employing a first photomask (PM1). The crystalline semiconductor layer is divided into island-patterns by dry-etching to form island-shaped semiconductor layers 104 to 108, as shown in FIG. 4C. For the dry etching process of the crystalline silicon film, a mixture gas of CF4 and O2 is used. A mask layer made of a silicon oxide film having a thickness of 50 to 200 nm is then formed with a plasma CVD method or a sputtering method. In this embodiment, a silicon oxide film having a thickness of 130 nm is formed. Thereafter, impurity elements providing the p-type conductivity are added to the entire surfaces of the island-shaped semiconductor layers at the concentration of about 1×1016 to 5×1017 atoms/cm3 for the purpose of controlling a threshold voltage (Vth) of TFTs. As the impurity elements providing the semiconductor material with the p-type conductivity, elements in Group 13 in the periodic table, such as boron (B), aluminum (Al), and gallium (Ga) are known. As the method for adding the impurity elements, the ion doping method as mentioned above is suitable. With the ion doping method, boron (B) is added by employing, as a source material gas, diborane (B2H6) diluted with hydrogens to the concentration of 0.5 to 5%, preferably 0.5 to 1%. In this embodiment, diborane diluted with hydrogens to the concentration of 5% is used as a source material gas, and the other parameters are set as follows: an accelerating voltage of 80 keV, a flow rate of 25 sccm, a current density of 50 nA, and a process period of time of 39.4 sec. Thus, borons are added to the entire surfaces of the island-shaped semiconductor layers at the concentration of about 2.6×1017 atoms/cm3. By setting the concentration of diborane at 5%, amounts of the impurity elements (carbon, nitrogen, oxygen) other than boron to be simultaneously added during the doping can be reduced. Although the impurities are added into the whole surface in the above, it is also possible to selectively add the impurities through a mask. This process is called as a channel doping process, which is preferably employed for setting a threshold voltage of, especially an n-channel TFT, within a predetermined range. The mask layer used for the control of the doping amount is then removed. Alternatively, it is possible to employ this insulating film as a gate insulating film or a portion thereof, in order to reduce the number of steps to be involved. A gate insulating film 109 is then formed. The gate insulating film 109 is formed by depositing an insulating film containing silicon to have a film thickness of 40 to 150 nm with a plasma CVD method or a sputtering method. In this embodiment, the gate insulating film 109 is formed of a silicon oxynitride film having a thickness of 120 nm. The silicon oxynitride film formed with the source material gases obtained by adding O2 into SiH4 and N2O is a suitable material for the purpose since the fixed charge density in the film is reduced. Furthermore, the silicon oxynitride film formed with the source material gases of SiH4 and N2O as well as H2 is preferable since the interface defect density at the interface with the gate insulating film can be reduced. It should be noted that the gate insulating film is not limited to such a silicon oxynitride film, but a single-layer structure or a multilayer structure of other insulating films containing silicon may be used. For example, in the case where a silicon oxide film is used, the film can be formed with a plasma CVD method in which TEOS (Tetraethyl Orthosilicate) and O2 are mixed to each other, and a discharge is generated with a reaction pressure of 40 Pa, a substrate temperature of 300 to 400° C., and a high frequency (13.56 MHz) power density of 0.0.5 to 0.8 W/cm2. The thus formed silicon oxide film can exhibit satisfactory characteristics as a gate insulating film by being subjected to a thermal annealing process at 400 to 500° C. Thereafter, as shown in FIG. 4D, a heat-resistant conductive layer 111 for forming a gate electrode is formed on the gate insulating film 109 with a first shape so as to have a thickness of 200 to 400 nm (preferably 250 to 350 nm). The heat-resistant conductive layer may be a single layer, or alternatively, have a layered-structure including a plurality of layers such as two or three layers, if necessary. The heat-resistive conductive layer in the present specification includes a film made of elements selected from the group consisting of Ta, Ti, and W, an alloy film including the aforementioned elements as constituent components, or an alloy film in which the aforementioned elements are combined. These heat-resistive conductive layers can be formed with a sputtering method or a CVD method, and it is preferable to reduce the concentration of impurities contained therein in order to obtain a low resistance. Especially, the oxygen concentration is preferably set to be at 30 ppm or lower. In this embodiment, the W film may be formed to have a thickness of 300 nm. The W film may be formed with a sputtering method employing a W target, or with a thermal CVD method employing hexafulouride tungsten (WF6). In either case, the resistance of the film is required to be lowered in order to be used as a gate electrode, so that the resistivity of the resultant W film is preferably set to be at 20 μΩ·cm or lower. The W film can have a lower resistivity with a larger grain size. However, when a larger amount of impurity elements such as oxygens is contained in the W film, crystallization is adversely affected to cause high resistance. Thus, in the case where a sputtering method is employed to form a W film, a W target with the purity of 99.9999% is employed, and sufficient attention is paid so as to prevent impurities from being mixed into the W film from the ambient atmosphere during the deposition, thereby resulting in a resistivity of 9 to 20 μΩ·cm. On the other hand, in the case where a Ta film is used as the heat-resistive conductive layer 111, the film can be similarly formed with a sputtering method. For the Ta film, an Ar gas is used as a sputtering gas. In addition, when an appropriate amount of Xe or Kr is added into the gas during the sputtering process, an internal stress of the resultant film can be relaxed so that the film can be prevented from being peeled off. The resistivity of the α-phase Ta film is about 20 μΩ·cm, and thus can be used as a gate electrode. However, the β-phase Ta film has the resistivity of about 180 μΩ·cm, which is not suitable for forming a gate electrode. Since the TaN film has a crystal structure close to that of the α-phase Ta film, the α-phase Ta film can be easily obtained by forming the underlying TaN film prior to the deposition of the Ta film. In addition, although not illustrated, it is effective to form a silicon film having a thickness of about 2 to 20 nm and doped with phosphorus (P) below the heat-resistive conductive layer 111. Thus, close adhesion to the overlying conductive film as well as prevention of oxidation can be realized, and furthermore, alkaline metal elements contained in the heat-resistive conductive layer 111 at a minute amount can be prevented from being diffused into the gate insulating film 109 having the first shape. In either case, it is preferable to set the resistivity of the heat-resistive conductive layer 111 in the range from 10 to 50 μΩ·cm. Then, other masks 112 to 117 made of a resist are formed with a photolithography technique by employing a second photomask (PM2). A first etching process is then performed. In this embodiment, an ICP etching apparatus is employed with Cl2 and CF4 as etching gases, and the etching is performed by forming plasma with an applied RF (13.56 MHz) power of 3.2 mW/cm2 under a pressure of 1 Pa. An RF (13.56 MHz) power of 224 mW/cm2 is also applied to the substrate (to a sample stage), so that substantially a negative self-biasing voltage can be applied. An etching speed of the W film under the above conditions is about 100 nm/min. In the first etching process, a time period required for the W film to be just etched away is calculated based on the above-mentioned etching speed, and the resultant time period is increased by 20% to be set as the actual etching time period. Conductive layers 118 to 123 having a first tapered shape are formed through the first etching process. As shown in FIG. 2A, the tapered angle of 15 to 30 degrees can be obtained. In order to perform the etching process without remaining any etching residue, overetching is performed in which an etching time is increased by 10 to 20%. A selection ratio of the silicon oxynitride film (the gate insulating film 109 having the first shape) with respect to the W film is about 2 to 4 (typically 3), and therefore, the exposed surface of the silicon oxynitride film can be etched away by about 20 to 50 nm through the overetching, so that a gate insulating film 134 can be formed to have a second shape in which tapered shapes are formed in the vicinity of end portions of the conductive layer having the first tapered shape. Thereafter, a first doping process is performed so that impurity elements with one conductivity type are added into the island-shaped semiconductor layers. In this embodiment, the impurity elements providing the n-type conductivity are added. The masks 112 to 117 used for forming the first-shaped conductive layers are remained, and the conductive layers 118 to 123 having the first tapered shapes are used as masks so that the impurity elements for providing the n-type conductivity are added with the ion doping method in a self-aligning manner. In order that the impurity elements for providing the n-type conductivity are added so as to pass through the tapered portion and the gate insulating film at the end portion of the gate electrode and reach the underlying semiconductor layer, the dosage is set in the range from 1×1013 to 5×1014 atoms/cm2 and the accelerating voltage is set in the range from 80 to 160 keV. As the impurity elements for providing the n-type conductivity, elements in Group 15 in the periodic table, typically phosphorus (P) or arsenic (As), can be used. In this embodiment, phosphorus (P) is used. Through the above-described ion doping method, the impurity elements for providing the n-type conductivity are added to first impurity regions 124 to 128 in the concentration range from 1×1020 to 1×1021 atoms/cm3, while the impurity elements for providing the n-type conductivity are added to a second impurity regions (A) formed below the tapered portions in the concentration range from 1×1017 to 1×1020 atoms/cm3 (although not necessarily uniformly added in the regions). In this process, in the second impurity regions (A) 129 to 132, the concentration profiles of the impurity elements for providing the n-type conductivity to be contained in at least portions overlapping with the first-shaped conductive layers 118 to 123 reflect changes in the film thickness of the tapered portions. More specifically, the concentration of phosphorus (P) to be added into the second impurity regions (A) 129 to 132 in the regions overlapping with the first-shaped conductive layers is gradually reduced inwardly from the end portion of the conductive layer. This is because the concentration of phosphorus (P) that can reach the semiconductor layer is changed depending on differences in the film thickness of the tapered portions. Then, as shown in FIG. 5B, a second etching process is performed. This etching process is similarly performed with the IPC etching apparatus by employing a mixture gas of CF4 and Cl2 as an etching gas under the conditions of an applied RF power of 3.2 W/cm2 (13.56 MHz) and a bias power of 45 mW/cm2 (13.56 MHz) under a pressure of 1.0 Pa. Thus, conductive layers 140 to 145 are formed to have a second shape obtainable under these conditions. Tapered portions are formed at respective end portions thereof, in which a thickness is gradually increased inwardly from the respective end portions. As compared with the first etching process, an isotropic etching component is increased due to a reduction in the bias power to be applied to the substrate side, so that the tapered portions are formed to have an angle of 30 to 60 degrees. In addition, the surfaces of the gate insulating films 134 having the second shape are etched way by about 40 nm, and third gate insulating films 170 are newly formed. Thereafter, the impurity elements for providing the n-type conductivity are doped with a reduced dosage at a higher accelerating voltage, as compared to the first doping process. For example, the accelerating voltage is set in the range from 70 to 120 keV and the dosage is set at 1×1013 atoms/cm2. The concentrations of the impurity elements to be included in the regions overlapping with the conductive layers 140 to 145 having the second shape are set to be in the range from 1×1016 to 1×1018 atoms/cm3. Thus, the second impurity regions (B) 146 to 150 are formed. Then, impurity regions 156 and 157 with the opposite conductivity are formed in the island-shaped conductive layers 104 and 106 that constitute p-channel TFTs. The impurity elements for providing the p-type conductivity are doped with the second-shaped conductive layers 140 and 142 as masks to form the impurity regions in a self-aligning manner. In this case, the island-shaped semiconductor layers 105, 107, 108 that constitute the n-channel TFTs are entirely covered with resist masks 151 to 153 formed by employing a third photomask (PM3). The impurity regions 156 and 157 in this stage are formed with the ion doping method employing diborane (B2H6). The concentrations of the impurity elements for providing the p-type conductivity in the impurity regions 156 and 157 are set in the range from 2×1020 to 2×1021 atoms/cm3. However, these impurity regions 156 and 157 when viewed in more detail can be divided into three regions containing the impurity elements for providing the n-type conductivity. More specifically, third impurity regions 156a and 157a contain the impurity elements for providing the n-type conductivity in the range from 1×1020 to 1×1021 atoms/cm3, fourth impurity regions (A) 156b and 157b contain the impurity elements for providing the n-type conductivity in the range from 1×1017 to 1×1020 atoms/cm3, and the fourth impurity regions (B) 156c and 157c contain the impurity elements for providing the n-type conductivity in the range from 1×1016 to 5×1018 atoms/cm3. However, when the concentrations of the impurity elements for providing the p-type conductivity are set to be at 1×1019 atoms/cm3 or more in the impurity regions 156b, 156c, 157b, and 157c, and the concentrations of the impurity elements for providing the p-type conductivity are set to become 1.5 to 3 times larger in the third impurity regions 156a and 157a, no adverse problems occur for allowing the third impurity regions to function as source and drain regions of the p-channel TFTs. In addition, portions of the fourth impurity regions (B) 156c and 157c are formed to overlap with the conductive layer 140 or 142 having the second tapered shape. Thereafter, as shown in FIG. 6A, a first interlayer insulating film 158 is formed over the gate electrodes and the gate insulating films. The first interlayer insulating film may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a layered film in which these films are combined. In either case, the first interlayer insulating film 158 is formed of an inorganic insulating material. The film thickness of the first interlayer insulating film 158 is set to be in the range from 100 to 200 nm. When a silicon oxide film is to be employed, the film is formed with the plasma CVD method in which TEOS and O2 are mixed to each other, and the discharge is generated under the conditions of a reaction pressure of 40 Pa, a substrate temperature in the range of 300 to 400° C., and a high frequency (13.56 MHz) power density of 0.5 to 0.8 W/cm2. When a silicon oxynitride film is to be employed, the film is formed of a silicon oxynitride film formed with the plasma CVD method from SiH4, N2O, and NH3, or a silicon oxynitride film formed with the plasma CVD method from SiH4 and N2O. The film formation conditions in these cases are set as follows: a reaction pressure in the range from 20 to 200 Pa, a substrate temperature in the range of 300 to 400° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W/cm2. Alternatively, a hydrogenated silicon oxynitride film formed from SiH4, N2O, and H2 may also be used. A silicon nitride film can also be formed with a plasma CVD method from SiH4 and NH3. Then, a process for activating the impurity elements providing the p-type and n-type conductivities added at the respective concentrations is performed. This process is realized as a thermal annealing method which employs a furnace anneal oven. Alternatively, a laser annealing method, or a rapid thermal annealing method (RTA method) may be applied for that purpose. The thermal annealing is performed within a nitrogen atmosphere having the oxygen concentration of 1 ppm or lower, preferably 0.1 ppm or lower, at 400 to 700° C., typically 500 to 600° C. In this embodiment, the thermal annealing is performed at 550° C. for 4 hours. In the case where a plastic substrate having a low heating endurance temperature is employed, a laser annealing method is preferably employed. After the activation process, the surrounding atmospheric gases are switched to a hydrogen atmosphere containing hydrogens at the concentration of 3 to 100%. A heat process is performed in this atmosphere at 300 to 450° C. for 1 to 12 hours so that the island-shaped semiconductor layers are hydrogenated. In this process, dangling bonds existing in the island-shaped semiconductor layers at the concentration of 1016 to 1018/cm3 are terminated with thermally excited hydrogens. As another means for the hydrogenation, plasma hydrogenation (in which hydrogens excited by means of plasma are employed) may be performed. In either case, the defect densities in the island-shaped semiconductor layers 104 to 108 are preferably set to be at 1016/cm3 or lower. For that purpose, hydrogens are added at the concentration of about 0.01 to 0.1 atomic %. Then, a second interlayer insulating film made of an organic insulating material is formed to cover the first interlayer insulating film. As the organic insulating material, polyimide, polyamide, polyimideamide, BCB (benzocyclobutene), or the like may be used. By thus forming the second interlayer insulating film of an organic insulating material, the surface thereof can be easily planarized. In addition, since the organic insulating material has in general a low dielectric constant, a parasitic capacitance can be reduced. However, the organic insulating material tends to absorb water, and therefore, is not suitable for the use as a protective film. Accordingly, as in this embodiment, it is preferable to combine the organic insulating film with a silicon oxide film, a silicon nitride film, or a silicon oxynitride film formed as the first interlayer insulating film 158. Thereafter, a resist mask having a predetermined pattern is formed by employing a fourth photomask (PM4) to form contact holes that reach the respective impurity regions formed in the island-shaped semiconductor layers so as to function as a source or drain region. These contact holes are formed with a dry etching method. In this case, a mixture gas of CF4, O2, and He is used as an etching gas to first etch away the second interlayer insulating film 159 made of the organic insulating material. The first interlayer insulating film 158 is then etched away with a mixture gas of CF4 and O2 as an etching gas. Furthermore, the etching gas is switched to CHF3 so as to enhance a selection ratio
{'bibliographic_information': "{'country': 'US', 'doc-number': '11448041', 'kind': 'B2', 'date': '20060607', 'extension': '33', 'invention_title': 'Method of manufacturing a semiconductor device'}", 'source_file': './grant/2008/ipg080930.xml', 'source_data': 'USPTO-Grant'}