Title of Invention: Semiconductor device and method for fabricating the same Abstract: A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insulation film 26 on the base substrate 10 with the interconnection 18 formed on, the step of etching the insulation film 26 with the insulation film 24 as a stopper to form openings in a region containing a region where the interconnection 18 is formed, and the step of etching the insulation film 24 in the opening to form sidewall insulation films 30 of the insulation film 24 on the side walls of the interconnection 18 and form contact holes 34, 36 to be connected to the base substrate 10 in alignment with the interconnection 18. Summary of Invention: BACKGROUND OF THE INVENTION &lsqb;0001&rsqb; The present invention relates to a method for fabricating a semiconductor device, and more specifically a semiconductor device including contact holes in alignment with a base pattern and a method for fabricating the same. &lsqb;0002&rsqb; As LSIs become larger-scaled, more micronization of devices is pursued. &lsqb;0003&rsqb; To realize semiconductor integrated circuits including gates, interconnections and contact holes of more micronized dimensions, conventionally wavelengths of the exposure radiation for the photolithography have been made shorter to thereby improve resolving power. &lsqb;0004&rsqb; While minimum resolved dimensions have been thus diminished, various device structures which decrease margins for alignment between lithography steps have been studied. In place of diminishing dimensions of patterns to be formed, dimensions of devices have been decreased. &lsqb;0005&rsqb; As such structure, self-aligned contact (hereinafter called SAC), for example, is known. &lsqb;0006&rsqb; The conventional SAC structure will be explained in comparison with a case including no SAC structure. &lsqb;0007&rsqb; As shown in FIG. 24A, in a case that two gate electrodes 208 are formed on a silicon substrate 200, and an inter-layer insulation film 226 is formed on the gate electrodes 208, when a contact hole 228 is opened between the two gate electrodes 208 down to the silicon substrate 200, the gate electrodes 208 must be arranged, considering in advance alignment precision for opening the contact hole 228. &lsqb;0008&rsqb; That is, gaps (a) between the contact hole 228 and the gate electrodes 208, which are larger than an alignment precision must be ensured so that when a conducting film is buried in the contact hole 228, the conducting film does not short-circuit with the gate electrodes 208 (FIG. 24B). Accordingly, a gap between the gate electrodes 208 is subject to the contact hole, which hinders further micronization. &lsqb;0009&rsqb; In contrast to this, as shown in FIG. 24C, gate electrodes 208 are covered with an insulation film 230 having etching selectivity with the inter-layer insulation film 226. The insulation film 230 functions as an etching stopper in etching the inter-layer insulation film 226 to thereby protect the insulation film 232 (on the gate electrodes 208 and on the side walls) from excessive etching, so that the gate electrodes 208 are never exposed in the opening 228 by over-etching of the insulation film 232. Accordingly, a conducting film buried in the contact hole 228 is not short-circuited with the gate electrodes 208. &lsqb;0010&rsqb; Thus, when disalignment occurs in the lithography step of forming the contact hole 228, an opening down to a silicon substrate 200, is defined only by the gate electrodes 208 and the insulation film 230, and even when the contact hole 228 is a little disaligned with the gate electrodes 208, the opening can be formed in a prescribed position (FIG. 24D). This enables the device to be micronized. &lsqb;0011&rsqb; A method for fabricating the conventional semiconductor device including the SAC structure will be specifically explained by means of a structure of the cell array region of a DRAM with reference to FIGS. 25 and 26. &lsqb;0012&rsqb; First, a device isolation film 202 is formed on a silicon substrate 200 by, e.g., the usual LOCOS method. &lsqb;0013&rsqb; Then a gate insulation film 206 is formed in a device region 204 by, e.g., thermal oxidation. &lsqb;0014&rsqb; Subsequently gate electrodes 208 are formed on the gate insulation film 206. Insulation films of, e.g., doped polycrystalline silicon film and silicon oxide film are continuously deposited by CVD, and the laid films are processed in the same pattern, and the gate electrodes 208 having the top surfaces covered with an insulation film 210 are formed (FIG. 25A). &lsqb;0015&rsqb; Then, ions are implanted with the gate electrodes 208 as a mask to form in the device region an impurity-doped region 212 which is to be a low-concentration diffused layer of LDD structure. &lsqb;0016&rsqb; Next, an insulation film 214 of, e.g., silicon oxide film is deposited on the entire surface (FIG. 25B). &lsqb;0017&rsqb; Subsequently, the insulation film 214 is etched back by anisotropic etching to form sidewall insulation films 216 on the side walls of the gate electrodes 208. &lsqb;0018&rsqb; Subsequently, ions are implanted with the gate electrodes and the sidewall insulation films as a mask to form an impurity doped region 218 which is to be a high-concentration diffused layer of LDD structure (FIG. 25C). &lsqb;0019&rsqb; Then, the implanted impurity is activated by, e.g., a thermal treatment at 1000° C. for 10 seconds to form a source/drain diffused layers 220, 222 of LDD structure. &lsqb;0020&rsqb; Then, an etching stopper film 224 of, e.g., silicon nitride film is deposited. The etching stopper film 224 is to be a protection film for protecting the base from being etched off when contact holes are opened in an inter-layer insulation film to be deposited on the etching stopper film 224. &lsqb;0021&rsqb; Subsequently, an insulation film of, e.g., silicon oxide film is deposited and has the surface polished by, e.g., CMP (Chemical Mechanical Polishing) to form an interlayer insulation film 226 having the surface planarized (FIG. 26A). The inter-layer insulation film 226 is formed of a material providing an etching selectivity with respect to the etching stopper film 224. &lsqb;0022&rsqb; Subsequently, contact holes 228 opened on the source/drain diffused layers 220, 222 are formed. &lsqb;0023&rsqb; When the contact holes 228 are etched, the inter-layer insulation film 226 is etched under conditions for etching the silicon oxide film, which can provide a sufficient selective ratio with respect to silicon nitride film, whereby even when parts of the contact holes 228 are extended over the gate electrodes 208, the etching stopper film 224 is not substantially etched. &lsqb;0024&rsqb; Thus, the sidewall insulation films 216, and the insulation film 210 on the gate electrodes 208 are not excessively etched, and the contact holes can be stably opened. &lsqb;0025&rsqb; Then, the etching stopper film 224 is etched to expose the source/drain diffused layers 220, 222 in the contact holes 228 (FIG. 26C). &lsqb;0026&rsqb; In etching the etching stopper film 224 it is usual that anisotropic etching is not used, but wet etching in which the etching isotropically goes on is used. There are two reasons for this. One of the reasons is that the etching stopper film remaining as the sidewall insulation films narrow the contact regions, which increases contact resistance. The other of the reasons is to prevent the silicon substrate from being damaged by the anisotropic etching and having crystal defects. &lsqb;0027&rsqb; The contact holes 228 are thus opened, whereby regions where the contact holes 228 are formed can overlap the gate electrodes 208, so that even when a resist pattern is a little disaligned by disalignment in the lithography step, the contact holes 228 can be opened in alignment with the gate electrodes 208 or the device isolation film 202. &lsqb;0028&rsqb; As LSIs are higher integrated, new problems of the method for fabricating the above-described conventional semiconductor device have been made clear. &lsqb;0029&rsqb; To attain higher integration of a semiconductor device it is necessary to form a larger number of transistors in a smaller region. The gap between the gate electrodes 208 is made smaller. In DRAMs, for example, the pattern size is about 0.7 times every generation, and is diminished by about ½ in two generations. On the other hand, to sufficiently function the etching stopper film 224 in the method for fabricating the semiconductor device shown in FIGS. 25 and 26, substantially the same film thickness as in the conventional semiconductor device is required. &lsqb;0030&rsqb; When a semiconductor device is fabricated with these conditions satisfied, the contact region between the gate electrodes 208 is completely filled with the etching stopper film 224 (FIG. 27). &lsqb;0031&rsqb; Here, to form the contact hole 228 in the contact region between the gate electrodes 208 it is necessary to remove the etching stopper film 224 filled in the contact region, but it is very difficult to remove the etching stopper film 224 in the contact region. &lsqb;0032&rsqb; That is, to remove the etching stopper film buried in the contact region by the above-described wet etching, the etching stopper film has to be etched off by a film thickness corresponding to a height of the gate electrodes 208, but the etching stopper film below the inter-layer insulation film is also side-etched by substantially the same degree. Consequently, for example, the etching stopper film 224 on the gate electrodes 208 is completely etched, and a micronized pattern formed on the inter-layer insulation film 226 is often broken. &lsqb;0033&rsqb; In removing the etching stopper film 224 by anisotropic etching, because an etching selectivity usable in wet etching cannot be ensured, the etching is carried on after the etching stopper film 224 on the side walls 216 is removed, to remove the etching stopper film 224 between the gate electrodes 208, and the sidewall insulation films 216 decrease a film thickness to expose, in some cases, the gate electrodes 208 in the contact hole 228. When the gate electrodes 208 are exposed in the contact hole 228, the gate electrodes 208 short-circuit with the source/drain diffused layers 220, 222, and the transistors often do not normally operate. &lsqb;0034&rsqb; Also in completely etching off the etching stopper film of a height of the gate electrodes, to completely remove the etching stopper film it is necessary to a little over-etch in consideration of a disuniform film thickness of the inter-layer insulation film (a height of the gate electrodes), a disuniform etching amount, etc. This excessive etching amount is substantially proportional to a thickness of the insulation film. In a case that the etching stopper film is buried deep, the over-etching amount is accordingly increased. Accordingly in the conventional method the silicon substrate is unavoidably much damaged. SUMMARY OF THE INVENTION &lsqb;0035&rsqb; An object of the present invention is to provide a method for fabricating a semiconductor device relating to a contact hole opening technique and is suitable for further micronization of a semiconductor device. &lsqb;0036&rsqb; The above-described object is achieved by the semiconductor device comprising: a semiconductor substrate; a device region defined by a device isolation film formed on the semiconductor substrate; a fist interconnection formed on the device region; an insulation film covering an upper surface and side walls of the first interconnection; an inter-layer insulation film formed on the semiconductor substrate with the insulation film formed on, and having an opening formed in a region including the device region; and a second interconnection formed, extended on the interlayer insulation film and/or the insulation film, and connected to the device region in the opening. The semiconductor device of this structure facilitates forming micronized openings by loose rules for the lithography step. &lsqb;0037&rsqb; In the above-described semiconductor device it is preferable that a plurality of the first interconnection are extended on the device region, and the second interconnection is connected to the device region between the first interconnections. &lsqb;0038&rsqb; In the above-described semiconductor device it is preferable that the insulation film and the inter-layer insulation film have height substantially equal to each other, and the second interconnection is buried between the inter-layer insulation film and/or the insulation film. &lsqb;0039&rsqb; The above-described object is achieved by a method for fabricating a semiconductor device comprising: a first interconnection forming step of forming a first interconnection having an upper surface covered with a first insulation film on a base substrate; an insulation film depositing step of sequentially depositing a second insulation film and a third insulation film on the base substrate with the first interconnection formed on; an opening forming step of etching the third insulation film with the second insulation film as a stopper to form an opening in a first region containing a region where the first interconnection is formed; and a contact hole forming step of etching the second insulation film in the opening to form sidewall insulation films of the second insulation film on the side walls of the first interconnection and form by self-alignment with the first interconnection a contact hole to be connected to the base substrate. According to the method for fabricating a semiconductor device, the second insulation film to be the etching stopper film is also the insulation film for the sidewall insulation films, which prevents the contact region for the gate electrodes from being filled with the second insulation film even in a case that the gate electrodes are spaced by a narrow gap. &lsqb;0040&rsqb; According to the conventional method for fabricating a semiconductor device, two sidewall insulation films are formed between gate electrodes, and an etching stopper film is further formed on the side walls of the sidewall insulation films. To form an opening between gate electrodes, it is necessary to set an interval between the gate electrodes in consideration of their thickness, and an interval of at least a sidewall width×2&plus;an etching stopper film thickness×2&plus;&agr; (contact size) must be ensured. However, according to the above-described method of the present application a width of twice an etching stopper film thickness (or twice a sidewall thickness) can be decreased. That is, the interval between the gate electrodes can be reduced to a sidewall width x 2 (or an etching stopper film thickness×2)&plus;&agr;. Thus, the opening has an interior space allowance, which facilitates forming an opening of a narrow opening width. &lsqb;0041&rsqb; A film forming the sidewall insulation films is the etching stopper film, which can decrease film forming steps and etching steps. This results in a shorter process and lower costs. &lsqb;0042&rsqb; In the above-described method for fabricating a semiconductor device it is preferable that in the opening forming step, the opening bridges both regions on both side of the first interconnection, whereby it is not necessary to leave a micronized pattern on the gate electrodes, which enables rules for the lithography step to be loosened. The first opening formed over both sides of the first interconnection is divided into two or more smaller openings on the first interconnection. Thus smaller openings than drawing rules for forming an opening bridging regions both sides of the first interconnection can be formed without disalignment. &lsqb;0043&rsqb; In the above-described method for fabricating a semiconductor device, it is preferable that the method further comprises, after the insulation film depositing step, an insulation film removing step of retreating a surface of the third insulation film to expose a part of the second insulation film on the first interconnection, whereby an opening bridging regions on both sides of the first interconnection is divided by the first interconnection, and two or more openings can be formed. &lsqb;0044&rsqb; In the method for fabricating a semiconductor device, it is preferable that the method further comprises, after the contact hole forming step, a second interconnection forming step of forming a second interconnection buried in the opening and connected to the base substrate, whereby two or more interconnections connected to the base substrate through an opening and divided by the first interconnection can be formed. &lsqb;0045&rsqb; In the above-described method for fabricating a semiconductor device it is preferable that in the second interconnection forming step, the second interconnection which contains an impurity, which donates to electric conductivity of the base substrate, is formed and the impurity dopes into the base substrate by diffusion from the second interconnection, whereby a shallow diffused layer can be easily formed directly below the second interconnection. &lsqb;0046&rsqb; In the above-described method for fabricating a semiconductor device it is preferable that the method further comprises, prior to the first interconnection forming step, a device isolation film forming step of forming a device isolation film on the base substrate; and a device isolation film removing step of removing the device isolation film until a surface of a device region defined by the device isolation film has a height substantially equal to the device isolation film, whereby the second interconnection can be formed by self-alignment without being influenced by steps of the device isolation film. &lsqb;0047&rsqb; In the above-described method for fabricating a semiconductor device it is preferable that the method further comprises, prior to the first interconnection forming step, a device isolation film forming step of forming a device isolation film on the base substrate; a first conducting film depositing step of depositing a first conducting film on the base substrate with the device isolation film formed on; and a conducting film burying step of polishing a surface of the base substrate with the first conducting film formed on until the device isolation film is exposed to bury the first conducting film in the device region defined by the device isolation film and planarize a surface of the base substrate, and wherein in the first interconnection forming step, the first conducting film under the first interconnection is processed in the substantially same pattern as the first interconnection, whereby steps of the device isolation film can be buried with the first conducting film, which enable the second interconnection to be formed by self-alignment without being influenced by the steps of the device isolation film. &lsqb;0048&rsqb; In the method for fabricating a semiconductor device it is preferable that the method further comprises, prior to the first interconnection forming step, a device isolating step of forming a device isolation film on the base substrate, and wherein in the first interconnection forming step, the first interconnection is formed on the device region defined by the device isolation film and on the device isolation film; and in the insulation film removing step, the third insulation film is retreated until the second insulation film formed on the first interconnection on the device region is exposed, whereby the second interconnections can be formed by self-alignment without being influenced by steps of the device isolation film. That is, cavities formed by steps of the device isolation film do not interconnect the second interconnections, and the second interconnections divided by the first interconnections can be formed. &lsqb;0049&rsqb; The above-described object is achieved by a method for fabricating a semiconductor device comprising: a device isolation film forming step of forming a device isolation film on a semiconductor substrate to define a plurality of device regions extended in a first direction and arranged in a staggered layout; a word line forming step of forming a plurality of word lines having surfaces covered with a first insulation film and extended in a second direction intersecting the first direction, two of the word lines being extended in each of the device regions; an insulation film depositing step of depositing a second insulation film on the semiconductor substrate with the word lines formed on; a resist pattern forming step of forming a resist pattern for covering regions which are between the device regions extended in the first direction and are between the two word lines intersecting the respective device regions and the word lines which are adjacent to the two word lines on the outsides of the two word lines, on the second insulation film on one sides of the respective device regions; and an opening forming step of etching the second insulation film with the resist pattern as a mask to form first openings extended from the respective device regions between the two word lines intersecting the respective device regions to the other sides of the respective device region, and second opening opened on the respective device regions between the adjacent word lines intersecting the different device regions. According to the method for fabricating a semiconductor device, the lithography step for opening the contact holes for leading the bit lines and the contact holes for leading the storage electrodes can have loosened rules. &lsqb;0050&rsqb; In the above-described method for fabricating a semiconductor device it is preferable that the method further comprises a contact hole forming step of etching the first insulation film in the first openings and the second openings to form sidewall insulation films of the first insulation film on side walls of the word lines and contact holes connected to the semiconductor substrate by alignment with the word lines, whereby the openings for the contact holes for leading the bit lines from the semiconductor substrate, and the openings for the contact holes for leading the storage electrodes from the semiconductor substrate can be easily formed. &lsqb;0051&rsqb; The above-described object can be achieved by a method for fabricating a semiconductor device comprising: a device isolation film forming step of forming a device isolation film on a semiconductor substrate to define a plurality of device regions extended in a first direction and arranged in a staggered layout; a word line forming step of forming a plurality of word lines having surfaces covered with a first insulation film and extended in a second direction intersecting the first direction, two of the word lines being extended in each of the device regions; an insulation film depositing step of depositing a second insulation film and a third insulation film on the semiconductor substrate with the word lines formed on; a planarization step of planarizing the third insulation film; a resist pattern forming step of forming a resist pattern for covering regions which are between the device regions extended in the first direction and are between the two word lines intersecting the respective device regions and the word lines which are adjacent to the two word lines on the outsides of the two word lines, on the third insulation film and on one sides of the respective device regions; an opening forming step of etching the third insulation film with the resist pattern as a mask to form first openings extended from the respective device regions between the two word lines to the other sides of the respective device regions, and second openings opened on the device regions between the adjacent word lines intersecting the different device regions; and a contact hole forming step of etching the second insulation film in the first openings and the second openings to form sidewall insulation films of the second insulation film on side walls of the word lines and to form contact holes to be connected to the semiconductor substrate in alignment with the word lines. According to the method for fabricating a semiconductor device, the openings for the contact holes for leading the bit lines from the semiconductor substrate, and the openings for the contact holes for leading the storage electrodes from the semiconductor substrate can be easily formed. The lithography for opening the contact holes does not require transferring a micronized contact hole pattern, which can simplify the lithography. &lsqb;0052&rsqb; The above-described object is achieved by a method for fabricating a semiconductor device comprising: a word line forming step of forming a plurality of word lines extended in a first direction on a semiconductor substrate; a bit line forming step of forming a plurality of bit lines having upper surfaces covered with a first insulation film and extended in a second direction intersecting the first direction on the semiconductor substrate with the word lines formed on; an insulation film depositing step of depositing a second insulation film and a third insulation film on the semiconductor substrate with the bit lines formed on; a planarization step of planarizing a surface of the third insulation film; a resist pattern forming step of forming a striped resist pattern for alternately covering regions between the word lines on the planarized third insulation film; an opening forming step of etching the third insulation film with the resist pattern as a mask to open a plurality of openings in regions between the bit lines; and a contact hole forming step of etching the second insulation film in the openings to form side walls of the second insulation film on side walls of the bit lines and open contact holes to be connected to the semiconductor substrate in alignment with the bit lines. According to the method for fabricating a semiconductor device, the opening for the contact holes for leading the storage electrodes from the semiconductor substrate can be easily formed. The lithography for opening the contact holes does not require transferring a micronized contact hole pattern, which can simplify the lithography. Detailed Description: DETAILED DESCRIPTION OF THE INVENTION &lsqb;0080&rsqb; &lsqb;A First Embodiment&rsqb; &lsqb;0081&rsqb; The method for fabricating a semiconductor device according to first embodiment of the present invention will be explained with reference to FIGS. 1A-1C and 2A-2C. &lsqb;0082&rsqb; FIGS. 1A-1C and 2A-2C are sectional views of the semiconductor device at the steps of the method for fabricating a semiconductor device according to the present embodiment. &lsqb;0083&rsqb; First, an about 200 nm-thick device isolation film 12 is formed on a silicon substrate 10 by, e.g., the usual LOCOS method to define a device region 14. &lsqb;0084&rsqb; Then, an about 5 nm-thick gate insulation film 16 is formed by, e.g., thermal oxidation. &lsqb;0085&rsqb; Subsequently, gate electrodes 18 are formed on the gate insulation film 16. A doped polycrystalline silicon film of, e.g., an about 200 nm-thick and an insulation film of silicon oxide film are continuously deposited by CVD and processed in the same pattern by lithography and etching to form the gate electrodes 18 having the top surfaces of the gate electrodes 18 covered with an insulation film 20 (FIG. 1A). &lsqb;0086&rsqb; Then, with the gate electrodes 18 as a mask ions are implanted to form in a device region an impurity-doped region 22 which is to be a low-concentration diffused layer of LDD structure. Ions of a Group V element, e.g., As (arsenic) or others, and ions of a Group III element, e.g., B (boron) or others are implanted in 5×1013-1×1014 cm−2 respectively in a case of an n-type transistor and in a case of a p-type transistor. &lsqb;0087&rsqb; The impurity-doped region 22 is not essential in a case that a transistor structure, such as MOD (Minimum Overlapped source Drain) structure is applied. MOD structure is a method for ions are implanted with the sidewall insulation films formed on the side walls of the gate electrodes, and an impurity is thermally diffused down below the sidewall insulation films to thereby form a source/drain diffused layer. &lsqb;0088&rsqb; Next, an about 50-200 nm-thick silicon nitride film is deposited by, e.g., CVD to form an etching stopper film 24 (FIG. 1B). &lsqb;0089&rsqb; The etching stopper film 24 is used as a stopper for etching the inter-layer insulation film in a later step, and as sidewall insulation films to be formed on the side walls of the gate electrodes 18. The etching stopper film 24 is not essentially silicon nitride film as long as the etching stopper film 24 can do these functions and may be formed of another film. For example, SiO2 film, SiON film or alumina film may be used. &lsqb;0090&rsqb; Subsequently an insulation film to be the inter-layer insulation film is deposited on the entire surface. The insulation film may be an insulation film deposited by CVD or SOG (Spin On Glass). &lsqb;0091&rsqb; Subsequently, the surface of the insulation film is planarized to form the inter-layer insulation film 26 having the surface planarized (FIG. 1C). In a case that the insulation film is a film having a low melting point, such as BPSG film, the surface of the insulation film can be planarized by, e.g., a melting step. The surface of the insulation film may be planarized by CMP. &lsqb;0092&rsqb; Then, a photoresist 28 having openings in regions where the source/drain diffused layer are to be formed is formed by the usual lithography. &lsqb;0093&rsqb; Subsequently, anisotropic etching is conducted with the photoresist 28 as a mask to pattern the inter-layer insulation film 26 (FIG. 2A). Etching conditions which allow a large selective ratio between the inter-layer insulation film 26 and the etching stopper film 24 to enable the etching stopper film 24 to sufficiently function as the stopper are preferable. By using, e.g., RIE (Reactive Ion Etching) using C4F8, CO, Ar and O2 gas, the inter-layer insulation film 26 is patterned substantially without etching the etching stopper film 24. &lsqb;0094&rsqb; Then, the anisotropic etching is further conducted with the photoresist film 28 as a mask to pattern the etching stopper film 24 below the inter-layer insulation film 26. Because of the etching stopper film 24 deposited on the side walls of the gate electrodes 18 and the insulation film 20, even when the etching goes on until the silicon substrate 10 is exposed in the regions where the source/drain diffused layer are to be formed, the etching stopper film 24 on the side walls is not removed to remain as the sidewall insulation films 30. &lsqb;0095&rsqb; Concurrently therewith, contact holes 34, 36 are opened in alignment with the gate electrodes 18 on the regions where the source/drain diffused layer is formed. &lsqb;0096&rsqb; In the method for fabricating a semiconductor device according to the present embodiment, although anisotropic etching is used in etching the etching stopper film 24, a total number of RIE steps is not increased because the present embodiment does not include an another step of forming the sidewall insulation films as does the conventional method for fabricating a semiconductor device shown in FIG. 25, and the damages introduced into the silicon substrate by the RIEs are not increased. &lsqb;0097&rsqb; By using RIE in etching the etching stopper film 24, no side-etching occurs in the etching stopper film 24, and accordingly more micronized semiconductor devices can be easily fabricated. &lsqb;0098&rsqb; One insulation film functions as the insulation film and the stopper film (e.g., silicon nitride film) for forming the sidewall insulation films, whereby accordingly, the fabrication process can be simplified, and cost reduction can be achieved. &lsqb;0099&rsqb; Then, ions are implanted with the gate electrodes 18 and the sidewall insulation films 30 as a mask to form in the device region impurity-doped regions 32 which are to be high-concentration diffused layers of LDD structure. Ions of a Group V element, e.g., As (arsenic), P (phosphorus) or others, and ions of a Group III element, e.g., B (boron) or others are implanted in an about 4×105 cm−2 dose respectively in a case of a n-type-transistor and in a case of a p-type-transistor (FIG. 2B). &lsqb;0100&rsqb; Subsequently, the substrate is thermal-treated under required conditions to make the implanted impurity ions electrically active. The impurity can be activated by, e.g., a rapid thermal annealing at 10000 and 10 seconds. Thus the source/drain diffused layer 38, 40 are formed. &lsqb;0101&rsqb; Then, a conducting film is deposited on the entire surface and patterned to form electrodes 42, 44 connected to the source/drain diffused layer 38, 40. &lsqb;0102&rsqb; As described above, according to the present embodiment, the sidewall insulation films 30 are formed of the etching stopper film 24 used in opening the contact holes 34, 36, whereby even in a case that the gate electrodes 18 are arranged at a narrow gap, the contact region between the gate electrodes 18 is never filled with the etching stopper film 24, which facilitates opening the contact holes. &lsqb;0103&rsqb; In the present embodiment, the contact holes 34, 36 are formed on the device region but may be formed on the device isolation film 12. Otherwise the contact holes 34, 36 may be formed in portions which do not bridge the gate electrodes. It is preferable that the regions for the openings are to be formed in are suitably designed depending on a layout of a semiconductor device or a method for fabricating the same. &lsqb;0104&rsqb; &lsqb;A Second Embodiment&rsqb; &lsqb;0105&rsqb; A method for fabricating a semiconductor device according to a second embodiment of the present invention will be explained with reference to FIGS. 3A-3B and 4A-4D. The same members of the present embodiment as those of the method for fabricating a semiconductor device according to the first embodiment are represented by the same reference numbers not to repeat or to simplify their explanation. &lsqb;0106&rsqb; FIGS. 3A and 3B are views which explain the disadvantage of the method for fabricating a semiconductor device according to the first embodiment. FIGS. 4A-4D are sectional views of a semiconductor device at the steps of the method for fabricating the semiconductor device according to the present embodiment, which explain the method. &lsqb;0107&rsqb; In the method for fabricating a semiconductor device according to the fist embodiment, the contact hole 34 and the contact hole 36 are opened on the source/drain diffused layer 38, 40, leaving the inter-layer insulation film 26 on the gate electrodes 18. &lsqb;0108&rsqb; However, in a case that disalignment takes place in the lithography step of opening the contact holes 34, 36, and the patterned inter-layer insulation film 26 is extended over the regions to be the source/drain diffused layer 38, 40 (FIG. 3A), the low-concentration diffused region of LDD may be elongated with a result of higher parasitic resistance (FIG. 3B). &lsqb;0109&rsqb; Consequently, a margin for disalignment in the lithography step for opening the contact holes must be small, which makes the patterning for the contact holes difficult. &lsqb;0110&rsqb; On the other hand, to ensure a disalignment margin it is necessary to extend the contact holes 34, 36 sufficiently over the gate electrodes 18, but this makes a width of the inter-layer insulation film 26 remaining on the gate electrodes 18 extremely narrow, which makes the patterning of the contact holes 34, 36 difficult. &lsqb;0111&rsqb; Although the method for fabricating a semiconductor device according to the first embodiment is an effective fabrication method because of it simple process, it has the risk that the above-described disadvantage in the lithography step may become serious as devices are increasingly micronized. &lsqb;0112&rsqb; The method for fabricating a semiconductor device according to the present embodiment can simplify the lithography step. &lsqb;0113&rsqb; First, in the same way as the method for fabricating a semiconductor device according to the first embodiment exemplified in FIGS. 1A to 1C, gate electrodes 18, an etching stopper film 24 and an inter-layer insulation film 26 are formed (FIG. 4A). &lsqb;0114&rsqb; Then, a photoresist 28 having an opening extended over regions for a source/drain diffused layer 38, 40 to be formed in is formed by the usual lithography. In the semiconductor device shown in FIGS. 4A-4D, the opening is formed over a region substantially equal to a device region 14 defined by a device isolation film 12 (preferably over a region larger than at least the device region by an alignment margin in consideration of disalignment in the lithography). &lsqb;0115&rsqb; Subsequently, anisotropic etching is conducted with the photoresist 28 as a mask to pattern the inter-layer insulation film 26, whereby the inter-layer insulation film 28 does not remain on the gate electrodes 18 in the device region 14 (FIG. 4B). &lsqb;0116&rsqb; Then, the photoresist 28 is removed, and the anisotropic etching is further conducted to pattern the etching stopper film 24 below the inter-layer insulation film 26. Because of the etching stopper film 24 deposited on the side walls of the gate electrodes 18 and the insulation film 20, when the etching goes on until the silicon substrate 10 is exposed in the regions for the source/drain diffused layer to be formed in, the etching stopper film 24 on the side walls is not removed to remain the sidewall insulation films 30. &lsqb;0117&rsqb; Then, ions are implanted with the gate electrodes 18 and the sidewall insulation films 30 as a mask to form in a device region an impurity-doped region 32 which is to be a high-concentration diffused layer of LDD structure. Ions of a Group V element, e.g., As (arsenic), P (phosphorus) or others and ions of a Group III element, e.g., B (boron) or others are implanted in an about 4×1015 cm−2 respectively in a case of a n-type-transistor and in a case of a p-type-transistor (FIG. 4C). &lsqb;0118&rsqb; Subsequently, the substrate is thermal-treated under prescribed conditions to make the implanted impurity ions electrically active. The impurity can be activated by rapid thermal annealing at, e.g., 1000° C. for 10 seconds. Thus the source/drain diffused layer 38, 40 is formed in the device region. &lsqb;0119&rsqb; Then, a conducting film is deposited on the entire surface and patterned to form electrodes 42, 44 connected to the source/drain diffused layer 38, 40 (FIG. 4D). &lsqb;0120&rsqb; As described above, according to the present embodiment, a contact hole extended over regions to be the source/drain diffused layer 38, 40 is formed, which allows rules of the lithography step for opening the contact hole to be less strict. &lsqb;0121&rsqb; &lsqb;A Third Embodiment&rsqb; &lsqb;0122&rsqb; The method for fabricating a semiconductor device according to a third embodiment of the present invention will be explained with reference to FIGS. 5A-5C and 6A-6B. The same members of the present embodiment as those of the method for fabricating a semiconductor device according to the first or the second embodiment are represented by the same reference numbers not to repeat or to simplify their explanation. &lsqb;0123&rsqb; FIGS. 5A-5C and 6A-6B are sectional views of a semiconductor device in the steps of the method for fabricating a semiconductor device according to the present embodiment. &lsqb;0124&rsqb; In the method for fabricating a semiconductor device according to the first or the second embodiment, the electrodes 42, 44 connected to the source/drain diffused layer 38, 40 are formed by pattering the conducting film deposited on the entire surface of the substrate. &lsqb;0125&rsqb; In the method for fabricating a semiconductor device according to the above-described embodiment, however, because of a height difference between the surface of an inter-layer insulation film 26 and an insulation film 20, for higher resolution, a depth of focus becomes smaller, and a resolution becomes lower for a larger depth of focus. As a result, it is difficult to realize micronized lithography both in the surface of the inter-layer insulation film 20 and the surface of the insulation film 20. &lsqb;0126&rsqb; The method for fabricating a semiconductor device according to the present embodiment facilitates patterning the electrodes 42, 44. &lsqb;0127&rsqb; First, in the same way as in the method for fabricating a semiconductor device according to the first embodiment exemplified in FIGS. 1A and 1B, gate electrodes 18 and an etching stopper film 24 are formed (FIG. 5A). &lsqb;0128&rsqb; Next, an insulation film to be an inter-layer insulation film is deposited on the entire surface, and the surface is planarized by, e.g., CMP. At this time, the insulation film is polished with the etching stopper film 22 extended on the gate electrodes as a stopper to expose the etching stopper film 24 extended on the gate electrodes 18 on the surface. Thus the inter-layer insulation film 26 having the surface planarized is formed (FIG. 5B). In this step it suffices that the upper end of the etching stopper film 24 is exposed. Accordingly another planarization technique, such as etching back or others, may be used to cause the insulation film to retreat. &lsqb;0129&rsqb; Subsequently, a photoresist 28 having an opening spanning regions to be a source/drain diffused layer 38 and regions to be a source/drain diffused layer 40 is formed by the usual lithography. &lsqb;0130&rsqb; Then, anisotropic etching is conducted with the photoresist 28 as a mask to pattern the inter-layer insulation film 26. Thus the inter-layer insulation film 26 does not remain on the gate electrodes 18 in the device region 14 (FIG. 5C). &lsqb;0131&rsqb; Next, the photoresist 28 is removed, and the anisotropic etching is further conducted. This anisotropic etching is conducted preferably under conditions which permit the inter-layer insulation film 26 and the etching stopper film 24 to be etched at substantially the same etching rate. For example, RIE using C4F8, Ar and O2 gas permits etching rates of the etching stopper film 24 and the inter-layer insulation film 26 to be substantially equal to each other. &lsqb;0132&rsqb; By this etching, sidewall insulation films 30 of the etching stopper film 24 are formed on the side walls of the gate electrodes 18 and the insulation film 20. On the other hand, the inter-layer insulation film 26 is etched by a film thickness substantially equal to a film thickness of the etching stopper film 24, and the inter-layer insulation film 26 has a height substantially equal to a height of the insulation film 20 exposed on the surface. Thus, contact holes 34, 36 can be opened with the surface maintained plane. &lsqb;0133&rsqb; Subsequently, ions are implanted with the gate electrodes 18 and the sidewall insulation films 30 as a mask to form impurity-doped regions 32 to be high-concentration diffused layer of LDD structure in the device region. Ions of a Group V element, e.g., As (arsenic) or others, and ions of a Group III element, e.g., B (boron) are implanted in a 4×105 cm−2 dose respectively in a case of an n-type transistor and in a case of a p-type transistor (FIG. 6A). &lsqb;0134&rsqb; Then, the substrate is thermal-treated under prescribed conditions to make the implanted impurity ions electrically active. The impurity ions can be activated by rapid thermal annealing, e.g., at 1000° C. for 10 seconds. Thus, the source/drain diffused layer 38, 40 is formed in the device region. &lsqb;0135&rsqb; Next, a conducting film is deposited on the entire surface and patterned to form electrodes 42, 44 connected to the source/drain diffused layer 38, 40 (FIG. 6B). In this patterning, the surface of the inter-layer insulation film 26 and that of the insulation film 20 are on substantially the same level, and accordingly can be finely patterned without the problem of the depth of focus. &lsqb;0136&rsqb; As described above, according to the present embodiment, the inter-layer insulation film 26 is planarized with the etching stopper film 24 to be the sidewall insulation films 30 as a stopper, and the contact holes are opened with the surface maintained plane, which permits the electrodes 42, 44 to be finely patterned. &lsqb;0137&rsqb; &lsqb;A Fourth Embodiment&rsqb; &lsqb;0138&rsqb; The method for fabricating a semiconductor device according to a fourth embodiment of the present invention will be explained with reference to FIGS. 7A and 7B. The same members of the embodiment as the method for fabricating a semiconductor device according to the first to the third embodiments are represented by the same reference numbers not to repeat or to simplify their explanation. &lsqb;0139&rsqb; FIGS. 7A and 7B are sectional views of a semiconductor device in the steps of the method for fabricating a semiconductor device according to the present embodiment, which explain the method. &lsqb;0140&rsqb; In the method for fabricating a semiconductor device according to the third embodiment, the electrodes 42, 44 are formed on the planarized surface of the substrate to thereby enable the electrodes 42, 44 to be finely patterned. As a device is further micronized, the device has a smaller gate length and a smaller gate gap, which makes a patterning to isolate the electrodes 42, 44 on the gate electrodes 18 difficult. &lsqb;0141&rsqb; The method for fabricating a semiconductor device according to the present embodiment permits the electrodes 42, 44 to be patterned free from restriction by lithographical processing precision. &lsqb;0142&rsqb; First, in the same way as in the method for fabricating a semiconductor device shown in FIGS. 5A to 6A, an inter-layer insulation film 26 with contact holes 34, 36 opened in regions where a source/drain diffused layer 38, 40 is to be formed is formed. The inter-layer insulation film 26 has a height substantially equal to a height of an insulation film 20 exposed on the surface (FIG. 7A). &lsqb;0143&rsqb; Then, a conducting film to be electrodes is deposited on the entire surface. An electrode material can be a various material, e.g., aluminium, titanium (Ti), titanium nitride (TiN), gold (Au), metal silicide or others, or films of their compounds. An electrode material may be a material, e.g., polycrystalline silicon film, which is not conductive at the time of deposition but can be made conductive by later ion implantation or thermal treatment. &lsqb;0144&rsqb; Subsequently, the conducting film is left only in the contact holes by CMP or back-etching (FIG. 7B). At the time it should be noted that the inter-layer insulation film 26 and the insulation film 20 have substantially the same height, and the region except the contact holes is substantially plane. &lsqb;0145&rsqb; This is because in burying the conducting film by CMP, unless the surface is plane, the electrode material remain in cavities except the contact regions with a resultant risk that the electrodes, which should be insulated from each other, may be short-circuited, and in burying the conducting film the back-etching, the conducting film remains as sidewalls on steps with a resultant risk of the above-described short-circuit. &lsqb;0146&rsqb; Thus, a height of the inter-layer insulation film 26 and that of the insulation film 20 are made substantially the same, and the region except the contact holes is substantially made plane, whereby the electrodes 42, 44 connected to the source/drain diffused layer 38, 40 can be formed by self-alignment. &lsqb;0147&rsqb; As described above, according to the present embodiment, the inter-layer insulation film 26 is planarized with the etching stopper film 24 to be sidewall insulation films 30 as a stopper, and the contact holes are opened with the surface maintained plane, which permits the electrodes 42, 44 connected to the source/drain diffused layer 38, 40 to be formed by self-alignment. &lsqb;0148&rsqb; In the above-described embodiments, the source/drain diffused layer 38, 40 is formed by ion implantation using the gate electrodes 18 and the sidewall insulation films 30 as a mask, but can be also formed by suitably selecting the conducting film of the electrodes 42, 44 to obtain thermal diffusion from the electrodes 42, 44 for forming the source/drain diffused layer 38, 40. &lsqb;0149&rsqb; The electrodes 42, 44 are formed of the conducting film of a material having a large dopant impurity diffusion coefficient, e.g., a polycrystalline silicon, an amorphous silicon, a metal silicide, such as WSi, TiSi, CoSi or others and doped, and then are subjected to a suitable thermal-treatment to diffuse the dopant impurity from the electrodes 42, 44 into the silicon substrate to thereby form the source/drain diffused layer 38, 40. The impurity in the conducting film may be introduced at the time of forming the conducting film. &lsqb;0150&rsqb; Thus forming the source/drain diffused layer 38, 40 by the thermal diffusion is suitable in comparison with the ion implantation in which an impurity is introduced into a substrate deep by an average projected range, to form a shallow diffused layer. &lsqb;0151&rsqb; It is a very important technique to form shallow diffused layers in micronized MOS transistors, etc., but actually the technique cannot be easily realized. However, by the use of the method for fabricating a semiconductor device, the electrodes 42, 44 can be formed by self-alignment, and concurrently therewith a shallow diffused layer can be formed, whereby the method for fabricating a semiconductor device can have a simple process and can fabricate a semiconductor device having improved characteristics. &lsqb;0152&rsqb; In forming the source/drain diffused layer by the above-described technique, it is essential to form the openings for the source/drain diffused layer by self-alignment with the gate electrodes. This is because when a distance between the openings in the source/drain diffused layer, and the ends of the gate electrodes varies, a channel region and the source/drain diffused layer are not perfectly connected with each other, with a resultant risk that the resistance between the source and the drain may become higher, or the source and the drain may be disconnected from each other. &lsqb;0153&rsqb; By the self-aligned contact hole forming technique of the present invention, the openings in the source/drain diffused layer can be formed by self-alignment with the gate electrodes, and thus the technique is very effective in forming shallow junction. &lsqb;0154&rsqb; In forming the source/drain diffused layer of LDD structure by the above-described technique, a low-concentration diffused layer is formed before forming the etching stopper film 24, and the high-concentration diffused layer is formed by diffusion from the electrodes 42, 44. It is also possible that an MOD transistor is formed, and the source/drain diffused layer is formed only by thermal diffusion from the electrodes 42, 44. &lsqb;0155&rsqb; In a case that the electrodes 42, 44 are formed of polycrystalline silicon film or others which is made conductive by introduction of an impurity it is necessary that separately from the introduction of an impurity into the source/drain diffused layer, an impurity is introduced also into the electrodes 42, 44 to make the polycrystalline silicon film conductive. Especially, in a case that a CMOS circuit is formed, because the source/drain diffused layer of the p-type transistor is p-type, and the source/drain diffused
{'app_number': '10638345', 'application_number': None, 'doc_number': '20040026787', 'publication_number': None, 'source_file': './application/2004/pa040212.xml', 'source_data': 'USPTO-Application'}