Title of Invention: PATTERN SYNTHESIS APPARATUS AND SEMICONDUCTOR TEST SYSTEM HAVING THE SAME Abstract: A semiconductor test system includes a user device configured to operate a reference device in accordance with an interface signal based on a timing signal having a variable operating frequency, a pattern synthesis apparatus configured to measure an interval between adjacent edges of the timing signal transmitted from the user device, and extract a logic value of the interface signal in accordance with the timing signal so as to generate test pattern data, and a test device configured to receive the test pattern data, reconstruct the timing signal based on the measured interval, generate a test driving signal such that the logic value is extracted from a device under test (DUT) based on the reconstructed timing signal, and apply the test driving signal to the DUT so as to determine an operating state of the DUT. Detailed Description: CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2011-0061483, filed on Jun. 24, 2011 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. BACKGROUND 1. Field Example embodiments of the inventive concepts relate to a pattern synthesis apparatus which determines pass or fail of a semiconductor device, and to a semiconductor test system having the same. 2. Description of the Related Art Wafers are formed into complete devices through procedures including a fabrication (FAB) process and a subsequent post-process. The thus-formed devices are categorized into non-defective units and defective units by electrical, thermal and functional tests conducted during or after a packaging process. However, a memory module or device which is commercially available after having been determined to be a non-defective unit may not operate properly when mounted in a personal computer (PC) or a user device including for example a customer end (CE) device. A semiconductor device to be tested is referred to as a device under test (DUT), and automatic test equipment (ATE), mounting-type test equipment, and fixed frequency mounting-type test equipment are used in testing the DUT. The ATE tests the DUT using a test pattern based on a semiconductor integrated circuit (IC) defect model obtained through experimentation. The ATE, which may exhibit superior performance in detecting logical failures and parametric failures, however, may be unreliable in terms of accuracy and ease of detection when detecting failures in an actual operation environment. For example, the ATE may have limits in detecting failure patterns in a user device. The mounting-type test equipment may test the DUT under simulated test conditions of an actual operation environment. In the case of a PC, the mounting-type test equipment may perform a test after fitting the DUT into a socket on a motherboard, thus performing the test in a relatively easy manner. However, when the DUT is welded to a printed circuit board (PCB), a socket may be required to be coupled to the DUT, which may cause distortion in an actual operation environment. Moreover, test patterns applicable to the DUT may be restricted, and the range of the test condition simulation may thus be limited. The fixed frequency mounting-type test equipment may capture signals input to/output from a semiconductor device in a user device, which operates at a fixed frequency, receives data based on the captured signals, and tests the DUT based on the data. The fixed frequency mounting-type test equipment may provide advantages of both the ATE and the mounting-type test equipment. However, electronic products with semiconductor devices which are actively variable in operating frequency are increasingly used recently, for example, to satisfy user demand for low power consumption and elongated life of electronic products. It may be desirable to have a semiconductor test system capable of testing pass or fail of semiconductor devices based on frequency variation. SUMMARY Example embodiments of the inventive concepts may provide a semiconductor test system including a pattern synthesis apparatus to measure an interval of a timing signal having a variable operating frequency using an interface signal of a user device mounted with a DUT which operates in accordance with the timing signal, and extract a logic value of the interface signal based on the measured interval to generate test pattern data, and a test device to reconstruct the timing signal and a driving signal based on the test pattern data, and apply the reconstructed timing signal and driving signal to the DUT. Example embodiments of the inventive concepts may provide a pattern synthesis apparatus to measure an interval of a timing signal having a variable operating frequency using an interface signal of a user device which operates a semiconductor device in synchronization with the timing signal, and extract a logic value of the interface signal to generate test pattern data. Additional aspects of example embodiments of the inventive concepts will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice. In accordance example embodiments of the inventive concepts, a semiconductor test system may include a user device to operate a device under test (DUT) in accordance with an interface signal synchronized with a timing signal having a variable operating frequency, a pattern synthesis apparatus to measure an interval between adjacent ones of edges of the timing signal transmitted from the user device, and extract a logic value of the interface signal in accordance with the timing signal so as to generate test pattern data, and a test device to receive the test pattern data, reconstruct the timing signal based on the measured interval, generate a test driving signal such that the logic value is extracted in synchronization with the reconstructed timing signal, and apply the test driving signal to the DUT so as to determine an operating state of the DUT. The pattern synthesis apparatus may include a time interval measurer to measure the interval between the adjacent edges of the timing signal, and count a sequence number of the measured interval to generate timing data, and a logic value capturer to generate a strobe signal based on the timing signal, and extract the logic value of the interface signal in accordance with the strobe signal. The time interval measurer may determine, based on the measured interval, whether a timing event has occurred, and stores the timing data, the timing data including an interval and an interval sequence number corresponding to an occurrence of the timing event. The timing event may include any one of a frequency change or duty ratio change, wherein the time interval measurer calculates a present period or a present duty ratio based on the interval, and determines the timing event to have occurred if a difference between the present period or present duty ratio and a reference value exceeds a predetermined threshold value. The reference values may be a reference period or reference duty ratio calculated through an interval of most recently stored timing data, or a reference period or reference duty ratio calculated through an average of intervals measured from a most recent time where the timing data is stored to a present time. The pattern synthesis apparatus may further include a control signal generator to generate an operating signal based on the logic value of the interface signal, the operating signal including information on whether an operating command is a read command or a write command, and generate an input/output enable signal based on the operating signal, the input/output enable signal including information on effective input/output timing between the test device and the DUT. The timing signal may include a clock signal and a data strobe signal, the data strobe signal being generated for a predetermined period according to the write command or the read command, and the interface signal includes a data signal, a command signal and an address signal. The logic value capturer may include a strobe generator to generate the strobe signal based on the timing signal, the strobe signal including information regarding effective timing to capture the logic value of the interface signal, a command/address signal capturer to extract logic values of the command signal and the address signal using the generated strobe signal, and a data signal capturer to extract a logic value of the data signal using the generated strobe signal. The strobe generator may detect the edges of the timing signal, and generates the strobe signal at each of the detected edges, the strobe signal being delayed by a predetermined time in accordance with a predetermined format. The strobe generator may detect edges of the clock signal and generates a clock strobe signal at each of the detected edges, detects edges of the data strobe signal and generates at least one write strobe signal at each of the detected edges, and generates at least one read strobe signal at a position delayed by a predetermined period from the generated write strobe signal. The command/address signal capturer may extract the logic values of the command signal and address signal corresponding to a position of the clock strobe signal based on the clock strobe signal. The data signal capturer may extract the logic value of the data signal based on at least one of the clock strobe signal, the write strobe signal and the read strobe signal in accordance with the predetermined format, and selects the extracted logic value based on the operating signal. The data signal capturer may extract the logic value of the data signal corresponding to a position of each of the clock strobe signal, the write strobe signal and the read strobe signal based on the clock strobe signal, the write strobe signal and the read strobe signal, and selects the logic value based on the operating signal, the logic value being extracted based on at least one of the clock strobe signal, the write strobe signal and the read strobe signal. The test device may include one or more test boards interconnected in a ring topology. Each of the test boards may include a timing generator to generate the timing signal using timing data, the timing data including the interval between the adjacent edges and a sequence number of the interval. The timing generator may generate the timing signal in any one of a first mode and a second mode, wherein the timing generator generates the timing signal in accordance with a timing set table in the first mode, the table including, by indices, information on a period of the timing signal and positions of edges in the period, wherein the timing generator generates the timing signal based on the timing data in the second mode, the edges of the timing signal being adjusted in position in accordance with a predetermined format. The timing generator in the first mode may set an index value based on a type of the timing signal to be generated and the timing data, and generates the timing signal based on data of the timing set table corresponding to the index value. The timing generator in the second mode may generate a clock signal based on the timing data, the clock signal being the timing signal, and, when the timing signal is not the clock signal, generates the timing signal based on the timing data and control data, the control data including information regarding positions of edges in a predetermined period of the timing signal to be generated. The timing generator in the second mode may include a timing set generator to generate a timing set using the timing data and the control data, the timing set including the information on the period of the timing signal and the edge positions in the period, and a timing waveform generator to generate the edges of the timing signal based on the generated timing set so as to generate the timing signal. Each of the test boards may further include a waveform generator to output a waveform of a driving signal based on waveform configuration information in synchronization with the timing signal, the waveform configuration information including information on a position where the logic value is extracted and information on a position of a transition between high and low levels. The driving signal may include wherein the driving signal includes a command signal, an address signal and a data signal, wherein the waveform generator generates the waveform such that logic values of the command signal and address signal are extracted at rising and falling edges of a clock signal to enable the command signal and the address signal to be synchronized with the clock signal, the clock signal being the timing signal, and the transition is made at a center of the clock signal. The waveform generator may generate the waveform such that a logic value of the data signal is extracted at each of the rising and falling edges of the clock signal or a rising edge or a falling edge of a data strobe signal and the transition is made at a center of the clock signal or data strobe signal. The waveform generator may generate the waveform generator generates the waveform such that the data signal is synchronized with the data strobe signal in a duration in which a write command is generated, and is synchronized with the clock signal in other durations. Each of the test boards may further include a pattern distributor to distribute the test pattern data to components of the test board, wherein the pattern distributor operates in any one of a first mode and a second mode, wherein the pattern distributor distributes the test pattern data directly to the respective components of the test board in the first mode, wherein, in the second mode, the pattern distributor filters only effective data among the test pattern data, the effective data including a predetermined command signal and data associated with the command signal, rearranges the effective data in accordance with an order format of the predetermined command signal, and distributes the rearranged data to respective components of the test board. The semiconductor test system may further include a pin electronics unit to output a test driving signal to the DUT only when a DRE signal is activated, the test driving signal being converted from the driving signal transmitted from the waveform generator to have a voltage level recognizable by the DUT, the DRE signal including information regarding effective timing to output the test driving signal; and a pattern comparator to extract a logic value of a DUT response signal output from the DUT, compare the logic value and predetermined expected data, and determine the operating state of the DUT in accordance with the result of the comparison, the comparison between the logic value and the expected data being performed only when a CPE signal is activated, the CPE signal including information on effective timing for comparison. The semiconductor test system may further include a storage server to store the test pattern data generated by the pattern synthesis apparatus in real time, wherein the test device receives at least one test pattern data from the storage server in real time. In accordance with example embodiments of the inventive concepts, a pattern synthesis apparatus may generate test pattern data using an interface signal in a user device, the user device operating a DUT in synchronization with a timing signal having a variable operating frequency. The pattern synthesis apparatus may include a time interval measurer to measure an interval between adjacent edges of the timing signal, and count a sequence number of the measured interval to generate timing data, and a logic value capturer to generate a strobe signal based on the timing signal, and extract a logic value of the interface signal in accordance with the strobe signal. The time interval measurer may determine, based on the measured interval, whether a timing event has occurred, and stores the timing data, the timing data including an interval and an interval sequence number corresponding to an occurrence of the timing event. The time interval measurer may include an edge detector to detect rising and falling edges of a clock signal, a timing data generator to measure an interval between the detected rising and falling edges, and counts a sequence number of the interval so as to generate timing data, a timing event checker to determine, based on the interval, whether the timing event has occurred, the timing event changing the frequency or a duty ratio, and a filter to filter the timing data if the timing event has not occurred. The timing event checker may calculate a present period or a present duty ratio based on the interval, and determines the timing event to have occurred if a difference between the present period or present duty ratio and a reference value exceeds a predetermined threshold value. The reference values may be a reference period or reference duty ratio calculated through an interval of most recently stored timing data, or a reference period or reference duty ratio calculated through an average of intervals, the intervals being measured from a most recent time when the timing data is stored to a present time. The timing event checker may store the average of intervals as timing data. The pattern synthesis apparatus may further include a control signal generator to generate an operating signal based on the logic value of the interface signal, the operating signal including information on whether an operating command is a read command or a write command, and generate an input/output enable signal based on the operating signal, the input/output enable signal including information on effective input/output timing between the test device and the DUT. The timing signal may include a clock signal and a data strobe signal, the data strobe signal being generated for a predetermined period according to the write command or the read command, and the interface signal includes a data signal, a command signal and an address signal. The logic value capturer may include a strobe generator to generate the strobe signal based on the timing signal, the strobe signal including information regarding effective timing to capture the logic value of the interface signal, a command/address signal capturer to extract logic values of the command signal and the address signal using the generated strobe signal, and a data signal capturer to extract a logic value of the data signal using the generated strobe signal. The strobe generator may detect the edges of the timing signal, and generate the strobe signal at each of the detected edges, the strobe signal being delayed by a predetermined time in accordance with a predetermined format. The strobe generator may detect edges of the clock signal and generate a clock strobe signal at each of the detected edges, detect edges of the data strobe signal and generate at least one write strobe signal at each of the detected edges, and generate at least one read strobe signal at a position delayed by a predetermined period from the generated write strobe signal. The strobe generator may check an interval of the clock signal to which generation time point of the write strobe signal belongs, and generate the read strobe signal at a position delayed by a half of the interval from the generation time point of the write strobe signal. The command/address signal capturer may extract extracts the logic values of the command signal and address signal corresponding to a position of the clock strobe signal based on the clock strobe signal. The data signal capturer may extract the logic value of the data signal based on at least one of the clock strobe signal, the write strobe signal and the read strobe signal in accordance with the predetermined format, and selects the extracted logic value based on the operating signal. The data signal capturer may extract the logic value of the data signal corresponding to a position of each of the clock strobe signal, the write strobe signal and the read strobe signal based on the clock strobe signal, the write strobe signal and the read strobe signal, and selects the logic value based on the operating signal, the logic value being extracted based on at least one of the clock strobe signal, the write strobe signal and the read strobe signal. The data signal capturer may select the logic value extracted based on the read strobe signal when the operating signal of the read command is generated, selects the logic value extracted based on the write strobe signal when the operating signal of the write command is generated, and selects the logic value extracted based on the clock strobe signal when the operating signal is not generated. The logic value extracted based on the read strobe signal may be stored as expected data, the expected data being a reference value for determining an operating state of the DUT. The input/output enable signal may include a DRE signal and a CPE signal, the DRE signal including information regarding effective timing to output a test driving signal from the test device to the DUT, the CPE signal including information regarding effective timing to compare a logic value of a DUT response signal and expected data, the DUT response signal a result of the test driving signal applied to the DUT. The pattern synthesis apparatus may be connected to an event generator, the event generator generating and transmitting a pulse signal when a predetermined event is performed by the user device. The pattern synthesis apparatus may further include an event checker to generate event information data when the pulse signal is transmitted, the event information data including a generation time point of the pulse signal and a type of the event. A semiconductor test system according to example embodiments of the inventive concepts may include a pattern synthesis apparatus configured to receive an interface signal from a reference semiconductor device, generate timing data by measuring intervals of a timing signal associated with the reference device, extract logic values from the interface signal, and generate test pattern data based on the extracted logic values; and a test device configured to receive the test pattern data and the timing data, reconstruct the timing signal based on the timing data, generate a test driving signal based on the test pattern data and the reconstructed timing signal, apply the test driving signal to a device under test (DUT) to generate test output data, and to determine an operating state of the DUT based on the test output data and the extracted logic values. The semiconductor system may further include a user device including a board, and the reference semiconductor device, the reference semiconductor device being mounted on the board, the interface signal being a signal sent between the board and the reference semiconductor device. The extracted logic values may include commands sent to the reference semiconductor device from the board, and data output from the reference semiconductor device, and the pattern synthesis device may be configured to store the data output from the reference semiconductor device as expected data. The test device may be configured such that determining the operating state of the DUT includes generating a comparison result based on the test output data and the expected data, and determining the operating state of the DUT based on the comparison result. BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of example embodiments will become more apparent by describing in detail example embodiments with reference to the attached drawings. The accompanying drawings are intended to depict example embodiments and should not be interpreted to limit the intended scope of the claims. The accompanying drawings are not to be considered as drawn to scale unless explicitly noted. FIG. 1 is a block diagram schematically showing a configuration of a semiconductor test system according to example embodiments of the inventive concepts; FIG. 2 is a block diagram showing a configuration of a pattern capture system in detail; FIG. 3 is a diagram illustrating a connection structure between a probe and a semiconductor device in a user device; FIG. 4 is a block diagram showing a configuration of a time interval measurer shown in FIG. 2 in detail; FIG. 5 is a timing diagram illustrating an example of timing data generated by the time interval measurer shown in FIG. 2; FIG. 6 is a block diagram showing configurations of a logic value capturer and a control signal generator in FIG. 2 in detail; FIG. 7 is a timing diagram illustrating an example of signal processing in the logic value capturer and control signal generator shown in FIG. 6; FIG. 8 is a block diagram schematically showing a configuration of a test system; FIG. 9 is a block diagram showing a configuration of a test board in detail; FIG. 10 is a block diagram showing a configuration of a pattern distributor in FIG. 9 based on operation modes thereof; FIG. 11 is a block diagram showing a configuration of a timing generator in FIG. 9 based on operation modes thereof; FIG. 12 is a timing diagram illustrating an example of a timing signal generated by the timing generator; FIG. 13 is a timing diagram illustrating an example of a driving signal generated by a waveform generator shown in FIG. 9; FIG. 14 is a timing diagram illustrating an example of a device under test (DUT) response signal output from the DUT when a test driving signal based on the driving signal generated in FIG. 13 is applied to the DUT; FIG. 15 is a flowchart schematically illustrating a semiconductor test method according to example embodiments of the inventive concepts; FIG. 16 is a flowchart illustrating a test pattern data generation process shown in FIG. 15; FIG. 17 is a flowchart illustrating a timing data generation process shown in FIG. 16 in detail; FIG. 18 is a flowchart illustrating a logic value capture process shown in FIG. 16 in detail; and FIG. 19 is a flowchart illustrating a semiconductor test process shown in FIG. 15 in detail. DETAILED DESCRIPTION Detailed example embodiments are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Example embodiments may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein. Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but to the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of example embodiments. Like numbers refer to like elements throughout the description of the figures. It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.). The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved. FIG. 1 is a block diagram schematically showing a configuration of a semiconductor test system according to example embodiments of the inventive concepts. Referring to FIG. 1, the semiconductor test system according to the present embodiment may include a pattern capture system 1000, a storage server 2000, a test system 3000 and a data communication link 4000. The pattern capture system 1000 may capture a signal for test logic from a user device, and synthesizes a test pattern using the captured signal. For example, in the pattern capture system 1000, a pattern synthesis apparatus may be connected with the user device. The user device may have a reference semiconductor device mounted therein, which is of the same type as (or is compatible) with a device under test (DUT) to be tested, to capture all signals of the semiconductor device. The storage server 2000 may store test pattern data transmitted from the pattern capture system 1000. In addition, the storage server 2000 may transmit data required by the test system 3000 during a DUT test. For example, the storage server 2000 may store various test pattern data captured by the pattern capture system 1000 in real time, and, as needed, search the stored data for appropriate information and transmit the information to the test system 3000 in real time. In addition to storing the test pattern data, the storage server 2000 may check and correct an error in the test pattern data. In addition, the storage server 2000 may be used for simple data backup or as a database. The storage server 2000 may include a plurality of storage servers depending on the transmission bandwidth and capacity of the test pattern data. The storage server 2000 may include an optical transceiver to input/output data through the data communication link 4000 so as to, for example, communicate with an external device, a bus adaptor for bus compatibility between the optical transceiver and the storage server 2000, and an internal central processing unit (CPU), a memory and a redundant array of independent disks (RAID) for data buffering and transfer. The storage server 2000 may be connected with an external controller such that the storage server 2000 and the external controller communicate with each other through a local area network (LAN) or the like. The controller may set operation parameters of the storage server 2000 and control and monitor the overall operation thereof. In the test system 3000, a test device may be connected with the DUT to apply a test signal to the DUT and determine pass or fail of the DUT based on an output waveform of the DUT in response to the test signal. The test system 3000 may receive test pattern data from the storage server 2000 in real time, generate a signal waveform to test the DUT based on the received test pattern data, and apply the signal waveform to the DUT. The test device may restore the test pattern data, apply the restored data to the DUT, detect a logic value of a DUT response signal output from the DUT, and determine the operating state of the DUT based on the detected logic value. For example, the test device may compare expected data restored from the test pattern data and the logic value extracted from the signal output from the DUT, and determine whether the operation of the DUT is normal or abnormal in accordance with a comparison result. For example, the DUT may be determined to pass if the logic value is identical to the expected data, and fail if the logic value is different from the expected data. The data communication link 4000 may perform data transmission/reception among the pattern capture system 1000, the test system 3000 and the storage server 2000. The data communication link 4000 may be composed of a plurality of high-speed optical cables to ensure high or higher transmission bandwidth, and may further include a switch. In this case, the switch of the data communications link 4000 may interconnect the pattern capture system 1000 and the test system 3000 via the storage server 2000. For example, the pattern capture system 1000 and the storage server 2000 may be interconnected via the data communication link 4000. Further, the test system 3000 and the storage server 2000 may be interconnected via the data communication link 4000. Thus, according to example embodiments of the inventive concepts, the test pattern data transmitted from the pattern capture system 1000 may be stored in the storage server 2000, and certain test pattern data may be selected from among the stored test pattern data and transmitted to the test system 3000 over the data communication link 4000. Although, in the example illustrated in FIG. 1, the semiconductor test system has been configured to include the storage server 2000, according to example embodiments of the inventive concepts the pattern capture system 1000 and the test system 3000 may be directly interconnected through the data communication link 4000 without the storage server 2000. Thus, test pattern data from the pattern capture system 1000 may be transmitted to the test system 3000 in real time to be used in the DUT test. According to example embodiments of the inventive concepts, the semiconductor test system may capture a pattern of an interface signal applied to the semiconductor device in the user device which is variable in frequency, and apply the captured pattern to the DUT to test pass or fail of the semiconductor device based on frequency variation. Now, configurations of the pattern capture system 1000 and test system 3000 to test pass or fail of the semiconductor device based on frequency variation will be explained in detail. FIG. 2 is a block diagram showing a configuration of the pattern capture system 1000 in detail. Referring to FIG. 2, the pattern capture system 1000 according to example embodiments of the inventive concepts may include a user device 100, an event generator 200 and a pattern synthesis apparatus 300. The user device 100 may be mounted with a reference semiconductor device of the same type as or compatible with a DUT to be tested. Here, the semiconductor device may be a memory device including for example a dynamic random access memory (DRAM), and the user device 100 may be a mobile phone, a gaming machine, a computer or the like having such a semiconductor device. The user device 100 may transmit an interface signal of the semiconductor device to the pattern synthesis apparatus 300 through a probe 110. For example, all signals to drive the semiconductor device may be transmitted to the pattern synthesis apparatus 300, and finally used in generating test pattern data. The probe 110 may transfer the interface signal to the pattern synthesis apparatus 300 in such a manner as to minimize distortion of the interface signal. To this end, the probe 110 may include an interposer, a cable and a fixing member. The probe 110 and the semiconductor device in the user device 100 may be interconnected as shown in FIG. 3. FIG. 3 is a diagram illustrating a connection structure between a probe and a semiconductor device in a user device. Referring to FIG. 3, an interposer 111 may be fixed between a PCB 10 and a semiconductor device (IC) 20 through a fixing member 112. The interposer 111 may have a signal path formed therein, which includes main paths 111a serving as signal paths between the PCB 10 and the reference semiconductor device 20, and additional paths 111b connected respectively to the main paths 111a to transfer signals to cables 114. In addition, resistors 113 may be connected respectively between the additional paths 111b and the cables 114. Here, each resistor 113 may have a resistance that is, for example, ten or more times an impedance of each main path 111a. As signals are transmitted to the cables 114 after passing through the resistors 113 each having a relatively high resistance, signal distortion along the main paths 111a may be reduced or minimized, and a signal, only an amplitude of which is attenuated, may be probed among the signals on the main paths 111a. The event generator 200 may generate an electrical pulse signal at an occurrence time of a specific operation (event) of the user device 100, and transmit the signal to the pattern synthesis apparatus 300. Accordingly, when the specific operation is performed, test pattern data for the signal of the user device 100 may be generated or the occurrence time of the specific operation may be recorded in the generated test pattern data. The event generator 200 may include a signal generator to generate a signal when the specific operation is performed, and a cable to transfer the generated signal to the pattern synthesis apparatus 300. The signal generator may be composed of a timer or a switch, and may generate a pulse signal when a specific timer condition is satisfied or when the switch is activated. Although the semiconductor test system according to example embodiments of the inventive concepts has the event generator 200 as a separate component, it may be possible to incorporate the event generator 200 into the user device 100 to generate a pulse signal for every occurrence of a specific operation of the user device 100. For example, a processor of the user device 100 may generate a signal, and the generated signal may be transmitted to the pattern synthesis apparatus 300 through an input/output (IO) line connectible to an external device. In this case, the event generator 200 may be realized through firmware to generate an electric signal via the input/output (IO) line at every occurrence time of a specific operation. The pattern synthesis apparatus 300 may synthesize mounting-type test pattern data based on signals transmitted respectively from the probe 110 and the event generator 200. Specifically, the pattern synthesis apparatus 300 according to example embodiments of the inventive concepts may measure timing of an interface signal probed by the probe 110, and capture a logic value of the interface signal synchronized with the measured timing. Thus, the pattern synthesis apparatus according to example embodiments of the inventive concepts may synthesize test pattern data to test pass or fail of a semiconductor device based on frequency variation. A configuration of the pattern synthesis apparatus 300 which may capture a signal waveform from a DRAM as a semiconductor device to synthesize test patterns will be described in detail below. However, it will be readily understood by those skilled in the art that the present embodiment is also applicable to the case of synthesizing test patterns of any semiconductor device other than the DRAM, the operating frequency of which may vary depending on conditions. In the example illustrated in FIG. 2, the pattern synthesis apparatus 300 according to the present embodiment includes a preprocessor 310, a time interval measurer 320, a logic value capturer 330, a control signal generator 340, an event checker 350 and a communication interface 360. The interface signal of the DRAM transferred through the probe 110 may be transmitted to the time interval measurer 320 and the logic value capturer 330 through the preprocessor 310, and test pattern data generated by the time interval measurer 320 and logic value capturer 330 may be externally transmitted through the communication interface 360. For example, the preprocessor 310 may amplify a signal with an attenuated amplitude, and compare the amplified signal with a predetermined value to convert the signal into a digital signal. In addition, the preprocessor 310 may send the converted digital signal to the time interval measurer 320 and logic value capturer 330. The time interval measurer 320 may receive a timing signal from the preprocessor 310, and store timing data including a time interval and a sequence number of the timing signal in a memory of the pattern synthesis apparatus 300. Although the time interval measurer 320 according to example embodiments of the inventive concepts may measure only the time interval of a clock signal which is a reference signal for a DRAM operation, it may also measure a time interval of any signal other than the clock signal. The term “time interval” may refer to an interval between adjacent rising and falling edges of a clock signal, and the measured time interval may indicate whether an operating frequency has changed and the changed operating frequency if the operating frequency has changed, and a logic value of data may be captured based on the measured interval. Particularly, the time interval measurer 320 according to example embodiments of the inventive concepts may store timing data in the memory corresponding to occurrence of a timing event instead of storing all measured timing data. For example, the time interval measurer 320 may compress and store only timing data corresponding to occurrence of a timing event instead of storing all measured timing data. For example, the time interval measurer 320 may determine whether a timing event has occurred based on a measured interval, and store timing data corresponding to the occurrence of the timing event as representative timing data of a duration ranging from an occurrence time of the recent timing event to the present time. For example, the time interval measurer 320 may continuously measure an interval between rising and falling edges of a clock signal so that an interval and a sequence number corresponding to the occurrence of the timing event may be stored as representative timing data so as to reduce the quantity of data stored. Here, the timing event may refer to an event in which a frequency has changed, or a duty ratio which is a ratio between a high level duration and a low level duration in one period has changed. Now, a configuration of the time interval measurer 320 and an example of a process of measuring an interval of a clock signal and calculating a sequence number thereof will be explained in detail with reference to FIG. 4 and FIG. 5. FIG. 4 is a block diagram showing a configuration of a time interval measurer shown in FIG. 2 in detail. In the example illustrated in FIG. 4, the time interval measurer 320 includes a buffer 321 which may temporarily store a clock signal sent from the preprocessor 310, an edge detector 322 which may detect rising and falling edges of the clock signal stored in the buffer 321, a timing data generator 323 which may measure an interval between the detected rising and falling edges, and count a sequence number of the measured interval to generate timing data, a timing event checker 324 which may determine, based on the measured interval, whether a frequency or a duty ratio has changed, and a filter 325 which may filter the timing data when no timing event has occurred. FIG. 5 is a timing diagram illustrating an example of timing data generated by the time interval measurer shown in FIG. 2. For example, as shown in FIG. 5, the timing data generator 323 may measure an interval I(k) (k=0, 1, 2 . . . ) between a rising edge and a falling edge of the clock signal, and count an interval sequence number k whenever the interval is measured. The timing data generator 323 may set a sequence number to ‘0’ for a first rising edge of the clock signal after the pattern synthesis apparatus 300 starts its operation, and may set sequence numbers by incrementing the sequence number by ‘1’ for each edge. Referring to the example illustrated in FIG. 5, the sequence number is counted for every edge starting from ‘0’, and an interval I(0) between an edge whose sequence number is ‘0’ and an edge whose sequence number is ‘1’ is measured. The timing event checker 324 may calculate a present period based on the measured interval, and determine whether a frequency has changed based on a difference between the calculated present period and a reference period. Here, the reference period may be calculated through an interval of the most recently stored timing data. For example, if the difference between the calculated present period and the reference period exceeds a predetermined or reference threshold value, it may be determined that a timing event has occurred, for example by the timing event checker 324, and present timing data (I(k) and k) may be stored in the memory. Referring to FIG. 5, the timing event checker 324 may determine that a difference between a present period calculated through a k1th interval I(k1) and the reference period calculated through the interval I(0), which is the interval of the most recently stored timing data, has changed, and perform a control operation to store the value of the interval I(k1) and an interval sequence number k1 for the interval value I in the memory. In addition, the timing event checker 324 may measure a present duty ratio based on the ratio between an interval value of a high level and an interval value of a low level within one period, and compare the measured present duty ratio and a reference duty ratio to determine whether there is a duty ratio change. Here, the reference duty ratio may be calculated through an interval of the most recently stored timing data. For example, the timing event checker 324 may determine whether a difference between the present duty ratio and the reference duty ratio exceeds a predetermined or reference threshold value, and store present timing data (1(k) and k) in the memory if the difference exceeds the threshold value. For example, the timing event checker 324 may calculate the present period and the present duty ratio based on the measured interval, and compare the calculated value and the reference value to determine whether a timing event has occurred. In the example described above with reference to FIG. 5, only timing data corresponding to occurrence of a timing event is stored in the memory, and the timing data is filtered when no timing event has occurred. However, according to example embodiments of the inventive concepts, timing data corresponding to non-occurrence of a timing event may be used in recalculating the reference value. For example, the timing event checker 324 may recalculate the reference value, including for example, the reference period and the reference duty ratio, continuously and compare the reference value with the present period and the present duty ratio to determine whether a timing event has occurred. Upon determining that no timing event has occurred, the timing event checker 324 recalculates the reference period and the reference duty ratio using a plurality of intervals measured from the most recent time where timing data is stored to the present time. The process of recalculating the reference period and the reference duty ratio is repeated until a timing event occurs. For example, the timing event checker 324 calculates an average of the plurality of intervals measured from the most recent time where timing data is stored to the present time, and recalculates the reference period and the reference duty ratio through the calculated average interval. In addition, the timing event checker 324 may store the thus-calculated average interval as timing data. Referring to FIG. 5, the timing event checker 324 may calculate an average interval value by reflecting all of the interval values measured from the interval I(0) to the interval I(k1-1) before the interval I(k1) where a timing event has occurred, and calculate a reference value based on the average value. Thus, the timing event checker 324 may store both an average value (I′(0)) of the values of intervals I(0) to I(k1-1) and a starting interval sequence number 0, as timing data. For example, the timing event checker 324 may calculate an average interval value until a subsequent timing event has occurred, continuously, and finally store the calculated average value as timing data, instead of storing only the timing data corresponding to an occurrence time of a timing event. Thus, it may be possible to prevent erroneous interval information from being stored as timing data influenced by noise. The logic value capturer 330 may receive an interface signal from the preprocessor 310 to capture the interface signal, and stores logic value data generated by capturing the interface signal in the memory. Here, the interface signal may include, for example, a timing signal, a data signal, a command signal, an address signal, etc. In addition, the timing signal may be a primary timing-related interface signal including for
{'app_number': None, 'application_number': '<application-reference appl-type="utility">\n<document-id>\n<country>US</country>\n<doc-number>13484481</doc-number>\n<date>20120531</date>\n</document-id>\n</application-reference>', 'doc_number': None, 'publication_number': '<publication-reference>\n<document-id>\n<country>US</country>\n<doc-number>20120326738</doc-number>\n<kind>A1</kind>\n<date>20121227</date>\n</document-id>\n</publication-reference>', 'source_file': './application/2012/ipa121227.xml', 'source_data': 'USPTO-Application'}