Title of Invention: Semiconductor device and manufacturing method thereof Abstract: A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext). Detailed Description: CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2003-317259, filed Sep. 9, 2003, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an MIS type field effect transistor and a manufacturing method thereof. 2. Description of the Related Art In recent years, as demands for a realization of a semiconductor integrated circuit with low power consumption and high operating speed or the like become rigid, a realization of a low power supply voltage and a fine element is desired. For this reason, in regard to a transistor element, attention is paid to a three-dimensional element in place of a conventional planar type element. As the three-dimensional element, there has been known, e.g., an MOS transistor utilizing a fin-shaped semiconductor layer, i.e., a FinFET. The FinFET is superior in suppression of a short channel effect, a low subthreshold slope, high mobility and others as compared with other types of transistors. FIGS. 1 and 2 show a structural example of the FinFET. An insulating layer 2 is formed on a silicon substrate 1, and a fin-shaped silicon layer 3 is formed on the insulating layer 2. A so-called SOI substrate is constituted by the silicon substrate 1, the insulating layer 2 and the silicon layer 3. A cap insulating layer 4 which is used as a mask when processing the silicon layer 3 is formed on the silicon layer 3. A gate electrode 6 is formed on each of two side surfaces of the silicon layer 3 in a direction y through a gate insulating layer 5. In this example, the gate electrode 6 on one side of the silicon layer 3 is separated from that on the other side of the same, but the both gate electrodes 6 may be electrically connected. An area in the silicon layer 3 sandwiched by the gate electrodes 6 is a channel area 7. Further, in the silicon layer 3, source/drain areas 8 are formed on both sides of the channel area 7. A direction of a current flowing through the channel area 7 is a direction parallel to the surface of the silicon substrate 1, i.e., a direction x. In case of operating such a FinFET as a fully depleted type element, in order to suppress a short channel effect, a fin in the channel area 7, i.e., a width Wch of the silicon layer 3 in the direction y (width of the channel area) must be set smaller than a gate length Lg. In each generation of LSI, however, since a dimension which can be processed into a minimum level by the lithography technology is usually coordinated with the gate length, it is very hard to form the channel area 7 having a width narrower than the gate length. Furthermore, in the FinFET shown in FIGS. 1 and 2, the width Wch of the channel area 7 is equal to the width of the fin, i.e., the silicon layer 3 in the source/drain area 8 in the direction y. In this case, when the width Wch of the channel area 7 is reduced in order to suppress the short channel effect, the width of the fin in the source/drain area 8 in the direction y is also decreased. As a result, a parasitic resistance of the source/drain area 8 is increased, thereby lowering a drive current. Moreover, an effective gate width (effective channel width) of the FinFET is twofold of a height h of the fin, i.e., the silicon layer 3. In order to increase the effective gate width, connecting a plurality of fins in parallel can suffice. On the other hand, in case of the FinFET, impurities must also be implanted into the side surfaces of the silicon layer 3 in order to form a source/drain area. Therefore, the source/drain area is usually formed by a tilted ion implantation method. When a plurality of fins are connected to each other in parallel, however, a size of a part connecting a plurality of the fins is large. As a result, in the tilted ion implantation method, impurities based on the ion implantation do not spread in the entire source/drain formation planned area in each fin, and there is a problem that an area which is of an electroconductive type opposite to that of the source/drain area partially remains in the source/drain formation planned area. In case of a planar (flat) transistor, as shown in FIG. 3, parasitic resistances consist of a silicide interface resistance Rc, a silicide sheet resistance Rs, a diffusion layer sheet resistance Rd immediately below the silicide and others, and these resistance components must be reduced in order to realize a high-speed operation. As shown in FIG. 4, however, in an SOI structure, when a major part of the source/drain area is silicided, the diffusion layer sheet resistance Rd immediately below silicide is increased, and the parasitic resistance becomes large. Additionally, when all of the source/drain area is silicided, the parasitic resistance becomes extremely large. Thus, it is important to sufficiently assure a depth Xd of the diffusion layer immediately below silicide so as to prevent the diffusion layer sheet resistance Rd immediately below silicide from being increased. In recent years, in order to realize high performances and high density of an element, fruition of fine transistors has been advanced, and a control over a current between the source and the drain by a gate electrode is becoming difficult (short channel effect). Thus, nowadays, for example, an MOS transistor utilizing a fin-shaped semiconductor layer, i.e., a FinFET has been studied. The FinFET is superior in suppression of the short channel effect, a low subthreshold slope, high mobility and others as compared with other types of transistors. FIG. 5 shows a structural example of the FinFET. An insulating layer 2 is formed on a silicon substrate 1, and a fin-shaped silicon layer 3 is formed on the insulating layer 2. A so-called SOI substrate is constituted by the silicon substrate 1, the insulating layer 2 and the silicon layer 3. A cap insulating layer 4 used as a mask when processing the silicon layer 3 is formed on the silicon layer 3. A gate electrode 6 is formed on two side surface of the silicon layer 3 in a direction y through gate insulating layers 5. In this example, the gate electrode on one side of the silicon layer 3 is electrically connected to the gate electrode 3 on the other side of the same so as to cut across the silicon layer 3, but the both gate electrodes 6 may be electrically separated from each other. Sidewall insulating layers (sidewalls) 9 are formed on side surface of the gate electrode 6 in a direction x. A cap insulating layer 10 used as a mask when processing the gate electrode 6 is formed on the gate electrode 6. Here, as shown in FIG. 6, an area in the silicon layer 3 sandwiched by the gate electrodes 6 is a channel area 7. Further, in the silicon layer 3, source/drain areas 8 and source/drain extension areas 8a are formed on both sides of the channel area 7. A direction of a current flowing through the channel area 7 is a direction parallel to a surface of the silicon substrate 1, i.e., the direction x. Usually, in the FinFET shown in FIG. 5, there is adopted a silicide process which forms a silicide layer on the source/drain areas formed in the silicon layer 3. FIG. 6 shows the FinFET which has been subjected to the silicide process. Silicide layers 11 are formed in the silicon layer 3 (source/drain areas 8). In this example, there occur a problem that a major part of the source/drain areas 8 excluding areas immediately below the sidewall insulating layers 9 is silicided and a parasitic resistance is increased. That is, the diffusion layer sheet resistance Rd immediately below silicide is increased, and the parasitic resistance becomes considerably high. Such a problem is also true in, e.g., transistors adopting an SOI structure and a double gate structure such as shown in FIG. 7. Therefore, in the FinFET formed on the SOI substrate, it is necessary to propose a structure by which all of the channel portion is not silicided, reduce the diffusion layer sheet resistance Rd immediately below silicide and decrease the parasitic resistance. As described above, in the prior art, it is hard to make a width of the fin (width of the channel area) in the channel area smaller than the gate length. Assuming the width of the channel area is smaller than the gate length, since this width is equal to the width of the fin in the source/drain area, there occur problems such as an increase in the parasitic resistance, a reduction in the drive current and others. In order to control an effective channel width, when a structure that a plurality of fins are connected to each other in parallel is adopted, an area which is of an electroconductive type different from an electroconductive type of the source/drain area partially remains in the source/drain area. Furthermore, when a silicide layer is provided on the source/drain area, a major part of the source/drain area is silicided since a width of the fin is small, and the diffusion layer sheet resistance immediately below silicide thereby becomes large. Therefore, the following problems must be examined. [1] Proposing a structure and a manufacturing method of a three-dimensional element such as a FinFET that {circle over (1)} a width of a channel area is smaller than a gate length, {circle over (2)} a width of a fin in a source/drain extension area is equal to or larger than the width of the channel area, and {circle over (3)} the width of the fin in the source/drain area is larger than the width of the channel area or the width of the fin in the source/drain extension area. [2] Proposing a structure and a manufacturing method of a three-dimensional element such as a FinFET in which an effective channel width is controlled by the number of fins connected to each other in parallel rather than heights of the fins, and proposing a structure and a manufacturing method by which an area which is of an electroconductive type different from an electroconductive type of the source/drain area is prevented from partially remaining in the source/drain area. [3] In regard to a silicide layer provided on the source/drain area in the fin, preventing a major part of the source/drain area from being silicided, reducing the diffusion layer sheet resistance immediately below silicide, thereby suppressing an increase in the parasitic resistance. BRIEF SUMMARY OF THE INVENTION According to an example of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a fin-formed semiconductor layer which is formed on the semiconductor substrate, is long in a first direction and is short in a second direction crossing the first direction; a gate insulating layer formed on side surfaces of the semiconductor layer in the second direction; a gate electrode arranged so as to be adjacent to the gate insulating layer; a channel area formed at a position adjacent to the gate insulating layer in the semiconductor layer; a source/drain extension area formed at a position adjacent to the channel area in the semiconductor layer in the first direction; and a source/drain area formed at a position adjacent to the source/drain extension area in the semiconductor layer in the first direction, wherein a width of the semiconductor layer in the second direction in the channel area is smaller than a width of the semiconductor layer in the second direction in the source/drain area. According to an example of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a plurality of fin-formed first semiconductor layers which are formed on the semiconductor substrate, long in a first direction, short in a second direction crossing the first direction and aligned in the second direction; a second semiconductor layer which connects a plurality of the first semiconductor layers at end portions of a plurality of the first semiconductor layers in the first direction; a gate insulating layer formed on side surfaces of each of a plurality of the first semiconductor layers in the second direction; a gate electrode arranged so as to be adjacent to the gate insulating layer; a channel area formed at a position adjacent to the gate insulating layer in a plurality of the first semiconductor layers; a source/drain extension area formed at a position adjacent to the channel area in the first direction in a plurality of the first semiconductor layers; and a source/drain area formed at a position adjacent to the source/drain extension area in the first direction in the second semiconductor layer. According to an example of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a fin-formed semiconductor layer which is formed on the semiconductor substrate, is long in a first direction and is short in a second direction crossing the first direction; a gate insulating layer formed on side surfaces of the semiconductor layer in the second direction; a gate electrode arranged so as to be adjacent to the gate insulating layer; a channel area formed at a position adjacent to the gate insulating layer in the semiconductor layer; a source/drain extension area formed at a position adjacent to the channel area in the first direction in the semiconductor layer; a source/drain area formed at a position adjacent to the source/drain extension area in the first direction in the semiconductor layer; and a silicide layer which is formed to a surface portion of the semiconductor layer in the source/drain area but not formed in the entire inner portion of the same. According to an example of the present invention, there is provided a manufacturing method of a semiconductor device, comprising: a step of forming on a semiconductor substrate a fin-formed semiconductor layer which is long in a first direction and short in a second direction crossing the first direction; a step of forming a dummy gate insulating layer on side surfaces of the semiconductor layer in the second direction; a step of forming a dummy gate electrode adjacent to the dummy gate insulating layer; a step of forming a source/drain extension area and a source/drain area in the semiconductor layer; a step of forming an insulating layer covering the semiconductor layer; a step of polishing or etching the insulating layer and thereby exposing surfaces of the dummy gate insulating layer and the dummy gate electrode; a step of removing the dummy gate insulating layer and the dummy gate electrode; a step of oxidizing the semiconductor layer at a part where the dummy gate insulating layer had been formed and forming an oxide layer; a step of removing the oxide layer; a step of forming a gate insulating layer at a part where the dummy gate insulating layer had been formed; and a step of forming a gate electrode adjacent to the gate insulating layer. According to an example of the present invention, there is provided a manufacturing method of a semiconductor device, comprising: a step forming on a semiconductor substrate a plurality of fin-formed first semiconductor layers which are long in a first direction and short in a second direction crossing the first direction, and a second semiconductor layer which connects end portions of a plurality of the first semiconductor layers in the first direction; a step of forming a dummy gate insulating layer on side surfaces of a plurality of the first semiconductor layers in the second direction; a step of forming a dummy gate electrode adjacent to the dummy gate insulating layer; a step of forming a source/drain extension area in a plurality of the first semiconductor layers; a step of forming a source/drain area in the second semiconductor layer; a step of forming an insulating layer covering the first and second semiconductor layers; a step of polishing or etching the insulating layer and thereby exposing surfaces of the dummy gate insulating layer and the dummy gate electrode; a step of removing the dummy gate insulating layer and the dummy gate electrode; a step of oxidizing the first semiconductor layers at a part where the dummy gate insulating layer had been formed and forming an oxide layer there; a step of removing the oxide layer; a step of forming a gate insulating layer at a part where the dummy gate insulating layer had been formed; and a step of forming a gate electrode adjacent to the gate insulating layer. According to an example of the present invention, there is provided a manufacturing method of a semiconductor device, comprising: a step of forming a cap insulating layer on a semiconductor layer on a first insulating layer; a step of etching the semiconductor layer by using the cap insulating layer as a mask, and forming the semiconductor layer into a fin shape which is long in a first direction and short in a second direction crossing the first direction; a step of forming a second insulating layer covering the semiconductor layer; a step of polishing or etching the second insulating layer and thereby exposing a surface of the cap insulating layer; a step of etching the cap insulating layer by isotropic etching and thereby reducing a size of the cap insulating layer; a step of forming a first resist having a slit whose width is smaller than a width of the semiconductor layer in the first direction; a step of etching the semiconductor layer by using the cap insulating layer and the first resist as masks, and making a width of the semiconductor layer at a central portion in the second direction smaller than a width in the second direction of the semiconductor layer at an end portion in the first direction; a step of forming a source/drain extension area at the central portion of the semiconductor layer; and a step of forming a source/drain area at the end portion of the semiconductor layer in the first direction. According to an example of the present invention, there is provided a manufacturing method of a semiconductor device, comprising: a step of forming on a semiconductor substrate a fin-shaped semiconductor layer which is long in a first direction and short in a second direction crossing the first direction; a step of forming a gate insulating layer on side surfaces of the semiconductor layer in the second direction; a step of forming a gate electrode adjacent to the gate insulating layer; a step of forming a source/drain extension area in the semiconductor layer by tilted ion implantation; a step of forming a sidewall insulating layer on sidewalls of the gate electrode; a step of forming a source/drain area by a combination of tilted ion implantation and vertical ion implantation or by vertical ion implantation; and a step of forming a silicide layer on the gate electrode and a surface of the source/drain area, wherein conditions of silicidation are set so as not to form the silicide layer in the entire inner portion of the semiconductor layer in the source/drain area. According to an example of the present invention, there is provided a manufacturing method of a semiconductor device, comprising: a step of forming on a semiconductor substrate a fin-shaped first semiconductor layer which is long in a first direction and short in a second direction crossing the first direction, a silicidation stopper on the first semiconductor layer, and a second semiconductor layer on the silicidation stopper; a step of forming a gate insulating layer on side surface of the first semiconductor layer in the second direction; a step of forming a gate electrode adjacent to the gate insulating layer; a step of forming a source/drain extension area in the first semiconductor layer; a step of forming a sidewall insulating layer on sidewalls of the gate electrode; a step of growing an epitaxial layer on surfaces of the first and second semiconductor layers by a selected growth, and coupling the epitaxial layer from the first layer with the epitaxial layer from the second semiconductor layer; a step of forming a source/drain area in the first semiconductor layer; and a step of forming a silicide layer on the gate electrode, the second semiconductor layer and the epitaxial layer, wherein the silicidation stopper functions as a stopper in silicidation so as to prevent silicidation from advancing from a top portion of the first semiconductor layer in silicidation. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING FIG. 1 is a view showing an example of a conventional FinFET; FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1; FIG. 3 is a view showing an example of a conventional transistor; FIG. 4 is a view showing the example of the conventional transistor; FIG. 5 is a view showing an example of a conventional FinFET; FIG. 6 is a view showing the example of the conventional FinFET; FIG. 7 is a view showing an example of a conventional transistor; FIG. 8 is a view showing an outline of an example of the present invention; FIG. 9 is a view showing an outline of an example of the present invention; FIG. 10 is a view showing an outline of an example of the present invention; FIG. 11 is a view showing an outline of an example of the present invention; FIG. 12 is a view showing an outline of an example of the present invention; FIG. 13 is a view showing an outline of an example of the present invention; FIG. 14 is a view showing an outline of an example of the present invention; FIG. 15 is a view showing a FinFET according to a first embodiment of the present invention; FIG. 16 is a cross-sectional view taken along the line XVI-XVI in FIG. 15; FIG. 17 is a view showing a first example of a manufacturing method according to the first embodiment; FIG. 18 is a cross-sectional view taken along the line XVIII-XVIII in FIG. 17; FIG. 19 is a view showing the first example of the manufacturing method of the first embodiment; FIG. 20 is a cross-sectional view taken along the line XX-XX in FIG. 19; FIG. 21 is a view showing the first example of the manufacturing method according to the first embodiment; FIG. 22 is a cross-sectional view taken along the line XXII-XXII in FIG. 21; FIG. 23 is a view showing the first example of the manufacturing method according to the first embodiment; FIG. 24 is a cross-sectional view taken along the line XXIV-XXIV in FIG. 23; FIG. 25 is a view showing the first example of the manufacturing method according to the first embodiment; FIG. 26 is a view showing the first example of the manufacturing method according to the first embodiment; FIG. 27 is a view showing the first example of the manufacturing method according to the first embodiment; FIG. 28 is a cross-sectional view taken along the line XXVIII-XXVIII in FIG. 27; FIG. 29 is a view showing the first example of the manufacturing method according to the first embodiment; FIG. 30 is a cross-sectional view taken along the line XXX-XXX in FIG. 29; FIG. 31 is a view showing a second example of the manufacturing method according to the first embodiment; FIG. 32 is a cross-sectional view taken along the line XXXII-XXXII in FIG. 31; FIG. 33 is a view showing the second example of the manufacturing method according to the first embodiment; FIG. 34 is a cross-sectional view taken along the line XXXIV-XXXIV in FIG. 33; FIG. 35 is a view showing the second example of the manufacturing method according to the first embodiment; FIG. 36 is a cross-sectional view taken along the line XXXVI-XXXVI in FIG. 35; FIG. 37 is a view showing the second example of the manufacturing method according to the first embodiment; FIG. 38 is a cross-sectional view taken along the line XXXVIII-XXXVIII in FIG. 37; FIG. 39 is a view showing the second example of the manufacturing method according to the first embodiment; FIG. 40 is a cross-sectional view taken along the line XL-XL in FIG. 39; FIG. 41 is a view showing the second example of the manufacturing method according to the first embodiment; FIG. 42 is a cross-sectional view taken along the line XLII-XLII in FIG. 41; FIG. 43 is a view showing a FinFET according to a second embodiment of the present invention; FIG. 44 is a cross-sectional view taken along the line XLIV-XLIV in FIG. 43; FIG. 45 is a view showing an example of the manufacturing method according to the second embodiment; FIG. 46 is a view showing the example of the manufacturing method according to the second embodiment; FIG. 47 is a view showing the example of the manufacturing method according to the second embodiment; FIG. 48 is a view showing the example of the manufacturing method according to the second embodiment; FIG. 49 is a view showing the example of the manufacturing method according to the second embodiment; FIG. 50 is a view showing a structural example 1 of a FinFET according to a third embodiment of the present invention; FIG. 51 is a cross-sectional view taken along the line LI-LI in FIG. 50; FIG. 52 is a view showing a structural example 2 of the FinFET according to the third embodiment of the present invention; FIG. 53 is a cross-sectional view taken along the line LIII-LIII in FIG. 52; FIG. 54 is a view showing a structural example 3 of the FinFET according to the third embodiment of the present invention; FIG. 55 is a cross-sectional view taken along the line LV-LV in FIG. 54; FIG. 56 is a view showing a first example of the manufacturing method according to the third embodiment; FIG. 57 is a view showing the first example of the manufacturing method according to the third embodiment; FIG. 58 is a cross-sectional view taken along the line LVIII-LVIII in FIG. 57; FIG. 59 is a view showing the first example of the manufacturing method according to the third embodiment; FIG. 60 is a cross-sectional view taken along the line LX-LX in FIG. 59; FIG. 61 is a view showing the first example of the manufacturing method according to the third embodiment; FIG. 62 is a cross-sectional view taken along the line LXII-LXII in FIG. 61; FIG. 63 is a view showing the first example of the manufacturing method according to the third embodiment; FIG. 64 is a cross-sectional view taken along the line LVIV-LVIV in FIG. 63; FIG. 65 is a view showing a second example of the manufacturing method according to the third embodiment; FIG. 66 is a cross-sectional view taken along the line LXVI-LXVI in FIG. 65; FIG. 67 is a view showing the second example of the manufacturing method according to the third embodiment; FIG. 68 is a cross-sectional view taken along the line LXVIII-LXVIII in FIG. 67; FIG. 69 is a view showing the second example of the manufacturing method according to the third embodiment; FIG. 70 is a cross-sectional view taken along the line LXX-LXX in FIG. 69; FIG. 71 is a view showing the second example of the manufacturing method according to the third embodiment; FIG. 72 is a cross-sectional view taken along the line LXXII-LXXII in FIG. 71; FIG. 73 is a view showing a third example of the manufacturing method according to the third embodiment; FIG. 74 is a view showing the third example of the manufacturing method according to the third embodiment; FIG. 75 is a view showing the third example of the manufacturing method according to the third embodiment; FIG. 76 is a view showing the third example of the manufacturing method according to the third embodiment; FIG. 77 is a view showing the third example of the manufacturing method according to the third embodiment; FIG. 78 is a view showing the third example of the manufacturing method according to the third embodiment; and FIG. 79 is a view showing the third example of the manufacturing method according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION A best mode for embodying the present invention will now be described in detail hereinafter with reference to the accompanying drawings. 1. Outline Examples of the present invention are roughly constituted by the following three. [1] First, in regard to a three-dimensional transistor element such as a FinFET, the following structure is adopted in order to realize suppression of a short channel effect, an increase in drive current due to a reduction in parasitic resistance, and others. That is, as shown in FIG. 8, a width of a fin in a channel area in a direction y, i.e., a width Wch of the channel area is set smaller than a gate length Lg, thereby suppressing the short channel effect. Further, a width Wsd of the fin in a source/drain area is set larger than a width Wch of the channel area or a width Wext of the fin in a source/drain extension area, and suppression of the short channel effect is thereby realized simultaneously with an increase in drive current due to a reduction in a parasitic resistance (Wch≦Wext<Wsd). The width Wext of the fin in the source/drain extension area may be equal to the width Wch of the channel area (Wch=Wext) as shown in FIG. 9, or it may be larger than the same (Wch<Wext) as shown in FIG. 8. Furthermore, when the relationship of Wch<Wext is provided, the width Wsd of the fin in the source/drain area may be equal to the width Wext of the fin in the source/drain extension area (Wext=Wsd) as shown in FIG. 10, or it may be larger than the same (Wext<Wsd) as shown in FIG. 8. [2] Then, as shown in FIG. 11, an effective channel width of the three-dimensional element such as a FinFET is controlled by the number of fins connected to each other in parallel in place of heights of the fins. Usually, a plurality of transistors having different effective channel widths are formed in an LSI. In this case, when the effective channel width of each transistor is adjusted by only the heights of the fins, the fins on a silicon substrate have different heights, and processing of the fins becomes complicated. Moreover, flattening the top face of the fin is difficult, and it is hard to correctly perform subsequent processing steps including photolithography. Thus, as to the three-dimensional element such as a FinFET, there are proposed a structure and a manufacturing method by which its effective channel width is 2×h×n. However, it is assumed that one transistor is constituted by n (n is a natural number) fins connected to each other in parallel and all n fins have the same height h. Additionally, in regard to a three-dimensional transistor element such as a FinFET having a structure that such n fins are connected to each other in parallel, an implantation angle θ of tilted ion implantation for forming the source/drain area is determined as an angle with respect to a plane vertical to a surface of the semiconductor substrate, e.g., a range of 0°<θ≦45° or preferably 10°≦θ≦30°, and an area which is of an electroconductive type different from an electroconductive type of the source/drain area is prevented from partially remaining in the source/drain area. It is hard to form the source/drain area (indicated by hatching) 8 in the entire fin by only the conventional tilted ion implantation as shown in FIG. 12, whereas the source/drain area can be readily formed in the entire fin according to the above-described method. Incidentally, as to ion implantation for forming, e.g., the source/drain area, tilted ion implantation (implantation angle θ falls within a range of 0°<θ≦90°) may be combined with a vertical ion implantation (implantation angle is 0°) as shown in FIGS. 13 and 14 besides the above method. The ion implantation method and the implantation angle for forming the source/drain extension area do not have to be the same as the ion implantation method and the implantation angle for forming the source/drain area. They may be the same or different from each other. The source/drain extension area may be formed by the tilted ion implantation method, and the source/drain area may be formed by the vertical ion implantation method or a combination of the vertical ion implantation method and the tilted ion implantation method. Before ion implantation, for example, germanium (Ge), silicon (Si) or the like is ion-implanted into a source/drain formation planned area, and the source/drain formation planned area is amorphousized. Additionally, after ion implantation for forming the source/drain area, low-temperature annealing at approximately 600° C. is carried out, thereby suppressing impurity diffusion to a minimum level. [3] Then, for example, in regard to a three-dimensional transistor element such as a FinFET having a silicide layer on the source/drain area in the fin, the following structure and manufacturing method are adopted in order to prevent a large part or all of the source/drain area from being silicided. First, conditions of a silicide process are determined so as to leave a silicon layer with a sufficient thickness immediately below a silicide layer. For example, a width of a fin-shaped silicon layer (shorter width), a thickness of a high-melting point metal layer deposited on the silicide layer, a time of silicidation and other are controlled. Second, an elevated source/drain process is adopted, and the silicon layer is selectively grown on the fin-shaped silicon layer. As a result, in the source/drain formation planned area, a width of the silicon layer is substantially increased, and the increased silicon layer functions as consumption silicon in silicidation. Therefore, the silicon layer with a sufficient thickness can be left immediately below the silicide layer. Third, a silicidation stopper (e.g., silicon dioxide) used to avoid excessive silicidation of the silicon layer is provided in order to prevent a large part or all of the source/drain area from being silicided. In silicidation, since this stopper suppresses silicidation of the silicon layer, the silicon layer with a sufficient thickness can be left immediately below the silicon layer. Adopting such a structure or a manufacturing method can suppress an increase in a diffusion layer sheet resistance immediately below silicide, thereby contributing to a reduction in a parasitic resistance. 2. First Embodiment The first embodiment concerns a structure and a manufacturing method of a FinFET which realize suppression of the short channel effect, an increase in a drive current due to a reduction in a parasitic resistance, and others. (1) Structure FIGS. 15 and 16 show a structure of the FinFET according to the first embodiment of the present invention. FIG. 16 is a cross-sectional view taken along the line XVI-XVI in FIG. 15. An insulating layer 2 is formed on a silicon substrate 1, and a fin-shaped silicon layer 3 is formed on the insulating layer 2. A so-called SOI substrate is constituted by the silicon substrate 1, the insulating layer 2 and the silicon layer (fin) 3. A cap insulating layer 4 used as a mask when processing the silicon layer 3 is formed on the insulating layer 2. A gate electrode 6 is formed on each of two side surfaces of the silicon layer 3 in a direction y through a gate insulating layer 5. Although the gate electrode 6 on one side of the silicon layer 3 is separated from that on the other side of the same in this example, they may be electrically connected to each other so as to cut across the silicon layer 3. A sidewall insulating layer (sidewall) 9 is formed on each side surface of the gate electrode 6 in a direction x. An area in the silicon layer 3 sandwiched by the gate electrode 6 is a channel area 7. Further, in the silicon layer 3, source/drain areas 8 and source/drain extension areas 8a are formed on both sides of the channel area 7. A direction of a current flowing through the channel area 7 is a direction parallel to the surface of the silicon substrate 1, i.e., a direction x. Silicide layers 11 are formed on the source/drain areas 8. In this example, the silicide layers 11 are formed on the source/drain areas 8 exposed at an opening portion of an insulating layer 12, i.e., three side surfaces and a top surface of the silicon layer 3. In such a FinFET, a twofold of a height h of the silicon layer 3 corresponds to an effective gate width (effective channel width). Furthermore, a width (shorter one) of the silicon layer 3 is not fixed, but is gradually increased from a central portion to an end portion on three stages. That is, a width Wext of the silicon layer 3 in the source/drain extension area 8a is larger than a width of the silicon layer 3 in the channel area, i.e., a width Wch of the channel area. Moreover, a width Wsd of the silicon layer 3 in the source/drain area 8 is larger than the width Wext of the silicon layer 3 in the source/drain extension area 8a. Therefore, by decreasing the width Wch of the channel area and increasing the width Wsd of the silicon layer 3 in the source/drain area 8, an impurity concentration of the source/drain area 8 can be made sufficiently high and deep, thereby greatly reducing the parasitic resistance. Additionally, when a gate length of the gate electrode 6 is determined as Lg, the width Wch of the channel area can be set smaller than the gate length Lg, thereby effectively suppressing the short channel effect. Although will be described later, the width Wch of the channel area is set smaller than the gate length Lg by a special method in this example. Therefore, even if a dimension which can be processed into a minimum level by the lithography technique is coordinated with the gate length Lg, the silicon layer 3 can be formed with a width equal to or larger than that dimension. (2) Manufacturing Method An example of a manufacturing method for realizing the structure shown in FIGS. 15 and 16 will now be described. {circle over (1)} EXAMPLE 1 First, as shown in FIGS. 17 and 18, for example, a silicon substrate 1 is prepared, and a buried insulating layer (e.g., silicon dioxide) 2 is formed in this silicon substrate 1. In the drawing, although a silicon layer (fin) 3 is formed on the buried insulating layer 2, this silicon layer 3 is originally a part of the silicon substrate 1. A cap insulating layer 4 as a mask material is formed on the silicon substrate 1 (silicon layer 3 in the drawing) by, e.g., LPCVD. Then, the cap insulating layer 4 is patterned by the photolithography and RIE, and the silicon substrate 1 (silicon layer 3 in the drawing) is etched with this cap insulating layer 4 being used as a mask by RIE. As a result, the silicon layer 3 is formed on the buried insulating layer 2. It is to be noted that a substrate having the insulating layer embedded in the silicon substrate from the beginning, e.g., an SIMOX substrate may be used as the SOI substrate. The cap insulating layer 4 is constituted by a stacked structure of, e.g., silicon dioxide and silicon nitride. Further, the silicon layer 3 is formed in such a manner that a width W1 at a part which will be a source/drain area later becomes larger than a width W2 at a part which will be a channel area later in order to reduce a parasitic resistance. In this example, although the fin (silicon layer 3) is formed on the assumption of the SOI substrate, the SOI structure may be alternatively realized by forming the fin on a regular silicon substrate by the photolithography and RIE and then embedding the insulating layer, for example. Subsequently, as shown in FIGS. 19 and 20, a dummy gate insulating layer 5A is formed on each side surface of the silicon layer 3 by, e.g., LPCVD, and then a polysilicon layer (dummy gate electrode 6A in the drawing) is formed on each dummy gate insulating layer 5A. Furthermore, a top face of the polysilicon layer is made substantially the same as a top face of the cap insulating layer 4 (flattening) by using the cap insulating layer 4 as a stopper, for example. Thereafter, the polysilicon layer is processed by the photolithography and RIE, and the dummy gate electrode 6A having such a gate length Lg as shown in the drawing is formed. Then, as shown in FIGS. 21 and 22, impurities are implanted to a surface area of the silicon layer 3 by tilted ion implantation (implantation angle θ is, e.g., 10°≦θ≦30°), thereby forming source/drain extension areas 8a. Thereafter, silicon nitride which completely covers the silicon layer 3 is formed on the buried insulating layer 2 by, e.g., LPCVD. Then, this silicon nitride is etched by RIE, and sidewall insulating layers (sidewalls) 9 are formed. Although the sidewall insulating layer 9 is formed on each of sidewalls of the dummy gate electrode 6A and sidewalls of the silicon layer 3, various conditions may be set in such a manner that it is formed on only the sidewalls of the dummy gate electrode 6A, for example. Thereafter, impurities are again implanted into the silicon layer 3 by tilted ion implantation (low angle) or vertical ion implantation (implantation angle θ is 0°), thereby forming source/drain areas 8. Here, before the ion implantation for forming the source/drain areas 8, e.g., germanium (Ge) or silicon (Si) may be ion-implanted into the source/drain formation planned areas so that the source/drain formation planned areas are amorphousized. In this case, after the ion implantation for forming the source/drain areas 8, performing low-temperature annealing (SPE (Solid Phase Epitaxial regrowth)) at approximately 600° C. can suppress the impurity diffusion to the minimum level. Moreover, after the sidewall insulating layers 9, the epitaxial growth may be carried out in order to form an epitaxial layer on the surface of the silicon layer 3. Then, as shown in FIGS. 23 and 24, insulating layers (e.g., silicon dioxide) 12 which completely cover the silicon layer 3 are formed on the buried insulating layer 2. Additionally, the insulating layers 12 are polished by CMP with the cap insulating layer 4 being used as a stopper, and top faces of the insulating layers 12 are made substantially the same as the top face of the cap insulating layer 4 (flattening), for example. As a result, the top face of each dummy gate electrode 6A (see FIGS. 21 and 22) is exposed. Thereafter, when the dummy gate electrodes 6A and the dummy gate insulating layers 5A are removed, slit-shaped holes are formed at those parts, and the surface of the silicon layer 3 is partially exposed. Then, when the exposed silicon layer 3 is oxidized by thermal oxidation, silicon dioxide layers 13 are formed so as to consume the silicon layer 3. Thereafter, when the silicon dioxide layers 13 are selectively removed, a concave portion is formed in the channel area 7 of the silicon layer 3 as shown in FIG. 25. As a result, a width Wch of the channel area 7 is smaller than a width Wext of the fin in the source/drain extension areas 8a. That is, assuming that Wsd is a width of the fin in the source/drain areas 8, a relationship of Wch<Wext<Wsd can be obtained. As a result, an increase in a drive current due to a reduction in a parasitic resistance in the source/drain areas 8 can be realized. Further, in this example, the width Wch of the channel area 7 can be readily made smaller than the gate length Lg without using the photolithography, which can contribute to suppression of the short channel effect. Thereafter, as shown in FIG. 26, thermal oxidation is again performed, and gate insulating layers (silicon dioxide) 5 are formed. Subsequently, as shown in FIGS. 27 and 28, polysilicon layers are formed so as to completely fill the slit-shaped holes formed to the insulating layers 12 by the LPCVD method. When the polysilicon layers are polished or etched back by CMP, self-aligned gate electrodes 6 are formed in the channel area 7 in the silicon layer 3. Thereafter, impurities are implanted into the gate electrodes 6 by the ion implantation method, and a thermal process for activation of the impurities is conducted. Here, in regard to the gate electrodes 6, a metal such as tungsten (W) or molybdenum (Mo) may be used in place of polysilicon. When the metal is used for the gate electrodes 6 in this manner, since so-called depletion of the gate electrodes is not generated, which can contribute to an improvement in a drive current. Then, as shown in FIGS. 29 and 30, the cap insulating layer 4, the sidewall insulating layers 9 and the insulating layers 12 are partially etched by the photolithography and RIE, an opening portion which reaches each source/drain area 8 is formed on each source/drain area 8. Thereafter, a metal layer consisting of, e.g., nickel (Ni), cobalt (Co) or titanium (Ti) is formed on the entire upper portions of the insulating layers 2 and 12 including this opening portion, and a thermal process is performed. As a result, metal silicide layers 11 are formed on each of top faces and side surfaces of the source/drain areas 8 and the top faces of the gate electrodes 6. Furthermore, thereafter, the metal layer which has not been converted into the metal silicide layer 11 is removed. Such a FinFET as shown in FIGS. 15 and 16 is completed by the above-described steps. Thereafter, although not shown, when an interlayer insulating layer, a contact, a wiring layer and others are formed by a regular wafer process, a semiconductor integrated circuit having an MIS type transistor is completed. {circle over (2)} EXAMPLE 2 First, as shown in FIGS. 31 and 32, for example, a silicon substrate 1 is prepared, and a buried insulating layer (e.g., silicon dioxide) 2 is formed in the silicon substrate 1. Here, the same thing as that in the example 1 can be applied to a silicon layer (fin) 3 on the buried insulating layer 2. That is, although the silicon layer 3 is formed on the buried insulating layer 2 in the drawing, this silicon layer 3 is originally a part of the silicon substrate 1. A cap insulating layer (e.g., silicon nitride) 4 as a mask material is formed on the silicon substrate 1 (silicon layer 3 in the drawing) by LPCVD. Then, the cap insulating layer 4 is patterned by the photolithography and RIE, and the silicon substrate 1 (silicon layer 3 in the drawing) is etched with this cap insulating layer 4 being used as a mask by RIE. As a result, the silicon layer 3 is formed on the buried insulating layer 2. Furthermore, an insulating layer 14 which completely covers the silicon layer 3 is formed on the buried insulating layer 2. Moreover, the insulating layer 14 is polished by CMP with the cap insulating layer 4 being used as a stopper, and a surface of the cap insulating layer 4 is made substantially the same as a surface of the insulating layer 14. It is to be noted that a substrate having an insulating layer embedded in the silicon substrate from the beginning, e.g., an SIMOX substrate may be used as the SOI substrate. In this example, although the fin (silicon layer 3) is formed on the assumption of the SOI substrate, the SOI structure may be alternatively realized by forming the fin on a regular silicon substrate by the photolithography and RIE and then embedding the insulating layer. Subsequently, as shown in FIGS. 33 and 34, the cap insulating layer 4 is etched by isotropic etching. As a result, a top face and side surfaces of the cap insulating layer 4 are isotropically etched, and a size of the cap insulating layer 4 is reduced. Then, as shown in FIGS. 35 and 36,
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